| 1 | Latest set of arm patches. I may end up doing another pullreq at the | 1 | Hi; here's a relatively small target-arm queue, pretty much all |
|---|---|---|---|
| 2 | end of the week, but this is big enough to send out, plus it has | 2 | bug fixes. (There are a few non-arm patches that I've thrown in |
| 3 | several instances of "let me take the first N patches in your series" | 3 | there too for my convenience :-)) |
| 4 | in it, so getting those into master makes patch respins for those | ||
| 5 | submitters easier. | ||
| 6 | 4 | ||
| 7 | thanks | 5 | thanks |
| 8 | -- PMM | 6 | -- PMM |
| 9 | 7 | ||
| 10 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 8 | The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1: |
| 11 | 9 | ||
| 12 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | 10 | Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into staging (2023-05-11 11:44:23 +0100) |
| 13 | 11 | ||
| 14 | are available in the Git repository at: | 12 | are available in the Git repository at: |
| 15 | 13 | ||
| 16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230512 |
| 17 | 15 | ||
| 18 | for you to fetch changes up to bdaffef4bb0729a74c7a325dba5c61d8cd8f464f: | 16 | for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537: |
| 19 | 17 | ||
| 20 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 16:16:42 +0100) | 18 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check (2023-05-12 16:01:25 +0100) |
| 21 | 19 | ||
| 22 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
| 23 | target-arm queue: | 21 | target-arm queue: |
| 24 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 22 | * More refactoring of files into tcg/ |
| 25 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 23 | * Don't allow stage 2 page table walks to downgrade to NS |
| 26 | * target/arm: Define fields of ISAR registers | 24 | * Fix handling of SW and NSW bits for stage 2 walks |
| 27 | * target/arm: Align cortex-r5 id_isar0 | 25 | * MAINTAINERS: Update Akihiko Odaki's email address |
| 28 | * target/arm: Fix cortex-a7 id_isar0 | 26 | * ui: Fix pixel colour channel order for PNG screenshots |
| 29 | * net/cadence_gem: Fix various bugs, add support for new | 27 | * docs: Remove unused weirdly-named cross-reference targets |
| 30 | features that will be used by the Xilinx Versal board | 28 | * hw/mips/malta: Fix minor dead code issue |
| 31 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 29 | * Fixes for the "allow CONFIG_TCG=n" changes |
| 32 | * target/arm: Add the Cortex-A72 | 30 | * tests/qtest: Don't run cdrom boot tests if no accelerator is present |
| 33 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 31 | * target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check |
| 34 | * target/arm: Mask PMOVSR writes based on supported counters | ||
| 35 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 36 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 37 | 32 | ||
| 38 | ---------------------------------------------------------------- | 33 | ---------------------------------------------------------------- |
| 39 | Aaron Lindsay (2): | 34 | Akihiko Odaki (1): |
| 40 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 35 | MAINTAINERS: Update Akihiko Odaki's email address |
| 41 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 42 | 36 | ||
| 43 | Edgar E. Iglesias (10): | 37 | Fabiano Rosas (3): |
| 44 | net: cadence_gem: Disable TSU feature bit | 38 | target/arm: Select SEMIHOSTING when using TCG |
| 45 | net: cadence_gem: Announce availability of priority queues | 39 | target/arm: Select CONFIG_ARM_V7M when TCG is enabled |
| 46 | net: cadence_gem: Use uint32_t for 32bit descriptor words | 40 | tests/qtest: Don't run cdrom boot tests if no accelerator is present |
| 47 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 48 | net: cadence_gem: Add support for extended descriptors | ||
| 49 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 50 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 51 | net: cadence_gem: Announce 64bit addressing support | ||
| 52 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 53 | target/arm: Add the Cortex-A72 | ||
| 54 | 41 | ||
| 55 | Jerome Forissier (1): | 42 | Peter Maydell (6): |
| 56 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 43 | target/arm: Don't allow stage 2 page table walks to downgrade to NS |
| 44 | target/arm: Fix handling of SW and NSW bits for stage 2 walks | ||
| 45 | ui: Fix pixel colour channel order for PNG screenshots | ||
| 46 | docs: Remove unused weirdly-named cross-reference targets | ||
| 47 | hw/mips/malta: Fix minor dead code issue | ||
| 48 | target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check | ||
| 57 | 49 | ||
| 58 | Peter Maydell (2): | 50 | Richard Henderson (2): |
| 59 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 51 | target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ |
| 60 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 52 | target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ |
| 61 | 53 | ||
| 62 | Richard Henderson (4): | 54 | MAINTAINERS | 4 +- |
| 63 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 55 | docs/system/devices/igb.rst | 2 +- |
| 64 | target/arm: Define fields of ISAR registers | 56 | docs/system/devices/ivshmem.rst | 2 - |
| 65 | target/arm: Align cortex-r5 id_isar0 | 57 | docs/system/devices/net.rst | 2 +- |
| 66 | target/arm: Fix cortex-a7 id_isar0 | 58 | docs/system/devices/usb.rst | 2 - |
| 67 | 59 | docs/system/keys.rst | 2 +- | |
| 68 | include/hw/net/cadence_gem.h | 7 +- | 60 | docs/system/linuxboot.rst | 2 +- |
| 69 | target/arm/cpu.h | 95 +++++++++++++- | 61 | docs/system/target-i386.rst | 4 -- |
| 70 | hw/arm/virt.c | 4 + | 62 | target/arm/helper.h | 8 +-- |
| 71 | hw/net/cadence_gem.c | 192 +++++++++++++++++++++-------- | 63 | target/arm/internals.h | 12 +++- |
| 72 | target/arm/arm-powerctl.c | 10 ++ | 64 | target/arm/{ => tcg}/arm_ldst.h | 0 |
| 73 | target/arm/cpu.c | 7 +- | 65 | target/arm/{ => tcg}/helper-a64.h | 0 |
| 74 | target/arm/cpu64.c | 66 +++++++++- | 66 | target/arm/{ => tcg}/helper-mve.h | 0 |
| 75 | target/arm/helper.c | 27 ++-- | 67 | target/arm/{ => tcg}/helper-sme.h | 0 |
| 76 | target/arm/op_helper.c | 6 +- | 68 | target/arm/{ => tcg}/helper-sve.h | 0 |
| 77 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | 69 | target/arm/{ => tcg}/sve_ldst_internal.h | 0 |
| 78 | 10 files changed, 408 insertions(+), 71 deletions(-) | 70 | target/arm/{ => tcg}/translate-a32.h | 0 |
| 79 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | 71 | hw/mips/malta.c | 5 +- |
| 80 | 72 | target/arm/gdbstub64.c | 2 +- | |
| 73 | target/arm/helper.c | 15 ++++- | ||
| 74 | target/arm/ptw.c | 95 +++++++++++++++++++------------- | ||
| 75 | target/arm/tcg/pauth_helper.c | 6 +- | ||
| 76 | tests/qtest/cdrom-test.c | 10 ++++ | ||
| 77 | ui/console.c | 4 +- | ||
| 78 | target/arm/Kconfig | 9 +-- | ||
| 79 | 25 files changed, 109 insertions(+), 77 deletions(-) | ||
| 80 | rename target/arm/{ => tcg}/arm_ldst.h (100%) | ||
| 81 | rename target/arm/{ => tcg}/helper-a64.h (100%) | ||
| 82 | rename target/arm/{ => tcg}/helper-mve.h (100%) | ||
| 83 | rename target/arm/{ => tcg}/helper-sme.h (100%) | ||
| 84 | rename target/arm/{ => tcg}/helper-sve.h (100%) | ||
| 85 | rename target/arm/{ => tcg}/sve_ldst_internal.h (100%) | ||
| 86 | rename target/arm/{ => tcg}/translate-a32.h (100%) | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Jerome Forissier <jerome.forissier@linaro.org> | ||
| 2 | 1 | ||
| 3 | Bindings for /secure-chosen and /secure-chosen/stdout-path have been | ||
| 4 | proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2]. | ||
| 5 | They've now been officially agreed on, so we can implement them | ||
| 6 | in QEMU. | ||
| 7 | |||
| 8 | This patch creates the property when the machine is secure. | ||
| 9 | |||
| 10 | [1] https://patchwork.kernel.org/patch/9602401/ | ||
| 11 | [2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a | ||
| 12 | |||
| 13 | Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> | ||
| 14 | Message-id: 20181005080729.6480-1-jerome.forissier@linaro.org | ||
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | [PMM: commit message tweak] | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | --- | ||
| 19 | hw/arm/virt.c | 4 ++++ | ||
| 20 | 1 file changed, 4 insertions(+) | ||
| 21 | |||
| 22 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/hw/arm/virt.c | ||
| 25 | +++ b/hw/arm/virt.c | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, | ||
| 27 | /* Mark as not usable by the normal world */ | ||
| 28 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | ||
| 29 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | ||
| 30 | + | ||
| 31 | + qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); | ||
| 32 | + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", | ||
| 33 | + nodename); | ||
| 34 | } | ||
| 35 | |||
| 36 | g_free(nodename); | ||
| 37 | -- | ||
| 38 | 2.19.0 | ||
| 39 | |||
| 40 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 3 | These files got missed when populating tcg/. |
| 4 | Because they are included with "", no change to the users required. | ||
| 5 | |||
| 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 5 | Message-id: 20181008212205.17752-3-richard.henderson@linaro.org | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 9 | Message-id: 20230504110412.1892411-2-richard.henderson@linaro.org | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | --- | 11 | --- |
| 9 | target/arm/cpu.h | 88 ++++++++++++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/{ => tcg}/arm_ldst.h | 0 |
| 10 | 1 file changed, 88 insertions(+) | 13 | target/arm/{ => tcg}/sve_ldst_internal.h | 0 |
| 14 | target/arm/{ => tcg}/translate-a32.h | 0 | ||
| 15 | 3 files changed, 0 insertions(+), 0 deletions(-) | ||
| 16 | rename target/arm/{ => tcg}/arm_ldst.h (100%) | ||
| 17 | rename target/arm/{ => tcg}/sve_ldst_internal.h (100%) | ||
| 18 | rename target/arm/{ => tcg}/translate-a32.h (100%) | ||
| 11 | 19 | ||
| 12 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 20 | diff --git a/target/arm/arm_ldst.h b/target/arm/tcg/arm_ldst.h |
| 13 | index XXXXXXX..XXXXXXX 100644 | 21 | similarity index 100% |
| 14 | --- a/target/arm/cpu.h | 22 | rename from target/arm/arm_ldst.h |
| 15 | +++ b/target/arm/cpu.h | 23 | rename to target/arm/tcg/arm_ldst.h |
| 16 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CSSELR, LEVEL, 1, 3) | 24 | diff --git a/target/arm/sve_ldst_internal.h b/target/arm/tcg/sve_ldst_internal.h |
| 17 | */ | 25 | similarity index 100% |
| 18 | FIELD(V7M_CSSELR, INDEX, 0, 4) | 26 | rename from target/arm/sve_ldst_internal.h |
| 19 | 27 | rename to target/arm/tcg/sve_ldst_internal.h | |
| 20 | +/* | 28 | diff --git a/target/arm/translate-a32.h b/target/arm/tcg/translate-a32.h |
| 21 | + * System register ID fields. | 29 | similarity index 100% |
| 22 | + */ | 30 | rename from target/arm/translate-a32.h |
| 23 | +FIELD(ID_ISAR0, SWAP, 0, 4) | 31 | rename to target/arm/tcg/translate-a32.h |
| 24 | +FIELD(ID_ISAR0, BITCOUNT, 4, 4) | ||
| 25 | +FIELD(ID_ISAR0, BITFIELD, 8, 4) | ||
| 26 | +FIELD(ID_ISAR0, CMPBRANCH, 12, 4) | ||
| 27 | +FIELD(ID_ISAR0, COPROC, 16, 4) | ||
| 28 | +FIELD(ID_ISAR0, DEBUG, 20, 4) | ||
| 29 | +FIELD(ID_ISAR0, DIVIDE, 24, 4) | ||
| 30 | + | ||
| 31 | +FIELD(ID_ISAR1, ENDIAN, 0, 4) | ||
| 32 | +FIELD(ID_ISAR1, EXCEPT, 4, 4) | ||
| 33 | +FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) | ||
| 34 | +FIELD(ID_ISAR1, EXTEND, 12, 4) | ||
| 35 | +FIELD(ID_ISAR1, IFTHEN, 16, 4) | ||
| 36 | +FIELD(ID_ISAR1, IMMEDIATE, 20, 4) | ||
| 37 | +FIELD(ID_ISAR1, INTERWORK, 24, 4) | ||
| 38 | +FIELD(ID_ISAR1, JAZELLE, 28, 4) | ||
| 39 | + | ||
| 40 | +FIELD(ID_ISAR2, LOADSTORE, 0, 4) | ||
| 41 | +FIELD(ID_ISAR2, MEMHINT, 4, 4) | ||
| 42 | +FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) | ||
| 43 | +FIELD(ID_ISAR2, MULT, 12, 4) | ||
| 44 | +FIELD(ID_ISAR2, MULTS, 16, 4) | ||
| 45 | +FIELD(ID_ISAR2, MULTU, 20, 4) | ||
| 46 | +FIELD(ID_ISAR2, PSR_AR, 24, 4) | ||
| 47 | +FIELD(ID_ISAR2, REVERSAL, 28, 4) | ||
| 48 | + | ||
| 49 | +FIELD(ID_ISAR3, SATURATE, 0, 4) | ||
| 50 | +FIELD(ID_ISAR3, SIMD, 4, 4) | ||
| 51 | +FIELD(ID_ISAR3, SVC, 8, 4) | ||
| 52 | +FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) | ||
| 53 | +FIELD(ID_ISAR3, TABBRANCH, 16, 4) | ||
| 54 | +FIELD(ID_ISAR3, T32COPY, 20, 4) | ||
| 55 | +FIELD(ID_ISAR3, TRUENOP, 24, 4) | ||
| 56 | +FIELD(ID_ISAR3, T32EE, 28, 4) | ||
| 57 | + | ||
| 58 | +FIELD(ID_ISAR4, UNPRIV, 0, 4) | ||
| 59 | +FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) | ||
| 60 | +FIELD(ID_ISAR4, WRITEBACK, 8, 4) | ||
| 61 | +FIELD(ID_ISAR4, SMC, 12, 4) | ||
| 62 | +FIELD(ID_ISAR4, BARRIER, 16, 4) | ||
| 63 | +FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) | ||
| 64 | +FIELD(ID_ISAR4, PSR_M, 24, 4) | ||
| 65 | +FIELD(ID_ISAR4, SWP_FRAC, 28, 4) | ||
| 66 | + | ||
| 67 | +FIELD(ID_ISAR5, SEVL, 0, 4) | ||
| 68 | +FIELD(ID_ISAR5, AES, 4, 4) | ||
| 69 | +FIELD(ID_ISAR5, SHA1, 8, 4) | ||
| 70 | +FIELD(ID_ISAR5, SHA2, 12, 4) | ||
| 71 | +FIELD(ID_ISAR5, CRC32, 16, 4) | ||
| 72 | +FIELD(ID_ISAR5, RDM, 24, 4) | ||
| 73 | +FIELD(ID_ISAR5, VCMA, 28, 4) | ||
| 74 | + | ||
| 75 | +FIELD(ID_ISAR6, JSCVT, 0, 4) | ||
| 76 | +FIELD(ID_ISAR6, DP, 4, 4) | ||
| 77 | +FIELD(ID_ISAR6, FHM, 8, 4) | ||
| 78 | +FIELD(ID_ISAR6, SB, 12, 4) | ||
| 79 | +FIELD(ID_ISAR6, SPECRES, 16, 4) | ||
| 80 | + | ||
| 81 | +FIELD(ID_AA64ISAR0, AES, 4, 4) | ||
| 82 | +FIELD(ID_AA64ISAR0, SHA1, 8, 4) | ||
| 83 | +FIELD(ID_AA64ISAR0, SHA2, 12, 4) | ||
| 84 | +FIELD(ID_AA64ISAR0, CRC32, 16, 4) | ||
| 85 | +FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) | ||
| 86 | +FIELD(ID_AA64ISAR0, RDM, 28, 4) | ||
| 87 | +FIELD(ID_AA64ISAR0, SHA3, 32, 4) | ||
| 88 | +FIELD(ID_AA64ISAR0, SM3, 36, 4) | ||
| 89 | +FIELD(ID_AA64ISAR0, SM4, 40, 4) | ||
| 90 | +FIELD(ID_AA64ISAR0, DP, 44, 4) | ||
| 91 | +FIELD(ID_AA64ISAR0, FHM, 48, 4) | ||
| 92 | +FIELD(ID_AA64ISAR0, TS, 52, 4) | ||
| 93 | +FIELD(ID_AA64ISAR0, TLB, 56, 4) | ||
| 94 | +FIELD(ID_AA64ISAR0, RNDR, 60, 4) | ||
| 95 | + | ||
| 96 | +FIELD(ID_AA64ISAR1, DPB, 0, 4) | ||
| 97 | +FIELD(ID_AA64ISAR1, APA, 4, 4) | ||
| 98 | +FIELD(ID_AA64ISAR1, API, 8, 4) | ||
| 99 | +FIELD(ID_AA64ISAR1, JSCVT, 12, 4) | ||
| 100 | +FIELD(ID_AA64ISAR1, FCMA, 16, 4) | ||
| 101 | +FIELD(ID_AA64ISAR1, LRCPC, 20, 4) | ||
| 102 | +FIELD(ID_AA64ISAR1, GPA, 24, 4) | ||
| 103 | +FIELD(ID_AA64ISAR1, GPI, 28, 4) | ||
| 104 | +FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) | ||
| 105 | +FIELD(ID_AA64ISAR1, SB, 36, 4) | ||
| 106 | +FIELD(ID_AA64ISAR1, SPECRES, 40, 4) | ||
| 107 | + | ||
| 108 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); | ||
| 109 | |||
| 110 | /* If adding a feature bit which corresponds to a Linux ELF | ||
| 111 | -- | 32 | -- |
| 112 | 2.19.0 | 33 | 2.34.1 |
| 113 | 34 | ||
| 114 | 35 | diff view generated by jsdifflib |
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | At present we assert: | 3 | While we cannot move the main "helper.h" out of target/arm/, |
| 4 | due to usage by generic code, we can move the sub-includes. | ||
| 4 | 5 | ||
| 5 | arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed. | ||
| 6 | |||
| 7 | The comment in arm_el_is_aa64 explains why asking about EL0 without | ||
| 8 | extra information is impossible. Add an extra argument to provide | ||
| 9 | it from the surrounding context. | ||
| 10 | |||
| 11 | Fixes: 0ab5953b00b3 | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
| 13 | Message-id: 20181008212205.17752-2-richard.henderson@linaro.org | 7 | Reviewed-by: Fabiano Rosas <farosas@suse.de> |
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Message-id: 20230504110412.1892411-3-richard.henderson@linaro.org |
| 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | --- | 11 | --- |
| 17 | target/arm/cpu.h | 7 +++++-- | 12 | target/arm/helper.h | 8 ++++---- |
| 18 | target/arm/helper.c | 16 ++++++++++++---- | 13 | target/arm/{ => tcg}/helper-a64.h | 0 |
| 19 | target/arm/op_helper.c | 6 +++++- | 14 | target/arm/{ => tcg}/helper-mve.h | 0 |
| 20 | 3 files changed, 22 insertions(+), 7 deletions(-) | 15 | target/arm/{ => tcg}/helper-sme.h | 0 |
| 16 | target/arm/{ => tcg}/helper-sve.h | 0 | ||
| 17 | 5 files changed, 4 insertions(+), 4 deletions(-) | ||
| 18 | rename target/arm/{ => tcg}/helper-a64.h (100%) | ||
| 19 | rename target/arm/{ => tcg}/helper-mve.h (100%) | ||
| 20 | rename target/arm/{ => tcg}/helper-sme.h (100%) | ||
| 21 | rename target/arm/{ => tcg}/helper-sve.h (100%) | ||
| 21 | 22 | ||
| 22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
| 23 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/target/arm/cpu.h | 25 | --- a/target/arm/helper.h |
| 25 | +++ b/target/arm/cpu.h | 26 | +++ b/target/arm/helper.h |
| 26 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, |
| 27 | int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | 28 | void, ptr, ptr, ptr, ptr, i32) |
| 28 | int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | 29 | |
| 29 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); | 30 | #ifdef TARGET_AARCH64 |
| 30 | -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el); | 31 | -#include "helper-a64.h" |
| 31 | +void aarch64_sve_change_el(CPUARMState *env, int old_el, | 32 | -#include "helper-sve.h" |
| 32 | + int new_el, bool el0_a64); | 33 | -#include "helper-sme.h" |
| 33 | #else | 34 | +#include "tcg/helper-a64.h" |
| 34 | static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } | 35 | +#include "tcg/helper-sve.h" |
| 35 | -static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) { } | 36 | +#include "tcg/helper-sme.h" |
| 36 | +static inline void aarch64_sve_change_el(CPUARMState *env, int o, | ||
| 37 | + int n, bool a) | ||
| 38 | +{ } | ||
| 39 | #endif | 37 | #endif |
| 40 | 38 | ||
| 41 | target_ulong do_arm_semihosting(CPUARMState *env); | 39 | -#include "helper-mve.h" |
| 42 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 40 | +#include "tcg/helper-mve.h" |
| 43 | index XXXXXXX..XXXXXXX 100644 | 41 | diff --git a/target/arm/helper-a64.h b/target/arm/tcg/helper-a64.h |
| 44 | --- a/target/arm/helper.c | 42 | similarity index 100% |
| 45 | +++ b/target/arm/helper.c | 43 | rename from target/arm/helper-a64.h |
| 46 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | 44 | rename to target/arm/tcg/helper-a64.h |
| 47 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | 45 | diff --git a/target/arm/helper-mve.h b/target/arm/tcg/helper-mve.h |
| 48 | unsigned int cur_el = arm_current_el(env); | 46 | similarity index 100% |
| 49 | 47 | rename from target/arm/helper-mve.h | |
| 50 | - aarch64_sve_change_el(env, cur_el, new_el); | 48 | rename to target/arm/tcg/helper-mve.h |
| 51 | + /* | 49 | diff --git a/target/arm/helper-sme.h b/target/arm/tcg/helper-sme.h |
| 52 | + * Note that new_el can never be 0. If cur_el is 0, then | 50 | similarity index 100% |
| 53 | + * el0_a64 is is_a64(), else el0_a64 is ignored. | 51 | rename from target/arm/helper-sme.h |
| 54 | + */ | 52 | rename to target/arm/tcg/helper-sme.h |
| 55 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | 53 | diff --git a/target/arm/helper-sve.h b/target/arm/tcg/helper-sve.h |
| 56 | 54 | similarity index 100% | |
| 57 | if (cur_el < new_el) { | 55 | rename from target/arm/helper-sve.h |
| 58 | /* Entry vector offset depends on whether the implemented EL | 56 | rename to target/arm/tcg/helper-sve.h |
| 59 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | ||
| 60 | /* | ||
| 61 | * Notice a change in SVE vector size when changing EL. | ||
| 62 | */ | ||
| 63 | -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) | ||
| 64 | +void aarch64_sve_change_el(CPUARMState *env, int old_el, | ||
| 65 | + int new_el, bool el0_a64) | ||
| 66 | { | ||
| 67 | int old_len, new_len; | ||
| 68 | + bool old_a64, new_a64; | ||
| 69 | |||
| 70 | /* Nothing to do if no SVE. */ | ||
| 71 | if (!arm_feature(env, ARM_FEATURE_SVE)) { | ||
| 72 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) | ||
| 73 | * we already have the correct register contents when encountering the | ||
| 74 | * vq0->vq0 transition between EL0->EL1. | ||
| 75 | */ | ||
| 76 | - old_len = (arm_el_is_aa64(env, old_el) && !sve_exception_el(env, old_el) | ||
| 77 | + old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; | ||
| 78 | + old_len = (old_a64 && !sve_exception_el(env, old_el) | ||
| 79 | ? sve_zcr_len_for_el(env, old_el) : 0); | ||
| 80 | - new_len = (arm_el_is_aa64(env, new_el) && !sve_exception_el(env, new_el) | ||
| 81 | + new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; | ||
| 82 | + new_len = (new_a64 && !sve_exception_el(env, new_el) | ||
| 83 | ? sve_zcr_len_for_el(env, new_el) : 0); | ||
| 84 | |||
| 85 | /* When changing vector length, clear inaccessible state. */ | ||
| 86 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 87 | index XXXXXXX..XXXXXXX 100644 | ||
| 88 | --- a/target/arm/op_helper.c | ||
| 89 | +++ b/target/arm/op_helper.c | ||
| 90 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env) | ||
| 91 | "AArch64 EL%d PC 0x%" PRIx64 "\n", | ||
| 92 | cur_el, new_el, env->pc); | ||
| 93 | } | ||
| 94 | - aarch64_sve_change_el(env, cur_el, new_el); | ||
| 95 | + /* | ||
| 96 | + * Note that cur_el can never be 0. If new_el is 0, then | ||
| 97 | + * el0_a64 is return_to_aa64, else el0_a64 is ignored. | ||
| 98 | + */ | ||
| 99 | + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); | ||
| 100 | |||
| 101 | qemu_mutex_lock_iothread(); | ||
| 102 | arm_call_el_change_hook(arm_env_get_cpu(env)); | ||
| 103 | -- | 57 | -- |
| 104 | 2.19.0 | 58 | 2.34.1 |
| 105 | 59 | ||
| 106 | 60 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The missing nibble made it more difficult to read. | ||
| 4 | |||
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20181008212205.17752-5-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/cpu.c | 2 +- | ||
| 11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/cpu.c | ||
| 16 | +++ b/target/arm/cpu.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj) | ||
| 18 | cpu->id_mmfr1 = 0x00000000; | ||
| 19 | cpu->id_mmfr2 = 0x01200000; | ||
| 20 | cpu->id_mmfr3 = 0x0211; | ||
| 21 | - cpu->id_isar0 = 0x2101111; | ||
| 22 | + cpu->id_isar0 = 0x02101111; | ||
| 23 | cpu->id_isar1 = 0x13112111; | ||
| 24 | cpu->id_isar2 = 0x21232141; | ||
| 25 | cpu->id_isar3 = 0x01112131; | ||
| 26 | -- | ||
| 27 | 2.19.0 | ||
| 28 | |||
| 29 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The incorrect value advertised only thumb2 div without arm div. | ||
| 4 | |||
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20181008212205.17752-6-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/cpu.c | 5 ++++- | ||
| 11 | 1 file changed, 4 insertions(+), 1 deletion(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/cpu.c | ||
| 16 | +++ b/target/arm/cpu.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
| 18 | cpu->id_mmfr1 = 0x40000000; | ||
| 19 | cpu->id_mmfr2 = 0x01240000; | ||
| 20 | cpu->id_mmfr3 = 0x02102211; | ||
| 21 | - cpu->id_isar0 = 0x01101110; | ||
| 22 | + /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but | ||
| 23 | + * table 4-41 gives 0x02101110, which includes the arm div insns. | ||
| 24 | + */ | ||
| 25 | + cpu->id_isar0 = 0x02101110; | ||
| 26 | cpu->id_isar1 = 0x13112111; | ||
| 27 | cpu->id_isar2 = 0x21232041; | ||
| 28 | cpu->id_isar3 = 0x11112131; | ||
| 29 | -- | ||
| 30 | 2.19.0 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Disable the Timestamping Unit feature bit since QEMU does not | ||
| 4 | yet support it. This allows guest SW to correctly probe for | ||
| 5 | its existance. | ||
| 6 | |||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-2-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/net/cadence_gem.c | 2 +- | ||
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/net/cadence_gem.c | ||
| 18 | +++ b/hw/net/cadence_gem.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 20 | s->regs[GEM_MODID] = s->revision; | ||
| 21 | s->regs[GEM_DESCONF] = 0x02500111; | ||
| 22 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | ||
| 23 | - s->regs[GEM_DESCONF5] = 0x002f2145; | ||
| 24 | + s->regs[GEM_DESCONF5] = 0x002f2045; | ||
| 25 | s->regs[GEM_DESCONF6] = 0x00000200; | ||
| 26 | |||
| 27 | /* Set MAC address */ | ||
| 28 | -- | ||
| 29 | 2.19.0 | ||
| 30 | |||
| 31 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Announce the availability of the various priority queues. | ||
| 4 | This fixes an issue where guest kernels would miss to | ||
| 5 | configure secondary queues due to inproper feature bits. | ||
| 6 | |||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-3-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/net/cadence_gem.c | 6 +++++- | ||
| 13 | 1 file changed, 5 insertions(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/net/cadence_gem.c | ||
| 18 | +++ b/hw/net/cadence_gem.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 20 | int i; | ||
| 21 | CadenceGEMState *s = CADENCE_GEM(d); | ||
| 22 | const uint8_t *a; | ||
| 23 | + uint32_t queues_mask; | ||
| 24 | |||
| 25 | DB_PRINT("\n"); | ||
| 26 | |||
| 27 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 28 | s->regs[GEM_DESCONF] = 0x02500111; | ||
| 29 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | ||
| 30 | s->regs[GEM_DESCONF5] = 0x002f2045; | ||
| 31 | - s->regs[GEM_DESCONF6] = 0x00000200; | ||
| 32 | + s->regs[GEM_DESCONF6] = 0x0; | ||
| 33 | + | ||
| 34 | + queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); | ||
| 35 | + s->regs[GEM_DESCONF6] |= queues_mask; | ||
| 36 | |||
| 37 | /* Set MAC address */ | ||
| 38 | a = &s->conf.macaddr.a[0]; | ||
| 39 | -- | ||
| 40 | 2.19.0 | ||
| 41 | |||
| 42 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Use uint32_t instead of unsigned to describe 32bit descriptor words. | ||
| 4 | |||
| 5 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 7 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 8 | Message-id: 20181011021931.4249-4-edgar.iglesias@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | include/hw/net/cadence_gem.h | 2 +- | ||
| 12 | hw/net/cadence_gem.c | 42 ++++++++++++++++++------------------ | ||
| 13 | 2 files changed, 22 insertions(+), 22 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/include/hw/net/cadence_gem.h | ||
| 18 | +++ b/include/hw/net/cadence_gem.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState { | ||
| 20 | |||
| 21 | uint8_t can_rx_state; /* Debug only */ | ||
| 22 | |||
| 23 | - unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; | ||
| 24 | + uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; | ||
| 25 | |||
| 26 | bool sar_active[4]; | ||
| 27 | } CadenceGEMState; | ||
| 28 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/net/cadence_gem.c | ||
| 31 | +++ b/hw/net/cadence_gem.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ | ||
| 33 | |||
| 34 | #define GEM_MODID_VALUE 0x00020118 | ||
| 35 | |||
| 36 | -static inline unsigned tx_desc_get_buffer(unsigned *desc) | ||
| 37 | +static inline unsigned tx_desc_get_buffer(uint32_t *desc) | ||
| 38 | { | ||
| 39 | return desc[0]; | ||
| 40 | } | ||
| 41 | |||
| 42 | -static inline unsigned tx_desc_get_used(unsigned *desc) | ||
| 43 | +static inline unsigned tx_desc_get_used(uint32_t *desc) | ||
| 44 | { | ||
| 45 | return (desc[1] & DESC_1_USED) ? 1 : 0; | ||
| 46 | } | ||
| 47 | |||
| 48 | -static inline void tx_desc_set_used(unsigned *desc) | ||
| 49 | +static inline void tx_desc_set_used(uint32_t *desc) | ||
| 50 | { | ||
| 51 | desc[1] |= DESC_1_USED; | ||
| 52 | } | ||
| 53 | |||
| 54 | -static inline unsigned tx_desc_get_wrap(unsigned *desc) | ||
| 55 | +static inline unsigned tx_desc_get_wrap(uint32_t *desc) | ||
| 56 | { | ||
| 57 | return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; | ||
| 58 | } | ||
| 59 | |||
| 60 | -static inline unsigned tx_desc_get_last(unsigned *desc) | ||
| 61 | +static inline unsigned tx_desc_get_last(uint32_t *desc) | ||
| 62 | { | ||
| 63 | return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; | ||
| 64 | } | ||
| 65 | |||
| 66 | -static inline void tx_desc_set_last(unsigned *desc) | ||
| 67 | +static inline void tx_desc_set_last(uint32_t *desc) | ||
| 68 | { | ||
| 69 | desc[1] |= DESC_1_TX_LAST; | ||
| 70 | } | ||
| 71 | |||
| 72 | -static inline unsigned tx_desc_get_length(unsigned *desc) | ||
| 73 | +static inline unsigned tx_desc_get_length(uint32_t *desc) | ||
| 74 | { | ||
| 75 | return desc[1] & DESC_1_LENGTH; | ||
| 76 | } | ||
| 77 | |||
| 78 | -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) | ||
| 79 | +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) | ||
| 80 | { | ||
| 81 | DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); | ||
| 82 | DB_PRINT("bufaddr: 0x%08x\n", *desc); | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) | ||
| 84 | DB_PRINT("length: %d\n", tx_desc_get_length(desc)); | ||
| 85 | } | ||
| 86 | |||
| 87 | -static inline unsigned rx_desc_get_buffer(unsigned *desc) | ||
| 88 | +static inline unsigned rx_desc_get_buffer(uint32_t *desc) | ||
| 89 | { | ||
| 90 | return desc[0] & ~0x3UL; | ||
| 91 | } | ||
| 92 | |||
| 93 | -static inline unsigned rx_desc_get_wrap(unsigned *desc) | ||
| 94 | +static inline unsigned rx_desc_get_wrap(uint32_t *desc) | ||
| 95 | { | ||
| 96 | return desc[0] & DESC_0_RX_WRAP ? 1 : 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | -static inline unsigned rx_desc_get_ownership(unsigned *desc) | ||
| 100 | +static inline unsigned rx_desc_get_ownership(uint32_t *desc) | ||
| 101 | { | ||
| 102 | return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; | ||
| 103 | } | ||
| 104 | |||
| 105 | -static inline void rx_desc_set_ownership(unsigned *desc) | ||
| 106 | +static inline void rx_desc_set_ownership(uint32_t *desc) | ||
| 107 | { | ||
| 108 | desc[0] |= DESC_0_RX_OWNERSHIP; | ||
| 109 | } | ||
| 110 | |||
| 111 | -static inline void rx_desc_set_sof(unsigned *desc) | ||
| 112 | +static inline void rx_desc_set_sof(uint32_t *desc) | ||
| 113 | { | ||
| 114 | desc[1] |= DESC_1_RX_SOF; | ||
| 115 | } | ||
| 116 | |||
| 117 | -static inline void rx_desc_set_eof(unsigned *desc) | ||
| 118 | +static inline void rx_desc_set_eof(uint32_t *desc) | ||
| 119 | { | ||
| 120 | desc[1] |= DESC_1_RX_EOF; | ||
| 121 | } | ||
| 122 | |||
| 123 | -static inline void rx_desc_set_length(unsigned *desc, unsigned len) | ||
| 124 | +static inline void rx_desc_set_length(uint32_t *desc, unsigned len) | ||
| 125 | { | ||
| 126 | desc[1] &= ~DESC_1_LENGTH; | ||
| 127 | desc[1] |= len; | ||
| 128 | } | ||
| 129 | |||
| 130 | -static inline void rx_desc_set_broadcast(unsigned *desc) | ||
| 131 | +static inline void rx_desc_set_broadcast(uint32_t *desc) | ||
| 132 | { | ||
| 133 | desc[1] |= R_DESC_1_RX_BROADCAST; | ||
| 134 | } | ||
| 135 | |||
| 136 | -static inline void rx_desc_set_unicast_hash(unsigned *desc) | ||
| 137 | +static inline void rx_desc_set_unicast_hash(uint32_t *desc) | ||
| 138 | { | ||
| 139 | desc[1] |= R_DESC_1_RX_UNICAST_HASH; | ||
| 140 | } | ||
| 141 | |||
| 142 | -static inline void rx_desc_set_multicast_hash(unsigned *desc) | ||
| 143 | +static inline void rx_desc_set_multicast_hash(uint32_t *desc) | ||
| 144 | { | ||
| 145 | desc[1] |= R_DESC_1_RX_MULTICAST_HASH; | ||
| 146 | } | ||
| 147 | |||
| 148 | -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) | ||
| 149 | +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) | ||
| 150 | { | ||
| 151 | desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, | ||
| 152 | sar_idx); | ||
| 153 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, | ||
| 154 | */ | ||
| 155 | static void gem_transmit(CadenceGEMState *s) | ||
| 156 | { | ||
| 157 | - unsigned desc[2]; | ||
| 158 | + uint32_t desc[2]; | ||
| 159 | hwaddr packet_desc_addr; | ||
| 160 | uint8_t tx_packet[2048]; | ||
| 161 | uint8_t *p; | ||
| 162 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 163 | |||
| 164 | /* Last descriptor for this packet; hand the whole thing off */ | ||
| 165 | if (tx_desc_get_last(desc)) { | ||
| 166 | - unsigned desc_first[2]; | ||
| 167 | + uint32_t desc_first[2]; | ||
| 168 | |||
| 169 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 170 | * the processor. | ||
| 171 | -- | ||
| 172 | 2.19.0 | ||
| 173 | |||
| 174 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add macro with max number of DMA descriptor words. | ||
| 4 | No functional change. | ||
| 5 | |||
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | include/hw/net/cadence_gem.h | 5 ++++- | ||
| 13 | hw/net/cadence_gem.c | 4 ++-- | ||
| 14 | 2 files changed, 6 insertions(+), 3 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/hw/net/cadence_gem.h | ||
| 19 | +++ b/include/hw/net/cadence_gem.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | |||
| 22 | #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ | ||
| 23 | |||
| 24 | +/* Max number of words in a DMA descriptor. */ | ||
| 25 | +#define DESC_MAX_NUM_WORDS 2 | ||
| 26 | + | ||
| 27 | #define MAX_PRIORITY_QUEUES 8 | ||
| 28 | #define MAX_TYPE1_SCREENERS 16 | ||
| 29 | #define MAX_TYPE2_SCREENERS 16 | ||
| 30 | @@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState { | ||
| 31 | |||
| 32 | uint8_t can_rx_state; /* Debug only */ | ||
| 33 | |||
| 34 | - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; | ||
| 35 | + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; | ||
| 36 | |||
| 37 | bool sar_active[4]; | ||
| 38 | } CadenceGEMState; | ||
| 39 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/hw/net/cadence_gem.c | ||
| 42 | +++ b/hw/net/cadence_gem.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, | ||
| 44 | */ | ||
| 45 | static void gem_transmit(CadenceGEMState *s) | ||
| 46 | { | ||
| 47 | - uint32_t desc[2]; | ||
| 48 | + uint32_t desc[DESC_MAX_NUM_WORDS]; | ||
| 49 | hwaddr packet_desc_addr; | ||
| 50 | uint8_t tx_packet[2048]; | ||
| 51 | uint8_t *p; | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 53 | |||
| 54 | /* Last descriptor for this packet; hand the whole thing off */ | ||
| 55 | if (tx_desc_get_last(desc)) { | ||
| 56 | - uint32_t desc_first[2]; | ||
| 57 | + uint32_t desc_first[DESC_MAX_NUM_WORDS]; | ||
| 58 | |||
| 59 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 60 | * the processor. | ||
| 61 | -- | ||
| 62 | 2.19.0 | ||
| 63 | |||
| 64 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | Bit 63 in a Table descriptor is only the NSTable bit for stage 1 |
|---|---|---|---|
| 2 | translations; in stage 2 it is RES0. We were incorrectly looking at | ||
| 3 | it all the time. | ||
| 2 | 4 | ||
| 3 | Add the ARM Cortex-A72. | 5 | This causes problems if: |
| 6 | * the stage 2 table descriptor was incorrectly setting the RES0 bit | ||
| 7 | * we are doing a stage 2 translation in Secure address space for | ||
| 8 | a NonSecure stage 1 regime -- in this case we would incorrectly | ||
| 9 | do an immediate downgrade to NonSecure | ||
| 4 | 10 | ||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 11 | A bug elsewhere in the code currently prevents us from getting |
| 6 | Message-id: 20181011021931.4249-11-edgar.iglesias@gmail.com | 12 | to the second situation, but when we fix that it will be possible. |
| 13 | |||
| 14 | Cc: qemu-stable@nongnu.org | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 18 | Message-id: 20230504135425.2748672-2-peter.maydell@linaro.org | ||
| 8 | --- | 19 | --- |
| 9 | target/arm/cpu64.c | 66 +++++++++++++++++++++++++++++++++++++++++++--- | 20 | target/arm/ptw.c | 5 +++-- |
| 10 | 1 file changed, 63 insertions(+), 3 deletions(-) | 21 | 1 file changed, 3 insertions(+), 2 deletions(-) |
| 11 | 22 | ||
| 12 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 23 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
| 13 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/arm/cpu64.c | 25 | --- a/target/arm/ptw.c |
| 15 | +++ b/target/arm/cpu64.c | 26 | +++ b/target/arm/ptw.c |
| 16 | @@ -XXX,XX +XXX,XX @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | 27 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, |
| 17 | } | 28 | descaddrmask &= ~indexmask_grainsize; |
| 18 | #endif | 29 | |
| 19 | 30 | /* | |
| 20 | -static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { | 31 | - * Secure accesses start with the page table in secure memory and |
| 21 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | 32 | + * Secure stage 1 accesses start with the page table in secure memory and |
| 22 | #ifndef CONFIG_USER_ONLY | 33 | * can be downgraded to non-secure at any step. Non-secure accesses |
| 23 | { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | 34 | * remain non-secure. We implement this by just ORing in the NSTable/NS |
| 24 | .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | 35 | * bits at each step. |
| 25 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | 36 | + * Stage 2 never gets this kind of downgrade. |
| 26 | cpu->gic_num_lrs = 4; | 37 | */ |
| 27 | cpu->gic_vpribits = 5; | 38 | tableattrs = is_secure ? 0 : (1 << 4); |
| 28 | cpu->gic_vprebits = 5; | 39 | |
| 29 | - define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); | 40 | next_level: |
| 30 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | 41 | descaddr |= (address >> (stride * (4 - level))) & indexmask; |
| 31 | } | 42 | descaddr &= ~7ULL; |
| 32 | 43 | - nstable = extract32(tableattrs, 4, 1); | |
| 33 | static void aarch64_a53_initfn(Object *obj) | 44 | + nstable = !regime_is_stage2(mmu_idx) && extract32(tableattrs, 4, 1); |
| 34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | 45 | if (nstable) { |
| 35 | cpu->gic_num_lrs = 4; | 46 | /* |
| 36 | cpu->gic_vpribits = 5; | 47 | * Stage2_S -> Stage2 or Phys_S -> Phys_NS |
| 37 | cpu->gic_vprebits = 5; | ||
| 38 | - define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); | ||
| 39 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 40 | +} | ||
| 41 | + | ||
| 42 | +static void aarch64_a72_initfn(Object *obj) | ||
| 43 | +{ | ||
| 44 | + ARMCPU *cpu = ARM_CPU(obj); | ||
| 45 | + | ||
| 46 | + cpu->dtb_compatible = "arm,cortex-a72"; | ||
| 47 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
| 48 | + set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
| 49 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
| 50 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
| 51 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
| 52 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
| 53 | + set_feature(&cpu->env, ARM_FEATURE_V8_AES); | ||
| 54 | + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | ||
| 55 | + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | ||
| 56 | + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
| 57 | + set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
| 58 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
| 59 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
| 60 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
| 61 | + cpu->midr = 0x410fd083; | ||
| 62 | + cpu->revidr = 0x00000000; | ||
| 63 | + cpu->reset_fpsid = 0x41034080; | ||
| 64 | + cpu->mvfr0 = 0x10110222; | ||
| 65 | + cpu->mvfr1 = 0x12111111; | ||
| 66 | + cpu->mvfr2 = 0x00000043; | ||
| 67 | + cpu->ctr = 0x8444c004; | ||
| 68 | + cpu->reset_sctlr = 0x00c50838; | ||
| 69 | + cpu->id_pfr0 = 0x00000131; | ||
| 70 | + cpu->id_pfr1 = 0x00011011; | ||
| 71 | + cpu->id_dfr0 = 0x03010066; | ||
| 72 | + cpu->id_afr0 = 0x00000000; | ||
| 73 | + cpu->id_mmfr0 = 0x10201105; | ||
| 74 | + cpu->id_mmfr1 = 0x40000000; | ||
| 75 | + cpu->id_mmfr2 = 0x01260000; | ||
| 76 | + cpu->id_mmfr3 = 0x02102211; | ||
| 77 | + cpu->id_isar0 = 0x02101110; | ||
| 78 | + cpu->id_isar1 = 0x13112111; | ||
| 79 | + cpu->id_isar2 = 0x21232042; | ||
| 80 | + cpu->id_isar3 = 0x01112131; | ||
| 81 | + cpu->id_isar4 = 0x00011142; | ||
| 82 | + cpu->id_isar5 = 0x00011121; | ||
| 83 | + cpu->id_aa64pfr0 = 0x00002222; | ||
| 84 | + cpu->id_aa64dfr0 = 0x10305106; | ||
| 85 | + cpu->pmceid0 = 0x00000000; | ||
| 86 | + cpu->pmceid1 = 0x00000000; | ||
| 87 | + cpu->id_aa64isar0 = 0x00011120; | ||
| 88 | + cpu->id_aa64mmfr0 = 0x00001124; | ||
| 89 | + cpu->dbgdidr = 0x3516d000; | ||
| 90 | + cpu->clidr = 0x0a200023; | ||
| 91 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 92 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
| 93 | + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ | ||
| 94 | + cpu->dcz_blocksize = 4; /* 64 bytes */ | ||
| 95 | + cpu->gic_num_lrs = 4; | ||
| 96 | + cpu->gic_vpribits = 5; | ||
| 97 | + cpu->gic_vprebits = 5; | ||
| 98 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 99 | } | ||
| 100 | |||
| 101 | static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, | ||
| 102 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMCPUInfo { | ||
| 103 | static const ARMCPUInfo aarch64_cpus[] = { | ||
| 104 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | ||
| 105 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | ||
| 106 | + { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
| 107 | { .name = "max", .initfn = aarch64_max_initfn }, | ||
| 108 | { .name = NULL } | ||
| 109 | }; | ||
| 110 | -- | 48 | -- |
| 111 | 2.19.0 | 49 | 2.34.1 |
| 112 | 50 | ||
| 113 | 51 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW |
|---|---|---|---|
| 2 | configuration bits. These allow configuration of whether the stage 2 | ||
| 3 | page table walks for Secure IPA and NonSecure IPA should do their | ||
| 4 | descriptor reads from Secure or NonSecure physical addresses. (This | ||
| 5 | is separate from how the translation table base address and other | ||
| 6 | parameters are set: an NS IPA always uses VTTBR_EL2 and VTCR_EL2 | ||
| 7 | for its base address and walk parameters, regardless of the NSW bit, | ||
| 8 | and similarly for Secure.) | ||
| 2 | 9 | ||
| 3 | Implement support for 64bit descriptor addresses. | 10 | Provide a new function ptw_idx_for_stage_2() which returns the |
| 11 | MMU index to use for descriptor reads, and use it to set up | ||
| 12 | the .in_ptw_idx wherever we call get_phys_addr_lpae(). | ||
| 4 | 13 | ||
| 5 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 14 | For a stage 2 walk, wherever we call get_phys_addr_lpae(): |
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 15 | * .in_ptw_idx should be ptw_idx_for_stage_2() of the .in_mmu_idx |
| 7 | Message-id: 20181011021931.4249-8-edgar.iglesias@gmail.com | 16 | * .in_secure should be true if .in_mmu_idx is Stage2_S |
| 17 | |||
| 18 | This allows us to correct S1_ptw_translate() so that it consistently | ||
| 19 | always sets its (out_secure, out_phys) to the result it gets from the | ||
| 20 | S2 walk (either by calling get_phys_addr_lpae() or by TLB lookup). | ||
| 21 | This makes better conceptual sense because the S2 walk should return | ||
| 22 | us an (address space, address) tuple, not an address that we then | ||
| 23 | randomly assign to S or NS. | ||
| 24 | |||
| 25 | Our previous handling of SW and NSW was broken, so guest code | ||
| 26 | trying to use these bits to put the s2 page tables in the "other" | ||
| 27 | address space wouldn't work correctly. | ||
| 28 | |||
| 29 | Cc: qemu-stable@nongnu.org | ||
| 30 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1600 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 31 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 32 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 33 | Message-id: 20230504135425.2748672-3-peter.maydell@linaro.org | ||
| 9 | --- | 34 | --- |
| 10 | hw/net/cadence_gem.c | 47 ++++++++++++++++++++++++++++++++++++-------- | 35 | target/arm/ptw.c | 76 ++++++++++++++++++++++++++++++++---------------- |
| 11 | 1 file changed, 39 insertions(+), 8 deletions(-) | 36 | 1 file changed, 51 insertions(+), 25 deletions(-) |
| 12 | 37 | ||
| 13 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | 38 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
| 14 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/net/cadence_gem.c | 40 | --- a/target/arm/ptw.c |
| 16 | +++ b/hw/net/cadence_gem.c | 41 | +++ b/target/arm/ptw.c |
| 17 | @@ -XXX,XX +XXX,XX @@ | 42 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) |
| 18 | #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) | 43 | return stage_1_mmu_idx(arm_mmu_idx(env)); |
| 19 | #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) | 44 | } |
| 20 | 45 | ||
| 21 | +#define GEM_TBQPH (0x000004C8 / 4) | 46 | +/* |
| 22 | +#define GEM_RBQPH (0x000004D4 / 4) | 47 | + * Return where we should do ptw loads from for a stage 2 walk. |
| 48 | + * This depends on whether the address we are looking up is a | ||
| 49 | + * Secure IPA or a NonSecure IPA, which we know from whether this is | ||
| 50 | + * Stage2 or Stage2_S. | ||
| 51 | + * If this is the Secure EL1&0 regime we need to check the NSW and SW bits. | ||
| 52 | + */ | ||
| 53 | +static ARMMMUIdx ptw_idx_for_stage_2(CPUARMState *env, ARMMMUIdx stage2idx) | ||
| 54 | +{ | ||
| 55 | + bool s2walk_secure; | ||
| 23 | + | 56 | + |
| 24 | #define GEM_INT_Q1_ENABLE (0x00000600 / 4) | 57 | + /* |
| 25 | #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) | 58 | + * We're OK to check the current state of the CPU here because |
| 26 | 59 | + * (1) we always invalidate all TLBs when the SCR_EL3.NS bit changes | |
| 27 | @@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, | 60 | + * (2) there's no way to do a lookup that cares about Stage 2 for a |
| 28 | return 0; | 61 | + * different security state to the current one for AArch64, and AArch32 |
| 29 | } | 62 | + * never has a secure EL2. (AArch32 ATS12NSO[UP][RW] allow EL3 to do |
| 30 | 63 | + * an NS stage 1+2 lookup while the NS bit is 0.) | |
| 31 | +static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) | 64 | + */ |
| 32 | +{ | 65 | + if (!arm_is_secure_below_el3(env) || !arm_el_is_aa64(env, 3)) { |
| 33 | + hwaddr desc_addr = 0; | 66 | + return ARMMMUIdx_Phys_NS; |
| 67 | + } | ||
| 68 | + if (stage2idx == ARMMMUIdx_Stage2_S) { | ||
| 69 | + s2walk_secure = !(env->cp15.vstcr_el2 & VSTCR_SW); | ||
| 70 | + } else { | ||
| 71 | + s2walk_secure = !(env->cp15.vtcr_el2 & VTCR_NSW); | ||
| 72 | + } | ||
| 73 | + return s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | ||
| 34 | + | 74 | + |
| 35 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 36 | + desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; | ||
| 37 | + } | ||
| 38 | + desc_addr <<= 32; | ||
| 39 | + desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; | ||
| 40 | + return desc_addr; | ||
| 41 | +} | 75 | +} |
| 42 | + | 76 | + |
| 43 | +static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) | 77 | static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 44 | +{ | 78 | { |
| 45 | + return gem_get_desc_addr(s, true, q); | 79 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; |
| 46 | +} | 80 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
| 81 | ARMMMUIdx mmu_idx = ptw->in_mmu_idx; | ||
| 82 | ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; | ||
| 83 | uint8_t pte_attrs; | ||
| 84 | - bool pte_secure; | ||
| 85 | |||
| 86 | ptw->out_virt = addr; | ||
| 87 | |||
| 88 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
| 89 | if (regime_is_stage2(s2_mmu_idx)) { | ||
| 90 | S1Translate s2ptw = { | ||
| 91 | .in_mmu_idx = s2_mmu_idx, | ||
| 92 | - .in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS, | ||
| 93 | - .in_secure = is_secure, | ||
| 94 | + .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), | ||
| 95 | + .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, | ||
| 96 | .in_debug = true, | ||
| 97 | }; | ||
| 98 | GetPhysAddrResult s2 = { }; | ||
| 99 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
| 100 | } | ||
| 101 | ptw->out_phys = s2.f.phys_addr; | ||
| 102 | pte_attrs = s2.cacheattrs.attrs; | ||
| 103 | - pte_secure = s2.f.attrs.secure; | ||
| 104 | + ptw->out_secure = s2.f.attrs.secure; | ||
| 105 | } else { | ||
| 106 | /* Regime is physical. */ | ||
| 107 | ptw->out_phys = addr; | ||
| 108 | pte_attrs = 0; | ||
| 109 | - pte_secure = is_secure; | ||
| 110 | + ptw->out_secure = s2_mmu_idx == ARMMMUIdx_Phys_S; | ||
| 111 | } | ||
| 112 | ptw->out_host = NULL; | ||
| 113 | ptw->out_rw = false; | ||
| 114 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
| 115 | ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); | ||
| 116 | ptw->out_rw = full->prot & PAGE_WRITE; | ||
| 117 | pte_attrs = full->pte_attrs; | ||
| 118 | - pte_secure = full->attrs.secure; | ||
| 119 | + ptw->out_secure = full->attrs.secure; | ||
| 120 | #else | ||
| 121 | g_assert_not_reached(); | ||
| 122 | #endif | ||
| 123 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | - /* Check if page table walk is to secure or non-secure PA space. */ | ||
| 128 | - ptw->out_secure = (is_secure | ||
| 129 | - && !(pte_secure | ||
| 130 | - ? env->cp15.vstcr_el2 & VSTCR_SW | ||
| 131 | - : env->cp15.vtcr_el2 & VTCR_NSW)); | ||
| 132 | ptw->out_be = regime_translation_big_endian(env, mmu_idx); | ||
| 133 | return true; | ||
| 134 | |||
| 135 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
| 136 | hwaddr ipa; | ||
| 137 | int s1_prot, s1_lgpgsz; | ||
| 138 | bool is_secure = ptw->in_secure; | ||
| 139 | - bool ret, ipa_secure, s2walk_secure; | ||
| 140 | + bool ret, ipa_secure; | ||
| 141 | ARMCacheAttrs cacheattrs1; | ||
| 142 | bool is_el0; | ||
| 143 | uint64_t hcr; | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, | ||
| 145 | |||
| 146 | ipa = result->f.phys_addr; | ||
| 147 | ipa_secure = result->f.attrs.secure; | ||
| 148 | - if (is_secure) { | ||
| 149 | - /* Select TCR based on the NS bit from the S1 walk. */ | ||
| 150 | - s2walk_secure = !(ipa_secure | ||
| 151 | - ? env->cp15.vstcr_el2 & VSTCR_SW | ||
| 152 | - : env->cp15.vtcr_el2 & VTCR_NSW); | ||
| 153 | - } else { | ||
| 154 | - assert(!ipa_secure); | ||
| 155 | - s2walk_secure = false; | ||
| 156 | - } | ||
| 157 | |||
| 158 | is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; | ||
| 159 | - ptw->in_mmu_idx = s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
| 160 | - ptw->in_ptw_idx = s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; | ||
| 161 | - ptw->in_secure = s2walk_secure; | ||
| 162 | + ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
| 163 | + ptw->in_secure = ipa_secure; | ||
| 164 | + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); | ||
| 165 | |||
| 166 | /* | ||
| 167 | * S1 is done, now do S2 translation. | ||
| 168 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, | ||
| 169 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; | ||
| 170 | break; | ||
| 171 | |||
| 172 | + case ARMMMUIdx_Stage2: | ||
| 173 | + case ARMMMUIdx_Stage2_S: | ||
| 174 | + /* | ||
| 175 | + * Second stage lookup uses physical for ptw; whether this is S or | ||
| 176 | + * NS may depend on the SW/NSW bits if this is a stage 2 lookup for | ||
| 177 | + * the Secure EL2&0 regime. | ||
| 178 | + */ | ||
| 179 | + ptw->in_ptw_idx = ptw_idx_for_stage_2(env, mmu_idx); | ||
| 180 | + break; | ||
| 47 | + | 181 | + |
| 48 | +static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) | 182 | case ARMMMUIdx_E10_0: |
| 49 | +{ | 183 | s1_mmu_idx = ARMMMUIdx_Stage1_E0; |
| 50 | + return gem_get_desc_addr(s, false, q); | 184 | goto do_twostage; |
| 51 | +} | 185 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, |
| 52 | + | 186 | /* fall through */ |
| 53 | static void gem_get_rx_desc(CadenceGEMState *s, int q) | 187 | |
| 54 | { | 188 | default: |
| 55 | - DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); | 189 | - /* Single stage and second stage uses physical for ptw. */ |
| 56 | + hwaddr desc_addr = gem_get_rx_desc_addr(s, q); | 190 | + /* Single stage uses physical for ptw. */ |
| 57 | + | 191 | ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_NS; |
| 58 | + DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); | 192 | break; |
| 59 | + | 193 | } |
| 60 | /* read current descriptor */ | ||
| 61 | - address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, | ||
| 62 | + address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, | ||
| 63 | (uint8_t *)s->rx_desc[q], | ||
| 64 | sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 65 | |||
| 66 | /* Descriptor owned by software ? */ | ||
| 67 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { | ||
| 68 | - DB_PRINT("descriptor 0x%x owned by sw.\n", | ||
| 69 | - (unsigned)s->rx_desc_addr[q]); | ||
| 70 | + DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); | ||
| 71 | s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; | ||
| 72 | s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); | ||
| 73 | /* Handle interrupt consequences */ | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 75 | q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); | ||
| 76 | |||
| 77 | while (bytes_to_copy) { | ||
| 78 | + hwaddr desc_addr; | ||
| 79 | + | ||
| 80 | /* Do nothing if receive is not enabled. */ | ||
| 81 | if (!gem_can_receive(nc)) { | ||
| 82 | assert(!first_desc); | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 84 | } | ||
| 85 | |||
| 86 | /* Descriptor write-back. */ | ||
| 87 | - address_space_write(&s->dma_as, s->rx_desc_addr[q], | ||
| 88 | + desc_addr = gem_get_rx_desc_addr(s, q); | ||
| 89 | + address_space_write(&s->dma_as, desc_addr, | ||
| 90 | MEMTXATTRS_UNSPECIFIED, | ||
| 91 | (uint8_t *)s->rx_desc[q], | ||
| 92 | sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 94 | |||
| 95 | for (q = s->num_priority_queues - 1; q >= 0; q--) { | ||
| 96 | /* read current descriptor */ | ||
| 97 | - packet_desc_addr = s->tx_desc_addr[q]; | ||
| 98 | + packet_desc_addr = gem_get_tx_desc_addr(s, q); | ||
| 99 | |||
| 100 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 101 | address_space_read(&s->dma_as, packet_desc_addr, | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 103 | /* Last descriptor for this packet; hand the whole thing off */ | ||
| 104 | if (tx_desc_get_last(desc)) { | ||
| 105 | uint32_t desc_first[DESC_MAX_NUM_WORDS]; | ||
| 106 | + hwaddr desc_addr = gem_get_tx_desc_addr(s, q); | ||
| 107 | |||
| 108 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 109 | * the processor. | ||
| 110 | */ | ||
| 111 | - address_space_read(&s->dma_as, s->tx_desc_addr[q], | ||
| 112 | + address_space_read(&s->dma_as, desc_addr, | ||
| 113 | MEMTXATTRS_UNSPECIFIED, | ||
| 114 | (uint8_t *)desc_first, | ||
| 115 | sizeof(desc_first)); | ||
| 116 | tx_desc_set_used(desc_first); | ||
| 117 | - address_space_write(&s->dma_as, s->tx_desc_addr[q], | ||
| 118 | + address_space_write(&s->dma_as, desc_addr, | ||
| 119 | MEMTXATTRS_UNSPECIFIED, | ||
| 120 | (uint8_t *)desc_first, | ||
| 121 | sizeof(desc_first)); | ||
| 122 | -- | 194 | -- |
| 123 | 2.19.0 | 195 | 2.34.1 |
| 124 | |||
| 125 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Akihiko Odaki <akihiko.odaki@gmail.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | When QEMU provides the equivalent of the EL3 firmware, we | 3 | I am now employed by Daynix. Although my role as a reviewer of |
| 4 | need to enable HVCs in scr_el3 when turning on CPUs that | 4 | macOS-related change is not very relevant to the employment, I decided |
| 5 | target EL2. | 5 | to use the company email address to avoid confusions from different |
| 6 | addresses. | ||
| 6 | 7 | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> |
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 9 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
| 9 | Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
| 11 | Message-id: 20230506072333.32510-1-akihiko.odaki@daynix.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 13 | --- |
| 12 | target/arm/arm-powerctl.c | 10 ++++++++++ | 14 | MAINTAINERS | 4 ++-- |
| 13 | 1 file changed, 10 insertions(+) | 15 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 14 | 16 | ||
| 15 | diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c | 17 | diff --git a/MAINTAINERS b/MAINTAINERS |
| 16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/target/arm/arm-powerctl.c | 19 | --- a/MAINTAINERS |
| 18 | +++ b/target/arm/arm-powerctl.c | 20 | +++ b/MAINTAINERS |
| 19 | @@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, | 21 | @@ -XXX,XX +XXX,XX @@ Core Audio framework backend |
| 20 | } else { | 22 | M: Gerd Hoffmann <kraxel@redhat.com> |
| 21 | /* Processor is not in secure mode */ | 23 | M: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 22 | target_cpu->env.cp15.scr_el3 |= SCR_NS; | 24 | R: Christian Schoenebeck <qemu_oss@crudebyte.com> |
| 23 | + | 25 | -R: Akihiko Odaki <akihiko.odaki@gmail.com> |
| 24 | + /* | 26 | +R: Akihiko Odaki <akihiko.odaki@daynix.com> |
| 25 | + * If QEMU is providing the equivalent of EL3 firmware, then we need | 27 | S: Odd Fixes |
| 26 | + * to make sure a CPU targeting EL2 comes out of reset with a | 28 | F: audio/coreaudio.c |
| 27 | + * functional HVC insn. | 29 | |
| 28 | + */ | 30 | @@ -XXX,XX +XXX,XX @@ F: docs/devel/ui.rst |
| 29 | + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) | 31 | Cocoa graphics |
| 30 | + && info->target_el == 2) { | 32 | M: Peter Maydell <peter.maydell@linaro.org> |
| 31 | + target_cpu->env.cp15.scr_el3 |= SCR_HCE; | 33 | M: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 32 | + } | 34 | -R: Akihiko Odaki <akihiko.odaki@gmail.com> |
| 33 | } | 35 | +R: Akihiko Odaki <akihiko.odaki@daynix.com> |
| 34 | 36 | S: Odd Fixes | |
| 35 | /* We check if the started CPU is now at the correct level */ | 37 | F: ui/cocoa.m |
| 38 | |||
| 36 | -- | 39 | -- |
| 37 | 2.19.0 | 40 | 2.34.1 |
| 38 | 41 | ||
| 39 | 42 | diff view generated by jsdifflib |
| 1 | The get_phys_addr() functions take a pointer to an ARMMMUFaultInfo | 1 | When we take a PNG screenshot the ordering of the colour channels in |
|---|---|---|---|
| 2 | struct, which they fill in only if a fault occurs. This means that | 2 | the data is not correct, resulting in the image having weird |
| 3 | the caller must always zero-initialize the struct before passing | 3 | colouring compared to the actual display. (Specifically, on a |
| 4 | it in. We forgot to do this in v7m_stack_read() and v7m_stack_write(). | 4 | little-endian host the blue and red channels are swapped; on |
| 5 | Correct the error. | 5 | big-endian everything is wrong.) |
| 6 | 6 | ||
| 7 | This happens because the pixman idea of the pixel data and the libpng | ||
| 8 | idea differ. PIXMAN_a8r8g8b8 defines that pixels are 32-bit values, | ||
| 9 | with A in bits 24-31, R in bits 16-23, G in bits 8-15 and B in bits | ||
| 10 | 0-7. This means that on little-endian systems the bytes in memory | ||
| 11 | are | ||
| 12 | B G R A | ||
| 13 | and on big-endian systems they are | ||
| 14 | A R G B | ||
| 15 | |||
| 16 | libpng, on the other hand, thinks of pixels as being a series of | ||
| 17 | values for each channel, so its format PNG_COLOR_TYPE_RGB_ALPHA | ||
| 18 | always wants bytes in the order | ||
| 19 | R G B A | ||
| 20 | |||
| 21 | This isn't the same as the pixman order for either big or little | ||
| 22 | endian hosts. | ||
| 23 | |||
| 24 | The alpha channel is also unnecessary bulk in the output PNG file, | ||
| 25 | because there is no alpha information in a screenshot. | ||
| 26 | |||
| 27 | To handle the endianness issue, we already define in ui/qemu-pixman.h | ||
| 28 | various PIXMAN_BE_* and PIXMAN_LE_* values that give consistent | ||
| 29 | byte-order pixel channel formats. So we can use PIXMAN_BE_r8g8b8 and | ||
| 30 | PNG_COLOR_TYPE_RGB, which both have an in-memory byte order of | ||
| 31 | R G B | ||
| 32 | and 3 bytes per pixel. | ||
| 33 | |||
| 34 | (PPM format screenshots get this right; they already use the | ||
| 35 | PIXMAN_BE_r8g8b8 format.) | ||
| 36 | |||
| 37 | Cc: qemu-stable@nongnu.org | ||
| 38 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1622 | ||
| 39 | Fixes: 9a0a119a382867 ("Added parameter to take screenshot with screendump as PNG") | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 40 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 41 | Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> |
| 9 | Message-id: 20181011172057.9466-1-peter.maydell@linaro.org | 42 | Message-id: 20230502135548.2451309-1-peter.maydell@linaro.org |
| 10 | --- | 43 | --- |
| 11 | target/arm/helper.c | 4 ++-- | 44 | ui/console.c | 4 ++-- |
| 12 | 1 file changed, 2 insertions(+), 2 deletions(-) | 45 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 13 | 46 | ||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 47 | diff --git a/ui/console.c b/ui/console.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/helper.c | 49 | --- a/ui/console.c |
| 17 | +++ b/target/arm/helper.c | 50 | +++ b/ui/console.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | 51 | @@ -XXX,XX +XXX,XX @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) |
| 19 | target_ulong page_size; | 52 | png_struct *png_ptr; |
| 20 | hwaddr physaddr; | 53 | png_info *info_ptr; |
| 21 | int prot; | 54 | g_autoptr(pixman_image_t) linebuf = |
| 22 | - ARMMMUFaultInfo fi; | 55 | - qemu_pixman_linebuf_create(PIXMAN_a8r8g8b8, width); |
| 23 | + ARMMMUFaultInfo fi = {}; | 56 | + qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); |
| 24 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; | 57 | uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf); |
| 25 | int exc; | 58 | FILE *f = fdopen(fd, "wb"); |
| 26 | bool exc_secure; | 59 | int y; |
| 27 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, | 60 | @@ -XXX,XX +XXX,XX @@ static bool png_save(int fd, pixman_image_t *image, Error **errp) |
| 28 | target_ulong page_size; | 61 | png_init_io(png_ptr, f); |
| 29 | hwaddr physaddr; | 62 | |
| 30 | int prot; | 63 | png_set_IHDR(png_ptr, info_ptr, width, height, 8, |
| 31 | - ARMMMUFaultInfo fi; | 64 | - PNG_COLOR_TYPE_RGB_ALPHA, PNG_INTERLACE_NONE, |
| 32 | + ARMMMUFaultInfo fi = {}; | 65 | + PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE, |
| 33 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; | 66 | PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); |
| 34 | int exc; | 67 | |
| 35 | bool exc_secure; | 68 | png_write_info(png_ptr, info_ptr); |
| 36 | -- | 69 | -- |
| 37 | 2.19.0 | 70 | 2.34.1 |
| 38 | 71 | ||
| 39 | 72 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | In the doc sources, we have a few cross-reference targets with odd |
|---|---|---|---|
| 2 | names "pcsys_005fxyz". These are the legacy of the semi-automated | ||
| 3 | conversion of the old info docs to rST (the '005f' is because ASCII | ||
| 4 | 0x5f is '_' and the old info link names had underscores in them). | ||
| 2 | 5 | ||
| 3 | Announce 64bit addressing support. | 6 | Remove the targets which nothing links to, and rename the two targets |
| 7 | which are used to something a bit more descriptive. | ||
| 4 | 8 | ||
| 5 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 7 | Message-id: 20181011021931.4249-9-edgar.iglesias@gmail.com | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | Message-id: 20230421163642.1151904-1-peter.maydell@linaro.org | ||
| 11 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
| 9 | --- | 12 | --- |
| 10 | hw/net/cadence_gem.c | 3 ++- | 13 | docs/system/devices/igb.rst | 2 +- |
| 11 | 1 file changed, 2 insertions(+), 1 deletion(-) | 14 | docs/system/devices/ivshmem.rst | 2 -- |
| 15 | docs/system/devices/net.rst | 2 +- | ||
| 16 | docs/system/devices/usb.rst | 2 -- | ||
| 17 | docs/system/keys.rst | 2 +- | ||
| 18 | docs/system/linuxboot.rst | 2 +- | ||
| 19 | docs/system/target-i386.rst | 4 ---- | ||
| 20 | 7 files changed, 4 insertions(+), 12 deletions(-) | ||
| 12 | 21 | ||
| 13 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | 22 | diff --git a/docs/system/devices/igb.rst b/docs/system/devices/igb.rst |
| 14 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/hw/net/cadence_gem.c | 24 | --- a/docs/system/devices/igb.rst |
| 16 | +++ b/hw/net/cadence_gem.c | 25 | +++ b/docs/system/devices/igb.rst |
| 26 | @@ -XXX,XX +XXX,XX @@ Using igb | ||
| 27 | ========= | ||
| 28 | |||
| 29 | Using igb should be nothing different from using another network device. See | ||
| 30 | -:ref:`pcsys_005fnetwork` in general. | ||
| 31 | +:ref:`Network_emulation` in general. | ||
| 32 | |||
| 33 | However, you may also need to perform additional steps to activate SR-IOV | ||
| 34 | feature on your guest. For Linux, refer to [4]_. | ||
| 35 | diff --git a/docs/system/devices/ivshmem.rst b/docs/system/devices/ivshmem.rst | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/docs/system/devices/ivshmem.rst | ||
| 38 | +++ b/docs/system/devices/ivshmem.rst | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | 39 | @@ -XXX,XX +XXX,XX @@ |
| 18 | #define GEM_DESCONF4 (0x0000028C/4) | 40 | -.. _pcsys_005fivshmem: |
| 19 | #define GEM_DESCONF5 (0x00000290/4) | 41 | - |
| 20 | #define GEM_DESCONF6 (0x00000294/4) | 42 | Inter-VM Shared Memory device |
| 21 | +#define GEM_DESCONF6_64B_MASK (1U << 23) | 43 | ----------------------------- |
| 22 | #define GEM_DESCONF7 (0x00000298/4) | 44 | |
| 23 | 45 | diff --git a/docs/system/devices/net.rst b/docs/system/devices/net.rst | |
| 24 | #define GEM_INT_Q1_STATUS (0x00000400 / 4) | 46 | index XXXXXXX..XXXXXXX 100644 |
| 25 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | 47 | --- a/docs/system/devices/net.rst |
| 26 | s->regs[GEM_DESCONF] = 0x02500111; | 48 | +++ b/docs/system/devices/net.rst |
| 27 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | 49 | @@ -XXX,XX +XXX,XX @@ |
| 28 | s->regs[GEM_DESCONF5] = 0x002f2045; | 50 | -.. _pcsys_005fnetwork: |
| 29 | - s->regs[GEM_DESCONF6] = 0x0; | 51 | +.. _Network_Emulation: |
| 30 | + s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; | 52 | |
| 31 | 53 | Network emulation | |
| 32 | queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); | 54 | ----------------- |
| 33 | s->regs[GEM_DESCONF6] |= queues_mask; | 55 | diff --git a/docs/system/devices/usb.rst b/docs/system/devices/usb.rst |
| 56 | index XXXXXXX..XXXXXXX 100644 | ||
| 57 | --- a/docs/system/devices/usb.rst | ||
| 58 | +++ b/docs/system/devices/usb.rst | ||
| 59 | @@ -XXX,XX +XXX,XX @@ | ||
| 60 | -.. _pcsys_005fusb: | ||
| 61 | - | ||
| 62 | USB emulation | ||
| 63 | ------------- | ||
| 64 | |||
| 65 | diff --git a/docs/system/keys.rst b/docs/system/keys.rst | ||
| 66 | index XXXXXXX..XXXXXXX 100644 | ||
| 67 | --- a/docs/system/keys.rst | ||
| 68 | +++ b/docs/system/keys.rst | ||
| 69 | @@ -XXX,XX +XXX,XX @@ | ||
| 70 | -.. _pcsys_005fkeys: | ||
| 71 | +.. _GUI_keys: | ||
| 72 | |||
| 73 | Keys in the graphical frontends | ||
| 74 | ------------------------------- | ||
| 75 | diff --git a/docs/system/linuxboot.rst b/docs/system/linuxboot.rst | ||
| 76 | index XXXXXXX..XXXXXXX 100644 | ||
| 77 | --- a/docs/system/linuxboot.rst | ||
| 78 | +++ b/docs/system/linuxboot.rst | ||
| 79 | @@ -XXX,XX +XXX,XX @@ virtual serial port and the QEMU monitor to the console with the | ||
| 80 | -append "root=/dev/hda console=ttyS0" -nographic | ||
| 81 | |||
| 82 | Use Ctrl-a c to switch between the serial console and the monitor (see | ||
| 83 | -:ref:`pcsys_005fkeys`). | ||
| 84 | +:ref:`GUI_keys`). | ||
| 85 | diff --git a/docs/system/target-i386.rst b/docs/system/target-i386.rst | ||
| 86 | index XXXXXXX..XXXXXXX 100644 | ||
| 87 | --- a/docs/system/target-i386.rst | ||
| 88 | +++ b/docs/system/target-i386.rst | ||
| 89 | @@ -XXX,XX +XXX,XX @@ | ||
| 90 | x86 System emulator | ||
| 91 | ------------------- | ||
| 92 | |||
| 93 | -.. _pcsys_005fdevices: | ||
| 94 | - | ||
| 95 | Board-specific documentation | ||
| 96 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | ||
| 97 | |||
| 98 | @@ -XXX,XX +XXX,XX @@ Architectural features | ||
| 99 | i386/sgx | ||
| 100 | i386/amd-memory-encryption | ||
| 101 | |||
| 102 | -.. _pcsys_005freq: | ||
| 103 | - | ||
| 104 | OS requirements | ||
| 105 | ~~~~~~~~~~~~~~~ | ||
| 106 | |||
| 34 | -- | 107 | -- |
| 35 | 2.19.0 | 108 | 2.34.1 |
| 36 | |||
| 37 | diff view generated by jsdifflib |
| 1 | Add a new Coccinelle script which replaces uses of the inplace | 1 | Coverity points out (in CID 1508390) that write_bootloader has |
|---|---|---|---|
| 2 | byteswapping functions *_to_cpus() and cpu_to_*s() with their | 2 | some dead code, where we assign to 'p' and then in the following |
| 3 | not-in-place equivalents. This is useful for where the swapping | 3 | line assign to it again. This happened as a result of the |
| 4 | is done on members of a packed struct -- taking the address | 4 | refactoring in commit cd5066f8618b. |
| 5 | of the member to pass it to an inplace function is undefined | 5 | |
| 6 | behaviour in C. | 6 | Fix the dead code by removing the 'void *v' variable entirely and |
| 7 | instead adding a cast when calling bl_setup_gt64120_jump_kernel(), as | ||
| 8 | we do at its other callsite in write_bootloader_nanomips(). | ||
| 7 | 9 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Reviewed-by: Eric Blake <eblake@redhat.com> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Message-id: 20181009181612.10633-1-peter.maydell@linaro.org | ||
| 12 | --- | 12 | --- |
| 13 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++++++++++++++ | 13 | hw/mips/malta.c | 5 +---- |
| 14 | 1 file changed, 65 insertions(+) | 14 | 1 file changed, 1 insertion(+), 4 deletions(-) |
| 15 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 16 | 15 | ||
| 17 | diff --git a/scripts/coccinelle/inplace-byteswaps.cocci b/scripts/coccinelle/inplace-byteswaps.cocci | 16 | diff --git a/hw/mips/malta.c b/hw/mips/malta.c |
| 18 | new file mode 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 19 | index XXXXXXX..XXXXXXX | 18 | --- a/hw/mips/malta.c |
| 20 | --- /dev/null | 19 | +++ b/hw/mips/malta.c |
| 21 | +++ b/scripts/coccinelle/inplace-byteswaps.cocci | 20 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, |
| 22 | @@ -XXX,XX +XXX,XX @@ | 21 | uint64_t kernel_entry) |
| 23 | +// Replace uses of in-place byteswapping functions with calls to the | 22 | { |
| 24 | +// equivalent not-in-place functions. This is necessary to avoid | 23 | uint32_t *p; |
| 25 | +// undefined behaviour if the expression being swapped is a field in a | 24 | - void *v; |
| 26 | +// packed struct. | 25 | |
| 27 | + | 26 | /* Small bootloader */ |
| 28 | +@@ | 27 | p = (uint32_t *)base; |
| 29 | +expression E; | 28 | @@ -XXX,XX +XXX,XX @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, |
| 30 | +@@ | 29 | * |
| 31 | +-be16_to_cpus(&E); | 30 | */ |
| 32 | ++E = be16_to_cpu(E); | 31 | |
| 33 | +@@ | 32 | - v = p; |
| 34 | +expression E; | 33 | - bl_setup_gt64120_jump_kernel(&v, run_addr, kernel_entry); |
| 35 | +@@ | 34 | - p = v; |
| 36 | +-be32_to_cpus(&E); | 35 | + bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry); |
| 37 | ++E = be32_to_cpu(E); | 36 | |
| 38 | +@@ | 37 | /* YAMON subroutines */ |
| 39 | +expression E; | 38 | p = (uint32_t *) (base + 0x800); |
| 40 | +@@ | ||
| 41 | +-be64_to_cpus(&E); | ||
| 42 | ++E = be64_to_cpu(E); | ||
| 43 | +@@ | ||
| 44 | +expression E; | ||
| 45 | +@@ | ||
| 46 | +-cpu_to_be16s(&E); | ||
| 47 | ++E = cpu_to_be16(E); | ||
| 48 | +@@ | ||
| 49 | +expression E; | ||
| 50 | +@@ | ||
| 51 | +-cpu_to_be32s(&E); | ||
| 52 | ++E = cpu_to_be32(E); | ||
| 53 | +@@ | ||
| 54 | +expression E; | ||
| 55 | +@@ | ||
| 56 | +-cpu_to_be64s(&E); | ||
| 57 | ++E = cpu_to_be64(E); | ||
| 58 | +@@ | ||
| 59 | +expression E; | ||
| 60 | +@@ | ||
| 61 | +-le16_to_cpus(&E); | ||
| 62 | ++E = le16_to_cpu(E); | ||
| 63 | +@@ | ||
| 64 | +expression E; | ||
| 65 | +@@ | ||
| 66 | +-le32_to_cpus(&E); | ||
| 67 | ++E = le32_to_cpu(E); | ||
| 68 | +@@ | ||
| 69 | +expression E; | ||
| 70 | +@@ | ||
| 71 | +-le64_to_cpus(&E); | ||
| 72 | ++E = le64_to_cpu(E); | ||
| 73 | +@@ | ||
| 74 | +expression E; | ||
| 75 | +@@ | ||
| 76 | +-cpu_to_le16s(&E); | ||
| 77 | ++E = cpu_to_le16(E); | ||
| 78 | +@@ | ||
| 79 | +expression E; | ||
| 80 | +@@ | ||
| 81 | +-cpu_to_le32s(&E); | ||
| 82 | ++E = cpu_to_le32(E); | ||
| 83 | +@@ | ||
| 84 | +expression E; | ||
| 85 | +@@ | ||
| 86 | +-cpu_to_le64s(&E); | ||
| 87 | ++E = cpu_to_le64(E); | ||
| 88 | -- | 39 | -- |
| 89 | 2.19.0 | 40 | 2.34.1 |
| 90 | 41 | ||
| 91 | 42 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for selecting the Memory Region that the GEM | 3 | Semihosting has been made a 'default y' entry in Kconfig, which does |
| 4 | will do DMA to. | 4 | not work because when building --without-default-devices, the |
| 5 | semihosting code would not be available. | ||
| 5 | 6 | ||
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 7 | Make semihosting unconditional when TCG is present. |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | |
| 8 | Message-id: 20181011021931.4249-7-edgar.iglesias@gmail.com | 9 | Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only build") |
| 10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20230508181611.2621-2-farosas@suse.de | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 14 | --- |
| 11 | include/hw/net/cadence_gem.h | 2 ++ | 15 | target/arm/Kconfig | 8 +------- |
| 12 | hw/net/cadence_gem.c | 59 ++++++++++++++++++++++-------------- | 16 | 1 file changed, 1 insertion(+), 7 deletions(-) |
| 13 | 2 files changed, 39 insertions(+), 22 deletions(-) | ||
| 14 | 17 | ||
| 15 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | 18 | diff --git a/target/arm/Kconfig b/target/arm/Kconfig |
| 16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/include/hw/net/cadence_gem.h | 20 | --- a/target/arm/Kconfig |
| 18 | +++ b/include/hw/net/cadence_gem.h | 21 | +++ b/target/arm/Kconfig |
| 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState { | ||
| 20 | |||
| 21 | /*< public >*/ | ||
| 22 | MemoryRegion iomem; | ||
| 23 | + MemoryRegion *dma_mr; | ||
| 24 | + AddressSpace dma_as; | ||
| 25 | NICState *nic; | ||
| 26 | NICConf conf; | ||
| 27 | qemu_irq irq[MAX_PRIORITY_QUEUES]; | ||
| 28 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/net/cadence_gem.c | ||
| 31 | +++ b/hw/net/cadence_gem.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
| 33 | #include "hw/net/cadence_gem.h" | 23 | config ARM |
| 34 | #include "qapi/error.h" | 24 | bool |
| 35 | #include "qemu/log.h" | 25 | + select ARM_COMPATIBLE_SEMIHOSTING if TCG |
| 36 | +#include "sysemu/dma.h" | 26 | |
| 37 | #include "net/checksum.h" | 27 | config AARCH64 |
| 38 | 28 | bool | |
| 39 | #ifdef CADENCE_GEM_ERR_DEBUG | 29 | select ARM |
| 40 | @@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) | 30 | - |
| 41 | { | 31 | -# This config exists just so we can make SEMIHOSTING default when TCG |
| 42 | DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); | 32 | -# is selected without also changing it for other architectures. |
| 43 | /* read current descriptor */ | 33 | -config ARM_SEMIHOSTING |
| 44 | - cpu_physical_memory_read(s->rx_desc_addr[q], | 34 | - bool |
| 45 | - (uint8_t *)s->rx_desc[q], | 35 | - default y if TCG && ARM |
| 46 | - sizeof(uint32_t) * gem_get_desc_len(s, true)); | 36 | - select ARM_COMPATIBLE_SEMIHOSTING |
| 47 | + address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, | ||
| 48 | + (uint8_t *)s->rx_desc[q], | ||
| 49 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 50 | |||
| 51 | /* Descriptor owned by software ? */ | ||
| 52 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 54 | rx_desc_get_buffer(s->rx_desc[q])); | ||
| 55 | |||
| 56 | /* Copy packet data to emulated DMA buffer */ | ||
| 57 | - cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + | ||
| 58 | + address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + | ||
| 59 | rxbuf_offset, | ||
| 60 | - rxbuf_ptr, | ||
| 61 | - MIN(bytes_to_copy, rxbufsize)); | ||
| 62 | + MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, | ||
| 63 | + MIN(bytes_to_copy, rxbufsize)); | ||
| 64 | rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); | ||
| 65 | bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); | ||
| 66 | |||
| 67 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 68 | } | ||
| 69 | |||
| 70 | /* Descriptor write-back. */ | ||
| 71 | - cpu_physical_memory_write(s->rx_desc_addr[q], | ||
| 72 | - (uint8_t *)s->rx_desc[q], | ||
| 73 | - sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 74 | + address_space_write(&s->dma_as, s->rx_desc_addr[q], | ||
| 75 | + MEMTXATTRS_UNSPECIFIED, | ||
| 76 | + (uint8_t *)s->rx_desc[q], | ||
| 77 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 78 | |||
| 79 | /* Next descriptor */ | ||
| 80 | if (rx_desc_get_wrap(s->rx_desc[q])) { | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 82 | packet_desc_addr = s->tx_desc_addr[q]; | ||
| 83 | |||
| 84 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 85 | - cpu_physical_memory_read(packet_desc_addr, | ||
| 86 | - (uint8_t *)desc, | ||
| 87 | - sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 88 | + address_space_read(&s->dma_as, packet_desc_addr, | ||
| 89 | + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, | ||
| 90 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 91 | /* Handle all descriptors owned by hardware */ | ||
| 92 | while (tx_desc_get_used(desc) == 0) { | ||
| 93 | |||
| 94 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 95 | /* Gather this fragment of the packet from "dma memory" to our | ||
| 96 | * contig buffer. | ||
| 97 | */ | ||
| 98 | - cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, | ||
| 99 | - tx_desc_get_length(desc)); | ||
| 100 | + address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), | ||
| 101 | + MEMTXATTRS_UNSPECIFIED, | ||
| 102 | + p, tx_desc_get_length(desc)); | ||
| 103 | p += tx_desc_get_length(desc); | ||
| 104 | total_bytes += tx_desc_get_length(desc); | ||
| 105 | |||
| 106 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 107 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 108 | * the processor. | ||
| 109 | */ | ||
| 110 | - cpu_physical_memory_read(s->tx_desc_addr[q], | ||
| 111 | - (uint8_t *)desc_first, | ||
| 112 | - sizeof(desc_first)); | ||
| 113 | + address_space_read(&s->dma_as, s->tx_desc_addr[q], | ||
| 114 | + MEMTXATTRS_UNSPECIFIED, | ||
| 115 | + (uint8_t *)desc_first, | ||
| 116 | + sizeof(desc_first)); | ||
| 117 | tx_desc_set_used(desc_first); | ||
| 118 | - cpu_physical_memory_write(s->tx_desc_addr[q], | ||
| 119 | - (uint8_t *)desc_first, | ||
| 120 | - sizeof(desc_first)); | ||
| 121 | + address_space_write(&s->dma_as, s->tx_desc_addr[q], | ||
| 122 | + MEMTXATTRS_UNSPECIFIED, | ||
| 123 | + (uint8_t *)desc_first, | ||
| 124 | + sizeof(desc_first)); | ||
| 125 | /* Advance the hardware current descriptor past this packet */ | ||
| 126 | if (tx_desc_get_wrap(desc)) { | ||
| 127 | s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 129 | packet_desc_addr += 4 * gem_get_desc_len(s, false); | ||
| 130 | } | ||
| 131 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 132 | - cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, | ||
| 133 | - sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 134 | + address_space_read(&s->dma_as, packet_desc_addr, | ||
| 135 | + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, | ||
| 136 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 137 | } | ||
| 138 | |||
| 139 | if (tx_desc_get_used(desc)) { | ||
| 140 | @@ -XXX,XX +XXX,XX @@ static void gem_realize(DeviceState *dev, Error **errp) | ||
| 141 | CadenceGEMState *s = CADENCE_GEM(dev); | ||
| 142 | int i; | ||
| 143 | |||
| 144 | + address_space_init(&s->dma_as, | ||
| 145 | + s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); | ||
| 146 | + | ||
| 147 | if (s->num_priority_queues == 0 || | ||
| 148 | s->num_priority_queues > MAX_PRIORITY_QUEUES) { | ||
| 149 | error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, | ||
| 150 | @@ -XXX,XX +XXX,XX @@ static void gem_init(Object *obj) | ||
| 151 | "enet", sizeof(s->regs)); | ||
| 152 | |||
| 153 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); | ||
| 154 | + | ||
| 155 | + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, | ||
| 156 | + (Object **)&s->dma_mr, | ||
| 157 | + qdev_prop_allow_set_link_before_realize, | ||
| 158 | + OBJ_PROP_LINK_STRONG, | ||
| 159 | + &error_abort); | ||
| 160 | } | ||
| 161 | |||
| 162 | static const VMStateDescription vmstate_cadence_gem = { | ||
| 163 | -- | 37 | -- |
| 164 | 2.19.0 | 38 | 2.34.1 |
| 165 | |||
| 166 | diff view generated by jsdifflib |
| 1 | From: Aaron Lindsay <aclindsa@gmail.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | This is an amendment to my earlier patch: | 3 | We cannot allow this config to be disabled at the moment as not all of |
| 4 | commit 7ece99b17e832065236c07a158dfac62619ef99b | 4 | the relevant code is protected by it. |
| 5 | Author: Aaron Lindsay <alindsay@codeaurora.org> | ||
| 6 | Date: Thu Apr 26 11:04:39 2018 +0100 | ||
| 7 | 5 | ||
| 8 | target/arm: Mask PMU register writes based on PMCR_EL0.N | 6 | Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a |
| 7 | KVM-only build") moved the CONFIGs of several boards to Kconfig, so it | ||
| 8 | is now possible that nothing selects ARM_V7M (e.g. when doing a | ||
| 9 | --without-default-devices build). | ||
| 9 | 10 | ||
| 10 | Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> | 11 | Return the CONFIG_ARM_V7M entry to a state where it is always selected |
| 12 | whenever TCG is available. | ||
| 13 | |||
| 14 | Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-only build") | ||
| 15 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 12 | Message-id: 20181010203735.27918-3-aclindsa@gmail.com | 17 | Message-id: 20230508181611.2621-3-farosas@suse.de |
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 14 | --- | 19 | --- |
| 15 | target/arm/helper.c | 1 + | 20 | target/arm/Kconfig | 1 + |
| 16 | 1 file changed, 1 insertion(+) | 21 | 1 file changed, 1 insertion(+) |
| 17 | 22 | ||
| 18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 23 | diff --git a/target/arm/Kconfig b/target/arm/Kconfig |
| 19 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/target/arm/helper.c | 25 | --- a/target/arm/Kconfig |
| 21 | +++ b/target/arm/helper.c | 26 | +++ b/target/arm/Kconfig |
| 22 | @@ -XXX,XX +XXX,XX @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 27 | @@ -XXX,XX +XXX,XX @@ |
| 23 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, | 28 | config ARM |
| 24 | uint64_t value) | 29 | bool |
| 25 | { | 30 | select ARM_COMPATIBLE_SEMIHOSTING if TCG |
| 26 | + value &= pmu_counter_mask(env); | 31 | + select ARM_V7M if TCG |
| 27 | env->cp15.c9_pmovsr &= ~value; | 32 | |
| 28 | } | 33 | config AARCH64 |
| 29 | 34 | bool | |
| 30 | -- | 35 | -- |
| 31 | 2.19.0 | 36 | 2.34.1 |
| 32 | |||
| 33 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for extended descriptors with optional 64bit | 3 | On a build configured with: --disable-tcg --enable-xen it is possible |
| 4 | addressing and timestamping. QEMU will not yet provide | 4 | to produce a QEMU binary with no TCG nor KVM support. Skip the cdrom |
| 5 | timestamps (always leaving the valid timestamp bit as zero). | 5 | boot tests if that's the case. |
| 6 | 6 | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present") |
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 9 | Message-id: 20181011021931.4249-6-edgar.iglesias@gmail.com | 9 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
| 10 | Message-id: 20230508181611.2621-4-farosas@suse.de | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 12 | --- |
| 12 | include/hw/net/cadence_gem.h | 2 +- | 13 | tests/qtest/cdrom-test.c | 10 ++++++++++ |
| 13 | hw/net/cadence_gem.c | 69 ++++++++++++++++++++++++++---------- | 14 | 1 file changed, 10 insertions(+) |
| 14 | 2 files changed, 52 insertions(+), 19 deletions(-) | ||
| 15 | 15 | ||
| 16 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | 16 | diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/net/cadence_gem.h | 18 | --- a/tests/qtest/cdrom-test.c |
| 19 | +++ b/include/hw/net/cadence_gem.h | 19 | +++ b/tests/qtest/cdrom-test.c |
| 20 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ static void test_cdboot(gconstpointer data) |
| 21 | #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ | 21 | |
| 22 | 22 | static void add_x86_tests(void) | |
| 23 | /* Max number of words in a DMA descriptor. */ | ||
| 24 | -#define DESC_MAX_NUM_WORDS 2 | ||
| 25 | +#define DESC_MAX_NUM_WORDS 6 | ||
| 26 | |||
| 27 | #define MAX_PRIORITY_QUEUES 8 | ||
| 28 | #define MAX_TYPE1_SCREENERS 16 | ||
| 29 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/hw/net/cadence_gem.c | ||
| 32 | +++ b/hw/net/cadence_gem.c | ||
| 33 | @@ -XXX,XX +XXX,XX @@ | ||
| 34 | #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ | ||
| 35 | #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ | ||
| 36 | |||
| 37 | +#define GEM_DMACFG_ADDR_64B (1U << 30) | ||
| 38 | +#define GEM_DMACFG_TX_BD_EXT (1U << 29) | ||
| 39 | +#define GEM_DMACFG_RX_BD_EXT (1U << 28) | ||
| 40 | #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ | ||
| 41 | #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ | ||
| 42 | #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ | ||
| 43 | @@ -XXX,XX +XXX,XX @@ | ||
| 44 | |||
| 45 | #define GEM_MODID_VALUE 0x00020118 | ||
| 46 | |||
| 47 | -static inline unsigned tx_desc_get_buffer(uint32_t *desc) | ||
| 48 | +static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) | ||
| 49 | { | 23 | { |
| 50 | - return desc[0]; | 24 | + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) { |
| 51 | + uint64_t ret = desc[0]; | 25 | + g_test_skip("No KVM or TCG accelerator available, skipping boot tests"); |
| 52 | + | 26 | + return; |
| 53 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 54 | + ret |= (uint64_t)desc[2] << 32; | ||
| 55 | + } | ||
| 56 | + return ret; | ||
| 57 | } | ||
| 58 | |||
| 59 | static inline unsigned tx_desc_get_used(uint32_t *desc) | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) | ||
| 61 | DB_PRINT("length: %d\n", tx_desc_get_length(desc)); | ||
| 62 | } | ||
| 63 | |||
| 64 | -static inline unsigned rx_desc_get_buffer(uint32_t *desc) | ||
| 65 | +static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) | ||
| 66 | { | ||
| 67 | - return desc[0] & ~0x3UL; | ||
| 68 | + uint64_t ret = desc[0] & ~0x3UL; | ||
| 69 | + | ||
| 70 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 71 | + ret |= (uint64_t)desc[2] << 32; | ||
| 72 | + } | ||
| 73 | + return ret; | ||
| 74 | +} | ||
| 75 | + | ||
| 76 | +static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) | ||
| 77 | +{ | ||
| 78 | + int ret = 2; | ||
| 79 | + | ||
| 80 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 81 | + ret += 2; | ||
| 82 | + } | ||
| 83 | + if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT | ||
| 84 | + : GEM_DMACFG_TX_BD_EXT)) { | ||
| 85 | + ret += 2; | ||
| 86 | + } | 27 | + } |
| 87 | + | 28 | + |
| 88 | + assert(ret <= DESC_MAX_NUM_WORDS); | 29 | qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot); |
| 89 | + return ret; | 30 | qtest_add_data_func("cdrom/boot/virtio-scsi", |
| 90 | } | 31 | "-device virtio-scsi -device scsi-cd,drive=cdr " |
| 91 | 32 | @@ -XXX,XX +XXX,XX @@ static void add_x86_tests(void) | |
| 92 | static inline unsigned rx_desc_get_wrap(uint32_t *desc) | 33 | |
| 93 | @@ -XXX,XX +XXX,XX @@ static void gem_init_register_masks(CadenceGEMState *s) | 34 | static void add_s390x_tests(void) |
| 94 | memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); | 35 | { |
| 95 | s->regs_ro[GEM_NWCTRL] = 0xFFF80000; | 36 | + if (!qtest_has_accel("tcg") && !qtest_has_accel("kvm")) { |
| 96 | s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; | 37 | + g_test_skip("No KVM or TCG accelerator available, skipping boot tests"); |
| 97 | - s->regs_ro[GEM_DMACFG] = 0xFE00F000; | 38 | + return; |
| 98 | + s->regs_ro[GEM_DMACFG] = 0x8E00F000; | 39 | + } |
| 99 | s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; | 40 | + |
| 100 | s->regs_ro[GEM_RXQBASE] = 0x00000003; | 41 | qtest_add_data_func("cdrom/boot/default", "-cdrom ", test_cdboot); |
| 101 | s->regs_ro[GEM_TXQBASE] = 0x00000003; | 42 | qtest_add_data_func("cdrom/boot/virtio-scsi", |
| 102 | @@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) | 43 | "-device virtio-scsi -device scsi-cd,drive=cdr " |
| 103 | DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); | ||
| 104 | /* read current descriptor */ | ||
| 105 | cpu_physical_memory_read(s->rx_desc_addr[q], | ||
| 106 | - (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q])); | ||
| 107 | + (uint8_t *)s->rx_desc[q], | ||
| 108 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 109 | |||
| 110 | /* Descriptor owned by software ? */ | ||
| 111 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { | ||
| 112 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 113 | rx_desc_get_buffer(s->rx_desc[q])); | ||
| 114 | |||
| 115 | /* Copy packet data to emulated DMA buffer */ | ||
| 116 | - cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + | ||
| 117 | - rxbuf_offset, | ||
| 118 | - rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); | ||
| 119 | + cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + | ||
| 120 | + rxbuf_offset, | ||
| 121 | + rxbuf_ptr, | ||
| 122 | + MIN(bytes_to_copy, rxbufsize)); | ||
| 123 | rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); | ||
| 124 | bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); | ||
| 125 | |||
| 126 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 127 | /* Descriptor write-back. */ | ||
| 128 | cpu_physical_memory_write(s->rx_desc_addr[q], | ||
| 129 | (uint8_t *)s->rx_desc[q], | ||
| 130 | - sizeof(s->rx_desc[q])); | ||
| 131 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 132 | |||
| 133 | /* Next descriptor */ | ||
| 134 | if (rx_desc_get_wrap(s->rx_desc[q])) { | ||
| 135 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 136 | s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; | ||
| 137 | } else { | ||
| 138 | DB_PRINT("incrementing RX descriptor list\n"); | ||
| 139 | - s->rx_desc_addr[q] += 8; | ||
| 140 | + s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); | ||
| 141 | } | ||
| 142 | |||
| 143 | gem_get_rx_desc(s, q); | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 145 | |||
| 146 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 147 | cpu_physical_memory_read(packet_desc_addr, | ||
| 148 | - (uint8_t *)desc, sizeof(desc)); | ||
| 149 | + (uint8_t *)desc, | ||
| 150 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 151 | /* Handle all descriptors owned by hardware */ | ||
| 152 | while (tx_desc_get_used(desc) == 0) { | ||
| 153 | |||
| 154 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 155 | /* The real hardware would eat this (and possibly crash). | ||
| 156 | * For QEMU let's lend a helping hand. | ||
| 157 | */ | ||
| 158 | - if ((tx_desc_get_buffer(desc) == 0) || | ||
| 159 | + if ((tx_desc_get_buffer(s, desc) == 0) || | ||
| 160 | (tx_desc_get_length(desc) == 0)) { | ||
| 161 | DB_PRINT("Invalid TX descriptor @ 0x%x\n", | ||
| 162 | (unsigned)packet_desc_addr); | ||
| 163 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 164 | /* Gather this fragment of the packet from "dma memory" to our | ||
| 165 | * contig buffer. | ||
| 166 | */ | ||
| 167 | - cpu_physical_memory_read(tx_desc_get_buffer(desc), p, | ||
| 168 | + cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, | ||
| 169 | tx_desc_get_length(desc)); | ||
| 170 | p += tx_desc_get_length(desc); | ||
| 171 | total_bytes += tx_desc_get_length(desc); | ||
| 172 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 173 | if (tx_desc_get_wrap(desc)) { | ||
| 174 | s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; | ||
| 175 | } else { | ||
| 176 | - s->tx_desc_addr[q] = packet_desc_addr + 8; | ||
| 177 | + s->tx_desc_addr[q] = packet_desc_addr + | ||
| 178 | + 4 * gem_get_desc_len(s, false); | ||
| 179 | } | ||
| 180 | DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); | ||
| 181 | |||
| 182 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 183 | tx_desc_set_last(desc); | ||
| 184 | packet_desc_addr = s->regs[GEM_TXQBASE]; | ||
| 185 | } else { | ||
| 186 | - packet_desc_addr += 8; | ||
| 187 | + packet_desc_addr += 4 * gem_get_desc_len(s, false); | ||
| 188 | } | ||
| 189 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 190 | - cpu_physical_memory_read(packet_desc_addr, | ||
| 191 | - (uint8_t *)desc, sizeof(desc)); | ||
| 192 | + cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, | ||
| 193 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 194 | } | ||
| 195 | |||
| 196 | if (tx_desc_get_used(desc)) { | ||
| 197 | -- | 44 | -- |
| 198 | 2.19.0 | 45 | 2.34.1 |
| 199 | |||
| 200 | diff view generated by jsdifflib |
| 1 | From: Aaron Lindsay <aclindsa@gmail.com> | 1 | In check_s2_mmu_setup() we have a check that is attempting to |
|---|---|---|---|
| 2 | implement the part of AArch64.S2MinTxSZ that is specific to when EL1 | ||
| 3 | is AArch32: | ||
| 2 | 4 | ||
| 3 | I previously fixed this for PMINTENSET_EL1, but missed these. | 5 | if !s1aarch64 then |
| 6 | // EL1 is AArch32 | ||
| 7 | min_txsz = Min(min_txsz, 24); | ||
| 4 | 8 | ||
| 5 | Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> | 9 | Unfortunately we got this wrong in two ways: |
| 6 | Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> | 10 | |
| 11 | (1) The minimum txsz corresponds to a maximum inputsize, but we got | ||
| 12 | the sense of the comparison wrong and were faulting for all | ||
| 13 | inputsizes less than 40 bits | ||
| 14 | |||
| 15 | (2) We try to implement this as an extra check that happens after | ||
| 16 | we've done the same txsz checks we would do for an AArch64 EL1, but | ||
| 17 | in fact the pseudocode is *loosening* the requirements, so that txsz | ||
| 18 | values that would fault for an AArch64 EL1 do not fault for AArch32 | ||
| 19 | EL1, because it does Min(old_min, 24), not Max(old_min, 24). | ||
| 20 | |||
| 21 | You can see this also in the text of the Arm ARM in table D8-8, which | ||
| 22 | shows that where the implemented PA size is less than 40 bits an | ||
| 23 | AArch32 EL1 is still OK with a configured stage2 T0SZ for a 40 bit | ||
| 24 | IPA, whereas if EL1 is AArch64 then the T0SZ must be big enough to | ||
| 25 | constrain the IPA to the implemented PA size. | ||
| 26 | |||
| 27 | Because of part (2), we can't do this as a separate check, but | ||
| 28 | have to integrate it into aa64_va_parameters(). Add a new argument | ||
| 29 | to that function to indicate that EL1 is 32-bit. All the existing | ||
| 30 | callsites except the one in get_phys_addr_lpae() can pass 'false', | ||
| 31 | because they are either doing a lookup for a stage 1 regime or | ||
| 32 | else they don't care about the tsz/tsz_oob fields. | ||
| 33 | |||
| 34 | Cc: qemu-stable@nongnu.org | ||
| 35 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1627 | ||
| 36 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 37 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20181010203735.27918-2-aclindsa@gmail.com | 38 | Message-id: 20230509092059.3176487-1-peter.maydell@linaro.org |
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | 39 | --- |
| 11 | target/arm/helper.c | 6 ++++-- | 40 | target/arm/internals.h | 12 +++++++++++- |
| 12 | 1 file changed, 4 insertions(+), 2 deletions(-) | 41 | target/arm/gdbstub64.c | 2 +- |
| 42 | target/arm/helper.c | 15 +++++++++++++-- | ||
| 43 | target/arm/ptw.c | 14 ++------------ | ||
| 44 | target/arm/tcg/pauth_helper.c | 6 +++--- | ||
| 45 | 5 files changed, 30 insertions(+), 19 deletions(-) | ||
| 13 | 46 | ||
| 47 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
| 48 | index XXXXXXX..XXXXXXX 100644 | ||
| 49 | --- a/target/arm/internals.h | ||
| 50 | +++ b/target/arm/internals.h | ||
| 51 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { | ||
| 52 | ARMGranuleSize gran : 2; | ||
| 53 | } ARMVAParameters; | ||
| 54 | |||
| 55 | +/** | ||
| 56 | + * aa64_va_parameters: Return parameters for an AArch64 virtual address | ||
| 57 | + * @env: CPU | ||
| 58 | + * @va: virtual address to look up | ||
| 59 | + * @mmu_idx: determines translation regime to use | ||
| 60 | + * @data: true if this is a data access | ||
| 61 | + * @el1_is_aa32: true if we are asking about stage 2 when EL1 is AArch32 | ||
| 62 | + * (ignored if @mmu_idx is for a stage 1 regime; only affects tsz/tsz_oob) | ||
| 63 | + */ | ||
| 64 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
| 65 | - ARMMMUIdx mmu_idx, bool data); | ||
| 66 | + ARMMMUIdx mmu_idx, bool data, | ||
| 67 | + bool el1_is_aa32); | ||
| 68 | |||
| 69 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
| 70 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); | ||
| 71 | diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c | ||
| 72 | index XXXXXXX..XXXXXXX 100644 | ||
| 73 | --- a/target/arm/gdbstub64.c | ||
| 74 | +++ b/target/arm/gdbstub64.c | ||
| 75 | @@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) | ||
| 76 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
| 77 | ARMVAParameters param; | ||
| 78 | |||
| 79 | - param = aa64_va_parameters(env, -is_high, mmu_idx, is_data); | ||
| 80 | + param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false); | ||
| 81 | return gdb_get_reg64(buf, pauth_ptr_mask(param)); | ||
| 82 | } | ||
| 83 | default: | ||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 84 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 85 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/helper.c | 86 | --- a/target/arm/helper.c |
| 17 | +++ b/target/arm/helper.c | 87 | +++ b/target/arm/helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | 88 | @@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, |
| 19 | .writefn = pmintenset_write, .raw_writefn = raw_write, | 89 | unsigned int page_size_granule, page_shift, num, scale, exponent; |
| 20 | .resetvalue = 0x0 }, | 90 | /* Extract one bit to represent the va selector in use. */ |
| 21 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, | 91 | uint64_t select = sextract64(value, 36, 1); |
| 22 | - .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, | 92 | - ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true); |
| 23 | + .access = PL1_RW, .accessfn = access_tpm, | 93 | + ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true, false); |
| 24 | + .type = ARM_CP_ALIAS | ARM_CP_IO, | 94 | TLBIRange ret = { }; |
| 25 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | 95 | ARMGranuleSize gran; |
| 26 | .writefn = pmintenclr_write, }, | 96 | |
| 27 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, | 97 | @@ -XXX,XX +XXX,XX @@ static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran, |
| 28 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | 98 | } |
| 29 | - .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, | 99 | |
| 30 | + .access = PL1_RW, .accessfn = access_tpm, | 100 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
| 31 | + .type = ARM_CP_ALIAS | ARM_CP_IO, | 101 | - ARMMMUIdx mmu_idx, bool data) |
| 32 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | 102 | + ARMMMUIdx mmu_idx, bool data, |
| 33 | .writefn = pmintenclr_write }, | 103 | + bool el1_is_aa32) |
| 34 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, | 104 | { |
| 105 | uint64_t tcr = regime_tcr(env, mmu_idx); | ||
| 106 | bool epd, hpd, tsz_oob, ds, ha, hd; | ||
| 107 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
| 108 | } | ||
| 109 | } | ||
| 110 | |||
| 111 | + if (stage2 && el1_is_aa32) { | ||
| 112 | + /* | ||
| 113 | + * For AArch32 EL1 the min txsz (and thus max IPA size) requirements | ||
| 114 | + * are loosened: a configured IPA of 40 bits is permitted even if | ||
| 115 | + * the implemented PA is less than that (and so a 40 bit IPA would | ||
| 116 | + * fault for an AArch64 EL1). See R_DTLMN. | ||
| 117 | + */ | ||
| 118 | + min_tsz = MIN(min_tsz, 24); | ||
| 119 | + } | ||
| 120 | + | ||
| 121 | if (tsz > max_tsz) { | ||
| 122 | tsz = max_tsz; | ||
| 123 | tsz_oob = true; | ||
| 124 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c | ||
| 125 | index XXXXXXX..XXXXXXX 100644 | ||
| 126 | --- a/target/arm/ptw.c | ||
| 127 | +++ b/target/arm/ptw.c | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, | ||
| 129 | |||
| 130 | sl0 = extract32(tcr, 6, 2); | ||
| 131 | if (is_aa64) { | ||
| 132 | - /* | ||
| 133 | - * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of | ||
| 134 | - * get_phys_addr_lpae, that used aa64_va_parameters which apply | ||
| 135 | - * to aarch64. If Stage1 is aarch32, the min_txsz is larger. | ||
| 136 | - * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to | ||
| 137 | - * inputsize is 64 - 24 = 40. | ||
| 138 | - */ | ||
| 139 | - if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) { | ||
| 140 | - goto fail; | ||
| 141 | - } | ||
| 142 | - | ||
| 143 | /* | ||
| 144 | * AArch64.S2InvalidSL: Interpretation of SL depends on the page size, | ||
| 145 | * so interleave AArch64.S2StartLevel. | ||
| 146 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, | ||
| 147 | int ps; | ||
| 148 | |||
| 149 | param = aa64_va_parameters(env, address, mmu_idx, | ||
| 150 | - access_type != MMU_INST_FETCH); | ||
| 151 | + access_type != MMU_INST_FETCH, | ||
| 152 | + !arm_el_is_aa64(env, 1)); | ||
| 153 | level = 0; | ||
| 154 | |||
| 155 | /* | ||
| 156 | diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c | ||
| 157 | index XXXXXXX..XXXXXXX 100644 | ||
| 158 | --- a/target/arm/tcg/pauth_helper.c | ||
| 159 | +++ b/target/arm/tcg/pauth_helper.c | ||
| 160 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
| 161 | ARMPACKey *key, bool data) | ||
| 162 | { | ||
| 163 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
| 164 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
| 165 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); | ||
| 166 | uint64_t pac, ext_ptr, ext, test; | ||
| 167 | int bot_bit, top_bit; | ||
| 168 | |||
| 169 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
| 170 | ARMPACKey *key, bool data, int keynumber) | ||
| 171 | { | ||
| 172 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
| 173 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
| 174 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); | ||
| 175 | int bot_bit, top_bit; | ||
| 176 | uint64_t pac, orig_ptr, test; | ||
| 177 | |||
| 178 | @@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, | ||
| 179 | static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data) | ||
| 180 | { | ||
| 181 | ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); | ||
| 182 | - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); | ||
| 183 | + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); | ||
| 184 | |||
| 185 | return pauth_original_ptr(ptr, param); | ||
| 186 | } | ||
| 35 | -- | 187 | -- |
| 36 | 2.19.0 | 188 | 2.34.1 |
| 37 | |||
| 38 | diff view generated by jsdifflib |