| 1 | Latest set of arm patches. I may end up doing another pullreq at the | 1 | v2: added Property array terminator (which caused crashes on |
|---|---|---|---|
| 2 | end of the week, but this is big enough to send out, plus it has | 2 | various non-x86 host architectures). |
| 3 | several instances of "let me take the first N patches in your series" | ||
| 4 | in it, so getting those into master makes patch respins for those | ||
| 5 | submitters easier. | ||
| 6 | 3 | ||
| 7 | thanks | 4 | The following changes since commit ae3aa5da96f4ccf0c2a28851449d92db9fcfad71: |
| 8 | -- PMM | ||
| 9 | 5 | ||
| 10 | The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f: | 6 | Merge remote-tracking branch 'remotes/berrange/tags/socket-next-pull-request' into staging (2020-05-21 16:47:28 +0100) |
| 11 | |||
| 12 | Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100) | ||
| 13 | 7 | ||
| 14 | are available in the Git repository at: | 8 | are available in the Git repository at: |
| 15 | 9 | ||
| 16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016 | 10 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200521-1 |
| 17 | 11 | ||
| 18 | for you to fetch changes up to bdaffef4bb0729a74c7a325dba5c61d8cd8f464f: | 12 | for you to fetch changes up to fafe7229272f39500c14845bc7ea60a8504a5a20: |
| 19 | 13 | ||
| 20 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 16:16:42 +0100) | 14 | linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 (2020-05-21 22:05:27 +0100) |
| 21 | 15 | ||
| 22 | ---------------------------------------------------------------- | 16 | ---------------------------------------------------------------- |
| 23 | target-arm queue: | 17 | target-arm queue: |
| 24 | * hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 18 | * tests/acceptance: Add a test for the canon-a1100 machine |
| 25 | * target/arm: Fix aarch64_sve_change_el wrt EL0 | 19 | * docs/system: Document some of the Arm development boards |
| 26 | * target/arm: Define fields of ISAR registers | 20 | * linux-user: make BKPT insn cause SIGTRAP, not be a syscall |
| 27 | * target/arm: Align cortex-r5 id_isar0 | 21 | * target/arm: Remove unused GEN_NEON_INTEGER_OP macro |
| 28 | * target/arm: Fix cortex-a7 id_isar0 | 22 | * fsl-imx25, fsl-imx31, fsl-imx6, fsl-imx6ul, fsl-imx7: implement watchdog |
| 29 | * net/cadence_gem: Fix various bugs, add support for new | 23 | * hw/arm: Use qemu_log_mask() instead of hw_error() in various places |
| 30 | features that will be used by the Xilinx Versal board | 24 | * ARM: PL061: Introduce N_GPIOS |
| 31 | * target-arm: powerctl: Enable HVC when starting CPUs to EL2 | 25 | * target/arm: Improve clear_vec_high() usage |
| 32 | * target/arm: Add the Cortex-A72 | 26 | * target/arm: Allow user-mode code to write CPSR.E via MSR |
| 33 | * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 27 | * linux-user/arm: Reset CPSR_E when entering a signal handler |
| 34 | * target/arm: Mask PMOVSR writes based on supported counters | 28 | * linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 |
| 35 | * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | ||
| 36 | * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | ||
| 37 | 29 | ||
| 38 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
| 39 | Aaron Lindsay (2): | 31 | Amanieu d'Antras (1): |
| 40 | target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO | 32 | linux-user/arm: Reset CPSR_E when entering a signal handler |
| 41 | target/arm: Mask PMOVSR writes based on supported counters | ||
| 42 | 33 | ||
| 43 | Edgar E. Iglesias (10): | 34 | Geert Uytterhoeven (1): |
| 44 | net: cadence_gem: Disable TSU feature bit | 35 | ARM: PL061: Introduce N_GPIOS |
| 45 | net: cadence_gem: Announce availability of priority queues | ||
| 46 | net: cadence_gem: Use uint32_t for 32bit descriptor words | ||
| 47 | net: cadence_gem: Add macro with max number of descriptor words | ||
| 48 | net: cadence_gem: Add support for extended descriptors | ||
| 49 | net: cadence_gem: Add support for selecting the DMA MemoryRegion | ||
| 50 | net: cadence_gem: Implement support for 64bit descriptor addresses | ||
| 51 | net: cadence_gem: Announce 64bit addressing support | ||
| 52 | target-arm: powerctl: Enable HVC when starting CPUs to EL2 | ||
| 53 | target/arm: Add the Cortex-A72 | ||
| 54 | 36 | ||
| 55 | Jerome Forissier (1): | 37 | Guenter Roeck (8): |
| 56 | hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART | 38 | hw: Move i.MX watchdog driver to hw/watchdog |
| 39 | hw/watchdog: Implement full i.MX watchdog support | ||
| 40 | hw/arm/fsl-imx25: Wire up watchdog | ||
| 41 | hw/arm/fsl-imx31: Wire up watchdog | ||
| 42 | hw/arm/fsl-imx6: Connect watchdog interrupts | ||
| 43 | hw/arm/fsl-imx6ul: Connect watchdog interrupts | ||
| 44 | hw/arm/fsl-imx7: Instantiate various unimplemented devices | ||
| 45 | hw/arm/fsl-imx7: Connect watchdog interrupts | ||
| 57 | 46 | ||
| 58 | Peter Maydell (2): | 47 | Peter Maydell (12): |
| 59 | target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write | 48 | docs/system: Add 'Arm' to the Integrator/CP document title |
| 60 | coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls | 49 | docs/system: Sort Arm board index into alphabetical order |
| 50 | docs/system: Document Arm Versatile Express boards | ||
| 51 | docs/system: Document the various MPS2 models | ||
| 52 | docs/system: Document Musca boards | ||
| 53 | linux-user/arm: BKPT should cause SIGTRAP, not be a syscall | ||
| 54 | linux-user/arm: Remove bogus SVC 0xf0002 handling | ||
| 55 | linux-user/arm: Handle invalid arm-specific syscalls correctly | ||
| 56 | linux-user/arm: Fix identification of syscall numbers | ||
| 57 | target/arm: Remove unused GEN_NEON_INTEGER_OP macro | ||
| 58 | target/arm: Allow user-mode code to write CPSR.E via MSR | ||
| 59 | linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 | ||
| 61 | 60 | ||
| 62 | Richard Henderson (4): | 61 | Philippe Mathieu-Daudé (4): |
| 63 | target/arm: Fix aarch64_sve_change_el wrt EL0 | 62 | hw/arm/integratorcp: Replace hw_error() by qemu_log_mask() |
| 64 | target/arm: Define fields of ISAR registers | 63 | hw/arm/pxa2xx: Replace hw_error() by qemu_log_mask() |
| 65 | target/arm: Align cortex-r5 id_isar0 | 64 | hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask() |
| 66 | target/arm: Fix cortex-a7 id_isar0 | 65 | hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask() |
| 67 | 66 | ||
| 68 | include/hw/net/cadence_gem.h | 7 +- | 67 | Richard Henderson (2): |
| 69 | target/arm/cpu.h | 95 +++++++++++++- | 68 | target/arm: Use tcg_gen_gvec_mov for clear_vec_high |
| 70 | hw/arm/virt.c | 4 + | 69 | target/arm: Use clear_vec_high more effectively |
| 71 | hw/net/cadence_gem.c | 192 +++++++++++++++++++++-------- | ||
| 72 | target/arm/arm-powerctl.c | 10 ++ | ||
| 73 | target/arm/cpu.c | 7 +- | ||
| 74 | target/arm/cpu64.c | 66 +++++++++- | ||
| 75 | target/arm/helper.c | 27 ++-- | ||
| 76 | target/arm/op_helper.c | 6 +- | ||
| 77 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++ | ||
| 78 | 10 files changed, 408 insertions(+), 71 deletions(-) | ||
| 79 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 80 | 70 | ||
| 71 | Thomas Huth (1): | ||
| 72 | tests/acceptance: Add a test for the canon-a1100 machine | ||
| 73 | |||
| 74 | docs/system/arm/integratorcp.rst | 4 +- | ||
| 75 | docs/system/arm/mps2.rst | 29 +++ | ||
| 76 | docs/system/arm/musca.rst | 31 +++ | ||
| 77 | docs/system/arm/vexpress.rst | 60 ++++++ | ||
| 78 | docs/system/target-arm.rst | 20 +- | ||
| 79 | include/hw/arm/fsl-imx25.h | 5 + | ||
| 80 | include/hw/arm/fsl-imx31.h | 4 + | ||
| 81 | include/hw/arm/fsl-imx6.h | 2 +- | ||
| 82 | include/hw/arm/fsl-imx6ul.h | 2 +- | ||
| 83 | include/hw/arm/fsl-imx7.h | 23 ++- | ||
| 84 | include/hw/misc/imx2_wdt.h | 33 ---- | ||
| 85 | include/hw/watchdog/wdt_imx2.h | 90 +++++++++ | ||
| 86 | target/arm/cpu.h | 2 +- | ||
| 87 | hw/arm/fsl-imx25.c | 10 + | ||
| 88 | hw/arm/fsl-imx31.c | 6 + | ||
| 89 | hw/arm/fsl-imx6.c | 9 + | ||
| 90 | hw/arm/fsl-imx6ul.c | 10 + | ||
| 91 | hw/arm/fsl-imx7.c | 35 ++++ | ||
| 92 | hw/arm/integratorcp.c | 23 ++- | ||
| 93 | hw/arm/pxa2xx_gpio.c | 7 +- | ||
| 94 | hw/char/xilinx_uartlite.c | 5 +- | ||
| 95 | hw/display/pxa2xx_lcd.c | 8 +- | ||
| 96 | hw/dma/pxa2xx_dma.c | 14 +- | ||
| 97 | hw/gpio/pl061.c | 12 +- | ||
| 98 | hw/misc/imx2_wdt.c | 90 --------- | ||
| 99 | hw/timer/exynos4210_mct.c | 12 +- | ||
| 100 | hw/watchdog/wdt_imx2.c | 304 +++++++++++++++++++++++++++++ | ||
| 101 | linux-user/arm/cpu_loop.c | 145 ++++++++------ | ||
| 102 | linux-user/arm/signal.c | 15 +- | ||
| 103 | target/arm/translate-a64.c | 63 +++--- | ||
| 104 | target/arm/translate.c | 23 --- | ||
| 105 | MAINTAINERS | 6 + | ||
| 106 | hw/arm/Kconfig | 5 + | ||
| 107 | hw/misc/Makefile.objs | 1 - | ||
| 108 | hw/watchdog/Kconfig | 3 + | ||
| 109 | hw/watchdog/Makefile.objs | 1 + | ||
| 110 | tests/acceptance/machine_arm_canona1100.py | 35 ++++ | ||
| 111 | 37 files changed, 855 insertions(+), 292 deletions(-) | ||
| 112 | create mode 100644 docs/system/arm/mps2.rst | ||
| 113 | create mode 100644 docs/system/arm/musca.rst | ||
| 114 | create mode 100644 docs/system/arm/vexpress.rst | ||
| 115 | delete mode 100644 include/hw/misc/imx2_wdt.h | ||
| 116 | create mode 100644 include/hw/watchdog/wdt_imx2.h | ||
| 117 | delete mode 100644 hw/misc/imx2_wdt.c | ||
| 118 | create mode 100644 hw/watchdog/wdt_imx2.c | ||
| 119 | create mode 100644 tests/acceptance/machine_arm_canona1100.py | ||
| 120 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Jerome Forissier <jerome.forissier@linaro.org> | ||
| 2 | 1 | ||
| 3 | Bindings for /secure-chosen and /secure-chosen/stdout-path have been | ||
| 4 | proposed 1.5 years ago [1] and implemented in OP-TEE at the same time [2]. | ||
| 5 | They've now been officially agreed on, so we can implement them | ||
| 6 | in QEMU. | ||
| 7 | |||
| 8 | This patch creates the property when the machine is secure. | ||
| 9 | |||
| 10 | [1] https://patchwork.kernel.org/patch/9602401/ | ||
| 11 | [2] https://github.com/OP-TEE/optee_os/commit/4dc31c52544a | ||
| 12 | |||
| 13 | Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> | ||
| 14 | Message-id: 20181005080729.6480-1-jerome.forissier@linaro.org | ||
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | [PMM: commit message tweak] | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | --- | ||
| 19 | hw/arm/virt.c | 4 ++++ | ||
| 20 | 1 file changed, 4 insertions(+) | ||
| 21 | |||
| 22 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/hw/arm/virt.c | ||
| 25 | +++ b/hw/arm/virt.c | ||
| 26 | @@ -XXX,XX +XXX,XX @@ static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart, | ||
| 27 | /* Mark as not usable by the normal world */ | ||
| 28 | qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); | ||
| 29 | qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); | ||
| 30 | + | ||
| 31 | + qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); | ||
| 32 | + qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", | ||
| 33 | + nodename); | ||
| 34 | } | ||
| 35 | |||
| 36 | g_free(nodename); | ||
| 37 | -- | ||
| 38 | 2.19.0 | ||
| 39 | |||
| 40 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | At present we assert: | ||
| 4 | |||
| 5 | arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed. | ||
| 6 | |||
| 7 | The comment in arm_el_is_aa64 explains why asking about EL0 without | ||
| 8 | extra information is impossible. Add an extra argument to provide | ||
| 9 | it from the surrounding context. | ||
| 10 | |||
| 11 | Fixes: 0ab5953b00b3 | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20181008212205.17752-2-richard.henderson@linaro.org | ||
| 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | --- | ||
| 17 | target/arm/cpu.h | 7 +++++-- | ||
| 18 | target/arm/helper.c | 16 ++++++++++++---- | ||
| 19 | target/arm/op_helper.c | 6 +++++- | ||
| 20 | 3 files changed, 22 insertions(+), 7 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/target/arm/cpu.h | ||
| 25 | +++ b/target/arm/cpu.h | ||
| 26 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, | ||
| 27 | int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); | ||
| 28 | int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | ||
| 29 | void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); | ||
| 30 | -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el); | ||
| 31 | +void aarch64_sve_change_el(CPUARMState *env, int old_el, | ||
| 32 | + int new_el, bool el0_a64); | ||
| 33 | #else | ||
| 34 | static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } | ||
| 35 | -static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) { } | ||
| 36 | +static inline void aarch64_sve_change_el(CPUARMState *env, int o, | ||
| 37 | + int n, bool a) | ||
| 38 | +{ } | ||
| 39 | #endif | ||
| 40 | |||
| 41 | target_ulong do_arm_semihosting(CPUARMState *env); | ||
| 42 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/target/arm/helper.c | ||
| 45 | +++ b/target/arm/helper.c | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) | ||
| 47 | unsigned int new_mode = aarch64_pstate_mode(new_el, true); | ||
| 48 | unsigned int cur_el = arm_current_el(env); | ||
| 49 | |||
| 50 | - aarch64_sve_change_el(env, cur_el, new_el); | ||
| 51 | + /* | ||
| 52 | + * Note that new_el can never be 0. If cur_el is 0, then | ||
| 53 | + * el0_a64 is is_a64(), else el0_a64 is ignored. | ||
| 54 | + */ | ||
| 55 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); | ||
| 56 | |||
| 57 | if (cur_el < new_el) { | ||
| 58 | /* Entry vector offset depends on whether the implemented EL | ||
| 59 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | ||
| 60 | /* | ||
| 61 | * Notice a change in SVE vector size when changing EL. | ||
| 62 | */ | ||
| 63 | -void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) | ||
| 64 | +void aarch64_sve_change_el(CPUARMState *env, int old_el, | ||
| 65 | + int new_el, bool el0_a64) | ||
| 66 | { | ||
| 67 | int old_len, new_len; | ||
| 68 | + bool old_a64, new_a64; | ||
| 69 | |||
| 70 | /* Nothing to do if no SVE. */ | ||
| 71 | if (!arm_feature(env, ARM_FEATURE_SVE)) { | ||
| 72 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el) | ||
| 73 | * we already have the correct register contents when encountering the | ||
| 74 | * vq0->vq0 transition between EL0->EL1. | ||
| 75 | */ | ||
| 76 | - old_len = (arm_el_is_aa64(env, old_el) && !sve_exception_el(env, old_el) | ||
| 77 | + old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; | ||
| 78 | + old_len = (old_a64 && !sve_exception_el(env, old_el) | ||
| 79 | ? sve_zcr_len_for_el(env, old_el) : 0); | ||
| 80 | - new_len = (arm_el_is_aa64(env, new_el) && !sve_exception_el(env, new_el) | ||
| 81 | + new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; | ||
| 82 | + new_len = (new_a64 && !sve_exception_el(env, new_el) | ||
| 83 | ? sve_zcr_len_for_el(env, new_el) : 0); | ||
| 84 | |||
| 85 | /* When changing vector length, clear inaccessible state. */ | ||
| 86 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 87 | index XXXXXXX..XXXXXXX 100644 | ||
| 88 | --- a/target/arm/op_helper.c | ||
| 89 | +++ b/target/arm/op_helper.c | ||
| 90 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env) | ||
| 91 | "AArch64 EL%d PC 0x%" PRIx64 "\n", | ||
| 92 | cur_el, new_el, env->pc); | ||
| 93 | } | ||
| 94 | - aarch64_sve_change_el(env, cur_el, new_el); | ||
| 95 | + /* | ||
| 96 | + * Note that cur_el can never be 0. If new_el is 0, then | ||
| 97 | + * el0_a64 is return_to_aa64, else el0_a64 is ignored. | ||
| 98 | + */ | ||
| 99 | + aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); | ||
| 100 | |||
| 101 | qemu_mutex_lock_iothread(); | ||
| 102 | arm_call_el_change_hook(arm_env_get_cpu(env)); | ||
| 103 | -- | ||
| 104 | 2.19.0 | ||
| 105 | |||
| 106 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20181008212205.17752-3-richard.henderson@linaro.org | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | --- | ||
| 9 | target/arm/cpu.h | 88 ++++++++++++++++++++++++++++++++++++++++++++++++ | ||
| 10 | 1 file changed, 88 insertions(+) | ||
| 11 | |||
| 12 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/cpu.h | ||
| 15 | +++ b/target/arm/cpu.h | ||
| 16 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CSSELR, LEVEL, 1, 3) | ||
| 17 | */ | ||
| 18 | FIELD(V7M_CSSELR, INDEX, 0, 4) | ||
| 19 | |||
| 20 | +/* | ||
| 21 | + * System register ID fields. | ||
| 22 | + */ | ||
| 23 | +FIELD(ID_ISAR0, SWAP, 0, 4) | ||
| 24 | +FIELD(ID_ISAR0, BITCOUNT, 4, 4) | ||
| 25 | +FIELD(ID_ISAR0, BITFIELD, 8, 4) | ||
| 26 | +FIELD(ID_ISAR0, CMPBRANCH, 12, 4) | ||
| 27 | +FIELD(ID_ISAR0, COPROC, 16, 4) | ||
| 28 | +FIELD(ID_ISAR0, DEBUG, 20, 4) | ||
| 29 | +FIELD(ID_ISAR0, DIVIDE, 24, 4) | ||
| 30 | + | ||
| 31 | +FIELD(ID_ISAR1, ENDIAN, 0, 4) | ||
| 32 | +FIELD(ID_ISAR1, EXCEPT, 4, 4) | ||
| 33 | +FIELD(ID_ISAR1, EXCEPT_AR, 8, 4) | ||
| 34 | +FIELD(ID_ISAR1, EXTEND, 12, 4) | ||
| 35 | +FIELD(ID_ISAR1, IFTHEN, 16, 4) | ||
| 36 | +FIELD(ID_ISAR1, IMMEDIATE, 20, 4) | ||
| 37 | +FIELD(ID_ISAR1, INTERWORK, 24, 4) | ||
| 38 | +FIELD(ID_ISAR1, JAZELLE, 28, 4) | ||
| 39 | + | ||
| 40 | +FIELD(ID_ISAR2, LOADSTORE, 0, 4) | ||
| 41 | +FIELD(ID_ISAR2, MEMHINT, 4, 4) | ||
| 42 | +FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4) | ||
| 43 | +FIELD(ID_ISAR2, MULT, 12, 4) | ||
| 44 | +FIELD(ID_ISAR2, MULTS, 16, 4) | ||
| 45 | +FIELD(ID_ISAR2, MULTU, 20, 4) | ||
| 46 | +FIELD(ID_ISAR2, PSR_AR, 24, 4) | ||
| 47 | +FIELD(ID_ISAR2, REVERSAL, 28, 4) | ||
| 48 | + | ||
| 49 | +FIELD(ID_ISAR3, SATURATE, 0, 4) | ||
| 50 | +FIELD(ID_ISAR3, SIMD, 4, 4) | ||
| 51 | +FIELD(ID_ISAR3, SVC, 8, 4) | ||
| 52 | +FIELD(ID_ISAR3, SYNCHPRIM, 12, 4) | ||
| 53 | +FIELD(ID_ISAR3, TABBRANCH, 16, 4) | ||
| 54 | +FIELD(ID_ISAR3, T32COPY, 20, 4) | ||
| 55 | +FIELD(ID_ISAR3, TRUENOP, 24, 4) | ||
| 56 | +FIELD(ID_ISAR3, T32EE, 28, 4) | ||
| 57 | + | ||
| 58 | +FIELD(ID_ISAR4, UNPRIV, 0, 4) | ||
| 59 | +FIELD(ID_ISAR4, WITHSHIFTS, 4, 4) | ||
| 60 | +FIELD(ID_ISAR4, WRITEBACK, 8, 4) | ||
| 61 | +FIELD(ID_ISAR4, SMC, 12, 4) | ||
| 62 | +FIELD(ID_ISAR4, BARRIER, 16, 4) | ||
| 63 | +FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4) | ||
| 64 | +FIELD(ID_ISAR4, PSR_M, 24, 4) | ||
| 65 | +FIELD(ID_ISAR4, SWP_FRAC, 28, 4) | ||
| 66 | + | ||
| 67 | +FIELD(ID_ISAR5, SEVL, 0, 4) | ||
| 68 | +FIELD(ID_ISAR5, AES, 4, 4) | ||
| 69 | +FIELD(ID_ISAR5, SHA1, 8, 4) | ||
| 70 | +FIELD(ID_ISAR5, SHA2, 12, 4) | ||
| 71 | +FIELD(ID_ISAR5, CRC32, 16, 4) | ||
| 72 | +FIELD(ID_ISAR5, RDM, 24, 4) | ||
| 73 | +FIELD(ID_ISAR5, VCMA, 28, 4) | ||
| 74 | + | ||
| 75 | +FIELD(ID_ISAR6, JSCVT, 0, 4) | ||
| 76 | +FIELD(ID_ISAR6, DP, 4, 4) | ||
| 77 | +FIELD(ID_ISAR6, FHM, 8, 4) | ||
| 78 | +FIELD(ID_ISAR6, SB, 12, 4) | ||
| 79 | +FIELD(ID_ISAR6, SPECRES, 16, 4) | ||
| 80 | + | ||
| 81 | +FIELD(ID_AA64ISAR0, AES, 4, 4) | ||
| 82 | +FIELD(ID_AA64ISAR0, SHA1, 8, 4) | ||
| 83 | +FIELD(ID_AA64ISAR0, SHA2, 12, 4) | ||
| 84 | +FIELD(ID_AA64ISAR0, CRC32, 16, 4) | ||
| 85 | +FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) | ||
| 86 | +FIELD(ID_AA64ISAR0, RDM, 28, 4) | ||
| 87 | +FIELD(ID_AA64ISAR0, SHA3, 32, 4) | ||
| 88 | +FIELD(ID_AA64ISAR0, SM3, 36, 4) | ||
| 89 | +FIELD(ID_AA64ISAR0, SM4, 40, 4) | ||
| 90 | +FIELD(ID_AA64ISAR0, DP, 44, 4) | ||
| 91 | +FIELD(ID_AA64ISAR0, FHM, 48, 4) | ||
| 92 | +FIELD(ID_AA64ISAR0, TS, 52, 4) | ||
| 93 | +FIELD(ID_AA64ISAR0, TLB, 56, 4) | ||
| 94 | +FIELD(ID_AA64ISAR0, RNDR, 60, 4) | ||
| 95 | + | ||
| 96 | +FIELD(ID_AA64ISAR1, DPB, 0, 4) | ||
| 97 | +FIELD(ID_AA64ISAR1, APA, 4, 4) | ||
| 98 | +FIELD(ID_AA64ISAR1, API, 8, 4) | ||
| 99 | +FIELD(ID_AA64ISAR1, JSCVT, 12, 4) | ||
| 100 | +FIELD(ID_AA64ISAR1, FCMA, 16, 4) | ||
| 101 | +FIELD(ID_AA64ISAR1, LRCPC, 20, 4) | ||
| 102 | +FIELD(ID_AA64ISAR1, GPA, 24, 4) | ||
| 103 | +FIELD(ID_AA64ISAR1, GPI, 28, 4) | ||
| 104 | +FIELD(ID_AA64ISAR1, FRINTTS, 32, 4) | ||
| 105 | +FIELD(ID_AA64ISAR1, SB, 36, 4) | ||
| 106 | +FIELD(ID_AA64ISAR1, SPECRES, 40, 4) | ||
| 107 | + | ||
| 108 | QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK); | ||
| 109 | |||
| 110 | /* If adding a feature bit which corresponds to a Linux ELF | ||
| 111 | -- | ||
| 112 | 2.19.0 | ||
| 113 | |||
| 114 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The missing nibble made it more difficult to read. | ||
| 4 | |||
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20181008212205.17752-5-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/cpu.c | 2 +- | ||
| 11 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/cpu.c | ||
| 16 | +++ b/target/arm/cpu.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj) | ||
| 18 | cpu->id_mmfr1 = 0x00000000; | ||
| 19 | cpu->id_mmfr2 = 0x01200000; | ||
| 20 | cpu->id_mmfr3 = 0x0211; | ||
| 21 | - cpu->id_isar0 = 0x2101111; | ||
| 22 | + cpu->id_isar0 = 0x02101111; | ||
| 23 | cpu->id_isar1 = 0x13112111; | ||
| 24 | cpu->id_isar2 = 0x21232141; | ||
| 25 | cpu->id_isar3 = 0x01112131; | ||
| 26 | -- | ||
| 27 | 2.19.0 | ||
| 28 | |||
| 29 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The incorrect value advertised only thumb2 div without arm div. | ||
| 4 | |||
| 5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20181008212205.17752-6-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/cpu.c | 5 ++++- | ||
| 11 | 1 file changed, 4 insertions(+), 1 deletion(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/cpu.c | ||
| 16 | +++ b/target/arm/cpu.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
| 18 | cpu->id_mmfr1 = 0x40000000; | ||
| 19 | cpu->id_mmfr2 = 0x01240000; | ||
| 20 | cpu->id_mmfr3 = 0x02102211; | ||
| 21 | - cpu->id_isar0 = 0x01101110; | ||
| 22 | + /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but | ||
| 23 | + * table 4-41 gives 0x02101110, which includes the arm div insns. | ||
| 24 | + */ | ||
| 25 | + cpu->id_isar0 = 0x02101110; | ||
| 26 | cpu->id_isar1 = 0x13112111; | ||
| 27 | cpu->id_isar2 = 0x21232041; | ||
| 28 | cpu->id_isar3 = 0x11112131; | ||
| 29 | -- | ||
| 30 | 2.19.0 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Disable the Timestamping Unit feature bit since QEMU does not | ||
| 4 | yet support it. This allows guest SW to correctly probe for | ||
| 5 | its existance. | ||
| 6 | |||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-2-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/net/cadence_gem.c | 2 +- | ||
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/net/cadence_gem.c | ||
| 18 | +++ b/hw/net/cadence_gem.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 20 | s->regs[GEM_MODID] = s->revision; | ||
| 21 | s->regs[GEM_DESCONF] = 0x02500111; | ||
| 22 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | ||
| 23 | - s->regs[GEM_DESCONF5] = 0x002f2145; | ||
| 24 | + s->regs[GEM_DESCONF5] = 0x002f2045; | ||
| 25 | s->regs[GEM_DESCONF6] = 0x00000200; | ||
| 26 | |||
| 27 | /* Set MAC address */ | ||
| 28 | -- | ||
| 29 | 2.19.0 | ||
| 30 | |||
| 31 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Announce the availability of the various priority queues. | ||
| 4 | This fixes an issue where guest kernels would miss to | ||
| 5 | configure secondary queues due to inproper feature bits. | ||
| 6 | |||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-3-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/net/cadence_gem.c | 6 +++++- | ||
| 13 | 1 file changed, 5 insertions(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/net/cadence_gem.c | ||
| 18 | +++ b/hw/net/cadence_gem.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 20 | int i; | ||
| 21 | CadenceGEMState *s = CADENCE_GEM(d); | ||
| 22 | const uint8_t *a; | ||
| 23 | + uint32_t queues_mask; | ||
| 24 | |||
| 25 | DB_PRINT("\n"); | ||
| 26 | |||
| 27 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 28 | s->regs[GEM_DESCONF] = 0x02500111; | ||
| 29 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | ||
| 30 | s->regs[GEM_DESCONF5] = 0x002f2045; | ||
| 31 | - s->regs[GEM_DESCONF6] = 0x00000200; | ||
| 32 | + s->regs[GEM_DESCONF6] = 0x0; | ||
| 33 | + | ||
| 34 | + queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); | ||
| 35 | + s->regs[GEM_DESCONF6] |= queues_mask; | ||
| 36 | |||
| 37 | /* Set MAC address */ | ||
| 38 | a = &s->conf.macaddr.a[0]; | ||
| 39 | -- | ||
| 40 | 2.19.0 | ||
| 41 | |||
| 42 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Use uint32_t instead of unsigned to describe 32bit descriptor words. | ||
| 4 | |||
| 5 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 7 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 8 | Message-id: 20181011021931.4249-4-edgar.iglesias@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | include/hw/net/cadence_gem.h | 2 +- | ||
| 12 | hw/net/cadence_gem.c | 42 ++++++++++++++++++------------------ | ||
| 13 | 2 files changed, 22 insertions(+), 22 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/include/hw/net/cadence_gem.h | ||
| 18 | +++ b/include/hw/net/cadence_gem.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState { | ||
| 20 | |||
| 21 | uint8_t can_rx_state; /* Debug only */ | ||
| 22 | |||
| 23 | - unsigned rx_desc[MAX_PRIORITY_QUEUES][2]; | ||
| 24 | + uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; | ||
| 25 | |||
| 26 | bool sar_active[4]; | ||
| 27 | } CadenceGEMState; | ||
| 28 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/net/cadence_gem.c | ||
| 31 | +++ b/hw/net/cadence_gem.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ | ||
| 33 | |||
| 34 | #define GEM_MODID_VALUE 0x00020118 | ||
| 35 | |||
| 36 | -static inline unsigned tx_desc_get_buffer(unsigned *desc) | ||
| 37 | +static inline unsigned tx_desc_get_buffer(uint32_t *desc) | ||
| 38 | { | ||
| 39 | return desc[0]; | ||
| 40 | } | ||
| 41 | |||
| 42 | -static inline unsigned tx_desc_get_used(unsigned *desc) | ||
| 43 | +static inline unsigned tx_desc_get_used(uint32_t *desc) | ||
| 44 | { | ||
| 45 | return (desc[1] & DESC_1_USED) ? 1 : 0; | ||
| 46 | } | ||
| 47 | |||
| 48 | -static inline void tx_desc_set_used(unsigned *desc) | ||
| 49 | +static inline void tx_desc_set_used(uint32_t *desc) | ||
| 50 | { | ||
| 51 | desc[1] |= DESC_1_USED; | ||
| 52 | } | ||
| 53 | |||
| 54 | -static inline unsigned tx_desc_get_wrap(unsigned *desc) | ||
| 55 | +static inline unsigned tx_desc_get_wrap(uint32_t *desc) | ||
| 56 | { | ||
| 57 | return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0; | ||
| 58 | } | ||
| 59 | |||
| 60 | -static inline unsigned tx_desc_get_last(unsigned *desc) | ||
| 61 | +static inline unsigned tx_desc_get_last(uint32_t *desc) | ||
| 62 | { | ||
| 63 | return (desc[1] & DESC_1_TX_LAST) ? 1 : 0; | ||
| 64 | } | ||
| 65 | |||
| 66 | -static inline void tx_desc_set_last(unsigned *desc) | ||
| 67 | +static inline void tx_desc_set_last(uint32_t *desc) | ||
| 68 | { | ||
| 69 | desc[1] |= DESC_1_TX_LAST; | ||
| 70 | } | ||
| 71 | |||
| 72 | -static inline unsigned tx_desc_get_length(unsigned *desc) | ||
| 73 | +static inline unsigned tx_desc_get_length(uint32_t *desc) | ||
| 74 | { | ||
| 75 | return desc[1] & DESC_1_LENGTH; | ||
| 76 | } | ||
| 77 | |||
| 78 | -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) | ||
| 79 | +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) | ||
| 80 | { | ||
| 81 | DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue); | ||
| 82 | DB_PRINT("bufaddr: 0x%08x\n", *desc); | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue) | ||
| 84 | DB_PRINT("length: %d\n", tx_desc_get_length(desc)); | ||
| 85 | } | ||
| 86 | |||
| 87 | -static inline unsigned rx_desc_get_buffer(unsigned *desc) | ||
| 88 | +static inline unsigned rx_desc_get_buffer(uint32_t *desc) | ||
| 89 | { | ||
| 90 | return desc[0] & ~0x3UL; | ||
| 91 | } | ||
| 92 | |||
| 93 | -static inline unsigned rx_desc_get_wrap(unsigned *desc) | ||
| 94 | +static inline unsigned rx_desc_get_wrap(uint32_t *desc) | ||
| 95 | { | ||
| 96 | return desc[0] & DESC_0_RX_WRAP ? 1 : 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | -static inline unsigned rx_desc_get_ownership(unsigned *desc) | ||
| 100 | +static inline unsigned rx_desc_get_ownership(uint32_t *desc) | ||
| 101 | { | ||
| 102 | return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0; | ||
| 103 | } | ||
| 104 | |||
| 105 | -static inline void rx_desc_set_ownership(unsigned *desc) | ||
| 106 | +static inline void rx_desc_set_ownership(uint32_t *desc) | ||
| 107 | { | ||
| 108 | desc[0] |= DESC_0_RX_OWNERSHIP; | ||
| 109 | } | ||
| 110 | |||
| 111 | -static inline void rx_desc_set_sof(unsigned *desc) | ||
| 112 | +static inline void rx_desc_set_sof(uint32_t *desc) | ||
| 113 | { | ||
| 114 | desc[1] |= DESC_1_RX_SOF; | ||
| 115 | } | ||
| 116 | |||
| 117 | -static inline void rx_desc_set_eof(unsigned *desc) | ||
| 118 | +static inline void rx_desc_set_eof(uint32_t *desc) | ||
| 119 | { | ||
| 120 | desc[1] |= DESC_1_RX_EOF; | ||
| 121 | } | ||
| 122 | |||
| 123 | -static inline void rx_desc_set_length(unsigned *desc, unsigned len) | ||
| 124 | +static inline void rx_desc_set_length(uint32_t *desc, unsigned len) | ||
| 125 | { | ||
| 126 | desc[1] &= ~DESC_1_LENGTH; | ||
| 127 | desc[1] |= len; | ||
| 128 | } | ||
| 129 | |||
| 130 | -static inline void rx_desc_set_broadcast(unsigned *desc) | ||
| 131 | +static inline void rx_desc_set_broadcast(uint32_t *desc) | ||
| 132 | { | ||
| 133 | desc[1] |= R_DESC_1_RX_BROADCAST; | ||
| 134 | } | ||
| 135 | |||
| 136 | -static inline void rx_desc_set_unicast_hash(unsigned *desc) | ||
| 137 | +static inline void rx_desc_set_unicast_hash(uint32_t *desc) | ||
| 138 | { | ||
| 139 | desc[1] |= R_DESC_1_RX_UNICAST_HASH; | ||
| 140 | } | ||
| 141 | |||
| 142 | -static inline void rx_desc_set_multicast_hash(unsigned *desc) | ||
| 143 | +static inline void rx_desc_set_multicast_hash(uint32_t *desc) | ||
| 144 | { | ||
| 145 | desc[1] |= R_DESC_1_RX_MULTICAST_HASH; | ||
| 146 | } | ||
| 147 | |||
| 148 | -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx) | ||
| 149 | +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx) | ||
| 150 | { | ||
| 151 | desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH, | ||
| 152 | sar_idx); | ||
| 153 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, | ||
| 154 | */ | ||
| 155 | static void gem_transmit(CadenceGEMState *s) | ||
| 156 | { | ||
| 157 | - unsigned desc[2]; | ||
| 158 | + uint32_t desc[2]; | ||
| 159 | hwaddr packet_desc_addr; | ||
| 160 | uint8_t tx_packet[2048]; | ||
| 161 | uint8_t *p; | ||
| 162 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 163 | |||
| 164 | /* Last descriptor for this packet; hand the whole thing off */ | ||
| 165 | if (tx_desc_get_last(desc)) { | ||
| 166 | - unsigned desc_first[2]; | ||
| 167 | + uint32_t desc_first[2]; | ||
| 168 | |||
| 169 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 170 | * the processor. | ||
| 171 | -- | ||
| 172 | 2.19.0 | ||
| 173 | |||
| 174 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add macro with max number of DMA descriptor words. | ||
| 4 | No functional change. | ||
| 5 | |||
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-5-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | include/hw/net/cadence_gem.h | 5 ++++- | ||
| 13 | hw/net/cadence_gem.c | 4 ++-- | ||
| 14 | 2 files changed, 6 insertions(+), 3 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/hw/net/cadence_gem.h | ||
| 19 | +++ b/include/hw/net/cadence_gem.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | |||
| 22 | #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ | ||
| 23 | |||
| 24 | +/* Max number of words in a DMA descriptor. */ | ||
| 25 | +#define DESC_MAX_NUM_WORDS 2 | ||
| 26 | + | ||
| 27 | #define MAX_PRIORITY_QUEUES 8 | ||
| 28 | #define MAX_TYPE1_SCREENERS 16 | ||
| 29 | #define MAX_TYPE2_SCREENERS 16 | ||
| 30 | @@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState { | ||
| 31 | |||
| 32 | uint8_t can_rx_state; /* Debug only */ | ||
| 33 | |||
| 34 | - uint32_t rx_desc[MAX_PRIORITY_QUEUES][2]; | ||
| 35 | + uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS]; | ||
| 36 | |||
| 37 | bool sar_active[4]; | ||
| 38 | } CadenceGEMState; | ||
| 39 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/hw/net/cadence_gem.c | ||
| 42 | +++ b/hw/net/cadence_gem.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet, | ||
| 44 | */ | ||
| 45 | static void gem_transmit(CadenceGEMState *s) | ||
| 46 | { | ||
| 47 | - uint32_t desc[2]; | ||
| 48 | + uint32_t desc[DESC_MAX_NUM_WORDS]; | ||
| 49 | hwaddr packet_desc_addr; | ||
| 50 | uint8_t tx_packet[2048]; | ||
| 51 | uint8_t *p; | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 53 | |||
| 54 | /* Last descriptor for this packet; hand the whole thing off */ | ||
| 55 | if (tx_desc_get_last(desc)) { | ||
| 56 | - uint32_t desc_first[2]; | ||
| 57 | + uint32_t desc_first[DESC_MAX_NUM_WORDS]; | ||
| 58 | |||
| 59 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 60 | * the processor. | ||
| 61 | -- | ||
| 62 | 2.19.0 | ||
| 63 | |||
| 64 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add support for extended descriptors with optional 64bit | ||
| 4 | addressing and timestamping. QEMU will not yet provide | ||
| 5 | timestamps (always leaving the valid timestamp bit as zero). | ||
| 6 | |||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-6-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | include/hw/net/cadence_gem.h | 2 +- | ||
| 13 | hw/net/cadence_gem.c | 69 ++++++++++++++++++++++++++---------- | ||
| 14 | 2 files changed, 52 insertions(+), 19 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/hw/net/cadence_gem.h | ||
| 19 | +++ b/include/hw/net/cadence_gem.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ | ||
| 21 | #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */ | ||
| 22 | |||
| 23 | /* Max number of words in a DMA descriptor. */ | ||
| 24 | -#define DESC_MAX_NUM_WORDS 2 | ||
| 25 | +#define DESC_MAX_NUM_WORDS 6 | ||
| 26 | |||
| 27 | #define MAX_PRIORITY_QUEUES 8 | ||
| 28 | #define MAX_TYPE1_SCREENERS 16 | ||
| 29 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/hw/net/cadence_gem.c | ||
| 32 | +++ b/hw/net/cadence_gem.c | ||
| 33 | @@ -XXX,XX +XXX,XX @@ | ||
| 34 | #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ | ||
| 35 | #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ | ||
| 36 | |||
| 37 | +#define GEM_DMACFG_ADDR_64B (1U << 30) | ||
| 38 | +#define GEM_DMACFG_TX_BD_EXT (1U << 29) | ||
| 39 | +#define GEM_DMACFG_RX_BD_EXT (1U << 28) | ||
| 40 | #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ | ||
| 41 | #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ | ||
| 42 | #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ | ||
| 43 | @@ -XXX,XX +XXX,XX @@ | ||
| 44 | |||
| 45 | #define GEM_MODID_VALUE 0x00020118 | ||
| 46 | |||
| 47 | -static inline unsigned tx_desc_get_buffer(uint32_t *desc) | ||
| 48 | +static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) | ||
| 49 | { | ||
| 50 | - return desc[0]; | ||
| 51 | + uint64_t ret = desc[0]; | ||
| 52 | + | ||
| 53 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 54 | + ret |= (uint64_t)desc[2] << 32; | ||
| 55 | + } | ||
| 56 | + return ret; | ||
| 57 | } | ||
| 58 | |||
| 59 | static inline unsigned tx_desc_get_used(uint32_t *desc) | ||
| 60 | @@ -XXX,XX +XXX,XX @@ static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue) | ||
| 61 | DB_PRINT("length: %d\n", tx_desc_get_length(desc)); | ||
| 62 | } | ||
| 63 | |||
| 64 | -static inline unsigned rx_desc_get_buffer(uint32_t *desc) | ||
| 65 | +static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc) | ||
| 66 | { | ||
| 67 | - return desc[0] & ~0x3UL; | ||
| 68 | + uint64_t ret = desc[0] & ~0x3UL; | ||
| 69 | + | ||
| 70 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 71 | + ret |= (uint64_t)desc[2] << 32; | ||
| 72 | + } | ||
| 73 | + return ret; | ||
| 74 | +} | ||
| 75 | + | ||
| 76 | +static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx) | ||
| 77 | +{ | ||
| 78 | + int ret = 2; | ||
| 79 | + | ||
| 80 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 81 | + ret += 2; | ||
| 82 | + } | ||
| 83 | + if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT | ||
| 84 | + : GEM_DMACFG_TX_BD_EXT)) { | ||
| 85 | + ret += 2; | ||
| 86 | + } | ||
| 87 | + | ||
| 88 | + assert(ret <= DESC_MAX_NUM_WORDS); | ||
| 89 | + return ret; | ||
| 90 | } | ||
| 91 | |||
| 92 | static inline unsigned rx_desc_get_wrap(uint32_t *desc) | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void gem_init_register_masks(CadenceGEMState *s) | ||
| 94 | memset(&s->regs_ro[0], 0, sizeof(s->regs_ro)); | ||
| 95 | s->regs_ro[GEM_NWCTRL] = 0xFFF80000; | ||
| 96 | s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF; | ||
| 97 | - s->regs_ro[GEM_DMACFG] = 0xFE00F000; | ||
| 98 | + s->regs_ro[GEM_DMACFG] = 0x8E00F000; | ||
| 99 | s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08; | ||
| 100 | s->regs_ro[GEM_RXQBASE] = 0x00000003; | ||
| 101 | s->regs_ro[GEM_TXQBASE] = 0x00000003; | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) | ||
| 103 | DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); | ||
| 104 | /* read current descriptor */ | ||
| 105 | cpu_physical_memory_read(s->rx_desc_addr[q], | ||
| 106 | - (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q])); | ||
| 107 | + (uint8_t *)s->rx_desc[q], | ||
| 108 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 109 | |||
| 110 | /* Descriptor owned by software ? */ | ||
| 111 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { | ||
| 112 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 113 | rx_desc_get_buffer(s->rx_desc[q])); | ||
| 114 | |||
| 115 | /* Copy packet data to emulated DMA buffer */ | ||
| 116 | - cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) + | ||
| 117 | - rxbuf_offset, | ||
| 118 | - rxbuf_ptr, MIN(bytes_to_copy, rxbufsize)); | ||
| 119 | + cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + | ||
| 120 | + rxbuf_offset, | ||
| 121 | + rxbuf_ptr, | ||
| 122 | + MIN(bytes_to_copy, rxbufsize)); | ||
| 123 | rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); | ||
| 124 | bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); | ||
| 125 | |||
| 126 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 127 | /* Descriptor write-back. */ | ||
| 128 | cpu_physical_memory_write(s->rx_desc_addr[q], | ||
| 129 | (uint8_t *)s->rx_desc[q], | ||
| 130 | - sizeof(s->rx_desc[q])); | ||
| 131 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 132 | |||
| 133 | /* Next descriptor */ | ||
| 134 | if (rx_desc_get_wrap(s->rx_desc[q])) { | ||
| 135 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 136 | s->rx_desc_addr[q] = s->regs[GEM_RXQBASE]; | ||
| 137 | } else { | ||
| 138 | DB_PRINT("incrementing RX descriptor list\n"); | ||
| 139 | - s->rx_desc_addr[q] += 8; | ||
| 140 | + s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true); | ||
| 141 | } | ||
| 142 | |||
| 143 | gem_get_rx_desc(s, q); | ||
| 144 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 145 | |||
| 146 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 147 | cpu_physical_memory_read(packet_desc_addr, | ||
| 148 | - (uint8_t *)desc, sizeof(desc)); | ||
| 149 | + (uint8_t *)desc, | ||
| 150 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 151 | /* Handle all descriptors owned by hardware */ | ||
| 152 | while (tx_desc_get_used(desc) == 0) { | ||
| 153 | |||
| 154 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 155 | /* The real hardware would eat this (and possibly crash). | ||
| 156 | * For QEMU let's lend a helping hand. | ||
| 157 | */ | ||
| 158 | - if ((tx_desc_get_buffer(desc) == 0) || | ||
| 159 | + if ((tx_desc_get_buffer(s, desc) == 0) || | ||
| 160 | (tx_desc_get_length(desc) == 0)) { | ||
| 161 | DB_PRINT("Invalid TX descriptor @ 0x%x\n", | ||
| 162 | (unsigned)packet_desc_addr); | ||
| 163 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 164 | /* Gather this fragment of the packet from "dma memory" to our | ||
| 165 | * contig buffer. | ||
| 166 | */ | ||
| 167 | - cpu_physical_memory_read(tx_desc_get_buffer(desc), p, | ||
| 168 | + cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, | ||
| 169 | tx_desc_get_length(desc)); | ||
| 170 | p += tx_desc_get_length(desc); | ||
| 171 | total_bytes += tx_desc_get_length(desc); | ||
| 172 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 173 | if (tx_desc_get_wrap(desc)) { | ||
| 174 | s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; | ||
| 175 | } else { | ||
| 176 | - s->tx_desc_addr[q] = packet_desc_addr + 8; | ||
| 177 | + s->tx_desc_addr[q] = packet_desc_addr + | ||
| 178 | + 4 * gem_get_desc_len(s, false); | ||
| 179 | } | ||
| 180 | DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]); | ||
| 181 | |||
| 182 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 183 | tx_desc_set_last(desc); | ||
| 184 | packet_desc_addr = s->regs[GEM_TXQBASE]; | ||
| 185 | } else { | ||
| 186 | - packet_desc_addr += 8; | ||
| 187 | + packet_desc_addr += 4 * gem_get_desc_len(s, false); | ||
| 188 | } | ||
| 189 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 190 | - cpu_physical_memory_read(packet_desc_addr, | ||
| 191 | - (uint8_t *)desc, sizeof(desc)); | ||
| 192 | + cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, | ||
| 193 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 194 | } | ||
| 195 | |||
| 196 | if (tx_desc_get_used(desc)) { | ||
| 197 | -- | ||
| 198 | 2.19.0 | ||
| 199 | |||
| 200 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add support for selecting the Memory Region that the GEM | ||
| 4 | will do DMA to. | ||
| 5 | |||
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Message-id: 20181011021931.4249-7-edgar.iglesias@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | include/hw/net/cadence_gem.h | 2 ++ | ||
| 12 | hw/net/cadence_gem.c | 59 ++++++++++++++++++++++-------------- | ||
| 13 | 2 files changed, 39 insertions(+), 22 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/include/hw/net/cadence_gem.h | ||
| 18 | +++ b/include/hw/net/cadence_gem.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState { | ||
| 20 | |||
| 21 | /*< public >*/ | ||
| 22 | MemoryRegion iomem; | ||
| 23 | + MemoryRegion *dma_mr; | ||
| 24 | + AddressSpace dma_as; | ||
| 25 | NICState *nic; | ||
| 26 | NICConf conf; | ||
| 27 | qemu_irq irq[MAX_PRIORITY_QUEUES]; | ||
| 28 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/hw/net/cadence_gem.c | ||
| 31 | +++ b/hw/net/cadence_gem.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ | ||
| 33 | #include "hw/net/cadence_gem.h" | ||
| 34 | #include "qapi/error.h" | ||
| 35 | #include "qemu/log.h" | ||
| 36 | +#include "sysemu/dma.h" | ||
| 37 | #include "net/checksum.h" | ||
| 38 | |||
| 39 | #ifdef CADENCE_GEM_ERR_DEBUG | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) | ||
| 41 | { | ||
| 42 | DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); | ||
| 43 | /* read current descriptor */ | ||
| 44 | - cpu_physical_memory_read(s->rx_desc_addr[q], | ||
| 45 | - (uint8_t *)s->rx_desc[q], | ||
| 46 | - sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 47 | + address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, | ||
| 48 | + (uint8_t *)s->rx_desc[q], | ||
| 49 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 50 | |||
| 51 | /* Descriptor owned by software ? */ | ||
| 52 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 54 | rx_desc_get_buffer(s->rx_desc[q])); | ||
| 55 | |||
| 56 | /* Copy packet data to emulated DMA buffer */ | ||
| 57 | - cpu_physical_memory_write(rx_desc_get_buffer(s, s->rx_desc[q]) + | ||
| 58 | + address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) + | ||
| 59 | rxbuf_offset, | ||
| 60 | - rxbuf_ptr, | ||
| 61 | - MIN(bytes_to_copy, rxbufsize)); | ||
| 62 | + MEMTXATTRS_UNSPECIFIED, rxbuf_ptr, | ||
| 63 | + MIN(bytes_to_copy, rxbufsize)); | ||
| 64 | rxbuf_ptr += MIN(bytes_to_copy, rxbufsize); | ||
| 65 | bytes_to_copy -= MIN(bytes_to_copy, rxbufsize); | ||
| 66 | |||
| 67 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 68 | } | ||
| 69 | |||
| 70 | /* Descriptor write-back. */ | ||
| 71 | - cpu_physical_memory_write(s->rx_desc_addr[q], | ||
| 72 | - (uint8_t *)s->rx_desc[q], | ||
| 73 | - sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 74 | + address_space_write(&s->dma_as, s->rx_desc_addr[q], | ||
| 75 | + MEMTXATTRS_UNSPECIFIED, | ||
| 76 | + (uint8_t *)s->rx_desc[q], | ||
| 77 | + sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 78 | |||
| 79 | /* Next descriptor */ | ||
| 80 | if (rx_desc_get_wrap(s->rx_desc[q])) { | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 82 | packet_desc_addr = s->tx_desc_addr[q]; | ||
| 83 | |||
| 84 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 85 | - cpu_physical_memory_read(packet_desc_addr, | ||
| 86 | - (uint8_t *)desc, | ||
| 87 | - sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 88 | + address_space_read(&s->dma_as, packet_desc_addr, | ||
| 89 | + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, | ||
| 90 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 91 | /* Handle all descriptors owned by hardware */ | ||
| 92 | while (tx_desc_get_used(desc) == 0) { | ||
| 93 | |||
| 94 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 95 | /* Gather this fragment of the packet from "dma memory" to our | ||
| 96 | * contig buffer. | ||
| 97 | */ | ||
| 98 | - cpu_physical_memory_read(tx_desc_get_buffer(s, desc), p, | ||
| 99 | - tx_desc_get_length(desc)); | ||
| 100 | + address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc), | ||
| 101 | + MEMTXATTRS_UNSPECIFIED, | ||
| 102 | + p, tx_desc_get_length(desc)); | ||
| 103 | p += tx_desc_get_length(desc); | ||
| 104 | total_bytes += tx_desc_get_length(desc); | ||
| 105 | |||
| 106 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 107 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 108 | * the processor. | ||
| 109 | */ | ||
| 110 | - cpu_physical_memory_read(s->tx_desc_addr[q], | ||
| 111 | - (uint8_t *)desc_first, | ||
| 112 | - sizeof(desc_first)); | ||
| 113 | + address_space_read(&s->dma_as, s->tx_desc_addr[q], | ||
| 114 | + MEMTXATTRS_UNSPECIFIED, | ||
| 115 | + (uint8_t *)desc_first, | ||
| 116 | + sizeof(desc_first)); | ||
| 117 | tx_desc_set_used(desc_first); | ||
| 118 | - cpu_physical_memory_write(s->tx_desc_addr[q], | ||
| 119 | - (uint8_t *)desc_first, | ||
| 120 | - sizeof(desc_first)); | ||
| 121 | + address_space_write(&s->dma_as, s->tx_desc_addr[q], | ||
| 122 | + MEMTXATTRS_UNSPECIFIED, | ||
| 123 | + (uint8_t *)desc_first, | ||
| 124 | + sizeof(desc_first)); | ||
| 125 | /* Advance the hardware current descriptor past this packet */ | ||
| 126 | if (tx_desc_get_wrap(desc)) { | ||
| 127 | s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; | ||
| 128 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 129 | packet_desc_addr += 4 * gem_get_desc_len(s, false); | ||
| 130 | } | ||
| 131 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 132 | - cpu_physical_memory_read(packet_desc_addr, (uint8_t *)desc, | ||
| 133 | - sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 134 | + address_space_read(&s->dma_as, packet_desc_addr, | ||
| 135 | + MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, | ||
| 136 | + sizeof(uint32_t) * gem_get_desc_len(s, false)); | ||
| 137 | } | ||
| 138 | |||
| 139 | if (tx_desc_get_used(desc)) { | ||
| 140 | @@ -XXX,XX +XXX,XX @@ static void gem_realize(DeviceState *dev, Error **errp) | ||
| 141 | CadenceGEMState *s = CADENCE_GEM(dev); | ||
| 142 | int i; | ||
| 143 | |||
| 144 | + address_space_init(&s->dma_as, | ||
| 145 | + s->dma_mr ? s->dma_mr : get_system_memory(), "dma"); | ||
| 146 | + | ||
| 147 | if (s->num_priority_queues == 0 || | ||
| 148 | s->num_priority_queues > MAX_PRIORITY_QUEUES) { | ||
| 149 | error_setg(errp, "Invalid num-priority-queues value: %" PRIx8, | ||
| 150 | @@ -XXX,XX +XXX,XX @@ static void gem_init(Object *obj) | ||
| 151 | "enet", sizeof(s->regs)); | ||
| 152 | |||
| 153 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); | ||
| 154 | + | ||
| 155 | + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, | ||
| 156 | + (Object **)&s->dma_mr, | ||
| 157 | + qdev_prop_allow_set_link_before_realize, | ||
| 158 | + OBJ_PROP_LINK_STRONG, | ||
| 159 | + &error_abort); | ||
| 160 | } | ||
| 161 | |||
| 162 | static const VMStateDescription vmstate_cadence_gem = { | ||
| 163 | -- | ||
| 164 | 2.19.0 | ||
| 165 | |||
| 166 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Implement support for 64bit descriptor addresses. | ||
| 4 | |||
| 5 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 7 | Message-id: 20181011021931.4249-8-edgar.iglesias@gmail.com | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | hw/net/cadence_gem.c | 47 ++++++++++++++++++++++++++++++++++++-------- | ||
| 11 | 1 file changed, 39 insertions(+), 8 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/hw/net/cadence_gem.c | ||
| 16 | +++ b/hw/net/cadence_gem.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | ||
| 18 | #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4) | ||
| 19 | #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6) | ||
| 20 | |||
| 21 | +#define GEM_TBQPH (0x000004C8 / 4) | ||
| 22 | +#define GEM_RBQPH (0x000004D4 / 4) | ||
| 23 | + | ||
| 24 | #define GEM_INT_Q1_ENABLE (0x00000600 / 4) | ||
| 25 | #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6) | ||
| 26 | |||
| 27 | @@ -XXX,XX +XXX,XX @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr, | ||
| 28 | return 0; | ||
| 29 | } | ||
| 30 | |||
| 31 | +static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q) | ||
| 32 | +{ | ||
| 33 | + hwaddr desc_addr = 0; | ||
| 34 | + | ||
| 35 | + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { | ||
| 36 | + desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH]; | ||
| 37 | + } | ||
| 38 | + desc_addr <<= 32; | ||
| 39 | + desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q]; | ||
| 40 | + return desc_addr; | ||
| 41 | +} | ||
| 42 | + | ||
| 43 | +static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q) | ||
| 44 | +{ | ||
| 45 | + return gem_get_desc_addr(s, true, q); | ||
| 46 | +} | ||
| 47 | + | ||
| 48 | +static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q) | ||
| 49 | +{ | ||
| 50 | + return gem_get_desc_addr(s, false, q); | ||
| 51 | +} | ||
| 52 | + | ||
| 53 | static void gem_get_rx_desc(CadenceGEMState *s, int q) | ||
| 54 | { | ||
| 55 | - DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]); | ||
| 56 | + hwaddr desc_addr = gem_get_rx_desc_addr(s, q); | ||
| 57 | + | ||
| 58 | + DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr); | ||
| 59 | + | ||
| 60 | /* read current descriptor */ | ||
| 61 | - address_space_read(&s->dma_as, s->rx_desc_addr[q], MEMTXATTRS_UNSPECIFIED, | ||
| 62 | + address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, | ||
| 63 | (uint8_t *)s->rx_desc[q], | ||
| 64 | sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 65 | |||
| 66 | /* Descriptor owned by software ? */ | ||
| 67 | if (rx_desc_get_ownership(s->rx_desc[q]) == 1) { | ||
| 68 | - DB_PRINT("descriptor 0x%x owned by sw.\n", | ||
| 69 | - (unsigned)s->rx_desc_addr[q]); | ||
| 70 | + DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr); | ||
| 71 | s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF; | ||
| 72 | s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]); | ||
| 73 | /* Handle interrupt consequences */ | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 75 | q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize); | ||
| 76 | |||
| 77 | while (bytes_to_copy) { | ||
| 78 | + hwaddr desc_addr; | ||
| 79 | + | ||
| 80 | /* Do nothing if receive is not enabled. */ | ||
| 81 | if (!gem_can_receive(nc)) { | ||
| 82 | assert(!first_desc); | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) | ||
| 84 | } | ||
| 85 | |||
| 86 | /* Descriptor write-back. */ | ||
| 87 | - address_space_write(&s->dma_as, s->rx_desc_addr[q], | ||
| 88 | + desc_addr = gem_get_rx_desc_addr(s, q); | ||
| 89 | + address_space_write(&s->dma_as, desc_addr, | ||
| 90 | MEMTXATTRS_UNSPECIFIED, | ||
| 91 | (uint8_t *)s->rx_desc[q], | ||
| 92 | sizeof(uint32_t) * gem_get_desc_len(s, true)); | ||
| 93 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 94 | |||
| 95 | for (q = s->num_priority_queues - 1; q >= 0; q--) { | ||
| 96 | /* read current descriptor */ | ||
| 97 | - packet_desc_addr = s->tx_desc_addr[q]; | ||
| 98 | + packet_desc_addr = gem_get_tx_desc_addr(s, q); | ||
| 99 | |||
| 100 | DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); | ||
| 101 | address_space_read(&s->dma_as, packet_desc_addr, | ||
| 102 | @@ -XXX,XX +XXX,XX @@ static void gem_transmit(CadenceGEMState *s) | ||
| 103 | /* Last descriptor for this packet; hand the whole thing off */ | ||
| 104 | if (tx_desc_get_last(desc)) { | ||
| 105 | uint32_t desc_first[DESC_MAX_NUM_WORDS]; | ||
| 106 | + hwaddr desc_addr = gem_get_tx_desc_addr(s, q); | ||
| 107 | |||
| 108 | /* Modify the 1st descriptor of this packet to be owned by | ||
| 109 | * the processor. | ||
| 110 | */ | ||
| 111 | - address_space_read(&s->dma_as, s->tx_desc_addr[q], | ||
| 112 | + address_space_read(&s->dma_as, desc_addr, | ||
| 113 | MEMTXATTRS_UNSPECIFIED, | ||
| 114 | (uint8_t *)desc_first, | ||
| 115 | sizeof(desc_first)); | ||
| 116 | tx_desc_set_used(desc_first); | ||
| 117 | - address_space_write(&s->dma_as, s->tx_desc_addr[q], | ||
| 118 | + address_space_write(&s->dma_as, desc_addr, | ||
| 119 | MEMTXATTRS_UNSPECIFIED, | ||
| 120 | (uint8_t *)desc_first, | ||
| 121 | sizeof(desc_first)); | ||
| 122 | -- | ||
| 123 | 2.19.0 | ||
| 124 | |||
| 125 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Announce 64bit addressing support. | ||
| 4 | |||
| 5 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 7 | Message-id: 20181011021931.4249-9-edgar.iglesias@gmail.com | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | hw/net/cadence_gem.c | 3 ++- | ||
| 11 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
| 12 | |||
| 13 | diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/hw/net/cadence_gem.c | ||
| 16 | +++ b/hw/net/cadence_gem.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | ||
| 18 | #define GEM_DESCONF4 (0x0000028C/4) | ||
| 19 | #define GEM_DESCONF5 (0x00000290/4) | ||
| 20 | #define GEM_DESCONF6 (0x00000294/4) | ||
| 21 | +#define GEM_DESCONF6_64B_MASK (1U << 23) | ||
| 22 | #define GEM_DESCONF7 (0x00000298/4) | ||
| 23 | |||
| 24 | #define GEM_INT_Q1_STATUS (0x00000400 / 4) | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static void gem_reset(DeviceState *d) | ||
| 26 | s->regs[GEM_DESCONF] = 0x02500111; | ||
| 27 | s->regs[GEM_DESCONF2] = 0x2ab13fff; | ||
| 28 | s->regs[GEM_DESCONF5] = 0x002f2045; | ||
| 29 | - s->regs[GEM_DESCONF6] = 0x0; | ||
| 30 | + s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; | ||
| 31 | |||
| 32 | queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1); | ||
| 33 | s->regs[GEM_DESCONF6] |= queues_mask; | ||
| 34 | -- | ||
| 35 | 2.19.0 | ||
| 36 | |||
| 37 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | When QEMU provides the equivalent of the EL3 firmware, we | ||
| 4 | need to enable HVCs in scr_el3 when turning on CPUs that | ||
| 5 | target EL2. | ||
| 6 | |||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Message-id: 20181011021931.4249-10-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/arm-powerctl.c | 10 ++++++++++ | ||
| 13 | 1 file changed, 10 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/arm-powerctl.c | ||
| 18 | +++ b/target/arm/arm-powerctl.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, | ||
| 20 | } else { | ||
| 21 | /* Processor is not in secure mode */ | ||
| 22 | target_cpu->env.cp15.scr_el3 |= SCR_NS; | ||
| 23 | + | ||
| 24 | + /* | ||
| 25 | + * If QEMU is providing the equivalent of EL3 firmware, then we need | ||
| 26 | + * to make sure a CPU targeting EL2 comes out of reset with a | ||
| 27 | + * functional HVC insn. | ||
| 28 | + */ | ||
| 29 | + if (arm_feature(&target_cpu->env, ARM_FEATURE_EL3) | ||
| 30 | + && info->target_el == 2) { | ||
| 31 | + target_cpu->env.cp15.scr_el3 |= SCR_HCE; | ||
| 32 | + } | ||
| 33 | } | ||
| 34 | |||
| 35 | /* We check if the started CPU is now at the correct level */ | ||
| 36 | -- | ||
| 37 | 2.19.0 | ||
| 38 | |||
| 39 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | ||
| 2 | 1 | ||
| 3 | Add the ARM Cortex-A72. | ||
| 4 | |||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 6 | Message-id: 20181011021931.4249-11-edgar.iglesias@gmail.com | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | --- | ||
| 9 | target/arm/cpu64.c | 66 +++++++++++++++++++++++++++++++++++++++++++--- | ||
| 10 | 1 file changed, 63 insertions(+), 3 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/cpu64.c | ||
| 15 | +++ b/target/arm/cpu64.c | ||
| 16 | @@ -XXX,XX +XXX,XX @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
| 17 | } | ||
| 18 | #endif | ||
| 19 | |||
| 20 | -static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = { | ||
| 21 | +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { | ||
| 22 | #ifndef CONFIG_USER_ONLY | ||
| 23 | { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 24 | .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj) | ||
| 26 | cpu->gic_num_lrs = 4; | ||
| 27 | cpu->gic_vpribits = 5; | ||
| 28 | cpu->gic_vprebits = 5; | ||
| 29 | - define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); | ||
| 30 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 31 | } | ||
| 32 | |||
| 33 | static void aarch64_a53_initfn(Object *obj) | ||
| 34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
| 35 | cpu->gic_num_lrs = 4; | ||
| 36 | cpu->gic_vpribits = 5; | ||
| 37 | cpu->gic_vprebits = 5; | ||
| 38 | - define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); | ||
| 39 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 40 | +} | ||
| 41 | + | ||
| 42 | +static void aarch64_a72_initfn(Object *obj) | ||
| 43 | +{ | ||
| 44 | + ARMCPU *cpu = ARM_CPU(obj); | ||
| 45 | + | ||
| 46 | + cpu->dtb_compatible = "arm,cortex-a72"; | ||
| 47 | + set_feature(&cpu->env, ARM_FEATURE_V8); | ||
| 48 | + set_feature(&cpu->env, ARM_FEATURE_VFP4); | ||
| 49 | + set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
| 50 | + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
| 51 | + set_feature(&cpu->env, ARM_FEATURE_AARCH64); | ||
| 52 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
| 53 | + set_feature(&cpu->env, ARM_FEATURE_V8_AES); | ||
| 54 | + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); | ||
| 55 | + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); | ||
| 56 | + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); | ||
| 57 | + set_feature(&cpu->env, ARM_FEATURE_CRC); | ||
| 58 | + set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
| 59 | + set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
| 60 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
| 61 | + cpu->midr = 0x410fd083; | ||
| 62 | + cpu->revidr = 0x00000000; | ||
| 63 | + cpu->reset_fpsid = 0x41034080; | ||
| 64 | + cpu->mvfr0 = 0x10110222; | ||
| 65 | + cpu->mvfr1 = 0x12111111; | ||
| 66 | + cpu->mvfr2 = 0x00000043; | ||
| 67 | + cpu->ctr = 0x8444c004; | ||
| 68 | + cpu->reset_sctlr = 0x00c50838; | ||
| 69 | + cpu->id_pfr0 = 0x00000131; | ||
| 70 | + cpu->id_pfr1 = 0x00011011; | ||
| 71 | + cpu->id_dfr0 = 0x03010066; | ||
| 72 | + cpu->id_afr0 = 0x00000000; | ||
| 73 | + cpu->id_mmfr0 = 0x10201105; | ||
| 74 | + cpu->id_mmfr1 = 0x40000000; | ||
| 75 | + cpu->id_mmfr2 = 0x01260000; | ||
| 76 | + cpu->id_mmfr3 = 0x02102211; | ||
| 77 | + cpu->id_isar0 = 0x02101110; | ||
| 78 | + cpu->id_isar1 = 0x13112111; | ||
| 79 | + cpu->id_isar2 = 0x21232042; | ||
| 80 | + cpu->id_isar3 = 0x01112131; | ||
| 81 | + cpu->id_isar4 = 0x00011142; | ||
| 82 | + cpu->id_isar5 = 0x00011121; | ||
| 83 | + cpu->id_aa64pfr0 = 0x00002222; | ||
| 84 | + cpu->id_aa64dfr0 = 0x10305106; | ||
| 85 | + cpu->pmceid0 = 0x00000000; | ||
| 86 | + cpu->pmceid1 = 0x00000000; | ||
| 87 | + cpu->id_aa64isar0 = 0x00011120; | ||
| 88 | + cpu->id_aa64mmfr0 = 0x00001124; | ||
| 89 | + cpu->dbgdidr = 0x3516d000; | ||
| 90 | + cpu->clidr = 0x0a200023; | ||
| 91 | + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ | ||
| 92 | + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ | ||
| 93 | + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ | ||
| 94 | + cpu->dcz_blocksize = 4; /* 64 bytes */ | ||
| 95 | + cpu->gic_num_lrs = 4; | ||
| 96 | + cpu->gic_vpribits = 5; | ||
| 97 | + cpu->gic_vprebits = 5; | ||
| 98 | + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); | ||
| 99 | } | ||
| 100 | |||
| 101 | static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, | ||
| 102 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMCPUInfo { | ||
| 103 | static const ARMCPUInfo aarch64_cpus[] = { | ||
| 104 | { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, | ||
| 105 | { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, | ||
| 106 | + { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, | ||
| 107 | { .name = "max", .initfn = aarch64_max_initfn }, | ||
| 108 | { .name = NULL } | ||
| 109 | }; | ||
| 110 | -- | ||
| 111 | 2.19.0 | ||
| 112 | |||
| 113 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Aaron Lindsay <aclindsa@gmail.com> | ||
| 2 | 1 | ||
| 3 | I previously fixed this for PMINTENSET_EL1, but missed these. | ||
| 4 | |||
| 5 | Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> | ||
| 6 | Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20181010203735.27918-2-aclindsa@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/helper.c | 6 ++++-- | ||
| 12 | 1 file changed, 4 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper.c | ||
| 17 | +++ b/target/arm/helper.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = { | ||
| 19 | .writefn = pmintenset_write, .raw_writefn = raw_write, | ||
| 20 | .resetvalue = 0x0 }, | ||
| 21 | { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2, | ||
| 22 | - .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, | ||
| 23 | + .access = PL1_RW, .accessfn = access_tpm, | ||
| 24 | + .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
| 25 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
| 26 | .writefn = pmintenclr_write, }, | ||
| 27 | { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, | ||
| 28 | .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, | ||
| 29 | - .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS, | ||
| 30 | + .access = PL1_RW, .accessfn = access_tpm, | ||
| 31 | + .type = ARM_CP_ALIAS | ARM_CP_IO, | ||
| 32 | .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), | ||
| 33 | .writefn = pmintenclr_write }, | ||
| 34 | { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH, | ||
| 35 | -- | ||
| 36 | 2.19.0 | ||
| 37 | |||
| 38 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Aaron Lindsay <aclindsa@gmail.com> | ||
| 2 | 1 | ||
| 3 | This is an amendment to my earlier patch: | ||
| 4 | commit 7ece99b17e832065236c07a158dfac62619ef99b | ||
| 5 | Author: Aaron Lindsay <alindsay@codeaurora.org> | ||
| 6 | Date: Thu Apr 26 11:04:39 2018 +0100 | ||
| 7 | |||
| 8 | target/arm: Mask PMU register writes based on PMCR_EL0.N | ||
| 9 | |||
| 10 | Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20181010203735.27918-3-aclindsa@gmail.com | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | target/arm/helper.c | 1 + | ||
| 16 | 1 file changed, 1 insertion(+) | ||
| 17 | |||
| 18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/arm/helper.c | ||
| 21 | +++ b/target/arm/helper.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 23 | static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 24 | uint64_t value) | ||
| 25 | { | ||
| 26 | + value &= pmu_counter_mask(env); | ||
| 27 | env->cp15.c9_pmovsr &= ~value; | ||
| 28 | } | ||
| 29 | |||
| 30 | -- | ||
| 31 | 2.19.0 | ||
| 32 | |||
| 33 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The get_phys_addr() functions take a pointer to an ARMMMUFaultInfo | ||
| 2 | struct, which they fill in only if a fault occurs. This means that | ||
| 3 | the caller must always zero-initialize the struct before passing | ||
| 4 | it in. We forgot to do this in v7m_stack_read() and v7m_stack_write(). | ||
| 5 | Correct the error. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20181011172057.9466-1-peter.maydell@linaro.org | ||
| 10 | --- | ||
| 11 | target/arm/helper.c | 4 ++-- | ||
| 12 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/helper.c | ||
| 17 | +++ b/target/arm/helper.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | ||
| 19 | target_ulong page_size; | ||
| 20 | hwaddr physaddr; | ||
| 21 | int prot; | ||
| 22 | - ARMMMUFaultInfo fi; | ||
| 23 | + ARMMMUFaultInfo fi = {}; | ||
| 24 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; | ||
| 25 | int exc; | ||
| 26 | bool exc_secure; | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, | ||
| 28 | target_ulong page_size; | ||
| 29 | hwaddr physaddr; | ||
| 30 | int prot; | ||
| 31 | - ARMMMUFaultInfo fi; | ||
| 32 | + ARMMMUFaultInfo fi = {}; | ||
| 33 | bool secure = mmu_idx & ARM_MMU_IDX_M_S; | ||
| 34 | int exc; | ||
| 35 | bool exc_secure; | ||
| 36 | -- | ||
| 37 | 2.19.0 | ||
| 38 | |||
| 39 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Add a new Coccinelle script which replaces uses of the inplace | ||
| 2 | byteswapping functions *_to_cpus() and cpu_to_*s() with their | ||
| 3 | not-in-place equivalents. This is useful for where the swapping | ||
| 4 | is done on members of a packed struct -- taking the address | ||
| 5 | of the member to pass it to an inplace function is undefined | ||
| 6 | behaviour in C. | ||
| 7 | 1 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Reviewed-by: Eric Blake <eblake@redhat.com> | ||
| 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Message-id: 20181009181612.10633-1-peter.maydell@linaro.org | ||
| 12 | --- | ||
| 13 | scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++++++++++++++ | ||
| 14 | 1 file changed, 65 insertions(+) | ||
| 15 | create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci | ||
| 16 | |||
| 17 | diff --git a/scripts/coccinelle/inplace-byteswaps.cocci b/scripts/coccinelle/inplace-byteswaps.cocci | ||
| 18 | new file mode 100644 | ||
| 19 | index XXXXXXX..XXXXXXX | ||
| 20 | --- /dev/null | ||
| 21 | +++ b/scripts/coccinelle/inplace-byteswaps.cocci | ||
| 22 | @@ -XXX,XX +XXX,XX @@ | ||
| 23 | +// Replace uses of in-place byteswapping functions with calls to the | ||
| 24 | +// equivalent not-in-place functions. This is necessary to avoid | ||
| 25 | +// undefined behaviour if the expression being swapped is a field in a | ||
| 26 | +// packed struct. | ||
| 27 | + | ||
| 28 | +@@ | ||
| 29 | +expression E; | ||
| 30 | +@@ | ||
| 31 | +-be16_to_cpus(&E); | ||
| 32 | ++E = be16_to_cpu(E); | ||
| 33 | +@@ | ||
| 34 | +expression E; | ||
| 35 | +@@ | ||
| 36 | +-be32_to_cpus(&E); | ||
| 37 | ++E = be32_to_cpu(E); | ||
| 38 | +@@ | ||
| 39 | +expression E; | ||
| 40 | +@@ | ||
| 41 | +-be64_to_cpus(&E); | ||
| 42 | ++E = be64_to_cpu(E); | ||
| 43 | +@@ | ||
| 44 | +expression E; | ||
| 45 | +@@ | ||
| 46 | +-cpu_to_be16s(&E); | ||
| 47 | ++E = cpu_to_be16(E); | ||
| 48 | +@@ | ||
| 49 | +expression E; | ||
| 50 | +@@ | ||
| 51 | +-cpu_to_be32s(&E); | ||
| 52 | ++E = cpu_to_be32(E); | ||
| 53 | +@@ | ||
| 54 | +expression E; | ||
| 55 | +@@ | ||
| 56 | +-cpu_to_be64s(&E); | ||
| 57 | ++E = cpu_to_be64(E); | ||
| 58 | +@@ | ||
| 59 | +expression E; | ||
| 60 | +@@ | ||
| 61 | +-le16_to_cpus(&E); | ||
| 62 | ++E = le16_to_cpu(E); | ||
| 63 | +@@ | ||
| 64 | +expression E; | ||
| 65 | +@@ | ||
| 66 | +-le32_to_cpus(&E); | ||
| 67 | ++E = le32_to_cpu(E); | ||
| 68 | +@@ | ||
| 69 | +expression E; | ||
| 70 | +@@ | ||
| 71 | +-le64_to_cpus(&E); | ||
| 72 | ++E = le64_to_cpu(E); | ||
| 73 | +@@ | ||
| 74 | +expression E; | ||
| 75 | +@@ | ||
| 76 | +-cpu_to_le16s(&E); | ||
| 77 | ++E = cpu_to_le16(E); | ||
| 78 | +@@ | ||
| 79 | +expression E; | ||
| 80 | +@@ | ||
| 81 | +-cpu_to_le32s(&E); | ||
| 82 | ++E = cpu_to_le32(E); | ||
| 83 | +@@ | ||
| 84 | +expression E; | ||
| 85 | +@@ | ||
| 86 | +-cpu_to_le64s(&E); | ||
| 87 | ++E = cpu_to_le64(E); | ||
| 88 | -- | ||
| 89 | 2.19.0 | ||
| 90 | |||
| 91 | diff view generated by jsdifflib |