1
v2: use "unsigned int" instead of "uint".
1
Squashed in a trivial fix for 32-bit hosts:
2
2
3
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
4
-- PMM
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-- PMM
5
6
The following changes since commit 506e4a00de01e0b29fa83db5cbbc3d154253b4ea:
7
16
8
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into staging (2018-09-25 13:30:45 +0100)
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
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19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
9
20
10
are available in the Git repository at:
21
are available in the Git repository at:
11
22
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180925-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
13
24
14
for you to fetch changes up to 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
15
26
16
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode (2018-09-25 15:13:24 +0100)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
17
28
18
----------------------------------------------------------------
29
----------------------------------------------------------------
19
target-arm queue:
30
target-arm queue:
20
* target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
21
* hw/arm/exynos4210: fix Exynos4210 UART support
32
* docs: Document which architecture extensions we emulate
22
* hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
33
* Fix bugs in M-profile FPCXT_NS accesses
23
* arm: Add BBC micro:bit machine
34
* First slice of MVE patches
24
* aspeed/i2c: Fix interrupt handling bugs
35
* Implement MTE3
25
* hw/arm/smmu-common: Fix the name of the iommu memory regions
36
* docs/system: arm: Add nRF boards description
26
* hw/arm/smmuv3: fix eventq recording and IRQ triggerring
27
* hw/intc/arm_gic: Document QEMU interface
28
* hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
29
* hw/net/pcnet-pci: Convert away from old_mmio accessors
30
* hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
31
* aspeed/timer: fix compile breakage with clang 3.4.2
32
* hw/arm/aspeed: change the FMC flash model of the AST2500 evb
33
* hw/arm/aspeed: Minor code cleanups
34
* target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
35
37
36
----------------------------------------------------------------
38
----------------------------------------------------------------
37
Bartlomiej Zolnierkiewicz (1):
39
Alexandre Iooss (1):
38
hw/arm/exynos4210: fix Exynos4210 UART support
40
docs/system: arm: Add nRF boards description
39
41
40
Cédric Le Goater (5):
42
Peter Collingbourne (1):
41
aspeed/i2c: interrupts should be cleared by software only
43
target/arm: Implement MTE3
42
aspeed/timer: fix compile breakage with clang 3.4.2
43
hw/arm/aspeed: change the FMC flash model of the AST2500 evb
44
hw/arm/aspeed: Add an Aspeed machine class
45
aspeed/smc: fix some alignment issues
46
44
47
Eric Auger (2):
45
Peter Maydell (55):
48
hw/arm/smmu-common: Fix the name of the iommu memory regions
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
49
hw/arm/smmuv3: fix eventq recording and IRQ triggerring
47
hw/acpi: Provide function acpi_ghes_present()
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
50
101
51
Guenter Roeck (2):
102
docs/system/arm/emulation.rst | 103 ++++
52
aspeed/i2c: Handle receive command in separate function
103
docs/system/arm/nrf.rst | 51 ++
53
aspeed/i2c: Fix receive done interrupt handling
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
54
135
55
Joel Stanley (3):
56
MAINTAINERS: Add NRF51 entry
57
arm: Add Nordic Semiconductor nRF51 SoC
58
arm: Add BBC micro:bit machine
59
60
Peter Maydell (6):
61
hw/intc/arm_gic: Document QEMU interface
62
hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
63
hw/net/pcnet-pci: Convert away from old_mmio accessors
64
hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
65
hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
66
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
67
68
Richard Henderson (1):
69
target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
70
71
Shannon Zhao (1):
72
hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
73
74
hw/arm/Makefile.objs | 1 +
75
hw/arm/smmuv3-internal.h | 26 ++---
76
hw/intc/gic_internal.h | 2 -
77
include/hw/arm/aspeed.h | 46 +++++++++
78
include/hw/arm/nrf51_soc.h | 41 ++++++++
79
include/hw/intc/arm_gic.h | 43 ++++++++
80
include/hw/timer/aspeed_timer.h | 3 +-
81
hw/arm/aspeed.c | 212 +++++++++++++---------------------------
82
hw/arm/exynos4210.c | 8 +-
83
hw/arm/microbit.c | 67 +++++++++++++
84
hw/arm/nrf51_soc.c | 133 +++++++++++++++++++++++++
85
hw/arm/smmu-common.c | 6 +-
86
hw/arm/smmuv3.c | 2 +-
87
hw/arm/virt-acpi-build.c | 10 +-
88
hw/i2c/aspeed_i2c.c | 63 ++++++++----
89
hw/intc/arm_gic.c | 31 +++---
90
hw/intc/arm_gic_common.c | 1 -
91
hw/net/pcnet-pci.c | 98 ++-----------------
92
hw/ssi/aspeed_smc.c | 8 +-
93
hw/timer/aspeed_timer.c | 1 -
94
hw/timer/cmsdk-apb-dualtimer.c | 2 +
95
target/arm/cpu.c | 14 ++-
96
target/arm/helper.c | 45 +++++----
97
MAINTAINERS | 8 ++
98
default-configs/arm-softmmu.mak | 1 +
99
hw/net/trace-events | 6 --
100
26 files changed, 542 insertions(+), 336 deletions(-)
101
create mode 100644 include/hw/arm/aspeed.h
102
create mode 100644 include/hw/arm/nrf51_soc.h
103
create mode 100644 hw/arm/microbit.c
104
create mode 100644 hw/arm/nrf51_soc.c
105
diff view generated by jsdifflib