1 | v2: use "unsigned int" instead of "uint". | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
---|---|---|---|
2 | ethernet device failed 'make check' on big-endian hosts. | ||
2 | 3 | ||
3 | thanks | ||
4 | -- PMM | 4 | -- PMM |
5 | |||
6 | The following changes since commit 506e4a00de01e0b29fa83db5cbbc3d154253b4ea: | ||
7 | 5 | ||
8 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into staging (2018-09-25 13:30:45 +0100) | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
7 | |||
8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) | ||
9 | 9 | ||
10 | are available in the Git repository at: | 10 | are available in the Git repository at: |
11 | 11 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180925-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
13 | 13 | ||
14 | for you to fetch changes up to 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
15 | 15 | ||
16 | target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode (2018-09-25 15:13:24 +0100) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
17 | 17 | ||
18 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
19 | target-arm queue: | 19 | target-arm queue: |
20 | * target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs | 20 | * Correctly initialize MDCR_EL2.HPMN |
21 | * hw/arm/exynos4210: fix Exynos4210 UART support | 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 |
22 | * hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes | 22 | * accel/tcg: Add URL of clang bug to comment about our workaround |
23 | * arm: Add BBC micro:bit machine | 23 | * Add support for FEAT_DIT, Data Independent Timing |
24 | * aspeed/i2c: Fix interrupt handling bugs | 24 | * Remove GPIO from unimplemented NPCM7XX |
25 | * hw/arm/smmu-common: Fix the name of the iommu memory regions | 25 | * Fix SCR RES1 handling |
26 | * hw/arm/smmuv3: fix eventq recording and IRQ triggerring | 26 | * Don't migrate CPUARMState.features |
27 | * hw/intc/arm_gic: Document QEMU interface | ||
28 | * hw/intc/arm_gic: Drop GIC_BASE_IRQ macro | ||
29 | * hw/net/pcnet-pci: Convert away from old_mmio accessors | ||
30 | * hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements | ||
31 | * aspeed/timer: fix compile breakage with clang 3.4.2 | ||
32 | * hw/arm/aspeed: change the FMC flash model of the AST2500 evb | ||
33 | * hw/arm/aspeed: Minor code cleanups | ||
34 | * target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode | ||
35 | 27 | ||
36 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
37 | Bartlomiej Zolnierkiewicz (1): | 29 | Aaron Lindsay (1): |
38 | hw/arm/exynos4210: fix Exynos4210 UART support | 30 | target/arm: Don't migrate CPUARMState.features |
39 | 31 | ||
40 | Cédric Le Goater (5): | 32 | Daniel Müller (1): |
41 | aspeed/i2c: interrupts should be cleared by software only | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
42 | aspeed/timer: fix compile breakage with clang 3.4.2 | ||
43 | hw/arm/aspeed: change the FMC flash model of the AST2500 evb | ||
44 | hw/arm/aspeed: Add an Aspeed machine class | ||
45 | aspeed/smc: fix some alignment issues | ||
46 | 34 | ||
47 | Eric Auger (2): | 35 | Edgar E. Iglesias (1): |
48 | hw/arm/smmu-common: Fix the name of the iommu memory regions | 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 |
49 | hw/arm/smmuv3: fix eventq recording and IRQ triggerring | ||
50 | 37 | ||
51 | Guenter Roeck (2): | 38 | Hao Wu (1): |
52 | aspeed/i2c: Handle receive command in separate function | 39 | hw/arm: Remove GPIO from unimplemented NPCM7XX |
53 | aspeed/i2c: Fix receive done interrupt handling | ||
54 | 40 | ||
55 | Joel Stanley (3): | 41 | Mike Nawrocki (1): |
56 | MAINTAINERS: Add NRF51 entry | 42 | target/arm: Fix SCR RES1 handling |
57 | arm: Add Nordic Semiconductor nRF51 SoC | ||
58 | arm: Add BBC micro:bit machine | ||
59 | 43 | ||
60 | Peter Maydell (6): | 44 | Peter Maydell (2): |
61 | hw/intc/arm_gic: Document QEMU interface | 45 | arm: Update infocenter.arm.com URLs |
62 | hw/intc/arm_gic: Drop GIC_BASE_IRQ macro | 46 | accel/tcg: Add URL of clang bug to comment about our workaround |
63 | hw/net/pcnet-pci: Convert away from old_mmio accessors | ||
64 | hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write | ||
65 | hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements | ||
66 | target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode | ||
67 | 47 | ||
68 | Richard Henderson (1): | 48 | Rebecca Cran (4): |
69 | target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs | 49 | target/arm: Add support for FEAT_DIT, Data Independent Timing |
50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate | ||
51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU | ||
52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU | ||
70 | 53 | ||
71 | Shannon Zhao (1): | 54 | include/hw/dma/pl080.h | 7 ++-- |
72 | hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes | 55 | include/hw/misc/arm_integrator_debug.h | 2 +- |
56 | include/hw/ssi/pl022.h | 5 ++- | ||
57 | target/arm/cpu.h | 17 ++++++++ | ||
58 | target/arm/internals.h | 6 +++ | ||
59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
61 | hw/arm/musca.c | 4 +- | ||
62 | hw/arm/npcm7xx.c | 8 ---- | ||
63 | hw/arm/xlnx-versal.c | 4 +- | ||
64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
65 | hw/timer/arm_timer.c | 7 ++-- | ||
66 | target/arm/cpu.c | 4 ++ | ||
67 | target/arm/cpu64.c | 5 +++ | ||
68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
70 | target/arm/machine.c | 2 +- | ||
71 | target/arm/op_helper.c | 9 +---- | ||
72 | target/arm/translate-a64.c | 12 ++++++ | ||
73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
73 | 74 | ||
74 | hw/arm/Makefile.objs | 1 + | ||
75 | hw/arm/smmuv3-internal.h | 26 ++--- | ||
76 | hw/intc/gic_internal.h | 2 - | ||
77 | include/hw/arm/aspeed.h | 46 +++++++++ | ||
78 | include/hw/arm/nrf51_soc.h | 41 ++++++++ | ||
79 | include/hw/intc/arm_gic.h | 43 ++++++++ | ||
80 | include/hw/timer/aspeed_timer.h | 3 +- | ||
81 | hw/arm/aspeed.c | 212 +++++++++++++--------------------------- | ||
82 | hw/arm/exynos4210.c | 8 +- | ||
83 | hw/arm/microbit.c | 67 +++++++++++++ | ||
84 | hw/arm/nrf51_soc.c | 133 +++++++++++++++++++++++++ | ||
85 | hw/arm/smmu-common.c | 6 +- | ||
86 | hw/arm/smmuv3.c | 2 +- | ||
87 | hw/arm/virt-acpi-build.c | 10 +- | ||
88 | hw/i2c/aspeed_i2c.c | 63 ++++++++---- | ||
89 | hw/intc/arm_gic.c | 31 +++--- | ||
90 | hw/intc/arm_gic_common.c | 1 - | ||
91 | hw/net/pcnet-pci.c | 98 ++----------------- | ||
92 | hw/ssi/aspeed_smc.c | 8 +- | ||
93 | hw/timer/aspeed_timer.c | 1 - | ||
94 | hw/timer/cmsdk-apb-dualtimer.c | 2 + | ||
95 | target/arm/cpu.c | 14 ++- | ||
96 | target/arm/helper.c | 45 +++++---- | ||
97 | MAINTAINERS | 8 ++ | ||
98 | default-configs/arm-softmmu.mak | 1 + | ||
99 | hw/net/trace-events | 6 -- | ||
100 | 26 files changed, 542 insertions(+), 336 deletions(-) | ||
101 | create mode 100644 include/hw/arm/aspeed.h | ||
102 | create mode 100644 include/hw/arm/nrf51_soc.h | ||
103 | create mode 100644 hw/arm/microbit.c | ||
104 | create mode 100644 hw/arm/nrf51_soc.c | ||
105 | diff view generated by jsdifflib |