target-arm queue of various easier things that had piled

up while I was on holiday.

thanks

-- PMM

The following changes since commit 506e4a00de01e0b29fa83db5cbbc3d154253b4ea:

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into staging (2018-09-25 13:30:45 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180925

for you to fetch changes up to 4a87106b160a3e72152443065fb92f8a1313c23d:

target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode (2018-09-25 14:14:07 +0100)

* target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs

* hw/arm/exynos4210: fix Exynos4210 UART support

* hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes

* arm: Add BBC micro:bit machine

* aspeed/i2c: Fix interrupt handling bugs

* hw/arm/smmu-common: Fix the name of the iommu memory regions

* hw/arm/smmuv3: fix eventq recording and IRQ triggerring

* hw/intc/arm_gic: Document QEMU interface

* hw/intc/arm_gic: Drop GIC_BASE_IRQ macro

* hw/net/pcnet-pci: Convert away from old_mmio accessors

* hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements

* aspeed/timer: fix compile breakage with clang 3.4.2

* hw/arm/aspeed: change the FMC flash model of the AST2500 evb

* hw/arm/aspeed: Minor code cleanups

* target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode

Bartlomiej Zolnierkiewicz (1):

hw/arm/exynos4210: fix Exynos4210 UART support

Cédric Le Goater (5):

aspeed/i2c: interrupts should be cleared by software only

aspeed/timer: fix compile breakage with clang 3.4.2

hw/arm/aspeed: change the FMC flash model of the AST2500 evb

hw/arm/aspeed: Add an Aspeed machine class

aspeed/smc: fix some alignment issues

Eric Auger (2):

hw/arm/smmu-common: Fix the name of the iommu memory regions

hw/arm/smmuv3: fix eventq recording and IRQ triggerring

Guenter Roeck (2):

aspeed/i2c: Handle receive command in separate function

aspeed/i2c: Fix receive done interrupt handling

Joel Stanley (3):

MAINTAINERS: Add NRF51 entry

arm: Add Nordic Semiconductor nRF51 SoC

arm: Add BBC micro:bit machine

The ARMv8 architecture defines that an AArch32 CPU starts

in SVC mode, unless EL2 is the highest available EL, in

which case it starts in Hyp mode. (In ARMv7 a CPU with EL2

but not EL3 was not a valid configuration, but we don't

specifically reject this if the user asks for one.)

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Message-id: 20180823135047.16525-1-peter.maydell@linaro.org

target/arm/cpu.c | 14 ++++++++++++--

1 file changed, 12 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

env->cp15.c15_cpar = 1;

}

#else

- /* SVC mode with interrupts disabled. */

- env->uncached_cpsr = ARM_CPU_MODE_SVC;

+

+ /*

+ * If the highest available EL is EL2, AArch32 will start in Hyp

+ * mode; otherwise it starts in SVC. Note that if we start in

+ * AArch64 then these values in the uncached_cpsr will be ignored.

+ */

+ if (arm_feature(env, ARM_FEATURE_EL2) &&

+ !arm_feature(env, ARM_FEATURE_EL3)) {

+ env->uncached_cpsr = ARM_CPU_MODE_HYP;

+ } else {

+ env->uncached_cpsr = ARM_CPU_MODE_SVC;

env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;

if (arm_feature(env, ARM_FEATURE_M)) {

2.19.0

From: Cédric Le Goater <clg@kaod.org>

The AST2500 evb is shipped with a W25Q256 which has a non volatile bit

to make the chip operate in 4 Byte address mode at power up. This

should be an interesting feature to model as it will exercise a bit

more the SMC controllers and MMIO execution at boot time.

Signed-off-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20180921161939.822-3-clg@kaod.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm/aspeed.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c

--- a/hw/arm/aspeed.c

+++ b/hw/arm/aspeed.c

@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {

[AST2500_EVB] = {

.soc_name = "ast2500-a1",

.hw_strap1 = AST2500_EVB_HW_STRAP1,

- .fmc_model = "n25q256a",

+ .fmc_model = "w25q256",

.spi_model = "mx25l25635e",

.num_cs = 1,

.i2c_init = ast2500_evb_i2c_init,

2.19.0

The GIC_BASE_IRQ macro is a leftover from when we shared code

between the GICv2 and the v7M NVIC. Since the NVIC is now

split off, GIC_BASE_IRQ is always 0, and we can just delete it.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20180824161819.11085-1-peter.maydell@linaro.org

hw/intc/gic_internal.h | 2 --

hw/intc/arm_gic.c | 31 ++++++++++++++-----------------

hw/intc/arm_gic_common.c | 1 -

3 files changed, 14 insertions(+), 20 deletions(-)

diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h

--- a/hw/intc/gic_internal.h

+++ b/hw/intc/gic_internal.h

@@ -XXX,XX +XXX,XX @@

#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))

-#define GIC_BASE_IRQ 0

#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))

#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))

#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gic.c

+++ b/hw/intc/arm_gic.c

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

res = 0;

if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {

/* Every byte offset holds 8 group status bits */

- irq = (offset - 0x080) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x080) * 8;

if (irq >= s->num_irq) {

goto bad_reg;

}

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

irq = (offset - 0x100) * 8;

else

irq = (offset - 0x180) * 8;

- irq += GIC_BASE_IRQ;

if (irq >= s->num_irq)

goto bad_reg;

res = 0;

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

irq = (offset - 0x200) * 8;

else

irq = (offset - 0x280) * 8;

- irq += GIC_BASE_IRQ;

if (irq >= s->num_irq)

goto bad_reg;

res = 0;

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

goto bad_reg;

}

- irq += GIC_BASE_IRQ;

if (irq >= s->num_irq)

goto bad_reg;

res = 0;

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

}

} else if (offset < 0x800) {

/* Interrupt Priority. */

- irq = (offset - 0x400) + GIC_BASE_IRQ;

+ irq = (offset - 0x400);

if (irq >= s->num_irq)

goto bad_reg;

res = gic_dist_get_priority(s, cpu, irq, attrs);

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

/* For uniprocessor GICs these RAZ/WI */

res = 0;

} else {

- irq = (offset - 0x800) + GIC_BASE_IRQ;

+ irq = (offset - 0x800);

if (irq >= s->num_irq) {

goto bad_reg;

}

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)

}

} else if (offset < 0xf00) {

/* Interrupt Configuration. */

- irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;

+ irq = (offset - 0xc00) * 4;

if (irq >= s->num_irq)

goto bad_reg;

res = 0;

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

*/

if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {

/* Every byte offset holds 8 group status bits */

- irq = (offset - 0x80) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x80) * 8;

if (irq >= s->num_irq) {

goto bad_reg;

}

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

}

} else if (offset < 0x180) {

/* Interrupt Set Enable. */

- irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x100) * 8;

if (irq >= s->num_irq)

goto bad_reg;

if (irq < GIC_NR_SGIS) {

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

}

} else if (offset < 0x200) {

/* Interrupt Clear Enable. */

- irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x180) * 8;

if (irq >= s->num_irq)

goto bad_reg;

if (irq < GIC_NR_SGIS) {

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

}

} else if (offset < 0x280) {

/* Interrupt Set Pending. */

- irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x200) * 8;

if (irq >= s->num_irq)

goto bad_reg;

if (irq < GIC_NR_SGIS) {

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

}

} else if (offset < 0x300) {

/* Interrupt Clear Pending. */

- irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x280) * 8;

if (irq >= s->num_irq)

goto bad_reg;

if (irq < GIC_NR_SGIS) {

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

goto bad_reg;

}

- irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x300) * 8;

if (irq >= s->num_irq) {

goto bad_reg;

}

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

goto bad_reg;

}

- irq = (offset - 0x380) * 8 + GIC_BASE_IRQ;

+ irq = (offset - 0x380) * 8;

if (irq >= s->num_irq) {

goto bad_reg;

}

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

}

} else if (offset < 0x800) {

/* Interrupt Priority. */

- irq = (offset - 0x400) + GIC_BASE_IRQ;

+ irq = (offset - 0x400);

if (irq >= s->num_irq)

goto bad_reg;

gic_dist_set_priority(s, cpu, irq, value, attrs);

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

* annoying exception of the 11MPCore's GIC.

*/

if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {

- irq = (offset - 0x800) + GIC_BASE_IRQ;

+ irq = (offset - 0x800);

if (irq >= s->num_irq) {

goto bad_reg;

}

@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,

}

} else if (offset < 0xf00) {

/* Interrupt Configuration. */

- irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;

+ irq = (offset - 0xc00) * 4;

if (irq >= s->num_irq)

goto bad_reg;

if (irq < GIC_NR_SGIS)

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gic_common.c

+++ b/hw/intc/arm_gic_common.c

@@ -XXX,XX +XXX,XX @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)

s->num_cpu, GIC_NCPU);

return;

}

- s->num_irq += GIC_BASE_IRQ;

if (s->num_irq > GIC_MAXIRQ) {

error_setg(errp,

"requested %u interrupt lines exceeds GIC maximum %d",

2.19.0

From: Cédric Le Goater <clg@kaod.org>

Signed-off-by: Cédric Le Goater <clg@kaod.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20180921161939.822-6-clg@kaod.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/ssi/aspeed_smc.c | 8 ++++----

1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c

--- a/hw/ssi/aspeed_smc.c

+++ b/hw/ssi/aspeed_smc.c

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,

static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,

uint64_t data, unsigned size)

- qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"

- PRIx64 "\n", __func__, addr, size, data);

+ qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"

+ PRIx64 "\n", __func__, addr, size, data);

static const MemoryRegionOps aspeed_smc_flash_default_ops = {

@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)

*/

if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {

for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {

- ssi_transfer(fl->controller->spi, 0xFF);

+ ssi_transfer(fl->controller->spi, 0xFF);

}

@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)

}

static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,

- unsigned size)

+ unsigned size)

{

AspeedSMCFlash *fl = opaque;

AspeedSMCState *s = fl->controller;

2.19.0

From: Shannon Zhao <shannon.zhaosl@gmail.com>

Like commit 16b4226(hw/acpi-build: Add a check for memory-less NUMA node

), it also needs to check memory length for NUMA nodes on ARM.

Signed-off-by: Shannon Zhao <shannon.zhaosl@gmail.com>

Reviewed-by: Andrew Jones <drjones@redhat.com>

Message-id: 20180911112643.19296-1-shenglong.zsl@alibaba-inc.com

hw/arm/virt-acpi-build.c | 10 ++++++----

1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

--- a/hw/arm/virt-acpi-build.c

+++ b/hw/arm/virt-acpi-build.c

@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

mem_base = vms->memmap[VIRT_MEM].base;

for (i = 0; i < nb_numa_nodes; ++i) {

- numamem = acpi_data_push(table_data, sizeof(*numamem));

- build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,

- MEM_AFFINITY_ENABLED);

- mem_base += numa_info[i].node_mem;

+ if (numa_info[i].node_mem > 0) {

+ numamem = acpi_data_push(table_data, sizeof(*numamem));

+ build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,

+ MEM_AFFINITY_ENABLED);

+ mem_base += numa_info[i].node_mem;

+ }

build_header(linker, table_data, (void *)(table_data->data + srat_start),

2.19.0