Currently this holder is limited to at most 32 flags on
a 32-bit architecture, which lets an unique bit available
for another 'chip specific instructions' flag.

Relax this limit using a 64-bit integer.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h       | 2 +-
 target/mips/internal.h  | 2 +-
 target/mips/translate.c | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d191c..f2a5031fd2 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -614,7 +614,7 @@ struct CPUMIPSState {
     int CCRes; /* Cycle count resolution/divisor */
     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
-    int insn_flags; /* Supported instruction set */
+    uint64_t insn_flags; /* Supported instruction set */
 
     /* Fields up to this point are cleared by a CPU reset */
     struct {} end_reset_fields;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f8e6..bfe83ee613 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -59,7 +59,7 @@ struct mips_def_t {
     int32_t CP0_PageGrain_rw_bitmask;
     int32_t CP0_PageGrain;
     target_ulong CP0_EBaseWG_rw_bitmask;
-    int insn_flags;
+    uint64_t insn_flags;
     enum mips_mmu_types mmu_type;
 };
 
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb911..3b4e9ebae9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1870,7 +1870,7 @@ static inline void check_dspr2(DisasContext *ctx)
 
 /* This code generates a "reserved instruction" exception if the
    CPU does not support the instruction set corresponding to flags. */
-static inline void check_insn(DisasContext *ctx, int flags)
+static inline void check_insn(DisasContext *ctx, uint64_t flags)
 {
     if (unlikely(!(ctx->insn_flags & flags))) {
         generate_exception_end(ctx, EXCP_RI);
@@ -1880,7 +1880,7 @@ static inline void check_insn(DisasContext *ctx, int flags)
 /* This code generates a "reserved instruction" exception if the
    CPU has corresponding flag set which indicates that the instruction
    has been removed. */
-static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
+static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
 {
     if (unlikely(ctx->insn_flags & flags)) {
         generate_exception_end(ctx, EXCP_RI);
-- 
2.19.0.rc2

> From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> on behalf of Philippe Mathieu-Daudé <f4bug@amsat.org>
> Sent: Sunday, September 9, 2018 3:34 AM
>
> Subject: [PATCH 1/2] target/mips: Increase the 'supported instructions' flags holder size
>
> Currently this holder is limited to at most 32 flags on
> a 32-bit architecture, which lets an unique bit available
> for another 'chip specific instructions' flag.
> 
> Relax this limit using a 64-bit integer.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.h       | 2 +-
> target/mips/internal.h  | 2 +-
> target/mips/translate.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)

"int insn_flags;" in DisasContext definition in target/mips/translate.c needs to be updated as well.

On 9/11/18 6:33 AM, Aleksandar Markovic wrote:
>> From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> on behalf of Philippe Mathieu-Daudé <f4bug@amsat.org>
>> Sent: Sunday, September 9, 2018 3:34 AM
>>
>> Subject: [PATCH 1/2] target/mips: Increase the 'supported instructions' flags holder size
>>
>> Currently this holder is limited to at most 32 flags on
>> a 32-bit architecture, which lets an unique bit available
>> for another 'chip specific instructions' flag.
>>
>> Relax this limit using a 64-bit integer.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> target/mips/cpu.h       | 2 +-
>> target/mips/internal.h  | 2 +-
>> target/mips/translate.c | 4 ++--
>> 3 files changed, 4 insertions(+), 4 deletions(-)
> 
> "int insn_flags;" in DisasContext definition in target/mips/translate.c needs to be updated as well.

Oops I missed this one, good catch :)