[v1] mips: Allow more 'Chip specific instructions' flags

[Qemu-devel] [PATCH 0/2] mips: Allow more 'Chip specific instructions' flags

Philippe Mathieu-Daudé posted 2 patches 7 years, 1 month ago

Diff against v2
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git fetch https://github.com/patchew-project/qemu tags/patchew/20180909013444.18936-1-f4bug@amsat.org

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target/mips/cpu.h       | 2 +-
target/mips/internal.h  | 2 +-
target/mips/mips-defs.h | 2 ++
target/mips/translate.c | 4 ++--
4 files changed, 6 insertions(+), 4 deletions(-)

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[Qemu-devel] [PATCH 0/2] mips: Allow more 'Chip specific instructions' flags

Posted by Philippe Mathieu-Daudé 7 years, 1 month ago

Hi,

After noticing Fredrik patch [1] clashes with an ongoing work, I shared my
concerns after the current limitations of CPUMIPSState::insn_flags, having
1 bit left to store more 'Chip specific instructions'.

The first patch drop this restriction,
the second simply add definitions for 2 Toshiba cores.

Regards,

Phil.

[1] http://lists.nongnu.org/archive/html/qemu-devel/2018-07/msg01978.html
[2] http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00901.html

Philippe Mathieu-Daudé (2):
  target/mips: Increase the 'supported instructions' flags holder size
  target/mips: Add entries for the Toshiba's R3900 and R5900 cores

 target/mips/cpu.h       | 2 +-
 target/mips/internal.h  | 2 +-
 target/mips/mips-defs.h | 2 ++
 target/mips/translate.c | 4 ++--
 4 files changed, 6 insertions(+), 4 deletions(-)

-- 
2.19.0.rc2