The following changes since commit 19b599f7664b2ebfd0f405fb79c14dd241557452:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-08-27-v2' into staging (2018-08-27 16:44:20 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-pullreq-20180905

for you to fetch changes up to 1ca79ece35a5bcdcefb5a2582bc6da91f0640bf2:

  riscv: remove define cpu_init() (2018-09-05 09:58:38 -0700)

----------------------------------------------------------------
A misc collection of RISC-V related patches for 3.1.

----------------------------------------------------------------
Alistair Francis (2):
      hw/riscv/virtio: Set the soc device tree node as a simple-bus
      hw/riscv/spike: Set the soc device tree node as a simple-bus

Emilio G. Cota (3):
      target/riscv: optimize cross-page direct jumps in softmmu
      target/riscv: optimize indirect branches
      target/riscv: call gen_goto_tb on DISAS_TOO_MANY

Igor Mammedov (1):
      riscv: remove define cpu_init()

Michael Clark (4):
      RISC-V: Update address bits to support sv39 and sv48
      RISC-V: Improve page table walker spec compliance
      RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
      RISC-V: Simplify riscv_cpu_local_irqs_pending

 hw/riscv/sifive_plic.c         | 49 ++++++++++-----------
 hw/riscv/spike.c               |  2 +-
 hw/riscv/virt.c                |  2 +-
 include/hw/riscv/sifive_plic.h |  1 -
 target/riscv/cpu.h             |  9 ++--
 target/riscv/cpu_bits.h        |  2 -
 target/riscv/helper.c          | 98 ++++++++++++++++++++++++------------------
 target/riscv/translate.c       | 11 ++---
 8 files changed, 88 insertions(+), 86 deletions(-)

On 5 September 2018 at 23:09, Alistair Francis <alistair.francis@wdc.com> wrote:
> The following changes since commit 19b599f7664b2ebfd0f405fb79c14dd241557452:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-08-27-v2' into staging (2018-08-27 16:44:20 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-pullreq-20180905
>
> for you to fetch changes up to 1ca79ece35a5bcdcefb5a2582bc6da91f0640bf2:
>
>   riscv: remove define cpu_init() (2018-09-05 09:58:38 -0700)
>
> ----------------------------------------------------------------
> A misc collection of RISC-V related patches for 3.1.
>
> ----------------------------------------------------------------
> Alistair Francis (2):
>       hw/riscv/virtio: Set the soc device tree node as a simple-bus
>       hw/riscv/spike: Set the soc device tree node as a simple-bus
>
> Emilio G. Cota (3):
>       target/riscv: optimize cross-page direct jumps in softmmu
>       target/riscv: optimize indirect branches
>       target/riscv: call gen_goto_tb on DISAS_TOO_MANY
>
> Igor Mammedov (1):
>       riscv: remove define cpu_init()
>
> Michael Clark (4):
>       RISC-V: Update address bits to support sv39 and sv48
>       RISC-V: Improve page table walker spec compliance
>       RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
>       RISC-V: Simplify riscv_cpu_local_irqs_pending
>

Applied, thanks.

-- PMM