This patch set begins to add MXU instruction support for mips
emulation.

Craig Janeczek (8):
  target/mips: Introduce MXU registers
  target/mips: Add all MXU opcodes
  target/mips: Add MXU instructions S32I2M and S32M2I
  target/mips: Add MXU instruction S8LDD
  target/mips: Add MXU instruction D16MUL
  target/mips: Add MXU instruction D16MAC
  target/mips: Add MXU instructions Q8MUL and Q8MULSU
  target/mips: Add MXU instructions S32LDD and S32LDDR

 target/mips/cpu.h       |   1 +
 target/mips/translate.c | 601 +++++++++++++++++++++++++++++++++++-----
 2 files changed, 540 insertions(+), 62 deletions(-)

-- 
2.18.0

> From: Craig Janeczek <jancraig@amazon.com>
> Sent: Tuesday, August 28, 2018 3:00 PM
>
> Subject: [PATCH v3 0/8] Add limited MXU instruction support
>
> This patch set begins to add MXU instruction support for mips emulation.

Craig,

May I ask you what is the exact platform (CPU/board) that you are targeting with this series? Do we need perhaps to add/modify something in translate_init.inc.c? I am very curious.

Thanks,
Aleksandar

Hi, Craig,

> From: Craig Janeczek <jancraig@amazon.com>
> Sent: Tuesday, August 28, 2018 3:00 PM
> 
> Subject: [PATCH v3 0/8] Add limited MXU instruction support
> 
> This patch set begins to add MXU instruction support for mips emulation.

Based on the info I have, I think a reasonable approach to integration of this series would be:

- Add this line in mips-defs.h

#define   ASE_MXU       0x02000000

- In main switch, use this segment

        if (ctx->insn_flags & ASE_MXU) {
                decode_opc_special2_mxu(env, ctx);
        } else {
                decode_opc_special2_legacy(env, ctx);
        }

That way, you would be able to add MXU code without specifying CPU that supports it. This will enable you to focus on MXU, which is a serieoous task anyway. Hopefully, a CPU will be added at some later date.

Thanks,
Aleksandar

That seems like a good plan to separate these tasks. I will implement this in the next patchset. Thank you

-----Original Message-----
From: Aleksandar Markovic <amarkovic@wavecomp.com> 
Sent: Thursday, August 30, 2018 8:40 AM
To: Janeczek, Craig <jancraig@amazon.com>; qemu-devel@nongnu.org
Cc: aurelien@aurel32.net; Petar Jovanovic <pjovanovic@wavecomp.com>; Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH v3 0/8] Add limited MXU instruction support

Hi, Craig,

> From: Craig Janeczek <jancraig@amazon.com>
> Sent: Tuesday, August 28, 2018 3:00 PM
> 
> Subject: [PATCH v3 0/8] Add limited MXU instruction support
> 
> This patch set begins to add MXU instruction support for mips emulation.

Based on the info I have, I think a reasonable approach to integration of this series would be:

- Add this line in mips-defs.h

#define   ASE_MXU       0x02000000

- In main switch, use this segment

        if (ctx->insn_flags & ASE_MXU) {
                decode_opc_special2_mxu(env, ctx);
        } else {
                decode_opc_special2_legacy(env, ctx);
        }

That way, you would be able to add MXU code without specifying CPU that supports it. This will enable you to focus on MXU, which is a serieoous task anyway. Hopefully, a CPU will be added at some later date.

Thanks,
Aleksandar