Some more outstanding target-arm patches; nothing terribly

exciting. Mostly they're mine; I'm trying to reduce the

number of patches I still have in flight, so I've picked

out some of the reviewed patches from a couple of sets I've

sent out and will resend v2 versions of those sets with the

remaining patches with fixes for issues noted in review once

this is in master.

The following changes since commit adaec191bfb31e12d40af8ab1b869f5b40d61ee9:

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2018-08-20 09:48:03 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180820

for you to fetch changes up to b85fad1588e812566f897f747e38da345a7016d6:

hw/dma/pl080: Remove hw_error() if DMA is enabled (2018-08-20 11:24:33 +0100)

* Fix crash on conditional instruction in an IT block

* docs/generic-loader: mention U-Boot and Intel HEX executable formats

* hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset

* imx_serial: Generate interrupt on receive data ready if enabled

* Fix various minor bugs in AArch32 Hyp related coprocessor registers

* Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)

* Implement AArch32 ERET instruction

* hw/arm/virt: Add virt-3.1 machine type

* sdhci: add i.MX SD Stable Clock bit

* Remove now-obsolete MMIO request_ptr APIs

* hw/timer/m48t59: Move away from old_mmio accessors

* hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module

* nvic: Expose NMI line

* hw/dma/pl080: cleanups and new features required for use in MPS boards

Andrew Jones (1):

hw/arm/virt: Add virt-3.1 machine type

Hans-Erik Floryd (2):

imx_serial: Generate interrupt on receive data ready if enabled

sdhci: add i.MX SD Stable Clock bit

Jia He (1):

hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset

Peter Maydell (19):

target/arm: Correct typo in HAMAIR1 regdef name

target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs

target/arm: Implement AArch32 HVBAR

target/arm: Implement AArch32 Hyp FARs

target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2

target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)

target/arm: Implement AArch32 ERET instruction

hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code

memory: Remove MMIO request_ptr APIs

hw/misc: Remove mmio_interface device

hw/timer/m48t59: Move away from old_mmio accessors

hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module

nvic: Expose NMI line

hw/dma/pl080: Allow use as embedded-struct device

hw/dma/pl080: Support all three interrupt lines

hw/dma/pl080: Don't use CPU address space for DMA accesses

hw/dma/pl080: Provide device reset function

hw/dma/pl080: Correct bug in register address decode logic

hw/dma/pl080: Remove hw_error() if DMA is enabled

Roman Kapl (1):

target/arm: Fix crash on conditional instruction in an IT block

Stefan Hajnoczi (1):

docs/generic-loader: mention U-Boot and Intel HEX executable formats

docs/generic-loader.txt | 20 +-

Makefile.objs | 1 +

hw/misc/Makefile.objs | 1 -

hw/watchdog/Makefile.objs | 1 +

hw/sd/sdhci-internal.h | 2 +

include/exec/memory.h | 35 ----

include/hw/char/imx_serial.h | 1 +

include/hw/dma/pl080.h | 71 +++++++

include/hw/misc/mmio_interface.h | 49 -----

include/hw/watchdog/cmsdk-apb-watchdog.h | 59 ++++++

hw/arm/armv7m.c | 1 +

hw/arm/realview.c | 8 +-

hw/arm/versatilepb.c | 9 +-

hw/arm/virt.c | 23 ++-

hw/char/imx_serial.c | 3 +-

hw/dma/pl080.c | 113 ++++++-----

hw/intc/arm_gicv3_its_kvm.c | 2 +-

hw/intc/armv7m_nvic.c | 19 ++

hw/misc/mmio_interface.c | 135 -------------

hw/sd/sdhci.c | 8 +

hw/ssi/xilinx_spips.c | 46 -----

hw/timer/m48t59.c | 59 ++----

hw/watchdog/cmsdk-apb-watchdog.c | 326 +++++++++++++++++++++++++++++++

memory.c | 110 -----------

target/arm/helper.c | 36 +++-

target/arm/op_helper.c | 22 +--

target/arm/translate.c | 76 +++++--

MAINTAINERS | 3 +

default-configs/arm-softmmu.mak | 1 +

hw/intc/trace-events | 1 +

hw/watchdog/trace-events | 6 +

31 files changed, 717 insertions(+), 530 deletions(-)

create mode 100644 include/hw/dma/pl080.h

delete mode 100644 include/hw/misc/mmio_interface.h

create mode 100644 include/hw/watchdog/cmsdk-apb-watchdog.h

delete mode 100644 hw/misc/mmio_interface.c

create mode 100644 hw/watchdog/cmsdk-apb-watchdog.c

create mode 100644 hw/watchdog/trace-events

The PL08x model currently will unconditionally call hw_error()

if the DMA engine is enabled by the guest. This has been

present since the PL080 model was edded in 2006, and is

presumably either unintentional debug code left enabled,

or a guard against untested DMA engine code being used.

Remove the hw_error(), since we now have a guest which

will actually try to use the DMA engine (the self-test

binary for the AN505 MPS2 FPGA image).

hw/dma/pl080.c | 1 -

1 file changed, 1 deletion(-)

diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c

--- a/hw/dma/pl080.c

+++ b/hw/dma/pl080.c

@@ -XXX,XX +XXX,XX @@ static void pl080_run(PL080State *s)

if ((s->conf & PL080_CONF_E) == 0)

return;

-hw_error("DMA active\n");

/* If we are already in the middle of a DMA operation then indicate that

there may be new DMA requests and return immediately. */

if (s->running) {

2.18.0

Move the m48t59 device away from using old_mmio MemoryRegionOps

accessors.

hw/timer/m48t59.c | 59 +++++++++--------------------------------------

1 file changed, 11 insertions(+), 48 deletions(-)

diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c

--- a/hw/timer/m48t59.c

+++ b/hw/timer/m48t59.c

@@ -XXX,XX +XXX,XX @@ static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)

return retval;

-static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)

- M48t59State *NVRAM = opaque;

-

- m48t59_write(NVRAM, addr, value & 0xff);

-static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)

- M48t59State *NVRAM = opaque;

-

- m48t59_write(NVRAM, addr, (value >> 8) & 0xff);

- m48t59_write(NVRAM, addr + 1, value & 0xff);

-static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)

- M48t59State *NVRAM = opaque;

-

- m48t59_write(NVRAM, addr, (value >> 24) & 0xff);

- m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);

- m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);

- m48t59_write(NVRAM, addr + 3, value & 0xff);

-static uint32_t nvram_readb (void *opaque, hwaddr addr)

+static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)

M48t59State *NVRAM = opaque;

return m48t59_read(NVRAM, addr);

-static uint32_t nvram_readw (void *opaque, hwaddr addr)

+static void nvram_write(void *opaque, hwaddr addr, uint64_t value,

+ unsigned size)

{

M48t59State *NVRAM = opaque;

- uint32_t retval;

- retval = m48t59_read(NVRAM, addr) << 8;

- retval |= m48t59_read(NVRAM, addr + 1);

- return retval;

-static uint32_t nvram_readl (void *opaque, hwaddr addr)

-{

- M48t59State *NVRAM = opaque;

- uint32_t retval;

-

- retval = m48t59_read(NVRAM, addr) << 24;

- retval |= m48t59_read(NVRAM, addr + 1) << 16;

- retval |= m48t59_read(NVRAM, addr + 2) << 8;

- retval |= m48t59_read(NVRAM, addr + 3);

- return retval;

+ return m48t59_write(NVRAM, addr, value);

}

static const MemoryRegionOps nvram_ops = {

- .old_mmio = {

- .read = { nvram_readb, nvram_readw, nvram_readl, },

- .write = { nvram_writeb, nvram_writew, nvram_writel, },

- },

- .endianness = DEVICE_NATIVE_ENDIAN,

+ .read = nvram_read,

+ .write = nvram_write,

+ .impl.min_access_size = 1,

+ .impl.max_access_size = 1,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

+ .endianness = DEVICE_BIG_ENDIAN,

};

static const VMStateDescription vmstate_m48t59 = {

2.18.0

The PL080/PL081 model is missing a reset function; implement it.

hw/dma/pl080.c | 25 +++++++++++++++++++++++++

1 file changed, 25 insertions(+)

diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c

--- a/hw/dma/pl080.c

+++ b/hw/dma/pl080.c

@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pl080_ops = {

.endianness = DEVICE_NATIVE_ENDIAN,

};

+static void pl080_reset(DeviceState *dev)

+{

+ PL080State *s = PL080(dev);

+ int i;

+

+ s->tc_int = 0;

+ s->tc_mask = 0;

+ s->err_int = 0;

+ s->err_mask = 0;

+ s->conf = 0;

+ s->sync = 0;

+ s->req_single = 0;

+ s->req_burst = 0;

+ s->running = 0;

+

+ for (i = 0; i < s->nchannels; i++) {

+ s->chan[i].src = 0;

+ s->chan[i].dest = 0;

+ s->chan[i].lli = 0;

+ s->chan[i].ctrl = 0;

+ s->chan[i].conf = 0;

+}

+

static void pl080_init(Object *obj)

SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

@@ -XXX,XX +XXX,XX @@ static void pl080_class_init(ObjectClass *oc, void *data)

dc->vmsd = &vmstate_pl080;

dc->realize = pl080_realize;

dc->props = pl080_properties;

+ dc->reset = pl080_reset;

}

static const TypeInfo pl080_info = {

2.18.0

The PL080 and PL081 have three outgoing interrupt lines:

* DMACINTERR signals DMA errors

* DMACINTTC is the DMA count interrupt

* DMACINTR is a combined interrupt, the logical OR of the other two

We currently only implement DMACINTR, because that's all the

realview and versatile boards needed, but the instances of the

PL081 in the MPS2 firmware images use all three interrupt lines.

Implement the missing DMACINTERR and DMACINTTC.

include/hw/dma/pl080.h | 6 +++++-

hw/dma/pl080.c | 13 ++++++++-----

2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h

--- a/include/hw/dma/pl080.h

+++ b/include/hw/dma/pl080.h

@@ -XXX,XX +XXX,XX @@

* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf

*

* QEMU interface:

- * + sysbus IRQ: DMACINTR combined interrupt line

+ * + sysbus IRQ 0: DMACINTR combined interrupt line

+ * + sysbus IRQ 1: DMACINTERR error interrupt request

+ * + sysbus IRQ 2: DMACINTTC count interrupt request

* + sysbus MMIO region 0: MemoryRegion for the device's registers

*/

@@ -XXX,XX +XXX,XX @@ typedef struct PL080State {

/* Flag to avoid recursive DMA invocations. */

int running;

qemu_irq irq;

+ qemu_irq interr;

+ qemu_irq inttc;

} PL080State;

#endif

diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/dma/pl080.c

+++ b/hw/dma/pl080.c

@@ -XXX,XX +XXX,XX @@ static const unsigned char pl081_id[] =

static void pl080_update(PL080State *s)

{

- if ((s->tc_int & s->tc_mask)

- || (s->err_int & s->err_mask))

- qemu_irq_raise(s->irq);

- else

- qemu_irq_lower(s->irq);

+ bool tclevel = (s->tc_int & s->tc_mask);

+ bool errlevel = (s->err_int & s->err_mask);

+

+ qemu_set_irq(s->interr, errlevel);

+ qemu_set_irq(s->inttc, tclevel);

+ qemu_set_irq(s->irq, errlevel || tclevel);

}

static void pl080_run(PL080State *s)

@@ -XXX,XX +XXX,XX @@ static void pl080_init(Object *obj)

memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000);

sysbus_init_mmio(sbd, &s->iomem);

sysbus_init_irq(sbd, &s->irq);

+ sysbus_init_irq(sbd, &s->interr);

+ sysbus_init_irq(sbd, &s->inttc);

s->nchannels = 8;

}

2.18.0

Currently our PL080/PL081 model uses a combination of the CPU's

address space (via cpu_physical_memory_{read,write}()) and the

system address space for performing DMA accesses.

For the PL081s in the MPS FPGA images, their DMA accesses

must go via Master Security Controllers. Switch the

PL080/PL081 model to take a MemoryRegion property which

defines its downstream for making DMA accesses.

Since the PL08x are only used in two board models, we

make provision of the 'downstream' link mandatory and convert

both users at once, rather than having it be optional with

a default to the system address space.

include/hw/dma/pl080.h | 5 +++++

hw/arm/realview.c | 8 +++++++-

hw/arm/versatilepb.c | 9 ++++++++-

hw/dma/pl080.c | 35 +++++++++++++++++++++++++++++------

4 files changed, 49 insertions(+), 8 deletions(-)

diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h

--- a/include/hw/dma/pl080.h

+++ b/include/hw/dma/pl080.h

#ifndef HW_DMA_PL080_H

@@ -XXX,XX +XXX,XX @@ typedef struct PL080State {

qemu_irq irq;

qemu_irq interr;

qemu_irq inttc;

+ MemoryRegion *downstream;

+ AddressSpace downstream_as;

} PL080State;

#endif

diff --git a/hw/arm/realview.c b/hw/arm/realview.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/realview.c

+++ b/hw/arm/realview.c

@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,

pl011_create(0x1000c000, pic[15], serial_hd(3));

/* DMA controller is optional, apparently. */

- sysbus_create_simple("pl081", 0x10030000, pic[24]);

+ dev = qdev_create(NULL, "pl081");

+ object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",

+ &error_fatal);

+ qdev_init_nofail(dev);

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, 0x10030000);

+ sysbus_connect_irq(busdev, 0, pic[24]);

sysbus_create_simple("sp804", 0x10011000, pic[4]);

sysbus_create_simple("sp804", 0x10012000, pic[5]);

diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/versatilepb.c

+++ b/hw/arm/versatilepb.c

@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)

pl011_create(0x101f3000, pic[14], serial_hd(2));

pl011_create(0x10009000, sic[6], serial_hd(3));

- sysbus_create_simple("pl080", 0x10130000, pic[17]);

+ dev = qdev_create(NULL, "pl080");

+ object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream",

+ &error_fatal);

+ qdev_init_nofail(dev);

+ busdev = SYS_BUS_DEVICE(dev);

+ sysbus_mmio_map(busdev, 0, 0x10130000);

+ sysbus_connect_irq(busdev, 0, pic[17]);

sysbus_create_simple("sp804", 0x101e2000, pic[4]);

sysbus_create_simple("sp804", 0x101e3000, pic[5]);

diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/dma/pl080.c

+++ b/hw/dma/pl080.c

@@ -XXX,XX +XXX,XX @@

#include "exec/address-spaces.h"

#include "qemu/log.h"

#include "hw/dma/pl080.h"

+#include "qapi/error.h"

#define PL080_CONF_E 0x1

#define PL080_CONF_M1 0x2

@@ -XXX,XX +XXX,XX @@ again:

swidth = 1 << ((ch->ctrl >> 18) & 7);

dwidth = 1 << ((ch->ctrl >> 21) & 7);

for (n = 0; n < dwidth; n+= swidth) {

- cpu_physical_memory_read(ch->src, buff + n, swidth);

+ address_space_read(&s->downstream_as, ch->src,

+ MEMTXATTRS_UNSPECIFIED, buff + n, swidth);

if (ch->ctrl & PL080_CCTRL_SI)

ch->src += swidth;

}

xsize = (dwidth < swidth) ? swidth : dwidth;

/* ??? This may pad the value incorrectly for dwidth < 32. */

for (n = 0; n < xsize; n += dwidth) {

- cpu_physical_memory_write(ch->dest + n, buff + n, dwidth);

+ address_space_write(&s->downstream_as, ch->dest + n,

+ MEMTXATTRS_UNSPECIFIED, buff + n, dwidth);

if (ch->ctrl & PL080_CCTRL_DI)

ch->dest += swidth;

}

@@ -XXX,XX +XXX,XX @@ again:

if (size == 0) {

/* Transfer complete. */

if (ch->lli) {

- ch->src = address_space_ldl_le(&address_space_memory,

+ ch->src = address_space_ldl_le(&s->downstream_as,

ch->lli,

MEMTXATTRS_UNSPECIFIED,

NULL);

- ch->dest = address_space_ldl_le(&address_space_memory,

+ ch->dest = address_space_ldl_le(&s->downstream_as,

ch->lli + 4,

MEMTXATTRS_UNSPECIFIED,

NULL);

- ch->ctrl = address_space_ldl_le(&address_space_memory,

+ ch->ctrl = address_space_ldl_le(&s->downstream_as,

ch->lli + 12,

MEMTXATTRS_UNSPECIFIED,

NULL);

- ch->lli = address_space_ldl_le(&address_space_memory,

+ ch->lli = address_space_ldl_le(&s->downstream_as,

ch->lli + 8,

MEMTXATTRS_UNSPECIFIED,

NULL);

@@ -XXX,XX +XXX,XX @@ static void pl080_init(Object *obj)

s->nchannels = 8;

}

+static void pl080_realize(DeviceState *dev, Error **errp)

+{

+ PL080State *s = PL080(dev);

+

+ if (!s->downstream) {

+ error_setg(errp, "PL080 'downstream' link not set");

+ return;

+ address_space_init(&s->downstream_as, s->downstream, "pl080-downstream");

+

static void pl081_init(Object *obj)

PL080State *s = PL080(obj);

@@ -XXX,XX +XXX,XX @@ static void pl081_init(Object *obj)

s->nchannels = 2;

+static Property pl080_properties[] = {

+ DEFINE_PROP_LINK("downstream", PL080State, downstream,

+ TYPE_MEMORY_REGION, MemoryRegion *),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

static void pl080_class_init(ObjectClass *oc, void *data)

DeviceClass *dc = DEVICE_CLASS(oc);

dc->vmsd = &vmstate_pl080;

+ dc->realize = pl080_realize;

+ dc->props = pl080_properties;

}

static const TypeInfo pl080_info = {

2.18.0

The mmio_interface device was a purely internal artifact

of the implementation of the memory subsystem's request_ptr

APIs. Now that we have removed those APIs, we can remove

the mmio_interface device too.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>

Message-id: 20180817114619.22354-4-peter.maydell@linaro.org

hw/misc/Makefile.objs | 1 -

include/hw/misc/mmio_interface.h | 49 -----------

hw/misc/mmio_interface.c | 135 -------------------------------

3 files changed, 185 deletions(-)

delete mode 100644 include/hw/misc/mmio_interface.h

delete mode 100644 hw/misc/mmio_interface.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_PVPANIC) += pvpanic.o

obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o

obj-$(CONFIG_AUX) += auxbus.o

obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o

-obj-y += mmio_interface.o

obj-$(CONFIG_MSF2) += msf2-sysreg.o

diff --git a/include/hw/misc/mmio_interface.h b/include/hw/misc/mmio_interface.h

deleted file mode 100644

index XXXXXXX..XXXXXXX

--- a/include/hw/misc/mmio_interface.h

+++ /dev/null

@@ -XXX,XX +XXX,XX @@

-/*

- * mmio_interface.h

- *

- * Copyright (C) 2017 : GreenSocs

- * http://www.greensocs.com/ , email: info@greensocs.com

- *

- * Developed by :

- * Frederic Konrad <fred.konrad@greensocs.com>

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License as published by

- * the Free Software Foundation, either version 2 of the License, or

- * (at your option)any later version.

- *

- * This program is distributed in the hope that it will be useful,

- * but WITHOUT ANY WARRANTY; without even the implied warranty of

- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

- * GNU General Public License for more details.

- *

- * You should have received a copy of the GNU General Public License along

- * with this program; if not, see <http://www.gnu.org/licenses/>.

- *

- */

-

-#ifndef MMIO_INTERFACE_H

-#define MMIO_INTERFACE_H

-

-#include "exec/memory.h"

-

-#define TYPE_MMIO_INTERFACE "mmio_interface"

-#define MMIO_INTERFACE(obj) OBJECT_CHECK(MMIOInterface, (obj), \

- TYPE_MMIO_INTERFACE)

-

-typedef struct MMIOInterface {

- DeviceState parent_obj;

-

- MemoryRegion *subregion;

- MemoryRegion ram_mem;

- uint64_t start;

- uint64_t end;

- bool ro;

- uint64_t id;

- void *host_ptr;

-} MMIOInterface;

-

-void mmio_interface_map(MMIOInterface *s);

-void mmio_interface_unmap(MMIOInterface *s);

-

-#endif /* MMIO_INTERFACE_H */

diff --git a/hw/misc/mmio_interface.c b/hw/misc/mmio_interface.c

deleted file mode 100644

index XXXXXXX..XXXXXXX

--- a/hw/misc/mmio_interface.c

+++ /dev/null

@@ -XXX,XX +XXX,XX @@

-/*

- * mmio_interface.c

- *

- * Copyright (C) 2017 : GreenSocs

- * http://www.greensocs.com/ , email: info@greensocs.com

- *

- * Developed by :

- * Frederic Konrad <fred.konrad@greensocs.com>

- *

- * This program is free software; you can redistribute it and/or modify

- * it under the terms of the GNU General Public License as published by

- * the Free Software Foundation, either version 2 of the License, or

- * (at your option)any later version.

- *

- * This program is distributed in the hope that it will be useful,

- * but WITHOUT ANY WARRANTY; without even the implied warranty of

- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

- * GNU General Public License for more details.

- *

- * You should have received a copy of the GNU General Public License along

- * with this program; if not, see <http://www.gnu.org/licenses/>.

- *

- */

-

-#include "qemu/osdep.h"

-#include "qemu/log.h"

-#include "trace.h"

-#include "hw/qdev-properties.h"

-#include "hw/misc/mmio_interface.h"

-#include "qapi/error.h"

-

-#ifndef DEBUG_MMIO_INTERFACE

-#define DEBUG_MMIO_INTERFACE 0

-#endif

-

-static uint64_t mmio_interface_counter;

-

-#define DPRINTF(fmt, ...) do { \

- if (DEBUG_MMIO_INTERFACE) { \

- qemu_log("mmio_interface: 0x%" PRIX64 ": " fmt, s->id, ## __VA_ARGS__);\

- } \

-} while (0)

-

-static void mmio_interface_init(Object *obj)

-{

- MMIOInterface *s = MMIO_INTERFACE(obj);

-

- if (DEBUG_MMIO_INTERFACE) {

- s->id = mmio_interface_counter++;

- }

-

- DPRINTF("interface created\n");

- s->host_ptr = 0;

- s->subregion = 0;

-}

-

-static void mmio_interface_realize(DeviceState *dev, Error **errp)

-{

- MMIOInterface *s = MMIO_INTERFACE(dev);

-

- DPRINTF("realize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer"

- " %p\n", s->start, s->end, s->host_ptr);

-

- if (!s->host_ptr) {

- error_setg(errp, "host_ptr property must be set");

- return;

- }

-

- if (!s->subregion) {

- error_setg(errp, "subregion property must be set");

- return;

- }

-

- memory_region_init_ram_ptr(&s->ram_mem, OBJECT(s), "ram",

- s->end - s->start + 1, s->host_ptr);

- memory_region_set_readonly(&s->ram_mem, s->ro);

- memory_region_add_subregion(s->subregion, s->start, &s->ram_mem);

-}

-

-static void mmio_interface_unrealize(DeviceState *dev, Error **errp)

-{

- MMIOInterface *s = MMIO_INTERFACE(dev);

-

- DPRINTF("unrealize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer"

- " %p\n", s->start, s->end, s->host_ptr);

- memory_region_del_subregion(s->subregion, &s->ram_mem);

-}

-

-static void mmio_interface_finalize(Object *obj)

-{

- MMIOInterface *s = MMIO_INTERFACE(obj);

-

- DPRINTF("finalize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer"

- " %p\n", s->start, s->end, s->host_ptr);

- object_unparent(OBJECT(&s->ram_mem));

-}

-

-static Property mmio_interface_properties[] = {

- DEFINE_PROP_UINT64("start", MMIOInterface, start, 0),

- DEFINE_PROP_UINT64("end", MMIOInterface, end, 0),

- DEFINE_PROP_PTR("host_ptr", MMIOInterface, host_ptr),

- DEFINE_PROP_BOOL("ro", MMIOInterface, ro, false),

- DEFINE_PROP_MEMORY_REGION("subregion", MMIOInterface, subregion),

- DEFINE_PROP_END_OF_LIST(),

-};

-

-static void mmio_interface_class_init(ObjectClass *oc, void *data)

-{

- DeviceClass *dc = DEVICE_CLASS(oc);

-

- dc->realize = mmio_interface_realize;

- dc->unrealize = mmio_interface_unrealize;

- dc->props = mmio_interface_properties;

- /* Reason: pointer property "host_ptr", and this device

- * is an implementation detail of the memory subsystem,

- * not intended to be created directly by the user.

- */

- dc->user_creatable = false;

-}

-

-static const TypeInfo mmio_interface_info = {

- .name = TYPE_MMIO_INTERFACE,

- .parent = TYPE_DEVICE,

- .instance_size = sizeof(MMIOInterface),

- .instance_init = mmio_interface_init,

- .instance_finalize = mmio_interface_finalize,

- .class_init = mmio_interface_class_init,

-};

-

-static void mmio_interface_register_types(void)

-{

- type_register_static(&mmio_interface_info);

-}

-

-type_init(mmio_interface_register_types)

2.18.0

Remove the obsolete MMIO request_ptr APIs; they have no

users now.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>

Message-id: 20180817114619.22354-3-peter.maydell@linaro.org

include/exec/memory.h | 35 --------------

memory.c | 110 ------------------------------------------

2 files changed, 145 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h

--- a/include/exec/memory.h

+++ b/include/exec/memory.h

@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {

uint64_t data,

unsigned size,

MemTxAttrs attrs);

- /* Instruction execution pre-callback:

- * @addr is the address of the access relative to the @mr.

- * @size is the size of the area returned by the callback.

- * @offset is the location of the pointer inside @mr.

- *

- * Returns a pointer to a location which contains guest code.

- */

- void *(*request_ptr)(void *opaque, hwaddr addr, unsigned *size,

- unsigned *offset);

enum device_endian endianness;

/* Guest-visible constraints: */

@@ -XXX,XX +XXX,XX @@ void memory_global_dirty_log_stop(void);

void mtree_info(fprintf_function mon_printf, void *f, bool flatview,

bool dispatch_tree, bool owner);

-/**

- * memory_region_request_mmio_ptr: request a pointer to an mmio

- * MemoryRegion. If it is possible map a RAM MemoryRegion with this pointer.

- * When the device wants to invalidate the pointer it will call

- * memory_region_invalidate_mmio_ptr.

- *

- * @mr: #MemoryRegion to check

- * @addr: address within that region

- *

- * Returns true on success, false otherwise.

- */

-bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr);

-

-/**

- * memory_region_invalidate_mmio_ptr: invalidate the pointer to an mmio

- * previously requested.

- * In the end that means that if something wants to execute from this area it

- * will need to request the pointer again.

- *

- * @mr: #MemoryRegion associated to the pointer.

- * @offset: offset within the memory region

- * @size: size of that area.

- */

-void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,

- unsigned size);

-

/**

* memory_region_dispatch_read: perform a read directly to the specified

* MemoryRegion.

diff --git a/memory.c b/memory.c

--- a/memory.c

+++ b/memory.c

@@ -XXX,XX +XXX,XX @@

#include "exec/ram_addr.h"

#include "sysemu/kvm.h"

#include "sysemu/sysemu.h"

-#include "hw/misc/mmio_interface.h"

#include "hw/qdev-properties.h"

#include "migration/vmstate.h"

@@ -XXX,XX +XXX,XX @@ void memory_listener_unregister(MemoryListener *listener)

listener->address_space = NULL;

-bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)

- void *host;

- unsigned size = 0;

- unsigned offset = 0;

- Object *new_interface;

-

- if (!mr || !mr->ops->request_ptr) {

- return false;

- }

-

- /*

- * Avoid an update if the request_ptr call

- * memory_region_invalidate_mmio_ptr which seems to be likely when we use

- * a cache.

- */

- memory_region_transaction_begin();

-

- host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);

-

- if (!host || !size) {

- memory_region_transaction_commit();

- return false;

- }

-

- new_interface = object_new("mmio_interface");

- qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);

- qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);

- qdev_prop_set_bit(DEVICE(new_interface), "ro", true);

- qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);

- qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);

- object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);

-

- memory_region_transaction_commit();

- return true;

-typedef struct MMIOPtrInvalidate {

- MemoryRegion *mr;

- hwaddr offset;

- unsigned size;

- int busy;

- int allocated;

-} MMIOPtrInvalidate;

-

-#define MAX_MMIO_INVALIDATE 10

-static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];

-

-static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,

- run_on_cpu_data data)

- MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;

- MemoryRegion *mr = invalidate_data->mr;

- hwaddr offset = invalidate_data->offset;

- unsigned size = invalidate_data->size;

- MemoryRegionSection section = memory_region_find(mr, offset, size);

-

- qemu_mutex_lock_iothread();

-

- /* Reset dirty so this doesn't happen later. */

- cpu_physical_memory_test_and_clear_dirty(offset, size, 1);

-

- if (section.mr != mr) {

- /* memory_region_find add a ref on section.mr */

- memory_region_unref(section.mr);

- if (MMIO_INTERFACE(section.mr->owner)) {

- /* We found the interface just drop it. */

- object_property_set_bool(section.mr->owner, false, "realized",

- NULL);

- object_unref(section.mr->owner);

- object_unparent(section.mr->owner);

- }

- }

-

- qemu_mutex_unlock_iothread();

-

- if (invalidate_data->allocated) {

- g_free(invalidate_data);

- } else {

- invalidate_data->busy = 0;

- }

-void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,

- unsigned size)

-{

- size_t i;

- MMIOPtrInvalidate *invalidate_data = NULL;

-

- for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {