Some more outstanding target-arm patches; nothing terribly

exciting. Mostly they're mine; I'm trying to reduce the

number of patches I still have in flight, so I've picked

out some of the reviewed patches from a couple of sets I've

sent out and will resend v2 versions of those sets with the

remaining patches with fixes for issues noted in review once

this is in master.

The following changes since commit adaec191bfb31e12d40af8ab1b869f5b40d61ee9:

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2018-08-20 09:48:03 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180820

for you to fetch changes up to b85fad1588e812566f897f747e38da345a7016d6:

hw/dma/pl080: Remove hw_error() if DMA is enabled (2018-08-20 11:24:33 +0100)

* Fix crash on conditional instruction in an IT block

* docs/generic-loader: mention U-Boot and Intel HEX executable formats

* hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset

* imx_serial: Generate interrupt on receive data ready if enabled

* Fix various minor bugs in AArch32 Hyp related coprocessor registers

* Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)

* Implement AArch32 ERET instruction

* hw/arm/virt: Add virt-3.1 machine type

* sdhci: add i.MX SD Stable Clock bit

* Remove now-obsolete MMIO request_ptr APIs

* hw/timer/m48t59: Move away from old_mmio accessors

* hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module

* nvic: Expose NMI line

* hw/dma/pl080: cleanups and new features required for use in MPS boards

Andrew Jones (1):

hw/arm/virt: Add virt-3.1 machine type

Hans-Erik Floryd (2):

imx_serial: Generate interrupt on receive data ready if enabled

sdhci: add i.MX SD Stable Clock bit

Jia He (1):

hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset

Peter Maydell (19):

target/arm: Correct typo in HAMAIR1 regdef name

target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs

target/arm: Implement AArch32 HVBAR

target/arm: Implement AArch32 Hyp FARs

target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2

target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)

target/arm: Implement AArch32 ERET instruction

hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code

memory: Remove MMIO request_ptr APIs

hw/misc: Remove mmio_interface device

hw/timer/m48t59: Move away from old_mmio accessors

hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module

nvic: Expose NMI line

hw/dma/pl080: Allow use as embedded-struct device

hw/dma/pl080: Support all three interrupt lines

hw/dma/pl080: Don't use CPU address space for DMA accesses

hw/dma/pl080: Provide device reset function

hw/dma/pl080: Correct bug in register address decode logic

hw/dma/pl080: Remove hw_error() if DMA is enabled

Roman Kapl (1):

target/arm: Fix crash on conditional instruction in an IT block

Stefan Hajnoczi (1):

docs/generic-loader: mention U-Boot and Intel HEX executable formats

The Arm Cortex-M System Design Kit includes a simple watchdog module

based on a 32-bit down-counter. Implement this.

Makefile.objs | 1 +

hw/watchdog/Makefile.objs | 1 +

include/hw/watchdog/cmsdk-apb-watchdog.h | 59 ++++

hw/watchdog/cmsdk-apb-watchdog.c | 326 +++++++++++++++++++++++

MAINTAINERS | 2 +

default-configs/arm-softmmu.mak | 1 +

hw/watchdog/trace-events | 6 +

7 files changed, 396 insertions(+)

create mode 100644 include/hw/watchdog/cmsdk-apb-watchdog.h

create mode 100644 hw/watchdog/cmsdk-apb-watchdog.c

create mode 100644 hw/watchdog/trace-events

diff --git a/Makefile.objs b/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/Makefile.objs

+++ b/Makefile.objs

@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/tpm

trace-events-subdirs += hw/usb

trace-events-subdirs += hw/vfio

trace-events-subdirs += hw/virtio

+trace-events-subdirs += hw/watchdog

trace-events-subdirs += hw/xen

trace-events-subdirs += io

trace-events-subdirs += linux-user

diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/Makefile.objs

+++ b/hw/watchdog/Makefile.objs

@@ -XXX,XX +XXX,XX @@

common-obj-y += watchdog.o

+common-obj-$(CONFIG_CMSDK_APB_WATCHDOG) += cmsdk-apb-watchdog.o

common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o

common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o

common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o

diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h

+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h

+ * ARM CMSDK APB watchdog emulation

+ *

+ * Copyright (c) 2018 Linaro Limited

+ * Written by Peter Maydell

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+/*

+ * This is a model of the "APB watchdog" which is part of the Cortex-M

+ * System Design Kit (CMSDK) and documented in the Cortex-M System

+ * Design Kit Technical Reference Manual (ARM DDI0479C):

+ * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit

+ *

+ * QEMU interface:

+ * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked

+ * + sysbus MMIO region 0: the register bank

+ * + sysbus IRQ 0: watchdog interrupt

+ *

+ * In real hardware the watchdog's reset output is just a GPIO line

+ * which can then be masked by the board or treated as a simple interrupt.

+ * (For instance the IoTKit does this with the non-secure watchdog, so that

+ * secure code can control whether non-secure code can perform a system

+ * reset via its watchdog.) In QEMU, we just wire up the watchdog reset

+ * to watchdog_perform_action(), at least for the moment.

+ */

+

+#ifndef CMSDK_APB_WATCHDOG_H

+#define CMSDK_APB_WATCHDOG_H

+

+#include "hw/sysbus.h"

+#include "hw/ptimer.h"

+

+#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"

+#define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \

+ TYPE_CMSDK_APB_WATCHDOG)

+

+typedef struct CMSDKAPBWatchdog {

+ MemoryRegion iomem;

+ qemu_irq wdogint;

+ uint32_t wdogclk_frq;

+ struct ptimer_state *timer;

+

+ uint32_t control;

+ uint32_t intstatus;

+ uint32_t lock;

+ uint32_t itcr;

+ uint32_t itop;

+ uint32_t resetstatus;

+} CMSDKAPBWatchdog;

diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c

+++ b/hw/watchdog/cmsdk-apb-watchdog.c

+ * ARM CMSDK APB watchdog emulation

+ *

+ * Copyright (c) 2018 Linaro Limited

+ * Written by Peter Maydell

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+#include "qemu/main-loop.h"

+#include "sysemu/watchdog.h"

+#include "hw/sysbus.h"

+#include "hw/registerfields.h"

+#include "hw/watchdog/cmsdk-apb-watchdog.h"

+

+REG32(WDOGLOAD, 0x0)

+REG32(WDOGVALUE, 0x4)

+REG32(WDOGCONTROL, 0x8)

+ FIELD(WDOGCONTROL, INTEN, 0, 1)

+ FIELD(WDOGCONTROL, RESEN, 1, 1)

+#define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \

+ R_WDOGCONTROL_RESEN_MASK)

+REG32(WDOGINTCLR, 0xc)

+REG32(WDOGRIS, 0x10)

+ FIELD(WDOGRIS, INT, 0, 1)

+REG32(WDOGMIS, 0x14)

+REG32(WDOGLOCK, 0xc00)

+#define WDOG_UNLOCK_VALUE 0x1ACCE551

+REG32(WDOGITCR, 0xf00)

+ FIELD(WDOGITCR, ENABLE, 0, 1)

+#define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK

+REG32(WDOGITOP, 0xf04)

+ FIELD(WDOGITOP, WDOGRES, 0, 1)

+ FIELD(WDOGITOP, WDOGINT, 1, 1)

+#define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \

+ R_WDOGITOP_WDOGINT_MASK)

+REG32(PID4, 0xfd0)

+REG32(PID5, 0xfd4)

+REG32(PID6, 0xfd8)

+REG32(PID7, 0xfdc)

+REG32(PID0, 0xfe0)

+REG32(PID1, 0xfe4)

+REG32(PID2, 0xfe8)

+REG32(PID3, 0xfec)

+REG32(CID0, 0xff0)

+REG32(CID1, 0xff4)

+REG32(CID2, 0xff8)

+REG32(CID3, 0xffc)

+

+/* PID/CID values */

+static const int watchdog_id[] = {

+ 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */

+ 0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */

+ 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */

+};

+

+static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)

+ /* Return masked interrupt status */

+ return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);

+static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)

+ /* Return masked reset status */

+ return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);

+static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)

+{

+ bool wdogint;

+ bool wdogres;

+

+ if (s->itcr) {

+ wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;

+ wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;

+ } else {

+ wdogint = cmsdk_apb_watchdog_intstatus(s);

+ wdogres = cmsdk_apb_watchdog_resetstatus(s);

+ }

+

+ qemu_set_irq(s->wdogint, wdogint);

+ if (wdogres) {

+ watchdog_perform_action();

+ }

+}

+

+static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);

+ uint64_t r;

+

+ switch (offset) {

+ case A_WDOGLOAD:

+ r = ptimer_get_limit(s->timer);

+ break;

+ case A_WDOGVALUE:

+ r = ptimer_get_count(s->timer);

+ break;

+ case A_WDOGCONTROL:

+ r = s->control;

+ break;

+ case A_WDOGRIS:

+ r = s->intstatus;

+ break;

+ case A_WDOGMIS:

+ r = cmsdk_apb_watchdog_intstatus(s);

+ break;

+ case A_WDOGLOCK:

+ r = s->lock;

+ break;

+ case A_WDOGITCR:

+ r = s->itcr;

+ break;

+ case A_PID4 ... A_CID3:

+ r = watchdog_id[(offset - A_PID4) / 4];

+ break;

+ case A_WDOGINTCLR:

+ case A_WDOGITOP:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "CMSDK APB watchdog read: read of WO offset %x\n",

+ (int)offset);

+ r = 0;

+ break;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "CMSDK APB watchdog read: bad offset %x\n", (int)offset);

+ r = 0;

+ break;

+ }

+ trace_cmsdk_apb_watchdog_read(offset, r, size);

+ return r;

+}

+

+static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);

+

+ trace_cmsdk_apb_watchdog_write(offset, value, size);

+

+ if (s->lock && offset != A_WDOGLOCK) {

+ /* Write access is disabled via WDOGLOCK */

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "CMSDK APB watchdog write: write to locked watchdog\n");

+ return;

+ }

+

+ switch (offset) {

+ case A_WDOGLOAD:

+ /*

+ * Reset the load value and the current count, and make sure

+ * we're counting.

+ */

+ ptimer_set_limit(s->timer, value, 1);

+ ptimer_run(s->timer, 0);

+ break;

+ case A_WDOGCONTROL:

+ s->control = value & R_WDOGCONTROL_VALID_MASK;

+ cmsdk_apb_watchdog_update(s);

+ break;

+ case A_WDOGINTCLR:

+ s->intstatus = 0;

+ ptimer_set_count(s->timer, ptimer_get_limit(s->timer));

+ cmsdk_apb_watchdog_update(s);

+ break;

+ case A_WDOGLOCK:

+ s->lock = (value != WDOG_UNLOCK_VALUE);

+ break;

+ case A_WDOGITCR:

+ s->itcr = value & R_WDOGITCR_VALID_MASK;

+ cmsdk_apb_watchdog_update(s);

+ break;

+ case A_WDOGITOP:

+ s->itop = value & R_WDOGITOP_VALID_MASK;

+ cmsdk_apb_watchdog_update(s);

+ break;

+ case A_WDOGVALUE:

+ case A_WDOGRIS:

+ case A_WDOGMIS:

+ case A_PID4 ... A_CID3:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "CMSDK APB watchdog write: write to RO offset 0x%x\n",

+ (int)offset);

+ break;

+ default:

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "CMSDK APB watchdog write: bad offset 0x%x\n",

+ (int)offset);

+ break;

+ }

+}

+

+static const MemoryRegionOps cmsdk_apb_watchdog_ops = {

+ .read = cmsdk_apb_watchdog_read,

+ .write = cmsdk_apb_watchdog_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+ /* byte/halfword accesses are just zero-padded on reads and writes */

+ .impl.min_access_size = 4,

+ .impl.max_access_size = 4,

+ .valid.min_access_size = 1,

+ .valid.max_access_size = 4,

+};

+

+static void cmsdk_apb_watchdog_tick(void *opaque)

+{

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);

+

+ if (!s->intstatus) {

+ /* Count expired for the first time: raise interrupt */

+ s->intstatus = R_WDOGRIS_INT_MASK;

+ } else {

+ /* Count expired for the second time: raise reset and stop clock */

+ s->resetstatus = 1;

+ ptimer_stop(s->timer);

+ }

+ cmsdk_apb_watchdog_update(s);

+}

+

+static void cmsdk_apb_watchdog_reset(DeviceState *dev)

+{

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);

+

+ trace_cmsdk_apb_watchdog_reset();

+ s->control = 0;

+ s->intstatus = 0;

+ s->lock = 0;

+ s->itcr = 0;

+ s->itop = 0;

+ s->resetstatus = 0;

+ /* Set the limit and the count */

+ ptimer_set_limit(s->timer, 0xffffffff, 1);

+ ptimer_run(s->timer, 0);

+}

+

+static void cmsdk_apb_watchdog_init(Object *obj)

+{

+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);

+

+ memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,

+ s, "cmsdk-apb-watchdog", 0x1000);

+ sysbus_init_mmio(sbd, &s->iomem);

+ sysbus_init_irq(sbd, &s->wdogint);

+}

+

+static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)

+{

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);

+ QEMUBH *bh;

+

+ if (s->wdogclk_frq == 0) {

+ error_setg(errp,

+ "CMSDK APB watchdog: wdogclk-frq property must be set");

+ return;

+ }

+

+ bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s);

+ s->timer = ptimer_init(bh,

+ PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |

+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |

+ PTIMER_POLICY_NO_IMMEDIATE_RELOAD |

+ PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);

+

+ ptimer_set_freq(s->timer, s->wdogclk_frq);

+}

+

+static const VMStateDescription cmsdk_apb_watchdog_vmstate = {

+ .name = "cmsdk-apb-watchdog",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),

+ VMSTATE_UINT32(control, CMSDKAPBWatchdog),

+ VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),

+ VMSTATE_UINT32(lock, CMSDKAPBWatchdog),

+ VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),

+ VMSTATE_UINT32(itop, CMSDKAPBWatchdog),

+ VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+static Property cmsdk_apb_watchdog_properties[] = {

+ DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),

+static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)

+ dc->realize = cmsdk_apb_watchdog_realize;

+ dc->vmsd = &cmsdk_apb_watchdog_vmstate;

+ dc->reset = cmsdk_apb_watchdog_reset;

+ dc->props = cmsdk_apb_watchdog_properties;

+static const TypeInfo cmsdk_apb_watchdog_info = {

+ .name = TYPE_CMSDK_APB_WATCHDOG,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(CMSDKAPBWatchdog),

+ .instance_init = cmsdk_apb_watchdog_init,

+ .class_init = cmsdk_apb_watchdog_class_init,

+static void cmsdk_apb_watchdog_register_types(void)

+ type_register_static(&cmsdk_apb_watchdog_info);

+type_init(cmsdk_apb_watchdog_register_types);

@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c

F: include/hw/timer/cmsdk-apb-timer.h

F: hw/char/cmsdk-apb-uart.c

F: include/hw/char/cmsdk-apb-uart.h

+F: hw/watchdog/cmsdk-apb-watchdog.c

+F: include/hw/watchdog/cmsdk-apb-watchdog.h

F: hw/misc/tz-ppc.c

F: include/hw/misc/tz-ppc.h

F: hw/misc/tz-mpc.c

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak

--- a/default-configs/arm-softmmu.mak

+++ b/default-configs/arm-softmmu.mak

@@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y

CONFIG_CMSDK_APB_TIMER=y

CONFIG_CMSDK_APB_UART=y

+CONFIG_CMSDK_APB_WATCHDOG=y

CONFIG_MPS2_FPGAIO=y

CONFIG_MPS2_SCC=y

diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/watchdog/trace-events

@@ -XXX,XX +XXX,XX @@

+# See docs/devel/tracing.txt for syntax documentation.

+

+# hw/char/cmsdk_apb_watchdog.c

+cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

+cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"

+cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset"

2.18.0

Create a new include file for the pl081's device struct,

type macros, etc, so that it can be instantiated using

the "embedded struct" coding style.

include/hw/dma/pl080.h | 62 ++++++++++++++++++++++++++++++++++++++++++

hw/dma/pl080.c | 34 ++---------------------

MAINTAINERS | 1 +

3 files changed, 65 insertions(+), 32 deletions(-)

create mode 100644 include/hw/dma/pl080.h

diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h

+++ b/include/hw/dma/pl080.h

+ * ARM PrimeCell PL080/PL081 DMA controller

+ * Copyright (c) 2006 CodeSourcery.

+ * Copyright (c) 2018 Linaro Limited

+ * Written by Paul Brook, Peter Maydell

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 or

+ * (at your option) any later version.

+/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:

+ * The PL080 TRM is:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf

+ * and the PL081 TRM is:

+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf

+ *

+ * QEMU interface:

+ * + sysbus IRQ: DMACINTR combined interrupt line

+ * + sysbus MMIO region 0: MemoryRegion for the device's registers

+ */

+#ifndef HW_DMA_PL080_H

+#define HW_DMA_PL080_H

+#include "hw/sysbus.h"

+#define PL080_MAX_CHANNELS 8

+typedef struct {

+ uint32_t src;

+ uint32_t dest;

+ uint32_t lli;

+ uint32_t ctrl;

+ uint32_t conf;

+} pl080_channel;

+#define TYPE_PL080 "pl080"

+#define TYPE_PL081 "pl081"

+#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)

+typedef struct PL080State {

+ SysBusDevice parent_obj;

+ MemoryRegion iomem;

+ uint8_t tc_int;

+ uint8_t tc_mask;

+ uint8_t err_int;

+ uint8_t err_mask;

+ uint32_t conf;

+ uint32_t sync;

+ uint32_t req_single;

+ uint32_t req_burst;

+ pl080_channel chan[PL080_MAX_CHANNELS];

+ int nchannels;

+ /* Flag to avoid recursive DMA invocations. */

+ int running;

+ qemu_irq irq;

+} PL080State;

+#endif

diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/dma/pl080.c

+++ b/hw/dma/pl080.c

@@ -XXX,XX +XXX,XX @@

#include "hw/sysbus.h"

#include "exec/address-spaces.h"

#include "qemu/log.h"

+#include "hw/dma/pl080.h"

-#define PL080_MAX_CHANNELS 8

#define PL080_CONF_E 0x1

#define PL080_CONF_M1 0x2

#define PL080_CONF_M2 0x4

@@ -XXX,XX +XXX,XX @@

#define PL080_CCTRL_D 0x02000000

#define PL080_CCTRL_S 0x01000000

-typedef struct {

- uint32_t src;

- uint32_t dest;

- uint32_t lli;

- uint32_t ctrl;

- uint32_t conf;

-} pl080_channel;

-

-#define TYPE_PL080 "pl080"

-#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)

-

-typedef struct PL080State {

- SysBusDevice parent_obj;

-

- MemoryRegion iomem;

- uint8_t tc_int;

- uint8_t tc_mask;

- uint8_t err_int;

- uint8_t err_mask;

- uint32_t conf;

- uint32_t sync;

- uint32_t req_single;

- uint32_t req_burst;

- pl080_channel chan[PL080_MAX_CHANNELS];

- int nchannels;

- /* Flag to avoid recursive DMA invocations. */

- int running;

- qemu_irq irq;

-} PL080State;

-

static const VMStateDescription vmstate_pl080_channel = {

.name = "pl080_channel",

.version_id = 1,

@@ -XXX,XX +XXX,XX @@ static const TypeInfo pl080_info = {

};

static const TypeInfo pl081_info = {

- .name = "pl081",

+ .name = TYPE_PL081,

.parent = TYPE_PL080,

.instance_init = pl081_init,

};

@@ -XXX,XX +XXX,XX @@ F: hw/char/pl011.c

F: include/hw/char/pl011.h

F: hw/display/pl110*

F: hw/dma/pl080.c

+F: include/hw/dma/pl080.h

F: hw/dma/pl330.c

F: hw/gpio/pl061.c

F: hw/input/pl050.c

2.18.0

From: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>

Generate an interrupt if USR2_RDR and UCR4_DREN are both set.

Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>

Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

include/hw/char/imx_serial.h | 1 +

hw/char/imx_serial.c | 3 ++-

2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h

--- a/include/hw/char/imx_serial.h

+++ b/include/hw/char/imx_serial.h

@@ -XXX,XX +XXX,XX @@

#define UCR2_RXEN (1<<1) /* Receiver enable */

#define UCR2_SRST (1<<0) /* Reset complete */

+#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */

#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */

#define UTS1_TXEMPTY (1<<6)

diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c

--- a/hw/char/imx_serial.c

+++ b/hw/char/imx_serial.c

@@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s)

mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;

/*

* TCEN and TXDC are both bit 3

+ * RDR and DREN are both bit 0

*/

- mask |= s->ucr4 & UCR4_TCEN;

+ mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);

usr2 = s->usr2 & mask;

2.18.0

From: Stefan Hajnoczi <stefanha@redhat.com>

The generic loader device supports the U-Boot and Intel HEX executable

formats in addition to the document raw and ELF formats. Reword the

documentation to include these formats and explain how various options

depend on the executable format.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20180816145554.9814-1-stefanha@redhat.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

docs/generic-loader.txt | 20 ++++++++++----------

1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/docs/generic-loader.txt b/docs/generic-loader.txt

--- a/docs/generic-loader.txt

+++ b/docs/generic-loader.txt

@@ -XXX,XX +XXX,XX @@ An example of setting CPU 0's PC to 0x8000 is:

Loading Files

-------------

-The loader device also allows files to be loaded into memory. It can load raw

-files and ELF executable files. Raw files are loaded verbatim. ELF executable

-files are loaded by an ELF loader. The syntax is shown below:

+The loader device also allows files to be loaded into memory. It can load ELF,

+U-Boot, and Intel HEX executable formats as well as raw images. The syntax is

+shown below:

-device loader,file=<file>[,addr=<addr>][,cpu-num=<cpu-num>][,force-raw=<raw>]

<file> - A file to be loaded into memory

- <addr> - The addr in memory that the file should be loaded. This is

- ignored if you are using an ELF (unless force-raw is true).

- This is required if you aren't loading an ELF.

+ <addr> - The memory address where the file should be loaded. This is

+ required for raw images and ignored for non-raw files.

<cpu-num> - This specifies the CPU that should be used. This is an

optional argument and will cause the CPU's PC to be set to

- where the image is stored or in the case of an ELF file to

- the value in the header. This option should only be used

- for the boot image.

+ the memory address where the raw file is loaded or the entry

+ point specified in the executable format header. This option

+ should only be used for the boot image.

This will also cause the image to be written to the specified

CPU's address space. If not specified, the default is CPU 0.

<force-raw> - Setting force-raw=on forces the file to be treated as a raw

- image. This can be used to load ELF files as if they were raw.

+ image. This can be used to load supported executable formats

+ as if they were raw.

All values are parsed using the standard QemuOps parsing. This allows the user

to specify any values in any format supported. By default the values

2.18.0

From: Jia He <hejianet@gmail.com>

In scripts/arch-run.bash of kvm-unit-tests, it will check the qemu

output log with:

if [ -z "$(echo "$errors" | grep -vi warning)" ]; then

Thus without the warning prefix, all of the test fail.

Since it is not unrecoverable error in kvm_arm_its_reset for

current implementation, downgrading the report from error to

warn makes sense.

Signed-off-by: Jia He <jia.he@hxt-semitech.com>

Message-id: 1531969910-32843-1-git-send-email-jia.he@hxt-semitech.com

hw/intc/arm_gicv3_its_kvm.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c

--- a/hw/intc/arm_gicv3_its_kvm.c

+++ b/hw/intc/arm_gicv3_its_kvm.c

@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_reset(DeviceState *dev)

- error_report("ITS KVM: full reset is not supported by the host kernel");

+ warn_report("ITS KVM: full reset is not supported by the host kernel");

if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS,

GITS_CTLR)) {

2.18.0