1 | Some more outstanding target-arm patches; nothing terribly | 1 | I might squeeze in another pullreq before softfreeze, but the |
---|---|---|---|
2 | exciting. Mostly they're mine; I'm trying to reduce the | 2 | queue was already big enough that I wanted to send this lot out now. |
3 | number of patches I still have in flight, so I've picked | ||
4 | out some of the reviewed patches from a couple of sets I've | ||
5 | sent out and will resend v2 versions of those sets with the | ||
6 | remaining patches with fixes for issues noted in review once | ||
7 | this is in master. | ||
8 | 3 | ||
9 | thanks | ||
10 | -- PMM | 4 | -- PMM |
11 | 5 | ||
6 | The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a: | ||
12 | 7 | ||
13 | The following changes since commit adaec191bfb31e12d40af8ab1b869f5b40d61ee9: | 8 | Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100) |
14 | |||
15 | Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging (2018-08-20 09:48:03 +0100) | ||
16 | 9 | ||
17 | are available in the Git repository at: | 10 | are available in the Git repository at: |
18 | 11 | ||
19 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180820 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703 |
20 | 13 | ||
21 | for you to fetch changes up to b85fad1588e812566f897f747e38da345a7016d6: | 14 | for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea: |
22 | 15 | ||
23 | hw/dma/pl080: Remove hw_error() if DMA is enabled (2018-08-20 11:24:33 +0100) | 16 | Deprecate TileGX port (2020-07-03 16:59:46 +0100) |
24 | 17 | ||
25 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
26 | target-arm queue: | 19 | target-arm queue: |
27 | * Fix crash on conditional instruction in an IT block | 20 | * i.MX6UL EVK board: put PHYs in the correct places |
28 | * docs/generic-loader: mention U-Boot and Intel HEX executable formats | 21 | * hw/arm/virt: Let the virtio-iommu bypass MSIs |
29 | * hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset | 22 | * target/arm: kvm: Handle DABT with no valid ISS |
30 | * imx_serial: Generate interrupt on receive data ready if enabled | 23 | * hw/arm/virt-acpi-build: Only expose flash on older machine types |
31 | * Fix various minor bugs in AArch32 Hyp related coprocessor registers | 24 | * target/arm: Fix temp double-free in sve ldr/str |
32 | * Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked) | 25 | * hw/display/bcm2835_fb.c: Initialize all fields of struct |
33 | * Implement AArch32 ERET instruction | 26 | * hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak |
34 | * hw/arm/virt: Add virt-3.1 machine type | 27 | * Deprecate TileGX port |
35 | * sdhci: add i.MX SD Stable Clock bit | ||
36 | * Remove now-obsolete MMIO request_ptr APIs | ||
37 | * hw/timer/m48t59: Move away from old_mmio accessors | ||
38 | * hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module | ||
39 | * nvic: Expose NMI line | ||
40 | * hw/dma/pl080: cleanups and new features required for use in MPS boards | ||
41 | 28 | ||
42 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
43 | Andrew Jones (1): | 30 | Andrew Jones (4): |
44 | hw/arm/virt: Add virt-3.1 machine type | 31 | tests/acpi: remove stale allowed tables |
32 | tests/acpi: virt: allow DSDT acpi table changes | ||
33 | hw/arm/virt-acpi-build: Only expose flash on older machine types | ||
34 | tests/acpi: virt: update golden masters for DSDT | ||
45 | 35 | ||
46 | Hans-Erik Floryd (2): | 36 | Beata Michalska (2): |
47 | imx_serial: Generate interrupt on receive data ready if enabled | 37 | target/arm: kvm: Handle DABT with no valid ISS |
48 | sdhci: add i.MX SD Stable Clock bit | 38 | target/arm: kvm: Handle misconfigured dabt injection |
49 | 39 | ||
50 | Jia He (1): | 40 | Eric Auger (5): |
51 | hw/intc/arm_gicv3_its: downgrade error_report to warn_report in kvm_arm_its_reset | 41 | qdev: Introduce DEFINE_PROP_RESERVED_REGION |
42 | virtio-iommu: Implement RESV_MEM probe request | ||
43 | virtio-iommu: Handle reserved regions in the translation process | ||
44 | virtio-iommu-pci: Add array of Interval properties | ||
45 | hw/arm/virt: Let the virtio-iommu bypass MSIs | ||
46 | |||
47 | Jean-Christophe Dubois (3): | ||
48 | Add a phy-num property to the i.MX FEC emulator | ||
49 | Add the ability to select a different PHY for each i.MX6UL FEC interface | ||
50 | Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board. | ||
52 | 51 | ||
53 | Peter Maydell (19): | 52 | Peter Maydell (19): |
54 | target/arm: Correct typo in HAMAIR1 regdef name | 53 | hw/display/bcm2835_fb.c: Initialize all fields of struct |
55 | target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs | 54 | hw/arm/spitz: Detabify |
56 | target/arm: Implement AArch32 HVBAR | 55 | hw/arm/spitz: Create SpitzMachineClass abstract base class |
57 | target/arm: Implement AArch32 Hyp FARs | 56 | hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState |
58 | target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2 | 57 | hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState |
59 | target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked) | 58 | hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals |
60 | target/arm: Implement AArch32 ERET instruction | 59 | hw/misc/max111x: provide QOM properties for setting initial values |
61 | hw/ssi/xilinx_spips: Remove unneeded MMIO request_ptr code | 60 | hw/misc/max111x: Don't use vmstate_register() |
62 | memory: Remove MMIO request_ptr APIs | 61 | ssi: Add ssi_realize_and_unref() |
63 | hw/misc: Remove mmio_interface device | 62 | hw/arm/spitz: Use max111x properties to set initial values |
64 | hw/timer/m48t59: Move away from old_mmio accessors | 63 | hw/misc/max111x: Use GPIO lines rather than max111x_set_input() |
65 | hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog module | 64 | hw/misc/max111x: Create header file for documentation, TYPE_ macros |
66 | nvic: Expose NMI line | 65 | hw/arm/spitz: Encapsulate misc GPIO handling in a device |
67 | hw/dma/pl080: Allow use as embedded-struct device | 66 | hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses |
68 | hw/dma/pl080: Support all three interrupt lines | 67 | hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses |
69 | hw/dma/pl080: Don't use CPU address space for DMA accesses | 68 | hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses |
70 | hw/dma/pl080: Provide device reset function | 69 | hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg |
71 | hw/dma/pl080: Correct bug in register address decode logic | 70 | Replace uses of FROM_SSI_SLAVE() macro with QOM casts |
72 | hw/dma/pl080: Remove hw_error() if DMA is enabled | 71 | Deprecate TileGX port |
73 | 72 | ||
74 | Roman Kapl (1): | 73 | Richard Henderson (1): |
75 | target/arm: Fix crash on conditional instruction in an IT block | 74 | target/arm: Fix temp double-free in sve ldr/str |
76 | 75 | ||
77 | Stefan Hajnoczi (1): | 76 | docs/system/deprecated.rst | 11 + |
78 | docs/generic-loader: mention U-Boot and Intel HEX executable formats | 77 | include/exec/memory.h | 6 + |
78 | include/hw/arm/fsl-imx6ul.h | 2 + | ||
79 | include/hw/arm/pxa.h | 1 - | ||
80 | include/hw/arm/sharpsl.h | 3 - | ||
81 | include/hw/arm/virt.h | 8 + | ||
82 | include/hw/misc/max111x.h | 56 +++ | ||
83 | include/hw/net/imx_fec.h | 1 + | ||
84 | include/hw/qdev-properties.h | 3 + | ||
85 | include/hw/ssi/ssi.h | 31 +- | ||
86 | include/hw/virtio/virtio-iommu.h | 2 + | ||
87 | include/qemu/typedefs.h | 1 + | ||
88 | target/arm/cpu.h | 2 + | ||
89 | target/arm/kvm_arm.h | 10 + | ||
90 | target/arm/translate-a64.h | 1 + | ||
91 | tests/qtest/bios-tables-test-allowed-diff.h | 18 - | ||
92 | hw/arm/fsl-imx6ul.c | 10 + | ||
93 | hw/arm/mcimx6ul-evk.c | 2 + | ||
94 | hw/arm/pxa2xx_pic.c | 9 +- | ||
95 | hw/arm/spitz.c | 507 ++++++++++++++++------------ | ||
96 | hw/arm/virt-acpi-build.c | 5 +- | ||
97 | hw/arm/virt.c | 33 ++ | ||
98 | hw/arm/z2.c | 11 +- | ||
99 | hw/core/qdev-properties.c | 89 +++++ | ||
100 | hw/display/ads7846.c | 9 +- | ||
101 | hw/display/bcm2835_fb.c | 4 + | ||
102 | hw/display/ssd0323.c | 10 +- | ||
103 | hw/gpio/zaurus.c | 12 +- | ||
104 | hw/misc/max111x.c | 86 +++-- | ||
105 | hw/net/imx_fec.c | 24 +- | ||
106 | hw/sd/ssi-sd.c | 4 +- | ||
107 | hw/ssi/ssi.c | 7 +- | ||
108 | hw/virtio/virtio-iommu-pci.c | 11 + | ||
109 | hw/virtio/virtio-iommu.c | 114 ++++++- | ||
110 | target/arm/kvm.c | 80 +++++ | ||
111 | target/arm/kvm32.c | 34 ++ | ||
112 | target/arm/kvm64.c | 49 +++ | ||
113 | target/arm/translate-a64.c | 6 + | ||
114 | target/arm/translate-sve.c | 8 +- | ||
115 | MAINTAINERS | 1 + | ||
116 | hw/net/trace-events | 4 +- | ||
117 | hw/virtio/trace-events | 1 + | ||
118 | tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes | ||
119 | tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes | ||
120 | tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes | ||
121 | 45 files changed, 974 insertions(+), 312 deletions(-) | ||
122 | create mode 100644 include/hw/misc/max111x.h | ||
79 | 123 | ||
80 | docs/generic-loader.txt | 20 +- | ||
81 | Makefile.objs | 1 + | ||
82 | hw/misc/Makefile.objs | 1 - | ||
83 | hw/watchdog/Makefile.objs | 1 + | ||
84 | hw/sd/sdhci-internal.h | 2 + | ||
85 | include/exec/memory.h | 35 ---- | ||
86 | include/hw/char/imx_serial.h | 1 + | ||
87 | include/hw/dma/pl080.h | 71 +++++++ | ||
88 | include/hw/misc/mmio_interface.h | 49 ----- | ||
89 | include/hw/watchdog/cmsdk-apb-watchdog.h | 59 ++++++ | ||
90 | hw/arm/armv7m.c | 1 + | ||
91 | hw/arm/realview.c | 8 +- | ||
92 | hw/arm/versatilepb.c | 9 +- | ||
93 | hw/arm/virt.c | 23 ++- | ||
94 | hw/char/imx_serial.c | 3 +- | ||
95 | hw/dma/pl080.c | 113 ++++++----- | ||
96 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | ||
97 | hw/intc/armv7m_nvic.c | 19 ++ | ||
98 | hw/misc/mmio_interface.c | 135 ------------- | ||
99 | hw/sd/sdhci.c | 8 + | ||
100 | hw/ssi/xilinx_spips.c | 46 ----- | ||
101 | hw/timer/m48t59.c | 59 ++---- | ||
102 | hw/watchdog/cmsdk-apb-watchdog.c | 326 +++++++++++++++++++++++++++++++ | ||
103 | memory.c | 110 ----------- | ||
104 | target/arm/helper.c | 36 +++- | ||
105 | target/arm/op_helper.c | 22 +-- | ||
106 | target/arm/translate.c | 76 +++++-- | ||
107 | MAINTAINERS | 3 + | ||
108 | default-configs/arm-softmmu.mak | 1 + | ||
109 | hw/intc/trace-events | 1 + | ||
110 | hw/watchdog/trace-events | 6 + | ||
111 | 31 files changed, 717 insertions(+), 530 deletions(-) | ||
112 | create mode 100644 include/hw/dma/pl080.h | ||
113 | delete mode 100644 include/hw/misc/mmio_interface.h | ||
114 | create mode 100644 include/hw/watchdog/cmsdk-apb-watchdog.h | ||
115 | delete mode 100644 hw/misc/mmio_interface.c | ||
116 | create mode 100644 hw/watchdog/cmsdk-apb-watchdog.c | ||
117 | create mode 100644 hw/watchdog/trace-events | ||
118 | diff view generated by jsdifflib |
1 | From: Jia He <hejianet@gmail.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | In scripts/arch-run.bash of kvm-unit-tests, it will check the qemu | 3 | We need a solution to use an Ethernet PHY that is not the first device |
4 | output log with: | 4 | on the MDIO bus (device 0 on MDIO bus). |
5 | if [ -z "$(echo "$errors" | grep -vi warning)" ]; then | ||
6 | 5 | ||
7 | Thus without the warning prefix, all of the test fail. | 6 | As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but |
7 | only one MDIO bus on which the 2 related PHY are connected but at unique | ||
8 | addresses. | ||
8 | 9 | ||
9 | Since it is not unrecoverable error in kvm_arm_its_reset for | 10 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
10 | current implementation, downgrading the report from error to | 11 | Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net |
11 | warn makes sense. | ||
12 | |||
13 | Signed-off-by: Jia He <jia.he@hxt-semitech.com> | ||
14 | Message-id: 1531969910-32843-1-git-send-email-jia.he@hxt-semitech.com | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 14 | --- |
18 | hw/intc/arm_gicv3_its_kvm.c | 2 +- | 15 | include/hw/net/imx_fec.h | 1 + |
19 | 1 file changed, 1 insertion(+), 1 deletion(-) | 16 | hw/net/imx_fec.c | 24 +++++++++++++++++------- |
17 | hw/net/trace-events | 4 ++-- | ||
18 | 3 files changed, 20 insertions(+), 9 deletions(-) | ||
20 | 19 | ||
21 | diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c | 20 | diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h |
22 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/intc/arm_gicv3_its_kvm.c | 22 | --- a/include/hw/net/imx_fec.h |
24 | +++ b/hw/intc/arm_gicv3_its_kvm.c | 23 | +++ b/include/hw/net/imx_fec.h |
25 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_reset(DeviceState *dev) | 24 | @@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState { |
25 | uint32_t phy_advertise; | ||
26 | uint32_t phy_int; | ||
27 | uint32_t phy_int_mask; | ||
28 | + uint32_t phy_num; | ||
29 | |||
30 | bool is_fec; | ||
31 | |||
32 | diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/net/imx_fec.c | ||
35 | +++ b/hw/net/imx_fec.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s) | ||
37 | static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
38 | { | ||
39 | uint32_t val; | ||
40 | + uint32_t phy = reg / 32; | ||
41 | |||
42 | - if (reg > 31) { | ||
43 | - /* we only advertise one phy */ | ||
44 | + if (phy != s->phy_num) { | ||
45 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n", | ||
46 | + TYPE_IMX_FEC, __func__, phy); | ||
47 | return 0; | ||
48 | } | ||
49 | |||
50 | + reg %= 32; | ||
51 | + | ||
52 | switch (reg) { | ||
53 | case 0: /* Basic Control */ | ||
54 | val = s->phy_control; | ||
55 | @@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg) | ||
56 | break; | ||
57 | } | ||
58 | |||
59 | - trace_imx_phy_read(val, reg); | ||
60 | + trace_imx_phy_read(val, phy, reg); | ||
61 | |||
62 | return val; | ||
63 | } | ||
64 | |||
65 | static void imx_phy_write(IMXFECState *s, int reg, uint32_t val) | ||
66 | { | ||
67 | - trace_imx_phy_write(val, reg); | ||
68 | + uint32_t phy = reg / 32; | ||
69 | |||
70 | - if (reg > 31) { | ||
71 | - /* we only advertise one phy */ | ||
72 | + if (phy != s->phy_num) { | ||
73 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n", | ||
74 | + TYPE_IMX_FEC, __func__, phy); | ||
26 | return; | 75 | return; |
27 | } | 76 | } |
28 | 77 | ||
29 | - error_report("ITS KVM: full reset is not supported by the host kernel"); | 78 | + reg %= 32; |
30 | + warn_report("ITS KVM: full reset is not supported by the host kernel"); | 79 | + |
31 | 80 | + trace_imx_phy_write(val, phy, reg); | |
32 | if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_ITS_REGS, | 81 | + |
33 | GITS_CTLR)) { | 82 | switch (reg) { |
83 | case 0: /* Basic Control */ | ||
84 | if (val & 0x8000) { | ||
85 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, | ||
86 | extract32(value, | ||
87 | 18, 10))); | ||
88 | } else { | ||
89 | - /* This a write operation */ | ||
90 | + /* This is a write operation */ | ||
91 | imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16)); | ||
92 | } | ||
93 | /* raise the interrupt as the PHY operation is done */ | ||
94 | @@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp) | ||
95 | static Property imx_eth_properties[] = { | ||
96 | DEFINE_NIC_PROPERTIES(IMXFECState, conf), | ||
97 | DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1), | ||
98 | + DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0), | ||
99 | DEFINE_PROP_END_OF_LIST(), | ||
100 | }; | ||
101 | |||
102 | diff --git a/hw/net/trace-events b/hw/net/trace-events | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/hw/net/trace-events | ||
105 | +++ b/hw/net/trace-events | ||
106 | @@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries" | ||
107 | i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION" | ||
108 | |||
109 | # imx_fec.c | ||
110 | -imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]" | ||
111 | -imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]" | ||
112 | +imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]" | ||
113 | +imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]" | ||
114 | imx_phy_update_link(const char *s) "%s" | ||
115 | imx_phy_reset(void) "" | ||
116 | imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x" | ||
34 | -- | 117 | -- |
35 | 2.18.0 | 118 | 2.20.1 |
36 | 119 | ||
37 | 120 | diff view generated by jsdifflib |
1 | From: Stefan Hajnoczi <stefanha@redhat.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | The generic loader device supports the U-Boot and Intel HEX executable | 3 | Add properties to the i.MX6UL processor to be able to select a |
4 | formats in addition to the document raw and ELF formats. Reword the | 4 | particular PHY on the MDIO bus for each FEC device. |
5 | documentation to include these formats and explain how various options | ||
6 | depend on the executable format. | ||
7 | 5 | ||
8 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | 6 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net |
10 | Message-id: 20180816145554.9814-1-stefanha@redhat.com | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | docs/generic-loader.txt | 20 ++++++++++---------- | 11 | include/hw/arm/fsl-imx6ul.h | 2 ++ |
15 | 1 file changed, 10 insertions(+), 10 deletions(-) | 12 | hw/arm/fsl-imx6ul.c | 10 ++++++++++ |
13 | 2 files changed, 12 insertions(+) | ||
16 | 14 | ||
17 | diff --git a/docs/generic-loader.txt b/docs/generic-loader.txt | 15 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/docs/generic-loader.txt | 17 | --- a/include/hw/arm/fsl-imx6ul.h |
20 | +++ b/docs/generic-loader.txt | 18 | +++ b/include/hw/arm/fsl-imx6ul.h |
21 | @@ -XXX,XX +XXX,XX @@ An example of setting CPU 0's PC to 0x8000 is: | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState { |
22 | 20 | MemoryRegion caam; | |
23 | Loading Files | 21 | MemoryRegion ocram; |
24 | ------------- | 22 | MemoryRegion ocram_alias; |
25 | -The loader device also allows files to be loaded into memory. It can load raw | 23 | + |
26 | -files and ELF executable files. Raw files are loaded verbatim. ELF executable | 24 | + uint32_t phy_num[FSL_IMX6UL_NUM_ETHS]; |
27 | -files are loaded by an ELF loader. The syntax is shown below: | 25 | } FslIMX6ULState; |
28 | +The loader device also allows files to be loaded into memory. It can load ELF, | 26 | |
29 | +U-Boot, and Intel HEX executable formats as well as raw images. The syntax is | 27 | enum FslIMX6ULMemoryMap { |
30 | +shown below: | 28 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c |
31 | 29 | index XXXXXXX..XXXXXXX 100644 | |
32 | -device loader,file=<file>[,addr=<addr>][,cpu-num=<cpu-num>][,force-raw=<raw>] | 30 | --- a/hw/arm/fsl-imx6ul.c |
33 | 31 | +++ b/hw/arm/fsl-imx6ul.c | |
34 | <file> - A file to be loaded into memory | 32 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
35 | - <addr> - The addr in memory that the file should be loaded. This is | 33 | FSL_IMX6UL_ENET2_TIMER_IRQ, |
36 | - ignored if you are using an ELF (unless force-raw is true). | 34 | }; |
37 | - This is required if you aren't loading an ELF. | 35 | |
38 | + <addr> - The memory address where the file should be loaded. This is | 36 | + object_property_set_uint(OBJECT(&s->eth[i]), |
39 | + required for raw images and ignored for non-raw files. | 37 | + s->phy_num[i], |
40 | <cpu-num> - This specifies the CPU that should be used. This is an | 38 | + "phy-num", &error_abort); |
41 | optional argument and will cause the CPU's PC to be set to | 39 | object_property_set_uint(OBJECT(&s->eth[i]), |
42 | - where the image is stored or in the case of an ELF file to | 40 | FSL_IMX6UL_ETH_NUM_TX_RINGS, |
43 | - the value in the header. This option should only be used | 41 | "tx-ring-num", &error_abort); |
44 | - for the boot image. | 42 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
45 | + the memory address where the raw file is loaded or the entry | 43 | FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); |
46 | + point specified in the executable format header. This option | 44 | } |
47 | + should only be used for the boot image. | 45 | |
48 | This will also cause the image to be written to the specified | 46 | +static Property fsl_imx6ul_properties[] = { |
49 | CPU's address space. If not specified, the default is CPU 0. | 47 | + DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0), |
50 | <force-raw> - Setting force-raw=on forces the file to be treated as a raw | 48 | + DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1), |
51 | - image. This can be used to load ELF files as if they were raw. | 49 | + DEFINE_PROP_END_OF_LIST(), |
52 | + image. This can be used to load supported executable formats | 50 | +}; |
53 | + as if they were raw. | 51 | + |
54 | 52 | static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) | |
55 | All values are parsed using the standard QemuOps parsing. This allows the user | 53 | { |
56 | to specify any values in any format supported. By default the values | 54 | DeviceClass *dc = DEVICE_CLASS(oc); |
55 | |||
56 | + device_class_set_props(dc, fsl_imx6ul_properties); | ||
57 | dc->realize = fsl_imx6ul_realize; | ||
58 | dc->desc = "i.MX6UL SOC"; | ||
59 | /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
57 | -- | 60 | -- |
58 | 2.18.0 | 61 | 2.20.1 |
59 | 62 | ||
60 | 63 | diff view generated by jsdifflib |
1 | From: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Add the ESDHC PRSSTAT_SDSTB bit, using the value of SDHC_CLOCK_INT_STABLE. | 3 | The i.MX6UL EVK 14x14 board uses: |
4 | Freescale recommends checking this bit when changing clock frequency. | 4 | - PHY 2 for FEC 1 |
5 | - PHY 1 for FEC 2 | ||
5 | 6 | ||
6 | Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> | 7 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
7 | Message-id: 1534507843-4251-1-git-send-email-hans-erik.floryd@rt-labs.com | 8 | Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net |
8 | [PMM: fixed indentation] | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | hw/sd/sdhci-internal.h | 2 ++ | 12 | hw/arm/mcimx6ul-evk.c | 2 ++ |
13 | hw/sd/sdhci.c | 8 ++++++++ | 13 | 1 file changed, 2 insertions(+) |
14 | 2 files changed, 10 insertions(+) | ||
15 | 14 | ||
16 | diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h | 15 | diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c |
17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/sd/sdhci-internal.h | 17 | --- a/hw/arm/mcimx6ul-evk.c |
19 | +++ b/hw/sd/sdhci-internal.h | 18 | +++ b/hw/arm/mcimx6ul-evk.c |
20 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription sdhci_vmstate; | 19 | @@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine) |
21 | #define ESDHC_CTRL_4BITBUS (0x1 << 1) | 20 | |
22 | #define ESDHC_CTRL_8BITBUS (0x2 << 1) | 21 | s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL)); |
23 | 22 | object_property_add_child(OBJECT(machine), "soc", OBJECT(s)); | |
24 | +#define ESDHC_PRNSTS_SDSTB (1 << 3) | 23 | + object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal); |
25 | + | 24 | + object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal); |
26 | #endif | 25 | qdev_realize(DEVICE(s), NULL, &error_fatal); |
27 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 26 | |
28 | index XXXXXXX..XXXXXXX 100644 | 27 | memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR, |
29 | --- a/hw/sd/sdhci.c | ||
30 | +++ b/hw/sd/sdhci.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) | ||
32 | |||
33 | break; | ||
34 | |||
35 | + case SDHC_PRNSTS: | ||
36 | + /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ | ||
37 | + ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; | ||
38 | + if (s->clkcon & SDHC_CLOCK_INT_STABLE) { | ||
39 | + ret |= ESDHC_PRNSTS_SDSTB; | ||
40 | + } | ||
41 | + break; | ||
42 | + | ||
43 | case ESDHC_DLL_CTRL: | ||
44 | case ESDHC_TUNE_CTRL_STATUS: | ||
45 | case ESDHC_UNDOCUMENTED_REG27: | ||
46 | -- | 28 | -- |
47 | 2.18.0 | 29 | 2.20.1 |
48 | 30 | ||
49 | 31 | diff view generated by jsdifflib |
1 | The Arm Cortex-M System Design Kit includes a simple watchdog module | 1 | From: Eric Auger <eric.auger@redhat.com> |
---|---|---|---|
2 | based on a 32-bit down-counter. Implement this. | ||
3 | 2 | ||
3 | Introduce a new property defining a reserved region: | ||
4 | <low address>:<high address>:<type>. | ||
5 | |||
6 | This will be used to encode reserved IOVA regions. | ||
7 | |||
8 | For instance, in virtio-iommu use case, reserved IOVA regions | ||
9 | will be passed by the machine code to the virtio-iommu-pci | ||
10 | device (an array of those). The type of the reserved region | ||
11 | will match the virtio_iommu_probe_resv_mem subtype value: | ||
12 | - VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0) | ||
13 | - VIRTIO_IOMMU_RESV_MEM_T_MSI (1) | ||
14 | |||
15 | on PC/Q35 machine, this will be used to inform the | ||
16 | virtio-iommu-pci device it should bypass the MSI region. | ||
17 | The reserved region will be: 0xfee00000:0xfeefffff:1. | ||
18 | |||
19 | On ARM, we can declare the ITS MSI doorbell as an MSI | ||
20 | region to prevent MSIs from being mapped on guest side. | ||
21 | |||
22 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
23 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
24 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
25 | Message-id: 20200629070404.10969-2-eric.auger@redhat.com | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | --- | 27 | --- |
6 | Makefile.objs | 1 + | 28 | include/exec/memory.h | 6 +++ |
7 | hw/watchdog/Makefile.objs | 1 + | 29 | include/hw/qdev-properties.h | 3 ++ |
8 | include/hw/watchdog/cmsdk-apb-watchdog.h | 59 ++++ | 30 | include/qemu/typedefs.h | 1 + |
9 | hw/watchdog/cmsdk-apb-watchdog.c | 326 +++++++++++++++++++++++ | 31 | hw/core/qdev-properties.c | 89 ++++++++++++++++++++++++++++++++++++ |
10 | MAINTAINERS | 2 + | 32 | 4 files changed, 99 insertions(+) |
11 | default-configs/arm-softmmu.mak | 1 + | ||
12 | hw/watchdog/trace-events | 6 + | ||
13 | 7 files changed, 396 insertions(+) | ||
14 | create mode 100644 include/hw/watchdog/cmsdk-apb-watchdog.h | ||
15 | create mode 100644 hw/watchdog/cmsdk-apb-watchdog.c | ||
16 | create mode 100644 hw/watchdog/trace-events | ||
17 | 33 | ||
18 | diff --git a/Makefile.objs b/Makefile.objs | 34 | diff --git a/include/exec/memory.h b/include/exec/memory.h |
19 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/Makefile.objs | 36 | --- a/include/exec/memory.h |
21 | +++ b/Makefile.objs | 37 | +++ b/include/exec/memory.h |
22 | @@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/tpm | 38 | @@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log; |
23 | trace-events-subdirs += hw/usb | 39 | |
24 | trace-events-subdirs += hw/vfio | 40 | typedef struct MemoryRegionOps MemoryRegionOps; |
25 | trace-events-subdirs += hw/virtio | 41 | |
26 | +trace-events-subdirs += hw/watchdog | 42 | +struct ReservedRegion { |
27 | trace-events-subdirs += hw/xen | 43 | + hwaddr low; |
28 | trace-events-subdirs += io | 44 | + hwaddr high; |
29 | trace-events-subdirs += linux-user | 45 | + unsigned type; |
30 | diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs | 46 | +}; |
47 | + | ||
48 | typedef struct IOMMUTLBEntry IOMMUTLBEntry; | ||
49 | |||
50 | /* See address_space_translate: bit 0 is read, bit 1 is write. */ | ||
51 | diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h | ||
31 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/watchdog/Makefile.objs | 53 | --- a/include/hw/qdev-properties.h |
33 | +++ b/hw/watchdog/Makefile.objs | 54 | +++ b/include/hw/qdev-properties.h |
55 | @@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string; | ||
56 | extern const PropertyInfo qdev_prop_chr; | ||
57 | extern const PropertyInfo qdev_prop_tpm; | ||
58 | extern const PropertyInfo qdev_prop_macaddr; | ||
59 | +extern const PropertyInfo qdev_prop_reserved_region; | ||
60 | extern const PropertyInfo qdev_prop_on_off_auto; | ||
61 | extern const PropertyInfo qdev_prop_multifd_compression; | ||
62 | extern const PropertyInfo qdev_prop_losttickpolicy; | ||
63 | @@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width; | ||
64 | DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *) | ||
65 | #define DEFINE_PROP_MACADDR(_n, _s, _f) \ | ||
66 | DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr) | ||
67 | +#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f) \ | ||
68 | + DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion) | ||
69 | #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \ | ||
70 | DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto) | ||
71 | #define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \ | ||
72 | diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/include/qemu/typedefs.h | ||
75 | +++ b/include/qemu/typedefs.h | ||
76 | @@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus; | ||
77 | typedef struct ISADevice ISADevice; | ||
78 | typedef struct IsaDma IsaDma; | ||
79 | typedef struct MACAddr MACAddr; | ||
80 | +typedef struct ReservedRegion ReservedRegion; | ||
81 | typedef struct MachineClass MachineClass; | ||
82 | typedef struct MachineState MachineState; | ||
83 | typedef struct MemoryListener MemoryListener; | ||
84 | diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/core/qdev-properties.c | ||
87 | +++ b/hw/core/qdev-properties.c | ||
34 | @@ -XXX,XX +XXX,XX @@ | 88 | @@ -XXX,XX +XXX,XX @@ |
35 | common-obj-y += watchdog.o | 89 | #include "chardev/char.h" |
36 | +common-obj-$(CONFIG_CMSDK_APB_WATCHDOG) += cmsdk-apb-watchdog.o | 90 | #include "qemu/uuid.h" |
37 | common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o | 91 | #include "qemu/units.h" |
38 | common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o | 92 | +#include "qemu/cutils.h" |
39 | common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o | 93 | |
40 | diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h | 94 | void qdev_prop_set_after_realize(DeviceState *dev, const char *name, |
41 | new file mode 100644 | 95 | Error **errp) |
42 | index XXXXXXX..XXXXXXX | 96 | @@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = { |
43 | --- /dev/null | 97 | .set = set_mac, |
44 | +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h | 98 | }; |
45 | @@ -XXX,XX +XXX,XX @@ | 99 | |
46 | +/* | 100 | +/* --- Reserved Region --- */ |
47 | + * ARM CMSDK APB watchdog emulation | ||
48 | + * | ||
49 | + * Copyright (c) 2018 Linaro Limited | ||
50 | + * Written by Peter Maydell | ||
51 | + * | ||
52 | + * This program is free software; you can redistribute it and/or modify | ||
53 | + * it under the terms of the GNU General Public License version 2 or | ||
54 | + * (at your option) any later version. | ||
55 | + */ | ||
56 | + | 101 | + |
57 | +/* | 102 | +/* |
58 | + * This is a model of the "APB watchdog" which is part of the Cortex-M | 103 | + * Accepted syntax: |
59 | + * System Design Kit (CMSDK) and documented in the Cortex-M System | 104 | + * <low address>:<high address>:<type> |
60 | + * Design Kit Technical Reference Manual (ARM DDI0479C): | 105 | + * where low/high addresses are uint64_t in hexadecimal |
61 | + * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit | 106 | + * and type is a non-negative decimal integer |
62 | + * | ||
63 | + * QEMU interface: | ||
64 | + * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked | ||
65 | + * + sysbus MMIO region 0: the register bank | ||
66 | + * + sysbus IRQ 0: watchdog interrupt | ||
67 | + * | ||
68 | + * In real hardware the watchdog's reset output is just a GPIO line | ||
69 | + * which can then be masked by the board or treated as a simple interrupt. | ||
70 | + * (For instance the IoTKit does this with the non-secure watchdog, so that | ||
71 | + * secure code can control whether non-secure code can perform a system | ||
72 | + * reset via its watchdog.) In QEMU, we just wire up the watchdog reset | ||
73 | + * to watchdog_perform_action(), at least for the moment. | ||
74 | + */ | 107 | + */ |
108 | +static void get_reserved_region(Object *obj, Visitor *v, const char *name, | ||
109 | + void *opaque, Error **errp) | ||
110 | +{ | ||
111 | + DeviceState *dev = DEVICE(obj); | ||
112 | + Property *prop = opaque; | ||
113 | + ReservedRegion *rr = qdev_get_prop_ptr(dev, prop); | ||
114 | + char buffer[64]; | ||
115 | + char *p = buffer; | ||
116 | + int rc; | ||
75 | + | 117 | + |
76 | +#ifndef CMSDK_APB_WATCHDOG_H | 118 | + rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u", |
77 | +#define CMSDK_APB_WATCHDOG_H | 119 | + rr->low, rr->high, rr->type); |
120 | + assert(rc < sizeof(buffer)); | ||
78 | + | 121 | + |
79 | +#include "hw/sysbus.h" | 122 | + visit_type_str(v, name, &p, errp); |
80 | +#include "hw/ptimer.h" | ||
81 | + | ||
82 | +#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog" | ||
83 | +#define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \ | ||
84 | + TYPE_CMSDK_APB_WATCHDOG) | ||
85 | + | ||
86 | +typedef struct CMSDKAPBWatchdog { | ||
87 | + /*< private >*/ | ||
88 | + SysBusDevice parent_obj; | ||
89 | + | ||
90 | + /*< public >*/ | ||
91 | + MemoryRegion iomem; | ||
92 | + qemu_irq wdogint; | ||
93 | + uint32_t wdogclk_frq; | ||
94 | + struct ptimer_state *timer; | ||
95 | + | ||
96 | + uint32_t control; | ||
97 | + uint32_t intstatus; | ||
98 | + uint32_t lock; | ||
99 | + uint32_t itcr; | ||
100 | + uint32_t itop; | ||
101 | + uint32_t resetstatus; | ||
102 | +} CMSDKAPBWatchdog; | ||
103 | + | ||
104 | +#endif | ||
105 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | ||
106 | new file mode 100644 | ||
107 | index XXXXXXX..XXXXXXX | ||
108 | --- /dev/null | ||
109 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | ||
110 | @@ -XXX,XX +XXX,XX @@ | ||
111 | +/* | ||
112 | + * ARM CMSDK APB watchdog emulation | ||
113 | + * | ||
114 | + * Copyright (c) 2018 Linaro Limited | ||
115 | + * Written by Peter Maydell | ||
116 | + * | ||
117 | + * This program is free software; you can redistribute it and/or modify | ||
118 | + * it under the terms of the GNU General Public License version 2 or | ||
119 | + * (at your option) any later version. | ||
120 | + */ | ||
121 | + | ||
122 | +/* | ||
123 | + * This is a model of the "APB watchdog" which is part of the Cortex-M | ||
124 | + * System Design Kit (CMSDK) and documented in the Cortex-M System | ||
125 | + * Design Kit Technical Reference Manual (ARM DDI0479C): | ||
126 | + * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit | ||
127 | + */ | ||
128 | + | ||
129 | +#include "qemu/osdep.h" | ||
130 | +#include "qemu/log.h" | ||
131 | +#include "trace.h" | ||
132 | +#include "qapi/error.h" | ||
133 | +#include "qemu/main-loop.h" | ||
134 | +#include "sysemu/watchdog.h" | ||
135 | +#include "hw/sysbus.h" | ||
136 | +#include "hw/registerfields.h" | ||
137 | +#include "hw/watchdog/cmsdk-apb-watchdog.h" | ||
138 | + | ||
139 | +REG32(WDOGLOAD, 0x0) | ||
140 | +REG32(WDOGVALUE, 0x4) | ||
141 | +REG32(WDOGCONTROL, 0x8) | ||
142 | + FIELD(WDOGCONTROL, INTEN, 0, 1) | ||
143 | + FIELD(WDOGCONTROL, RESEN, 1, 1) | ||
144 | +#define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \ | ||
145 | + R_WDOGCONTROL_RESEN_MASK) | ||
146 | +REG32(WDOGINTCLR, 0xc) | ||
147 | +REG32(WDOGRIS, 0x10) | ||
148 | + FIELD(WDOGRIS, INT, 0, 1) | ||
149 | +REG32(WDOGMIS, 0x14) | ||
150 | +REG32(WDOGLOCK, 0xc00) | ||
151 | +#define WDOG_UNLOCK_VALUE 0x1ACCE551 | ||
152 | +REG32(WDOGITCR, 0xf00) | ||
153 | + FIELD(WDOGITCR, ENABLE, 0, 1) | ||
154 | +#define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK | ||
155 | +REG32(WDOGITOP, 0xf04) | ||
156 | + FIELD(WDOGITOP, WDOGRES, 0, 1) | ||
157 | + FIELD(WDOGITOP, WDOGINT, 1, 1) | ||
158 | +#define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \ | ||
159 | + R_WDOGITOP_WDOGINT_MASK) | ||
160 | +REG32(PID4, 0xfd0) | ||
161 | +REG32(PID5, 0xfd4) | ||
162 | +REG32(PID6, 0xfd8) | ||
163 | +REG32(PID7, 0xfdc) | ||
164 | +REG32(PID0, 0xfe0) | ||
165 | +REG32(PID1, 0xfe4) | ||
166 | +REG32(PID2, 0xfe8) | ||
167 | +REG32(PID3, 0xfec) | ||
168 | +REG32(CID0, 0xff0) | ||
169 | +REG32(CID1, 0xff4) | ||
170 | +REG32(CID2, 0xff8) | ||
171 | +REG32(CID3, 0xffc) | ||
172 | + | ||
173 | +/* PID/CID values */ | ||
174 | +static const int watchdog_id[] = { | ||
175 | + 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ | ||
176 | + 0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ | ||
177 | + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ | ||
178 | +}; | ||
179 | + | ||
180 | +static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s) | ||
181 | +{ | ||
182 | + /* Return masked interrupt status */ | ||
183 | + return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK); | ||
184 | +} | 123 | +} |
185 | + | 124 | + |
186 | +static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s) | 125 | +static void set_reserved_region(Object *obj, Visitor *v, const char *name, |
126 | + void *opaque, Error **errp) | ||
187 | +{ | 127 | +{ |
188 | + /* Return masked reset status */ | 128 | + DeviceState *dev = DEVICE(obj); |
189 | + return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK); | 129 | + Property *prop = opaque; |
190 | +} | 130 | + ReservedRegion *rr = qdev_get_prop_ptr(dev, prop); |
131 | + Error *local_err = NULL; | ||
132 | + const char *endptr; | ||
133 | + char *str; | ||
134 | + int ret; | ||
191 | + | 135 | + |
192 | +static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s) | 136 | + if (dev->realized) { |
193 | +{ | 137 | + qdev_prop_set_after_realize(dev, name, errp); |
194 | + bool wdogint; | ||
195 | + bool wdogres; | ||
196 | + | ||
197 | + if (s->itcr) { | ||
198 | + wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK; | ||
199 | + wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK; | ||
200 | + } else { | ||
201 | + wdogint = cmsdk_apb_watchdog_intstatus(s); | ||
202 | + wdogres = cmsdk_apb_watchdog_resetstatus(s); | ||
203 | + } | ||
204 | + | ||
205 | + qemu_set_irq(s->wdogint, wdogint); | ||
206 | + if (wdogres) { | ||
207 | + watchdog_perform_action(); | ||
208 | + } | ||
209 | +} | ||
210 | + | ||
211 | +static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset, | ||
212 | + unsigned size) | ||
213 | +{ | ||
214 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); | ||
215 | + uint64_t r; | ||
216 | + | ||
217 | + switch (offset) { | ||
218 | + case A_WDOGLOAD: | ||
219 | + r = ptimer_get_limit(s->timer); | ||
220 | + break; | ||
221 | + case A_WDOGVALUE: | ||
222 | + r = ptimer_get_count(s->timer); | ||
223 | + break; | ||
224 | + case A_WDOGCONTROL: | ||
225 | + r = s->control; | ||
226 | + break; | ||
227 | + case A_WDOGRIS: | ||
228 | + r = s->intstatus; | ||
229 | + break; | ||
230 | + case A_WDOGMIS: | ||
231 | + r = cmsdk_apb_watchdog_intstatus(s); | ||
232 | + break; | ||
233 | + case A_WDOGLOCK: | ||
234 | + r = s->lock; | ||
235 | + break; | ||
236 | + case A_WDOGITCR: | ||
237 | + r = s->itcr; | ||
238 | + break; | ||
239 | + case A_PID4 ... A_CID3: | ||
240 | + r = watchdog_id[(offset - A_PID4) / 4]; | ||
241 | + break; | ||
242 | + case A_WDOGINTCLR: | ||
243 | + case A_WDOGITOP: | ||
244 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
245 | + "CMSDK APB watchdog read: read of WO offset %x\n", | ||
246 | + (int)offset); | ||
247 | + r = 0; | ||
248 | + break; | ||
249 | + default: | ||
250 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
251 | + "CMSDK APB watchdog read: bad offset %x\n", (int)offset); | ||
252 | + r = 0; | ||
253 | + break; | ||
254 | + } | ||
255 | + trace_cmsdk_apb_watchdog_read(offset, r, size); | ||
256 | + return r; | ||
257 | +} | ||
258 | + | ||
259 | +static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | ||
260 | + uint64_t value, unsigned size) | ||
261 | +{ | ||
262 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); | ||
263 | + | ||
264 | + trace_cmsdk_apb_watchdog_write(offset, value, size); | ||
265 | + | ||
266 | + if (s->lock && offset != A_WDOGLOCK) { | ||
267 | + /* Write access is disabled via WDOGLOCK */ | ||
268 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
269 | + "CMSDK APB watchdog write: write to locked watchdog\n"); | ||
270 | + return; | 138 | + return; |
271 | + } | 139 | + } |
272 | + | 140 | + |
273 | + switch (offset) { | 141 | + visit_type_str(v, name, &str, &local_err); |
274 | + case A_WDOGLOAD: | 142 | + if (local_err) { |
275 | + /* | 143 | + error_propagate(errp, local_err); |
276 | + * Reset the load value and the current count, and make sure | ||
277 | + * we're counting. | ||
278 | + */ | ||
279 | + ptimer_set_limit(s->timer, value, 1); | ||
280 | + ptimer_run(s->timer, 0); | ||
281 | + break; | ||
282 | + case A_WDOGCONTROL: | ||
283 | + s->control = value & R_WDOGCONTROL_VALID_MASK; | ||
284 | + cmsdk_apb_watchdog_update(s); | ||
285 | + break; | ||
286 | + case A_WDOGINTCLR: | ||
287 | + s->intstatus = 0; | ||
288 | + ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); | ||
289 | + cmsdk_apb_watchdog_update(s); | ||
290 | + break; | ||
291 | + case A_WDOGLOCK: | ||
292 | + s->lock = (value != WDOG_UNLOCK_VALUE); | ||
293 | + break; | ||
294 | + case A_WDOGITCR: | ||
295 | + s->itcr = value & R_WDOGITCR_VALID_MASK; | ||
296 | + cmsdk_apb_watchdog_update(s); | ||
297 | + break; | ||
298 | + case A_WDOGITOP: | ||
299 | + s->itop = value & R_WDOGITOP_VALID_MASK; | ||
300 | + cmsdk_apb_watchdog_update(s); | ||
301 | + break; | ||
302 | + case A_WDOGVALUE: | ||
303 | + case A_WDOGRIS: | ||
304 | + case A_WDOGMIS: | ||
305 | + case A_PID4 ... A_CID3: | ||
306 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
307 | + "CMSDK APB watchdog write: write to RO offset 0x%x\n", | ||
308 | + (int)offset); | ||
309 | + break; | ||
310 | + default: | ||
311 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
312 | + "CMSDK APB watchdog write: bad offset 0x%x\n", | ||
313 | + (int)offset); | ||
314 | + break; | ||
315 | + } | ||
316 | +} | ||
317 | + | ||
318 | +static const MemoryRegionOps cmsdk_apb_watchdog_ops = { | ||
319 | + .read = cmsdk_apb_watchdog_read, | ||
320 | + .write = cmsdk_apb_watchdog_write, | ||
321 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
322 | + /* byte/halfword accesses are just zero-padded on reads and writes */ | ||
323 | + .impl.min_access_size = 4, | ||
324 | + .impl.max_access_size = 4, | ||
325 | + .valid.min_access_size = 1, | ||
326 | + .valid.max_access_size = 4, | ||
327 | +}; | ||
328 | + | ||
329 | +static void cmsdk_apb_watchdog_tick(void *opaque) | ||
330 | +{ | ||
331 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque); | ||
332 | + | ||
333 | + if (!s->intstatus) { | ||
334 | + /* Count expired for the first time: raise interrupt */ | ||
335 | + s->intstatus = R_WDOGRIS_INT_MASK; | ||
336 | + } else { | ||
337 | + /* Count expired for the second time: raise reset and stop clock */ | ||
338 | + s->resetstatus = 1; | ||
339 | + ptimer_stop(s->timer); | ||
340 | + } | ||
341 | + cmsdk_apb_watchdog_update(s); | ||
342 | +} | ||
343 | + | ||
344 | +static void cmsdk_apb_watchdog_reset(DeviceState *dev) | ||
345 | +{ | ||
346 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); | ||
347 | + | ||
348 | + trace_cmsdk_apb_watchdog_reset(); | ||
349 | + s->control = 0; | ||
350 | + s->intstatus = 0; | ||
351 | + s->lock = 0; | ||
352 | + s->itcr = 0; | ||
353 | + s->itop = 0; | ||
354 | + s->resetstatus = 0; | ||
355 | + /* Set the limit and the count */ | ||
356 | + ptimer_set_limit(s->timer, 0xffffffff, 1); | ||
357 | + ptimer_run(s->timer, 0); | ||
358 | +} | ||
359 | + | ||
360 | +static void cmsdk_apb_watchdog_init(Object *obj) | ||
361 | +{ | ||
362 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
363 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj); | ||
364 | + | ||
365 | + memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops, | ||
366 | + s, "cmsdk-apb-watchdog", 0x1000); | ||
367 | + sysbus_init_mmio(sbd, &s->iomem); | ||
368 | + sysbus_init_irq(sbd, &s->wdogint); | ||
369 | +} | ||
370 | + | ||
371 | +static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | ||
372 | +{ | ||
373 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev); | ||
374 | + QEMUBH *bh; | ||
375 | + | ||
376 | + if (s->wdogclk_frq == 0) { | ||
377 | + error_setg(errp, | ||
378 | + "CMSDK APB watchdog: wdogclk-frq property must be set"); | ||
379 | + return; | 144 | + return; |
380 | + } | 145 | + } |
381 | + | 146 | + |
382 | + bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s); | 147 | + ret = qemu_strtou64(str, &endptr, 16, &rr->low); |
383 | + s->timer = ptimer_init(bh, | 148 | + if (ret) { |
384 | + PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | | 149 | + error_setg(errp, "start address of '%s'" |
385 | + PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT | | 150 | + " must be a hexadecimal integer", name); |
386 | + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | | 151 | + goto out; |
387 | + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); | 152 | + } |
153 | + if (*endptr != ':') { | ||
154 | + goto separator_error; | ||
155 | + } | ||
388 | + | 156 | + |
389 | + ptimer_set_freq(s->timer, s->wdogclk_frq); | 157 | + ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high); |
158 | + if (ret) { | ||
159 | + error_setg(errp, "end address of '%s'" | ||
160 | + " must be a hexadecimal integer", name); | ||
161 | + goto out; | ||
162 | + } | ||
163 | + if (*endptr != ':') { | ||
164 | + goto separator_error; | ||
165 | + } | ||
166 | + | ||
167 | + ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type); | ||
168 | + if (ret) { | ||
169 | + error_setg(errp, "type of '%s'" | ||
170 | + " must be a non-negative decimal integer", name); | ||
171 | + } | ||
172 | + goto out; | ||
173 | + | ||
174 | +separator_error: | ||
175 | + error_setg(errp, "reserved region fields must be separated with ':'"); | ||
176 | +out: | ||
177 | + g_free(str); | ||
178 | + return; | ||
390 | +} | 179 | +} |
391 | + | 180 | + |
392 | +static const VMStateDescription cmsdk_apb_watchdog_vmstate = { | 181 | +const PropertyInfo qdev_prop_reserved_region = { |
393 | + .name = "cmsdk-apb-watchdog", | 182 | + .name = "reserved_region", |
394 | + .version_id = 1, | 183 | + .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0", |
395 | + .minimum_version_id = 1, | 184 | + .get = get_reserved_region, |
396 | + .fields = (VMStateField[]) { | 185 | + .set = set_reserved_region, |
397 | + VMSTATE_PTIMER(timer, CMSDKAPBWatchdog), | ||
398 | + VMSTATE_UINT32(control, CMSDKAPBWatchdog), | ||
399 | + VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog), | ||
400 | + VMSTATE_UINT32(lock, CMSDKAPBWatchdog), | ||
401 | + VMSTATE_UINT32(itcr, CMSDKAPBWatchdog), | ||
402 | + VMSTATE_UINT32(itop, CMSDKAPBWatchdog), | ||
403 | + VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog), | ||
404 | + VMSTATE_END_OF_LIST() | ||
405 | + } | ||
406 | +}; | 186 | +}; |
407 | + | 187 | + |
408 | +static Property cmsdk_apb_watchdog_properties[] = { | 188 | /* --- on/off/auto --- */ |
409 | + DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0), | 189 | |
410 | + DEFINE_PROP_END_OF_LIST(), | 190 | const PropertyInfo qdev_prop_on_off_auto = { |
411 | +}; | ||
412 | + | ||
413 | +static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data) | ||
414 | +{ | ||
415 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
416 | + | ||
417 | + dc->realize = cmsdk_apb_watchdog_realize; | ||
418 | + dc->vmsd = &cmsdk_apb_watchdog_vmstate; | ||
419 | + dc->reset = cmsdk_apb_watchdog_reset; | ||
420 | + dc->props = cmsdk_apb_watchdog_properties; | ||
421 | +} | ||
422 | + | ||
423 | +static const TypeInfo cmsdk_apb_watchdog_info = { | ||
424 | + .name = TYPE_CMSDK_APB_WATCHDOG, | ||
425 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
426 | + .instance_size = sizeof(CMSDKAPBWatchdog), | ||
427 | + .instance_init = cmsdk_apb_watchdog_init, | ||
428 | + .class_init = cmsdk_apb_watchdog_class_init, | ||
429 | +}; | ||
430 | + | ||
431 | +static void cmsdk_apb_watchdog_register_types(void) | ||
432 | +{ | ||
433 | + type_register_static(&cmsdk_apb_watchdog_info); | ||
434 | +} | ||
435 | + | ||
436 | +type_init(cmsdk_apb_watchdog_register_types); | ||
437 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
438 | index XXXXXXX..XXXXXXX 100644 | ||
439 | --- a/MAINTAINERS | ||
440 | +++ b/MAINTAINERS | ||
441 | @@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c | ||
442 | F: include/hw/timer/cmsdk-apb-timer.h | ||
443 | F: hw/char/cmsdk-apb-uart.c | ||
444 | F: include/hw/char/cmsdk-apb-uart.h | ||
445 | +F: hw/watchdog/cmsdk-apb-watchdog.c | ||
446 | +F: include/hw/watchdog/cmsdk-apb-watchdog.h | ||
447 | F: hw/misc/tz-ppc.c | ||
448 | F: include/hw/misc/tz-ppc.h | ||
449 | F: hw/misc/tz-mpc.c | ||
450 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
451 | index XXXXXXX..XXXXXXX 100644 | ||
452 | --- a/default-configs/arm-softmmu.mak | ||
453 | +++ b/default-configs/arm-softmmu.mak | ||
454 | @@ -XXX,XX +XXX,XX @@ CONFIG_STM32F205_SOC=y | ||
455 | |||
456 | CONFIG_CMSDK_APB_TIMER=y | ||
457 | CONFIG_CMSDK_APB_UART=y | ||
458 | +CONFIG_CMSDK_APB_WATCHDOG=y | ||
459 | |||
460 | CONFIG_MPS2_FPGAIO=y | ||
461 | CONFIG_MPS2_SCC=y | ||
462 | diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events | ||
463 | new file mode 100644 | ||
464 | index XXXXXXX..XXXXXXX | ||
465 | --- /dev/null | ||
466 | +++ b/hw/watchdog/trace-events | ||
467 | @@ -XXX,XX +XXX,XX @@ | ||
468 | +# See docs/devel/tracing.txt for syntax documentation. | ||
469 | + | ||
470 | +# hw/char/cmsdk_apb_watchdog.c | ||
471 | +cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
472 | +cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
473 | +cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset" | ||
474 | -- | 191 | -- |
475 | 2.18.0 | 192 | 2.20.1 |
476 | 193 | ||
477 | 194 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Eric Auger <eric.auger@redhat.com> | |
2 | |||
3 | This patch implements the PROBE request. At the moment, | ||
4 | only THE RESV_MEM property is handled. The first goal is | ||
5 | to report iommu wide reserved regions such as the MSI regions | ||
6 | set by the machine code. On x86 this will be the IOAPIC MSI | ||
7 | region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS | ||
8 | doorbell. | ||
9 | |||
10 | In the future we may introduce per device reserved regions. | ||
11 | This will be useful when protecting host assigned devices | ||
12 | which may expose their own reserved regions | ||
13 | |||
14 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
15 | Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
16 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
17 | Message-id: 20200629070404.10969-3-eric.auger@redhat.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | --- | ||
20 | include/hw/virtio/virtio-iommu.h | 2 + | ||
21 | hw/virtio/virtio-iommu.c | 94 ++++++++++++++++++++++++++++++-- | ||
22 | hw/virtio/trace-events | 1 + | ||
23 | 3 files changed, 93 insertions(+), 4 deletions(-) | ||
24 | |||
25 | diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/include/hw/virtio/virtio-iommu.h | ||
28 | +++ b/include/hw/virtio/virtio-iommu.h | ||
29 | @@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU { | ||
30 | GHashTable *as_by_busptr; | ||
31 | IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX]; | ||
32 | PCIBus *primary_bus; | ||
33 | + ReservedRegion *reserved_regions; | ||
34 | + uint32_t nb_reserved_regions; | ||
35 | GTree *domains; | ||
36 | QemuMutex mutex; | ||
37 | GTree *endpoints; | ||
38 | diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/hw/virtio/virtio-iommu.c | ||
41 | +++ b/hw/virtio/virtio-iommu.c | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | |||
44 | /* Max size */ | ||
45 | #define VIOMMU_DEFAULT_QUEUE_SIZE 256 | ||
46 | +#define VIOMMU_PROBE_SIZE 512 | ||
47 | |||
48 | typedef struct VirtIOIOMMUDomain { | ||
49 | uint32_t id; | ||
50 | @@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s, | ||
51 | return ret; | ||
52 | } | ||
53 | |||
54 | +static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep, | ||
55 | + uint8_t *buf, size_t free) | ||
56 | +{ | ||
57 | + struct virtio_iommu_probe_resv_mem prop = {}; | ||
58 | + size_t size = sizeof(prop), length = size - sizeof(prop.head), total; | ||
59 | + int i; | ||
60 | + | ||
61 | + total = size * s->nb_reserved_regions; | ||
62 | + | ||
63 | + if (total > free) { | ||
64 | + return -ENOSPC; | ||
65 | + } | ||
66 | + | ||
67 | + for (i = 0; i < s->nb_reserved_regions; i++) { | ||
68 | + unsigned subtype = s->reserved_regions[i].type; | ||
69 | + | ||
70 | + assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED || | ||
71 | + subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI); | ||
72 | + prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM); | ||
73 | + prop.head.length = cpu_to_le16(length); | ||
74 | + prop.subtype = subtype; | ||
75 | + prop.start = cpu_to_le64(s->reserved_regions[i].low); | ||
76 | + prop.end = cpu_to_le64(s->reserved_regions[i].high); | ||
77 | + | ||
78 | + memcpy(buf, &prop, size); | ||
79 | + | ||
80 | + trace_virtio_iommu_fill_resv_property(ep, prop.subtype, | ||
81 | + prop.start, prop.end); | ||
82 | + buf += size; | ||
83 | + } | ||
84 | + return total; | ||
85 | +} | ||
86 | + | ||
87 | +/** | ||
88 | + * virtio_iommu_probe - Fill the probe request buffer with | ||
89 | + * the properties the device is able to return | ||
90 | + */ | ||
91 | +static int virtio_iommu_probe(VirtIOIOMMU *s, | ||
92 | + struct virtio_iommu_req_probe *req, | ||
93 | + uint8_t *buf) | ||
94 | +{ | ||
95 | + uint32_t ep_id = le32_to_cpu(req->endpoint); | ||
96 | + size_t free = VIOMMU_PROBE_SIZE; | ||
97 | + ssize_t count; | ||
98 | + | ||
99 | + if (!virtio_iommu_mr(s, ep_id)) { | ||
100 | + return VIRTIO_IOMMU_S_NOENT; | ||
101 | + } | ||
102 | + | ||
103 | + count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free); | ||
104 | + if (count < 0) { | ||
105 | + return VIRTIO_IOMMU_S_INVAL; | ||
106 | + } | ||
107 | + buf += count; | ||
108 | + free -= count; | ||
109 | + | ||
110 | + return VIRTIO_IOMMU_S_OK; | ||
111 | +} | ||
112 | + | ||
113 | static int virtio_iommu_iov_to_req(struct iovec *iov, | ||
114 | unsigned int iov_cnt, | ||
115 | void *req, size_t req_sz) | ||
116 | @@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach) | ||
117 | virtio_iommu_handle_req(map) | ||
118 | virtio_iommu_handle_req(unmap) | ||
119 | |||
120 | +static int virtio_iommu_handle_probe(VirtIOIOMMU *s, | ||
121 | + struct iovec *iov, | ||
122 | + unsigned int iov_cnt, | ||
123 | + uint8_t *buf) | ||
124 | +{ | ||
125 | + struct virtio_iommu_req_probe req; | ||
126 | + int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req)); | ||
127 | + | ||
128 | + return ret ? ret : virtio_iommu_probe(s, &req, buf); | ||
129 | +} | ||
130 | + | ||
131 | static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) | ||
132 | { | ||
133 | VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); | ||
134 | struct virtio_iommu_req_head head; | ||
135 | struct virtio_iommu_req_tail tail = {}; | ||
136 | + size_t output_size = sizeof(tail), sz; | ||
137 | VirtQueueElement *elem; | ||
138 | unsigned int iov_cnt; | ||
139 | struct iovec *iov; | ||
140 | - size_t sz; | ||
141 | + void *buf = NULL; | ||
142 | |||
143 | for (;;) { | ||
144 | elem = virtqueue_pop(vq, sizeof(VirtQueueElement)); | ||
145 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) | ||
146 | case VIRTIO_IOMMU_T_UNMAP: | ||
147 | tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt); | ||
148 | break; | ||
149 | + case VIRTIO_IOMMU_T_PROBE: | ||
150 | + { | ||
151 | + struct virtio_iommu_req_tail *ptail; | ||
152 | + | ||
153 | + output_size = s->config.probe_size + sizeof(tail); | ||
154 | + buf = g_malloc0(output_size); | ||
155 | + | ||
156 | + ptail = (struct virtio_iommu_req_tail *) | ||
157 | + (buf + s->config.probe_size); | ||
158 | + ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf); | ||
159 | + } | ||
160 | default: | ||
161 | tail.status = VIRTIO_IOMMU_S_UNSUPP; | ||
162 | } | ||
163 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq) | ||
164 | |||
165 | out: | ||
166 | sz = iov_from_buf(elem->in_sg, elem->in_num, 0, | ||
167 | - &tail, sizeof(tail)); | ||
168 | - assert(sz == sizeof(tail)); | ||
169 | + buf ? buf : &tail, output_size); | ||
170 | + assert(sz == output_size); | ||
171 | |||
172 | - virtqueue_push(vq, elem, sizeof(tail)); | ||
173 | + virtqueue_push(vq, elem, sz); | ||
174 | virtio_notify(vdev, vq); | ||
175 | g_free(elem); | ||
176 | + g_free(buf); | ||
177 | } | ||
178 | } | ||
179 | |||
180 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) | ||
181 | s->config.page_size_mask = TARGET_PAGE_MASK; | ||
182 | s->config.input_range.end = -1UL; | ||
183 | s->config.domain_range.end = 32; | ||
184 | + s->config.probe_size = VIOMMU_PROBE_SIZE; | ||
185 | |||
186 | virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX); | ||
187 | virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC); | ||
188 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp) | ||
189 | virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP); | ||
190 | virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS); | ||
191 | virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO); | ||
192 | + virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE); | ||
193 | |||
194 | qemu_mutex_init(&s->mutex); | ||
195 | |||
196 | diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events | ||
197 | index XXXXXXX..XXXXXXX 100644 | ||
198 | --- a/hw/virtio/trace-events | ||
199 | +++ b/hw/virtio/trace-events | ||
200 | @@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d" | ||
201 | virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d" | ||
202 | virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d" | ||
203 | virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64 | ||
204 | +virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64 | ||
205 | -- | ||
206 | 2.20.1 | ||
207 | |||
208 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Eric Auger <eric.auger@redhat.com> | ||
1 | 2 | ||
3 | When translating an address we need to check if it belongs to | ||
4 | a reserved virtual address range. If it does, there are 2 cases: | ||
5 | |||
6 | - it belongs to a RESERVED region: the guest should neither use | ||
7 | this address in a MAP not instruct the end-point to DMA on | ||
8 | them. We report an error | ||
9 | |||
10 | - It belongs to an MSI region: we bypass the translation. | ||
11 | |||
12 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
13 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
14 | Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
15 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
16 | Message-id: 20200629070404.10969-4-eric.auger@redhat.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | --- | ||
19 | hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++ | ||
20 | 1 file changed, 20 insertions(+) | ||
21 | |||
22 | diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/virtio/virtio-iommu.c | ||
25 | +++ b/hw/virtio/virtio-iommu.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
27 | uint32_t sid, flags; | ||
28 | bool bypass_allowed; | ||
29 | bool found; | ||
30 | + int i; | ||
31 | |||
32 | interval.low = addr; | ||
33 | interval.high = addr + 1; | ||
34 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
35 | goto unlock; | ||
36 | } | ||
37 | |||
38 | + for (i = 0; i < s->nb_reserved_regions; i++) { | ||
39 | + ReservedRegion *reg = &s->reserved_regions[i]; | ||
40 | + | ||
41 | + if (addr >= reg->low && addr <= reg->high) { | ||
42 | + switch (reg->type) { | ||
43 | + case VIRTIO_IOMMU_RESV_MEM_T_MSI: | ||
44 | + entry.perm = flag; | ||
45 | + break; | ||
46 | + case VIRTIO_IOMMU_RESV_MEM_T_RESERVED: | ||
47 | + default: | ||
48 | + virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING, | ||
49 | + VIRTIO_IOMMU_FAULT_F_ADDRESS, | ||
50 | + sid, addr); | ||
51 | + break; | ||
52 | + } | ||
53 | + goto unlock; | ||
54 | + } | ||
55 | + } | ||
56 | + | ||
57 | if (!ep->domain) { | ||
58 | if (!bypass_allowed) { | ||
59 | error_report_once("%s %02x:%02x.%01x not attached to any domain", | ||
60 | -- | ||
61 | 2.20.1 | ||
62 | |||
63 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Eric Auger <eric.auger@redhat.com> | ||
1 | 2 | ||
3 | The machine may need to pass reserved regions to the | ||
4 | virtio-iommu-pci device (such as the MSI window on x86 | ||
5 | or the MSI doorbells on ARM). | ||
6 | |||
7 | So let's add an array of Interval properties. | ||
8 | |||
9 | Note: if some reserved regions are already set by the | ||
10 | machine code - which should be the case in general -, | ||
11 | the length of the property array is already set and | ||
12 | prevents the end-user from modifying them. For example, | ||
13 | attempting to use: | ||
14 | |||
15 | -device virtio-iommu-pci,\ | ||
16 | len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1 | ||
17 | |||
18 | would result in the following error message: | ||
19 | |||
20 | qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa, | ||
21 | len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1: | ||
22 | array size property len-reserved-regions may not be set more than once | ||
23 | |||
24 | Otherwise, for example, adding two reserved regions is achieved | ||
25 | using the following options: | ||
26 | |||
27 | -device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\ | ||
28 | reserved-regions[0]=0xfee00000:0xfeefffff:1,\ | ||
29 | reserved-regions[1]=0x1000000:100ffff:1 | ||
30 | |||
31 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
32 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
33 | Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
34 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
35 | Message-id: 20200629070404.10969-5-eric.auger@redhat.com | ||
36 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
37 | --- | ||
38 | hw/virtio/virtio-iommu-pci.c | 11 +++++++++++ | ||
39 | 1 file changed, 11 insertions(+) | ||
40 | |||
41 | diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/hw/virtio/virtio-iommu-pci.c | ||
44 | +++ b/hw/virtio/virtio-iommu-pci.c | ||
45 | @@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI { | ||
46 | |||
47 | static Property virtio_iommu_pci_properties[] = { | ||
48 | DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0), | ||
49 | + DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI, | ||
50 | + vdev.nb_reserved_regions, vdev.reserved_regions, | ||
51 | + qdev_prop_reserved_region, ReservedRegion), | ||
52 | DEFINE_PROP_END_OF_LIST(), | ||
53 | }; | ||
54 | |||
55 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) | ||
56 | { | ||
57 | VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev); | ||
58 | DeviceState *vdev = DEVICE(&dev->vdev); | ||
59 | + VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); | ||
60 | |||
61 | if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { | ||
62 | MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); | ||
63 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) | ||
64 | "-no-acpi\n"); | ||
65 | return; | ||
66 | } | ||
67 | + for (int i = 0; i < s->nb_reserved_regions; i++) { | ||
68 | + if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED && | ||
69 | + s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) { | ||
70 | + error_setg(errp, "reserved region %d has an invalid type", i); | ||
71 | + error_append_hint(errp, "Valid values are 0 and 1\n"); | ||
72 | + } | ||
73 | + } | ||
74 | object_property_set_link(OBJECT(dev), | ||
75 | OBJECT(pci_get_bus(&vpci_dev->pci_dev)), | ||
76 | "primary-bus", &error_abort); | ||
77 | -- | ||
78 | 2.20.1 | ||
79 | |||
80 | diff view generated by jsdifflib |
1 | From: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> | 1 | From: Eric Auger <eric.auger@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Generate an interrupt if USR2_RDR and UCR4_DREN are both set. | 3 | At the moment the virtio-iommu translates MSI transactions. |
4 | This behavior is inherited from ARM SMMU. The virt machine | ||
5 | code knows where the guest MSI doorbells are so we can easily | ||
6 | declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that | ||
7 | setting the guest will not map MSIs through the IOMMU and those | ||
8 | transactions will be simply bypassed. | ||
4 | 9 | ||
5 | Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> | 10 | Depending on which MSI controller is in use (ITS or GICV2M), |
6 | Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com | 11 | we declare either: |
12 | - the ITS interrupt translation space (ITS_base + 0x10000), | ||
13 | containing the GITS_TRANSLATOR or | ||
14 | - The GICV2M single frame, containing the MSI_SETSP_NS register. | ||
15 | |||
16 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
17 | Message-id: 20200629070404.10969-6-eric.auger@redhat.com | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 20 | --- |
10 | include/hw/char/imx_serial.h | 1 + | 21 | include/hw/arm/virt.h | 7 +++++++ |
11 | hw/char/imx_serial.c | 3 ++- | 22 | hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++ |
12 | 2 files changed, 3 insertions(+), 1 deletion(-) | 23 | 2 files changed, 37 insertions(+) |
13 | 24 | ||
14 | diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h | 25 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h |
15 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/char/imx_serial.h | 27 | --- a/include/hw/arm/virt.h |
17 | +++ b/include/hw/char/imx_serial.h | 28 | +++ b/include/hw/arm/virt.h |
18 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType { |
19 | #define UCR2_RXEN (1<<1) /* Receiver enable */ | 30 | VIRT_IOMMU_VIRTIO, |
20 | #define UCR2_SRST (1<<0) /* Reset complete */ | 31 | } VirtIOMMUType; |
21 | 32 | ||
22 | +#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ | 33 | +typedef enum VirtMSIControllerType { |
23 | #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ | 34 | + VIRT_MSI_CTRL_NONE, |
24 | 35 | + VIRT_MSI_CTRL_GICV2M, | |
25 | #define UTS1_TXEMPTY (1<<6) | 36 | + VIRT_MSI_CTRL_ITS, |
26 | diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c | 37 | +} VirtMSIControllerType; |
38 | + | ||
39 | typedef enum VirtGICType { | ||
40 | VIRT_GIC_VERSION_MAX, | ||
41 | VIRT_GIC_VERSION_HOST, | ||
42 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
43 | OnOffAuto acpi; | ||
44 | VirtGICType gic_version; | ||
45 | VirtIOMMUType iommu; | ||
46 | + VirtMSIControllerType msi_controller; | ||
47 | uint16_t virtio_iommu_bdf; | ||
48 | struct arm_boot_info bootinfo; | ||
49 | MemMapEntry *memmap; | ||
50 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 51 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/char/imx_serial.c | 52 | --- a/hw/arm/virt.c |
29 | +++ b/hw/char/imx_serial.c | 53 | +++ b/hw/arm/virt.c |
30 | @@ -XXX,XX +XXX,XX @@ static void imx_update(IMXSerialState *s) | 54 | @@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms) |
31 | mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; | 55 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base); |
32 | /* | 56 | |
33 | * TCEN and TXDC are both bit 3 | 57 | fdt_add_its_gic_node(vms); |
34 | + * RDR and DREN are both bit 0 | 58 | + vms->msi_controller = VIRT_MSI_CTRL_ITS; |
35 | */ | 59 | } |
36 | - mask |= s->ucr4 & UCR4_TCEN; | 60 | |
37 | + mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN); | 61 | static void create_v2m(VirtMachineState *vms) |
38 | 62 | @@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms) | |
39 | usr2 = s->usr2 & mask; | 63 | } |
64 | |||
65 | fdt_add_v2m_gic_node(vms); | ||
66 | + vms->msi_controller = VIRT_MSI_CTRL_GICV2M; | ||
67 | } | ||
68 | |||
69 | static void create_gic(VirtMachineState *vms) | ||
70 | @@ -XXX,XX +XXX,XX @@ out: | ||
71 | static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, | ||
72 | DeviceState *dev, Error **errp) | ||
73 | { | ||
74 | + VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | ||
75 | + | ||
76 | if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | ||
77 | virt_memory_pre_plug(hotplug_dev, dev, errp); | ||
78 | + } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | ||
79 | + hwaddr db_start = 0, db_end = 0; | ||
80 | + char *resv_prop_str; | ||
81 | + | ||
82 | + switch (vms->msi_controller) { | ||
83 | + case VIRT_MSI_CTRL_NONE: | ||
84 | + return; | ||
85 | + case VIRT_MSI_CTRL_ITS: | ||
86 | + /* GITS_TRANSLATER page */ | ||
87 | + db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000; | ||
88 | + db_end = base_memmap[VIRT_GIC_ITS].base + | ||
89 | + base_memmap[VIRT_GIC_ITS].size - 1; | ||
90 | + break; | ||
91 | + case VIRT_MSI_CTRL_GICV2M: | ||
92 | + /* MSI_SETSPI_NS page */ | ||
93 | + db_start = base_memmap[VIRT_GIC_V2M].base; | ||
94 | + db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1; | ||
95 | + break; | ||
96 | + } | ||
97 | + resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", | ||
98 | + db_start, db_end, | ||
99 | + VIRTIO_IOMMU_RESV_MEM_T_MSI); | ||
100 | + | ||
101 | + qdev_prop_set_uint32(dev, "len-reserved-regions", 1); | ||
102 | + qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); | ||
103 | + g_free(resv_prop_str); | ||
104 | } | ||
105 | } | ||
40 | 106 | ||
41 | -- | 107 | -- |
42 | 2.18.0 | 108 | 2.20.1 |
43 | 109 | ||
44 | 110 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Beata Michalska <beata.michalska@linaro.org> | ||
1 | 2 | ||
3 | On ARMv7 & ARMv8 some load/store instructions might trigger a data abort | ||
4 | exception with no valid ISS info to be decoded. The lack of decode info | ||
5 | makes it at least tricky to emulate those instruction which is one of the | ||
6 | (many) reasons why KVM will not even try to do so. | ||
7 | |||
8 | Add support for handling those by requesting KVM to inject external | ||
9 | dabt into the quest. | ||
10 | |||
11 | Signed-off-by: Beata Michalska <beata.michalska@linaro.org> | ||
12 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
13 | Message-id: 20200629114110.30723-2-beata.michalska@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++ | ||
17 | 1 file changed, 52 insertions(+) | ||
18 | |||
19 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/kvm.c | ||
22 | +++ b/target/arm/kvm.c | ||
23 | @@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { | ||
24 | |||
25 | static bool cap_has_mp_state; | ||
26 | static bool cap_has_inject_serror_esr; | ||
27 | +static bool cap_has_inject_ext_dabt; | ||
28 | |||
29 | static ARMHostCPUFeatures arm_host_cpu_features; | ||
30 | |||
31 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s) | ||
32 | ret = -EINVAL; | ||
33 | } | ||
34 | |||
35 | + if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) { | ||
36 | + if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) { | ||
37 | + error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap"); | ||
38 | + } else { | ||
39 | + /* Set status for supporting the external dabt injection */ | ||
40 | + cap_has_inject_ext_dabt = kvm_check_extension(s, | ||
41 | + KVM_CAP_ARM_INJECT_EXT_DABT); | ||
42 | + } | ||
43 | + } | ||
44 | + | ||
45 | return ret; | ||
46 | } | ||
47 | |||
48 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state) | ||
49 | } | ||
50 | } | ||
51 | |||
52 | +/** | ||
53 | + * kvm_arm_handle_dabt_nisv: | ||
54 | + * @cs: CPUState | ||
55 | + * @esr_iss: ISS encoding (limited) for the exception from Data Abort | ||
56 | + * ISV bit set to '0b0' -> no valid instruction syndrome | ||
57 | + * @fault_ipa: faulting address for the synchronous data abort | ||
58 | + * | ||
59 | + * Returns: 0 if the exception has been handled, < 0 otherwise | ||
60 | + */ | ||
61 | +static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, | ||
62 | + uint64_t fault_ipa) | ||
63 | +{ | ||
64 | + /* | ||
65 | + * Request KVM to inject the external data abort into the guest | ||
66 | + */ | ||
67 | + if (cap_has_inject_ext_dabt) { | ||
68 | + struct kvm_vcpu_events events = { }; | ||
69 | + /* | ||
70 | + * The external data abort event will be handled immediately by KVM | ||
71 | + * using the address fault that triggered the exit on given VCPU. | ||
72 | + * Requesting injection of the external data abort does not rely | ||
73 | + * on any other VCPU state. Therefore, in this particular case, the VCPU | ||
74 | + * synchronization can be exceptionally skipped. | ||
75 | + */ | ||
76 | + events.exception.ext_dabt_pending = 1; | ||
77 | + /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ | ||
78 | + return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events); | ||
79 | + } else { | ||
80 | + error_report("Data abort exception triggered by guest memory access " | ||
81 | + "at physical address: 0x" TARGET_FMT_lx, | ||
82 | + (target_ulong)fault_ipa); | ||
83 | + error_printf("KVM unable to emulate faulting instruction.\n"); | ||
84 | + } | ||
85 | + return -1; | ||
86 | +} | ||
87 | + | ||
88 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | ||
89 | { | ||
90 | int ret = 0; | ||
91 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | ||
92 | ret = EXCP_DEBUG; | ||
93 | } /* otherwise return to guest */ | ||
94 | break; | ||
95 | + case KVM_EXIT_ARM_NISV: | ||
96 | + /* External DABT with no valid iss to decode */ | ||
97 | + ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, | ||
98 | + run->arm_nisv.fault_ipa); | ||
99 | + break; | ||
100 | default: | ||
101 | qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", | ||
102 | __func__, run->exit_reason); | ||
103 | -- | ||
104 | 2.20.1 | ||
105 | |||
106 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Beata Michalska <beata.michalska@linaro.org> | |
2 | |||
3 | Injecting external data abort through KVM might trigger | ||
4 | an issue on kernels that do not get updated to include the KVM fix. | ||
5 | For those and aarch32 guests, the injected abort gets misconfigured | ||
6 | to be an implementation defined exception. This leads to the guest | ||
7 | repeatedly re-running the faulting instruction. | ||
8 | |||
9 | Add support for handling that case. | ||
10 | |||
11 | [ | ||
12 | Fixed-by: 018f22f95e8a | ||
13 | ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests') | ||
14 | Fixed-by: 21aecdbd7f3a | ||
15 | ('KVM: arm: Make inject_abt32() inject an external abort instead') | ||
16 | ] | ||
17 | |||
18 | Signed-off-by: Beata Michalska <beata.michalska@linaro.org> | ||
19 | Acked-by: Andrew Jones <drjones@redhat.com> | ||
20 | Message-id: 20200629114110.30723-3-beata.michalska@linaro.org | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | --- | ||
24 | target/arm/cpu.h | 2 ++ | ||
25 | target/arm/kvm_arm.h | 10 +++++++++ | ||
26 | target/arm/kvm.c | 30 ++++++++++++++++++++++++++- | ||
27 | target/arm/kvm32.c | 34 ++++++++++++++++++++++++++++++ | ||
28 | target/arm/kvm64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++ | ||
29 | 5 files changed, 124 insertions(+), 1 deletion(-) | ||
30 | |||
31 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/cpu.h | ||
34 | +++ b/target/arm/cpu.h | ||
35 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | ||
36 | uint64_t esr; | ||
37 | } serror; | ||
38 | |||
39 | + uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */ | ||
40 | + | ||
41 | /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */ | ||
42 | uint32_t irq_line_state; | ||
43 | |||
44 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/kvm_arm.h | ||
47 | +++ b/target/arm/kvm_arm.h | ||
48 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs); | ||
49 | struct kvm_guest_debug_arch; | ||
50 | void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); | ||
51 | |||
52 | +/** | ||
53 | + * kvm_arm_verify_ext_dabt_pending: | ||
54 | + * @cs: CPUState | ||
55 | + * | ||
56 | + * Verify the fault status code wrt the Ext DABT injection | ||
57 | + * | ||
58 | + * Returns: true if the fault status code is as expected, false otherwise | ||
59 | + */ | ||
60 | +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs); | ||
61 | + | ||
62 | /** | ||
63 | * its_class_name: | ||
64 | * | ||
65 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/kvm.c | ||
68 | +++ b/target/arm/kvm.c | ||
69 | @@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu) | ||
70 | |||
71 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) | ||
72 | { | ||
73 | + ARMCPU *cpu = ARM_CPU(cs); | ||
74 | + CPUARMState *env = &cpu->env; | ||
75 | + | ||
76 | + if (unlikely(env->ext_dabt_raised)) { | ||
77 | + /* | ||
78 | + * Verifying that the ext DABT has been properly injected, | ||
79 | + * otherwise risking indefinitely re-running the faulting instruction | ||
80 | + * Covering a very narrow case for kernels 5.5..5.5.4 | ||
81 | + * when injected abort was misconfigured to be | ||
82 | + * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) | ||
83 | + */ | ||
84 | + if (!arm_feature(env, ARM_FEATURE_AARCH64) && | ||
85 | + unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { | ||
86 | + | ||
87 | + error_report("Data abort exception with no valid ISS generated by " | ||
88 | + "guest memory access. KVM unable to emulate faulting " | ||
89 | + "instruction. Failed to inject an external data abort " | ||
90 | + "into the guest."); | ||
91 | + abort(); | ||
92 | + } | ||
93 | + /* Clear the status */ | ||
94 | + env->ext_dabt_raised = 0; | ||
95 | + } | ||
96 | } | ||
97 | |||
98 | MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) | ||
99 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state) | ||
100 | static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, | ||
101 | uint64_t fault_ipa) | ||
102 | { | ||
103 | + ARMCPU *cpu = ARM_CPU(cs); | ||
104 | + CPUARMState *env = &cpu->env; | ||
105 | /* | ||
106 | * Request KVM to inject the external data abort into the guest | ||
107 | */ | ||
108 | @@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, | ||
109 | */ | ||
110 | events.exception.ext_dabt_pending = 1; | ||
111 | /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ | ||
112 | - return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events); | ||
113 | + if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { | ||
114 | + env->ext_dabt_raised = 1; | ||
115 | + return 0; | ||
116 | + } | ||
117 | } else { | ||
118 | error_report("Data abort exception triggered by guest memory access " | ||
119 | "at physical address: 0x" TARGET_FMT_lx, | ||
120 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | ||
121 | index XXXXXXX..XXXXXXX 100644 | ||
122 | --- a/target/arm/kvm32.c | ||
123 | +++ b/target/arm/kvm32.c | ||
124 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs) | ||
125 | { | ||
126 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | ||
127 | } | ||
128 | + | ||
129 | +#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0) | ||
130 | +#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2) | ||
131 | +/* | ||
132 | + *DFSR: | ||
133 | + * TTBCR.EAE == 0 | ||
134 | + * FS[4] - DFSR[10] | ||
135 | + * FS[3:0] - DFSR[3:0] | ||
136 | + * TTBCR.EAE == 1 | ||
137 | + * FS, bits [5:0] | ||
138 | + */ | ||
139 | +#define DFSR_FSC(lpae, v) \ | ||
140 | + ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F))) | ||
141 | + | ||
142 | +#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08) | ||
143 | + | ||
144 | +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) | ||
145 | +{ | ||
146 | + uint32_t dfsr_val; | ||
147 | + | ||
148 | + if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) { | ||
149 | + ARMCPU *cpu = ARM_CPU(cs); | ||
150 | + CPUARMState *env = &cpu->env; | ||
151 | + uint32_t ttbcr; | ||
152 | + int lpae = 0; | ||
153 | + | ||
154 | + if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) { | ||
155 | + lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE); | ||
156 | + } | ||
157 | + /* The verification is based on FS filed of the DFSR reg only*/ | ||
158 | + return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae)); | ||
159 | + } | ||
160 | + return false; | ||
161 | +} | ||
162 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
163 | index XXXXXXX..XXXXXXX 100644 | ||
164 | --- a/target/arm/kvm64.c | ||
165 | +++ b/target/arm/kvm64.c | ||
166 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit) | ||
167 | |||
168 | return false; | ||
169 | } | ||
170 | + | ||
171 | +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) | ||
172 | +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) | ||
173 | + | ||
174 | +/* | ||
175 | + * ESR_EL1 | ||
176 | + * ISS encoding | ||
177 | + * AARCH64: DFSC, bits [5:0] | ||
178 | + * AARCH32: | ||
179 | + * TTBCR.EAE == 0 | ||
180 | + * FS[4] - DFSR[10] | ||
181 | + * FS[3:0] - DFSR[3:0] | ||
182 | + * TTBCR.EAE == 1 | ||
183 | + * FS, bits [5:0] | ||
184 | + */ | ||
185 | +#define ESR_DFSC(aarch64, lpae, v) \ | ||
186 | + ((aarch64 || (lpae)) ? ((v) & 0x3F) \ | ||
187 | + : (((v) >> 6) | ((v) & 0x1F))) | ||
188 | + | ||
189 | +#define ESR_DFSC_EXTABT(aarch64, lpae) \ | ||
190 | + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) | ||
191 | + | ||
192 | +bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) | ||
193 | +{ | ||
194 | + uint64_t dfsr_val; | ||
195 | + | ||
196 | + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { | ||
197 | + ARMCPU *cpu = ARM_CPU(cs); | ||
198 | + CPUARMState *env = &cpu->env; | ||
199 | + int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64); | ||
200 | + int lpae = 0; | ||
201 | + | ||
202 | + if (!aarch64_mode) { | ||
203 | + uint64_t ttbcr; | ||
204 | + | ||
205 | + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { | ||
206 | + lpae = arm_feature(env, ARM_FEATURE_LPAE) | ||
207 | + && (ttbcr & TTBCR_EAE); | ||
208 | + } | ||
209 | + } | ||
210 | + /* | ||
211 | + * The verification here is based on the DFSC bits | ||
212 | + * of the ESR_EL1 reg only | ||
213 | + */ | ||
214 | + return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) == | ||
215 | + ESR_DFSC_EXTABT(aarch64_mode, lpae)); | ||
216 | + } | ||
217 | + return false; | ||
218 | +} | ||
219 | -- | ||
220 | 2.20.1 | ||
221 | |||
222 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files") | ||
4 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
5 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Message-id: 20200629140938.17566-2-drjones@redhat.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------ | ||
11 | 1 file changed, 18 deletions(-) | ||
12 | |||
13 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
16 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
17 | @@ -1,19 +1 @@ | ||
18 | /* List of comma-separated changed AML files to ignore */ | ||
19 | -"tests/data/acpi/pc/DSDT", | ||
20 | -"tests/data/acpi/pc/DSDT.acpihmat", | ||
21 | -"tests/data/acpi/pc/DSDT.bridge", | ||
22 | -"tests/data/acpi/pc/DSDT.cphp", | ||
23 | -"tests/data/acpi/pc/DSDT.dimmpxm", | ||
24 | -"tests/data/acpi/pc/DSDT.ipmikcs", | ||
25 | -"tests/data/acpi/pc/DSDT.memhp", | ||
26 | -"tests/data/acpi/pc/DSDT.numamem", | ||
27 | -"tests/data/acpi/q35/DSDT", | ||
28 | -"tests/data/acpi/q35/DSDT.acpihmat", | ||
29 | -"tests/data/acpi/q35/DSDT.bridge", | ||
30 | -"tests/data/acpi/q35/DSDT.cphp", | ||
31 | -"tests/data/acpi/q35/DSDT.dimmpxm", | ||
32 | -"tests/data/acpi/q35/DSDT.ipmibt", | ||
33 | -"tests/data/acpi/q35/DSDT.memhp", | ||
34 | -"tests/data/acpi/q35/DSDT.mmio64", | ||
35 | -"tests/data/acpi/q35/DSDT.numamem", | ||
36 | -"tests/data/acpi/q35/DSDT.tis", | ||
37 | -- | ||
38 | 2.20.1 | ||
39 | |||
40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
4 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
5 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
6 | Message-id: 20200629140938.17566-3-drjones@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ | ||
10 | 1 file changed, 3 insertions(+) | ||
11 | |||
12 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
15 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
16 | @@ -1 +1,4 @@ | ||
17 | /* List of comma-separated changed AML files to ignore */ | ||
18 | +"tests/data/acpi/virt/DSDT", | ||
19 | +"tests/data/acpi/virt/DSDT.memhp", | ||
20 | +"tests/data/acpi/virt/DSDT.numamem", | ||
21 | -- | ||
22 | 2.20.1 | ||
23 | |||
24 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Andrew Jones <drjones@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | The flash device is exclusively for the host-controlled firmware, so | ||
4 | we should not expose it to the OS. Exposing it risks the OS messing | ||
5 | with it, which could break firmware runtime services and surprise the | ||
6 | OS when all its changes disappear after reboot. | ||
7 | |||
8 | As firmware needs the device and uses DT, we leave the device exposed | ||
9 | there. It's up to firmware to remove the nodes from DT before sending | ||
10 | it on to the OS. However, there's no need to force firmware to remove | ||
11 | tables from ACPI (which it doesn't know how to do anyway), so we | ||
12 | simply don't add the tables in the first place. But, as we've been | ||
13 | adding the tables for quite some time and don't want to change the | ||
14 | default hardware exposed to versioned machines, then we only stop | ||
15 | exposing the flash device tables for 5.1 and later machine types. | ||
16 | |||
17 | Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com> | ||
18 | Suggested-by: Laszlo Ersek <lersek@redhat.com> | ||
3 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 19 | Signed-off-by: Andrew Jones <drjones@redhat.com> |
4 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 20 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
22 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
23 | Reviewed-by: Laszlo Ersek <lersek@redhat.com> | ||
24 | Message-id: 20200629140938.17566-4-drjones@redhat.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 26 | --- |
8 | hw/arm/virt.c | 23 +++++++++++++++++------ | 27 | include/hw/arm/virt.h | 1 + |
9 | 1 file changed, 17 insertions(+), 6 deletions(-) | 28 | hw/arm/virt-acpi-build.c | 5 ++++- |
29 | hw/arm/virt.c | 3 +++ | ||
30 | 3 files changed, 8 insertions(+), 1 deletion(-) | ||
10 | 31 | ||
32 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/hw/arm/virt.h | ||
35 | +++ b/include/hw/arm/virt.h | ||
36 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
37 | bool no_highmem_ecam; | ||
38 | bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ | ||
39 | bool kvm_no_adjvtime; | ||
40 | + bool acpi_expose_flash; | ||
41 | } VirtMachineClass; | ||
42 | |||
43 | typedef struct { | ||
44 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/hw/arm/virt-acpi-build.c | ||
47 | +++ b/hw/arm/virt-acpi-build.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, | ||
49 | static void | ||
50 | build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
51 | { | ||
52 | + VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | ||
53 | Aml *scope, *dsdt; | ||
54 | MachineState *ms = MACHINE(vms); | ||
55 | const MemMapEntry *memmap = vms->memmap; | ||
56 | @@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
57 | acpi_dsdt_add_cpus(scope, vms->smp_cpus); | ||
58 | acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], | ||
59 | (irqmap[VIRT_UART] + ARM_SPI_BASE)); | ||
60 | - acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | ||
61 | + if (vmc->acpi_expose_flash) { | ||
62 | + acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); | ||
63 | + } | ||
64 | acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]); | ||
65 | acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], | ||
66 | (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS); | ||
11 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 67 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
12 | index XXXXXXX..XXXXXXX 100644 | 68 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/virt.c | 69 | --- a/hw/arm/virt.c |
14 | +++ b/hw/arm/virt.c | 70 | +++ b/hw/arm/virt.c |
15 | @@ -XXX,XX +XXX,XX @@ static void machvirt_machine_init(void) | 71 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1) |
72 | |||
73 | static void virt_machine_5_0_options(MachineClass *mc) | ||
74 | { | ||
75 | + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); | ||
76 | + | ||
77 | virt_machine_5_1_options(mc); | ||
78 | compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); | ||
79 | mc->numa_mem_supported = true; | ||
80 | + vmc->acpi_expose_flash = true; | ||
16 | } | 81 | } |
17 | type_init(machvirt_machine_init); | 82 | DEFINE_VIRT_MACHINE(5, 0) |
18 | 83 | ||
19 | -#define VIRT_COMPAT_2_12 \ | ||
20 | - HW_COMPAT_2_12 | ||
21 | - | ||
22 | -static void virt_3_0_instance_init(Object *obj) | ||
23 | +static void virt_3_1_instance_init(Object *obj) | ||
24 | { | ||
25 | VirtMachineState *vms = VIRT_MACHINE(obj); | ||
26 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | ||
27 | @@ -XXX,XX +XXX,XX @@ static void virt_3_0_instance_init(Object *obj) | ||
28 | vms->irqmap = a15irqmap; | ||
29 | } | ||
30 | |||
31 | -static void virt_machine_3_0_options(MachineClass *mc) | ||
32 | +static void virt_machine_3_1_options(MachineClass *mc) | ||
33 | { | ||
34 | } | ||
35 | -DEFINE_VIRT_MACHINE_AS_LATEST(3, 0) | ||
36 | +DEFINE_VIRT_MACHINE_AS_LATEST(3, 1) | ||
37 | + | ||
38 | +static void virt_3_0_instance_init(Object *obj) | ||
39 | +{ | ||
40 | + virt_3_1_instance_init(obj); | ||
41 | +} | ||
42 | + | ||
43 | +static void virt_machine_3_0_options(MachineClass *mc) | ||
44 | +{ | ||
45 | + virt_machine_3_1_options(mc); | ||
46 | +} | ||
47 | +DEFINE_VIRT_MACHINE(3, 0) | ||
48 | + | ||
49 | +#define VIRT_COMPAT_2_12 \ | ||
50 | + HW_COMPAT_2_12 | ||
51 | |||
52 | static void virt_2_12_instance_init(Object *obj) | ||
53 | { | ||
54 | -- | 84 | -- |
55 | 2.18.0 | 85 | 2.20.1 |
56 | 86 | ||
57 | 87 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | Differences between disassembled ASL files for DSDT: | ||
4 | |||
5 | @@ -XXX,XX +XXX,XX @@ | ||
6 | * | ||
7 | * Disassembling to symbolic ASL+ operators | ||
8 | * | ||
9 | - * Disassembly of a, Mon Jun 29 09:50:01 2020 | ||
10 | + * Disassembly of b, Mon Jun 29 09:50:03 2020 | ||
11 | * | ||
12 | * Original Table Header: | ||
13 | * Signature "DSDT" | ||
14 | - * Length 0x000014BB (5307) | ||
15 | + * Length 0x00001455 (5205) | ||
16 | * Revision 0x02 | ||
17 | - * Checksum 0xD1 | ||
18 | + * Checksum 0xE1 | ||
19 | * OEM ID "BOCHS " | ||
20 | * OEM Table ID "BXPCDSDT" | ||
21 | * OEM Revision 0x00000001 (1) | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | }) | ||
24 | } | ||
25 | |||
26 | - Device (FLS0) | ||
27 | - { | ||
28 | - Name (_HID, "LNRO0015") // _HID: Hardware ID | ||
29 | - Name (_UID, Zero) // _UID: Unique ID | ||
30 | - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
31 | - { | ||
32 | - Memory32Fixed (ReadWrite, | ||
33 | - 0x00000000, // Address Base | ||
34 | - 0x04000000, // Address Length | ||
35 | - ) | ||
36 | - }) | ||
37 | - } | ||
38 | - | ||
39 | - Device (FLS1) | ||
40 | - { | ||
41 | - Name (_HID, "LNRO0015") // _HID: Hardware ID | ||
42 | - Name (_UID, One) // _UID: Unique ID | ||
43 | - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
44 | - { | ||
45 | - Memory32Fixed (ReadWrite, | ||
46 | - 0x04000000, // Address Base | ||
47 | - 0x04000000, // Address Length | ||
48 | - ) | ||
49 | - }) | ||
50 | - } | ||
51 | - | ||
52 | Device (FWCF) | ||
53 | { | ||
54 | Name (_HID, "QEMU0002") // _HID: Hardware ID | ||
55 | |||
56 | The other two binaries have the same changes (the removal of the | ||
57 | flash devices). | ||
58 | |||
59 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
60 | Reviewed-by: Michael S. Tsirkin <mst@redhat.com> | ||
61 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
62 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
63 | Reviewed-by: Laszlo Ersek <lersek@redhat.com> | ||
64 | Message-id: 20200629140938.17566-5-drjones@redhat.com | ||
65 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
66 | --- | ||
67 | tests/qtest/bios-tables-test-allowed-diff.h | 3 --- | ||
68 | tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes | ||
69 | tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes | ||
70 | tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes | ||
71 | 4 files changed, 3 deletions(-) | ||
72 | |||
73 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
76 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
77 | @@ -1,4 +1 @@ | ||
78 | /* List of comma-separated changed AML files to ignore */ | ||
79 | -"tests/data/acpi/virt/DSDT", | ||
80 | -"tests/data/acpi/virt/DSDT.memhp", | ||
81 | -"tests/data/acpi/virt/DSDT.numamem", | ||
82 | diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | GIT binary patch | ||
85 | delta 28 | ||
86 | kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a | ||
87 | |||
88 | delta 156 | ||
89 | zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+ | ||
90 | zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5 | ||
91 | LaERl^1zUvy_;n(J | ||
92 | |||
93 | diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | GIT binary patch | ||
96 | delta 28 | ||
97 | kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910 | ||
98 | |||
99 | delta 156 | ||
100 | zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^ | ||
101 | zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj | ||
102 | LIK*+|0yaqism~!^ | ||
103 | |||
104 | diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | GIT binary patch | ||
107 | delta 28 | ||
108 | kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a | ||
109 | |||
110 | delta 156 | ||
111 | zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+ | ||
112 | zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5 | ||
113 | LaERl^1zUvy_;n(J | ||
114 | |||
115 | -- | ||
116 | 2.20.1 | ||
117 | |||
118 | diff view generated by jsdifflib |
1 | From: Roman Kapl <rka@sysgo.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | If an instruction is conditional (like CBZ) and it is executed | 3 | The temp that gets assigned to clean_addr has been allocated with |
4 | conditionally (using the ITx instruction), a jump to an undefined | 4 | new_tmp_a64, which means that it will be freed at the end of the |
5 | label is generated, and QEMU crashes. | 5 | instruction. Freeing it earlier leads to assertion failure. |
6 | 6 | ||
7 | CBZ in IT block is an UNPREDICTABLE behavior, but we should not | 7 | The loop creates a complication, in which we allocate a new local |
8 | crash. Honouring the condition code is allowed by the spec in this | 8 | temp, which does need freeing, and the final code path is shared |
9 | case (constrained unpredictable, ARMv8, section K1.1.7), and matches | 9 | between the loop and non-loop. |
10 | what we do for other "UNPREDICTABLE inside an IT block" instructions. | ||
11 | 10 | ||
12 | Fix the 'skip on condition' code to create a new label only if it | 11 | Fix this complication by adding new_tmp_a64_local so that the new |
13 | does not already exist. Previously multiple labels were created, but | 12 | local temp is freed at the end, and can be treated exactly like |
14 | only the last one of them was set. | 13 | the non-loop path. |
15 | 14 | ||
16 | Signed-off-by: Roman Kapl <rka@sysgo.com> | 15 | Fixes: bba87d0a0f4 |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
18 | Message-id: 20180816120533.6587-1-rka@sysgo.com | 17 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
19 | [PMM: fixed ^ 1 being applied to wrong argument, fixed typo] | 18 | Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org |
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
22 | --- | 20 | --- |
23 | target/arm/translate.c | 35 +++++++++++++++++++++-------------- | 21 | target/arm/translate-a64.h | 1 + |
24 | 1 file changed, 21 insertions(+), 14 deletions(-) | 22 | target/arm/translate-a64.c | 6 ++++++ |
23 | target/arm/translate-sve.c | 8 ++------ | ||
24 | 3 files changed, 9 insertions(+), 6 deletions(-) | ||
25 | 25 | ||
26 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 26 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h |
27 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/translate.c | 28 | --- a/target/arm/translate-a64.h |
29 | +++ b/target/arm/translate.c | 29 | +++ b/target/arm/translate-a64.h |
30 | @@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s, | 30 | @@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s); |
31 | s->base.is_jmp = DISAS_UPDATE; | 31 | } while (0) |
32 | |||
33 | TCGv_i64 new_tmp_a64(DisasContext *s); | ||
34 | +TCGv_i64 new_tmp_a64_local(DisasContext *s); | ||
35 | TCGv_i64 new_tmp_a64_zero(DisasContext *s); | ||
36 | TCGv_i64 cpu_reg(DisasContext *s, int reg); | ||
37 | TCGv_i64 cpu_reg_sp(DisasContext *s, int reg); | ||
38 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/translate-a64.c | ||
41 | +++ b/target/arm/translate-a64.c | ||
42 | @@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s) | ||
43 | return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); | ||
32 | } | 44 | } |
33 | 45 | ||
34 | +/* Generate a label used for skipping this instruction */ | 46 | +TCGv_i64 new_tmp_a64_local(DisasContext *s) |
35 | +static void arm_gen_condlabel(DisasContext *s) | ||
36 | +{ | 47 | +{ |
37 | + if (!s->condjmp) { | 48 | + assert(s->tmp_a64_count < TMP_A64_MAX); |
38 | + s->condlabel = gen_new_label(); | 49 | + return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64(); |
39 | + s->condjmp = 1; | ||
40 | + } | ||
41 | +} | 50 | +} |
42 | + | 51 | + |
43 | +/* Skip this instruction if the ARM condition is false */ | 52 | TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
44 | +static void arm_skip_unless(DisasContext *s, uint32_t cond) | ||
45 | +{ | ||
46 | + arm_gen_condlabel(s); | ||
47 | + arm_gen_test_cc(cond ^ 1, s->condlabel); | ||
48 | +} | ||
49 | + | ||
50 | static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
51 | { | 53 | { |
52 | unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; | 54 | TCGv_i64 t = new_tmp_a64(s); |
53 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 55 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
54 | if (cond != 0xe) { | 56 | index XXXXXXX..XXXXXXX 100644 |
55 | /* if not always execute, we generate a conditional jump to | 57 | --- a/target/arm/translate-sve.c |
56 | next instruction */ | 58 | +++ b/target/arm/translate-sve.c |
57 | - s->condlabel = gen_new_label(); | 59 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
58 | - arm_gen_test_cc(cond ^ 1, s->condlabel); | 60 | |
59 | - s->condjmp = 1; | 61 | /* Copy the clean address into a local temp, live across the loop. */ |
60 | + arm_skip_unless(s, cond); | 62 | t0 = clean_addr; |
63 | - clean_addr = tcg_temp_local_new_i64(); | ||
64 | + clean_addr = new_tmp_a64_local(s); | ||
65 | tcg_gen_mov_i64(clean_addr, t0); | ||
66 | - tcg_temp_free_i64(t0); | ||
67 | |||
68 | gen_set_label(loop); | ||
69 | |||
70 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | ||
71 | tcg_gen_st_i64(t0, cpu_env, vofs + len_align); | ||
72 | tcg_temp_free_i64(t0); | ||
61 | } | 73 | } |
62 | if ((insn & 0x0f900000) == 0x03000000) { | 74 | - tcg_temp_free_i64(clean_addr); |
63 | if ((insn & (1 << 21)) == 0) { | 75 | } |
64 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 76 | |
65 | /* Conditional branch. */ | 77 | /* Similarly for stores. */ |
66 | op = (insn >> 22) & 0xf; | 78 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
67 | /* Generate a conditional jump to next instruction. */ | 79 | |
68 | - s->condlabel = gen_new_label(); | 80 | /* Copy the clean address into a local temp, live across the loop. */ |
69 | - arm_gen_test_cc(op ^ 1, s->condlabel); | 81 | t0 = clean_addr; |
70 | - s->condjmp = 1; | 82 | - clean_addr = tcg_temp_local_new_i64(); |
71 | + arm_skip_unless(s, op); | 83 | + clean_addr = new_tmp_a64_local(s); |
72 | 84 | tcg_gen_mov_i64(clean_addr, t0); | |
73 | /* offset[11:1] = insn[10:0] */ | 85 | - tcg_temp_free_i64(t0); |
74 | offset = (insn & 0x7ff) << 1; | 86 | |
75 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) | 87 | gen_set_label(loop); |
76 | case 1: case 3: case 9: case 11: /* czb */ | 88 | |
77 | rm = insn & 7; | 89 | @@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) |
78 | tmp = load_reg(s, rm); | ||
79 | - s->condlabel = gen_new_label(); | ||
80 | - s->condjmp = 1; | ||
81 | + arm_gen_condlabel(s); | ||
82 | if (insn & (1 << 11)) | ||
83 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); | ||
84 | else | ||
85 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) | ||
86 | break; | ||
87 | } | 90 | } |
88 | /* generate a conditional jump to next instruction */ | 91 | tcg_temp_free_i64(t0); |
89 | - s->condlabel = gen_new_label(); | ||
90 | - arm_gen_test_cc(cond ^ 1, s->condlabel); | ||
91 | - s->condjmp = 1; | ||
92 | + arm_skip_unless(s, cond); | ||
93 | |||
94 | /* jump to the offset */ | ||
95 | val = (uint32_t)s->pc + 2; | ||
96 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
97 | uint32_t cond = dc->condexec_cond; | ||
98 | |||
99 | if (cond != 0x0e) { /* Skip conditional when condition is AL. */ | ||
100 | - dc->condlabel = gen_new_label(); | ||
101 | - arm_gen_test_cc(cond ^ 1, dc->condlabel); | ||
102 | - dc->condjmp = 1; | ||
103 | + arm_skip_unless(dc, cond); | ||
104 | } | ||
105 | } | 92 | } |
106 | 93 | - tcg_temp_free_i64(clean_addr); | |
94 | } | ||
95 | |||
96 | static bool trans_LDR_zri(DisasContext *s, arg_rri *a) | ||
107 | -- | 97 | -- |
108 | 2.18.0 | 98 | 2.20.1 |
109 | 99 | ||
110 | 100 | diff view generated by jsdifflib |
1 | A bug in the handling of the register address decode logic | 1 | In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we |
---|---|---|---|
2 | for the PL08x meant that we were incorrectly treating | 2 | pass a pointer to a local struct to another function without |
3 | accesses to the DMA channel registers (DMACCxSrcAddr, | 3 | initializing all its fields. This is a real bug: |
4 | DMACCxDestaddr, DMACCxLLI, DMACCxControl, DMACCxConfiguration) | 4 | bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig |
5 | as bad offsets. Fix this long-standing bug. | 5 | struct into s->config, so any fields we don't initialize will corrupt |
6 | the state of the device. | ||
6 | 7 | ||
7 | Fixes: https://bugs.launchpad.net/qemu/+bug/1637974 | 8 | Copy the two fields which we don't want to update (pixo and alpha) |
9 | from the existing config so we don't accidentally change them. | ||
10 | |||
11 | Fixes: cfb7ba983857e40e88 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
14 | Message-id: 20200628195436.27582-1-peter.maydell@linaro.org | ||
10 | --- | 15 | --- |
11 | hw/dma/pl080.c | 5 +++-- | 16 | hw/display/bcm2835_fb.c | 4 ++++ |
12 | 1 file changed, 3 insertions(+), 2 deletions(-) | 17 | 1 file changed, 4 insertions(+) |
13 | 18 | ||
14 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | 19 | diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c |
15 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/dma/pl080.c | 21 | --- a/hw/display/bcm2835_fb.c |
17 | +++ b/hw/dma/pl080.c | 22 | +++ b/hw/display/bcm2835_fb.c |
18 | @@ -XXX,XX +XXX,XX @@ static uint64_t pl080_read(void *opaque, hwaddr offset, | 23 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value) |
19 | i = (offset & 0xe0) >> 5; | 24 | newconf.base = s->vcram_base | (value & 0xc0000000); |
20 | if (i >= s->nchannels) | 25 | newconf.base += BCM2835_FB_OFFSET; |
21 | goto bad_offset; | 26 | |
22 | - switch (offset >> 2) { | 27 | + /* Copy fields which we don't want to change from the existing config */ |
23 | + switch ((offset >> 2) & 7) { | 28 | + newconf.pixo = s->config.pixo; |
24 | case 0: /* SrcAddr */ | 29 | + newconf.alpha = s->config.alpha; |
25 | return s->chan[i].src; | 30 | + |
26 | case 1: /* DestAddr */ | 31 | bcm2835_fb_validate_config(&newconf); |
27 | @@ -XXX,XX +XXX,XX @@ static void pl080_write(void *opaque, hwaddr offset, | 32 | |
28 | i = (offset & 0xe0) >> 5; | 33 | pitch = bcm2835_fb_get_pitch(&newconf); |
29 | if (i >= s->nchannels) | ||
30 | goto bad_offset; | ||
31 | - switch (offset >> 2) { | ||
32 | + switch ((offset >> 2) & 7) { | ||
33 | case 0: /* SrcAddr */ | ||
34 | s->chan[i].src = value; | ||
35 | break; | ||
36 | @@ -XXX,XX +XXX,XX @@ static void pl080_write(void *opaque, hwaddr offset, | ||
37 | pl080_run(s); | ||
38 | break; | ||
39 | } | ||
40 | + return; | ||
41 | } | ||
42 | switch (offset >> 2) { | ||
43 | case 2: /* IntTCClear */ | ||
44 | -- | 34 | -- |
45 | 2.18.0 | 35 | 2.20.1 |
46 | 36 | ||
47 | 37 | diff view generated by jsdifflib |
1 | We now support direct execution from MMIO regions in the | 1 | The spitz board has been around a long time, and still has a fair number |
---|---|---|---|
2 | core memory subsystem. This means that we don't need to | 2 | of hard-coded tab characters in it. We're about to do some work on |
3 | have device-specific support for it, and we can remove | 3 | this source file, so start out by expanding out the tabs. |
4 | the request_ptr handling from the Xilinx SPIPS device. | 4 | |
5 | (It was broken anyway due to race conditions, and disabled | 5 | This commit is a pure whitespace only change. |
6 | by default.) | ||
7 | |||
8 | This device is the only in-tree user of this API. | ||
9 | 6 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
13 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | 10 | Message-id: 20200628142429.17111-2-peter.maydell@linaro.org |
14 | Message-id: 20180817114619.22354-2-peter.maydell@linaro.org | ||
15 | --- | 11 | --- |
16 | hw/ssi/xilinx_spips.c | 46 ------------------------------------------- | 12 | hw/arm/spitz.c | 156 ++++++++++++++++++++++++------------------------- |
17 | 1 file changed, 46 deletions(-) | 13 | 1 file changed, 78 insertions(+), 78 deletions(-) |
18 | 14 | ||
19 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | 15 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/ssi/xilinx_spips.c | 17 | --- a/hw/arm/spitz.c |
22 | +++ b/hw/ssi/xilinx_spips.c | 18 | +++ b/hw/arm/spitz.c |
23 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps spips_ops = { | 19 | @@ -XXX,XX +XXX,XX @@ |
24 | 20 | #include "cpu.h" | |
25 | static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) | 21 | |
22 | #undef REG_FMT | ||
23 | -#define REG_FMT "0x%02lx" | ||
24 | +#define REG_FMT "0x%02lx" | ||
25 | |||
26 | /* Spitz Flash */ | ||
27 | -#define FLASH_BASE 0x0c000000 | ||
28 | -#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ | ||
29 | -#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ | ||
30 | -#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ | ||
31 | -#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ | ||
32 | -#define FLASH_ECCCLRR 0x10 /* Clear ECC */ | ||
33 | -#define FLASH_FLASHIO 0x14 /* Flash I/O */ | ||
34 | -#define FLASH_FLASHCTL 0x18 /* Flash Control */ | ||
35 | +#define FLASH_BASE 0x0c000000 | ||
36 | +#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ | ||
37 | +#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */ | ||
38 | +#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */ | ||
39 | +#define FLASH_ECCCNTR 0x0c /* ECC byte counter */ | ||
40 | +#define FLASH_ECCCLRR 0x10 /* Clear ECC */ | ||
41 | +#define FLASH_FLASHIO 0x14 /* Flash I/O */ | ||
42 | +#define FLASH_FLASHCTL 0x18 /* Flash Control */ | ||
43 | |||
44 | -#define FLASHCTL_CE0 (1 << 0) | ||
45 | -#define FLASHCTL_CLE (1 << 1) | ||
46 | -#define FLASHCTL_ALE (1 << 2) | ||
47 | -#define FLASHCTL_WP (1 << 3) | ||
48 | -#define FLASHCTL_CE1 (1 << 4) | ||
49 | -#define FLASHCTL_RYBY (1 << 5) | ||
50 | -#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) | ||
51 | +#define FLASHCTL_CE0 (1 << 0) | ||
52 | +#define FLASHCTL_CLE (1 << 1) | ||
53 | +#define FLASHCTL_ALE (1 << 2) | ||
54 | +#define FLASHCTL_WP (1 << 3) | ||
55 | +#define FLASHCTL_CE1 (1 << 4) | ||
56 | +#define FLASHCTL_RYBY (1 << 5) | ||
57 | +#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1) | ||
58 | |||
59 | #define TYPE_SL_NAND "sl-nand" | ||
60 | #define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND) | ||
61 | @@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size) | ||
62 | int ryby; | ||
63 | |||
64 | switch (addr) { | ||
65 | -#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) | ||
66 | +#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to)) | ||
67 | case FLASH_ECCLPLB: | ||
68 | return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) | | ||
69 | BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7); | ||
70 | |||
71 | -#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) | ||
72 | +#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to)) | ||
73 | case FLASH_ECCLPUB: | ||
74 | return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) | | ||
75 | BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7); | ||
76 | @@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp) | ||
77 | |||
78 | /* Spitz Keyboard */ | ||
79 | |||
80 | -#define SPITZ_KEY_STROBE_NUM 11 | ||
81 | -#define SPITZ_KEY_SENSE_NUM 7 | ||
82 | +#define SPITZ_KEY_STROBE_NUM 11 | ||
83 | +#define SPITZ_KEY_SENSE_NUM 7 | ||
84 | |||
85 | static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = { | ||
86 | 12, 17, 91, 34, 36, 38, 39 | ||
87 | @@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = { | ||
88 | { 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 }, | ||
89 | }; | ||
90 | |||
91 | -#define SPITZ_GPIO_AK_INT 13 /* Remote control */ | ||
92 | -#define SPITZ_GPIO_SYNC 16 /* Sync button */ | ||
93 | -#define SPITZ_GPIO_ON_KEY 95 /* Power button */ | ||
94 | -#define SPITZ_GPIO_SWA 97 /* Lid */ | ||
95 | -#define SPITZ_GPIO_SWB 96 /* Tablet mode */ | ||
96 | +#define SPITZ_GPIO_AK_INT 13 /* Remote control */ | ||
97 | +#define SPITZ_GPIO_SYNC 16 /* Sync button */ | ||
98 | +#define SPITZ_GPIO_ON_KEY 95 /* Power button */ | ||
99 | +#define SPITZ_GPIO_SWA 97 /* Lid */ | ||
100 | +#define SPITZ_GPIO_SWB 96 /* Tablet mode */ | ||
101 | |||
102 | /* The special buttons are mapped to unused keys */ | ||
103 | static const int spitz_gpiomap[5] = { | ||
104 | @@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode) | ||
105 | #define SPITZ_MOD_CTRL (1 << 8) | ||
106 | #define SPITZ_MOD_FN (1 << 9) | ||
107 | |||
108 | -#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c | ||
109 | +#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c | ||
110 | |||
111 | static void spitz_keyboard_handler(void *opaque, int keycode) | ||
26 | { | 112 | { |
27 | - XilinxSPIPS *s = &q->parent_obj; | 113 | @@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode) |
28 | - | 114 | uint16_t code; |
29 | - if ((q->mmio_execution_enabled) && (q->lqspi_cached_addr != ~0ULL)) { | 115 | int mapcode; |
30 | - /* Invalidate the current mapped mmio */ | 116 | switch (keycode) { |
31 | - memory_region_invalidate_mmio_ptr(&s->mmlqspi, q->lqspi_cached_addr, | 117 | - case 0x2a: /* Left Shift */ |
32 | - LQSPI_CACHE_SIZE); | 118 | + case 0x2a: /* Left Shift */ |
33 | - } | 119 | s->modifiers |= 1; |
34 | - | 120 | break; |
35 | q->lqspi_cached_addr = ~0ULL; | 121 | case 0xaa: |
122 | s->modifiers &= ~1; | ||
123 | break; | ||
124 | - case 0x36: /* Right Shift */ | ||
125 | + case 0x36: /* Right Shift */ | ||
126 | s->modifiers |= 2; | ||
127 | break; | ||
128 | case 0xb6: | ||
129 | s->modifiers &= ~2; | ||
130 | break; | ||
131 | - case 0x1d: /* Control */ | ||
132 | + case 0x1d: /* Control */ | ||
133 | s->modifiers |= 4; | ||
134 | break; | ||
135 | case 0x9d: | ||
136 | s->modifiers &= ~4; | ||
137 | break; | ||
138 | - case 0x38: /* Alt */ | ||
139 | + case 0x38: /* Alt */ | ||
140 | s->modifiers |= 8; | ||
141 | break; | ||
142 | case 0xb8: | ||
143 | @@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp) | ||
144 | |||
145 | /* LCD backlight controller */ | ||
146 | |||
147 | -#define LCDTG_RESCTL 0x00 | ||
148 | -#define LCDTG_PHACTRL 0x01 | ||
149 | -#define LCDTG_DUTYCTRL 0x02 | ||
150 | -#define LCDTG_POWERREG0 0x03 | ||
151 | -#define LCDTG_POWERREG1 0x04 | ||
152 | -#define LCDTG_GPOR3 0x05 | ||
153 | -#define LCDTG_PICTRL 0x06 | ||
154 | -#define LCDTG_POLCTRL 0x07 | ||
155 | +#define LCDTG_RESCTL 0x00 | ||
156 | +#define LCDTG_PHACTRL 0x01 | ||
157 | +#define LCDTG_DUTYCTRL 0x02 | ||
158 | +#define LCDTG_POWERREG0 0x03 | ||
159 | +#define LCDTG_POWERREG1 0x04 | ||
160 | +#define LCDTG_GPOR3 0x05 | ||
161 | +#define LCDTG_PICTRL 0x06 | ||
162 | +#define LCDTG_POLCTRL 0x07 | ||
163 | |||
164 | typedef struct { | ||
165 | SSISlave ssidev; | ||
166 | @@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp) | ||
167 | |||
168 | /* SSP devices */ | ||
169 | |||
170 | -#define CORGI_SSP_PORT 2 | ||
171 | +#define CORGI_SSP_PORT 2 | ||
172 | |||
173 | -#define SPITZ_GPIO_LCDCON_CS 53 | ||
174 | -#define SPITZ_GPIO_ADS7846_CS 14 | ||
175 | -#define SPITZ_GPIO_MAX1111_CS 20 | ||
176 | -#define SPITZ_GPIO_TP_INT 11 | ||
177 | +#define SPITZ_GPIO_LCDCON_CS 53 | ||
178 | +#define SPITZ_GPIO_ADS7846_CS 14 | ||
179 | +#define SPITZ_GPIO_MAX1111_CS 20 | ||
180 | +#define SPITZ_GPIO_TP_INT 11 | ||
181 | |||
182 | static DeviceState *max1111; | ||
183 | |||
184 | @@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) | ||
185 | s->enable[line] = !level; | ||
36 | } | 186 | } |
37 | 187 | ||
38 | @@ -XXX,XX +XXX,XX @@ static void lqspi_load_cache(void *opaque, hwaddr addr) | 188 | -#define MAX1111_BATT_VOLT 1 |
189 | -#define MAX1111_BATT_TEMP 2 | ||
190 | -#define MAX1111_ACIN_VOLT 3 | ||
191 | +#define MAX1111_BATT_VOLT 1 | ||
192 | +#define MAX1111_BATT_TEMP 2 | ||
193 | +#define MAX1111_ACIN_VOLT 3 | ||
194 | |||
195 | -#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ | ||
196 | -#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ | ||
197 | -#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ | ||
198 | +#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */ | ||
199 | +#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ | ||
200 | +#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ | ||
201 | |||
202 | static void spitz_adc_temp_on(void *opaque, int line, int level) | ||
203 | { | ||
204 | @@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot) | ||
205 | |||
206 | /* Wm8750 and Max7310 on I2C */ | ||
207 | |||
208 | -#define AKITA_MAX_ADDR 0x18 | ||
209 | -#define SPITZ_WM_ADDRL 0x1b | ||
210 | -#define SPITZ_WM_ADDRH 0x1a | ||
211 | +#define AKITA_MAX_ADDR 0x18 | ||
212 | +#define SPITZ_WM_ADDRL 0x1b | ||
213 | +#define SPITZ_WM_ADDRH 0x1a | ||
214 | |||
215 | -#define SPITZ_GPIO_WM 5 | ||
216 | +#define SPITZ_GPIO_WM 5 | ||
217 | |||
218 | static void spitz_wm8750_addr(void *opaque, int line, int level) | ||
219 | { | ||
220 | @@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level) | ||
39 | } | 221 | } |
40 | } | 222 | } |
41 | 223 | ||
42 | -static void *lqspi_request_mmio_ptr(void *opaque, hwaddr addr, unsigned *size, | 224 | -#define SPITZ_SCP_LED_GREEN 1 |
43 | - unsigned *offset) | 225 | -#define SPITZ_SCP_JK_B 2 |
44 | -{ | 226 | -#define SPITZ_SCP_CHRG_ON 3 |
45 | - XilinxQSPIPS *q = opaque; | 227 | -#define SPITZ_SCP_MUTE_L 4 |
46 | - hwaddr offset_within_the_region; | 228 | -#define SPITZ_SCP_MUTE_R 5 |
47 | - | 229 | -#define SPITZ_SCP_CF_POWER 6 |
48 | - if (!q->mmio_execution_enabled) { | 230 | -#define SPITZ_SCP_LED_ORANGE 7 |
49 | - return NULL; | 231 | -#define SPITZ_SCP_JK_A 8 |
50 | - } | 232 | -#define SPITZ_SCP_ADC_TEMP_ON 9 |
51 | - | 233 | -#define SPITZ_SCP2_IR_ON 1 |
52 | - offset_within_the_region = addr & ~(LQSPI_CACHE_SIZE - 1); | 234 | -#define SPITZ_SCP2_AKIN_PULLUP 2 |
53 | - lqspi_load_cache(opaque, offset_within_the_region); | 235 | -#define SPITZ_SCP2_BACKLIGHT_CONT 7 |
54 | - *size = LQSPI_CACHE_SIZE; | 236 | -#define SPITZ_SCP2_BACKLIGHT_ON 8 |
55 | - *offset = offset_within_the_region; | 237 | -#define SPITZ_SCP2_MIC_BIAS 9 |
56 | - return q->lqspi_buf; | 238 | +#define SPITZ_SCP_LED_GREEN 1 |
57 | -} | 239 | +#define SPITZ_SCP_JK_B 2 |
58 | - | 240 | +#define SPITZ_SCP_CHRG_ON 3 |
59 | static uint64_t | 241 | +#define SPITZ_SCP_MUTE_L 4 |
60 | lqspi_read(void *opaque, hwaddr addr, unsigned int size) | 242 | +#define SPITZ_SCP_MUTE_R 5 |
61 | { | 243 | +#define SPITZ_SCP_CF_POWER 6 |
62 | @@ -XXX,XX +XXX,XX @@ lqspi_read(void *opaque, hwaddr addr, unsigned int size) | 244 | +#define SPITZ_SCP_LED_ORANGE 7 |
63 | 245 | +#define SPITZ_SCP_JK_A 8 | |
64 | static const MemoryRegionOps lqspi_ops = { | 246 | +#define SPITZ_SCP_ADC_TEMP_ON 9 |
65 | .read = lqspi_read, | 247 | +#define SPITZ_SCP2_IR_ON 1 |
66 | - .request_ptr = lqspi_request_mmio_ptr, | 248 | +#define SPITZ_SCP2_AKIN_PULLUP 2 |
67 | .endianness = DEVICE_NATIVE_ENDIAN, | 249 | +#define SPITZ_SCP2_BACKLIGHT_CONT 7 |
68 | .valid = { | 250 | +#define SPITZ_SCP2_BACKLIGHT_ON 8 |
69 | .min_access_size = 1, | 251 | +#define SPITZ_SCP2_MIC_BIAS 9 |
70 | @@ -XXX,XX +XXX,XX @@ static void xilinx_qspips_realize(DeviceState *dev, Error **errp) | 252 | |
71 | sysbus_init_mmio(sbd, &s->mmlqspi); | 253 | static void spitz_scoop_gpio_setup(PXA2xxState *cpu, |
72 | 254 | DeviceState *scp0, DeviceState *scp1) | |
73 | q->lqspi_cached_addr = ~0ULL; | 255 | @@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu, |
74 | - | 256 | qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); |
75 | - /* mmio_execution breaks migration better aborting than having strange | ||
76 | - * bugs. | ||
77 | - */ | ||
78 | - if (q->mmio_execution_enabled) { | ||
79 | - error_setg(&q->migration_blocker, | ||
80 | - "enabling mmio_execution breaks migration"); | ||
81 | - migrate_add_blocker(q->migration_blocker, &error_fatal); | ||
82 | - } | ||
83 | } | 257 | } |
84 | 258 | ||
85 | static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp) | 259 | -#define SPITZ_GPIO_HSYNC 22 |
86 | @@ -XXX,XX +XXX,XX @@ static Property xilinx_zynqmp_qspips_properties[] = { | 260 | -#define SPITZ_GPIO_SD_DETECT 9 |
87 | DEFINE_PROP_END_OF_LIST(), | 261 | -#define SPITZ_GPIO_SD_WP 81 |
88 | }; | 262 | -#define SPITZ_GPIO_ON_RESET 89 |
89 | 263 | -#define SPITZ_GPIO_BAT_COVER 90 | |
90 | -static Property xilinx_qspips_properties[] = { | 264 | -#define SPITZ_GPIO_CF1_IRQ 105 |
91 | - /* We had to turn this off for 2.10 as it is not compatible with migration. | 265 | -#define SPITZ_GPIO_CF1_CD 94 |
92 | - * It can be enabled but will prevent the device to be migrated. | 266 | -#define SPITZ_GPIO_CF2_IRQ 106 |
93 | - * This will go aways when a fix will be released. | 267 | -#define SPITZ_GPIO_CF2_CD 93 |
94 | - */ | 268 | +#define SPITZ_GPIO_HSYNC 22 |
95 | - DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled, | 269 | +#define SPITZ_GPIO_SD_DETECT 9 |
96 | - false), | 270 | +#define SPITZ_GPIO_SD_WP 81 |
97 | - DEFINE_PROP_END_OF_LIST(), | 271 | +#define SPITZ_GPIO_ON_RESET 89 |
98 | -}; | 272 | +#define SPITZ_GPIO_BAT_COVER 90 |
99 | - | 273 | +#define SPITZ_GPIO_CF1_IRQ 105 |
100 | static Property xilinx_spips_properties[] = { | 274 | +#define SPITZ_GPIO_CF1_CD 94 |
101 | DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), | 275 | +#define SPITZ_GPIO_CF2_IRQ 106 |
102 | DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), | 276 | +#define SPITZ_GPIO_CF2_CD 93 |
103 | @@ -XXX,XX +XXX,XX @@ static void xilinx_qspips_class_init(ObjectClass *klass, void * data) | 277 | |
104 | XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass); | 278 | static int spitz_hsync; |
105 | 279 | ||
106 | dc->realize = xilinx_qspips_realize; | 280 | @@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) |
107 | - dc->props = xilinx_qspips_properties; | 281 | /* Board init. */ |
108 | xsc->reg_ops = &qspips_ops; | 282 | enum spitz_model_e { spitz, akita, borzoi, terrier }; |
109 | xsc->rx_fifo_size = RXFF_A_Q; | 283 | |
110 | xsc->tx_fifo_size = TXFF_A_Q; | 284 | -#define SPITZ_RAM 0x04000000 |
285 | -#define SPITZ_ROM 0x00800000 | ||
286 | +#define SPITZ_RAM 0x04000000 | ||
287 | +#define SPITZ_ROM 0x00800000 | ||
288 | |||
289 | static struct arm_boot_info spitz_binfo = { | ||
290 | .loader_start = PXA2XX_SDRAM_BASE, | ||
111 | -- | 291 | -- |
112 | 2.18.0 | 292 | 2.20.1 |
113 | 293 | ||
114 | 294 | diff view generated by jsdifflib |
1 | The mmio_interface device was a purely internal artifact | 1 | For the four Spitz-family machines (akita, borzoi, spitz, terrier) |
---|---|---|---|
2 | of the implementation of the memory subsystem's request_ptr | 2 | create a proper abstract class SpitzMachineClass which encapsulates |
3 | APIs. Now that we have removed those APIs, we can remove | 3 | the common behaviour, rather than having them all derive directly |
4 | the mmio_interface device too. | 4 | from TYPE_MACHINE: |
5 | * instead of each machine class setting mc->init to a wrapper | ||
6 | function which calls spitz_common_init() with parameters, | ||
7 | put that data in the SpitzMachineClass and make spitz_common_init | ||
8 | the SpitzMachineClass machine-init function | ||
9 | * move the settings of mc->block_default_type and | ||
10 | mc->ignore_memory_transaction_failures into the SpitzMachineClass | ||
11 | class init rather than repeating them in each machine's class init | ||
12 | |||
13 | (The motivation is that we're going to want to keep some state in | ||
14 | the SpitzMachineState so we can connect GPIOs between devices created | ||
15 | in one sub-function of the machine init to devices created in a | ||
16 | different sub-function.) | ||
5 | 17 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 19 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 20 | Message-id: 20200628142429.17111-3-peter.maydell@linaro.org |
9 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
10 | Message-id: 20180817114619.22354-4-peter.maydell@linaro.org | ||
11 | --- | 21 | --- |
12 | hw/misc/Makefile.objs | 1 - | 22 | hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++-------------------- |
13 | include/hw/misc/mmio_interface.h | 49 ----------- | 23 | 1 file changed, 55 insertions(+), 36 deletions(-) |
14 | hw/misc/mmio_interface.c | 135 ------------------------------- | 24 | |
15 | 3 files changed, 185 deletions(-) | 25 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
16 | delete mode 100644 include/hw/misc/mmio_interface.h | ||
17 | delete mode 100644 hw/misc/mmio_interface.c | ||
18 | |||
19 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
20 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/Makefile.objs | 27 | --- a/hw/arm/spitz.c |
22 | +++ b/hw/misc/Makefile.objs | 28 | +++ b/hw/arm/spitz.c |
23 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_PVPANIC) += pvpanic.o | ||
24 | obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o | ||
25 | obj-$(CONFIG_AUX) += auxbus.o | ||
26 | obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o | ||
27 | -obj-y += mmio_interface.o | ||
28 | obj-$(CONFIG_MSF2) += msf2-sysreg.o | ||
29 | diff --git a/include/hw/misc/mmio_interface.h b/include/hw/misc/mmio_interface.h | ||
30 | deleted file mode 100644 | ||
31 | index XXXXXXX..XXXXXXX | ||
32 | --- a/include/hw/misc/mmio_interface.h | ||
33 | +++ /dev/null | ||
34 | @@ -XXX,XX +XXX,XX @@ | 29 | @@ -XXX,XX +XXX,XX @@ |
35 | -/* | 30 | #include "exec/address-spaces.h" |
36 | - * mmio_interface.h | 31 | #include "cpu.h" |
37 | - * | 32 | |
38 | - * Copyright (C) 2017 : GreenSocs | 33 | +enum spitz_model_e { spitz, akita, borzoi, terrier }; |
39 | - * http://www.greensocs.com/ , email: info@greensocs.com | 34 | + |
40 | - * | 35 | +typedef struct { |
41 | - * Developed by : | 36 | + MachineClass parent; |
42 | - * Frederic Konrad <fred.konrad@greensocs.com> | 37 | + enum spitz_model_e model; |
43 | - * | 38 | + int arm_id; |
44 | - * This program is free software; you can redistribute it and/or modify | 39 | +} SpitzMachineClass; |
45 | - * it under the terms of the GNU General Public License as published by | 40 | + |
46 | - * the Free Software Foundation, either version 2 of the License, or | 41 | +typedef struct { |
47 | - * (at your option)any later version. | 42 | + MachineState parent; |
48 | - * | 43 | +} SpitzMachineState; |
49 | - * This program is distributed in the hope that it will be useful, | 44 | + |
50 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | 45 | +#define TYPE_SPITZ_MACHINE "spitz-common" |
51 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 46 | +#define SPITZ_MACHINE(obj) \ |
52 | - * GNU General Public License for more details. | 47 | + OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE) |
53 | - * | 48 | +#define SPITZ_MACHINE_GET_CLASS(obj) \ |
54 | - * You should have received a copy of the GNU General Public License along | 49 | + OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE) |
55 | - * with this program; if not, see <http://www.gnu.org/licenses/>. | 50 | +#define SPITZ_MACHINE_CLASS(klass) \ |
56 | - * | 51 | + OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE) |
57 | - */ | 52 | + |
53 | #undef REG_FMT | ||
54 | #define REG_FMT "0x%02lx" | ||
55 | |||
56 | @@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots) | ||
57 | } | ||
58 | |||
59 | /* Board init. */ | ||
60 | -enum spitz_model_e { spitz, akita, borzoi, terrier }; | ||
58 | - | 61 | - |
59 | -#ifndef MMIO_INTERFACE_H | 62 | #define SPITZ_RAM 0x04000000 |
60 | -#define MMIO_INTERFACE_H | 63 | #define SPITZ_ROM 0x00800000 |
61 | - | 64 | |
62 | -#include "exec/memory.h" | 65 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = { |
63 | - | 66 | .ram_size = 0x04000000, |
64 | -#define TYPE_MMIO_INTERFACE "mmio_interface" | 67 | }; |
65 | -#define MMIO_INTERFACE(obj) OBJECT_CHECK(MMIOInterface, (obj), \ | 68 | |
66 | - TYPE_MMIO_INTERFACE) | 69 | -static void spitz_common_init(MachineState *machine, |
67 | - | 70 | - enum spitz_model_e model, int arm_id) |
68 | -typedef struct MMIOInterface { | 71 | +static void spitz_common_init(MachineState *machine) |
69 | - DeviceState parent_obj; | 72 | { |
70 | - | 73 | + SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine); |
71 | - MemoryRegion *subregion; | 74 | + enum spitz_model_e model = smc->model; |
72 | - MemoryRegion ram_mem; | 75 | PXA2xxState *mpu; |
73 | - uint64_t start; | 76 | DeviceState *scp0, *scp1 = NULL; |
74 | - uint64_t end; | 77 | MemoryRegion *address_space_mem = get_system_memory(); |
75 | - bool ro; | 78 | @@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine, |
76 | - uint64_t id; | 79 | /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ |
77 | - void *host_ptr; | 80 | spitz_microdrive_attach(mpu, 0); |
78 | -} MMIOInterface; | 81 | |
79 | - | 82 | - spitz_binfo.board_id = arm_id; |
80 | -void mmio_interface_map(MMIOInterface *s); | 83 | + spitz_binfo.board_id = smc->arm_id; |
81 | -void mmio_interface_unmap(MMIOInterface *s); | 84 | arm_load_kernel(mpu->cpu, machine, &spitz_binfo); |
82 | - | 85 | sl_bootparam_write(SL_PXA_PARAM_BASE); |
83 | -#endif /* MMIO_INTERFACE_H */ | 86 | } |
84 | diff --git a/hw/misc/mmio_interface.c b/hw/misc/mmio_interface.c | 87 | |
85 | deleted file mode 100644 | 88 | -static void spitz_init(MachineState *machine) |
86 | index XXXXXXX..XXXXXXX | 89 | +static void spitz_common_class_init(ObjectClass *oc, void *data) |
87 | --- a/hw/misc/mmio_interface.c | 90 | { |
88 | +++ /dev/null | 91 | - spitz_common_init(machine, spitz, 0x2c9); |
89 | @@ -XXX,XX +XXX,XX @@ | 92 | + MachineClass *mc = MACHINE_CLASS(oc); |
90 | -/* | 93 | + |
91 | - * mmio_interface.c | 94 | + mc->block_default_type = IF_IDE; |
92 | - * | 95 | + mc->ignore_memory_transaction_failures = true; |
93 | - * Copyright (C) 2017 : GreenSocs | 96 | + mc->init = spitz_common_init; |
94 | - * http://www.greensocs.com/ , email: info@greensocs.com | 97 | } |
95 | - * | 98 | |
96 | - * Developed by : | 99 | -static void borzoi_init(MachineState *machine) |
97 | - * Frederic Konrad <fred.konrad@greensocs.com> | ||
98 | - * | ||
99 | - * This program is free software; you can redistribute it and/or modify | ||
100 | - * it under the terms of the GNU General Public License as published by | ||
101 | - * the Free Software Foundation, either version 2 of the License, or | ||
102 | - * (at your option)any later version. | ||
103 | - * | ||
104 | - * This program is distributed in the hope that it will be useful, | ||
105 | - * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
106 | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
107 | - * GNU General Public License for more details. | ||
108 | - * | ||
109 | - * You should have received a copy of the GNU General Public License along | ||
110 | - * with this program; if not, see <http://www.gnu.org/licenses/>. | ||
111 | - * | ||
112 | - */ | ||
113 | - | ||
114 | -#include "qemu/osdep.h" | ||
115 | -#include "qemu/log.h" | ||
116 | -#include "trace.h" | ||
117 | -#include "hw/qdev-properties.h" | ||
118 | -#include "hw/misc/mmio_interface.h" | ||
119 | -#include "qapi/error.h" | ||
120 | - | ||
121 | -#ifndef DEBUG_MMIO_INTERFACE | ||
122 | -#define DEBUG_MMIO_INTERFACE 0 | ||
123 | -#endif | ||
124 | - | ||
125 | -static uint64_t mmio_interface_counter; | ||
126 | - | ||
127 | -#define DPRINTF(fmt, ...) do { \ | ||
128 | - if (DEBUG_MMIO_INTERFACE) { \ | ||
129 | - qemu_log("mmio_interface: 0x%" PRIX64 ": " fmt, s->id, ## __VA_ARGS__);\ | ||
130 | - } \ | ||
131 | -} while (0) | ||
132 | - | ||
133 | -static void mmio_interface_init(Object *obj) | ||
134 | -{ | 100 | -{ |
135 | - MMIOInterface *s = MMIO_INTERFACE(obj); | 101 | - spitz_common_init(machine, borzoi, 0x33f); |
136 | - | ||
137 | - if (DEBUG_MMIO_INTERFACE) { | ||
138 | - s->id = mmio_interface_counter++; | ||
139 | - } | ||
140 | - | ||
141 | - DPRINTF("interface created\n"); | ||
142 | - s->host_ptr = 0; | ||
143 | - s->subregion = 0; | ||
144 | -} | 102 | -} |
145 | - | 103 | - |
146 | -static void mmio_interface_realize(DeviceState *dev, Error **errp) | 104 | -static void akita_init(MachineState *machine) |
147 | -{ | 105 | -{ |
148 | - MMIOInterface *s = MMIO_INTERFACE(dev); | 106 | - spitz_common_init(machine, akita, 0x2e8); |
149 | - | ||
150 | - DPRINTF("realize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" | ||
151 | - " %p\n", s->start, s->end, s->host_ptr); | ||
152 | - | ||
153 | - if (!s->host_ptr) { | ||
154 | - error_setg(errp, "host_ptr property must be set"); | ||
155 | - return; | ||
156 | - } | ||
157 | - | ||
158 | - if (!s->subregion) { | ||
159 | - error_setg(errp, "subregion property must be set"); | ||
160 | - return; | ||
161 | - } | ||
162 | - | ||
163 | - memory_region_init_ram_ptr(&s->ram_mem, OBJECT(s), "ram", | ||
164 | - s->end - s->start + 1, s->host_ptr); | ||
165 | - memory_region_set_readonly(&s->ram_mem, s->ro); | ||
166 | - memory_region_add_subregion(s->subregion, s->start, &s->ram_mem); | ||
167 | -} | 107 | -} |
168 | - | 108 | - |
169 | -static void mmio_interface_unrealize(DeviceState *dev, Error **errp) | 109 | -static void terrier_init(MachineState *machine) |
170 | -{ | 110 | -{ |
171 | - MMIOInterface *s = MMIO_INTERFACE(dev); | 111 | - spitz_common_init(machine, terrier, 0x33f); |
172 | - | ||
173 | - DPRINTF("unrealize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" | ||
174 | - " %p\n", s->start, s->end, s->host_ptr); | ||
175 | - memory_region_del_subregion(s->subregion, &s->ram_mem); | ||
176 | -} | 112 | -} |
177 | - | 113 | +static const TypeInfo spitz_common_info = { |
178 | -static void mmio_interface_finalize(Object *obj) | 114 | + .name = TYPE_SPITZ_MACHINE, |
179 | -{ | 115 | + .parent = TYPE_MACHINE, |
180 | - MMIOInterface *s = MMIO_INTERFACE(obj); | 116 | + .abstract = true, |
181 | - | 117 | + .instance_size = sizeof(SpitzMachineState), |
182 | - DPRINTF("finalize from 0x%" PRIX64 " to 0x%" PRIX64 " map host pointer" | 118 | + .class_size = sizeof(SpitzMachineClass), |
183 | - " %p\n", s->start, s->end, s->host_ptr); | 119 | + .class_init = spitz_common_class_init, |
184 | - object_unparent(OBJECT(&s->ram_mem)); | 120 | +}; |
185 | -} | 121 | |
186 | - | 122 | static void akitapda_class_init(ObjectClass *oc, void *data) |
187 | -static Property mmio_interface_properties[] = { | 123 | { |
188 | - DEFINE_PROP_UINT64("start", MMIOInterface, start, 0), | 124 | MachineClass *mc = MACHINE_CLASS(oc); |
189 | - DEFINE_PROP_UINT64("end", MMIOInterface, end, 0), | 125 | + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); |
190 | - DEFINE_PROP_PTR("host_ptr", MMIOInterface, host_ptr), | 126 | |
191 | - DEFINE_PROP_BOOL("ro", MMIOInterface, ro, false), | 127 | mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)"; |
192 | - DEFINE_PROP_MEMORY_REGION("subregion", MMIOInterface, subregion), | 128 | - mc->init = akita_init; |
193 | - DEFINE_PROP_END_OF_LIST(), | 129 | - mc->ignore_memory_transaction_failures = true; |
194 | -}; | 130 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); |
195 | - | 131 | + smc->model = akita; |
196 | -static void mmio_interface_class_init(ObjectClass *oc, void *data) | 132 | + smc->arm_id = 0x2e8; |
197 | -{ | 133 | } |
198 | - DeviceClass *dc = DEVICE_CLASS(oc); | 134 | |
199 | - | 135 | static const TypeInfo akitapda_type = { |
200 | - dc->realize = mmio_interface_realize; | 136 | .name = MACHINE_TYPE_NAME("akita"), |
201 | - dc->unrealize = mmio_interface_unrealize; | 137 | - .parent = TYPE_MACHINE, |
202 | - dc->props = mmio_interface_properties; | 138 | + .parent = TYPE_SPITZ_MACHINE, |
203 | - /* Reason: pointer property "host_ptr", and this device | 139 | .class_init = akitapda_class_init, |
204 | - * is an implementation detail of the memory subsystem, | 140 | }; |
205 | - * not intended to be created directly by the user. | 141 | |
206 | - */ | 142 | static void spitzpda_class_init(ObjectClass *oc, void *data) |
207 | - dc->user_creatable = false; | 143 | { |
208 | -} | 144 | MachineClass *mc = MACHINE_CLASS(oc); |
209 | - | 145 | + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); |
210 | -static const TypeInfo mmio_interface_info = { | 146 | |
211 | - .name = TYPE_MMIO_INTERFACE, | 147 | mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)"; |
212 | - .parent = TYPE_DEVICE, | 148 | - mc->init = spitz_init; |
213 | - .instance_size = sizeof(MMIOInterface), | 149 | - mc->block_default_type = IF_IDE; |
214 | - .instance_init = mmio_interface_init, | 150 | - mc->ignore_memory_transaction_failures = true; |
215 | - .instance_finalize = mmio_interface_finalize, | 151 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); |
216 | - .class_init = mmio_interface_class_init, | 152 | + smc->model = spitz; |
217 | -}; | 153 | + smc->arm_id = 0x2c9; |
218 | - | 154 | } |
219 | -static void mmio_interface_register_types(void) | 155 | |
220 | -{ | 156 | static const TypeInfo spitzpda_type = { |
221 | - type_register_static(&mmio_interface_info); | 157 | .name = MACHINE_TYPE_NAME("spitz"), |
222 | -} | 158 | - .parent = TYPE_MACHINE, |
223 | - | 159 | + .parent = TYPE_SPITZ_MACHINE, |
224 | -type_init(mmio_interface_register_types) | 160 | .class_init = spitzpda_class_init, |
161 | }; | ||
162 | |||
163 | static void borzoipda_class_init(ObjectClass *oc, void *data) | ||
164 | { | ||
165 | MachineClass *mc = MACHINE_CLASS(oc); | ||
166 | + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); | ||
167 | |||
168 | mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; | ||
169 | - mc->init = borzoi_init; | ||
170 | - mc->block_default_type = IF_IDE; | ||
171 | - mc->ignore_memory_transaction_failures = true; | ||
172 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0"); | ||
173 | + smc->model = borzoi; | ||
174 | + smc->arm_id = 0x33f; | ||
175 | } | ||
176 | |||
177 | static const TypeInfo borzoipda_type = { | ||
178 | .name = MACHINE_TYPE_NAME("borzoi"), | ||
179 | - .parent = TYPE_MACHINE, | ||
180 | + .parent = TYPE_SPITZ_MACHINE, | ||
181 | .class_init = borzoipda_class_init, | ||
182 | }; | ||
183 | |||
184 | static void terrierpda_class_init(ObjectClass *oc, void *data) | ||
185 | { | ||
186 | MachineClass *mc = MACHINE_CLASS(oc); | ||
187 | + SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc); | ||
188 | |||
189 | mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)"; | ||
190 | - mc->init = terrier_init; | ||
191 | - mc->block_default_type = IF_IDE; | ||
192 | - mc->ignore_memory_transaction_failures = true; | ||
193 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5"); | ||
194 | + smc->model = terrier; | ||
195 | + smc->arm_id = 0x33f; | ||
196 | } | ||
197 | |||
198 | static const TypeInfo terrierpda_type = { | ||
199 | .name = MACHINE_TYPE_NAME("terrier"), | ||
200 | - .parent = TYPE_MACHINE, | ||
201 | + .parent = TYPE_SPITZ_MACHINE, | ||
202 | .class_init = terrierpda_class_init, | ||
203 | }; | ||
204 | |||
205 | static void spitz_machine_init(void) | ||
206 | { | ||
207 | + type_register_static(&spitz_common_info); | ||
208 | type_register_static(&akitapda_type); | ||
209 | type_register_static(&spitzpda_type); | ||
210 | type_register_static(&borzoipda_type); | ||
225 | -- | 211 | -- |
226 | 2.18.0 | 212 | 2.20.1 |
227 | 213 | ||
228 | 214 | diff view generated by jsdifflib |
1 | ARMv7VE introduced the ERET instruction, which is necessary to | 1 | Keep pointers to the MPU and the SSI devices in SpitzMachineState. |
---|---|---|---|
2 | return from an exception taken to Hyp mode. Implement this. | 2 | We're going to want to make GPIO connections between some of the |
3 | In A32 encoding it is a completely new encoding; in T32 it | 3 | SSI devices and the SCPs, so we want to keep hold of a pointer to |
4 | is an adjustment of the behaviour of the existing | 4 | those; putting the MPU into the struct allows us to pass just |
5 | "SUBS PC, LR, #<imm8>" instruction. | 5 | one thing to spitz_ssp_attach() rather than two. |
6 | |||
7 | We have to retain the setting of the global "max1111" variable | ||
8 | for the moment as it is used in spitz_adc_temp_on(); later in | ||
9 | this series of commits we will be able to remove it. | ||
6 | 10 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
9 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 13 | Message-id: 20200628142429.17111-4-peter.maydell@linaro.org |
10 | Message-id: 20180814124254.5229-10-peter.maydell@linaro.org | ||
11 | --- | 14 | --- |
12 | target/arm/translate.c | 31 +++++++++++++++++++++++++++++-- | 15 | hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++---------------------- |
13 | 1 file changed, 29 insertions(+), 2 deletions(-) | 16 | 1 file changed, 28 insertions(+), 22 deletions(-) |
14 | 17 | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 18 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
16 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 20 | --- a/hw/arm/spitz.c |
18 | +++ b/target/arm/translate.c | 21 | +++ b/hw/arm/spitz.c |
19 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
20 | tcg_temp_free_i32(tmp2); | 23 | |
21 | store_reg(s, rd, tmp); | 24 | typedef struct { |
22 | break; | 25 | MachineState parent; |
23 | + case 0x6: /* ERET */ | 26 | + PXA2xxState *mpu; |
24 | + if (op1 != 3) { | 27 | + DeviceState *mux; |
25 | + goto illegal_op; | 28 | + DeviceState *lcdtg; |
26 | + } | 29 | + DeviceState *ads7846; |
27 | + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { | 30 | + DeviceState *max1111; |
28 | + goto illegal_op; | 31 | } SpitzMachineState; |
29 | + } | 32 | |
30 | + if ((insn & 0x000fff0f) != 0x0000000e) { | 33 | #define TYPE_SPITZ_MACHINE "spitz-common" |
31 | + /* UNPREDICTABLE; we choose to UNDEF */ | 34 | @@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp) |
32 | + goto illegal_op; | 35 | s->bus[2] = ssi_create_bus(dev, "ssi2"); |
33 | + } | 36 | } |
34 | + | 37 | |
35 | + if (s->current_el == 2) { | 38 | -static void spitz_ssp_attach(PXA2xxState *cpu) |
36 | + tmp = load_cpu_field(elr_el[2]); | 39 | +static void spitz_ssp_attach(SpitzMachineState *sms) |
37 | + } else { | 40 | { |
38 | + tmp = load_reg(s, 14); | 41 | - DeviceState *mux; |
39 | + } | 42 | - DeviceState *dev; |
40 | + gen_exception_return(s, tmp); | 43 | void *bus; |
41 | + break; | 44 | |
42 | case 7: | 45 | - mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); |
43 | { | 46 | + sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); |
44 | int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); | 47 | |
45 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 48 | - bus = qdev_get_child_bus(mux, "ssi0"); |
46 | if (rn != 14 || rd != 15) { | 49 | - ssi_create_slave(bus, "spitz-lcdtg"); |
47 | goto illegal_op; | 50 | + bus = qdev_get_child_bus(sms->mux, "ssi0"); |
48 | } | 51 | + sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg"); |
49 | - tmp = load_reg(s, rn); | 52 | |
50 | - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); | 53 | - bus = qdev_get_child_bus(mux, "ssi1"); |
51 | + if (s->current_el == 2) { | 54 | - dev = ssi_create_slave(bus, "ads7846"); |
52 | + /* ERET from Hyp uses ELR_Hyp, not LR */ | 55 | - qdev_connect_gpio_out(dev, 0, |
53 | + if (insn & 0xff) { | 56 | - qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT)); |
54 | + goto illegal_op; | 57 | + bus = qdev_get_child_bus(sms->mux, "ssi1"); |
55 | + } | 58 | + sms->ads7846 = ssi_create_slave(bus, "ads7846"); |
56 | + tmp = load_cpu_field(elr_el[2]); | 59 | + qdev_connect_gpio_out(sms->ads7846, 0, |
57 | + } else { | 60 | + qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); |
58 | + tmp = load_reg(s, rn); | 61 | |
59 | + tcg_gen_subi_i32(tmp, tmp, insn & 0xff); | 62 | - bus = qdev_get_child_bus(mux, "ssi2"); |
60 | + } | 63 | - max1111 = ssi_create_slave(bus, "max1111"); |
61 | gen_exception_return(s, tmp); | 64 | - max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
62 | break; | 65 | - max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); |
63 | case 6: /* MRS */ | 66 | - max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); |
67 | + bus = qdev_get_child_bus(sms->mux, "ssi2"); | ||
68 | + sms->max1111 = ssi_create_slave(bus, "max1111"); | ||
69 | + max1111 = sms->max1111; | ||
70 | + max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); | ||
71 | + max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0); | ||
72 | + max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); | ||
73 | |||
74 | - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS, | ||
75 | - qdev_get_gpio_in(mux, 0)); | ||
76 | - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS, | ||
77 | - qdev_get_gpio_in(mux, 1)); | ||
78 | - qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS, | ||
79 | - qdev_get_gpio_in(mux, 2)); | ||
80 | + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS, | ||
81 | + qdev_get_gpio_in(sms->mux, 0)); | ||
82 | + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS, | ||
83 | + qdev_get_gpio_in(sms->mux, 1)); | ||
84 | + qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS, | ||
85 | + qdev_get_gpio_in(sms->mux, 2)); | ||
86 | } | ||
87 | |||
88 | /* CF Microdrive */ | ||
89 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = { | ||
90 | static void spitz_common_init(MachineState *machine) | ||
91 | { | ||
92 | SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine); | ||
93 | + SpitzMachineState *sms = SPITZ_MACHINE(machine); | ||
94 | enum spitz_model_e model = smc->model; | ||
95 | PXA2xxState *mpu; | ||
96 | DeviceState *scp0, *scp1 = NULL; | ||
97 | @@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine) | ||
98 | /* Setup CPU & memory */ | ||
99 | mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, | ||
100 | machine->cpu_type); | ||
101 | + sms->mpu = mpu; | ||
102 | |||
103 | sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); | ||
104 | |||
105 | @@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine) | ||
106 | /* Setup peripherals */ | ||
107 | spitz_keyboard_register(mpu); | ||
108 | |||
109 | - spitz_ssp_attach(mpu); | ||
110 | + spitz_ssp_attach(sms); | ||
111 | |||
112 | scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); | ||
113 | if (model != akita) { | ||
64 | -- | 114 | -- |
65 | 2.18.0 | 115 | 2.20.1 |
66 | 116 | ||
67 | 117 | diff view generated by jsdifflib |
1 | The AArch32 HSR is the equivalent of AArch64 ESR_EL2; | 1 | Keep pointers to scp0, scp1 in SpitzMachineState, and just pass |
---|---|---|---|
2 | we can implement it by marking our existing ESR_EL2 regdef | 2 | that to spitz_scoop_gpio_setup(). |
3 | as STATE_BOTH. It also needs to be "RES0 from EL3 if | 3 | |
4 | EL2 not implemented", so add the missing stanza to | 4 | (We'll want to use some of the other fields in SpitzMachineState |
5 | el3_no_el2_cp_reginfo. | 5 | in that function in the next commit.) |
6 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
9 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 9 | Message-id: 20200628142429.17111-5-peter.maydell@linaro.org |
10 | Message-id: 20180814124254.5229-8-peter.maydell@linaro.org | ||
11 | --- | 10 | --- |
12 | target/arm/helper.c | 6 +++++- | 11 | hw/arm/spitz.c | 34 +++++++++++++++++++--------------- |
13 | 1 file changed, 5 insertions(+), 1 deletion(-) | 12 | 1 file changed, 19 insertions(+), 15 deletions(-) |
14 | 13 | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 16 | --- a/hw/arm/spitz.c |
18 | +++ b/target/arm/helper.c | 17 | +++ b/hw/arm/spitz.c |
19 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | 18 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
20 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, | 19 | DeviceState *lcdtg; |
21 | .access = PL2_RW, | 20 | DeviceState *ads7846; |
22 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | 21 | DeviceState *max1111; |
23 | + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, | 22 | + DeviceState *scp0; |
24 | + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | 23 | + DeviceState *scp1; |
25 | + .access = PL2_RW, | 24 | } SpitzMachineState; |
26 | + .type = ARM_CP_CONST, .resetvalue = 0 }, | 25 | |
27 | { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, | 26 | #define TYPE_SPITZ_MACHINE "spitz-common" |
28 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, | 27 | @@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level) |
29 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 28 | #define SPITZ_SCP2_BACKLIGHT_ON 8 |
30 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 29 | #define SPITZ_SCP2_MIC_BIAS 9 |
31 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, | 30 | |
32 | .access = PL2_RW, | 31 | -static void spitz_scoop_gpio_setup(PXA2xxState *cpu, |
33 | .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, | 32 | - DeviceState *scp0, DeviceState *scp1) |
34 | - { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, | 33 | +static void spitz_scoop_gpio_setup(SpitzMachineState *sms) |
35 | + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, | 34 | { |
36 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | 35 | - qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8); |
37 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | 36 | + qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8); |
38 | { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | 37 | |
38 | - qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); | ||
39 | - qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]); | ||
40 | - qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); | ||
41 | - qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); | ||
42 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); | ||
43 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]); | ||
44 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); | ||
45 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); | ||
46 | |||
47 | - if (scp1) { | ||
48 | - qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]); | ||
49 | - qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]); | ||
50 | + if (sms->scp1) { | ||
51 | + qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, | ||
52 | + outsignals[4]); | ||
53 | + qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, | ||
54 | + outsignals[5]); | ||
55 | } | ||
56 | |||
57 | - qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); | ||
58 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); | ||
59 | } | ||
60 | |||
61 | #define SPITZ_GPIO_HSYNC 22 | ||
62 | @@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine) | ||
63 | SpitzMachineState *sms = SPITZ_MACHINE(machine); | ||
64 | enum spitz_model_e model = smc->model; | ||
65 | PXA2xxState *mpu; | ||
66 | - DeviceState *scp0, *scp1 = NULL; | ||
67 | MemoryRegion *address_space_mem = get_system_memory(); | ||
68 | MemoryRegion *rom = g_new(MemoryRegion, 1); | ||
69 | |||
70 | @@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine) | ||
71 | |||
72 | spitz_ssp_attach(sms); | ||
73 | |||
74 | - scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); | ||
75 | + sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL); | ||
76 | if (model != akita) { | ||
77 | - scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); | ||
78 | + sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL); | ||
79 | + } else { | ||
80 | + sms->scp1 = NULL; | ||
81 | } | ||
82 | |||
83 | - spitz_scoop_gpio_setup(mpu, scp0, scp1); | ||
84 | + spitz_scoop_gpio_setup(sms); | ||
85 | |||
86 | spitz_gpio_setup(mpu, (model == akita) ? 1 : 2); | ||
87 | |||
39 | -- | 88 | -- |
40 | 2.18.0 | 89 | 2.20.1 |
41 | 90 | ||
42 | 91 | diff view generated by jsdifflib |
1 | The MSR (banked) and MRS (banked) instructions allow accesses to ELR_Hyp | 1 | Currently the Spitz board uses a nasty hack for the GPIO lines |
---|---|---|---|
2 | from either Monitor or Hyp mode. Our translate time check | 2 | that pass "bit5" and "power" information to the LCD controller: |
3 | was overly strict and only permitted access from Monitor mode. | 3 | the lcdtg realize function sets a global variable to point to |
4 | the instance it just realized, and then the functions spitz_bl_power() | ||
5 | and spitz_bl_bit5() use that to find the device they are changing | ||
6 | the internal state of. There is a comment reading: | ||
7 | FIXME: Implement GPIO properly and remove this hack. | ||
8 | which was added in 2009. | ||
4 | 9 | ||
5 | The runtime check we do in msr_mrs_banked_exc_checks() had the | 10 | Implement GPIO properly and remove this hack. |
6 | correct code in it, but never got there because of the earlier | ||
7 | "currmode == tgtmode" check. Special case ELR_Hyp. | ||
8 | 11 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
11 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 14 | Message-id: 20200628142429.17111-6-peter.maydell@linaro.org |
12 | Message-id: 20180814124254.5229-9-peter.maydell@linaro.org | ||
13 | --- | 15 | --- |
14 | target/arm/op_helper.c | 22 +++++++++++----------- | 16 | hw/arm/spitz.c | 28 ++++++++++++---------------- |
15 | target/arm/translate.c | 10 +++++++--- | 17 | 1 file changed, 12 insertions(+), 16 deletions(-) |
16 | 2 files changed, 18 insertions(+), 14 deletions(-) | ||
17 | 18 | ||
18 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | 19 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
19 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/op_helper.c | 21 | --- a/hw/arm/spitz.c |
21 | +++ b/target/arm/op_helper.c | 22 | +++ b/hw/arm/spitz.c |
22 | @@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, | 23 | @@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s) |
23 | */ | 24 | zaurus_printf("LCD Backlight now off\n"); |
24 | int curmode = env->uncached_cpsr & CPSR_M; | 25 | } |
25 | 26 | ||
26 | + if (regno == 17) { | 27 | -/* FIXME: Implement GPIO properly and remove this hack. */ |
27 | + /* ELR_Hyp: a special case because access from tgtmode is OK */ | 28 | -static SpitzLCDTG *spitz_lcdtg; |
28 | + if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { | 29 | - |
29 | + goto undef; | 30 | static inline void spitz_bl_bit5(void *opaque, int line, int level) |
30 | + } | 31 | { |
31 | + return; | 32 | - SpitzLCDTG *s = spitz_lcdtg; |
32 | + } | 33 | + SpitzLCDTG *s = opaque; |
34 | int prev = s->bl_intensity; | ||
35 | |||
36 | if (level) | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level) | ||
38 | |||
39 | static inline void spitz_bl_power(void *opaque, int line, int level) | ||
40 | { | ||
41 | - SpitzLCDTG *s = spitz_lcdtg; | ||
42 | + SpitzLCDTG *s = opaque; | ||
43 | s->bl_power = !!level; | ||
44 | spitz_bl_update(s); | ||
45 | } | ||
46 | @@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) | ||
47 | return 0; | ||
48 | } | ||
49 | |||
50 | -static void spitz_lcdtg_realize(SSISlave *dev, Error **errp) | ||
51 | +static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) | ||
52 | { | ||
53 | - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); | ||
54 | + SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi); | ||
55 | + DeviceState *dev = DEVICE(s); | ||
56 | |||
57 | - spitz_lcdtg = s; | ||
58 | s->bl_power = 0; | ||
59 | s->bl_intensity = 0x20; | ||
33 | + | 60 | + |
34 | if (curmode == tgtmode) { | 61 | + qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1); |
35 | goto undef; | 62 | + qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1); |
63 | } | ||
64 | |||
65 | /* SSP devices */ | ||
66 | @@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level) | ||
67 | case 3: | ||
68 | zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); | ||
69 | break; | ||
70 | - case 4: | ||
71 | - spitz_bl_bit5(opaque, line, level); | ||
72 | - break; | ||
73 | - case 5: | ||
74 | - spitz_bl_power(opaque, line, level); | ||
75 | - break; | ||
76 | case 6: | ||
77 | spitz_adc_temp_on(opaque, line, level); | ||
78 | break; | ||
79 | + default: | ||
80 | + g_assert_not_reached(); | ||
36 | } | 81 | } |
37 | @@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, | 82 | } |
83 | |||
84 | @@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms) | ||
85 | |||
86 | if (sms->scp1) { | ||
87 | qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, | ||
88 | - outsignals[4]); | ||
89 | + qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0)); | ||
90 | qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, | ||
91 | - outsignals[5]); | ||
92 | + qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0)); | ||
38 | } | 93 | } |
39 | 94 | ||
40 | if (tgtmode == ARM_CPU_MODE_HYP) { | 95 | qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); |
41 | - switch (regno) { | ||
42 | - case 17: /* ELR_Hyp */ | ||
43 | - if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { | ||
44 | - goto undef; | ||
45 | - } | ||
46 | - break; | ||
47 | - default: | ||
48 | - if (curmode != ARM_CPU_MODE_MON) { | ||
49 | - goto undef; | ||
50 | - } | ||
51 | - break; | ||
52 | + /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */ | ||
53 | + if (curmode != ARM_CPU_MODE_MON) { | ||
54 | + goto undef; | ||
55 | } | ||
56 | } | ||
57 | |||
58 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate.c | ||
61 | +++ b/target/arm/translate.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
63 | } | ||
64 | break; | ||
65 | case ARM_CPU_MODE_HYP: | ||
66 | - /* Note that we can forbid accesses from EL2 here because they | ||
67 | - * must be from Hyp mode itself | ||
68 | + /* | ||
69 | + * SPSR_hyp and r13_hyp can only be accessed from Monitor mode | ||
70 | + * (and so we can forbid accesses from EL2 or below). elr_hyp | ||
71 | + * can be accessed also from Hyp mode, so forbid accesses from | ||
72 | + * EL0 or EL1. | ||
73 | */ | ||
74 | - if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 3) { | ||
75 | + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 || | ||
76 | + (s->current_el < 3 && *regno != 17)) { | ||
77 | goto undef; | ||
78 | } | ||
79 | break; | ||
80 | -- | 96 | -- |
81 | 2.18.0 | 97 | 2.20.1 |
82 | 98 | ||
83 | 99 | diff view generated by jsdifflib |
1 | Currently our PL080/PL081 model uses a combination of the CPU's | 1 | Add some QOM properties to the max111x ADC device to allow the |
---|---|---|---|
2 | address space (via cpu_physical_memory_{read,write}()) and the | 2 | initial values to be configured. Currently this is done by |
3 | system address space for performing DMA accesses. | 3 | board code calling max111x_set_input() after it creates the |
4 | device, which doesn't work on system reset. | ||
4 | 5 | ||
5 | For the PL081s in the MPS FPGA images, their DMA accesses | 6 | This requires us to implement a reset method for this device, |
6 | must go via Master Security Controllers. Switch the | 7 | so while we're doing that make sure we reset the other parts |
7 | PL080/PL081 model to take a MemoryRegion property which | 8 | of the device state. |
8 | defines its downstream for making DMA accesses. | ||
9 | |||
10 | Since the PL08x are only used in two board models, we | ||
11 | make provision of the 'downstream' link mandatory and convert | ||
12 | both users at once, rather than having it be optional with | ||
13 | a default to the system address space. | ||
14 | 9 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
12 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
13 | Message-id: 20200628142429.17111-7-peter.maydell@linaro.org | ||
17 | --- | 14 | --- |
18 | include/hw/dma/pl080.h | 5 +++++ | 15 | hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++--------- |
19 | hw/arm/realview.c | 8 +++++++- | 16 | 1 file changed, 47 insertions(+), 10 deletions(-) |
20 | hw/arm/versatilepb.c | 9 ++++++++- | ||
21 | hw/dma/pl080.c | 35 +++++++++++++++++++++++++++++------ | ||
22 | 4 files changed, 49 insertions(+), 8 deletions(-) | ||
23 | 17 | ||
24 | diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h | 18 | diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c |
25 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/hw/dma/pl080.h | 20 | --- a/hw/misc/max111x.c |
27 | +++ b/include/hw/dma/pl080.h | 21 | +++ b/hw/misc/max111x.c |
28 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
29 | * + sysbus IRQ 1: DMACINTERR error interrupt request | 23 | #include "hw/ssi/ssi.h" |
30 | * + sysbus IRQ 2: DMACINTTC count interrupt request | 24 | #include "migration/vmstate.h" |
31 | * + sysbus MMIO region 0: MemoryRegion for the device's registers | 25 | #include "qemu/module.h" |
32 | + * + QOM property "downstream": MemoryRegion defining where DMA | 26 | +#include "hw/qdev-properties.h" |
33 | + * bus master transactions are made | 27 | |
34 | */ | 28 | typedef struct { |
35 | 29 | SSISlave parent_obj; | |
36 | #ifndef HW_DMA_PL080_H | 30 | |
37 | @@ -XXX,XX +XXX,XX @@ typedef struct PL080State { | 31 | qemu_irq interrupt; |
38 | qemu_irq irq; | 32 | + /* Values of inputs at system reset (settable by QOM property) */ |
39 | qemu_irq interr; | 33 | + uint8_t reset_input[8]; |
40 | qemu_irq inttc; | ||
41 | + | 34 | + |
42 | + MemoryRegion *downstream; | 35 | uint8_t tb1, rb2, rb3; |
43 | + AddressSpace downstream_as; | 36 | int cycle; |
44 | } PL080State; | 37 | |
45 | 38 | @@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs) | |
46 | #endif | 39 | qdev_init_gpio_out(dev, &s->interrupt, 1); |
47 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | 40 | |
48 | index XXXXXXX..XXXXXXX 100644 | 41 | s->inputs = inputs; |
49 | --- a/hw/arm/realview.c | 42 | - /* TODO: add a user interface for setting these */ |
50 | +++ b/hw/arm/realview.c | 43 | - s->input[0] = 0xf0; |
51 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | 44 | - s->input[1] = 0xe0; |
52 | pl011_create(0x1000c000, pic[15], serial_hd(3)); | 45 | - s->input[2] = 0xd0; |
53 | 46 | - s->input[3] = 0xc0; | |
54 | /* DMA controller is optional, apparently. */ | 47 | - s->input[4] = 0xb0; |
55 | - sysbus_create_simple("pl081", 0x10030000, pic[24]); | 48 | - s->input[5] = 0xa0; |
56 | + dev = qdev_create(NULL, "pl081"); | 49 | - s->input[6] = 0x90; |
57 | + object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", | 50 | - s->input[7] = 0x80; |
58 | + &error_fatal); | 51 | - s->com = 0; |
59 | + qdev_init_nofail(dev); | 52 | |
60 | + busdev = SYS_BUS_DEVICE(dev); | 53 | vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY, |
61 | + sysbus_mmio_map(busdev, 0, 0x10030000); | 54 | &vmstate_max111x, s); |
62 | + sysbus_connect_irq(busdev, 0, pic[24]); | 55 | @@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value) |
63 | 56 | s->input[line] = value; | |
64 | sysbus_create_simple("sp804", 0x10011000, pic[4]); | 57 | } |
65 | sysbus_create_simple("sp804", 0x10012000, pic[5]); | 58 | |
66 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | 59 | +static void max111x_reset(DeviceState *dev) |
67 | index XXXXXXX..XXXXXXX 100644 | 60 | +{ |
68 | --- a/hw/arm/versatilepb.c | 61 | + MAX111xState *s = MAX_111X(dev); |
69 | +++ b/hw/arm/versatilepb.c | 62 | + int i; |
70 | @@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id) | ||
71 | pl011_create(0x101f3000, pic[14], serial_hd(2)); | ||
72 | pl011_create(0x10009000, sic[6], serial_hd(3)); | ||
73 | |||
74 | - sysbus_create_simple("pl080", 0x10130000, pic[17]); | ||
75 | + dev = qdev_create(NULL, "pl080"); | ||
76 | + object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream", | ||
77 | + &error_fatal); | ||
78 | + qdev_init_nofail(dev); | ||
79 | + busdev = SYS_BUS_DEVICE(dev); | ||
80 | + sysbus_mmio_map(busdev, 0, 0x10130000); | ||
81 | + sysbus_connect_irq(busdev, 0, pic[17]); | ||
82 | + | 63 | + |
83 | sysbus_create_simple("sp804", 0x101e2000, pic[4]); | 64 | + for (i = 0; i < s->inputs; i++) { |
84 | sysbus_create_simple("sp804", 0x101e3000, pic[5]); | 65 | + s->input[i] = s->reset_input[i]; |
85 | |||
86 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/dma/pl080.c | ||
89 | +++ b/hw/dma/pl080.c | ||
90 | @@ -XXX,XX +XXX,XX @@ | ||
91 | #include "exec/address-spaces.h" | ||
92 | #include "qemu/log.h" | ||
93 | #include "hw/dma/pl080.h" | ||
94 | +#include "qapi/error.h" | ||
95 | |||
96 | #define PL080_CONF_E 0x1 | ||
97 | #define PL080_CONF_M1 0x2 | ||
98 | @@ -XXX,XX +XXX,XX @@ again: | ||
99 | swidth = 1 << ((ch->ctrl >> 18) & 7); | ||
100 | dwidth = 1 << ((ch->ctrl >> 21) & 7); | ||
101 | for (n = 0; n < dwidth; n+= swidth) { | ||
102 | - cpu_physical_memory_read(ch->src, buff + n, swidth); | ||
103 | + address_space_read(&s->downstream_as, ch->src, | ||
104 | + MEMTXATTRS_UNSPECIFIED, buff + n, swidth); | ||
105 | if (ch->ctrl & PL080_CCTRL_SI) | ||
106 | ch->src += swidth; | ||
107 | } | ||
108 | xsize = (dwidth < swidth) ? swidth : dwidth; | ||
109 | /* ??? This may pad the value incorrectly for dwidth < 32. */ | ||
110 | for (n = 0; n < xsize; n += dwidth) { | ||
111 | - cpu_physical_memory_write(ch->dest + n, buff + n, dwidth); | ||
112 | + address_space_write(&s->downstream_as, ch->dest + n, | ||
113 | + MEMTXATTRS_UNSPECIFIED, buff + n, dwidth); | ||
114 | if (ch->ctrl & PL080_CCTRL_DI) | ||
115 | ch->dest += swidth; | ||
116 | } | ||
117 | @@ -XXX,XX +XXX,XX @@ again: | ||
118 | if (size == 0) { | ||
119 | /* Transfer complete. */ | ||
120 | if (ch->lli) { | ||
121 | - ch->src = address_space_ldl_le(&address_space_memory, | ||
122 | + ch->src = address_space_ldl_le(&s->downstream_as, | ||
123 | ch->lli, | ||
124 | MEMTXATTRS_UNSPECIFIED, | ||
125 | NULL); | ||
126 | - ch->dest = address_space_ldl_le(&address_space_memory, | ||
127 | + ch->dest = address_space_ldl_le(&s->downstream_as, | ||
128 | ch->lli + 4, | ||
129 | MEMTXATTRS_UNSPECIFIED, | ||
130 | NULL); | ||
131 | - ch->ctrl = address_space_ldl_le(&address_space_memory, | ||
132 | + ch->ctrl = address_space_ldl_le(&s->downstream_as, | ||
133 | ch->lli + 12, | ||
134 | MEMTXATTRS_UNSPECIFIED, | ||
135 | NULL); | ||
136 | - ch->lli = address_space_ldl_le(&address_space_memory, | ||
137 | + ch->lli = address_space_ldl_le(&s->downstream_as, | ||
138 | ch->lli + 8, | ||
139 | MEMTXATTRS_UNSPECIFIED, | ||
140 | NULL); | ||
141 | @@ -XXX,XX +XXX,XX @@ static void pl080_init(Object *obj) | ||
142 | s->nchannels = 8; | ||
143 | } | ||
144 | |||
145 | +static void pl080_realize(DeviceState *dev, Error **errp) | ||
146 | +{ | ||
147 | + PL080State *s = PL080(dev); | ||
148 | + | ||
149 | + if (!s->downstream) { | ||
150 | + error_setg(errp, "PL080 'downstream' link not set"); | ||
151 | + return; | ||
152 | + } | 66 | + } |
153 | + | 67 | + s->com = 0; |
154 | + address_space_init(&s->downstream_as, s->downstream, "pl080-downstream"); | 68 | + s->tb1 = 0; |
69 | + s->rb2 = 0; | ||
70 | + s->rb3 = 0; | ||
71 | + s->cycle = 0; | ||
155 | +} | 72 | +} |
156 | + | 73 | + |
157 | static void pl081_init(Object *obj) | 74 | +static Property max1110_properties[] = { |
158 | { | 75 | + /* Reset values for ADC inputs */ |
159 | PL080State *s = PL080(obj); | 76 | + DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), |
160 | @@ -XXX,XX +XXX,XX @@ static void pl081_init(Object *obj) | 77 | + DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), |
161 | s->nchannels = 2; | 78 | + DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), |
162 | } | 79 | + DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), |
163 | |||
164 | +static Property pl080_properties[] = { | ||
165 | + DEFINE_PROP_LINK("downstream", PL080State, downstream, | ||
166 | + TYPE_MEMORY_REGION, MemoryRegion *), | ||
167 | + DEFINE_PROP_END_OF_LIST(), | 80 | + DEFINE_PROP_END_OF_LIST(), |
168 | +}; | 81 | +}; |
169 | + | 82 | + |
170 | static void pl080_class_init(ObjectClass *oc, void *data) | 83 | +static Property max1111_properties[] = { |
84 | + /* Reset values for ADC inputs */ | ||
85 | + DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0), | ||
86 | + DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0), | ||
87 | + DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0), | ||
88 | + DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0), | ||
89 | + DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0), | ||
90 | + DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0), | ||
91 | + DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90), | ||
92 | + DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80), | ||
93 | + DEFINE_PROP_END_OF_LIST(), | ||
94 | +}; | ||
95 | + | ||
96 | static void max111x_class_init(ObjectClass *klass, void *data) | ||
171 | { | 97 | { |
172 | DeviceClass *dc = DEVICE_CLASS(oc); | 98 | SSISlaveClass *k = SSI_SLAVE_CLASS(klass); |
173 | 99 | + DeviceClass *dc = DEVICE_CLASS(klass); | |
174 | dc->vmsd = &vmstate_pl080; | 100 | |
175 | + dc->realize = pl080_realize; | 101 | k->transfer = max111x_transfer; |
176 | + dc->props = pl080_properties; | 102 | + dc->reset = max111x_reset; |
177 | } | 103 | } |
178 | 104 | ||
179 | static const TypeInfo pl080_info = { | 105 | static const TypeInfo max111x_info = { |
106 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = { | ||
107 | static void max1110_class_init(ObjectClass *klass, void *data) | ||
108 | { | ||
109 | SSISlaveClass *k = SSI_SLAVE_CLASS(klass); | ||
110 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
111 | |||
112 | k->realize = max1110_realize; | ||
113 | + device_class_set_props(dc, max1110_properties); | ||
114 | } | ||
115 | |||
116 | static const TypeInfo max1110_info = { | ||
117 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = { | ||
118 | static void max1111_class_init(ObjectClass *klass, void *data) | ||
119 | { | ||
120 | SSISlaveClass *k = SSI_SLAVE_CLASS(klass); | ||
121 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
122 | |||
123 | k->realize = max1111_realize; | ||
124 | + device_class_set_props(dc, max1111_properties); | ||
125 | } | ||
126 | |||
127 | static const TypeInfo max1111_info = { | ||
180 | -- | 128 | -- |
181 | 2.18.0 | 129 | 2.20.1 |
182 | 130 | ||
183 | 131 | diff view generated by jsdifflib |
1 | Implement the AArch32 HVBAR register; we can do this just by | 1 | The max111x is a proper qdev device; we can use dc->vmsd rather than |
---|---|---|---|
2 | making the existing VBAR_EL2 regdefs be STATE_BOTH. | 2 | directly calling vmstate_register(). |
3 | |||
4 | It's possible that this is a migration compat break, but the only | ||
5 | boards that use this device are the spitz-family ('akita', 'borzoi', | ||
6 | 'spitz', 'terrier'). | ||
3 | 7 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Message-id: 20180814124254.5229-5-peter.maydell@linaro.org | 11 | Message-id: 20200628142429.17111-8-peter.maydell@linaro.org |
8 | --- | 12 | --- |
9 | target/arm/helper.c | 4 ++-- | 13 | hw/misc/max111x.c | 3 +-- |
10 | 1 file changed, 2 insertions(+), 2 deletions(-) | 14 | 1 file changed, 1 insertion(+), 2 deletions(-) |
11 | 15 | ||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.c | 18 | --- a/hw/misc/max111x.c |
15 | +++ b/target/arm/helper.c | 19 | +++ b/hw/misc/max111x.c |
16 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | 20 | @@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs) |
17 | 21 | ||
18 | /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ | 22 | s->inputs = inputs; |
19 | static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | 23 | |
20 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, | 24 | - vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY, |
21 | + { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, | 25 | - &vmstate_max111x, s); |
22 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | 26 | return 0; |
23 | .access = PL2_RW, | 27 | } |
24 | .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, | 28 | |
25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 29 | @@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data) |
26 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, | 30 | |
27 | .access = PL2_RW, | 31 | k->transfer = max111x_transfer; |
28 | .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, | 32 | dc->reset = max111x_reset; |
29 | - { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64, | 33 | + dc->vmsd = &vmstate_max111x; |
30 | + { .name = "VBAR_EL2", .state = ARM_CP_STATE_BOTH, | 34 | } |
31 | .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, | 35 | |
32 | .access = PL2_RW, .writefn = vbar_write, | 36 | static const TypeInfo max111x_info = { |
33 | .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]), | ||
34 | -- | 37 | -- |
35 | 2.18.0 | 38 | 2.20.1 |
36 | 39 | ||
37 | 40 | diff view generated by jsdifflib |
1 | The PL080/PL081 model is missing a reset function; implement it. | 1 | Add an ssi_realize_and_unref(), for the benefit of callers |
---|---|---|---|
2 | who want to be able to create an SSI device, set QOM properties | ||
3 | on it, and then do the realize-and-unref afterwards. | ||
4 | |||
5 | The API works on the same principle as the recently added | ||
6 | qdev_realize_and_undef(), sysbus_realize_and_undef(), etc. | ||
2 | 7 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
11 | Message-id: 20200628142429.17111-9-peter.maydell@linaro.org | ||
5 | --- | 12 | --- |
6 | hw/dma/pl080.c | 25 +++++++++++++++++++++++++ | 13 | include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++ |
7 | 1 file changed, 25 insertions(+) | 14 | hw/ssi/ssi.c | 7 ++++++- |
15 | 2 files changed, 32 insertions(+), 1 deletion(-) | ||
8 | 16 | ||
9 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | 17 | diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h |
10 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
11 | --- a/hw/dma/pl080.c | 19 | --- a/include/hw/ssi/ssi.h |
12 | +++ b/hw/dma/pl080.c | 20 | +++ b/include/hw/ssi/ssi.h |
13 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pl080_ops = { | 21 | @@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave; |
14 | .endianness = DEVICE_NATIVE_ENDIAN, | 22 | } |
23 | |||
24 | DeviceState *ssi_create_slave(SSIBus *bus, const char *name); | ||
25 | +/** | ||
26 | + * ssi_realize_and_unref: realize and unref an SSI slave device | ||
27 | + * @dev: SSI slave device to realize | ||
28 | + * @bus: SSI bus to put it on | ||
29 | + * @errp: error pointer | ||
30 | + * | ||
31 | + * Call 'realize' on @dev, put it on the specified @bus, and drop the | ||
32 | + * reference to it. Errors are reported via @errp and by returning | ||
33 | + * false. | ||
34 | + * | ||
35 | + * This function is useful if you have created @dev via qdev_new() | ||
36 | + * (which takes a reference to the device it returns to you), so that | ||
37 | + * you can set properties on it before realizing it. If you don't need | ||
38 | + * to set properties then ssi_create_slave() is probably better (as it | ||
39 | + * does the create, init and realize in one step). | ||
40 | + * | ||
41 | + * If you are embedding the SSI slave into another QOM device and | ||
42 | + * initialized it via some variant on object_initialize_child() then | ||
43 | + * do not use this function, because that family of functions arrange | ||
44 | + * for the only reference to the child device to be held by the parent | ||
45 | + * via the child<> property, and so the reference-count-drop done here | ||
46 | + * would be incorrect. (Instead you would want ssi_realize(), which | ||
47 | + * doesn't currently exist but would be trivial to create if we had | ||
48 | + * any code that wanted it.) | ||
49 | + */ | ||
50 | +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp); | ||
51 | |||
52 | /* Master interface. */ | ||
53 | SSIBus *ssi_create_bus(DeviceState *parent, const char *name); | ||
54 | diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/ssi/ssi.c | ||
57 | +++ b/hw/ssi/ssi.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = { | ||
59 | .abstract = true, | ||
15 | }; | 60 | }; |
16 | 61 | ||
17 | +static void pl080_reset(DeviceState *dev) | 62 | +bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp) |
18 | +{ | 63 | +{ |
19 | + PL080State *s = PL080(dev); | 64 | + return qdev_realize_and_unref(dev, &bus->parent_obj, errp); |
20 | + int i; | ||
21 | + | ||
22 | + s->tc_int = 0; | ||
23 | + s->tc_mask = 0; | ||
24 | + s->err_int = 0; | ||
25 | + s->err_mask = 0; | ||
26 | + s->conf = 0; | ||
27 | + s->sync = 0; | ||
28 | + s->req_single = 0; | ||
29 | + s->req_burst = 0; | ||
30 | + s->running = 0; | ||
31 | + | ||
32 | + for (i = 0; i < s->nchannels; i++) { | ||
33 | + s->chan[i].src = 0; | ||
34 | + s->chan[i].dest = 0; | ||
35 | + s->chan[i].lli = 0; | ||
36 | + s->chan[i].ctrl = 0; | ||
37 | + s->chan[i].conf = 0; | ||
38 | + } | ||
39 | +} | 65 | +} |
40 | + | 66 | + |
41 | static void pl080_init(Object *obj) | 67 | DeviceState *ssi_create_slave(SSIBus *bus, const char *name) |
42 | { | 68 | { |
43 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 69 | DeviceState *dev = qdev_new(name); |
44 | @@ -XXX,XX +XXX,XX @@ static void pl080_class_init(ObjectClass *oc, void *data) | 70 | |
45 | dc->vmsd = &vmstate_pl080; | 71 | - qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal); |
46 | dc->realize = pl080_realize; | 72 | + ssi_realize_and_unref(dev, bus, &error_fatal); |
47 | dc->props = pl080_properties; | 73 | return dev; |
48 | + dc->reset = pl080_reset; | ||
49 | } | 74 | } |
50 | 75 | ||
51 | static const TypeInfo pl080_info = { | ||
52 | -- | 76 | -- |
53 | 2.18.0 | 77 | 2.20.1 |
54 | 78 | ||
55 | 79 | diff view generated by jsdifflib |
1 | The PL08x model currently will unconditionally call hw_error() | 1 | Use the new max111x qdev properties to set the initial input |
---|---|---|---|
2 | if the DMA engine is enabled by the guest. This has been | 2 | values rather than calling max111x_set_input(); this means that |
3 | present since the PL080 model was edded in 2006, and is | 3 | on system reset the inputs will correctly return to their initial |
4 | presumably either unintentional debug code left enabled, | 4 | values. |
5 | or a guard against untested DMA engine code being used. | ||
6 | |||
7 | Remove the hw_error(), since we now have a guest which | ||
8 | will actually try to use the DMA engine (the self-test | ||
9 | binary for the AN505 MPS2 FPGA image). | ||
10 | 5 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Message-id: 20200628142429.17111-10-peter.maydell@linaro.org | ||
13 | --- | 9 | --- |
14 | hw/dma/pl080.c | 1 - | 10 | hw/arm/spitz.c | 11 +++++++---- |
15 | 1 file changed, 1 deletion(-) | 11 | 1 file changed, 7 insertions(+), 4 deletions(-) |
16 | 12 | ||
17 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | 13 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/dma/pl080.c | 15 | --- a/hw/arm/spitz.c |
20 | +++ b/hw/dma/pl080.c | 16 | +++ b/hw/arm/spitz.c |
21 | @@ -XXX,XX +XXX,XX @@ static void pl080_run(PL080State *s) | 17 | @@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms) |
22 | if ((s->conf & PL080_CONF_E) == 0) | 18 | qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); |
23 | return; | 19 | |
24 | 20 | bus = qdev_get_child_bus(sms->mux, "ssi2"); | |
25 | -hw_error("DMA active\n"); | 21 | - sms->max1111 = ssi_create_slave(bus, "max1111"); |
26 | /* If we are already in the middle of a DMA operation then indicate that | 22 | + sms->max1111 = qdev_new("max1111"); |
27 | there may be new DMA requests and return immediately. */ | 23 | max1111 = sms->max1111; |
28 | if (s->running) { | 24 | - max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT); |
25 | - max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0); | ||
26 | - max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN); | ||
27 | + qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, | ||
28 | + SPITZ_BATTERY_VOLT); | ||
29 | + qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0); | ||
30 | + qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */, | ||
31 | + SPITZ_CHARGEON_ACIN); | ||
32 | + ssi_realize_and_unref(sms->max1111, bus, &error_fatal); | ||
33 | |||
34 | qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS, | ||
35 | qdev_get_gpio_in(sms->mux, 0)); | ||
29 | -- | 36 | -- |
30 | 2.18.0 | 37 | 2.20.1 |
31 | 38 | ||
32 | 39 | diff view generated by jsdifflib |
1 | Remove the obsolete MMIO request_ptr APIs; they have no | 1 | The max111x ADC device model allows other code to set the level on |
---|---|---|---|
2 | users now. | 2 | the 8 ADC inputs using the max111x_set_input() function. Replace |
3 | this with generic qdev GPIO inputs, which also allow inputs to be set | ||
4 | to arbitrary values. | ||
5 | |||
6 | Using GPIO lines will make it easier for board code to wire things | ||
7 | up, so that if device A wants to set the ADC input it doesn't need to | ||
8 | have a direct pointer to the max111x but can just set that value on | ||
9 | its output GPIO, which is then wired up by the board to the | ||
10 | appropriate max111x input. | ||
3 | 11 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | 14 | Message-id: 20200628142429.17111-11-peter.maydell@linaro.org |
8 | Message-id: 20180817114619.22354-3-peter.maydell@linaro.org | ||
9 | --- | 15 | --- |
10 | include/exec/memory.h | 35 -------------- | 16 | include/hw/ssi/ssi.h | 3 --- |
11 | memory.c | 110 ------------------------------------------ | 17 | hw/arm/spitz.c | 9 +++++---- |
12 | 2 files changed, 145 deletions(-) | 18 | hw/misc/max111x.c | 16 +++++++++------- |
19 | 3 files changed, 14 insertions(+), 14 deletions(-) | ||
13 | 20 | ||
14 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 21 | diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h |
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/exec/memory.h | 23 | --- a/include/hw/ssi/ssi.h |
17 | +++ b/include/exec/memory.h | 24 | +++ b/include/hw/ssi/ssi.h |
18 | @@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps { | 25 | @@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name); |
19 | uint64_t data, | 26 | |
20 | unsigned size, | 27 | uint32_t ssi_transfer(SSIBus *bus, uint32_t val); |
21 | MemTxAttrs attrs); | 28 | |
22 | - /* Instruction execution pre-callback: | 29 | -/* max111x.c */ |
23 | - * @addr is the address of the access relative to the @mr. | 30 | -void max111x_set_input(DeviceState *dev, int line, uint8_t value); |
24 | - * @size is the size of the area returned by the callback. | ||
25 | - * @offset is the location of the pointer inside @mr. | ||
26 | - * | ||
27 | - * Returns a pointer to a location which contains guest code. | ||
28 | - */ | ||
29 | - void *(*request_ptr)(void *opaque, hwaddr addr, unsigned *size, | ||
30 | - unsigned *offset); | ||
31 | |||
32 | enum device_endian endianness; | ||
33 | /* Guest-visible constraints: */ | ||
34 | @@ -XXX,XX +XXX,XX @@ void memory_global_dirty_log_stop(void); | ||
35 | void mtree_info(fprintf_function mon_printf, void *f, bool flatview, | ||
36 | bool dispatch_tree, bool owner); | ||
37 | |||
38 | -/** | ||
39 | - * memory_region_request_mmio_ptr: request a pointer to an mmio | ||
40 | - * MemoryRegion. If it is possible map a RAM MemoryRegion with this pointer. | ||
41 | - * When the device wants to invalidate the pointer it will call | ||
42 | - * memory_region_invalidate_mmio_ptr. | ||
43 | - * | ||
44 | - * @mr: #MemoryRegion to check | ||
45 | - * @addr: address within that region | ||
46 | - * | ||
47 | - * Returns true on success, false otherwise. | ||
48 | - */ | ||
49 | -bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr); | ||
50 | - | 31 | - |
51 | -/** | 32 | #endif |
52 | - * memory_region_invalidate_mmio_ptr: invalidate the pointer to an mmio | 33 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
53 | - * previously requested. | ||
54 | - * In the end that means that if something wants to execute from this area it | ||
55 | - * will need to request the pointer again. | ||
56 | - * | ||
57 | - * @mr: #MemoryRegion associated to the pointer. | ||
58 | - * @offset: offset within the memory region | ||
59 | - * @size: size of that area. | ||
60 | - */ | ||
61 | -void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset, | ||
62 | - unsigned size); | ||
63 | - | ||
64 | /** | ||
65 | * memory_region_dispatch_read: perform a read directly to the specified | ||
66 | * MemoryRegion. | ||
67 | diff --git a/memory.c b/memory.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
69 | --- a/memory.c | 35 | --- a/hw/arm/spitz.c |
70 | +++ b/memory.c | 36 | +++ b/hw/arm/spitz.c |
71 | @@ -XXX,XX +XXX,XX @@ | 37 | @@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) |
72 | #include "exec/ram_addr.h" | 38 | |
73 | #include "sysemu/kvm.h" | 39 | static void spitz_adc_temp_on(void *opaque, int line, int level) |
74 | #include "sysemu/sysemu.h" | 40 | { |
75 | -#include "hw/misc/mmio_interface.h" | 41 | + int batt_temp; |
76 | #include "hw/qdev-properties.h" | 42 | + |
77 | #include "migration/vmstate.h" | 43 | if (!max1111) |
78 | 44 | return; | |
79 | @@ -XXX,XX +XXX,XX @@ void memory_listener_unregister(MemoryListener *listener) | 45 | |
80 | listener->address_space = NULL; | 46 | - if (level) |
47 | - max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP); | ||
48 | - else | ||
49 | - max111x_set_input(max1111, MAX1111_BATT_TEMP, 0); | ||
50 | + batt_temp = level ? SPITZ_BATTERY_TEMP : 0; | ||
51 | + | ||
52 | + qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp); | ||
81 | } | 53 | } |
82 | 54 | ||
83 | -bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr) | 55 | static void corgi_ssp_realize(SSISlave *d, Error **errp) |
56 | diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/misc/max111x.c | ||
59 | +++ b/hw/misc/max111x.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = { | ||
61 | } | ||
62 | }; | ||
63 | |||
64 | +static void max111x_input_set(void *opaque, int line, int value) | ||
65 | +{ | ||
66 | + MAX111xState *s = MAX_111X(opaque); | ||
67 | + | ||
68 | + assert(line >= 0 && line < s->inputs); | ||
69 | + s->input[line] = value; | ||
70 | +} | ||
71 | + | ||
72 | static int max111x_init(SSISlave *d, int inputs) | ||
73 | { | ||
74 | DeviceState *dev = DEVICE(d); | ||
75 | MAX111xState *s = MAX_111X(dev); | ||
76 | |||
77 | qdev_init_gpio_out(dev, &s->interrupt, 1); | ||
78 | + qdev_init_gpio_in(dev, max111x_input_set, inputs); | ||
79 | |||
80 | s->inputs = inputs; | ||
81 | |||
82 | @@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp) | ||
83 | max111x_init(dev, 4); | ||
84 | } | ||
85 | |||
86 | -void max111x_set_input(DeviceState *dev, int line, uint8_t value) | ||
84 | -{ | 87 | -{ |
85 | - void *host; | 88 | - MAX111xState *s = MAX_111X(dev); |
86 | - unsigned size = 0; | 89 | - assert(line >= 0 && line < s->inputs); |
87 | - unsigned offset = 0; | 90 | - s->input[line] = value; |
88 | - Object *new_interface; | ||
89 | - | ||
90 | - if (!mr || !mr->ops->request_ptr) { | ||
91 | - return false; | ||
92 | - } | ||
93 | - | ||
94 | - /* | ||
95 | - * Avoid an update if the request_ptr call | ||
96 | - * memory_region_invalidate_mmio_ptr which seems to be likely when we use | ||
97 | - * a cache. | ||
98 | - */ | ||
99 | - memory_region_transaction_begin(); | ||
100 | - | ||
101 | - host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset); | ||
102 | - | ||
103 | - if (!host || !size) { | ||
104 | - memory_region_transaction_commit(); | ||
105 | - return false; | ||
106 | - } | ||
107 | - | ||
108 | - new_interface = object_new("mmio_interface"); | ||
109 | - qdev_prop_set_uint64(DEVICE(new_interface), "start", offset); | ||
110 | - qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1); | ||
111 | - qdev_prop_set_bit(DEVICE(new_interface), "ro", true); | ||
112 | - qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host); | ||
113 | - qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr); | ||
114 | - object_property_set_bool(OBJECT(new_interface), true, "realized", NULL); | ||
115 | - | ||
116 | - memory_region_transaction_commit(); | ||
117 | - return true; | ||
118 | -} | 91 | -} |
119 | - | 92 | - |
120 | -typedef struct MMIOPtrInvalidate { | 93 | static void max111x_reset(DeviceState *dev) |
121 | - MemoryRegion *mr; | ||
122 | - hwaddr offset; | ||
123 | - unsigned size; | ||
124 | - int busy; | ||
125 | - int allocated; | ||
126 | -} MMIOPtrInvalidate; | ||
127 | - | ||
128 | -#define MAX_MMIO_INVALIDATE 10 | ||
129 | -static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE]; | ||
130 | - | ||
131 | -static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu, | ||
132 | - run_on_cpu_data data) | ||
133 | -{ | ||
134 | - MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr; | ||
135 | - MemoryRegion *mr = invalidate_data->mr; | ||
136 | - hwaddr offset = invalidate_data->offset; | ||
137 | - unsigned size = invalidate_data->size; | ||
138 | - MemoryRegionSection section = memory_region_find(mr, offset, size); | ||
139 | - | ||
140 | - qemu_mutex_lock_iothread(); | ||
141 | - | ||
142 | - /* Reset dirty so this doesn't happen later. */ | ||
143 | - cpu_physical_memory_test_and_clear_dirty(offset, size, 1); | ||
144 | - | ||
145 | - if (section.mr != mr) { | ||
146 | - /* memory_region_find add a ref on section.mr */ | ||
147 | - memory_region_unref(section.mr); | ||
148 | - if (MMIO_INTERFACE(section.mr->owner)) { | ||
149 | - /* We found the interface just drop it. */ | ||
150 | - object_property_set_bool(section.mr->owner, false, "realized", | ||
151 | - NULL); | ||
152 | - object_unref(section.mr->owner); | ||
153 | - object_unparent(section.mr->owner); | ||
154 | - } | ||
155 | - } | ||
156 | - | ||
157 | - qemu_mutex_unlock_iothread(); | ||
158 | - | ||
159 | - if (invalidate_data->allocated) { | ||
160 | - g_free(invalidate_data); | ||
161 | - } else { | ||
162 | - invalidate_data->busy = 0; | ||
163 | - } | ||
164 | -} | ||
165 | - | ||
166 | -void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset, | ||
167 | - unsigned size) | ||
168 | -{ | ||
169 | - size_t i; | ||
170 | - MMIOPtrInvalidate *invalidate_data = NULL; | ||
171 | - | ||
172 | - for (i = 0; i < MAX_MMIO_INVALIDATE; i++) { | ||
173 | - if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) { | ||
174 | - invalidate_data = &mmio_ptr_invalidate_list[i]; | ||
175 | - break; | ||
176 | - } | ||
177 | - } | ||
178 | - | ||
179 | - if (!invalidate_data) { | ||
180 | - invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate)); | ||
181 | - invalidate_data->allocated = 1; | ||
182 | - } | ||
183 | - | ||
184 | - invalidate_data->mr = mr; | ||
185 | - invalidate_data->offset = offset; | ||
186 | - invalidate_data->size = size; | ||
187 | - | ||
188 | - async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr, | ||
189 | - RUN_ON_CPU_HOST_PTR(invalidate_data)); | ||
190 | -} | ||
191 | - | ||
192 | void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name) | ||
193 | { | 94 | { |
194 | memory_region_ref(root); | 95 | MAX111xState *s = MAX_111X(dev); |
195 | -- | 96 | -- |
196 | 2.18.0 | 97 | 2.20.1 |
197 | 98 | ||
198 | 99 | diff view generated by jsdifflib |
1 | Create a new include file for the pl081's device struct, | 1 | Create a header file for the hw/misc/max111x device, in the |
---|---|---|---|
2 | type macros, etc, so that it can be instantiated using | 2 | usual modern style for QOM devices: |
3 | the "embedded struct" coding style. | 3 | * definition of the TYPE_ constants and macros |
4 | * definition of the device's state struct so that it can | ||
5 | be embedded in other structs if desired | ||
6 | * documentation of the interface | ||
7 | |||
8 | This allows us to use TYPE_MAX_1111 in the spitz.c code rather | ||
9 | than the string "max1111". | ||
4 | 10 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
13 | Message-id: 20200628142429.17111-12-peter.maydell@linaro.org | ||
7 | --- | 14 | --- |
8 | include/hw/dma/pl080.h | 62 ++++++++++++++++++++++++++++++++++++++++++ | 15 | include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++ |
9 | hw/dma/pl080.c | 34 ++--------------------- | 16 | hw/arm/spitz.c | 3 ++- |
10 | MAINTAINERS | 1 + | 17 | hw/misc/max111x.c | 24 +---------------- |
11 | 3 files changed, 65 insertions(+), 32 deletions(-) | 18 | MAINTAINERS | 1 + |
12 | create mode 100644 include/hw/dma/pl080.h | 19 | 4 files changed, 60 insertions(+), 24 deletions(-) |
20 | create mode 100644 include/hw/misc/max111x.h | ||
13 | 21 | ||
14 | diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h | 22 | diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h |
15 | new file mode 100644 | 23 | new file mode 100644 |
16 | index XXXXXXX..XXXXXXX | 24 | index XXXXXXX..XXXXXXX |
17 | --- /dev/null | 25 | --- /dev/null |
18 | +++ b/include/hw/dma/pl080.h | 26 | +++ b/include/hw/misc/max111x.h |
19 | @@ -XXX,XX +XXX,XX @@ | 27 | @@ -XXX,XX +XXX,XX @@ |
20 | +/* | 28 | +/* |
21 | + * ARM PrimeCell PL080/PL081 DMA controller | 29 | + * Maxim MAX1110/1111 ADC chip emulation. |
22 | + * | 30 | + * |
23 | + * Copyright (c) 2006 CodeSourcery. | 31 | + * Copyright (c) 2006 Openedhand Ltd. |
24 | + * Copyright (c) 2018 Linaro Limited | 32 | + * Written by Andrzej Zaborowski <balrog@zabor.org> |
25 | + * Written by Paul Brook, Peter Maydell | ||
26 | + * | 33 | + * |
27 | + * This program is free software; you can redistribute it and/or modify | 34 | + * This code is licensed under the GNU GPLv2. |
28 | + * it under the terms of the GNU General Public License version 2 or | 35 | + * |
29 | + * (at your option) any later version. | 36 | + * Contributions after 2012-01-13 are licensed under the terms of the |
37 | + * GNU GPL, version 2 or (at your option) any later version. | ||
30 | + */ | 38 | + */ |
31 | + | 39 | + |
32 | +/* This is a model of the Arm PrimeCell PL080/PL081 DMA controller: | 40 | +#ifndef HW_MISC_MAX111X_H |
33 | + * The PL080 TRM is: | 41 | +#define HW_MISC_MAX111X_H |
34 | + * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf | 42 | + |
35 | + * and the PL081 TRM is: | 43 | +#include "hw/ssi/ssi.h" |
36 | + * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf | 44 | + |
45 | +/* | ||
46 | + * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU | ||
47 | + * is an SSI slave device. It has either 4 (max1110) or 8 (max1111) | ||
48 | + * 8-bit ADC channels. | ||
37 | + * | 49 | + * |
38 | + * QEMU interface: | 50 | + * QEMU interface: |
39 | + * + sysbus IRQ: DMACINTR combined interrupt line | 51 | + * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value |
40 | + * + sysbus MMIO region 0: MemoryRegion for the device's registers | 52 | + * of each ADC input, as an unsigned 8-bit value |
53 | + * + GPIO output 0: interrupt line | ||
54 | + * + Properties "input0" to "input3" (max1110) or "input0" to "input7" | ||
55 | + * (max1111): initial reset values for ADC inputs. | ||
56 | + * | ||
57 | + * Known bugs: | ||
58 | + * + the interrupt line is not correctly implemented, and will never | ||
59 | + * be lowered once it has been asserted. | ||
41 | + */ | 60 | + */ |
61 | +typedef struct { | ||
62 | + SSISlave parent_obj; | ||
42 | + | 63 | + |
43 | +#ifndef HW_DMA_PL080_H | 64 | + qemu_irq interrupt; |
44 | +#define HW_DMA_PL080_H | 65 | + /* Values of inputs at system reset (settable by QOM property) */ |
66 | + uint8_t reset_input[8]; | ||
45 | + | 67 | + |
46 | +#include "hw/sysbus.h" | 68 | + uint8_t tb1, rb2, rb3; |
69 | + int cycle; | ||
47 | + | 70 | + |
48 | +#define PL080_MAX_CHANNELS 8 | 71 | + uint8_t input[8]; |
72 | + int inputs, com; | ||
73 | +} MAX111xState; | ||
49 | + | 74 | + |
50 | +typedef struct { | 75 | +#define TYPE_MAX_111X "max111x" |
51 | + uint32_t src; | ||
52 | + uint32_t dest; | ||
53 | + uint32_t lli; | ||
54 | + uint32_t ctrl; | ||
55 | + uint32_t conf; | ||
56 | +} pl080_channel; | ||
57 | + | 76 | + |
58 | +#define TYPE_PL080 "pl080" | 77 | +#define MAX_111X(obj) \ |
59 | +#define TYPE_PL081 "pl081" | 78 | + OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) |
60 | +#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080) | ||
61 | + | 79 | + |
62 | +typedef struct PL080State { | 80 | +#define TYPE_MAX_1110 "max1110" |
63 | + SysBusDevice parent_obj; | 81 | +#define TYPE_MAX_1111 "max1111" |
64 | + | ||
65 | + MemoryRegion iomem; | ||
66 | + uint8_t tc_int; | ||
67 | + uint8_t tc_mask; | ||
68 | + uint8_t err_int; | ||
69 | + uint8_t err_mask; | ||
70 | + uint32_t conf; | ||
71 | + uint32_t sync; | ||
72 | + uint32_t req_single; | ||
73 | + uint32_t req_burst; | ||
74 | + pl080_channel chan[PL080_MAX_CHANNELS]; | ||
75 | + int nchannels; | ||
76 | + /* Flag to avoid recursive DMA invocations. */ | ||
77 | + int running; | ||
78 | + qemu_irq irq; | ||
79 | +} PL080State; | ||
80 | + | 82 | + |
81 | +#endif | 83 | +#endif |
82 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | 84 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
83 | index XXXXXXX..XXXXXXX 100644 | 85 | index XXXXXXX..XXXXXXX 100644 |
84 | --- a/hw/dma/pl080.c | 86 | --- a/hw/arm/spitz.c |
85 | +++ b/hw/dma/pl080.c | 87 | +++ b/hw/arm/spitz.c |
86 | @@ -XXX,XX +XXX,XX @@ | 88 | @@ -XXX,XX +XXX,XX @@ |
89 | #include "audio/audio.h" | ||
90 | #include "hw/boards.h" | ||
87 | #include "hw/sysbus.h" | 91 | #include "hw/sysbus.h" |
92 | +#include "hw/misc/max111x.h" | ||
93 | #include "migration/vmstate.h" | ||
88 | #include "exec/address-spaces.h" | 94 | #include "exec/address-spaces.h" |
89 | #include "qemu/log.h" | 95 | #include "cpu.h" |
90 | +#include "hw/dma/pl080.h" | 96 | @@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms) |
91 | 97 | qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT)); | |
92 | -#define PL080_MAX_CHANNELS 8 | 98 | |
93 | #define PL080_CONF_E 0x1 | 99 | bus = qdev_get_child_bus(sms->mux, "ssi2"); |
94 | #define PL080_CONF_M1 0x2 | 100 | - sms->max1111 = qdev_new("max1111"); |
95 | #define PL080_CONF_M2 0x4 | 101 | + sms->max1111 = qdev_new(TYPE_MAX_1111); |
102 | max1111 = sms->max1111; | ||
103 | qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, | ||
104 | SPITZ_BATTERY_VOLT); | ||
105 | diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c | ||
106 | index XXXXXXX..XXXXXXX 100644 | ||
107 | --- a/hw/misc/max111x.c | ||
108 | +++ b/hw/misc/max111x.c | ||
96 | @@ -XXX,XX +XXX,XX @@ | 109 | @@ -XXX,XX +XXX,XX @@ |
97 | #define PL080_CCTRL_D 0x02000000 | 110 | */ |
98 | #define PL080_CCTRL_S 0x01000000 | 111 | |
112 | #include "qemu/osdep.h" | ||
113 | +#include "hw/misc/max111x.h" | ||
114 | #include "hw/irq.h" | ||
115 | -#include "hw/ssi/ssi.h" | ||
116 | #include "migration/vmstate.h" | ||
117 | #include "qemu/module.h" | ||
118 | #include "hw/qdev-properties.h" | ||
99 | 119 | ||
100 | -typedef struct { | 120 | -typedef struct { |
101 | - uint32_t src; | 121 | - SSISlave parent_obj; |
102 | - uint32_t dest; | ||
103 | - uint32_t lli; | ||
104 | - uint32_t ctrl; | ||
105 | - uint32_t conf; | ||
106 | -} pl080_channel; | ||
107 | - | 122 | - |
108 | -#define TYPE_PL080 "pl080" | 123 | - qemu_irq interrupt; |
109 | -#define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080) | 124 | - /* Values of inputs at system reset (settable by QOM property) */ |
125 | - uint8_t reset_input[8]; | ||
110 | - | 126 | - |
111 | -typedef struct PL080State { | 127 | - uint8_t tb1, rb2, rb3; |
112 | - SysBusDevice parent_obj; | 128 | - int cycle; |
113 | - | 129 | - |
114 | - MemoryRegion iomem; | 130 | - uint8_t input[8]; |
115 | - uint8_t tc_int; | 131 | - int inputs, com; |
116 | - uint8_t tc_mask; | 132 | -} MAX111xState; |
117 | - uint8_t err_int; | ||
118 | - uint8_t err_mask; | ||
119 | - uint32_t conf; | ||
120 | - uint32_t sync; | ||
121 | - uint32_t req_single; | ||
122 | - uint32_t req_burst; | ||
123 | - pl080_channel chan[PL080_MAX_CHANNELS]; | ||
124 | - int nchannels; | ||
125 | - /* Flag to avoid recursive DMA invocations. */ | ||
126 | - int running; | ||
127 | - qemu_irq irq; | ||
128 | -} PL080State; | ||
129 | - | 133 | - |
130 | static const VMStateDescription vmstate_pl080_channel = { | 134 | -#define TYPE_MAX_111X "max111x" |
131 | .name = "pl080_channel", | 135 | - |
132 | .version_id = 1, | 136 | -#define MAX_111X(obj) \ |
133 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo pl080_info = { | 137 | - OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X) |
134 | }; | 138 | - |
135 | 139 | -#define TYPE_MAX_1110 "max1110" | |
136 | static const TypeInfo pl081_info = { | 140 | -#define TYPE_MAX_1111 "max1111" |
137 | - .name = "pl081", | 141 | - |
138 | + .name = TYPE_PL081, | 142 | /* Control-byte bitfields */ |
139 | .parent = TYPE_PL080, | 143 | #define CB_PD0 (1 << 0) |
140 | .instance_init = pl081_init, | 144 | #define CB_PD1 (1 << 1) |
141 | }; | ||
142 | diff --git a/MAINTAINERS b/MAINTAINERS | 145 | diff --git a/MAINTAINERS b/MAINTAINERS |
143 | index XXXXXXX..XXXXXXX 100644 | 146 | index XXXXXXX..XXXXXXX 100644 |
144 | --- a/MAINTAINERS | 147 | --- a/MAINTAINERS |
145 | +++ b/MAINTAINERS | 148 | +++ b/MAINTAINERS |
146 | @@ -XXX,XX +XXX,XX @@ F: hw/char/pl011.c | 149 | @@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c |
147 | F: include/hw/char/pl011.h | 150 | F: hw/gpio/zaurus.c |
148 | F: hw/display/pl110* | 151 | F: hw/misc/mst_fpga.c |
149 | F: hw/dma/pl080.c | 152 | F: hw/misc/max111x.c |
150 | +F: include/hw/dma/pl080.h | 153 | +F: include/hw/misc/max111x.h |
151 | F: hw/dma/pl330.c | 154 | F: include/hw/arm/pxa.h |
152 | F: hw/gpio/pl061.c | 155 | F: include/hw/arm/sharpsl.h |
153 | F: hw/input/pl050.c | 156 | F: include/hw/display/tc6393xb.h |
154 | -- | 157 | -- |
155 | 2.18.0 | 158 | 2.20.1 |
156 | 159 | ||
157 | 160 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Currently we have a free-floating set of IRQs and a function | |
2 | spitz_out_switch() which handle some miscellaneous GPIO lines for the | ||
3 | spitz board. Encapsulate this behaviour in a simple QOM device. | ||
4 | |||
5 | At this point we can finally remove the 'max1111' global, because the | ||
6 | ADC battery-temperature value is now handled by the misc-gpio device | ||
7 | writing the value to its outbound "adc-temp" GPIO, which the board | ||
8 | code wires up to the appropriate inbound GPIO line on the max1111. | ||
9 | |||
10 | This commit also fixes Coverity issue CID 1421913 (which pointed out | ||
11 | that the 'outsignals' in spitz_scoop_gpio_setup() were leaked), | ||
12 | because it removes the use of the qemu_allocate_irqs() API from this | ||
13 | code entirely. | ||
14 | |||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
17 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
18 | Message-id: 20200628142429.17111-13-peter.maydell@linaro.org | ||
19 | --- | ||
20 | hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++---------------- | ||
21 | 1 file changed, 87 insertions(+), 42 deletions(-) | ||
22 | |||
23 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/hw/arm/spitz.c | ||
26 | +++ b/hw/arm/spitz.c | ||
27 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
28 | DeviceState *max1111; | ||
29 | DeviceState *scp0; | ||
30 | DeviceState *scp1; | ||
31 | + DeviceState *misc_gpio; | ||
32 | } SpitzMachineState; | ||
33 | |||
34 | #define TYPE_SPITZ_MACHINE "spitz-common" | ||
35 | @@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) | ||
36 | #define SPITZ_GPIO_MAX1111_CS 20 | ||
37 | #define SPITZ_GPIO_TP_INT 11 | ||
38 | |||
39 | -static DeviceState *max1111; | ||
40 | - | ||
41 | /* "Demux" the signal based on current chipselect */ | ||
42 | typedef struct { | ||
43 | SSISlave ssidev; | ||
44 | @@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) | ||
45 | #define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */ | ||
46 | #define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */ | ||
47 | |||
48 | -static void spitz_adc_temp_on(void *opaque, int line, int level) | ||
49 | -{ | ||
50 | - int batt_temp; | ||
51 | - | ||
52 | - if (!max1111) | ||
53 | - return; | ||
54 | - | ||
55 | - batt_temp = level ? SPITZ_BATTERY_TEMP : 0; | ||
56 | - | ||
57 | - qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp); | ||
58 | -} | ||
59 | - | ||
60 | static void corgi_ssp_realize(SSISlave *d, Error **errp) | ||
61 | { | ||
62 | DeviceState *dev = DEVICE(d); | ||
63 | @@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms) | ||
64 | |||
65 | bus = qdev_get_child_bus(sms->mux, "ssi2"); | ||
66 | sms->max1111 = qdev_new(TYPE_MAX_1111); | ||
67 | - max1111 = sms->max1111; | ||
68 | qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */, | ||
69 | SPITZ_BATTERY_VOLT); | ||
70 | qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0); | ||
71 | @@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu) | ||
72 | |||
73 | /* Other peripherals */ | ||
74 | |||
75 | -static void spitz_out_switch(void *opaque, int line, int level) | ||
76 | +/* | ||
77 | + * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards. | ||
78 | + * | ||
79 | + * QEMU interface: | ||
80 | + * + named GPIO inputs "green-led", "orange-led", "charging", "discharging": | ||
81 | + * these currently just print messages that the line has been signalled | ||
82 | + * + named GPIO input "adc-temp-on": set to cause the battery-temperature | ||
83 | + * value to be passed to the max111x ADC | ||
84 | + * + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x | ||
85 | + */ | ||
86 | +#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio" | ||
87 | +#define SPITZ_MISC_GPIO(obj) \ | ||
88 | + OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO) | ||
89 | + | ||
90 | +typedef struct SpitzMiscGPIOState { | ||
91 | + SysBusDevice parent_obj; | ||
92 | + | ||
93 | + qemu_irq adc_value; | ||
94 | +} SpitzMiscGPIOState; | ||
95 | + | ||
96 | +static void spitz_misc_charging(void *opaque, int n, int level) | ||
97 | { | ||
98 | - switch (line) { | ||
99 | - case 0: | ||
100 | - zaurus_printf("Charging %s.\n", level ? "off" : "on"); | ||
101 | - break; | ||
102 | - case 1: | ||
103 | - zaurus_printf("Discharging %s.\n", level ? "on" : "off"); | ||
104 | - break; | ||
105 | - case 2: | ||
106 | - zaurus_printf("Green LED %s.\n", level ? "on" : "off"); | ||
107 | - break; | ||
108 | - case 3: | ||
109 | - zaurus_printf("Orange LED %s.\n", level ? "on" : "off"); | ||
110 | - break; | ||
111 | - case 6: | ||
112 | - spitz_adc_temp_on(opaque, line, level); | ||
113 | - break; | ||
114 | - default: | ||
115 | - g_assert_not_reached(); | ||
116 | - } | ||
117 | + zaurus_printf("Charging %s.\n", level ? "off" : "on"); | ||
118 | +} | ||
119 | + | ||
120 | +static void spitz_misc_discharging(void *opaque, int n, int level) | ||
121 | +{ | ||
122 | + zaurus_printf("Discharging %s.\n", level ? "off" : "on"); | ||
123 | +} | ||
124 | + | ||
125 | +static void spitz_misc_green_led(void *opaque, int n, int level) | ||
126 | +{ | ||
127 | + zaurus_printf("Green LED %s.\n", level ? "off" : "on"); | ||
128 | +} | ||
129 | + | ||
130 | +static void spitz_misc_orange_led(void *opaque, int n, int level) | ||
131 | +{ | ||
132 | + zaurus_printf("Orange LED %s.\n", level ? "off" : "on"); | ||
133 | +} | ||
134 | + | ||
135 | +static void spitz_misc_adc_temp(void *opaque, int n, int level) | ||
136 | +{ | ||
137 | + SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque); | ||
138 | + int batt_temp = level ? SPITZ_BATTERY_TEMP : 0; | ||
139 | + | ||
140 | + qemu_set_irq(s->adc_value, batt_temp); | ||
141 | +} | ||
142 | + | ||
143 | +static void spitz_misc_gpio_init(Object *obj) | ||
144 | +{ | ||
145 | + SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj); | ||
146 | + DeviceState *dev = DEVICE(obj); | ||
147 | + | ||
148 | + qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1); | ||
149 | + qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1); | ||
150 | + qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1); | ||
151 | + qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1); | ||
152 | + qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1); | ||
153 | + | ||
154 | + qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1); | ||
155 | } | ||
156 | |||
157 | #define SPITZ_SCP_LED_GREEN 1 | ||
158 | @@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level) | ||
159 | |||
160 | static void spitz_scoop_gpio_setup(SpitzMachineState *sms) | ||
161 | { | ||
162 | - qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8); | ||
163 | + DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL); | ||
164 | |||
165 | - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]); | ||
166 | - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]); | ||
167 | - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]); | ||
168 | - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]); | ||
169 | + sms->misc_gpio = miscdev; | ||
170 | + | ||
171 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, | ||
172 | + qdev_get_gpio_in_named(miscdev, "charging", 0)); | ||
173 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, | ||
174 | + qdev_get_gpio_in_named(miscdev, "discharging", 0)); | ||
175 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, | ||
176 | + qdev_get_gpio_in_named(miscdev, "green-led", 0)); | ||
177 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, | ||
178 | + qdev_get_gpio_in_named(miscdev, "orange-led", 0)); | ||
179 | + qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, | ||
180 | + qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0)); | ||
181 | + qdev_connect_gpio_out_named(miscdev, "adc-temp", 0, | ||
182 | + qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP)); | ||
183 | |||
184 | if (sms->scp1) { | ||
185 | qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT, | ||
186 | @@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms) | ||
187 | qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON, | ||
188 | qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0)); | ||
189 | } | ||
190 | - | ||
191 | - qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]); | ||
192 | } | ||
193 | |||
194 | #define SPITZ_GPIO_HSYNC 22 | ||
195 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = { | ||
196 | .class_init = spitz_lcdtg_class_init, | ||
197 | }; | ||
198 | |||
199 | +static const TypeInfo spitz_misc_gpio_info = { | ||
200 | + .name = TYPE_SPITZ_MISC_GPIO, | ||
201 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
202 | + .instance_size = sizeof(SpitzMiscGPIOState), | ||
203 | + .instance_init = spitz_misc_gpio_init, | ||
204 | + /* | ||
205 | + * No class_init required: device has no internal state so does not | ||
206 | + * need to set up reset or vmstate, and does not have a realize method. | ||
207 | + */ | ||
208 | +}; | ||
209 | + | ||
210 | static void spitz_register_types(void) | ||
211 | { | ||
212 | type_register_static(&corgi_ssp_info); | ||
213 | type_register_static(&spitz_lcdtg_info); | ||
214 | type_register_static(&spitz_keyboard_info); | ||
215 | type_register_static(&sl_nand_info); | ||
216 | + type_register_static(&spitz_misc_gpio_info); | ||
217 | } | ||
218 | |||
219 | type_init(spitz_register_types) | ||
220 | -- | ||
221 | 2.20.1 | ||
222 | |||
223 | diff view generated by jsdifflib |
1 | On real v7M hardware, the NMI line is an externally visible signal | 1 | Instead of logging guest accesses to invalid register offsets in this |
---|---|---|---|
2 | that an SoC or board can toggle to assert an NMI. Expose it in | 2 | device using zaurus_printf() (which just prints to stderr), use the |
3 | our QEMU NVIC and armv7m container objects so that a board model | 3 | usual qemu_log_mask(LOG_GUEST_ERROR,...). |
4 | can wire it up if it needs to. | ||
5 | 4 | ||
6 | In particular, the MPS2 watchdog is wired to NMI. | 5 | Since this was the only use of the zaurus_printf() macro outside |
6 | spitz.c, we can move the definition of that macro from sharpsl.h | ||
7 | to spitz.c. | ||
7 | 8 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
11 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
12 | Message-id: 20200628142429.17111-14-peter.maydell@linaro.org | ||
10 | --- | 13 | --- |
11 | hw/arm/armv7m.c | 1 + | 14 | include/hw/arm/sharpsl.h | 3 --- |
12 | hw/intc/armv7m_nvic.c | 19 +++++++++++++++++++ | 15 | hw/arm/spitz.c | 3 +++ |
13 | hw/intc/trace-events | 1 + | 16 | hw/gpio/zaurus.c | 12 +++++++----- |
14 | 3 files changed, 21 insertions(+) | 17 | 3 files changed, 10 insertions(+), 8 deletions(-) |
15 | 18 | ||
16 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 19 | diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h |
17 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/armv7m.c | 21 | --- a/include/hw/arm/sharpsl.h |
19 | +++ b/hw/arm/armv7m.c | 22 | +++ b/include/hw/arm/sharpsl.h |
20 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 23 | @@ -XXX,XX +XXX,XX @@ |
21 | */ | 24 | |
22 | qdev_pass_gpios(DEVICE(&s->nvic), dev, NULL); | 25 | #include "exec/hwaddr.h" |
23 | qdev_pass_gpios(DEVICE(&s->nvic), dev, "SYSRESETREQ"); | 26 | |
24 | + qdev_pass_gpios(DEVICE(&s->nvic), dev, "NMI"); | 27 | -#define zaurus_printf(format, ...) \ |
25 | 28 | - fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) | |
26 | /* Wire the NVIC up to the CPU */ | 29 | - |
27 | sbd = SYS_BUS_DEVICE(&s->nvic); | 30 | /* zaurus.c */ |
28 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 31 | |
32 | #define SL_PXA_PARAM_BASE 0xa0000a00 | ||
33 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/intc/armv7m_nvic.c | 35 | --- a/hw/arm/spitz.c |
31 | +++ b/hw/intc/armv7m_nvic.c | 36 | +++ b/hw/arm/spitz.c |
32 | @@ -XXX,XX +XXX,XX @@ static void set_irq_level(void *opaque, int n, int level) | 37 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
38 | #define SPITZ_MACHINE_CLASS(klass) \ | ||
39 | OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE) | ||
40 | |||
41 | +#define zaurus_printf(format, ...) \ | ||
42 | + fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) | ||
43 | + | ||
44 | #undef REG_FMT | ||
45 | #define REG_FMT "0x%02lx" | ||
46 | |||
47 | diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/hw/gpio/zaurus.c | ||
50 | +++ b/hw/gpio/zaurus.c | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | #include "hw/sysbus.h" | ||
53 | #include "migration/vmstate.h" | ||
54 | #include "qemu/module.h" | ||
55 | - | ||
56 | -#undef REG_FMT | ||
57 | -#define REG_FMT "0x%02lx" | ||
58 | +#include "qemu/log.h" | ||
59 | |||
60 | /* SCOOP devices */ | ||
61 | |||
62 | @@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr, | ||
63 | case SCOOP_GPRR: | ||
64 | return s->gpio_level; | ||
65 | default: | ||
66 | - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); | ||
67 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
68 | + "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n", | ||
69 | + addr); | ||
70 | } | ||
71 | |||
72 | return 0; | ||
73 | @@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr, | ||
74 | scoop_gpio_handler_update(s); | ||
75 | break; | ||
76 | default: | ||
77 | - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); | ||
78 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
79 | + "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n", | ||
80 | + addr); | ||
33 | } | 81 | } |
34 | } | 82 | } |
35 | 83 | ||
36 | +/* callback when external NMI line is changed */ | ||
37 | +static void nvic_nmi_trigger(void *opaque, int n, int level) | ||
38 | +{ | ||
39 | + NVICState *s = opaque; | ||
40 | + | ||
41 | + trace_nvic_set_nmi_level(level); | ||
42 | + | ||
43 | + /* | ||
44 | + * The architecture doesn't specify whether NMI should share | ||
45 | + * the normal-interrupt behaviour of being resampled on | ||
46 | + * exception handler return. We choose not to, so just | ||
47 | + * set NMI pending here and don't track the current level. | ||
48 | + */ | ||
49 | + if (level) { | ||
50 | + armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); | ||
51 | + } | ||
52 | +} | ||
53 | + | ||
54 | static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
55 | { | ||
56 | ARMCPU *cpu = s->cpu; | ||
57 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_instance_init(Object *obj) | ||
58 | qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1); | ||
59 | qdev_init_gpio_in_named(dev, nvic_systick_trigger, "systick-trigger", | ||
60 | M_REG_NUM_BANKS); | ||
61 | + qdev_init_gpio_in_named(dev, nvic_nmi_trigger, "NMI", 1); | ||
62 | } | ||
63 | |||
64 | static void armv7m_nvic_class_init(ObjectClass *klass, void *data) | ||
65 | diff --git a/hw/intc/trace-events b/hw/intc/trace-events | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/hw/intc/trace-events | ||
68 | +++ b/hw/intc/trace-events | ||
69 | @@ -XXX,XX +XXX,XX @@ nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (pr | ||
70 | nvic_get_pending_irq_info(int irq, bool secure) "NVIC next IRQ %d: targets_secure: %d" | ||
71 | nvic_complete_irq(int irq, bool secure) "NVIC complete IRQ %d (secure %d)" | ||
72 | nvic_set_irq_level(int irq, int level) "NVIC external irq %d level set to %d" | ||
73 | +nvic_set_nmi_level(int level) "NVIC external NMI level set to %d" | ||
74 | nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" | ||
75 | nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) "NVIC sysreg write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u" | ||
76 | |||
77 | -- | 84 | -- |
78 | 2.18.0 | 85 | 2.20.1 |
79 | 86 | ||
80 | 87 | diff view generated by jsdifflib |
1 | The PL080 and PL081 have three outgoing interrupt lines: | 1 | Instead of logging guest accesses to invalid register offsets in the |
---|---|---|---|
2 | * DMACINTERR signals DMA errors | 2 | Spitz flash device with zaurus_printf() (which just prints to stderr), |
3 | * DMACINTTC is the DMA count interrupt | 3 | use the usual qemu_log_mask(LOG_GUEST_ERROR,...). |
4 | * DMACINTR is a combined interrupt, the logical OR of the other two | ||
5 | |||
6 | We currently only implement DMACINTR, because that's all the | ||
7 | realview and versatile boards needed, but the instances of the | ||
8 | PL081 in the MPS2 firmware images use all three interrupt lines. | ||
9 | Implement the missing DMACINTERR and DMACINTTC. | ||
10 | 4 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
8 | Message-id: 20200628142429.17111-15-peter.maydell@linaro.org | ||
13 | --- | 9 | --- |
14 | include/hw/dma/pl080.h | 6 +++++- | 10 | hw/arm/spitz.c | 12 +++++++----- |
15 | hw/dma/pl080.c | 13 ++++++++----- | 11 | 1 file changed, 7 insertions(+), 5 deletions(-) |
16 | 2 files changed, 13 insertions(+), 6 deletions(-) | ||
17 | 12 | ||
18 | diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h | 13 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
19 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/dma/pl080.h | 15 | --- a/hw/arm/spitz.c |
21 | +++ b/include/hw/dma/pl080.h | 16 | +++ b/hw/arm/spitz.c |
22 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ |
23 | * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf | 18 | #include "hw/ssi/ssi.h" |
24 | * | 19 | #include "hw/block/flash.h" |
25 | * QEMU interface: | 20 | #include "qemu/timer.h" |
26 | - * + sysbus IRQ: DMACINTR combined interrupt line | 21 | +#include "qemu/log.h" |
27 | + * + sysbus IRQ 0: DMACINTR combined interrupt line | 22 | #include "hw/arm/sharpsl.h" |
28 | + * + sysbus IRQ 1: DMACINTERR error interrupt request | 23 | #include "ui/console.h" |
29 | + * + sysbus IRQ 2: DMACINTTC count interrupt request | 24 | #include "hw/audio/wm8750.h" |
30 | * + sysbus MMIO region 0: MemoryRegion for the device's registers | 25 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
31 | */ | 26 | #define zaurus_printf(format, ...) \ |
32 | 27 | fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__) | |
33 | @@ -XXX,XX +XXX,XX @@ typedef struct PL080State { | 28 | |
34 | /* Flag to avoid recursive DMA invocations. */ | 29 | -#undef REG_FMT |
35 | int running; | 30 | -#define REG_FMT "0x%02lx" |
36 | qemu_irq irq; | 31 | - |
37 | + qemu_irq interr; | 32 | /* Spitz Flash */ |
38 | + qemu_irq inttc; | 33 | #define FLASH_BASE 0x0c000000 |
39 | } PL080State; | 34 | #define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */ |
40 | 35 | @@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size) | |
41 | #endif | 36 | return ecc_digest(&s->ecc, nand_getio(s->nand)); |
42 | diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c | 37 | |
43 | index XXXXXXX..XXXXXXX 100644 | 38 | default: |
44 | --- a/hw/dma/pl080.c | 39 | - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
45 | +++ b/hw/dma/pl080.c | 40 | + qemu_log_mask(LOG_GUEST_ERROR, |
46 | @@ -XXX,XX +XXX,XX @@ static const unsigned char pl081_id[] = | 41 | + "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n", |
47 | 42 | + addr); | |
48 | static void pl080_update(PL080State *s) | 43 | } |
49 | { | 44 | return 0; |
50 | - if ((s->tc_int & s->tc_mask) | ||
51 | - || (s->err_int & s->err_mask)) | ||
52 | - qemu_irq_raise(s->irq); | ||
53 | - else | ||
54 | - qemu_irq_lower(s->irq); | ||
55 | + bool tclevel = (s->tc_int & s->tc_mask); | ||
56 | + bool errlevel = (s->err_int & s->err_mask); | ||
57 | + | ||
58 | + qemu_set_irq(s->interr, errlevel); | ||
59 | + qemu_set_irq(s->inttc, tclevel); | ||
60 | + qemu_set_irq(s->irq, errlevel || tclevel); | ||
61 | } | 45 | } |
62 | 46 | @@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr, | |
63 | static void pl080_run(PL080State *s) | 47 | break; |
64 | @@ -XXX,XX +XXX,XX @@ static void pl080_init(Object *obj) | 48 | |
65 | memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x1000); | 49 | default: |
66 | sysbus_init_mmio(sbd, &s->iomem); | 50 | - zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr); |
67 | sysbus_init_irq(sbd, &s->irq); | 51 | + qemu_log_mask(LOG_GUEST_ERROR, |
68 | + sysbus_init_irq(sbd, &s->interr); | 52 | + "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n", |
69 | + sysbus_init_irq(sbd, &s->inttc); | 53 | + addr); |
70 | s->nchannels = 8; | 54 | } |
71 | } | 55 | } |
72 | 56 | ||
73 | -- | 57 | -- |
74 | 2.18.0 | 58 | 2.20.1 |
75 | 59 | ||
76 | 60 | diff view generated by jsdifflib |
1 | The AArch32 virtualization extensions support these fault address | 1 | Instead of using printf() for logging guest accesses to invalid |
---|---|---|---|
2 | registers: | 2 | register offsets in the pxa2xx PIC device, use the usual |
3 | * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) | 3 | qemu_log_mask(LOG_GUEST_ERROR,...). |
4 | * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) | ||
5 | 4 | ||
6 | Implement the accessors for these. This fixes in passing a bug | 5 | This was the only user of the REG_FMT macro in pxa.h, so we can |
7 | where we weren't implementing the "RES0 from EL3 if EL2 not | 6 | remove that. |
8 | implemented" behaviour for AArch64 FAR_EL2. | ||
9 | 7 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
12 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
13 | Message-id: 20180814124254.5229-7-peter.maydell@linaro.org | 11 | Message-id: 20200628142429.17111-16-peter.maydell@linaro.org |
14 | --- | 12 | --- |
15 | target/arm/helper.c | 14 +++++++++++++- | 13 | include/hw/arm/pxa.h | 1 - |
16 | 1 file changed, 13 insertions(+), 1 deletion(-) | 14 | hw/arm/pxa2xx_pic.c | 9 +++++++-- |
15 | 2 files changed, 7 insertions(+), 3 deletions(-) | ||
17 | 16 | ||
18 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 17 | diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.c | 19 | --- a/include/hw/arm/pxa.h |
21 | +++ b/target/arm/helper.c | 20 | +++ b/include/hw/arm/pxa.h |
22 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | 21 | @@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState { |
23 | { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH, | ||
24 | .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3, | ||
25 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
26 | + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | ||
27 | + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | ||
28 | + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
29 | + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | ||
30 | + .type = ARM_CP_CONST, | ||
31 | + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | ||
32 | + .access = PL2_RW, .resetvalue = 0 }, | ||
33 | REGINFO_SENTINEL | ||
34 | }; | 22 | }; |
35 | 23 | ||
36 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 24 | # define PA_FMT "0x%08lx" |
37 | { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, | 25 | -# define REG_FMT "0x" TARGET_FMT_plx |
38 | .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, | 26 | |
39 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) }, | 27 | PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, |
40 | - { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64, | 28 | const char *revision); |
41 | + { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, | 29 | diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c |
42 | .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0, | 30 | index XXXXXXX..XXXXXXX 100644 |
43 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) }, | 31 | --- a/hw/arm/pxa2xx_pic.c |
44 | + { .name = "HIFAR", .state = ARM_CP_STATE_AA32, | 32 | +++ b/hw/arm/pxa2xx_pic.c |
45 | + .type = ARM_CP_ALIAS, | 33 | @@ -XXX,XX +XXX,XX @@ |
46 | + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 2, | 34 | #include "qemu/osdep.h" |
47 | + .access = PL2_RW, | 35 | #include "qapi/error.h" |
48 | + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[2]) }, | 36 | #include "qemu/module.h" |
49 | { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, | 37 | +#include "qemu/log.h" |
50 | .type = ARM_CP_ALIAS, | 38 | #include "cpu.h" |
51 | .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, | 39 | #include "hw/arm/pxa.h" |
40 | #include "hw/sysbus.h" | ||
41 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset, | ||
42 | case ICHP: /* Highest Priority register */ | ||
43 | return pxa2xx_pic_highest(s); | ||
44 | default: | ||
45 | - printf("%s: Bad register offset " REG_FMT "\n", __func__, offset); | ||
46 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
47 | + "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx | ||
48 | + "\n", offset); | ||
49 | return 0; | ||
50 | } | ||
51 | } | ||
52 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset, | ||
53 | s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f; | ||
54 | break; | ||
55 | default: | ||
56 | - printf("%s: Bad register offset " REG_FMT "\n", __func__, offset); | ||
57 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
58 | + "pxa2xx_pic_mem_write: bad register offset 0x%" | ||
59 | + HWADDR_PRIx "\n", offset); | ||
60 | return; | ||
61 | } | ||
62 | pxa2xx_pic_update(opaque); | ||
52 | -- | 63 | -- |
53 | 2.18.0 | 64 | 2.20.1 |
54 | 65 | ||
55 | 66 | diff view generated by jsdifflib |
1 | ARMCPRegInfo structs will default to .cp = 15 if they | 1 | The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the |
---|---|---|---|
2 | are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32 | 2 | usual QOM TYPE and casting macros; provide and use them. |
3 | (because a coprocessor number of 0 is valid for AArch32). | 3 | |
4 | We forgot to explicitly set .cp = 15 for the HMAIR1 and | 4 | In particular, we can safely use the QOM cast macros instead of |
5 | HAMAIR1 regdefs, which meant they would UNDEF when the guest | 5 | FROM_SSI_SLAVE() because in both cases the 'ssidev' field of |
6 | tried to access them under cp15. | 6 | the instance state struct is the first field in it. |
7 | 7 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
11 | Message-id: 20180814124254.5229-3-peter.maydell@linaro.org | 11 | Message-id: 20200628142429.17111-17-peter.maydell@linaro.org |
12 | --- | 12 | --- |
13 | target/arm/helper.c | 8 ++++---- | 13 | hw/arm/spitz.c | 23 +++++++++++++++-------- |
14 | 1 file changed, 4 insertions(+), 4 deletions(-) | 14 | 1 file changed, 15 insertions(+), 8 deletions(-) |
15 | 15 | ||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 16 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper.c | 18 | --- a/hw/arm/spitz.c |
19 | +++ b/target/arm/helper.c | 19 | +++ b/hw/arm/spitz.c |
20 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | 20 | @@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp) |
21 | .access = PL2_RW, .type = ARM_CP_CONST, | 21 | #define LCDTG_PICTRL 0x06 |
22 | .resetvalue = 0 }, | 22 | #define LCDTG_POLCTRL 0x07 |
23 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | 23 | |
24 | - .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | 24 | +#define TYPE_SPITZ_LCDTG "spitz-lcdtg" |
25 | + .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | 25 | +#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG) |
26 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | 26 | + |
27 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, | 27 | typedef struct { |
28 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | 28 | SSISlave ssidev; |
29 | .access = PL2_RW, .type = ARM_CP_CONST, | 29 | uint32_t bl_intensity; |
30 | .resetvalue = 0 }, | 30 | @@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level) |
31 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | 31 | |
32 | - .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | 32 | static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) |
33 | + .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | 33 | { |
34 | .access = PL2_RW, .type = ARM_CP_CONST, | 34 | - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev); |
35 | .resetvalue = 0 }, | 35 | + SpitzLCDTG *s = SPITZ_LCDTG(dev); |
36 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, | 36 | int addr; |
37 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 37 | addr = value >> 5; |
38 | .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), | 38 | value &= 0x1f; |
39 | .resetvalue = 0 }, | 39 | @@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value) |
40 | { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | 40 | |
41 | - .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | 41 | static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) |
42 | + .cp = 15, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1, | 42 | { |
43 | .access = PL2_RW, .type = ARM_CP_ALIAS, | 43 | - SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi); |
44 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, | 44 | + SpitzLCDTG *s = SPITZ_LCDTG(ssi); |
45 | { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH, | 45 | DeviceState *dev = DEVICE(s); |
46 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 46 | |
47 | .resetvalue = 0 }, | 47 | s->bl_power = 0; |
48 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | 48 | @@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp) |
49 | { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | 49 | #define SPITZ_GPIO_MAX1111_CS 20 |
50 | - .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | 50 | #define SPITZ_GPIO_TP_INT 11 |
51 | + .cp = 15, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | 51 | |
52 | .access = PL2_RW, .type = ARM_CP_CONST, | 52 | +#define TYPE_CORGI_SSP "corgi-ssp" |
53 | .resetvalue = 0 }, | 53 | +#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP) |
54 | { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH, | 54 | + |
55 | /* "Demux" the signal based on current chipselect */ | ||
56 | typedef struct { | ||
57 | SSISlave ssidev; | ||
58 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
59 | |||
60 | static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value) | ||
61 | { | ||
62 | - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev); | ||
63 | + CorgiSSPState *s = CORGI_SSP(dev); | ||
64 | int i; | ||
65 | |||
66 | for (i = 0; i < 3; i++) { | ||
67 | @@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level) | ||
68 | static void corgi_ssp_realize(SSISlave *d, Error **errp) | ||
69 | { | ||
70 | DeviceState *dev = DEVICE(d); | ||
71 | - CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d); | ||
72 | + CorgiSSPState *s = CORGI_SSP(d); | ||
73 | |||
74 | qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3); | ||
75 | s->bus[0] = ssi_create_bus(dev, "ssi0"); | ||
76 | @@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms) | ||
77 | { | ||
78 | void *bus; | ||
79 | |||
80 | - sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp"); | ||
81 | + sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], | ||
82 | + TYPE_CORGI_SSP); | ||
83 | |||
84 | bus = qdev_get_child_bus(sms->mux, "ssi0"); | ||
85 | - sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg"); | ||
86 | + sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG); | ||
87 | |||
88 | bus = qdev_get_child_bus(sms->mux, "ssi1"); | ||
89 | sms->ads7846 = ssi_create_slave(bus, "ads7846"); | ||
90 | @@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data) | ||
91 | } | ||
92 | |||
93 | static const TypeInfo corgi_ssp_info = { | ||
94 | - .name = "corgi-ssp", | ||
95 | + .name = TYPE_CORGI_SSP, | ||
96 | .parent = TYPE_SSI_SLAVE, | ||
97 | .instance_size = sizeof(CorgiSSPState), | ||
98 | .class_init = corgi_ssp_class_init, | ||
99 | @@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data) | ||
100 | } | ||
101 | |||
102 | static const TypeInfo spitz_lcdtg_info = { | ||
103 | - .name = "spitz-lcdtg", | ||
104 | + .name = TYPE_SPITZ_LCDTG, | ||
105 | .parent = TYPE_SSI_SLAVE, | ||
106 | .instance_size = sizeof(SpitzLCDTG), | ||
107 | .class_init = spitz_lcdtg_class_init, | ||
55 | -- | 108 | -- |
56 | 2.18.0 | 109 | 2.20.1 |
57 | 110 | ||
58 | 111 | diff view generated by jsdifflib |
1 | Move the m48t59 device away from using old_mmio MemoryRegionOps | 1 | The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way |
---|---|---|---|
2 | accessors. | 2 | to cast from an SSISlave* to the instance struct of a subtype of |
3 | TYPE_SSI_SLAVE. Switch to using the QOM cast macros instead, which | ||
4 | have the same effect (by writing the QOM macros if the types were | ||
5 | previously missing them.) | ||
6 | |||
7 | (The FROM_SSI_SLAVE() macro allows the SSISlave member of the | ||
8 | subtype's struct to be anywhere as long as it is named "ssidev", | ||
9 | whereas a QOM cast macro insists that it is the first thing in the | ||
10 | subtype's struct. This is true for all the types we convert here.) | ||
11 | |||
12 | This removes all the uses of FROM_SSI_SLAVE() so we can delete the | ||
13 | definition. | ||
3 | 14 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 16 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 17 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
7 | Message-id: 20180802180602.22047-1-peter.maydell@linaro.org | 18 | Message-id: 20200628142429.17111-18-peter.maydell@linaro.org |
8 | --- | 19 | --- |
9 | hw/timer/m48t59.c | 59 +++++++++-------------------------------------- | 20 | include/hw/ssi/ssi.h | 2 -- |
10 | 1 file changed, 11 insertions(+), 48 deletions(-) | 21 | hw/arm/z2.c | 11 +++++++---- |
22 | hw/display/ads7846.c | 9 ++++++--- | ||
23 | hw/display/ssd0323.c | 10 +++++++--- | ||
24 | hw/sd/ssi-sd.c | 4 ++-- | ||
25 | 5 files changed, 22 insertions(+), 14 deletions(-) | ||
11 | 26 | ||
12 | diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c | 27 | diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h |
13 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/timer/m48t59.c | 29 | --- a/include/hw/ssi/ssi.h |
15 | +++ b/hw/timer/m48t59.c | 30 | +++ b/include/hw/ssi/ssi.h |
16 | @@ -XXX,XX +XXX,XX @@ static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) | 31 | @@ -XXX,XX +XXX,XX @@ struct SSISlave { |
17 | return retval; | 32 | bool cs; |
33 | }; | ||
34 | |||
35 | -#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) | ||
36 | - | ||
37 | extern const VMStateDescription vmstate_ssi_slave; | ||
38 | |||
39 | #define VMSTATE_SSI_SLAVE(_field, _state) { \ | ||
40 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/z2.c | ||
43 | +++ b/hw/arm/z2.c | ||
44 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
45 | int pos; | ||
46 | } ZipitLCD; | ||
47 | |||
48 | +#define TYPE_ZIPIT_LCD "zipit-lcd" | ||
49 | +#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD) | ||
50 | + | ||
51 | static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value) | ||
52 | { | ||
53 | - ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev); | ||
54 | + ZipitLCD *z = ZIPIT_LCD(dev); | ||
55 | uint16_t val; | ||
56 | if (z->selected) { | ||
57 | z->buf[z->pos] = value & 0xff; | ||
58 | @@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level) | ||
59 | |||
60 | static void zipit_lcd_realize(SSISlave *dev, Error **errp) | ||
61 | { | ||
62 | - ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev); | ||
63 | + ZipitLCD *z = ZIPIT_LCD(dev); | ||
64 | z->selected = 0; | ||
65 | z->enabled = 0; | ||
66 | z->pos = 0; | ||
67 | @@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data) | ||
18 | } | 68 | } |
19 | 69 | ||
20 | -static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) | 70 | static const TypeInfo zipit_lcd_info = { |
21 | -{ | 71 | - .name = "zipit-lcd", |
22 | - M48t59State *NVRAM = opaque; | 72 | + .name = TYPE_ZIPIT_LCD, |
23 | - | 73 | .parent = TYPE_SSI_SLAVE, |
24 | - m48t59_write(NVRAM, addr, value & 0xff); | 74 | .instance_size = sizeof(ZipitLCD), |
25 | -} | 75 | .class_init = zipit_lcd_class_init, |
26 | - | 76 | @@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine) |
27 | -static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) | 77 | |
28 | -{ | 78 | type_register_static(&zipit_lcd_info); |
29 | - M48t59State *NVRAM = opaque; | 79 | type_register_static(&aer915_info); |
30 | - | 80 | - z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd"); |
31 | - m48t59_write(NVRAM, addr, (value >> 8) & 0xff); | 81 | + z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD); |
32 | - m48t59_write(NVRAM, addr + 1, value & 0xff); | 82 | bus = pxa2xx_i2c_bus(mpu->i2c[0]); |
33 | -} | 83 | i2c_create_slave(bus, TYPE_AER915, 0x55); |
34 | - | 84 | wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b); |
35 | -static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) | 85 | diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c |
36 | -{ | 86 | index XXXXXXX..XXXXXXX 100644 |
37 | - M48t59State *NVRAM = opaque; | 87 | --- a/hw/display/ads7846.c |
38 | - | 88 | +++ b/hw/display/ads7846.c |
39 | - m48t59_write(NVRAM, addr, (value >> 24) & 0xff); | 89 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
40 | - m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); | 90 | int output; |
41 | - m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); | 91 | } ADS7846State; |
42 | - m48t59_write(NVRAM, addr + 3, value & 0xff); | 92 | |
43 | -} | 93 | +#define TYPE_ADS7846 "ads7846" |
44 | - | 94 | +#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846) |
45 | -static uint32_t nvram_readb (void *opaque, hwaddr addr) | 95 | + |
46 | +static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size) | 96 | /* Control-byte bitfields */ |
97 | #define CB_PD0 (1 << 0) | ||
98 | #define CB_PD1 (1 << 1) | ||
99 | @@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s) | ||
100 | |||
101 | static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value) | ||
47 | { | 102 | { |
48 | M48t59State *NVRAM = opaque; | 103 | - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev); |
49 | 104 | + ADS7846State *s = ADS7846(dev); | |
50 | return m48t59_read(NVRAM, addr); | 105 | |
106 | switch (s->cycle ++) { | ||
107 | case 0: | ||
108 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = { | ||
109 | static void ads7846_realize(SSISlave *d, Error **errp) | ||
110 | { | ||
111 | DeviceState *dev = DEVICE(d); | ||
112 | - ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d); | ||
113 | + ADS7846State *s = ADS7846(d); | ||
114 | |||
115 | qdev_init_gpio_out(dev, &s->interrupt, 1); | ||
116 | |||
117 | @@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data) | ||
51 | } | 118 | } |
52 | 119 | ||
53 | -static uint32_t nvram_readw (void *opaque, hwaddr addr) | 120 | static const TypeInfo ads7846_info = { |
54 | +static void nvram_write(void *opaque, hwaddr addr, uint64_t value, | 121 | - .name = "ads7846", |
55 | + unsigned size) | 122 | + .name = TYPE_ADS7846, |
123 | .parent = TYPE_SSI_SLAVE, | ||
124 | .instance_size = sizeof(ADS7846State), | ||
125 | .class_init = ads7846_class_init, | ||
126 | diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c | ||
127 | index XXXXXXX..XXXXXXX 100644 | ||
128 | --- a/hw/display/ssd0323.c | ||
129 | +++ b/hw/display/ssd0323.c | ||
130 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
131 | uint8_t framebuffer[128 * 80 / 2]; | ||
132 | } ssd0323_state; | ||
133 | |||
134 | +#define TYPE_SSD0323 "ssd0323" | ||
135 | +#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323) | ||
136 | + | ||
137 | + | ||
138 | static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data) | ||
56 | { | 139 | { |
57 | M48t59State *NVRAM = opaque; | 140 | - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev); |
58 | - uint32_t retval; | 141 | + ssd0323_state *s = SSD0323(dev); |
59 | 142 | ||
60 | - retval = m48t59_read(NVRAM, addr) << 8; | 143 | switch (s->mode) { |
61 | - retval |= m48t59_read(NVRAM, addr + 1); | 144 | case SSD0323_DATA: |
62 | - return retval; | 145 | @@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = { |
63 | -} | 146 | static void ssd0323_realize(SSISlave *d, Error **errp) |
64 | - | 147 | { |
65 | -static uint32_t nvram_readl (void *opaque, hwaddr addr) | 148 | DeviceState *dev = DEVICE(d); |
66 | -{ | 149 | - ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d); |
67 | - M48t59State *NVRAM = opaque; | 150 | + ssd0323_state *s = SSD0323(d); |
68 | - uint32_t retval; | 151 | |
69 | - | 152 | s->col_end = 63; |
70 | - retval = m48t59_read(NVRAM, addr) << 24; | 153 | s->row_end = 79; |
71 | - retval |= m48t59_read(NVRAM, addr + 1) << 16; | 154 | @@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data) |
72 | - retval |= m48t59_read(NVRAM, addr + 2) << 8; | ||
73 | - retval |= m48t59_read(NVRAM, addr + 3); | ||
74 | - return retval; | ||
75 | + return m48t59_write(NVRAM, addr, value); | ||
76 | } | 155 | } |
77 | 156 | ||
78 | static const MemoryRegionOps nvram_ops = { | 157 | static const TypeInfo ssd0323_info = { |
79 | - .old_mmio = { | 158 | - .name = "ssd0323", |
80 | - .read = { nvram_readb, nvram_readw, nvram_readl, }, | 159 | + .name = TYPE_SSD0323, |
81 | - .write = { nvram_writeb, nvram_writew, nvram_writel, }, | 160 | .parent = TYPE_SSI_SLAVE, |
82 | - }, | 161 | .instance_size = sizeof(ssd0323_state), |
83 | - .endianness = DEVICE_NATIVE_ENDIAN, | 162 | .class_init = ssd0323_class_init, |
84 | + .read = nvram_read, | 163 | diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c |
85 | + .write = nvram_write, | 164 | index XXXXXXX..XXXXXXX 100644 |
86 | + .impl.min_access_size = 1, | 165 | --- a/hw/sd/ssi-sd.c |
87 | + .impl.max_access_size = 1, | 166 | +++ b/hw/sd/ssi-sd.c |
88 | + .valid.min_access_size = 1, | 167 | @@ -XXX,XX +XXX,XX @@ typedef struct { |
89 | + .valid.max_access_size = 4, | 168 | |
90 | + .endianness = DEVICE_BIG_ENDIAN, | 169 | static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val) |
91 | }; | 170 | { |
92 | 171 | - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev); | |
93 | static const VMStateDescription vmstate_m48t59 = { | 172 | + ssi_sd_state *s = SSI_SD(dev); |
173 | |||
174 | /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */ | ||
175 | if (s->mode == SSI_SD_DATA_READ && val == 0x4d) { | ||
176 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = { | ||
177 | |||
178 | static void ssi_sd_realize(SSISlave *d, Error **errp) | ||
179 | { | ||
180 | - ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d); | ||
181 | + ssi_sd_state *s = SSI_SD(d); | ||
182 | DeviceState *carddev; | ||
183 | DriveInfo *dinfo; | ||
184 | Error *err = NULL; | ||
94 | -- | 185 | -- |
95 | 2.18.0 | 186 | 2.20.1 |
96 | 187 | ||
97 | 188 | diff view generated by jsdifflib |
1 | We implement the HAMAIR1 register as RAZ/WI; we had a typo in the | 1 | Deprecate our TileGX target support: |
---|---|---|---|
2 | regdef, though, and were incorrectly naming it HMAIR1 (which is | 2 | * we have no active maintainer for it |
3 | a different register which we also implement as RAZ/WI). | 3 | * it has had essentially no contributions (other than tree-wide cleanups |
4 | and similar) since it was first added | ||
5 | * the Linux kernel dropped support in 2018, as has glibc | ||
6 | |||
7 | Note the deprecation in the manual, but don't try to print a warning | ||
8 | when QEMU runs -- printing unsuppressable messages is more obtrusive | ||
9 | for linux-user mode than it would be for system-emulation mode, and | ||
10 | it doesn't seem worth trying to invent a new suppressible-error | ||
11 | system for linux-user just for this. | ||
4 | 12 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 14 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
7 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Message-id: 20180814124254.5229-2-peter.maydell@linaro.org | 16 | Reviewed-by: Thomas Huth <thuth@redhat.com> |
17 | Message-id: 20200619154831.26319-1-peter.maydell@linaro.org | ||
9 | --- | 18 | --- |
10 | target/arm/helper.c | 4 ++-- | 19 | docs/system/deprecated.rst | 11 +++++++++++ |
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | 20 | 1 file changed, 11 insertions(+) |
12 | 21 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 22 | diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst |
14 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 24 | --- a/docs/system/deprecated.rst |
16 | +++ b/target/arm/helper.c | 25 | +++ b/docs/system/deprecated.rst |
17 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { | 26 | @@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format:: |
18 | .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0, | 27 | |
19 | .access = PL2_RW, .type = ARM_CP_CONST, | 28 | json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"} |
20 | .resetvalue = 0 }, | 29 | |
21 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | 30 | +linux-user mode CPUs |
22 | + { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | 31 | +-------------------- |
23 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | 32 | + |
24 | .access = PL2_RW, .type = ARM_CP_CONST, | 33 | +``tilegx`` CPUs (since 5.1.0) |
25 | .resetvalue = 0 }, | 34 | +''''''''''''''''''''''''''''' |
26 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = { | 35 | + |
27 | .access = PL2_RW, .type = ARM_CP_CONST, | 36 | +The ``tilegx`` guest CPU support (which was only implemented in |
28 | .resetvalue = 0 }, | 37 | +linux-user mode) is deprecated and will be removed in a future version |
29 | /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ | 38 | +of QEMU. Support for this CPU was removed from the upstream Linux |
30 | - { .name = "HMAIR1", .state = ARM_CP_STATE_AA32, | 39 | +kernel in 2018, and has also been dropped from glibc. |
31 | + { .name = "HAMAIR1", .state = ARM_CP_STATE_AA32, | 40 | + |
32 | .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1, | 41 | Related binaries |
33 | .access = PL2_RW, .type = ARM_CP_CONST, | 42 | ---------------- |
34 | .resetvalue = 0 }, | 43 | |
35 | -- | 44 | -- |
36 | 2.18.0 | 45 | 2.20.1 |
37 | 46 | ||
38 | 47 | diff view generated by jsdifflib |