[Qemu-devel] [PULL 00/30] target-arm queue
[PULL 00/16] target-arm queue
1
Less than a day of post-3.0 code review and already enough
1
Patches for rc1: nothing major, just some minor bugfixes and
2
patches for another pullreq :-)
2
code cleanups.
3
3
4
thanks
5
-- PMM
4
-- PMM
6
5
7
The following changes since commit c542a9f9794ec8e0bc3fcf5956d3cc8bce667789:
6
The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:
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7
9
Merge remote-tracking branch 'remotes/armbru/tags/pull-tests-2018-08-16' into staging (2018-08-16 09:50:54 +0100)
8
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180816
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110
14
13
15
for you to fetch changes up to fcf13ca556f462b52956059bf8fa622bc8575edb:
14
for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:
16
15
17
hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() (2018-08-16 14:29:58 +0100)
16
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* Fixes for various bugs in SVE instructions
20
* hw/arm/Kconfig: ARM_V7M depends on PTIMER
22
* Add model of Freescale i.MX6 UltraLite 14x14 EVK Board
21
* Minor coding style fixes
23
* hw/arm: make bitbanded IO optional on ARMv7-M
22
* docs: add some notes on the sbsa-ref machine
24
* Add model of Cortex-M0 CPU
23
* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
25
* Add support for loading Intel HEX files to the generic loader
24
* target/arm: Fix neon VTBL/VTBX for len > 1
26
* imx_spi: Unset XCH when TX FIFO becomes empty
25
* hw/arm/armsse: Correct expansion MPC interrupt lines
27
* aspeed_sdmc: fix various bugs
26
* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
28
* Fix bugs in Arm FP16 instruction support
27
* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
29
* Fix aa64 FCADD and FCMLA decode
28
* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
30
* softfloat: Fix missing inexact for floating-point add
29
* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
31
* hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
30
* hw/arm/nseries: Check return value from load_image_targphys()
31
* tests/qtest/npcm7xx_rng-test: count runs properly
32
* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
32
33
33
----------------------------------------------------------------
34
----------------------------------------------------------------
34
Cédric Le Goater (1):
35
Alex Bennée (1):
35
aspeed: add a max_ram_size property to the memory controller
36
docs: add some notes on the sbsa-ref machine
36
37
37
Jean-Christophe Dubois (3):
38
AlexChen (1):
38
i.MX6UL: Add i.MX6UL specific CCM device
39
ssi: Fix bad printf format specifiers
39
i.MX6UL: Add i.MX6UL SOC
40
i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board
41
40
42
Joel Stanley (5):
41
Andrew Jones (1):
43
aspeed_sdmc: Extend number of valid registers
42
hw/arm/Kconfig: ARM_V7M depends on PTIMER
44
aspeed_sdmc: Fix saved values
45
aspeed_sdmc: Set 'cache initial sequence' always true
46
aspeed_sdmc: Init status always idle
47
aspeed_sdmc: Handle ECC training
48
43
49
Richard Henderson (13):
44
Havard Skinnemoen (1):
50
target/arm: Fix typo in helper_sve_ld1hss_r
45
tests/qtest/npcm7xx_rng-test: count runs properly
51
target/arm: Fix sign-extension in sve do_ldr/do_str
52
target/arm: Fix offset for LD1R instructions
53
target/arm: Fix offset scaling for LD_zprr and ST_zprr
54
target/arm: Reformat integer register dump
55
target/arm: Dump SVE state if enabled
56
target/arm: Add sve-max-vq cpu property to -cpu max
57
target/arm: Adjust FPCR_MASK for FZ16
58
target/arm: Ignore float_flag_input_denormal from fp_status_f16
59
target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
60
target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
61
target/arm: Fix aa64 FCADD and FCMLA decode
62
softfloat: Fix missing inexact for floating-point add
63
46
64
Stefan Hajnoczi (4):
47
Peter Maydell (2):
65
hw/arm: make bitbanded IO optional on ARMv7-M
48
hw/arm/nseries: Check return value from load_image_targphys()
66
target/arm: add "cortex-m0" CPU model
49
target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
67
loader: extract rom_free() function
68
loader: add rom transaction API
69
50
70
Su Hang (2):
51
Philippe Mathieu-Daudé (6):
71
loader: Implement .hex file loader
52
hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
72
Add QTest testcase for the Intel Hexadecimal
53
hw/arm/armsse: Correct expansion MPC interrupt lines
54
hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
55
hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
56
hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
57
hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
73
58
74
Thomas Huth (1):
59
Richard Henderson (1):
75
hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
60
target/arm: Fix neon VTBL/VTBX for len > 1
76
61
77
Trent Piepho (1):
62
Xinhao Zhang (3):
78
imx_spi: Unset XCH when TX FIFO becomes empty
63
target/arm: add spaces around operator
64
target/arm: Don't use '#' flag of printf format
65
target/arm: add space before the open parenthesis '('
79
66
80
configure | 4 +
67
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++
81
hw/arm/Makefile.objs | 1 +
68
docs/system/target-arm.rst | 1 +
82
hw/misc/Makefile.objs | 1 +
69
include/hw/misc/stm32f2xx_syscfg.h | 2 --
83
tests/Makefile.include | 2 +
70
target/arm/helper.h | 2 +-
84
include/hw/arm/armv7m.h | 2 +
71
hw/arm/armsse.c | 3 +-
85
include/hw/arm/fsl-imx6ul.h | 339 ++++++++++++++
72
hw/arm/musicpal.c | 40 +++++++++++++++++----------
86
include/hw/loader.h | 31 ++
73
hw/arm/nseries.c | 26 ++++++++----------
87
include/hw/misc/aspeed_sdmc.h | 4 +-
74
hw/arm/stm32f205_soc.c | 1 -
88
include/hw/misc/imx6ul_ccm.h | 226 +++++++++
75
hw/misc/stm32f2xx_syscfg.c | 2 --
89
target/arm/cpu.h | 5 +-
76
hw/ssi/imx_spi.c | 2 +-
90
fpu/softfloat.c | 2 +-
77
hw/ssi/xilinx_spi.c | 2 +-
91
hw/arm/armv7m.c | 37 +-
78
target/arm/arch_dump.c | 8 +++---
92
hw/arm/aspeed.c | 31 ++
79
target/arm/arm-semi.c | 8 +++---
93
hw/arm/aspeed_soc.c | 2 +
80
target/arm/helper.c | 2 +-
94
hw/arm/fsl-imx6ul.c | 617 ++++++++++++++++++++++++
81
target/arm/op_helper.c | 23 +++++++++-------
95
hw/arm/mcimx6ul-evk.c | 85 ++++
82
target/arm/translate-a64.c | 4 +--
96
hw/arm/mps2-tz.c | 32 +-
83
target/arm/translate.c | 2 +-
97
hw/arm/mps2.c | 1 +
84
tests/qtest/npcm7xx_rng-test.c | 2 +-
98
hw/arm/msf2-soc.c | 1 +
85
hw/arm/Kconfig | 3 +-
99
hw/arm/stellaris.c | 1 +
86
target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------
100
hw/arm/stm32f205_soc.c | 1 +
87
20 files changed, 123 insertions(+), 98 deletions(-)
101
hw/core/generic-loader.c | 4 +
88
create mode 100644 docs/system/arm/sbsa.rst
102
hw/core/loader.c | 302 +++++++++++-
103
hw/misc/aspeed_sdmc.c | 55 ++-
104
hw/misc/imx6ul_ccm.c | 886 +++++++++++++++++++++++++++++++++++
105
hw/ssi/imx_spi.c | 3 +-
106
linux-user/syscall.c | 19 +-
107
target/arm/cpu.c | 17 +-
108
target/arm/cpu64.c | 29 ++
109
target/arm/helper.c | 18 +-
110
target/arm/sve_helper.c | 4 +-
111
target/arm/translate-a64.c | 120 ++++-
112
target/arm/translate-sve.c | 30 +-
113
tests/hexloader-test.c | 45 ++
114
MAINTAINERS | 6 +
115
default-configs/arm-softmmu.mak | 1 +
116
hw/misc/trace-events | 7 +
117
tests/hex-loader-check-data/test.hex | 18 +
118
38 files changed, 2863 insertions(+), 126 deletions(-)
119
create mode 100644 include/hw/arm/fsl-imx6ul.h
120
create mode 100644 include/hw/misc/imx6ul_ccm.h
121
create mode 100644 hw/arm/fsl-imx6ul.c
122
create mode 100644 hw/arm/mcimx6ul-evk.c
123
create mode 100644 hw/misc/imx6ul_ccm.c
124
create mode 100644 tests/hexloader-test.c
125
create mode 100644 tests/hex-loader-check-data/test.hex
126
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/30] aspeed_sdmc: Set 'cache initial sequence' always true
[PULL 01/16] hw/arm/Kconfig: ARM_V7M depends on PTIMER
1
From: Joel Stanley <joel@jms.id.au>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
The SDRAM training routine sets the 'Enable cache initial' bit, and then
3
commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers")
4
waits for the 'cache initial sequence' to be done.
4
changed armv7m_systick to build on ptimers. Make sure we have ptimers
5
in the build when building armv7m_systick.
5
6
6
Have it always return done, as there is no other side effects that the
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
model needs to implement. This allows the upstream u-boot training to
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
proceed on the ast2500-evb board.
9
Message-id: 20201104103343.30392-1-drjones@redhat.com
9
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Tested-by: Cédric Le Goater <clg@kaod.org>
13
Message-id: 20180807075757.7242-4-joel@jms.id.au
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
11
---
16
hw/misc/aspeed_sdmc.c | 1 +
12
hw/arm/Kconfig | 1 +
17
1 file changed, 1 insertion(+)
13
1 file changed, 1 insertion(+)
18
14
19
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
15
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/aspeed_sdmc.c
17
--- a/hw/arm/Kconfig
22
+++ b/hw/misc/aspeed_sdmc.c
18
+++ b/hw/arm/Kconfig
23
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@ config ZYNQ
24
s->ram_bits = ast2500_rambits(s);
20
25
s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
21
config ARM_V7M
26
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
22
bool
27
+ ASPEED_SDMC_CACHE_INITIAL_DONE |
23
+ select PTIMER
28
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
24
29
break;
25
config ALLWINNER_A10
30
default:
26
bool
31
--
27
--
32
2.18.0
28
2.20.1
33
29
34
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/30] imx_spi: Unset XCH when TX FIFO becomes empty
[PULL 02/16] ssi: Fix bad printf format specifiers
1
From: Trent Piepho <tpiepho@impinj.com>
1
From: AlexChen <alex.chen@huawei.com>
2
2
3
The current emulation will clear the XCH bit when a burst finishes.
3
We should use printf format specifier "%u" instead of "%d" for
4
This is not quite correct. According to the i.MX7d referemce manual,
4
argument of type "unsigned int".
5
Rev 0.1, §10.1.7.3:
6
5
7
This bit [XCH] is cleared automatically when all data in the TXFIFO
6
Reported-by: Euler Robot <euler.robot@huawei.com>
8
and the shift register has been shifted out.
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
9
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
So XCH should be cleared when the FIFO empties, not on completion of a
9
Message-id: 5FA280F5.8060902@huawei.com
11
burst. The FIFO is 64 x 32 bits = 2048 bits, while the max burst size
12
is larger at 4096 bits. So it's possible that the burst is not finished
13
after the TXFIFO empties.
14
15
Sending a large block (> 2048 bits) with the Linux driver will use a
16
burst that is larger than the TXFIFO. After the TXFIFO has emptied XCH
17
does not become unset, as the burst is not yet finished.
18
19
What should happen after the TXFIFO empties is the driver will refill it
20
and set XCH. The rising edge of XCH will trigger another transfer to
21
begin. However, since the emulation does not set XCH to 0, there is no
22
rising edge and the next trasfer never begins.
23
24
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
25
Message-id: 20180731201056.29257-1-tpiepho@impinj.com
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
11
---
29
hw/ssi/imx_spi.c | 3 +--
12
hw/ssi/imx_spi.c | 2 +-
30
1 file changed, 1 insertion(+), 2 deletions(-)
13
hw/ssi/xilinx_spi.c | 2 +-
14
2 files changed, 2 insertions(+), 2 deletions(-)
31
15
32
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
16
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
33
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/ssi/imx_spi.c
18
--- a/hw/ssi/imx_spi.c
35
+++ b/hw/ssi/imx_spi.c
19
+++ b/hw/ssi/imx_spi.c
36
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
20
@@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg)
37
}
21
case ECSPI_MSGDATA:
38
22
return "ECSPI_MSGDATA";
39
if (s->burst_length <= 0) {
23
default:
40
- s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
24
- sprintf(unknown, "%d ?", reg);
41
-
25
+ sprintf(unknown, "%u ?", reg);
42
if (!imx_spi_is_multiple_master_burst(s)) {
26
return unknown;
43
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
44
break;
45
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
46
47
if (fifo32_is_empty(&s->tx_fifo)) {
48
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
49
+ s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
50
}
27
}
51
28
}
52
/* TODO: We should also use TDR and RDR bits */
29
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/ssi/xilinx_spi.c
32
+++ b/hw/ssi/xilinx_spi.c
33
@@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s)
34
irq chain unless things really changed. */
35
if (pending != s->irqline) {
36
s->irqline = pending;
37
- DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
38
+ DB_PRINT("irq_change of state %u ISR:%x IER:%X\n",
39
pending, s->regs[R_IPISR], s->regs[R_IPIER]);
40
qemu_set_irq(s->irq, pending);
41
}
53
--
42
--
54
2.18.0
43
2.20.1
55
44
56
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/30] target/arm: Ignore float_flag_input_denormal from fp_status_f16
[PULL 03/16] target/arm: add spaces around operator
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
When FZ is set, input_denormal exceptions are recognized, but this does
3
Fix code style. Operator needs spaces both sides.
4
not happen with FZ16. The softfloat code has no way to distinguish
5
these bits and will raise such exceptions into fp_status_f16.flags,
6
so ignore them when computing the accumulated flags.
7
4
8
Cc: qemu-stable@nongnu.org (3.0.1)
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com
11
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
13
Message-id: 20180810193129.1556-3-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
10
---
16
target/arm/helper.c | 6 +++++-
11
target/arm/arch_dump.c | 8 ++++----
17
1 file changed, 5 insertions(+), 1 deletion(-)
12
target/arm/arm-semi.c | 8 ++++----
13
target/arm/helper.c | 2 +-
14
3 files changed, 9 insertions(+), 9 deletions(-)
18
15
16
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/arch_dump.c
19
+++ b/target/arm/arch_dump.c
20
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
21
22
for (i = 0; i < 32; ++i) {
23
uint64_t *q = aa64_vfp_qreg(env, i);
24
- note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]);
25
- note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]);
26
+ note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]);
27
+ note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]);
28
}
29
30
if (s->dump_info.d_endian == ELFDATA2MSB) {
31
@@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
32
*/
33
for (i = 0; i < 32; ++i) {
34
uint64_t tmp = note.vfp.vregs[2*i];
35
- note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1];
36
- note.vfp.vregs[2*i+1] = tmp;
37
+ note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1];
38
+ note.vfp.vregs[2 * i + 1] = tmp;
39
}
40
}
41
42
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/arm-semi.c
45
+++ b/target/arm/arm-semi.c
46
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
47
if (use_gdb_syscalls()) {
48
arm_semi_open_guestfd = guestfd;
49
ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0,
50
- (int)arg2+1, gdb_open_modeflags[arg1]);
51
+ (int)arg2 + 1, gdb_open_modeflags[arg1]);
52
} else {
53
ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644));
54
if (ret == (uint32_t)-1) {
55
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
56
GET_ARG(1);
57
if (use_gdb_syscalls()) {
58
ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s",
59
- arg0, (int)arg1+1);
60
+ arg0, (int)arg1 + 1);
61
} else {
62
s = lock_user_string(arg0);
63
if (!s) {
64
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
65
GET_ARG(3);
66
if (use_gdb_syscalls()) {
67
return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s",
68
- arg0, (int)arg1+1, arg2, (int)arg3+1);
69
+ arg0, (int)arg1 + 1, arg2, (int)arg3 + 1);
70
} else {
71
char *s2;
72
s = lock_user_string(arg0);
73
@@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env)
74
GET_ARG(1);
75
if (use_gdb_syscalls()) {
76
return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s",
77
- arg0, (int)arg1+1);
78
+ arg0, (int)arg1 + 1);
79
} else {
80
s = lock_user_string(arg0);
81
if (!s) {
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
83
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
84
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
85
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
86
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
24
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
87
uint32_t sum;
25
| (env->vfp.vec_len << 16)
88
sum = do_usad(a, b);
26
| (env->vfp.vec_stride << 20);
89
sum += do_usad(a >> 8, b >> 8);
27
+
90
- sum += do_usad(a >> 16, b >>16);
28
i = get_float_exception_flags(&env->vfp.fp_status);
91
+ sum += do_usad(a >> 16, b >> 16);
29
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
92
sum += do_usad(a >> 24, b >> 24);
30
- i |= get_float_exception_flags(&env->vfp.fp_status_f16);
93
return sum;
31
+ /* FZ16 does not generate an input denormal exception. */
32
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
33
+ & ~float_flag_input_denormal);
34
+
35
fpscr |= vfp_exceptbits_from_host(i);
36
return fpscr;
37
}
94
}
38
--
95
--
39
2.18.0
96
2.20.1
40
97
41
98
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/30] target/arm: Reformat integer register dump
[PULL 04/16] target/arm: Don't use '#' flag of printf format
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
With PC, there are 33 registers. Three per line lines up nicely
3
Fix code style. Don't use '#' flag of printf format ('%#') in
4
without overflowing 80 columns.
4
format strings, use '0x' prefix instead
5
5
6
Cc: qemu-stable@nongnu.org (3.0.1)
6
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 13 ++++++-------
12
target/arm/translate-a64.c | 4 ++--
12
1 file changed, 6 insertions(+), 7 deletions(-)
13
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
19
int el = arm_current_el(env);
20
gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
20
const char *ns_status;
21
break;
21
22
default:
22
- cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
23
- fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
23
- env->pc, env->xregs[31]);
24
+ fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n",
24
- for (i = 0; i < 31; i++) {
25
__func__, insn, fpopcode, s->pc_curr);
25
- cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
26
g_assert_not_reached();
26
- if ((i % 4) == 3) {
27
}
27
- cpu_fprintf(f, "\n");
28
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
28
+ cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
29
case 0x7f: /* FSQRT (vector) */
29
+ for (i = 0; i < 32; i++) {
30
break;
30
+ if (i == 31) {
31
default:
31
+ cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
32
- fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
32
} else {
33
+ fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop);
33
- cpu_fprintf(f, " ");
34
g_assert_not_reached();
34
+ cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
35
+ (i + 2) % 3 ? " " : "\n");
36
}
37
}
35
}
38
36
39
--
37
--
40
2.18.0
38
2.20.1
41
39
42
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/30] softfloat: Fix missing inexact for floating-point add
[PULL 05/16] target/arm: add space before the open parenthesis '('
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Xinhao Zhang <zhangxinhao1@huawei.com>
2
2
3
For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15
3
Fix code style. Space required before the open parenthesis '('.
4
we dropped the sticky bit and so failed to raise inexact.
5
4
6
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
5
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Kai Deng <dengkai1@huawei.com>
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Message-id: 20180810193129.1556-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
fpu/softfloat.c | 2 +-
11
target/arm/translate.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
13
16
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/fpu/softfloat.c
16
--- a/target/arm/translate.c
19
+++ b/fpu/softfloat.c
17
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract,
18
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
21
}
19
- Hardware watchpoints.
22
a.frac += b.frac;
20
Hardware breakpoints have already been handled and skip this code.
23
if (a.frac & DECOMPOSED_OVERFLOW_BIT) {
21
*/
24
- a.frac >>= 1;
22
- switch(dc->base.is_jmp) {
25
+ shift64RightJamming(a.frac, 1, &a.frac);
23
+ switch (dc->base.is_jmp) {
26
a.exp += 1;
24
case DISAS_NEXT:
27
}
25
case DISAS_TOO_MANY:
28
return a;
26
gen_goto_tb(dc, 1, dc->base.pc_next);
29
--
27
--
30
2.18.0
28
2.20.1
31
29
32
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/30] Add QTest testcase for the Intel Hexadecimal
[PULL 06/16] docs: add some notes on the sbsa-ref machine
1
From: Su Hang <suhang16@mails.ucas.ac.cn>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
'test.hex' file is a memory test pattern stored in Hexadecimal Object
3
We should at least document what this machine is about.
4
Format. It loads at 0x10000 in RAM and contains values from 0 through
5
255.
6
4
7
The test case verifies that the expected memory test pattern was loaded.
5
Reviewed-by: Graeme Gregory <graeme@nuviainc.com>
8
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
7
Message-id: 20201104165254.24822-1-alex.bennee@linaro.org
10
Suggested-by: Steffen Gortz <qemu.ml@steffen-goertz.de>
8
Cc: Leif Lindholm <leif@nuviainc.com>
11
Suggested-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Cc: Shashi Mallela <shashi.mallela@linaro.org>
12
Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn>
10
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
13
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
11
[PMM: fixed filename mismatch]
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
[PMM: changed qtest_startf() to qtest_initf() to work with
16
current master after the refactoring in commit 88b988c895e3c2]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
13
---
19
configure | 4 +++
14
docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++
20
tests/Makefile.include | 2 ++
15
docs/system/target-arm.rst | 1 +
21
tests/hexloader-test.c | 45 ++++++++++++++++++++++++++++
16
2 files changed, 33 insertions(+)
22
MAINTAINERS | 6 ++++
17
create mode 100644 docs/system/arm/sbsa.rst
23
tests/hex-loader-check-data/test.hex | 18 +++++++++++
24
5 files changed, 75 insertions(+)
25
create mode 100644 tests/hexloader-test.c
26
create mode 100644 tests/hex-loader-check-data/test.hex
27
18
28
diff --git a/configure b/configure
19
diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst
29
index XXXXXXX..XXXXXXX 100755
30
--- a/configure
31
+++ b/configure
32
@@ -XXX,XX +XXX,XX @@ for test_file in $(find $source_path/tests/acpi-test-data -type f)
33
do
34
FILES="$FILES tests/acpi-test-data$(echo $test_file | sed -e 's/.*acpi-test-data//')"
35
done
36
+for test_file in $(find $source_path/tests/hex-loader-check-data -type f)
37
+do
38
+ FILES="$FILES tests/hex-loader-check-data$(echo $test_file | sed -e 's/.*hex-loader-check-data//')"
39
+done
40
mkdir -p $DIRS
41
for f in $FILES ; do
42
if [ -e "$source_path/$f" ] && [ "$pwd_is_source_path" != "y" ]; then
43
diff --git a/tests/Makefile.include b/tests/Makefile.include
44
index XXXXXXX..XXXXXXX 100644
45
--- a/tests/Makefile.include
46
+++ b/tests/Makefile.include
47
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
48
gcov-files-arm-y += hw/timer/arm_mptimer.c
49
check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
50
check-qtest-arm-y += tests/sdhci-test$(EXESUF)
51
+check-qtest-arm-y += tests/hexloader-test$(EXESUF)
52
53
check-qtest-aarch64-y = tests/numa-test$(EXESUF)
54
check-qtest-aarch64-y += tests/sdhci-test$(EXESUF)
55
@@ -XXX,XX +XXX,XX @@ tests/qmp-test$(EXESUF): tests/qmp-test.o
56
tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o
57
tests/rtc-test$(EXESUF): tests/rtc-test.o
58
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
59
+tests/hexloader-test$(EXESUF): tests/hexloader-test.o
60
tests/endianness-test$(EXESUF): tests/endianness-test.o
61
tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
62
tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y)
63
diff --git a/tests/hexloader-test.c b/tests/hexloader-test.c
64
new file mode 100644
20
new file mode 100644
65
index XXXXXXX..XXXXXXX
21
index XXXXXXX..XXXXXXX
66
--- /dev/null
22
--- /dev/null
67
+++ b/tests/hexloader-test.c
23
+++ b/docs/system/arm/sbsa.rst
68
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@
69
+/*
25
+Arm Server Base System Architecture Reference board (``sbsa-ref``)
70
+ * QTest testcase for the Intel Hexadecimal Object File Loader
26
+==================================================================
71
+ *
72
+ * Authors:
73
+ * Su Hang <suhang16@mails.ucas.ac.cn> 2018
74
+ *
75
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
76
+ * See the COPYING file in the top-level directory.
77
+ *
78
+ */
79
+
27
+
80
+#include "qemu/osdep.h"
28
+While the `virt` board is a generic board platform that doesn't match
81
+#include "libqtest.h"
29
+any real hardware the `sbsa-ref` board intends to look like real
30
+hardware. The `Server Base System Architecture
31
+<https://developer.arm.com/documentation/den0029/latest>` defines a
32
+minimum base line of hardware support and importantly how the firmware
33
+reports that to any operating system. It is a static system that
34
+reports a very minimal DT to the firmware for non-discoverable
35
+information about components affected by the qemu command line (i.e.
36
+cpus and memory). As a result it must have a firmware specifically
37
+built to expect a certain hardware layout (as you would in a real
38
+machine).
82
+
39
+
83
+/* Load 'test.hex' and verify that the in-memory contents are as expected.
40
+It is intended to be a machine for developing firmware and testing
84
+ * 'test.hex' is a memory test pattern stored in Hexadecimal Object
41
+standards compliance with operating systems.
85
+ * format. It loads at 0x10000 in RAM and contains values from 0 through
86
+ * 255.
87
+ */
88
+static void hex_loader_test(void)
89
+{
90
+ unsigned int i;
91
+ const unsigned int base_addr = 0x00010000;
92
+
42
+
93
+ QTestState *s = qtest_initf(
43
+Supported devices
94
+ "-M vexpress-a9 -nographic -device loader,file=tests/hex-loader-check-data/test.hex");
44
+"""""""""""""""""
95
+
45
+
96
+ for (i = 0; i < 256; ++i) {
46
+The sbsa-ref board supports:
97
+ uint8_t val = qtest_readb(s, base_addr + i);
98
+ g_assert_cmpuint(i, ==, val);
99
+ }
100
+ qtest_quit(s);
101
+}
102
+
47
+
103
+int main(int argc, char **argv)
48
+ - A configurable number of AArch64 CPUs
104
+{
49
+ - GIC version 3
105
+ int ret;
50
+ - System bus AHCI controller
51
+ - System bus EHCI controller
52
+ - CDROM and hard disc on AHCI bus
53
+ - E1000E ethernet card on PCIe bus
54
+ - VGA display adaptor on PCIe bus
55
+ - A generic SBSA watchdog device
106
+
56
+
107
+ g_test_init(&argc, &argv, NULL);
57
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
108
+
109
+ qtest_add_func("/tmp/hex_loader", hex_loader_test);
110
+ ret = g_test_run();
111
+
112
+ return ret;
113
+}
114
diff --git a/MAINTAINERS b/MAINTAINERS
115
index XXXXXXX..XXXXXXX 100644
58
index XXXXXXX..XXXXXXX 100644
116
--- a/MAINTAINERS
59
--- a/docs/system/target-arm.rst
117
+++ b/MAINTAINERS
60
+++ b/docs/system/target-arm.rst
118
@@ -XXX,XX +XXX,XX @@ F: hw/core/generic-loader.c
61
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
119
F: include/hw/core/generic-loader.h
62
arm/mps2
120
F: docs/generic-loader.txt
63
arm/musca
121
64
arm/realview
122
+Intel Hexadecimal Object File Loader
65
+ arm/sbsa
123
+M: Su Hang <suhang16@mails.ucas.ac.cn>
66
arm/versatile
124
+S: Maintained
67
arm/vexpress
125
+F: tests/hexloader-test.c
68
arm/aspeed
126
+F: tests/hex-loader-check-data/test.hex
127
+
128
CHRP NVRAM
129
M: Thomas Huth <thuth@redhat.com>
130
S: Maintained
131
diff --git a/tests/hex-loader-check-data/test.hex b/tests/hex-loader-check-data/test.hex
132
new file mode 100644
133
index XXXXXXX..XXXXXXX
134
--- /dev/null
135
+++ b/tests/hex-loader-check-data/test.hex
136
@@ -XXX,XX +XXX,XX @@
137
+:020000040001F9
138
+:10000000000102030405060708090a0b0c0d0e0f78
139
+:10001000101112131415161718191a1b1c1d1e1f68
140
+:10002000202122232425262728292a2b2c2d2e2f58
141
+:10003000303132333435363738393a3b3c3d3e3f48
142
+:10004000404142434445464748494a4b4c4d4e4f38
143
+:10005000505152535455565758595a5b5c5d5e5f28
144
+:10006000606162636465666768696a6b6c6d6e6f18
145
+:10007000707172737475767778797a7b7c7d7e7f08
146
+:10008000808182838485868788898a8b8c8d8e8ff8
147
+:10009000909192939495969798999a9b9c9d9e9fe8
148
+:1000a000a0a1a2a3a4a5a6a7a8a9aaabacadaeafd8
149
+:1000b000b0b1b2b3b4b5b6b7b8b9babbbcbdbebfc8
150
+:1000c000c0c1c2c3c4c5c6c7c8c9cacbcccdcecfb8
151
+:1000d000d0d1d2d3d4d5d6d7d8d9dadbdcdddedfa8
152
+:1000e000e0e1e2e3e4e5e6e7e8e9eaebecedeeef98
153
+:1000f000f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff88
154
+:00000001FF
155
--
69
--
156
2.18.0
70
2.20.1
157
71
158
72
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/30] aspeed: add a max_ram_size property to the memory controller
[PULL 07/16] hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
This will be used to construct a memory region beyond the RAM region
3
When using a Cortex-A15, the Virt machine does not use any
4
to let firmwares scan the address space with load/store to guess how
4
MPCore peripherals. Remove the dependency.
5
much RAM the SoC has.
6
5
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig")
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
9
Tested-by: Cédric Le Goater <clg@kaod.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20180807075757.7242-7-joel@jms.id.au
9
Message-id: 20201107114852.271922-1-philmd@redhat.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
12
---
14
include/hw/misc/aspeed_sdmc.h | 1 +
13
hw/arm/Kconfig | 1 -
15
hw/arm/aspeed.c | 31 +++++++++++++++++++++++++++++++
14
1 file changed, 1 deletion(-)
16
hw/arm/aspeed_soc.c | 2 ++
17
hw/misc/aspeed_sdmc.c | 3 +++
18
4 files changed, 37 insertions(+)
19
15
20
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
16
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/misc/aspeed_sdmc.h
18
--- a/hw/arm/Kconfig
23
+++ b/include/hw/misc/aspeed_sdmc.h
19
+++ b/hw/arm/Kconfig
24
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState {
20
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
25
uint32_t silicon_rev;
21
imply VFIO_PLATFORM
26
uint32_t ram_bits;
22
imply VFIO_XGMAC
27
uint64_t ram_size;
23
imply TPM_TIS_SYSBUS
28
+ uint64_t max_ram_size;
24
- select A15MPCORE
29
uint32_t fixed_conf;
25
select ACPI
30
26
select ARM_SMMUV3
31
} AspeedSDMCState;
27
select GPIO_KEY
32
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/aspeed.c
35
+++ b/hw/arm/aspeed.c
36
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = {
37
typedef struct AspeedBoardState {
38
AspeedSoCState soc;
39
MemoryRegion ram;
40
+ MemoryRegion max_ram;
41
} AspeedBoardState;
42
43
typedef struct AspeedBoardConfig {
44
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
45
},
46
};
47
48
+/*
49
+ * The max ram region is for firmwares that scan the address space
50
+ * with load/store to guess how much RAM the SoC has.
51
+ */
52
+static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
53
+{
54
+ return 0;
55
+}
56
+
57
+static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
58
+ unsigned size)
59
+{
60
+ /* Discard writes */
61
+}
62
+
63
+static const MemoryRegionOps max_ram_ops = {
64
+ .read = max_ram_read,
65
+ .write = max_ram_write,
66
+ .endianness = DEVICE_NATIVE_ENDIAN,
67
+};
68
+
69
#define FIRMWARE_ADDR 0x0
70
71
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
72
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
73
AspeedBoardState *bmc;
74
AspeedSoCClass *sc;
75
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
76
+ ram_addr_t max_ram_size;
77
78
bmc = g_new0(AspeedBoardState, 1);
79
object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
80
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
81
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
82
&error_abort);
83
84
+ max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
85
+ &error_abort);
86
+ memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
87
+ "max_ram", max_ram_size - ram_size);
88
+ memory_region_add_subregion(get_system_memory(),
89
+ sc->info->sdram_base + ram_size,
90
+ &bmc->max_ram);
91
+
92
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
93
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
94
95
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/arm/aspeed_soc.c
98
+++ b/hw/arm/aspeed_soc.c
99
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
100
sc->info->silicon_rev);
101
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
102
"ram-size", &error_abort);
103
+ object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
104
+ "max-ram-size", &error_abort);
105
106
for (i = 0; i < sc->info->wdts_num; i++) {
107
object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
108
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/hw/misc/aspeed_sdmc.c
111
+++ b/hw/misc/aspeed_sdmc.c
112
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
113
case AST2400_A0_SILICON_REV:
114
case AST2400_A1_SILICON_REV:
115
s->ram_bits = ast2400_rambits(s);
116
+ s->max_ram_size = 512 << 20;
117
s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
118
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
119
break;
120
case AST2500_A0_SILICON_REV:
121
case AST2500_A1_SILICON_REV:
122
s->ram_bits = ast2500_rambits(s);
123
+ s->max_ram_size = 1024 << 20;
124
s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
125
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
126
ASPEED_SDMC_CACHE_INITIAL_DONE |
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdmc = {
128
static Property aspeed_sdmc_properties[] = {
129
DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
130
DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
131
+ DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
132
DEFINE_PROP_END_OF_LIST(),
133
};
134
135
--
28
--
136
2.18.0
29
2.20.1
137
30
138
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/30] target/arm: Dump SVE state if enabled
[PULL 08/16] target/arm: Fix neon VTBL/VTBX for len > 1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Also fold the FPCR/FPSR state onto the same line as PSTATE,
3
The helper function did not get updated when we reorganized
4
and mention but do not dump disabled FPU state.
4
the vector register file for SVE. Since then, the neon dregs
5
are non-sequential and cannot be simply indexed.
5
6
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
At the same time, make the helper function operate on 64-bit
8
quantities so that we do not have to call it twice.
9
10
Fixes: c39c2b9043e
11
Reported-by: Ard Biesheuvel <ardb@kernel.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
[PMM: use aa32_vfp_dreg() rather than opencoding]
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20201105171126.88014-1-richard.henderson@linaro.org
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
target/arm/translate-a64.c | 95 +++++++++++++++++++++++++++++++++-----
18
target/arm/helper.h | 2 +-
13
1 file changed, 83 insertions(+), 12 deletions(-)
19
target/arm/op_helper.c | 23 +++++++++--------
20
target/arm/translate-neon.c.inc | 44 +++++++++++----------------------
21
3 files changed, 29 insertions(+), 40 deletions(-)
14
22
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
25
--- a/target/arm/helper.h
18
+++ b/target/arm/translate-a64.c
26
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)
28
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)
29
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
30
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
31
-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)
32
+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)
33
34
DEF_HELPER_3(shl_cc, i32, env, i32, i32)
35
DEF_HELPER_3(shr_cc, i32, env, i32, i32)
36
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/op_helper.c
39
+++ b/target/arm/op_helper.c
40
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
41
cpu_loop_exit_restore(cs, ra);
42
}
43
44
-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
45
- uint32_t maxindex)
46
+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,
47
+ uint64_t ireg, uint64_t def)
48
{
49
- uint32_t val, shift;
50
- uint64_t *table = vn;
51
+ uint64_t tmp, val = 0;
52
+ uint32_t maxindex = ((desc & 3) + 1) * 8;
53
+ uint32_t base_reg = desc >> 2;
54
+ uint32_t shift, index, reg;
55
56
- val = 0;
57
- for (shift = 0; shift < 32; shift += 8) {
58
- uint32_t index = (ireg >> shift) & 0xff;
59
+ for (shift = 0; shift < 64; shift += 8) {
60
+ index = (ireg >> shift) & 0xff;
61
if (index < maxindex) {
62
- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
63
- val |= tmp << shift;
64
+ reg = base_reg + (index >> 3);
65
+ tmp = *aa32_vfp_dreg(env, reg);
66
+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;
67
} else {
68
- val |= def & (0xff << shift);
69
+ tmp = def & (0xffull << shift);
70
}
71
+ val |= tmp;
72
}
73
return val;
74
}
75
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/translate-neon.c.inc
78
+++ b/target/arm/translate-neon.c.inc
79
@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)
80
81
static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
82
{
83
- int n;
84
- TCGv_i32 tmp, tmp2, tmp3, tmp4;
85
- TCGv_ptr ptr1;
86
+ TCGv_i64 val, def;
87
+ TCGv_i32 desc;
88
89
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
90
return false;
91
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
92
return true;
93
}
94
95
- n = a->len + 1;
96
- if ((a->vn + n) > 32) {
97
+ if ((a->vn + a->len + 1) > 32) {
98
/*
99
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
100
* helper function running off the end of the register file.
101
*/
102
return false;
103
}
104
- n <<= 3;
105
- tmp = tcg_temp_new_i32();
106
- if (a->op) {
107
- read_neon_element32(tmp, a->vd, 0, MO_32);
108
- } else {
109
- tcg_gen_movi_i32(tmp, 0);
110
- }
111
- tmp2 = tcg_temp_new_i32();
112
- read_neon_element32(tmp2, a->vm, 0, MO_32);
113
- ptr1 = vfp_reg_ptr(true, a->vn);
114
- tmp4 = tcg_const_i32(n);
115
- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);
116
117
+ desc = tcg_const_i32((a->vn << 2) | a->len);
118
+ def = tcg_temp_new_i64();
119
if (a->op) {
120
- read_neon_element32(tmp, a->vd, 1, MO_32);
121
+ read_neon_element64(def, a->vd, 0, MO_64);
20
} else {
122
} else {
21
ns_status = "";
123
- tcg_gen_movi_i32(tmp, 0);
124
+ tcg_gen_movi_i64(def, 0);
22
}
125
}
23
-
126
- tmp3 = tcg_temp_new_i32();
24
- cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
127
- read_neon_element32(tmp3, a->vm, 1, MO_32);
25
+ cpu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
128
- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);
26
psr,
129
- tcg_temp_free_i32(tmp);
27
psr & PSTATE_N ? 'N' : '-',
130
- tcg_temp_free_i32(tmp4);
28
psr & PSTATE_Z ? 'Z' : '-',
131
- tcg_temp_free_ptr(ptr1);
29
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
132
+ val = tcg_temp_new_i64();
30
el,
133
+ read_neon_element64(val, a->vm, 0, MO_64);
31
psr & PSTATE_SP ? 'h' : 't');
134
32
135
- write_neon_element32(tmp2, a->vd, 0, MO_32);
33
- if (flags & CPU_DUMP_FPU) {
136
- write_neon_element32(tmp3, a->vd, 1, MO_32);
34
- int numvfpregs = 32;
137
- tcg_temp_free_i32(tmp2);
35
- for (i = 0; i < numvfpregs; i++) {
138
- tcg_temp_free_i32(tmp3);
36
- uint64_t *q = aa64_vfp_qreg(env, i);
139
+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);
37
- uint64_t vlo = q[0];
140
+ write_neon_element64(val, a->vd, 0, MO_64);
38
- uint64_t vhi = q[1];
39
- cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c",
40
- i, vhi, vlo, (i & 1 ? '\n' : ' '));
41
+ if (!(flags & CPU_DUMP_FPU)) {
42
+ cpu_fprintf(f, "\n");
43
+ return;
44
+ }
45
+ cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
46
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
47
+
141
+
48
+ if (arm_feature(env, ARM_FEATURE_SVE)) {
142
+ tcg_temp_free_i64(def);
49
+ int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */
143
+ tcg_temp_free_i64(val);
50
+
144
+ tcg_temp_free_i32(desc);
51
+ for (i = 0; i <= FFR_PRED_NUM; i++) {
145
return true;
52
+ bool eol;
53
+ if (i == FFR_PRED_NUM) {
54
+ cpu_fprintf(f, "FFR=");
55
+ /* It's last, so end the line. */
56
+ eol = true;
57
+ } else {
58
+ cpu_fprintf(f, "P%02d=", i);
59
+ switch (zcr_len) {
60
+ case 0:
61
+ eol = i % 8 == 7;
62
+ break;
63
+ case 1:
64
+ eol = i % 6 == 5;
65
+ break;
66
+ case 2:
67
+ case 3:
68
+ eol = i % 3 == 2;
69
+ break;
70
+ default:
71
+ /* More than one quadword per predicate. */
72
+ eol = true;
73
+ break;
74
+ }
75
+ }
76
+ for (j = zcr_len / 4; j >= 0; j--) {
77
+ int digits;
78
+ if (j * 4 + 4 <= zcr_len + 1) {
79
+ digits = 16;
80
+ } else {
81
+ digits = (zcr_len % 4 + 1) * 4;
82
+ }
83
+ cpu_fprintf(f, "%0*" PRIx64 "%s", digits,
84
+ env->vfp.pregs[i].p[j],
85
+ j ? ":" : eol ? "\n" : " ");
86
+ }
87
+ }
88
+
89
+ for (i = 0; i < 32; i++) {
90
+ if (zcr_len == 0) {
91
+ cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
92
+ i, env->vfp.zregs[i].d[1],
93
+ env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
94
+ } else if (zcr_len == 1) {
95
+ cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
96
+ ":%016" PRIx64 ":%016" PRIx64 "\n",
97
+ i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
98
+ env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
99
+ } else {
100
+ for (j = zcr_len; j >= 0; j--) {
101
+ bool odd = (zcr_len - j) % 2 != 0;
102
+ if (j == zcr_len) {
103
+ cpu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
104
+ } else if (!odd) {
105
+ if (j > 0) {
106
+ cpu_fprintf(f, " [%x-%x]=", j, j - 1);
107
+ } else {
108
+ cpu_fprintf(f, " [%x]=", j);
109
+ }
110
+ }
111
+ cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
112
+ env->vfp.zregs[i].d[j * 2 + 1],
113
+ env->vfp.zregs[i].d[j * 2],
114
+ odd || j == 0 ? "\n" : ":");
115
+ }
116
+ }
117
+ }
118
+ } else {
119
+ for (i = 0; i < 32; i++) {
120
+ uint64_t *q = aa64_vfp_qreg(env, i);
121
+ cpu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
122
+ i, q[1], q[0], (i & 1 ? "\n" : " "));
123
}
124
- cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
125
- vfp_get_fpcr(env), vfp_get_fpsr(env));
126
}
127
}
146
}
128
147
129
--
148
--
130
2.18.0
149
2.20.1
131
150
132
151
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/30] loader: Implement .hex file loader
[PULL 09/16] hw/arm/armsse: Correct expansion MPC interrupt lines
1
From: Su Hang <suhang16@mails.ucas.ac.cn>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
This patch adds Intel Hexadecimal Object File format support to the
3
We can use one MPC per SRAM bank, but we currently only wire the
4
generic loader device. The file format specification is available here:
4
IRQ from the first expansion MPC to the IRQ splitter. Fix that.
5
http://www.piclist.com/techref/fileext/hex/intel.htm
6
5
7
This file format is often used with microcontrollers such as the
6
Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")
8
micro:bit, Arduino, STM32, etc. Users expect to be able to run .hex
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
files directly with without first converting them to ELF. Most
8
Message-id: 20201107193403.436146-2-f4bug@amsat.org
10
micro:bit code is developed in web-based IDEs without direct user access
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
to binutils so it is important for QEMU to handle this file format
12
natively.
13
14
Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn>
15
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
16
Acked-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20180814162739.11814-6-stefanha@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
11
---
20
include/hw/loader.h | 12 ++
12
hw/arm/armsse.c | 3 ++-
21
hw/core/generic-loader.c | 4 +
13
1 file changed, 2 insertions(+), 1 deletion(-)
22
hw/core/loader.c | 249 +++++++++++++++++++++++++++++++++++++++
23
3 files changed, 265 insertions(+)
24
14
25
diff --git a/include/hw/loader.h b/include/hw/loader.h
15
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/loader.h
17
--- a/hw/arm/armsse.c
28
+++ b/include/hw/loader.h
18
+++ b/hw/arm/armsse.c
29
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_size(const char *filename, void *addr, size_t size);
19
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
30
int load_image_targphys_as(const char *filename,
20
qdev_get_gpio_in(dev_splitter, 0));
31
hwaddr addr, uint64_t max_sz, AddressSpace *as);
21
qdev_connect_gpio_out(dev_splitter, 0,
32
22
qdev_get_gpio_in_named(dev_secctl,
33
+/**load_targphys_hex_as:
23
- "mpc_status", 0));
34
+ * @filename: Path to the .hex file
24
+ "mpc_status",
35
+ * @entry: Store the entry point given by the .hex file
25
+ i - IOTS_NUM_EXP_MPC));
36
+ * @as: The AddressSpace to load the .hex file to. The value of
37
+ * address_space_memory is used if nothing is supplied here.
38
+ *
39
+ * Load a fixed .hex file into memory.
40
+ *
41
+ * Returns the size of the loaded .hex file on success, -1 otherwise.
42
+ */
43
+int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as);
44
+
45
/** load_image_targphys:
46
* Same as load_image_targphys_as(), but doesn't allow the caller to specify
47
* an AddressSpace.
48
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/core/generic-loader.c
51
+++ b/hw/core/generic-loader.c
52
@@ -XXX,XX +XXX,XX @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
53
size = load_uimage_as(s->file, &entry, NULL, NULL, NULL, NULL,
54
as);
55
}
56
+
57
+ if (size < 0) {
58
+ size = load_targphys_hex_as(s->file, &entry, as);
59
+ }
60
}
26
}
61
27
62
if (size < 0 || s->force_raw) {
28
qdev_connect_gpio_out(dev_splitter, 1,
63
diff --git a/hw/core/loader.c b/hw/core/loader.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/core/loader.c
66
+++ b/hw/core/loader.c
67
@@ -XXX,XX +XXX,XX @@ void hmp_info_roms(Monitor *mon, const QDict *qdict)
68
}
69
}
70
}
71
+
72
+typedef enum HexRecord HexRecord;
73
+enum HexRecord {
74
+ DATA_RECORD = 0,
75
+ EOF_RECORD,
76
+ EXT_SEG_ADDR_RECORD,
77
+ START_SEG_ADDR_RECORD,
78
+ EXT_LINEAR_ADDR_RECORD,
79
+ START_LINEAR_ADDR_RECORD,
80
+};
81
+
82
+/* Each record contains a 16-bit address which is combined with the upper 16
83
+ * bits of the implicit "next address" to form a 32-bit address.
84
+ */
85
+#define NEXT_ADDR_MASK 0xffff0000
86
+
87
+#define DATA_FIELD_MAX_LEN 0xff
88
+#define LEN_EXCEPT_DATA 0x5
89
+/* 0x5 = sizeof(byte_count) + sizeof(address) + sizeof(record_type) +
90
+ * sizeof(checksum) */
91
+typedef struct {
92
+ uint8_t byte_count;
93
+ uint16_t address;
94
+ uint8_t record_type;
95
+ uint8_t data[DATA_FIELD_MAX_LEN];
96
+ uint8_t checksum;
97
+} HexLine;
98
+
99
+/* return 0 or -1 if error */
100
+static bool parse_record(HexLine *line, uint8_t *our_checksum, const uint8_t c,
101
+ uint32_t *index, const bool in_process)
102
+{
103
+ /* +-------+---------------+-------+---------------------+--------+
104
+ * | byte | |record | | |
105
+ * | count | address | type | data |checksum|
106
+ * +-------+---------------+-------+---------------------+--------+
107
+ * ^ ^ ^ ^ ^ ^
108
+ * |1 byte | 2 bytes |1 byte | 0-255 bytes | 1 byte |
109
+ */
110
+ uint8_t value = 0;
111
+ uint32_t idx = *index;
112
+ /* ignore space */
113
+ if (g_ascii_isspace(c)) {
114
+ return true;
115
+ }
116
+ if (!g_ascii_isxdigit(c) || !in_process) {
117
+ return false;
118
+ }
119
+ value = g_ascii_xdigit_value(c);
120
+ value = (idx & 0x1) ? (value & 0xf) : (value << 4);
121
+ if (idx < 2) {
122
+ line->byte_count |= value;
123
+ } else if (2 <= idx && idx < 6) {
124
+ line->address <<= 4;
125
+ line->address += g_ascii_xdigit_value(c);
126
+ } else if (6 <= idx && idx < 8) {
127
+ line->record_type |= value;
128
+ } else if (8 <= idx && idx < 8 + 2 * line->byte_count) {
129
+ line->data[(idx - 8) >> 1] |= value;
130
+ } else if (8 + 2 * line->byte_count <= idx &&
131
+ idx < 10 + 2 * line->byte_count) {
132
+ line->checksum |= value;
133
+ } else {
134
+ return false;
135
+ }
136
+ *our_checksum += value;
137
+ ++(*index);
138
+ return true;
139
+}
140
+
141
+typedef struct {
142
+ const char *filename;
143
+ HexLine line;
144
+ uint8_t *bin_buf;
145
+ hwaddr *start_addr;
146
+ int total_size;
147
+ uint32_t next_address_to_write;
148
+ uint32_t current_address;
149
+ uint32_t current_rom_index;
150
+ uint32_t rom_start_address;
151
+ AddressSpace *as;
152
+} HexParser;
153
+
154
+/* return size or -1 if error */
155
+static int handle_record_type(HexParser *parser)
156
+{
157
+ HexLine *line = &(parser->line);
158
+ switch (line->record_type) {
159
+ case DATA_RECORD:
160
+ parser->current_address =
161
+ (parser->next_address_to_write & NEXT_ADDR_MASK) | line->address;
162
+ /* verify this is a contiguous block of memory */
163
+ if (parser->current_address != parser->next_address_to_write) {
164
+ if (parser->current_rom_index != 0) {
165
+ rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
166
+ parser->current_rom_index,
167
+ parser->rom_start_address, parser->as);
168
+ }
169
+ parser->rom_start_address = parser->current_address;
170
+ parser->current_rom_index = 0;
171
+ }
172
+
173
+ /* copy from line buffer to output bin_buf */
174
+ memcpy(parser->bin_buf + parser->current_rom_index, line->data,
175
+ line->byte_count);
176
+ parser->current_rom_index += line->byte_count;
177
+ parser->total_size += line->byte_count;
178
+ /* save next address to write */
179
+ parser->next_address_to_write =
180
+ parser->current_address + line->byte_count;
181
+ break;
182
+
183
+ case EOF_RECORD:
184
+ if (parser->current_rom_index != 0) {
185
+ rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
186
+ parser->current_rom_index,
187
+ parser->rom_start_address, parser->as);
188
+ }
189
+ return parser->total_size;
190
+ case EXT_SEG_ADDR_RECORD:
191
+ case EXT_LINEAR_ADDR_RECORD:
192
+ if (line->byte_count != 2 && line->address != 0) {
193
+ return -1;
194
+ }
195
+
196
+ if (parser->current_rom_index != 0) {
197
+ rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
198
+ parser->current_rom_index,
199
+ parser->rom_start_address, parser->as);
200
+ }
201
+
202
+ /* save next address to write,
203
+ * in case of non-contiguous block of memory */
204
+ parser->next_address_to_write = (line->data[0] << 12) |
205
+ (line->data[1] << 4);
206
+ if (line->record_type == EXT_LINEAR_ADDR_RECORD) {
207
+ parser->next_address_to_write <<= 12;
208
+ }
209
+
210
+ parser->rom_start_address = parser->next_address_to_write;
211
+ parser->current_rom_index = 0;
212
+ break;
213
+
214
+ case START_SEG_ADDR_RECORD:
215
+ if (line->byte_count != 4 && line->address != 0) {
216
+ return -1;
217
+ }
218
+
219
+ /* x86 16-bit CS:IP segmented addressing */
220
+ *(parser->start_addr) = (((line->data[0] << 8) | line->data[1]) << 4) +
221
+ ((line->data[2] << 8) | line->data[3]);
222
+ break;
223
+
224
+ case START_LINEAR_ADDR_RECORD:
225
+ if (line->byte_count != 4 && line->address != 0) {
226
+ return -1;
227
+ }
228
+
229
+ *(parser->start_addr) = ldl_be_p(line->data);
230
+ break;
231
+
232
+ default:
233
+ return -1;
234
+ }
235
+
236
+ return parser->total_size;
237
+}
238
+
239
+/* return size or -1 if error */
240
+static int parse_hex_blob(const char *filename, hwaddr *addr, uint8_t *hex_blob,
241
+ size_t hex_blob_size, AddressSpace *as)
242
+{
243
+ bool in_process = false; /* avoid re-enter and
244
+ * check whether record begin with ':' */
245
+ uint8_t *end = hex_blob + hex_blob_size;
246
+ uint8_t our_checksum = 0;
247
+ uint32_t record_index = 0;
248
+ HexParser parser = {
249
+ .filename = filename,
250
+ .bin_buf = g_malloc(hex_blob_size),
251
+ .start_addr = addr,
252
+ .as = as,
253
+ };
254
+
255
+ rom_transaction_begin();
256
+
257
+ for (; hex_blob < end; ++hex_blob) {
258
+ switch (*hex_blob) {
259
+ case '\r':
260
+ case '\n':
261
+ if (!in_process) {
262
+ break;
263
+ }
264
+
265
+ in_process = false;
266
+ if ((LEN_EXCEPT_DATA + parser.line.byte_count) * 2 !=
267
+ record_index ||
268
+ our_checksum != 0) {
269
+ parser.total_size = -1;
270
+ goto out;
271
+ }
272
+
273
+ if (handle_record_type(&parser) == -1) {
274
+ parser.total_size = -1;
275
+ goto out;
276
+ }
277
+ break;
278
+
279
+ /* start of a new record. */
280
+ case ':':
281
+ memset(&parser.line, 0, sizeof(HexLine));
282
+ in_process = true;
283
+ record_index = 0;
284
+ break;
285
+
286
+ /* decoding lines */
287
+ default:
288
+ if (!parse_record(&parser.line, &our_checksum, *hex_blob,
289
+ &record_index, in_process)) {
290
+ parser.total_size = -1;
291
+ goto out;
292
+ }
293
+ break;
294
+ }
295
+ }
296
+
297
+out:
298
+ g_free(parser.bin_buf);
299
+ rom_transaction_end(parser.total_size != -1);
300
+ return parser.total_size;
301
+}
302
+
303
+/* return size or -1 if error */
304
+int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as)
305
+{
306
+ gsize hex_blob_size;
307
+ gchar *hex_blob;
308
+ int total_size = 0;
309
+
310
+ if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) {
311
+ return -1;
312
+ }
313
+
314
+ total_size = parse_hex_blob(filename, entry, (uint8_t *)hex_blob,
315
+ hex_blob_size, as);
316
+
317
+ g_free(hex_blob);
318
+ return total_size;
319
+}
320
--
29
--
321
2.18.0
30
2.20.1
322
31
323
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/30] hw/arm: make bitbanded IO optional on ARMv7-M
[PULL 10/16] hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ
1
From: Stefan Hajnoczi <stefanha@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Some ARM CPUs have bitbanded IO, a memory region that allows convenient
3
The system configuration controller (SYSCFG) doesn't have
4
bit access via 32-bit memory loads/stores. This eliminates the need for
4
any output IRQ (and the INTC input #71 belongs to the UART6).
5
read-modify-update instruction sequences.
5
Remove the invalid code.
6
6
7
This patch makes this optional feature an ARMv7MState qdev property,
7
Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC")
8
allowing boards to choose whether they want bitbanding or not.
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
9
Message-id: 20201107193403.436146-3-f4bug@amsat.org
10
Status of boards:
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
* iotkit (Cortex M33), no bitband
12
* mps2 (Cortex M3), bitband
13
* msf2 (Cortex M3), bitband
14
* stellaris (Cortex M3), bitband
15
* stm32f205 (Cortex M3), bitband
16
17
As a side-effect of this patch, Peter Maydell noted that the Ethernet
18
controller on mps2 board is now accessible. Previously they were hidden
19
by the bitband region (which does not exist on the real board).
20
21
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
22
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Message-id: 20180814162739.11814-2-stefanha@redhat.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
12
---
26
include/hw/arm/armv7m.h | 2 ++
13
include/hw/misc/stm32f2xx_syscfg.h | 2 --
27
hw/arm/armv7m.c | 37 ++++++++++++++++++++-----------------
14
hw/arm/stm32f205_soc.c | 1 -
28
hw/arm/mps2.c | 1 +
15
hw/misc/stm32f2xx_syscfg.c | 2 --
29
hw/arm/msf2-soc.c | 1 +
16
3 files changed, 5 deletions(-)
30
hw/arm/stellaris.c | 1 +
31
hw/arm/stm32f205_soc.c | 1 +
32
6 files changed, 26 insertions(+), 17 deletions(-)
33
17
34
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
18
diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h
35
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/armv7m.h
20
--- a/include/hw/misc/stm32f2xx_syscfg.h
37
+++ b/include/hw/arm/armv7m.h
21
+++ b/include/hw/misc/stm32f2xx_syscfg.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct {
22
@@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState {
39
* devices will be automatically layered on top of this view.)
23
uint32_t syscfg_exticr3;
40
* + Property "idau": IDAU interface (forwarded to CPU object)
24
uint32_t syscfg_exticr4;
41
* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
25
uint32_t syscfg_cmpcr;
42
+ * + Property "enable-bitband": expose bitbanded IO
26
-
43
*/
27
- qemu_irq irq;
44
typedef struct ARMv7MState {
45
/*< private >*/
46
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
47
MemoryRegion *board_memory;
48
Object *idau;
49
uint32_t init_svtor;
50
+ bool enable_bitband;
51
} ARMv7MState;
52
53
#endif
54
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/armv7m.c
57
+++ b/hw/arm/armv7m.c
58
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
59
memory_region_add_subregion(&s->container, 0xe000e000,
60
sysbus_mmio_get_region(sbd, 0));
61
62
- for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
63
- Object *obj = OBJECT(&s->bitband[i]);
64
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
65
+ if (s->enable_bitband) {
66
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
67
+ Object *obj = OBJECT(&s->bitband[i]);
68
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
69
70
- object_property_set_int(obj, bitband_input_addr[i], "base", &err);
71
- if (err != NULL) {
72
- error_propagate(errp, err);
73
- return;
74
- }
75
- object_property_set_link(obj, OBJECT(s->board_memory),
76
- "source-memory", &error_abort);
77
- object_property_set_bool(obj, true, "realized", &err);
78
- if (err != NULL) {
79
- error_propagate(errp, err);
80
- return;
81
- }
82
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
83
+ if (err != NULL) {
84
+ error_propagate(errp, err);
85
+ return;
86
+ }
87
+ object_property_set_link(obj, OBJECT(s->board_memory),
88
+ "source-memory", &error_abort);
89
+ object_property_set_bool(obj, true, "realized", &err);
90
+ if (err != NULL) {
91
+ error_propagate(errp, err);
92
+ return;
93
+ }
94
95
- memory_region_add_subregion(&s->container, bitband_output_addr[i],
96
- sysbus_mmio_get_region(sbd, 0));
97
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
98
+ sysbus_mmio_get_region(sbd, 0));
99
+ }
100
}
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
104
MemoryRegion *),
105
DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
106
DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
107
+ DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
108
DEFINE_PROP_END_OF_LIST(),
109
};
28
};
110
29
111
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
30
#endif /* HW_STM32F2XX_SYSCFG_H */
112
index XXXXXXX..XXXXXXX 100644
113
--- a/hw/arm/mps2.c
114
+++ b/hw/arm/mps2.c
115
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
116
g_assert_not_reached();
117
}
118
qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
119
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
120
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
121
"memory", &error_abort);
122
object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
123
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/msf2-soc.c
126
+++ b/hw/arm/msf2-soc.c
127
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
128
armv7m = DEVICE(&s->armv7m);
129
qdev_prop_set_uint32(armv7m, "num-irq", 81);
130
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
131
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
132
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
133
"memory", &error_abort);
134
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
135
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
136
index XXXXXXX..XXXXXXX 100644
137
--- a/hw/arm/stellaris.c
138
+++ b/hw/arm/stellaris.c
139
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
140
nvic = qdev_create(NULL, TYPE_ARMV7M);
141
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
142
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
143
+ qdev_prop_set_bit(nvic, "enable-bitband", true);
144
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
145
"memory", &error_abort);
146
/* This will exit with an error if the user passed us a bad cpu_type */
147
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
31
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
148
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
149
--- a/hw/arm/stm32f205_soc.c
33
--- a/hw/arm/stm32f205_soc.c
150
+++ b/hw/arm/stm32f205_soc.c
34
+++ b/hw/arm/stm32f205_soc.c
151
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
35
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
152
armv7m = DEVICE(&s->armv7m);
36
}
153
qdev_prop_set_uint32(armv7m, "num-irq", 96);
37
busdev = SYS_BUS_DEVICE(dev);
154
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
38
sysbus_mmio_map(busdev, 0, 0x40013800);
155
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
39
- sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
156
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
40
157
"memory", &error_abort);
41
/* Attach UART (uses USART registers) and USART controllers */
158
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
42
for (i = 0; i < STM_NUM_USARTS; i++) {
43
diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/misc/stm32f2xx_syscfg.c
46
+++ b/hw/misc/stm32f2xx_syscfg.c
47
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj)
48
{
49
STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
50
51
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
52
-
53
memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
54
TYPE_STM32F2XX_SYSCFG, 0x400);
55
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
159
--
56
--
160
2.18.0
57
2.20.1
161
58
162
59
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/30] hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
[PULL 11/16] hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()
1
From: Thomas Huth <thuth@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Now that we've got the common sysbus_init_child_obj() function, we do
3
omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic
4
not need the local init_sysbus_child() anymore.
4
OMAP2 chip support") takes care of creating the 3 UARTs.
5
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
6
Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+
7
Message-id: 1534420566-15799-1-git-send-email-thuth@redhat.com
7
extensions and attach to n8x0's UART") added n8x0_uart_setup()
8
which create the UART and connects it to an IRQ output,
9
overwritting the existing peripheral and its IRQ connection.
10
This is incorrect.
11
12
Fortunately we don't need to fix this, because commit 6da68df7f9b
13
("hw/arm/nseries: Replace the bluetooth chardev with a "null"
14
chardev") removed the use of this peripheral. We can simply
15
remove the code.
16
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20201107193403.436146-4-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
hw/arm/mps2-tz.c | 32 +++++++++++---------------------
22
hw/arm/nseries.c | 11 -----------
12
1 file changed, 11 insertions(+), 21 deletions(-)
23
1 file changed, 11 deletions(-)
13
24
14
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
25
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2-tz.c
27
--- a/hw/arm/nseries.c
17
+++ b/hw/arm/mps2-tz.c
28
+++ b/hw/arm/nseries.c
18
@@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name,
29
@@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s)
19
memory_region_add_subregion(get_system_memory(), base, mr);
30
cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1));
20
}
31
}
21
32
22
-static void init_sysbus_child(Object *parent, const char *childname,
33
-static void n8x0_uart_setup(struct n800_s *s)
23
- void *child, size_t childsize,
24
- const char *childtype)
25
-{
34
-{
26
- object_initialize(child, childsize, childtype);
35
- Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL);
27
- object_property_add_child(parent, childname, OBJECT(child), &error_abort);
36
- /*
28
- qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
37
- * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO
29
-
38
- * here, but this code has been removed with the bluetooth backend.
39
- */
40
- omap_uart_attach(s->mpu->uart[BT_UART], radio);
30
-}
41
-}
31
-
42
-
32
/* Most of the devices in the AN505 FPGA image sit behind
43
static void n8x0_usb_setup(struct n800_s *s)
33
* Peripheral Protection Controllers. These data structures
44
{
34
* define the layout of which devices sit behind which PPCs.
45
SysBusDevice *dev;
35
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
46
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
36
*/
47
n8x0_spi_setup(s);
37
UnimplementedDeviceState *uds = opaque;
48
n8x0_dss_setup(s);
38
49
n8x0_cbus_setup(s);
39
- init_sysbus_child(OBJECT(mms), name, uds,
50
- n8x0_uart_setup(s);
40
- sizeof(UnimplementedDeviceState),
51
if (machine_usb(machine)) {
41
- TYPE_UNIMPLEMENTED_DEVICE);
52
n8x0_usb_setup(s);
42
+ sysbus_init_child_obj(OBJECT(mms), name, uds,
43
+ sizeof(UnimplementedDeviceState),
44
+ TYPE_UNIMPLEMENTED_DEVICE);
45
qdev_prop_set_string(DEVICE(uds), "name", name);
46
qdev_prop_set_uint64(DEVICE(uds), "size", size);
47
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
48
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
49
DeviceState *iotkitdev = DEVICE(&mms->iotkit);
50
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
51
52
- init_sysbus_child(OBJECT(mms), name, uart,
53
- sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);
54
+ sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
55
+ TYPE_CMSDK_APB_UART);
56
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
57
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
58
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
60
61
memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
62
63
- init_sysbus_child(OBJECT(mms), mpcname, mpc,
64
- sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC);
65
+ sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
66
+ TYPE_TZ_MPC);
67
object_property_set_link(OBJECT(mpc), OBJECT(ssram),
68
"downstream", &error_fatal);
69
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
70
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
71
exit(1);
72
}
53
}
73
74
- init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit,
75
- sizeof(mms->iotkit), TYPE_IOTKIT);
76
+ sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
77
+ sizeof(mms->iotkit), TYPE_IOTKIT);
78
iotkitdev = DEVICE(&mms->iotkit);
79
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
80
"memory", &error_abort);
81
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
82
int port;
83
char *gpioname;
84
85
- init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc,
86
- sizeof(TZPPC), TYPE_TZ_PPC);
87
+ sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
88
+ sizeof(TZPPC), TYPE_TZ_PPC);
89
ppcdev = DEVICE(ppc);
90
91
for (port = 0; port < TZ_NUM_PORTS; port++) {
92
--
54
--
93
2.18.0
55
2.20.1
94
56
95
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/30] i.MX6UL: Add i.MX6UL SOC
[PULL 12/16] hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
3
The MusicPal board code connects both of the IRQ outputs of the UART
4
Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net
4
to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly
5
to the same input is not valid as it produces subtly wrong behaviour
6
(for instance if both the IRQ lines are high, and then one goes
7
low, the INTC input will see this as a high-to-low transition
8
even though the second IRQ line should still be holding it high).
9
10
This kind of wiring needs an explicitly created OR gate; add one.
11
12
Inspired-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20201107193403.436146-5-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
17
---
8
hw/arm/Makefile.objs | 1 +
18
hw/arm/musicpal.c | 17 +++++++++++++----
9
include/hw/arm/fsl-imx6ul.h | 339 ++++++++++++++++++
19
hw/arm/Kconfig | 1 +
10
hw/arm/fsl-imx6ul.c | 617 ++++++++++++++++++++++++++++++++
20
2 files changed, 14 insertions(+), 4 deletions(-)
11
default-configs/arm-softmmu.mak | 1 +
12
4 files changed, 958 insertions(+)
13
create mode 100644 include/hw/arm/fsl-imx6ul.h
14
create mode 100644 hw/arm/fsl-imx6ul.c
15
21
16
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
22
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
17
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Makefile.objs
24
--- a/hw/arm/musicpal.c
19
+++ b/hw/arm/Makefile.objs
25
+++ b/hw/arm/musicpal.c
20
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
21
obj-$(CONFIG_IOTKIT) += iotkit.o
22
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
23
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
24
+obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o
25
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
26
new file mode 100644
27
index XXXXXXX..XXXXXXX
28
--- /dev/null
29
+++ b/include/hw/arm/fsl-imx6ul.h
30
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@
31
+/*
27
#include "ui/console.h"
32
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
28
#include "hw/i2c/i2c.h"
33
+ *
29
#include "hw/irq.h"
34
+ * i.MX6ul SoC definitions
30
+#include "hw/or-irq.h"
35
+ *
31
#include "hw/audio/wm8750.h"
36
+ * This program is free software; you can redistribute it and/or modify
32
#include "sysemu/block-backend.h"
37
+ * it under the terms of the GNU General Public License as published by
33
#include "sysemu/runstate.h"
38
+ * the Free Software Foundation; either version 2 of the License, or
34
@@ -XXX,XX +XXX,XX @@
39
+ * (at your option) any later version.
35
#define MP_TIMER4_IRQ 7
40
+ *
36
#define MP_EHCI_IRQ 8
41
+ * This program is distributed in the hope that it will be useful,
37
#define MP_ETH_IRQ 9
42
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
38
-#define MP_UART1_IRQ 11
43
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
39
-#define MP_UART2_IRQ 11
44
+ * GNU General Public License for more details.
40
+#define MP_UART_SHARED_IRQ 11
45
+ */
41
#define MP_GPIO_IRQ 12
42
#define MP_RTC_IRQ 28
43
#define MP_AUDIO_IRQ 30
44
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
45
ARMCPU *cpu;
46
qemu_irq pic[32];
47
DeviceState *dev;
48
+ DeviceState *uart_orgate;
49
DeviceState *i2c_dev;
50
DeviceState *lcd_dev;
51
DeviceState *key_dev;
52
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
53
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
54
pic[MP_TIMER4_IRQ], NULL);
55
56
- serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
57
+ /* Logically OR both UART IRQs together */
58
+ uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
59
+ object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
60
+ qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
61
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
46
+
62
+
47
+#ifndef FSL_IMX6UL_H
63
+ serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
48
+#define FSL_IMX6UL_H
64
+ qdev_get_gpio_in(uart_orgate, 0),
49
+
65
1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN);
50
+#include "hw/arm/arm.h"
66
- serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
51
+#include "hw/cpu/a15mpcore.h"
67
+ serial_mm_init(address_space_mem, MP_UART2_BASE, 2,
52
+#include "hw/misc/imx6ul_ccm.h"
68
+ qdev_get_gpio_in(uart_orgate, 1),
53
+#include "hw/misc/imx6_src.h"
69
1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN);
54
+#include "hw/misc/imx7_snvs.h"
70
55
+#include "hw/misc/imx7_gpr.h"
71
/* Register flash */
56
+#include "hw/intc/imx_gpcv2.h"
72
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
57
+#include "hw/misc/imx2_wdt.h"
58
+#include "hw/gpio/imx_gpio.h"
59
+#include "hw/char/imx_serial.h"
60
+#include "hw/timer/imx_gpt.h"
61
+#include "hw/timer/imx_epit.h"
62
+#include "hw/i2c/imx_i2c.h"
63
+#include "hw/gpio/imx_gpio.h"
64
+#include "hw/sd/sdhci.h"
65
+#include "hw/ssi/imx_spi.h"
66
+#include "hw/net/imx_fec.h"
67
+#include "exec/memory.h"
68
+#include "cpu.h"
69
+
70
+#define TYPE_FSL_IMX6UL "fsl,imx6ul"
71
+#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL)
72
+
73
+enum FslIMX6ULConfiguration {
74
+ FSL_IMX6UL_NUM_CPUS = 1,
75
+ FSL_IMX6UL_NUM_UARTS = 8,
76
+ FSL_IMX6UL_NUM_ETHS = 2,
77
+ FSL_IMX6UL_ETH_NUM_TX_RINGS = 2,
78
+ FSL_IMX6UL_NUM_USDHCS = 2,
79
+ FSL_IMX6UL_NUM_WDTS = 3,
80
+ FSL_IMX6UL_NUM_GPTS = 2,
81
+ FSL_IMX6UL_NUM_EPITS = 2,
82
+ FSL_IMX6UL_NUM_IOMUXCS = 2,
83
+ FSL_IMX6UL_NUM_GPIOS = 5,
84
+ FSL_IMX6UL_NUM_I2CS = 4,
85
+ FSL_IMX6UL_NUM_ECSPIS = 4,
86
+ FSL_IMX6UL_NUM_ADCS = 2,
87
+};
88
+
89
+typedef struct FslIMX6ULState {
90
+ /*< private >*/
91
+ DeviceState parent_obj;
92
+
93
+ /*< public >*/
94
+ ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
95
+ A15MPPrivState a7mpcore;
96
+ IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
97
+ IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
98
+ IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS];
99
+ IMX6ULCCMState ccm;
100
+ IMX6SRCState src;
101
+ IMX7SNVSState snvs;
102
+ IMXGPCv2State gpcv2;
103
+ IMX7GPRState gpr;
104
+ IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
105
+ IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
106
+ IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
107
+ IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
108
+ SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
109
+ IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
110
+ MemoryRegion rom;
111
+ MemoryRegion caam;
112
+ MemoryRegion ocram;
113
+ MemoryRegion ocram_alias;
114
+} FslIMX6ULState;
115
+
116
+enum FslIMX6ULMemoryMap {
117
+ FSL_IMX6UL_MMDC_ADDR = 0x80000000,
118
+ FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
119
+
120
+ FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
121
+ FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
122
+ FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
123
+ FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
124
+ FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
125
+
126
+ /* AIPS-2 */
127
+ FSL_IMX6UL_UART6_ADDR = 0x021FC000,
128
+ FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
129
+ FSL_IMX6UL_UART5_ADDR = 0x021F4000,
130
+ FSL_IMX6UL_UART4_ADDR = 0x021F0000,
131
+ FSL_IMX6UL_UART3_ADDR = 0x021EC000,
132
+ FSL_IMX6UL_UART2_ADDR = 0x021E8000,
133
+ FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
134
+ FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
135
+ FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
136
+ FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
137
+ FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
138
+ FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
139
+ FSL_IMX6UL_PXP_ADDR = 0x021CC000,
140
+ FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
141
+ FSL_IMX6UL_CSI_ADDR = 0x021C4000,
142
+ FSL_IMX6UL_CSU_ADDR = 0x021C0000,
143
+ FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
144
+ FSL_IMX6UL_EIM_ADDR = 0x021B8000,
145
+ FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
146
+ FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
147
+ FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
148
+ FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
149
+ FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
150
+ FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
151
+ FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
152
+ FSL_IMX6UL_ADC1_ADDR = 0x02198000,
153
+ FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
154
+ FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
155
+ FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
156
+ FSL_IMX6UL_ENET1_ADDR = 0x02188000,
157
+ FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
158
+ FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
159
+ FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
160
+ FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
161
+ FSL_IMX6UL_CAAM_ADDR = 0x02140000,
162
+ FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
163
+
164
+ /* AIPS-1 */
165
+ FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
166
+ FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
167
+ FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
168
+ FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
169
+ FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
170
+ FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
171
+ FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
172
+ FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
173
+ FSL_IMX6UL_GPC_ADDR = 0x020DC000,
174
+ FSL_IMX6UL_SRC_ADDR = 0x020D8000,
175
+ FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
176
+ FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
177
+ FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
178
+ FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
179
+ FSL_IMX6UL_CCM_ADDR = 0x020C4000,
180
+ FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
181
+ FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
182
+ FSL_IMX6UL_KPP_ADDR = 0x020B8000,
183
+ FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
184
+ FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
185
+ FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
186
+ FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
187
+ FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
188
+ FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
189
+ FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
190
+ FSL_IMX6UL_GPT1_ADDR = 0x02098000,
191
+ FSL_IMX6UL_CAN2_ADDR = 0x02094000,
192
+ FSL_IMX6UL_CAN1_ADDR = 0x02090000,
193
+ FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
194
+ FSL_IMX6UL_PWM3_ADDR = 0x02088000,
195
+ FSL_IMX6UL_PWM2_ADDR = 0x02084000,
196
+ FSL_IMX6UL_PWM1_ADDR = 0x02080000,
197
+ FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
198
+ FSL_IMX6UL_BEE_ADDR = 0x02044000,
199
+ FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
200
+ FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
201
+ FSL_IMX6UL_ASRC_ADDR = 0x02034000,
202
+ FSL_IMX6UL_SAI3_ADDR = 0x02030000,
203
+ FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
204
+ FSL_IMX6UL_SAI1_ADDR = 0x02028000,
205
+ FSL_IMX6UL_UART8_ADDR = 0x02024000,
206
+ FSL_IMX6UL_UART1_ADDR = 0x02020000,
207
+ FSL_IMX6UL_UART7_ADDR = 0x02018000,
208
+ FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
209
+ FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
210
+ FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
211
+ FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
212
+ FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
213
+
214
+ FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
215
+ FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
216
+
217
+ FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
218
+
219
+ FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
220
+ FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
221
+ FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
222
+ FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
223
+ FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
224
+ FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
225
+ FSL_IMX6UL_ROM_ADDR = 0x00000000,
226
+ FSL_IMX6UL_ROM_SIZE = 0x00018000,
227
+};
228
+
229
+enum FslIMX6ULIRQs {
230
+ FSL_IMX6UL_IOMUXC_IRQ = 0,
231
+ FSL_IMX6UL_DAP_IRQ = 1,
232
+ FSL_IMX6UL_SDMA_IRQ = 2,
233
+ FSL_IMX6UL_TSC_IRQ = 3,
234
+ FSL_IMX6UL_SNVS_IRQ = 4,
235
+ FSL_IMX6UL_LCDIF_IRQ = 5,
236
+ FSL_IMX6UL_BEE_IRQ = 6,
237
+ FSL_IMX6UL_CSI_IRQ = 7,
238
+ FSL_IMX6UL_PXP_IRQ = 8,
239
+ FSL_IMX6UL_SCTR1_IRQ = 9,
240
+ FSL_IMX6UL_SCTR2_IRQ = 10,
241
+ FSL_IMX6UL_WDOG3_IRQ = 11,
242
+ FSL_IMX6UL_APBH_DMA_IRQ = 13,
243
+ FSL_IMX6UL_WEIM_IRQ = 14,
244
+ FSL_IMX6UL_RAWNAND1_IRQ = 15,
245
+ FSL_IMX6UL_RAWNAND2_IRQ = 16,
246
+ FSL_IMX6UL_UART6_IRQ = 17,
247
+ FSL_IMX6UL_SRTC_IRQ = 19,
248
+ FSL_IMX6UL_SRTC_SEC_IRQ = 20,
249
+ FSL_IMX6UL_CSU_IRQ = 21,
250
+ FSL_IMX6UL_USDHC1_IRQ = 22,
251
+ FSL_IMX6UL_USDHC2_IRQ = 23,
252
+ FSL_IMX6UL_SAI3_IRQ = 24,
253
+ FSL_IMX6UL_SAI32_IRQ = 25,
254
+
255
+ FSL_IMX6UL_UART1_IRQ = 26,
256
+ FSL_IMX6UL_UART2_IRQ = 27,
257
+ FSL_IMX6UL_UART3_IRQ = 28,
258
+ FSL_IMX6UL_UART4_IRQ = 29,
259
+ FSL_IMX6UL_UART5_IRQ = 30,
260
+
261
+ FSL_IMX6UL_ECSPI1_IRQ = 31,
262
+ FSL_IMX6UL_ECSPI2_IRQ = 32,
263
+ FSL_IMX6UL_ECSPI3_IRQ = 33,
264
+ FSL_IMX6UL_ECSPI4_IRQ = 34,
265
+
266
+ FSL_IMX6UL_I2C4_IRQ = 35,
267
+ FSL_IMX6UL_I2C1_IRQ = 36,
268
+ FSL_IMX6UL_I2C2_IRQ = 37,
269
+ FSL_IMX6UL_I2C3_IRQ = 38,
270
+
271
+ FSL_IMX6UL_UART7_IRQ = 39,
272
+ FSL_IMX6UL_UART8_IRQ = 40,
273
+
274
+ FSL_IMX6UL_USB1_IRQ = 42,
275
+ FSL_IMX6UL_USB2_IRQ = 43,
276
+ FSL_IMX6UL_USB_PHY1_IRQ = 44,
277
+ FSL_IMX6UL_USB_PHY2_IRQ = 44,
278
+
279
+ FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
280
+ FSL_IMX6UL_CAAM_ERR_IRQ = 47,
281
+ FSL_IMX6UL_CAAM_RTIC_IRQ = 48,
282
+ FSL_IMX6UL_TEMP_IRQ = 49,
283
+ FSL_IMX6UL_ASRC_IRQ = 50,
284
+ FSL_IMX6UL_SPDIF_IRQ = 52,
285
+ FSL_IMX6UL_PMU_REG_IRQ = 54,
286
+ FSL_IMX6UL_GPT1_IRQ = 55,
287
+
288
+ FSL_IMX6UL_EPIT1_IRQ = 56,
289
+ FSL_IMX6UL_EPIT2_IRQ = 57,
290
+
291
+ FSL_IMX6UL_GPIO1_INT7_IRQ = 58,
292
+ FSL_IMX6UL_GPIO1_INT6_IRQ = 59,
293
+ FSL_IMX6UL_GPIO1_INT5_IRQ = 60,
294
+ FSL_IMX6UL_GPIO1_INT4_IRQ = 61,
295
+ FSL_IMX6UL_GPIO1_INT3_IRQ = 62,
296
+ FSL_IMX6UL_GPIO1_INT2_IRQ = 63,
297
+ FSL_IMX6UL_GPIO1_INT1_IRQ = 64,
298
+ FSL_IMX6UL_GPIO1_INT0_IRQ = 65,
299
+ FSL_IMX6UL_GPIO1_LOW_IRQ = 66,
300
+ FSL_IMX6UL_GPIO1_HIGH_IRQ = 67,
301
+ FSL_IMX6UL_GPIO2_LOW_IRQ = 68,
302
+ FSL_IMX6UL_GPIO2_HIGH_IRQ = 69,
303
+ FSL_IMX6UL_GPIO3_LOW_IRQ = 70,
304
+ FSL_IMX6UL_GPIO3_HIGH_IRQ = 71,
305
+ FSL_IMX6UL_GPIO4_LOW_IRQ = 72,
306
+ FSL_IMX6UL_GPIO4_HIGH_IRQ = 73,
307
+ FSL_IMX6UL_GPIO5_LOW_IRQ = 74,
308
+ FSL_IMX6UL_GPIO5_HIGH_IRQ = 75,
309
+
310
+ FSL_IMX6UL_WDOG1_IRQ = 80,
311
+ FSL_IMX6UL_WDOG2_IRQ = 81,
312
+
313
+ FSL_IMX6UL_KPP_IRQ = 82,
314
+
315
+ FSL_IMX6UL_PWM1_IRQ = 83,
316
+ FSL_IMX6UL_PWM2_IRQ = 84,
317
+ FSL_IMX6UL_PWM3_IRQ = 85,
318
+ FSL_IMX6UL_PWM4_IRQ = 86,
319
+
320
+ FSL_IMX6UL_CCM1_IRQ = 87,
321
+ FSL_IMX6UL_CCM2_IRQ = 88,
322
+
323
+ FSL_IMX6UL_GPC_IRQ = 89,
324
+
325
+ FSL_IMX6UL_SRC_IRQ = 91,
326
+
327
+ FSL_IMX6UL_CPU_PERF_IRQ = 94,
328
+ FSL_IMX6UL_CPU_CTI_IRQ = 95,
329
+
330
+ FSL_IMX6UL_SRC_WDOG_IRQ = 96,
331
+
332
+ FSL_IMX6UL_SAI1_IRQ = 97,
333
+ FSL_IMX6UL_SAI2_IRQ = 98,
334
+
335
+ FSL_IMX6UL_ADC1_IRQ = 100,
336
+ FSL_IMX6UL_ADC2_IRQ = 101,
337
+
338
+ FSL_IMX6UL_SJC_IRQ = 104,
339
+
340
+ FSL_IMX6UL_CAAM_RING0_IRQ = 105,
341
+ FSL_IMX6UL_CAAM_RING1_IRQ = 106,
342
+
343
+ FSL_IMX6UL_QSPI_IRQ = 107,
344
+
345
+ FSL_IMX6UL_TZASC_IRQ = 108,
346
+
347
+ FSL_IMX6UL_GPT2_IRQ = 109,
348
+
349
+ FSL_IMX6UL_CAN1_IRQ = 110,
350
+ FSL_IMX6UL_CAN2_IRQ = 111,
351
+
352
+ FSL_IMX6UL_SIM1_IRQ = 112,
353
+ FSL_IMX6UL_SIM2_IRQ = 113,
354
+
355
+ FSL_IMX6UL_PWM5_IRQ = 114,
356
+ FSL_IMX6UL_PWM6_IRQ = 115,
357
+ FSL_IMX6UL_PWM7_IRQ = 116,
358
+ FSL_IMX6UL_PWM8_IRQ = 117,
359
+
360
+ FSL_IMX6UL_ENET1_IRQ = 118,
361
+ FSL_IMX6UL_ENET1_TIMER_IRQ = 119,
362
+ FSL_IMX6UL_ENET2_IRQ = 120,
363
+ FSL_IMX6UL_ENET2_TIMER_IRQ = 121,
364
+
365
+ FSL_IMX6UL_PMU_CORE_IRQ = 127,
366
+ FSL_IMX6UL_MAX_IRQ = 128,
367
+};
368
+
369
+#endif /* FSL_IMX6UL_H */
370
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
371
new file mode 100644
372
index XXXXXXX..XXXXXXX
373
--- /dev/null
374
+++ b/hw/arm/fsl-imx6ul.c
375
@@ -XXX,XX +XXX,XX @@
376
+/*
377
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
378
+ *
379
+ * i.MX6UL SOC emulation.
380
+ *
381
+ * Based on hw/arm/fsl-imx7.c
382
+ *
383
+ * This program is free software; you can redistribute it and/or modify
384
+ * it under the terms of the GNU General Public License as published by
385
+ * the Free Software Foundation; either version 2 of the License, or
386
+ * (at your option) any later version.
387
+ *
388
+ * This program is distributed in the hope that it will be useful,
389
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
390
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
391
+ * GNU General Public License for more details.
392
+ */
393
+
394
+#include "qemu/osdep.h"
395
+#include "qapi/error.h"
396
+#include "qemu-common.h"
397
+#include "hw/arm/fsl-imx6ul.h"
398
+#include "hw/misc/unimp.h"
399
+#include "sysemu/sysemu.h"
400
+#include "qemu/error-report.h"
401
+
402
+#define NAME_SIZE 20
403
+
404
+static void fsl_imx6ul_init(Object *obj)
405
+{
406
+ FslIMX6ULState *s = FSL_IMX6UL(obj);
407
+ char name[NAME_SIZE];
408
+ int i;
409
+
410
+ for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) {
411
+ snprintf(name, NAME_SIZE, "cpu%d", i);
412
+ object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
413
+ "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
414
+ }
415
+
416
+ /*
417
+ * A7MPCORE
418
+ */
419
+ sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
420
+ TYPE_A15MPCORE_PRIV);
421
+
422
+ /*
423
+ * CCM
424
+ */
425
+ sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
426
+
427
+ /*
428
+ * SRC
429
+ */
430
+ sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
431
+
432
+ /*
433
+ * GPCv2
434
+ */
435
+ sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
436
+ TYPE_IMX_GPCV2);
437
+
438
+ /*
439
+ * SNVS
440
+ */
441
+ sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
442
+ TYPE_IMX7_SNVS);
443
+
444
+ /*
445
+ * GPR
446
+ */
447
+ sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
448
+ TYPE_IMX7_GPR);
449
+
450
+ /*
451
+ * GPIOs 1 to 5
452
+ */
453
+ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
454
+ snprintf(name, NAME_SIZE, "gpio%d", i);
455
+ sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
456
+ TYPE_IMX_GPIO);
457
+ }
458
+
459
+ /*
460
+ * GPT 1, 2
461
+ */
462
+ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
463
+ snprintf(name, NAME_SIZE, "gpt%d", i);
464
+ sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
465
+ TYPE_IMX7_GPT);
466
+ }
467
+
468
+ /*
469
+ * EPIT 1, 2
470
+ */
471
+ for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
472
+ snprintf(name, NAME_SIZE, "epit%d", i + 1);
473
+ sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
474
+ TYPE_IMX_EPIT);
475
+ }
476
+
477
+ /*
478
+ * eCSPI
479
+ */
480
+ for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
481
+ snprintf(name, NAME_SIZE, "spi%d", i + 1);
482
+ sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
483
+ TYPE_IMX_SPI);
484
+ }
485
+
486
+ /*
487
+ * I2C
488
+ */
489
+ for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
490
+ snprintf(name, NAME_SIZE, "i2c%d", i + 1);
491
+ sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
492
+ TYPE_IMX_I2C);
493
+ }
494
+
495
+ /*
496
+ * UART
497
+ */
498
+ for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
499
+ snprintf(name, NAME_SIZE, "uart%d", i);
500
+ sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
501
+ TYPE_IMX_SERIAL);
502
+ }
503
+
504
+ /*
505
+ * Ethernet
506
+ */
507
+ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
508
+ snprintf(name, NAME_SIZE, "eth%d", i);
509
+ sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
510
+ TYPE_IMX_ENET);
511
+ }
512
+
513
+ /*
514
+ * SDHCI
515
+ */
516
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
517
+ snprintf(name, NAME_SIZE, "usdhc%d", i);
518
+ sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
519
+ TYPE_IMX_USDHC);
520
+ }
521
+
522
+ /*
523
+ * Watchdog
524
+ */
525
+ for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
526
+ snprintf(name, NAME_SIZE, "wdt%d", i);
527
+ sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
528
+ TYPE_IMX2_WDT);
529
+ }
530
+}
531
+
532
+static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
533
+{
534
+ FslIMX6ULState *s = FSL_IMX6UL(dev);
535
+ int i;
536
+ qemu_irq irq;
537
+ char name[NAME_SIZE];
538
+
539
+ if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
540
+ error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
541
+ TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
542
+ return;
543
+ }
544
+
545
+ for (i = 0; i < smp_cpus; i++) {
546
+ Object *o = OBJECT(&s->cpu[i]);
547
+
548
+ object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
549
+ "psci-conduit", &error_abort);
550
+
551
+ /* On uniprocessor, the CBAR is set to 0 */
552
+ if (smp_cpus > 1) {
553
+ object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
554
+ "reset-cbar", &error_abort);
555
+ }
556
+
557
+ if (i) {
558
+ /* Secondary CPUs start in PSCI powered-down state */
559
+ object_property_set_bool(o, true,
560
+ "start-powered-off", &error_abort);
561
+ }
562
+
563
+ object_property_set_bool(o, true, "realized", &error_abort);
564
+ }
565
+
566
+ /*
567
+ * A7MPCORE
568
+ */
569
+ object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
570
+ &error_abort);
571
+ object_property_set_int(OBJECT(&s->a7mpcore),
572
+ FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
573
+ "num-irq", &error_abort);
574
+ object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
575
+ &error_abort);
576
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
577
+
578
+ for (i = 0; i < smp_cpus; i++) {
579
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
580
+ DeviceState *d = DEVICE(qemu_get_cpu(i));
581
+
582
+ irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
583
+ sysbus_connect_irq(sbd, i, irq);
584
+ sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
585
+ }
586
+
587
+ /*
588
+ * A7MPCORE DAP
589
+ */
590
+ create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
591
+ 0x100000);
592
+
593
+ /*
594
+ * GPT 1, 2
595
+ */
596
+ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
597
+ static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
598
+ FSL_IMX6UL_GPT1_ADDR,
599
+ FSL_IMX6UL_GPT2_ADDR,
600
+ };
601
+
602
+ static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
603
+ FSL_IMX6UL_GPT1_IRQ,
604
+ FSL_IMX6UL_GPT2_IRQ,
605
+ };
606
+
607
+ s->gpt[i].ccm = IMX_CCM(&s->ccm);
608
+ object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
609
+ &error_abort);
610
+
611
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
612
+ FSL_IMX6UL_GPTn_ADDR[i]);
613
+
614
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
615
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
616
+ FSL_IMX6UL_GPTn_IRQ[i]));
617
+ }
618
+
619
+ /*
620
+ * EPIT 1, 2
621
+ */
622
+ for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
623
+ static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
624
+ FSL_IMX6UL_EPIT1_ADDR,
625
+ FSL_IMX6UL_EPIT2_ADDR,
626
+ };
627
+
628
+ static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
629
+ FSL_IMX6UL_EPIT1_IRQ,
630
+ FSL_IMX6UL_EPIT2_IRQ,
631
+ };
632
+
633
+ s->epit[i].ccm = IMX_CCM(&s->ccm);
634
+ object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
635
+ &error_abort);
636
+
637
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
638
+ FSL_IMX6UL_EPITn_ADDR[i]);
639
+
640
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
641
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
642
+ FSL_IMX6UL_EPITn_IRQ[i]));
643
+ }
644
+
645
+ /*
646
+ * GPIO
647
+ */
648
+ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
649
+ static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
650
+ FSL_IMX6UL_GPIO1_ADDR,
651
+ FSL_IMX6UL_GPIO2_ADDR,
652
+ FSL_IMX6UL_GPIO3_ADDR,
653
+ FSL_IMX6UL_GPIO4_ADDR,
654
+ FSL_IMX6UL_GPIO5_ADDR,
655
+ };
656
+
657
+ static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
658
+ FSL_IMX6UL_GPIO1_LOW_IRQ,
659
+ FSL_IMX6UL_GPIO2_LOW_IRQ,
660
+ FSL_IMX6UL_GPIO3_LOW_IRQ,
661
+ FSL_IMX6UL_GPIO4_LOW_IRQ,
662
+ FSL_IMX6UL_GPIO5_LOW_IRQ,
663
+ };
664
+
665
+ static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
666
+ FSL_IMX6UL_GPIO1_HIGH_IRQ,
667
+ FSL_IMX6UL_GPIO2_HIGH_IRQ,
668
+ FSL_IMX6UL_GPIO3_HIGH_IRQ,
669
+ FSL_IMX6UL_GPIO4_HIGH_IRQ,
670
+ FSL_IMX6UL_GPIO5_HIGH_IRQ,
671
+ };
672
+
673
+ object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
674
+ &error_abort);
675
+
676
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
677
+ FSL_IMX6UL_GPIOn_ADDR[i]);
678
+
679
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
680
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
681
+ FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
682
+
683
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
684
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
685
+ FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
686
+ }
687
+
688
+ /*
689
+ * IOMUXC and IOMUXC_GPR
690
+ */
691
+ for (i = 0; i < 1; i++) {
692
+ static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
693
+ FSL_IMX6UL_IOMUXC_ADDR,
694
+ FSL_IMX6UL_IOMUXC_GPR_ADDR,
695
+ };
696
+
697
+ snprintf(name, NAME_SIZE, "iomuxc%d", i);
698
+ create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
699
+ }
700
+
701
+ /*
702
+ * CCM
703
+ */
704
+ object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
705
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
706
+
707
+ /*
708
+ * SRC
709
+ */
710
+ object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
711
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
712
+
713
+ /*
714
+ * GPCv2
715
+ */
716
+ object_property_set_bool(OBJECT(&s->gpcv2), true,
717
+ "realized", &error_abort);
718
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
719
+
720
+ /* Initialize all ECSPI */
721
+ for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
722
+ static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
723
+ FSL_IMX6UL_ECSPI1_ADDR,
724
+ FSL_IMX6UL_ECSPI2_ADDR,
725
+ FSL_IMX6UL_ECSPI3_ADDR,
726
+ FSL_IMX6UL_ECSPI4_ADDR,
727
+ };
728
+
729
+ static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
730
+ FSL_IMX6UL_ECSPI1_IRQ,
731
+ FSL_IMX6UL_ECSPI2_IRQ,
732
+ FSL_IMX6UL_ECSPI3_IRQ,
733
+ FSL_IMX6UL_ECSPI4_IRQ,
734
+ };
735
+
736
+ /* Initialize the SPI */
737
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
738
+ &error_abort);
739
+
740
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
741
+ FSL_IMX6UL_SPIn_ADDR[i]);
742
+
743
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
744
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
745
+ FSL_IMX6UL_SPIn_IRQ[i]));
746
+ }
747
+
748
+ /*
749
+ * I2C
750
+ */
751
+ for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
752
+ static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
753
+ FSL_IMX6UL_I2C1_ADDR,
754
+ FSL_IMX6UL_I2C2_ADDR,
755
+ FSL_IMX6UL_I2C3_ADDR,
756
+ FSL_IMX6UL_I2C4_ADDR,
757
+ };
758
+
759
+ static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
760
+ FSL_IMX6UL_I2C1_IRQ,
761
+ FSL_IMX6UL_I2C2_IRQ,
762
+ FSL_IMX6UL_I2C3_IRQ,
763
+ FSL_IMX6UL_I2C4_IRQ,
764
+ };
765
+
766
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
767
+ &error_abort);
768
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
769
+
770
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
771
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
772
+ FSL_IMX6UL_I2Cn_IRQ[i]));
773
+ }
774
+
775
+ /*
776
+ * UART
777
+ */
778
+ for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
779
+ static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
780
+ FSL_IMX6UL_UART1_ADDR,
781
+ FSL_IMX6UL_UART2_ADDR,
782
+ FSL_IMX6UL_UART3_ADDR,
783
+ FSL_IMX6UL_UART4_ADDR,
784
+ FSL_IMX6UL_UART5_ADDR,
785
+ FSL_IMX6UL_UART6_ADDR,
786
+ FSL_IMX6UL_UART7_ADDR,
787
+ FSL_IMX6UL_UART8_ADDR,
788
+ };
789
+
790
+ static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
791
+ FSL_IMX6UL_UART1_IRQ,
792
+ FSL_IMX6UL_UART2_IRQ,
793
+ FSL_IMX6UL_UART3_IRQ,
794
+ FSL_IMX6UL_UART4_IRQ,
795
+ FSL_IMX6UL_UART5_IRQ,
796
+ FSL_IMX6UL_UART6_IRQ,
797
+ FSL_IMX6UL_UART7_IRQ,
798
+ FSL_IMX6UL_UART8_IRQ,
799
+ };
800
+
801
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
802
+
803
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
804
+ &error_abort);
805
+
806
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
807
+ FSL_IMX6UL_UARTn_ADDR[i]);
808
+
809
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
810
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
811
+ FSL_IMX6UL_UARTn_IRQ[i]));
812
+ }
813
+
814
+ /*
815
+ * Ethernet
816
+ */
817
+ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
818
+ static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
819
+ FSL_IMX6UL_ENET1_ADDR,
820
+ FSL_IMX6UL_ENET2_ADDR,
821
+ };
822
+
823
+ static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
824
+ FSL_IMX6UL_ENET1_IRQ,
825
+ FSL_IMX6UL_ENET2_IRQ,
826
+ };
827
+
828
+ static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
829
+ FSL_IMX6UL_ENET1_TIMER_IRQ,
830
+ FSL_IMX6UL_ENET2_TIMER_IRQ,
831
+ };
832
+
833
+ object_property_set_uint(OBJECT(&s->eth[i]),
834
+ FSL_IMX6UL_ETH_NUM_TX_RINGS,
835
+ "tx-ring-num", &error_abort);
836
+ qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
837
+ object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
838
+ &error_abort);
839
+
840
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
841
+ FSL_IMX6UL_ENETn_ADDR[i]);
842
+
843
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
844
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
845
+ FSL_IMX6UL_ENETn_IRQ[i]));
846
+
847
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
848
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
849
+ FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
850
+ }
851
+
852
+ /*
853
+ * USDHC
854
+ */
855
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
856
+ static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
857
+ FSL_IMX6UL_USDHC1_ADDR,
858
+ FSL_IMX6UL_USDHC2_ADDR,
859
+ };
860
+
861
+ static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
862
+ FSL_IMX6UL_USDHC1_IRQ,
863
+ FSL_IMX6UL_USDHC2_IRQ,
864
+ };
865
+
866
+ object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
867
+ &error_abort);
868
+
869
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
870
+ FSL_IMX6UL_USDHCn_ADDR[i]);
871
+
872
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
873
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
874
+ FSL_IMX6UL_USDHCn_IRQ[i]));
875
+ }
876
+
877
+ /*
878
+ * SNVS
879
+ */
880
+ object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
881
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
882
+
883
+ /*
884
+ * Watchdog
885
+ */
886
+ for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
887
+ static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
888
+ FSL_IMX6UL_WDOG1_ADDR,
889
+ FSL_IMX6UL_WDOG2_ADDR,
890
+ FSL_IMX6UL_WDOG3_ADDR,
891
+ };
892
+
893
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
894
+ &error_abort);
895
+
896
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
897
+ FSL_IMX6UL_WDOGn_ADDR[i]);
898
+ }
899
+
900
+ /*
901
+ * GPR
902
+ */
903
+ object_property_set_bool(OBJECT(&s->gpr), true, "realized",
904
+ &error_abort);
905
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
906
+
907
+ /*
908
+ * SDMA
909
+ */
910
+ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
911
+
912
+ /*
913
+ * APHB_DMA
914
+ */
915
+ create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
916
+ FSL_IMX6UL_APBH_DMA_SIZE);
917
+
918
+ /*
919
+ * ADCs
920
+ */
921
+ for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
922
+ static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
923
+ FSL_IMX6UL_ADC1_ADDR,
924
+ FSL_IMX6UL_ADC2_ADDR,
925
+ };
926
+
927
+ snprintf(name, NAME_SIZE, "adc%d", i);
928
+ create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
929
+ }
930
+
931
+ /*
932
+ * LCD
933
+ */
934
+ create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
935
+
936
+ /*
937
+ * ROM memory
938
+ */
939
+ memory_region_init_rom(&s->rom, NULL, "imx6ul.rom",
940
+ FSL_IMX6UL_ROM_SIZE, &error_abort);
941
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
942
+ &s->rom);
943
+
944
+ /*
945
+ * CAAM memory
946
+ */
947
+ memory_region_init_rom(&s->caam, NULL, "imx6ul.caam",
948
+ FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
949
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
950
+ &s->caam);
951
+
952
+ /*
953
+ * OCRAM memory
954
+ */
955
+ memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
956
+ FSL_IMX6UL_OCRAM_MEM_SIZE,
957
+ &error_abort);
958
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
959
+ &s->ocram);
960
+
961
+ /*
962
+ * internal OCRAM (128 KB) is aliased over 512 KB
963
+ */
964
+ memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias",
965
+ &s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE);
966
+ memory_region_add_subregion(get_system_memory(),
967
+ FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
968
+}
969
+
970
+static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
971
+{
972
+ DeviceClass *dc = DEVICE_CLASS(oc);
973
+
974
+ dc->realize = fsl_imx6ul_realize;
975
+ dc->desc = "i.MX6UL SOC";
976
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
977
+ dc->user_creatable = false;
978
+}
979
+
980
+static const TypeInfo fsl_imx6ul_type_info = {
981
+ .name = TYPE_FSL_IMX6UL,
982
+ .parent = TYPE_DEVICE,
983
+ .instance_size = sizeof(FslIMX6ULState),
984
+ .instance_init = fsl_imx6ul_init,
985
+ .class_init = fsl_imx6ul_class_init,
986
+};
987
+
988
+static void fsl_imx6ul_register_types(void)
989
+{
990
+ type_register_static(&fsl_imx6ul_type_info);
991
+}
992
+type_init(fsl_imx6ul_register_types)
993
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
994
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
995
--- a/default-configs/arm-softmmu.mak
74
--- a/hw/arm/Kconfig
996
+++ b/default-configs/arm-softmmu.mak
75
+++ b/hw/arm/Kconfig
997
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX6=y
76
@@ -XXX,XX +XXX,XX @@ config MUSCA
998
CONFIG_FSL_IMX31=y
77
999
CONFIG_FSL_IMX25=y
78
config MUSICPAL
1000
CONFIG_FSL_IMX7=y
79
bool
1001
+CONFIG_FSL_IMX6UL=y
80
+ select OR_IRQ
1002
81
select BITBANG_I2C
1003
CONFIG_IMX_I2C=y
82
select MARVELL_88W8618
1004
83
select PTIMER
1005
--
84
--
1006
2.18.0
85
2.20.1
1007
86
1008
87
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/30] i.MX6UL: Add i.MX6UL specific CCM device
[PULL 13/16] hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
3
We don't need to fill the full pic[] array if we only use
4
Message-id: 34b6704ceb81b49e35ce1ad162bf758e5141ff87.1532984236.git.jcd@tribudubois.net
4
few of the interrupt lines. Directly call qdev_get_gpio_in()
5
[PMM: fixed some comment typos etc]
5
when necessary.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20201107193403.436146-6-f4bug@amsat.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
11
---
9
hw/misc/Makefile.objs | 1 +
12
hw/arm/musicpal.c | 25 +++++++++++++------------
10
include/hw/misc/imx6ul_ccm.h | 226 +++++++++
13
1 file changed, 13 insertions(+), 12 deletions(-)
11
hw/misc/imx6ul_ccm.c | 886 +++++++++++++++++++++++++++++++++++
12
hw/misc/trace-events | 7 +
13
4 files changed, 1120 insertions(+)
14
create mode 100644 include/hw/misc/imx6ul_ccm.h
15
create mode 100644 hw/misc/imx6ul_ccm.c
16
14
17
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/Makefile.objs
17
--- a/hw/arm/musicpal.c
20
+++ b/hw/misc/Makefile.objs
18
+++ b/hw/arm/musicpal.c
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IMX) += imx_ccm.o
19
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = {
22
obj-$(CONFIG_IMX) += imx31_ccm.o
20
static void musicpal_init(MachineState *machine)
23
obj-$(CONFIG_IMX) += imx25_ccm.o
21
{
24
obj-$(CONFIG_IMX) += imx6_ccm.o
22
ARMCPU *cpu;
25
+obj-$(CONFIG_IMX) += imx6ul_ccm.o
23
- qemu_irq pic[32];
26
obj-$(CONFIG_IMX) += imx6_src.o
24
DeviceState *dev;
27
obj-$(CONFIG_IMX) += imx7_ccm.o
25
+ DeviceState *pic;
28
obj-$(CONFIG_IMX) += imx2_wdt.o
26
DeviceState *uart_orgate;
29
diff --git a/include/hw/misc/imx6ul_ccm.h b/include/hw/misc/imx6ul_ccm.h
27
DeviceState *i2c_dev;
30
new file mode 100644
28
DeviceState *lcd_dev;
31
index XXXXXXX..XXXXXXX
29
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
32
--- /dev/null
30
&error_fatal);
33
+++ b/include/hw/misc/imx6ul_ccm.h
31
memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
34
@@ -XXX,XX +XXX,XX @@
32
35
+/*
33
- dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
36
+ * IMX6UL Clock Control Module
34
+ pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE,
37
+ *
35
qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
38
+ * Copyright (C) 2018 by Jean-Christophe Dubois <jcd@tribudubois.net>
36
- for (i = 0; i < 32; i++) {
39
+ *
37
- pic[i] = qdev_get_gpio_in(dev, i);
40
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
38
- }
41
+ * See the COPYING file in the top-level directory.
39
- sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ],
42
+ */
40
- pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
43
+
41
- pic[MP_TIMER4_IRQ], NULL);
44
+#ifndef IMX6UL_CCM_H
42
+ sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE,
45
+#define IMX6UL_CCM_H
43
+ qdev_get_gpio_in(pic, MP_TIMER1_IRQ),
46
+
44
+ qdev_get_gpio_in(pic, MP_TIMER2_IRQ),
47
+#include "hw/misc/imx_ccm.h"
45
+ qdev_get_gpio_in(pic, MP_TIMER3_IRQ),
48
+#include "qemu/bitops.h"
46
+ qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL);
49
+
47
50
+#define CCM_CCR 0
48
/* Logically OR both UART IRQs together */
51
+#define CCM_CCDR 1
49
uart_orgate = DEVICE(object_new(TYPE_OR_IRQ));
52
+#define CCM_CSR 2
50
object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal);
53
+#define CCM_CCSR 3
51
qdev_realize_and_unref(uart_orgate, NULL, &error_fatal);
54
+#define CCM_CACRR 4
52
- qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]);
55
+#define CCM_CBCDR 5
53
+ qdev_connect_gpio_out(DEVICE(uart_orgate), 0,
56
+#define CCM_CBCMR 6
54
+ qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ));
57
+#define CCM_CSCMR1 7
55
58
+#define CCM_CSCMR2 8
56
serial_mm_init(address_space_mem, MP_UART1_BASE, 2,
59
+#define CCM_CSCDR1 9
57
qdev_get_gpio_in(uart_orgate, 0),
60
+#define CCM_CS1CDR 10
58
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
61
+#define CCM_CS2CDR 11
59
OBJECT(get_system_memory()), &error_fatal);
62
+#define CCM_CDCDR 12
60
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
63
+#define CCM_CHSCCDR 13
61
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
64
+#define CCM_CSCDR2 14
62
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);
65
+#define CCM_CSCDR3 15
63
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
66
+#define CCM_CDHIPR 18
64
+ qdev_get_gpio_in(pic, MP_ETH_IRQ));
67
+#define CCM_CTOR 20
65
68
+#define CCM_CLPCR 21
66
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
69
+#define CCM_CISR 22
67
70
+#define CCM_CIMR 23
68
sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL);
71
+#define CCM_CCOSR 24
69
72
+#define CCM_CGPR 25
70
dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE,
73
+#define CCM_CCGR0 26
71
- pic[MP_GPIO_IRQ]);
74
+#define CCM_CCGR1 27
72
+ qdev_get_gpio_in(pic, MP_GPIO_IRQ));
75
+#define CCM_CCGR2 28
73
i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
76
+#define CCM_CCGR3 29
74
i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c");
77
+#define CCM_CCGR4 30
75
78
+#define CCM_CCGR5 31
76
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
79
+#define CCM_CCGR6 32
77
NULL);
80
+#define CCM_CMEOR 34
78
sysbus_realize_and_unref(s, &error_fatal);
81
+#define CCM_MAX 35
79
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
82
+
80
- sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
83
+#define CCM_ANALOG_PLL_ARM 0
81
+ sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ));
84
+#define CCM_ANALOG_PLL_ARM_SET 1
82
85
+#define CCM_ANALOG_PLL_ARM_CLR 2
83
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
86
+#define CCM_ANALOG_PLL_ARM_TOG 3
84
arm_load_kernel(cpu, machine, &musicpal_binfo);
87
+#define CCM_ANALOG_PLL_USB1 4
88
+#define CCM_ANALOG_PLL_USB1_SET 5
89
+#define CCM_ANALOG_PLL_USB1_CLR 6
90
+#define CCM_ANALOG_PLL_USB1_TOG 7
91
+#define CCM_ANALOG_PLL_USB2 8
92
+#define CCM_ANALOG_PLL_USB2_SET 9
93
+#define CCM_ANALOG_PLL_USB2_CLR 10
94
+#define CCM_ANALOG_PLL_USB2_TOG 11
95
+#define CCM_ANALOG_PLL_SYS 12
96
+#define CCM_ANALOG_PLL_SYS_SET 13
97
+#define CCM_ANALOG_PLL_SYS_CLR 14
98
+#define CCM_ANALOG_PLL_SYS_TOG 15
99
+#define CCM_ANALOG_PLL_SYS_SS 16
100
+#define CCM_ANALOG_PLL_SYS_NUM 20
101
+#define CCM_ANALOG_PLL_SYS_DENOM 24
102
+#define CCM_ANALOG_PLL_AUDIO 28
103
+#define CCM_ANALOG_PLL_AUDIO_SET 29
104
+#define CCM_ANALOG_PLL_AUDIO_CLR 30
105
+#define CCM_ANALOG_PLL_AUDIO_TOG 31
106
+#define CCM_ANALOG_PLL_AUDIO_NUM 32
107
+#define CCM_ANALOG_PLL_AUDIO_DENOM 36
108
+#define CCM_ANALOG_PLL_VIDEO 40
109
+#define CCM_ANALOG_PLL_VIDEO_SET 41
110
+#define CCM_ANALOG_PLL_VIDEO_CLR 42
111
+#define CCM_ANALOG_PLL_VIDEO_TOG 44
112
+#define CCM_ANALOG_PLL_VIDEO_NUM 46
113
+#define CCM_ANALOG_PLL_VIDEO_DENOM 48
114
+#define CCM_ANALOG_PLL_ENET 56
115
+#define CCM_ANALOG_PLL_ENET_SET 57
116
+#define CCM_ANALOG_PLL_ENET_CLR 58
117
+#define CCM_ANALOG_PLL_ENET_TOG 59
118
+#define CCM_ANALOG_PFD_480 60
119
+#define CCM_ANALOG_PFD_480_SET 61
120
+#define CCM_ANALOG_PFD_480_CLR 62
121
+#define CCM_ANALOG_PFD_480_TOG 63
122
+#define CCM_ANALOG_PFD_528 64
123
+#define CCM_ANALOG_PFD_528_SET 65
124
+#define CCM_ANALOG_PFD_528_CLR 66
125
+#define CCM_ANALOG_PFD_528_TOG 67
126
+
127
+/* PMU registers */
128
+#define PMU_REG_1P1 68
129
+#define PMU_REG_3P0 72
130
+#define PMU_REG_2P5 76
131
+#define PMU_REG_CORE 80
132
+
133
+#define CCM_ANALOG_MISC0 84
134
+#define PMU_MISC0 CCM_ANALOG_MISC0
135
+#define CCM_ANALOG_MISC0_SET 85
136
+#define PMU_MISC0_SET CCM_ANALOG_MISC0_SET
137
+#define CCM_ANALOG_MISC0_CLR 86
138
+#define PMU_MISC0_CLR CCM_ANALOG_MISC0_CLR
139
+#define CCM_ANALOG_MISC0_TOG 87
140
+#define PMU_MISC0_TOG CCM_ANALOG_MISC0_TOG
141
+
142
+#define CCM_ANALOG_MISC1 88
143
+#define PMU_MISC1 CCM_ANALOG_MISC1
144
+#define CCM_ANALOG_MISC1_SET 89
145
+#define PMU_MISC1_SET CCM_ANALOG_MISC1_SET
146
+#define CCM_ANALOG_MISC1_CLR 90
147
+#define PMU_MISC1_CLR CCM_ANALOG_MISC1_CLR
148
+#define CCM_ANALOG_MISC1_TOG 91
149
+#define PMU_MISC1_TOG CCM_ANALOG_MISC1_TOG
150
+
151
+#define CCM_ANALOG_MISC2 92
152
+#define PMU_MISC2 CCM_ANALOG_MISC2
153
+#define CCM_ANALOG_MISC2_SET 93
154
+#define PMU_MISC2_SET CCM_ANALOG_MISC2_SET
155
+#define CCM_ANALOG_MISC2_CLR 94
156
+#define PMU_MISC2_CLR CCM_ANALOG_MISC2_CLR
157
+#define CCM_ANALOG_MISC2_TOG 95
158
+#define PMU_MISC2_TOG CCM_ANALOG_MISC2_TOG
159
+
160
+#define TEMPMON_TEMPSENSE0 96
161
+#define TEMPMON_TEMPSENSE0_SET 97
162
+#define TEMPMON_TEMPSENSE0_CLR 98
163
+#define TEMPMON_TEMPSENSE0_TOG 99
164
+#define TEMPMON_TEMPSENSE1 100
165
+#define TEMPMON_TEMPSENSE1_SET 101
166
+#define TEMPMON_TEMPSENSE1_CLR 102
167
+#define TEMPMON_TEMPSENSE1_TOG 103
168
+#define TEMPMON_TEMPSENSE2 164
169
+#define TEMPMON_TEMPSENSE2_SET 165
170
+#define TEMPMON_TEMPSENSE2_CLR 166
171
+#define TEMPMON_TEMPSENSE2_TOG 167
172
+
173
+#define PMU_LOWPWR_CTRL 155
174
+#define PMU_LOWPWR_CTRL_SET 156
175
+#define PMU_LOWPWR_CTRL_CLR 157
176
+#define PMU_LOWPWR_CTRL_TOG 158
177
+
178
+#define USB_ANALOG_USB1_VBUS_DETECT 104
179
+#define USB_ANALOG_USB1_VBUS_DETECT_SET 105
180
+#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106
181
+#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107
182
+#define USB_ANALOG_USB1_CHRG_DETECT 108
183
+#define USB_ANALOG_USB1_CHRG_DETECT_SET 109
184
+#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110
185
+#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111
186
+#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112
187
+#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116
188
+#define USB_ANALOG_USB1_MISC 124
189
+#define USB_ANALOG_USB1_MISC_SET 125
190
+#define USB_ANALOG_USB1_MISC_CLR 126
191
+#define USB_ANALOG_USB1_MISC_TOG 127
192
+#define USB_ANALOG_USB2_VBUS_DETECT 128
193
+#define USB_ANALOG_USB2_VBUS_DETECT_SET 129
194
+#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130
195
+#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131
196
+#define USB_ANALOG_USB2_CHRG_DETECT 132
197
+#define USB_ANALOG_USB2_CHRG_DETECT_SET 133
198
+#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134
199
+#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135
200
+#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136
201
+#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140
202
+#define USB_ANALOG_USB2_MISC 148
203
+#define USB_ANALOG_USB2_MISC_SET 149
204
+#define USB_ANALOG_USB2_MISC_CLR 150
205
+#define USB_ANALOG_USB2_MISC_TOG 151
206
+#define USB_ANALOG_DIGPROG 152
207
+#define CCM_ANALOG_MAX 4096
208
+
209
+/* CCM_CBCMR */
210
+#define R_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18)
211
+#define R_CBCMR_PRE_PERIPH_CLK_SEL_LENGTH (2)
212
+#define R_CBCMR_PERIPH_CLK2_SEL_SHIFT (12)
213
+#define R_CBCMR_PERIPH_CLK2_SEL_LENGTH (2)
214
+
215
+/* CCM_CBCDR */
216
+#define R_CBCDR_AHB_PODF_SHIFT (10)
217
+#define R_CBCDR_AHB_PODF_LENGTH (3)
218
+#define R_CBCDR_IPG_PODF_SHIFT (8)
219
+#define R_CBCDR_IPG_PODF_LENGTH (2)
220
+#define R_CBCDR_PERIPH_CLK_SEL_SHIFT (25)
221
+#define R_CBCDR_PERIPH_CLK_SEL_LENGTH (1)
222
+#define R_CBCDR_PERIPH_CLK2_PODF_SHIFT (27)
223
+#define R_CBCDR_PERIPH_CLK2_PODF_LENGTH (3)
224
+
225
+/* CCM_CSCMR1 */
226
+#define R_CSCMR1_PERCLK_PODF_SHIFT (0)
227
+#define R_CSCMR1_PERCLK_PODF_LENGTH (6)
228
+#define R_CSCMR1_PERCLK_CLK_SEL_SHIFT (6)
229
+#define R_CSCMR1_PERCLK_CLK_SEL_LENGTH (1)
230
+
231
+/* CCM_ANALOG_PFD_528 */
232
+#define R_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0)
233
+#define R_ANALOG_PFD_528_PFD0_FRAC_LENGTH (6)
234
+#define R_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16)
235
+#define R_ANALOG_PFD_528_PFD2_FRAC_LENGTH (6)
236
+
237
+/* CCM_ANALOG_PLL_SYS */
238
+#define R_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0)
239
+#define R_ANALOG_PLL_SYS_DIV_SELECT_LENGTH (1)
240
+
241
+#define CCM_ANALOG_PLL_LOCK (1 << 31);
242
+
243
+#define TYPE_IMX6UL_CCM "imx6ul.ccm"
244
+#define IMX6UL_CCM(obj) OBJECT_CHECK(IMX6ULCCMState, (obj), TYPE_IMX6UL_CCM)
245
+
246
+typedef struct IMX6ULCCMState {
247
+ /* <private> */
248
+ IMXCCMState parent_obj;
249
+
250
+ /* <public> */
251
+ MemoryRegion container;
252
+ MemoryRegion ioccm;
253
+ MemoryRegion ioanalog;
254
+
255
+ uint32_t ccm[CCM_MAX];
256
+ uint32_t analog[CCM_ANALOG_MAX];
257
+
258
+} IMX6ULCCMState;
259
+
260
+#endif /* IMX6UL_CCM_H */
261
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
262
new file mode 100644
263
index XXXXXXX..XXXXXXX
264
--- /dev/null
265
+++ b/hw/misc/imx6ul_ccm.c
266
@@ -XXX,XX +XXX,XX @@
267
+/*
268
+ * IMX6UL Clock Control Module
269
+ *
270
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
271
+ *
272
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
273
+ * See the COPYING file in the top-level directory.
274
+ *
275
+ * To get the timer frequencies right, we need to emulate at least part of
276
+ * the CCM.
277
+ */
278
+
279
+#include "qemu/osdep.h"
280
+#include "hw/registerfields.h"
281
+#include "hw/misc/imx6ul_ccm.h"
282
+#include "qemu/log.h"
283
+
284
+#include "trace.h"
285
+
286
+static const char *imx6ul_ccm_reg_name(uint32_t reg)
287
+{
288
+ static char unknown[20];
289
+
290
+ switch (reg) {
291
+ case CCM_CCR:
292
+ return "CCR";
293
+ case CCM_CCDR:
294
+ return "CCDR";
295
+ case CCM_CSR:
296
+ return "CSR";
297
+ case CCM_CCSR:
298
+ return "CCSR";
299
+ case CCM_CACRR:
300
+ return "CACRR";
301
+ case CCM_CBCDR:
302
+ return "CBCDR";
303
+ case CCM_CBCMR:
304
+ return "CBCMR";
305
+ case CCM_CSCMR1:
306
+ return "CSCMR1";
307
+ case CCM_CSCMR2:
308
+ return "CSCMR2";
309
+ case CCM_CSCDR1:
310
+ return "CSCDR1";
311
+ case CCM_CS1CDR:
312
+ return "CS1CDR";
313
+ case CCM_CS2CDR:
314
+ return "CS2CDR";
315
+ case CCM_CDCDR:
316
+ return "CDCDR";
317
+ case CCM_CHSCCDR:
318
+ return "CHSCCDR";
319
+ case CCM_CSCDR2:
320
+ return "CSCDR2";
321
+ case CCM_CSCDR3:
322
+ return "CSCDR3";
323
+ case CCM_CDHIPR:
324
+ return "CDHIPR";
325
+ case CCM_CTOR:
326
+ return "CTOR";
327
+ case CCM_CLPCR:
328
+ return "CLPCR";
329
+ case CCM_CISR:
330
+ return "CISR";
331
+ case CCM_CIMR:
332
+ return "CIMR";
333
+ case CCM_CCOSR:
334
+ return "CCOSR";
335
+ case CCM_CGPR:
336
+ return "CGPR";
337
+ case CCM_CCGR0:
338
+ return "CCGR0";
339
+ case CCM_CCGR1:
340
+ return "CCGR1";
341
+ case CCM_CCGR2:
342
+ return "CCGR2";
343
+ case CCM_CCGR3:
344
+ return "CCGR3";
345
+ case CCM_CCGR4:
346
+ return "CCGR4";
347
+ case CCM_CCGR5:
348
+ return "CCGR5";
349
+ case CCM_CCGR6:
350
+ return "CCGR6";
351
+ case CCM_CMEOR:
352
+ return "CMEOR";
353
+ default:
354
+ sprintf(unknown, "%d ?", reg);
355
+ return unknown;
356
+ }
357
+}
358
+
359
+static const char *imx6ul_analog_reg_name(uint32_t reg)
360
+{
361
+ static char unknown[20];
362
+
363
+ switch (reg) {
364
+ case CCM_ANALOG_PLL_ARM:
365
+ return "PLL_ARM";
366
+ case CCM_ANALOG_PLL_ARM_SET:
367
+ return "PLL_ARM_SET";
368
+ case CCM_ANALOG_PLL_ARM_CLR:
369
+ return "PLL_ARM_CLR";
370
+ case CCM_ANALOG_PLL_ARM_TOG:
371
+ return "PLL_ARM_TOG";
372
+ case CCM_ANALOG_PLL_USB1:
373
+ return "PLL_USB1";
374
+ case CCM_ANALOG_PLL_USB1_SET:
375
+ return "PLL_USB1_SET";
376
+ case CCM_ANALOG_PLL_USB1_CLR:
377
+ return "PLL_USB1_CLR";
378
+ case CCM_ANALOG_PLL_USB1_TOG:
379
+ return "PLL_USB1_TOG";
380
+ case CCM_ANALOG_PLL_USB2:
381
+ return "PLL_USB2";
382
+ case CCM_ANALOG_PLL_USB2_SET:
383
+ return "PLL_USB2_SET";
384
+ case CCM_ANALOG_PLL_USB2_CLR:
385
+ return "PLL_USB2_CLR";
386
+ case CCM_ANALOG_PLL_USB2_TOG:
387
+ return "PLL_USB2_TOG";
388
+ case CCM_ANALOG_PLL_SYS:
389
+ return "PLL_SYS";
390
+ case CCM_ANALOG_PLL_SYS_SET:
391
+ return "PLL_SYS_SET";
392
+ case CCM_ANALOG_PLL_SYS_CLR:
393
+ return "PLL_SYS_CLR";
394
+ case CCM_ANALOG_PLL_SYS_TOG:
395
+ return "PLL_SYS_TOG";
396
+ case CCM_ANALOG_PLL_SYS_SS:
397
+ return "PLL_SYS_SS";
398
+ case CCM_ANALOG_PLL_SYS_NUM:
399
+ return "PLL_SYS_NUM";
400
+ case CCM_ANALOG_PLL_SYS_DENOM:
401
+ return "PLL_SYS_DENOM";
402
+ case CCM_ANALOG_PLL_AUDIO:
403
+ return "PLL_AUDIO";
404
+ case CCM_ANALOG_PLL_AUDIO_SET:
405
+ return "PLL_AUDIO_SET";
406
+ case CCM_ANALOG_PLL_AUDIO_CLR:
407
+ return "PLL_AUDIO_CLR";
408
+ case CCM_ANALOG_PLL_AUDIO_TOG:
409
+ return "PLL_AUDIO_TOG";
410
+ case CCM_ANALOG_PLL_AUDIO_NUM:
411
+ return "PLL_AUDIO_NUM";
412
+ case CCM_ANALOG_PLL_AUDIO_DENOM:
413
+ return "PLL_AUDIO_DENOM";
414
+ case CCM_ANALOG_PLL_VIDEO:
415
+ return "PLL_VIDEO";
416
+ case CCM_ANALOG_PLL_VIDEO_SET:
417
+ return "PLL_VIDEO_SET";
418
+ case CCM_ANALOG_PLL_VIDEO_CLR:
419
+ return "PLL_VIDEO_CLR";
420
+ case CCM_ANALOG_PLL_VIDEO_TOG:
421
+ return "PLL_VIDEO_TOG";
422
+ case CCM_ANALOG_PLL_VIDEO_NUM:
423
+ return "PLL_VIDEO_NUM";
424
+ case CCM_ANALOG_PLL_VIDEO_DENOM:
425
+ return "PLL_VIDEO_DENOM";
426
+ case CCM_ANALOG_PLL_ENET:
427
+ return "PLL_ENET";
428
+ case CCM_ANALOG_PLL_ENET_SET:
429
+ return "PLL_ENET_SET";
430
+ case CCM_ANALOG_PLL_ENET_CLR:
431
+ return "PLL_ENET_CLR";
432
+ case CCM_ANALOG_PLL_ENET_TOG:
433
+ return "PLL_ENET_TOG";
434
+ case CCM_ANALOG_PFD_480:
435
+ return "PFD_480";
436
+ case CCM_ANALOG_PFD_480_SET:
437
+ return "PFD_480_SET";
438
+ case CCM_ANALOG_PFD_480_CLR:
439
+ return "PFD_480_CLR";
440
+ case CCM_ANALOG_PFD_480_TOG:
441
+ return "PFD_480_TOG";
442
+ case CCM_ANALOG_PFD_528:
443
+ return "PFD_528";
444
+ case CCM_ANALOG_PFD_528_SET:
445
+ return "PFD_528_SET";
446
+ case CCM_ANALOG_PFD_528_CLR:
447
+ return "PFD_528_CLR";
448
+ case CCM_ANALOG_PFD_528_TOG:
449
+ return "PFD_528_TOG";
450
+ case CCM_ANALOG_MISC0:
451
+ return "MISC0";
452
+ case CCM_ANALOG_MISC0_SET:
453
+ return "MISC0_SET";
454
+ case CCM_ANALOG_MISC0_CLR:
455
+ return "MISC0_CLR";
456
+ case CCM_ANALOG_MISC0_TOG:
457
+ return "MISC0_TOG";
458
+ case CCM_ANALOG_MISC2:
459
+ return "MISC2";
460
+ case CCM_ANALOG_MISC2_SET:
461
+ return "MISC2_SET";
462
+ case CCM_ANALOG_MISC2_CLR:
463
+ return "MISC2_CLR";
464
+ case CCM_ANALOG_MISC2_TOG:
465
+ return "MISC2_TOG";
466
+ case PMU_REG_1P1:
467
+ return "PMU_REG_1P1";
468
+ case PMU_REG_3P0:
469
+ return "PMU_REG_3P0";
470
+ case PMU_REG_2P5:
471
+ return "PMU_REG_2P5";
472
+ case PMU_REG_CORE:
473
+ return "PMU_REG_CORE";
474
+ case PMU_MISC1:
475
+ return "PMU_MISC1";
476
+ case PMU_MISC1_SET:
477
+ return "PMU_MISC1_SET";
478
+ case PMU_MISC1_CLR:
479
+ return "PMU_MISC1_CLR";
480
+ case PMU_MISC1_TOG:
481
+ return "PMU_MISC1_TOG";
482
+ case USB_ANALOG_DIGPROG:
483
+ return "USB_ANALOG_DIGPROG";
484
+ default:
485
+ sprintf(unknown, "%d ?", reg);
486
+ return unknown;
487
+ }
488
+}
489
+
490
+#define CKIH_FREQ 24000000 /* 24MHz crystal input */
491
+
492
+static const VMStateDescription vmstate_imx6ul_ccm = {
493
+ .name = TYPE_IMX6UL_CCM,
494
+ .version_id = 1,
495
+ .minimum_version_id = 1,
496
+ .fields = (VMStateField[]) {
497
+ VMSTATE_UINT32_ARRAY(ccm, IMX6ULCCMState, CCM_MAX),
498
+ VMSTATE_UINT32_ARRAY(analog, IMX6ULCCMState, CCM_ANALOG_MAX),
499
+ VMSTATE_END_OF_LIST()
500
+ },
501
+};
502
+
503
+static uint64_t imx6ul_analog_get_osc_clk(IMX6ULCCMState *dev)
504
+{
505
+ uint64_t freq = CKIH_FREQ;
506
+
507
+ trace_ccm_freq((uint32_t)freq);
508
+
509
+ return freq;
510
+}
511
+
512
+static uint64_t imx6ul_analog_get_pll2_clk(IMX6ULCCMState *dev)
513
+{
514
+ uint64_t freq = imx6ul_analog_get_osc_clk(dev);
515
+
516
+ if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS],
517
+ ANALOG_PLL_SYS, DIV_SELECT)) {
518
+ freq *= 22;
519
+ } else {
520
+ freq *= 20;
521
+ }
522
+
523
+ trace_ccm_freq((uint32_t)freq);
524
+
525
+ return freq;
526
+}
527
+
528
+static uint64_t imx6ul_analog_get_pll3_clk(IMX6ULCCMState *dev)
529
+{
530
+ uint64_t freq = imx6ul_analog_get_osc_clk(dev) * 20;
531
+
532
+ trace_ccm_freq((uint32_t)freq);
533
+
534
+ return freq;
535
+}
536
+
537
+static uint64_t imx6ul_analog_get_pll2_pfd0_clk(IMX6ULCCMState *dev)
538
+{
539
+ uint64_t freq = 0;
540
+
541
+ freq = imx6ul_analog_get_pll2_clk(dev) * 18
542
+ / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528],
543
+ ANALOG_PFD_528, PFD0_FRAC);
544
+
545
+ trace_ccm_freq((uint32_t)freq);
546
+
547
+ return freq;
548
+}
549
+
550
+static uint64_t imx6ul_analog_get_pll2_pfd2_clk(IMX6ULCCMState *dev)
551
+{
552
+ uint64_t freq = 0;
553
+
554
+ freq = imx6ul_analog_get_pll2_clk(dev) * 18
555
+ / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528],
556
+ ANALOG_PFD_528, PFD2_FRAC);
557
+
558
+ trace_ccm_freq((uint32_t)freq);
559
+
560
+ return freq;
561
+}
562
+
563
+static uint64_t imx6ul_analog_pll2_bypass_clk(IMX6ULCCMState *dev)
564
+{
565
+ uint64_t freq = 0;
566
+
567
+ trace_ccm_freq((uint32_t)freq);
568
+
569
+ return freq;
570
+}
571
+
572
+static uint64_t imx6ul_ccm_get_periph_clk2_sel_clk(IMX6ULCCMState *dev)
573
+{
574
+ uint64_t freq = 0;
575
+
576
+ switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) {
577
+ case 0:
578
+ freq = imx6ul_analog_get_pll3_clk(dev);
579
+ break;
580
+ case 1:
581
+ freq = imx6ul_analog_get_osc_clk(dev);
582
+ break;
583
+ case 2:
584
+ freq = imx6ul_analog_pll2_bypass_clk(dev);
585
+ break;
586
+ case 3:
587
+ /* We should never get there as 3 is a reserved value */
588
+ qemu_log_mask(LOG_GUEST_ERROR,
589
+ "[%s]%s: unsupported PERIPH_CLK2_SEL value 3\n",
590
+ TYPE_IMX6UL_CCM, __func__);
591
+ /* freq is set to 0 as we don't know what it should be */
592
+ break;
593
+ default:
594
+ g_assert_not_reached();
595
+ }
596
+
597
+ trace_ccm_freq((uint32_t)freq);
598
+
599
+ return freq;
600
+}
601
+
602
+static uint64_t imx6ul_ccm_get_periph_clk_sel_clk(IMX6ULCCMState *dev)
603
+{
604
+ uint64_t freq = 0;
605
+
606
+ switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) {
607
+ case 0:
608
+ freq = imx6ul_analog_get_pll2_clk(dev);
609
+ break;
610
+ case 1:
611
+ freq = imx6ul_analog_get_pll2_pfd2_clk(dev);
612
+ break;
613
+ case 2:
614
+ freq = imx6ul_analog_get_pll2_pfd0_clk(dev);
615
+ break;
616
+ case 3:
617
+ freq = imx6ul_analog_get_pll2_pfd2_clk(dev) / 2;
618
+ break;
619
+ default:
620
+ g_assert_not_reached();
621
+ }
622
+
623
+ trace_ccm_freq((uint32_t)freq);
624
+
625
+ return freq;
626
+}
627
+
628
+static uint64_t imx6ul_ccm_get_periph_clk2_clk(IMX6ULCCMState *dev)
629
+{
630
+ uint64_t freq = 0;
631
+
632
+ freq = imx6ul_ccm_get_periph_clk2_sel_clk(dev)
633
+ / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF));
634
+
635
+ trace_ccm_freq((uint32_t)freq);
636
+
637
+ return freq;
638
+}
639
+
640
+static uint64_t imx6ul_ccm_get_periph_sel_clk(IMX6ULCCMState *dev)
641
+{
642
+ uint64_t freq = 0;
643
+
644
+ switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) {
645
+ case 0:
646
+ freq = imx6ul_ccm_get_periph_clk_sel_clk(dev);
647
+ break;
648
+ case 1:
649
+ freq = imx6ul_ccm_get_periph_clk2_clk(dev);
650
+ break;
651
+ default:
652
+ g_assert_not_reached();
653
+ }
654
+
655
+ trace_ccm_freq((uint32_t)freq);
656
+
657
+ return freq;
658
+}
659
+
660
+static uint64_t imx6ul_ccm_get_ahb_clk(IMX6ULCCMState *dev)
661
+{
662
+ uint64_t freq = 0;
663
+
664
+ freq = imx6ul_ccm_get_periph_sel_clk(dev)
665
+ / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF));
666
+
667
+ trace_ccm_freq((uint32_t)freq);
668
+
669
+ return freq;
670
+}
671
+
672
+static uint64_t imx6ul_ccm_get_ipg_clk(IMX6ULCCMState *dev)
673
+{
674
+ uint64_t freq = 0;
675
+
676
+ freq = imx6ul_ccm_get_ahb_clk(dev)
677
+ / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF));
678
+
679
+ trace_ccm_freq((uint32_t)freq);
680
+
681
+ return freq;
682
+}
683
+
684
+static uint64_t imx6ul_ccm_get_per_sel_clk(IMX6ULCCMState *dev)
685
+{
686
+ uint64_t freq = 0;
687
+
688
+ switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) {
689
+ case 0:
690
+ freq = imx6ul_ccm_get_ipg_clk(dev);
691
+ break;
692
+ case 1:
693
+ freq = imx6ul_analog_get_osc_clk(dev);
694
+ break;
695
+ default:
696
+ g_assert_not_reached();
697
+ }
698
+
699
+ trace_ccm_freq((uint32_t)freq);
700
+
701
+ return freq;
702
+}
703
+
704
+static uint64_t imx6ul_ccm_get_per_clk(IMX6ULCCMState *dev)
705
+{
706
+ uint64_t freq = 0;
707
+
708
+ freq = imx6ul_ccm_get_per_sel_clk(dev)
709
+ / (1 + FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_PODF));
710
+
711
+ trace_ccm_freq((uint32_t)freq);
712
+
713
+ return freq;
714
+}
715
+
716
+static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
717
+{
718
+ uint32_t freq = 0;
719
+ IMX6ULCCMState *s = IMX6UL_CCM(dev);
720
+
721
+ switch (clock) {
722
+ case CLK_NONE:
723
+ break;
724
+ case CLK_IPG:
725
+ freq = imx6ul_ccm_get_ipg_clk(s);
726
+ break;
727
+ case CLK_IPG_HIGH:
728
+ freq = imx6ul_ccm_get_per_clk(s);
729
+ break;
730
+ case CLK_32k:
731
+ freq = CKIL_FREQ;
732
+ break;
733
+ case CLK_HIGH:
734
+ freq = CKIH_FREQ;
735
+ break;
736
+ case CLK_HIGH_DIV:
737
+ freq = CKIH_FREQ / 8;
738
+ break;
739
+ default:
740
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
741
+ TYPE_IMX6UL_CCM, __func__, clock);
742
+ break;
743
+ }
744
+
745
+ trace_ccm_clock_freq(clock, freq);
746
+
747
+ return freq;
748
+}
749
+
750
+static void imx6ul_ccm_reset(DeviceState *dev)
751
+{
752
+ IMX6ULCCMState *s = IMX6UL_CCM(dev);
753
+
754
+ trace_ccm_entry();
755
+
756
+ s->ccm[CCM_CCR] = 0x0401167F;
757
+ s->ccm[CCM_CCDR] = 0x00000000;
758
+ s->ccm[CCM_CSR] = 0x00000010;
759
+ s->ccm[CCM_CCSR] = 0x00000100;
760
+ s->ccm[CCM_CACRR] = 0x00000000;
761
+ s->ccm[CCM_CBCDR] = 0x00018D00;
762
+ s->ccm[CCM_CBCMR] = 0x24860324;
763
+ s->ccm[CCM_CSCMR1] = 0x04900080;
764
+ s->ccm[CCM_CSCMR2] = 0x03192F06;
765
+ s->ccm[CCM_CSCDR1] = 0x00490B00;
766
+ s->ccm[CCM_CS1CDR] = 0x0EC102C1;
767
+ s->ccm[CCM_CS2CDR] = 0x000336C1;
768
+ s->ccm[CCM_CDCDR] = 0x33F71F92;
769
+ s->ccm[CCM_CHSCCDR] = 0x000248A4;
770
+ s->ccm[CCM_CSCDR2] = 0x00029B48;
771
+ s->ccm[CCM_CSCDR3] = 0x00014841;
772
+ s->ccm[CCM_CDHIPR] = 0x00000000;
773
+ s->ccm[CCM_CTOR] = 0x00000000;
774
+ s->ccm[CCM_CLPCR] = 0x00000079;
775
+ s->ccm[CCM_CISR] = 0x00000000;
776
+ s->ccm[CCM_CIMR] = 0xFFFFFFFF;
777
+ s->ccm[CCM_CCOSR] = 0x000A0001;
778
+ s->ccm[CCM_CGPR] = 0x0000FE62;
779
+ s->ccm[CCM_CCGR0] = 0xFFFFFFFF;
780
+ s->ccm[CCM_CCGR1] = 0xFFFFFFFF;
781
+ s->ccm[CCM_CCGR2] = 0xFC3FFFFF;
782
+ s->ccm[CCM_CCGR3] = 0xFFFFFFFF;
783
+ s->ccm[CCM_CCGR4] = 0xFFFFFFFF;
784
+ s->ccm[CCM_CCGR5] = 0xFFFFFFFF;
785
+ s->ccm[CCM_CCGR6] = 0xFFFFFFFF;
786
+ s->ccm[CCM_CMEOR] = 0xFFFFFFFF;
787
+
788
+ s->analog[CCM_ANALOG_PLL_ARM] = 0x00013063;
789
+ s->analog[CCM_ANALOG_PLL_USB1] = 0x00012000;
790
+ s->analog[CCM_ANALOG_PLL_USB2] = 0x00012000;
791
+ s->analog[CCM_ANALOG_PLL_SYS] = 0x00013001;
792
+ s->analog[CCM_ANALOG_PLL_SYS_SS] = 0x00000000;
793
+ s->analog[CCM_ANALOG_PLL_SYS_NUM] = 0x00000000;
794
+ s->analog[CCM_ANALOG_PLL_SYS_DENOM] = 0x00000012;
795
+ s->analog[CCM_ANALOG_PLL_AUDIO] = 0x00011006;
796
+ s->analog[CCM_ANALOG_PLL_AUDIO_NUM] = 0x05F5E100;
797
+ s->analog[CCM_ANALOG_PLL_AUDIO_DENOM] = 0x2964619C;
798
+ s->analog[CCM_ANALOG_PLL_VIDEO] = 0x0001100C;
799
+ s->analog[CCM_ANALOG_PLL_VIDEO_NUM] = 0x05F5E100;
800
+ s->analog[CCM_ANALOG_PLL_VIDEO_DENOM] = 0x10A24447;
801
+ s->analog[CCM_ANALOG_PLL_ENET] = 0x00011001;
802
+ s->analog[CCM_ANALOG_PFD_480] = 0x1311100C;
803
+ s->analog[CCM_ANALOG_PFD_528] = 0x1018101B;
804
+
805
+ s->analog[PMU_REG_1P1] = 0x00001073;
806
+ s->analog[PMU_REG_3P0] = 0x00000F74;
807
+ s->analog[PMU_REG_2P5] = 0x00001073;
808
+ s->analog[PMU_REG_CORE] = 0x00482012;
809
+ s->analog[PMU_MISC0] = 0x04000000;
810
+ s->analog[PMU_MISC1] = 0x00000000;
811
+ s->analog[PMU_MISC2] = 0x00272727;
812
+ s->analog[PMU_LOWPWR_CTRL] = 0x00004009;
813
+
814
+ s->analog[USB_ANALOG_USB1_VBUS_DETECT] = 0x01000004;
815
+ s->analog[USB_ANALOG_USB1_CHRG_DETECT] = 0x00000000;
816
+ s->analog[USB_ANALOG_USB1_VBUS_DETECT_STAT] = 0x00000000;
817
+ s->analog[USB_ANALOG_USB1_CHRG_DETECT_STAT] = 0x00000000;
818
+ s->analog[USB_ANALOG_USB1_MISC] = 0x00000002;
819
+ s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x01000004;
820
+ s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000;
821
+ s->analog[USB_ANALOG_USB2_MISC] = 0x00000002;
822
+ s->analog[USB_ANALOG_DIGPROG] = 0x00640000;
823
+
824
+ /* all PLLs need to be locked */
825
+ s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK;
826
+ s->analog[CCM_ANALOG_PLL_USB1] |= CCM_ANALOG_PLL_LOCK;
827
+ s->analog[CCM_ANALOG_PLL_USB2] |= CCM_ANALOG_PLL_LOCK;
828
+ s->analog[CCM_ANALOG_PLL_SYS] |= CCM_ANALOG_PLL_LOCK;
829
+ s->analog[CCM_ANALOG_PLL_AUDIO] |= CCM_ANALOG_PLL_LOCK;
830
+ s->analog[CCM_ANALOG_PLL_VIDEO] |= CCM_ANALOG_PLL_LOCK;
831
+ s->analog[CCM_ANALOG_PLL_ENET] |= CCM_ANALOG_PLL_LOCK;
832
+
833
+ s->analog[TEMPMON_TEMPSENSE0] = 0x00000001;
834
+ s->analog[TEMPMON_TEMPSENSE1] = 0x00000001;
835
+ s->analog[TEMPMON_TEMPSENSE2] = 0x00000000;
836
+}
837
+
838
+static uint64_t imx6ul_ccm_read(void *opaque, hwaddr offset, unsigned size)
839
+{
840
+ uint32_t value = 0;
841
+ uint32_t index = offset >> 2;
842
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
843
+
844
+ assert(index < CCM_MAX);
845
+
846
+ value = s->ccm[index];
847
+
848
+ trace_ccm_read_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
849
+
850
+ return (uint64_t)value;
851
+}
852
+
853
+static void imx6ul_ccm_write(void *opaque, hwaddr offset, uint64_t value,
854
+ unsigned size)
855
+{
856
+ uint32_t index = offset >> 2;
857
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
858
+
859
+ assert(index < CCM_MAX);
860
+
861
+ trace_ccm_write_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
862
+
863
+ /*
864
+ * We will do a better implementation later. In particular some bits
865
+ * cannot be written to.
866
+ */
867
+ s->ccm[index] = (uint32_t)value;
868
+}
869
+
870
+static uint64_t imx6ul_analog_read(void *opaque, hwaddr offset, unsigned size)
871
+{
872
+ uint32_t value;
873
+ uint32_t index = offset >> 2;
874
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
875
+
876
+ assert(index < CCM_ANALOG_MAX);
877
+
878
+ switch (index) {
879
+ case CCM_ANALOG_PLL_ARM_SET:
880
+ case CCM_ANALOG_PLL_USB1_SET:
881
+ case CCM_ANALOG_PLL_USB2_SET:
882
+ case CCM_ANALOG_PLL_SYS_SET:
883
+ case CCM_ANALOG_PLL_AUDIO_SET:
884
+ case CCM_ANALOG_PLL_VIDEO_SET:
885
+ case CCM_ANALOG_PLL_ENET_SET:
886
+ case CCM_ANALOG_PFD_480_SET:
887
+ case CCM_ANALOG_PFD_528_SET:
888
+ case CCM_ANALOG_MISC0_SET:
889
+ case PMU_MISC1_SET:
890
+ case CCM_ANALOG_MISC2_SET:
891
+ case USB_ANALOG_USB1_VBUS_DETECT_SET:
892
+ case USB_ANALOG_USB1_CHRG_DETECT_SET:
893
+ case USB_ANALOG_USB1_MISC_SET:
894
+ case USB_ANALOG_USB2_VBUS_DETECT_SET:
895
+ case USB_ANALOG_USB2_CHRG_DETECT_SET:
896
+ case USB_ANALOG_USB2_MISC_SET:
897
+ case TEMPMON_TEMPSENSE0_SET:
898
+ case TEMPMON_TEMPSENSE1_SET:
899
+ case TEMPMON_TEMPSENSE2_SET:
900
+ /*
901
+ * All REG_NAME_SET register access are in fact targeting
902
+ * the REG_NAME register.
903
+ */
904
+ value = s->analog[index - 1];
905
+ break;
906
+ case CCM_ANALOG_PLL_ARM_CLR:
907
+ case CCM_ANALOG_PLL_USB1_CLR:
908
+ case CCM_ANALOG_PLL_USB2_CLR:
909
+ case CCM_ANALOG_PLL_SYS_CLR:
910
+ case CCM_ANALOG_PLL_AUDIO_CLR:
911
+ case CCM_ANALOG_PLL_VIDEO_CLR:
912
+ case CCM_ANALOG_PLL_ENET_CLR:
913
+ case CCM_ANALOG_PFD_480_CLR:
914
+ case CCM_ANALOG_PFD_528_CLR:
915
+ case CCM_ANALOG_MISC0_CLR:
916
+ case PMU_MISC1_CLR:
917
+ case CCM_ANALOG_MISC2_CLR:
918
+ case USB_ANALOG_USB1_VBUS_DETECT_CLR:
919
+ case USB_ANALOG_USB1_CHRG_DETECT_CLR:
920
+ case USB_ANALOG_USB1_MISC_CLR:
921
+ case USB_ANALOG_USB2_VBUS_DETECT_CLR:
922
+ case USB_ANALOG_USB2_CHRG_DETECT_CLR:
923
+ case USB_ANALOG_USB2_MISC_CLR:
924
+ case TEMPMON_TEMPSENSE0_CLR:
925
+ case TEMPMON_TEMPSENSE1_CLR:
926
+ case TEMPMON_TEMPSENSE2_CLR:
927
+ /*
928
+ * All REG_NAME_CLR register access are in fact targeting
929
+ * the REG_NAME register.
930
+ */
931
+ value = s->analog[index - 2];
932
+ break;
933
+ case CCM_ANALOG_PLL_ARM_TOG:
934
+ case CCM_ANALOG_PLL_USB1_TOG:
935
+ case CCM_ANALOG_PLL_USB2_TOG:
936
+ case CCM_ANALOG_PLL_SYS_TOG:
937
+ case CCM_ANALOG_PLL_AUDIO_TOG:
938
+ case CCM_ANALOG_PLL_VIDEO_TOG:
939
+ case CCM_ANALOG_PLL_ENET_TOG:
940
+ case CCM_ANALOG_PFD_480_TOG:
941
+ case CCM_ANALOG_PFD_528_TOG:
942
+ case CCM_ANALOG_MISC0_TOG:
943
+ case PMU_MISC1_TOG:
944
+ case CCM_ANALOG_MISC2_TOG:
945
+ case USB_ANALOG_USB1_VBUS_DETECT_TOG:
946
+ case USB_ANALOG_USB1_CHRG_DETECT_TOG:
947
+ case USB_ANALOG_USB1_MISC_TOG:
948
+ case USB_ANALOG_USB2_VBUS_DETECT_TOG:
949
+ case USB_ANALOG_USB2_CHRG_DETECT_TOG:
950
+ case USB_ANALOG_USB2_MISC_TOG:
951
+ case TEMPMON_TEMPSENSE0_TOG:
952
+ case TEMPMON_TEMPSENSE1_TOG:
953
+ case TEMPMON_TEMPSENSE2_TOG:
954
+ /*
955
+ * All REG_NAME_TOG register access are in fact targeting
956
+ * the REG_NAME register.
957
+ */
958
+ value = s->analog[index - 3];
959
+ break;
960
+ default:
961
+ value = s->analog[index];
962
+ break;
963
+ }
964
+
965
+ trace_ccm_read_reg(imx6ul_analog_reg_name(index), (uint32_t)value);
966
+
967
+ return (uint64_t)value;
968
+}
969
+
970
+static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
971
+ unsigned size)
972
+{
973
+ uint32_t index = offset >> 2;
974
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
975
+
976
+ assert(index < CCM_ANALOG_MAX);
977
+
978
+ trace_ccm_write_reg(imx6ul_analog_reg_name(index), (uint32_t)value);
979
+
980
+ switch (index) {
981
+ case CCM_ANALOG_PLL_ARM_SET:
982
+ case CCM_ANALOG_PLL_USB1_SET:
983
+ case CCM_ANALOG_PLL_USB2_SET:
984
+ case CCM_ANALOG_PLL_SYS_SET:
985
+ case CCM_ANALOG_PLL_AUDIO_SET:
986
+ case CCM_ANALOG_PLL_VIDEO_SET:
987
+ case CCM_ANALOG_PLL_ENET_SET:
988
+ case CCM_ANALOG_PFD_480_SET:
989
+ case CCM_ANALOG_PFD_528_SET:
990
+ case CCM_ANALOG_MISC0_SET:
991
+ case PMU_MISC1_SET:
992
+ case CCM_ANALOG_MISC2_SET:
993
+ case USB_ANALOG_USB1_VBUS_DETECT_SET:
994
+ case USB_ANALOG_USB1_CHRG_DETECT_SET:
995
+ case USB_ANALOG_USB1_MISC_SET:
996
+ case USB_ANALOG_USB2_VBUS_DETECT_SET:
997
+ case USB_ANALOG_USB2_CHRG_DETECT_SET:
998
+ case USB_ANALOG_USB2_MISC_SET:
999
+ /*
1000
+ * All REG_NAME_SET register access are in fact targeting
1001
+ * the REG_NAME register. So we change the value of the
1002
+ * REG_NAME register, setting bits passed in the value.
1003
+ */
1004
+ s->analog[index - 1] |= value;
1005
+ break;
1006
+ case CCM_ANALOG_PLL_ARM_CLR:
1007
+ case CCM_ANALOG_PLL_USB1_CLR:
1008
+ case CCM_ANALOG_PLL_USB2_CLR:
1009
+ case CCM_ANALOG_PLL_SYS_CLR:
1010
+ case CCM_ANALOG_PLL_AUDIO_CLR:
1011
+ case CCM_ANALOG_PLL_VIDEO_CLR:
1012
+ case CCM_ANALOG_PLL_ENET_CLR:
1013
+ case CCM_ANALOG_PFD_480_CLR:
1014
+ case CCM_ANALOG_PFD_528_CLR:
1015
+ case CCM_ANALOG_MISC0_CLR:
1016
+ case PMU_MISC1_CLR:
1017
+ case CCM_ANALOG_MISC2_CLR:
1018
+ case USB_ANALOG_USB1_VBUS_DETECT_CLR:
1019
+ case USB_ANALOG_USB1_CHRG_DETECT_CLR:
1020
+ case USB_ANALOG_USB1_MISC_CLR:
1021
+ case USB_ANALOG_USB2_VBUS_DETECT_CLR:
1022
+ case USB_ANALOG_USB2_CHRG_DETECT_CLR:
1023
+ case USB_ANALOG_USB2_MISC_CLR:
1024
+ /*
1025
+ * All REG_NAME_CLR register access are in fact targeting
1026
+ * the REG_NAME register. So we change the value of the
1027
+ * REG_NAME register, unsetting bits passed in the value.
1028
+ */
1029
+ s->analog[index - 2] &= ~value;
1030
+ break;
1031
+ case CCM_ANALOG_PLL_ARM_TOG:
1032
+ case CCM_ANALOG_PLL_USB1_TOG:
1033
+ case CCM_ANALOG_PLL_USB2_TOG:
1034
+ case CCM_ANALOG_PLL_SYS_TOG:
1035
+ case CCM_ANALOG_PLL_AUDIO_TOG:
1036
+ case CCM_ANALOG_PLL_VIDEO_TOG:
1037
+ case CCM_ANALOG_PLL_ENET_TOG:
1038
+ case CCM_ANALOG_PFD_480_TOG:
1039
+ case CCM_ANALOG_PFD_528_TOG:
1040
+ case CCM_ANALOG_MISC0_TOG:
1041
+ case PMU_MISC1_TOG:
1042
+ case CCM_ANALOG_MISC2_TOG:
1043
+ case USB_ANALOG_USB1_VBUS_DETECT_TOG:
1044
+ case USB_ANALOG_USB1_CHRG_DETECT_TOG:
1045
+ case USB_ANALOG_USB1_MISC_TOG:
1046
+ case USB_ANALOG_USB2_VBUS_DETECT_TOG:
1047
+ case USB_ANALOG_USB2_CHRG_DETECT_TOG:
1048
+ case USB_ANALOG_USB2_MISC_TOG:
1049
+ /*
1050
+ * All REG_NAME_TOG register access are in fact targeting
1051
+ * the REG_NAME register. So we change the value of the
1052
+ * REG_NAME register, toggling bits passed in the value.
1053
+ */
1054
+ s->analog[index - 3] ^= value;
1055
+ break;
1056
+ default:
1057
+ /*
1058
+ * We will do a better implementation later. In particular some bits
1059
+ * cannot be written to.
1060
+ */
1061
+ s->analog[index] = value;
1062
+ break;
1063
+ }
1064
+}
1065
+
1066
+static const struct MemoryRegionOps imx6ul_ccm_ops = {
1067
+ .read = imx6ul_ccm_read,
1068
+ .write = imx6ul_ccm_write,
1069
+ .endianness = DEVICE_NATIVE_ENDIAN,
1070
+ .valid = {
1071
+ /*
1072
+ * Our device would not work correctly if the guest was doing
1073
+ * unaligned access. This might not be a limitation on the real
1074
+ * device but in practice there is no reason for a guest to access
1075
+ * this device unaligned.
1076
+ */
1077
+ .min_access_size = 4,
1078
+ .max_access_size = 4,
1079
+ .unaligned = false,
1080
+ },
1081
+};
1082
+
1083
+static const struct MemoryRegionOps imx6ul_analog_ops = {
1084
+ .read = imx6ul_analog_read,
1085
+ .write = imx6ul_analog_write,
1086
+ .endianness = DEVICE_NATIVE_ENDIAN,
1087
+ .valid = {
1088
+ /*
1089
+ * Our device would not work correctly if the guest was doing
1090
+ * unaligned access. This might not be a limitation on the real
1091
+ * device but in practice there is no reason for a guest to access
1092
+ * this device unaligned.
1093
+ */
1094
+ .min_access_size = 4,
1095
+ .max_access_size = 4,
1096
+ .unaligned = false,
1097
+ },
1098
+};
1099
+
1100
+static void imx6ul_ccm_init(Object *obj)
1101
+{
1102
+ DeviceState *dev = DEVICE(obj);
1103
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
1104
+ IMX6ULCCMState *s = IMX6UL_CCM(obj);
1105
+
1106
+ /* initialize a container for the all memory range */
1107
+ memory_region_init(&s->container, OBJECT(dev), TYPE_IMX6UL_CCM, 0x8000);
1108
+
1109
+ /* We initialize an IO memory region for the CCM part */
1110
+ memory_region_init_io(&s->ioccm, OBJECT(dev), &imx6ul_ccm_ops, s,
1111
+ TYPE_IMX6UL_CCM ".ccm", CCM_MAX * sizeof(uint32_t));
1112
+
1113
+ /* Add the CCM as a subregion at offset 0 */
1114
+ memory_region_add_subregion(&s->container, 0, &s->ioccm);
1115
+
1116
+ /* We initialize an IO memory region for the ANALOG part */
1117
+ memory_region_init_io(&s->ioanalog, OBJECT(dev), &imx6ul_analog_ops, s,
1118
+ TYPE_IMX6UL_CCM ".analog",
1119
+ CCM_ANALOG_MAX * sizeof(uint32_t));
1120
+
1121
+ /* Add the ANALOG as a subregion at offset 0x4000 */
1122
+ memory_region_add_subregion(&s->container, 0x4000, &s->ioanalog);
1123
+
1124
+ sysbus_init_mmio(sd, &s->container);
1125
+}
1126
+
1127
+static void imx6ul_ccm_class_init(ObjectClass *klass, void *data)
1128
+{
1129
+ DeviceClass *dc = DEVICE_CLASS(klass);
1130
+ IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
1131
+
1132
+ dc->reset = imx6ul_ccm_reset;
1133
+ dc->vmsd = &vmstate_imx6ul_ccm;
1134
+ dc->desc = "i.MX6UL Clock Control Module";
1135
+
1136
+ ccm->get_clock_frequency = imx6ul_ccm_get_clock_frequency;
1137
+}
1138
+
1139
+static const TypeInfo imx6ul_ccm_info = {
1140
+ .name = TYPE_IMX6UL_CCM,
1141
+ .parent = TYPE_IMX_CCM,
1142
+ .instance_size = sizeof(IMX6ULCCMState),
1143
+ .instance_init = imx6ul_ccm_init,
1144
+ .class_init = imx6ul_ccm_class_init,
1145
+};
1146
+
1147
+static void imx6ul_ccm_register_types(void)
1148
+{
1149
+ type_register_static(&imx6ul_ccm_info);
1150
+}
1151
+
1152
+type_init(imx6ul_ccm_register_types)
1153
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
1154
index XXXXXXX..XXXXXXX 100644
1155
--- a/hw/misc/trace-events
1156
+++ b/hw/misc/trace-events
1157
@@ -XXX,XX +XXX,XX @@ iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec
1158
iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u"
1159
iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u"
1160
iotkit_secctl_reset(void) "IoTKit SecCtl: reset"
1161
+
1162
+# hw/misc/imx6ul_ccm.c
1163
+ccm_entry(void) "\n"
1164
+ccm_freq(uint32_t freq) "freq = %d\n"
1165
+ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d\n"
1166
+ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 "\n"
1167
+ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 "\n"
1168
--
85
--
1169
2.18.0
86
2.20.1
1170
87
1171
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/30] target/arm: Fix aa64 FCADD and FCMLA decode
[PULL 14/16] hw/arm/nseries: Check return value from load_image_targphys()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The nseries machines have a codepath that allows them to load a
2
secondary bootloader. This code wasn't checking that the
3
load_image_targphys() succeeded. Check the return value and report
4
the error to the user.
2
5
3
These insns require u=1; failed to include that in the switch
6
While we're in the vicinity, fix the comment style of the
4
cases. This probably happened during one of the rebases just
7
comment documenting what this image load is doing.
5
before final commit.
6
8
7
Fixes: d17b7cdcf4e
9
Fixes: Coverity CID 1192904
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Message-id: 20180810193129.1556-6-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20201103114918.11807-1-peter.maydell@linaro.org
12
---
13
---
13
target/arm/translate-a64.c | 12 ++++++------
14
hw/arm/nseries.c | 15 +++++++++++----
14
1 file changed, 6 insertions(+), 6 deletions(-)
15
1 file changed, 11 insertions(+), 4 deletions(-)
15
16
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
19
--- a/hw/arm/nseries.c
19
+++ b/target/arm/translate-a64.c
20
+++ b/hw/arm/nseries.c
20
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
21
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
21
}
22
/* No, wait, better start at the ROM. */
22
feature = ARM_FEATURE_V8_DOTPROD;
23
s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000;
23
break;
24
24
- case 0x8: /* FCMLA, #0 */
25
- /* This is intended for loading the `secondary.bin' program from
25
- case 0x9: /* FCMLA, #90 */
26
+ /*
26
- case 0xa: /* FCMLA, #180 */
27
+ * This is intended for loading the `secondary.bin' program from
27
- case 0xb: /* FCMLA, #270 */
28
* Nokia images (the NOLO bootloader). The entry point seems
28
- case 0xc: /* FCADD, #90 */
29
* to be at OMAP2_Q2_BASE + 0x400000.
29
- case 0xe: /* FCADD, #270 */
30
*
30
+ case 0x18: /* FCMLA, #0 */
31
@@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine,
31
+ case 0x19: /* FCMLA, #90 */
32
* for them the entry point needs to be set to OMAP2_SRAM_BASE.
32
+ case 0x1a: /* FCMLA, #180 */
33
*
33
+ case 0x1b: /* FCMLA, #270 */
34
* The code above is for loading the `zImage' file from Nokia
34
+ case 0x1c: /* FCADD, #90 */
35
- * images. */
35
+ case 0x1e: /* FCADD, #270 */
36
- load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000,
36
if (size == 0
37
- machine->ram_size - 0x400000);
37
|| (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
38
+ * images.
38
|| (size == 3 && !is_q)) {
39
+ */
40
+ if (load_image_targphys(option_rom[0].name,
41
+ OMAP2_Q2_BASE + 0x400000,
42
+ machine->ram_size - 0x400000) < 0) {
43
+ error_report("Failed to load secondary bootloader %s",
44
+ option_rom[0].name);
45
+ exit(EXIT_FAILURE);
46
+ }
47
48
n800_setup_nolo_tags(nolo_tags);
49
cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000);
39
--
50
--
40
2.18.0
51
2.20.1
41
52
42
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/30] target/arm: Fix typo in helper_sve_ld1hss_r
[PULL 15/16] tests/qtest/npcm7xx_rng-test: count runs properly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Havard Skinnemoen <hskinnemoen@google.com>
2
2
3
Cc: qemu-stable@nongnu.org (3.0.1)
3
The number of runs is equal to the number of 0-1 and 1-0 transitions,
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
plus one. Currently, it's counting the number of times these transitions
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
do _not_ happen, plus one.
6
7
Source:
8
https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf
9
section 2.3.4 point (3).
10
11
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
12
Message-id: 20201103011457.2959989-2-hskinnemoen@google.com
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
15
---
8
target/arm/sve_helper.c | 2 +-
16
tests/qtest/npcm7xx_rng-test.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 1 insertion(+), 1 deletion(-)
10
18
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
19
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
21
--- a/tests/qtest/npcm7xx_rng-test.c
14
+++ b/target/arm/sve_helper.c
22
+++ b/tests/qtest/npcm7xx_rng-test.c
15
@@ -XXX,XX +XXX,XX @@ DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, )
23
@@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits)
16
DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, )
24
pi = (double)nr_ones / nr_bits;
17
25
18
DO_LD1(sve_ld1hsu_r, cpu_lduw_data_ra, uint32_t, uint16_t, H1_4)
26
for (k = 0; k < nr_bits - 1; k++) {
19
-DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int8_t, H1_4)
27
- vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf));
20
+DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int16_t, H1_4)
28
+ vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf));
21
DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, )
29
}
22
DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, )
30
vn_obs += 1;
23
31
24
--
32
--
25
2.18.0
33
2.20.1
26
34
27
35
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/30] target/arm: Fix sign-extension in sve do_ldr/do_str
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The expression (int) imm + (uint32_t) len_align turns into uint32_t
4
and thus with negative imm produces a memory operation at the wrong
5
offset. None of the numbers involved are particularly large, so
6
change everything to use int.
7
8
Cc: qemu-stable@nongnu.org (3.0.1)
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-sve.c | 18 ++++++++----------
15
1 file changed, 8 insertions(+), 10 deletions(-)
16
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
20
+++ b/target/arm/translate-sve.c
21
@@ -XXX,XX +XXX,XX @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
22
* The load should begin at the address Rn + IMM.
23
*/
24
25
-static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
26
- int rn, int imm)
27
+static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
28
{
29
- uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
30
- uint32_t len_remain = len % 8;
31
- uint32_t nparts = len / 8 + ctpop8(len_remain);
32
+ int len_align = QEMU_ALIGN_DOWN(len, 8);
33
+ int len_remain = len % 8;
34
+ int nparts = len / 8 + ctpop8(len_remain);
35
int midx = get_mem_index(s);
36
TCGv_i64 addr, t0, t1;
37
38
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
39
}
40
41
/* Similarly for stores. */
42
-static void do_str(DisasContext *s, uint32_t vofs, uint32_t len,
43
- int rn, int imm)
44
+static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
45
{
46
- uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
47
- uint32_t len_remain = len % 8;
48
- uint32_t nparts = len / 8 + ctpop8(len_remain);
49
+ int len_align = QEMU_ALIGN_DOWN(len, 8);
50
+ int len_remain = len % 8;
51
+ int nparts = len / 8 + ctpop8(len_remain);
52
int midx = get_mem_index(s);
53
TCGv_i64 addr, t0;
54
55
--
56
2.18.0
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/30] target/arm: Fix offset for LD1R instructions
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The immediate should be scaled by the size of the memory reference,
4
not the size of the elements into which it is loaded.
5
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-sve.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
21
unsigned vsz = vec_full_reg_size(s);
22
unsigned psz = pred_full_reg_size(s);
23
unsigned esz = dtype_esz[a->dtype];
24
+ unsigned msz = dtype_msz(a->dtype);
25
TCGLabel *over = gen_new_label();
26
TCGv_i64 temp;
27
28
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
29
30
/* Load the data. */
31
temp = tcg_temp_new_i64();
32
- tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
33
+ tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
34
tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
35
s->be_data | dtype_mop[a->dtype]);
36
37
--
38
2.18.0
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/30] target/arm: Fix offset scaling for LD_zprr and ST_zprr
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The scaling should be solely on the memory operation size; the number
4
of registers being loaded does not come in to the initial computation.
5
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-sve.c | 5 ++---
14
1 file changed, 2 insertions(+), 3 deletions(-)
15
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
21
}
22
if (sve_access_check(s)) {
23
TCGv_i64 addr = new_tmp_a64(s);
24
- tcg_gen_muli_i64(addr, cpu_reg(s, a->rm),
25
- (a->nreg + 1) << dtype_msz(a->dtype));
26
+ tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
27
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
28
do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg);
29
}
30
@@ -XXX,XX +XXX,XX @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn)
31
}
32
if (sve_access_check(s)) {
33
TCGv_i64 addr = new_tmp_a64(s);
34
- tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz);
35
+ tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz);
36
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
37
do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg);
38
}
39
--
40
2.18.0
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/30] target/arm: Add sve-max-vq cpu property to -cpu max
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This allows the default (and maximum) vector length to be set
4
from the command-line. Which is extraordinarily helpful in
5
debugging problems depending on vector length without having to
6
bake knowledge of PR_SET_SVE_VL into every guest binary.
7
8
Cc: qemu-stable@nongnu.org (3.0.1)
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 3 +++
15
linux-user/syscall.c | 19 +++++++++++++------
16
target/arm/cpu.c | 6 +++---
17
target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++
18
target/arm/helper.c | 7 +++++--
19
5 files changed, 53 insertions(+), 11 deletions(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
26
27
/* Used to synchronize KVM and QEMU in-kernel device levels */
28
uint8_t device_irq_level;
29
+
30
+ /* Used to set the maximum vector length the cpu will support. */
31
+ uint32_t sve_max_vq;
32
};
33
34
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
35
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/linux-user/syscall.c
38
+++ b/linux-user/syscall.c
39
@@ -XXX,XX +XXX,XX @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
40
#endif
41
#ifdef TARGET_AARCH64
42
case TARGET_PR_SVE_SET_VL:
43
- /* We cannot support either PR_SVE_SET_VL_ONEXEC
44
- or PR_SVE_VL_INHERIT. Therefore, anything above
45
- ARM_MAX_VQ results in EINVAL. */
46
+ /*
47
+ * We cannot support either PR_SVE_SET_VL_ONEXEC or
48
+ * PR_SVE_VL_INHERIT. Note the kernel definition
49
+ * of sve_vl_valid allows for VQ=512, i.e. VL=8192,
50
+ * even though the current architectural maximum is VQ=16.
51
+ */
52
ret = -TARGET_EINVAL;
53
if (arm_feature(cpu_env, ARM_FEATURE_SVE)
54
- && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) {
55
+ && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
56
CPUARMState *env = cpu_env;
57
- int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
58
- int vq = MAX(arg2 / 16, 1);
59
+ ARMCPU *cpu = arm_env_get_cpu(env);
60
+ uint32_t vq, old_vq;
61
+
62
+ old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
63
+ vq = MAX(arg2 / 16, 1);
64
+ vq = MIN(vq, cpu->sve_max_vq);
65
66
if (vq < old_vq) {
67
aarch64_sve_narrow_vq(env, vq);
68
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/cpu.c
71
+++ b/target/arm/cpu.c
72
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
73
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
74
env->cp15.cptr_el[3] |= CPTR_EZ;
75
/* with maximum vector length */
76
- env->vfp.zcr_el[1] = ARM_MAX_VQ - 1;
77
- env->vfp.zcr_el[2] = ARM_MAX_VQ - 1;
78
- env->vfp.zcr_el[3] = ARM_MAX_VQ - 1;
79
+ env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
80
+ env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
81
+ env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
82
#else
83
/* Reset into the highest available EL */
84
if (arm_feature(env, ARM_FEATURE_EL3)) {
85
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/target/arm/cpu64.c
88
+++ b/target/arm/cpu64.c
89
@@ -XXX,XX +XXX,XX @@
90
#include "sysemu/sysemu.h"
91
#include "sysemu/kvm.h"
92
#include "kvm_arm.h"
93
+#include "qapi/visitor.h"
94
95
static inline void set_feature(CPUARMState *env, int feature)
96
{
97
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
98
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
99
}
100
101
+static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
102
+ void *opaque, Error **errp)
103
+{
104
+ ARMCPU *cpu = ARM_CPU(obj);
105
+ visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
106
+}
107
+
108
+static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
109
+ void *opaque, Error **errp)
110
+{
111
+ ARMCPU *cpu = ARM_CPU(obj);
112
+ Error *err = NULL;
113
+
114
+ visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
115
+
116
+ if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
117
+ error_setg(&err, "unsupported SVE vector length");
118
+ error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
119
+ ARM_MAX_VQ);
120
+ }
121
+ error_propagate(errp, err);
122
+}
123
+
124
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
125
* otherwise, a CPU with as many features enabled as our emulation supports.
126
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
127
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
128
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
129
cpu->dcz_blocksize = 7; /* 512 bytes */
130
#endif
131
+
132
+ cpu->sve_max_vq = ARM_MAX_VQ;
133
+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
134
+ cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
135
}
136
}
137
138
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
139
uint64_t pmask;
140
141
assert(vq >= 1 && vq <= ARM_MAX_VQ);
142
+ assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
143
144
/* Zap the high bits of the zregs. */
145
for (i = 0; i < 32; i++) {
146
diff --git a/target/arm/helper.c b/target/arm/helper.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/target/arm/helper.c
149
+++ b/target/arm/helper.c
150
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
151
zcr_len = 0;
152
} else {
153
int current_el = arm_current_el(env);
154
+ ARMCPU *cpu = arm_env_get_cpu(env);
155
156
- zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el];
157
- zcr_len &= 0xf;
158
+ zcr_len = cpu->sve_max_vq - 1;
159
+ if (current_el <= 1) {
160
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
161
+ }
162
if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
163
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
164
}
165
--
166
2.18.0
167
168
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/30] i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board
Deleted patch
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
1
3
Tested by booting linux 4.18 (built using imx_v6_v7_defconfig) on the
4
emulated board.
5
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
Message-id: 3f8eb4300206634dc01e04b12f65b73c0ad2f955.1532984236.git.jcd@tribudubois.net
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/Makefile.objs | 2 +-
12
hw/arm/mcimx6ul-evk.c | 85 +++++++++++++++++++++++++++++++++++++++++++
13
2 files changed, 86 insertions(+), 1 deletion(-)
14
create mode 100644 hw/arm/mcimx6ul-evk.c
15
16
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Makefile.objs
19
+++ b/hw/arm/Makefile.objs
20
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
21
obj-$(CONFIG_IOTKIT) += iotkit.o
22
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
23
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
24
-obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o
25
+obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o
26
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
27
new file mode 100644
28
index XXXXXXX..XXXXXXX
29
--- /dev/null
30
+++ b/hw/arm/mcimx6ul-evk.c
31
@@ -XXX,XX +XXX,XX @@
32
+/*
33
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
34
+ *
35
+ * MCIMX6UL_EVK Board System emulation.
36
+ *
37
+ * This code is licensed under the GPL, version 2 or later.
38
+ * See the file `COPYING' in the top level directory.
39
+ *
40
+ * It (partially) emulates a mcimx6ul_evk board, with a Freescale
41
+ * i.MX6ul SoC
42
+ */
43
+
44
+#include "qemu/osdep.h"
45
+#include "qapi/error.h"
46
+#include "qemu-common.h"
47
+#include "hw/arm/fsl-imx6ul.h"
48
+#include "hw/boards.h"
49
+#include "sysemu/sysemu.h"
50
+#include "qemu/error-report.h"
51
+#include "sysemu/qtest.h"
52
+
53
+typedef struct {
54
+ FslIMX6ULState soc;
55
+ MemoryRegion ram;
56
+} MCIMX6ULEVK;
57
+
58
+static void mcimx6ul_evk_init(MachineState *machine)
59
+{
60
+ static struct arm_boot_info boot_info;
61
+ MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1);
62
+ int i;
63
+
64
+ if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) {
65
+ error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
66
+ machine->ram_size, FSL_IMX6UL_MMDC_SIZE);
67
+ exit(1);
68
+ }
69
+
70
+ boot_info = (struct arm_boot_info) {
71
+ .loader_start = FSL_IMX6UL_MMDC_ADDR,
72
+ .board_id = -1,
73
+ .ram_size = machine->ram_size,
74
+ .kernel_filename = machine->kernel_filename,
75
+ .kernel_cmdline = machine->kernel_cmdline,
76
+ .initrd_filename = machine->initrd_filename,
77
+ .nb_cpus = smp_cpus,
78
+ };
79
+
80
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
81
+ TYPE_FSL_IMX6UL, &error_fatal, NULL);
82
+
83
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
84
+
85
+ memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram",
86
+ machine->ram_size);
87
+ memory_region_add_subregion(get_system_memory(),
88
+ FSL_IMX6UL_MMDC_ADDR, &s->ram);
89
+
90
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
91
+ BusState *bus;
92
+ DeviceState *carddev;
93
+ DriveInfo *di;
94
+ BlockBackend *blk;
95
+
96
+ di = drive_get_next(IF_SD);
97
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
98
+ bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
99
+ carddev = qdev_create(bus, TYPE_SD_CARD);
100
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
101
+ object_property_set_bool(OBJECT(carddev), true,
102
+ "realized", &error_fatal);
103
+ }
104
+
105
+ if (!qtest_enabled()) {
106
+ arm_load_kernel(&s->soc.cpu[0], &boot_info);
107
+ }
108
+}
109
+
110
+static void mcimx6ul_evk_machine_init(MachineClass *mc)
111
+{
112
+ mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)";
113
+ mc->init = mcimx6ul_evk_init;
114
+ mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
115
+}
116
+DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
117
--
118
2.18.0
119
120
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/30] target/arm: add "cortex-m0" CPU model
Deleted patch
1
From: Stefan Hajnoczi <stefanha@redhat.com>
2
1
3
Define a "cortex-m0" ARMv6-M CPU model.
4
5
Most of the register reset values set by other CPU models are not
6
relevant for the cut-down ARMv6-M architecture.
7
8
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180814162739.11814-3-stefanha@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.c | 11 +++++++++++
15
1 file changed, 11 insertions(+)
16
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.c
20
+++ b/target/arm/cpu.c
21
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
22
cpu->reset_auxcr = 1;
23
}
24
25
+static void cortex_m0_initfn(Object *obj)
26
+{
27
+ ARMCPU *cpu = ARM_CPU(obj);
28
+ set_feature(&cpu->env, ARM_FEATURE_V6);
29
+ set_feature(&cpu->env, ARM_FEATURE_M);
30
+
31
+ cpu->midr = 0x410cc200;
32
+}
33
+
34
static void cortex_m3_initfn(Object *obj)
35
{
36
ARMCPU *cpu = ARM_CPU(obj);
37
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
38
{ .name = "arm1136", .initfn = arm1136_initfn },
39
{ .name = "arm1176", .initfn = arm1176_initfn },
40
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
41
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
42
+ .class_init = arm_v7m_class_init },
43
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
44
.class_init = arm_v7m_class_init },
45
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
46
--
47
2.18.0
48
49
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/30] loader: extract rom_free() function
Deleted patch
1
From: Stefan Hajnoczi <stefanha@redhat.com>
2
1
3
The next patch will need to free a rom. There is already code to do
4
this in rom_add_file().
5
6
Note that rom_add_file() uses:
7
8
rom = g_malloc0(sizeof(*rom));
9
...
10
if (rom->fw_dir) {
11
g_free(rom->fw_dir);
12
g_free(rom->fw_file);
13
}
14
15
The conditional is unnecessary since g_free(NULL) is a no-op.
16
17
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
18
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20180814162739.11814-4-stefanha@redhat.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/core/loader.c | 21 ++++++++++++---------
24
1 file changed, 12 insertions(+), 9 deletions(-)
25
26
diff --git a/hw/core/loader.c b/hw/core/loader.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/core/loader.c
29
+++ b/hw/core/loader.c
30
@@ -XXX,XX +XXX,XX @@ struct Rom {
31
static FWCfgState *fw_cfg;
32
static QTAILQ_HEAD(, Rom) roms = QTAILQ_HEAD_INITIALIZER(roms);
33
34
+/* rom->data must be heap-allocated (do not use with rom_add_elf_program()) */
35
+static void rom_free(Rom *rom)
36
+{
37
+ g_free(rom->data);
38
+ g_free(rom->path);
39
+ g_free(rom->name);
40
+ g_free(rom->fw_dir);
41
+ g_free(rom->fw_file);
42
+ g_free(rom);
43
+}
44
+
45
static inline bool rom_order_compare(Rom *rom, Rom *item)
46
{
47
return ((uintptr_t)(void *)rom->as > (uintptr_t)(void *)item->as) ||
48
@@ -XXX,XX +XXX,XX @@ err:
49
if (fd != -1)
50
close(fd);
51
52
- g_free(rom->data);
53
- g_free(rom->path);
54
- g_free(rom->name);
55
- if (fw_dir) {
56
- g_free(rom->fw_dir);
57
- g_free(rom->fw_file);
58
- }
59
- g_free(rom);
60
-
61
+ rom_free(rom);
62
return -1;
63
}
64
65
--
66
2.18.0
67
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/30] loader: add rom transaction API
Deleted patch
1
From: Stefan Hajnoczi <stefanha@redhat.com>
2
1
3
Image file loaders may add a series of roms. If an error occurs partway
4
through loading there is no easy way to drop previously added roms.
5
6
This patch adds a transaction mechanism that works like this:
7
8
rom_transaction_begin();
9
...call rom_add_*()...
10
rom_transaction_end(ok);
11
12
If ok is false then roms added in this transaction are dropped.
13
14
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20180814162739.11814-5-stefanha@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/loader.h | 19 +++++++++++++++++++
20
hw/core/loader.c | 32 ++++++++++++++++++++++++++++++++
21
2 files changed, 51 insertions(+)
22
23
diff --git a/include/hw/loader.h b/include/hw/loader.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/loader.h
26
+++ b/include/hw/loader.h
27
@@ -XXX,XX +XXX,XX @@ int rom_check_and_register_reset(void);
28
void rom_set_fw(FWCfgState *f);
29
void rom_set_order_override(int order);
30
void rom_reset_order_override(void);
31
+
32
+/**
33
+ * rom_transaction_begin:
34
+ *
35
+ * Call this before of a series of rom_add_*() calls. Call
36
+ * rom_transaction_end() afterwards to commit or abort. These functions are
37
+ * useful for undoing a series of rom_add_*() calls if image file loading fails
38
+ * partway through.
39
+ */
40
+void rom_transaction_begin(void);
41
+
42
+/**
43
+ * rom_transaction_end:
44
+ * @commit: true to commit added roms, false to drop added roms
45
+ *
46
+ * Call this after a series of rom_add_*() calls. See rom_transaction_begin().
47
+ */
48
+void rom_transaction_end(bool commit);
49
+
50
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
51
void *rom_ptr(hwaddr addr, size_t size);
52
void hmp_info_roms(Monitor *mon, const QDict *qdict);
53
diff --git a/hw/core/loader.c b/hw/core/loader.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/loader.c
56
+++ b/hw/core/loader.c
57
@@ -XXX,XX +XXX,XX @@ struct Rom {
58
char *fw_dir;
59
char *fw_file;
60
61
+ bool committed;
62
+
63
hwaddr addr;
64
QTAILQ_ENTRY(Rom) next;
65
};
66
@@ -XXX,XX +XXX,XX @@ static void rom_insert(Rom *rom)
67
rom->as = &address_space_memory;
68
}
69
70
+ rom->committed = false;
71
+
72
/* List is ordered by load address in the same address space */
73
QTAILQ_FOREACH(item, &roms, next) {
74
if (rom_order_compare(rom, item)) {
75
@@ -XXX,XX +XXX,XX @@ void rom_reset_order_override(void)
76
fw_cfg_reset_order_override(fw_cfg);
77
}
78
79
+void rom_transaction_begin(void)
80
+{
81
+ Rom *rom;
82
+
83
+ /* Ignore ROMs added without the transaction API */
84
+ QTAILQ_FOREACH(rom, &roms, next) {
85
+ rom->committed = true;
86
+ }
87
+}
88
+
89
+void rom_transaction_end(bool commit)
90
+{
91
+ Rom *rom;
92
+ Rom *tmp;
93
+
94
+ QTAILQ_FOREACH_SAFE(rom, &roms, next, tmp) {
95
+ if (rom->committed) {
96
+ continue;
97
+ }
98
+ if (commit) {
99
+ rom->committed = true;
100
+ } else {
101
+ QTAILQ_REMOVE(&roms, rom, next);
102
+ rom_free(rom);
103
+ }
104
+ }
105
+}
106
+
107
static Rom *find_rom(hwaddr addr, size_t size)
108
{
109
Rom *rom;
110
--
111
2.18.0
112
113
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/30] aspeed_sdmc: Extend number of valid registers
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The SDMC on the ast2500 has 170 registers.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Tested-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20180807075757.7242-2-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/misc/aspeed_sdmc.h | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/misc/aspeed_sdmc.h
17
+++ b/include/hw/misc/aspeed_sdmc.h
18
@@ -XXX,XX +XXX,XX @@
19
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
20
#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
21
22
-#define ASPEED_SDMC_NR_REGS (0x8 >> 2)
23
+#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
24
25
typedef struct AspeedSDMCState {
26
/*< private >*/
27
--
28
2.18.0
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/30] aspeed_sdmc: Fix saved values
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
This fixes the intended protection of read-only values in the
4
configuration register. They were being always set to zero by mistake.
5
6
The read-only fields depend on the configured memory size of the system,
7
so they cannot be fixed at compile time. The most straight forward
8
option was to store them in the state structure.
9
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Tested-by: Cédric Le Goater <clg@kaod.org>
13
Message-id: 20180807075757.7242-3-joel@jms.id.au
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/misc/aspeed_sdmc.h | 1 +
17
hw/misc/aspeed_sdmc.c | 27 ++++++++-------------------
18
2 files changed, 9 insertions(+), 19 deletions(-)
19
20
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/misc/aspeed_sdmc.h
23
+++ b/include/hw/misc/aspeed_sdmc.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState {
25
uint32_t silicon_rev;
26
uint32_t ram_bits;
27
uint64_t ram_size;
28
+ uint32_t fixed_conf;
29
30
} AspeedSDMCState;
31
32
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/misc/aspeed_sdmc.c
35
+++ b/hw/misc/aspeed_sdmc.c
36
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
37
case AST2400_A0_SILICON_REV:
38
case AST2400_A1_SILICON_REV:
39
data &= ~ASPEED_SDMC_READONLY_MASK;
40
+ data |= s->fixed_conf;
41
break;
42
case AST2500_A0_SILICON_REV:
43
case AST2500_A1_SILICON_REV:
44
data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
45
+ data |= s->fixed_conf;
46
break;
47
default:
48
g_assert_not_reached();
49
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_reset(DeviceState *dev)
50
memset(s->regs, 0, sizeof(s->regs));
51
52
/* Set ram size bit and defaults values */
53
- switch (s->silicon_rev) {
54
- case AST2400_A0_SILICON_REV:
55
- case AST2400_A1_SILICON_REV:
56
- s->regs[R_CONF] |=
57
- ASPEED_SDMC_VGA_COMPAT |
58
- ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
59
- break;
60
-
61
- case AST2500_A0_SILICON_REV:
62
- case AST2500_A1_SILICON_REV:
63
- s->regs[R_CONF] |=
64
- ASPEED_SDMC_HW_VERSION(1) |
65
- ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
66
- ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
67
- break;
68
-
69
- default:
70
- g_assert_not_reached();
71
- }
72
+ s->regs[R_CONF] = s->fixed_conf;
73
}
74
75
static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
76
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
77
case AST2400_A0_SILICON_REV:
78
case AST2400_A1_SILICON_REV:
79
s->ram_bits = ast2400_rambits(s);
80
+ s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
81
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
82
break;
83
case AST2500_A0_SILICON_REV:
84
case AST2500_A1_SILICON_REV:
85
s->ram_bits = ast2500_rambits(s);
86
+ s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
87
+ ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
88
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
89
break;
90
default:
91
g_assert_not_reached();
92
--
93
2.18.0
94
95
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/30] aspeed_sdmc: Init status always idle
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
The ast2500 SDRAM training routine busy waits on the 'init cycle busy
4
state' bit in DDR PHY Control/Status register #1 (MCR60).
5
6
This ensures the bit always reads zero, and allows training to
7
complete with upstream u-boot on the ast2500-evb.
8
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Cédric Le Goater <clg@kaod.org>
11
Tested-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20180807075757.7242-5-joel@jms.id.au
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/misc/aspeed_sdmc.c | 15 +++++++++++++++
16
1 file changed, 15 insertions(+)
17
18
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/aspeed_sdmc.c
21
+++ b/hw/misc/aspeed_sdmc.c
22
@@ -XXX,XX +XXX,XX @@
23
/* Configuration Register */
24
#define R_CONF (0x04 / 4)
25
26
+/* Control/Status Register #1 (ast2500) */
27
+#define R_STATUS1 (0x60 / 4)
28
+#define PHY_BUSY_STATE BIT(0)
29
+
30
/*
31
* Configuration register Ox4 (for Aspeed AST2400 SOC)
32
*
33
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
34
g_assert_not_reached();
35
}
36
}
37
+ if (s->silicon_rev == AST2500_A0_SILICON_REV ||
38
+ s->silicon_rev == AST2500_A1_SILICON_REV) {
39
+ switch (addr) {
40
+ case R_STATUS1:
41
+ /* Will never return 'busy' */
42
+ data &= ~PHY_BUSY_STATE;
43
+ break;
44
+ default:
45
+ break;
46
+ }
47
+ }
48
49
s->regs[addr] = data;
50
}
51
--
52
2.18.0
53
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/30] aspeed_sdmc: Handle ECC training
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
This is required to ensure u-boot SDRAM training completes.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Tested-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20180807075757.7242-6-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/misc/aspeed_sdmc.c | 9 +++++++++
12
1 file changed, 9 insertions(+)
13
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
17
+++ b/hw/misc/aspeed_sdmc.c
18
@@ -XXX,XX +XXX,XX @@
19
#define R_STATUS1 (0x60 / 4)
20
#define PHY_BUSY_STATE BIT(0)
21
22
+#define R_ECC_TEST_CTRL (0x70 / 4)
23
+#define ECC_TEST_FINISHED BIT(12)
24
+#define ECC_TEST_FAIL BIT(13)
25
+
26
/*
27
* Configuration register Ox4 (for Aspeed AST2400 SOC)
28
*
29
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
30
/* Will never return 'busy' */
31
data &= ~PHY_BUSY_STATE;
32
break;
33
+ case R_ECC_TEST_CTRL:
34
+ /* Always done, always happy */
35
+ data |= ECC_TEST_FINISHED;
36
+ data &= ~ECC_TEST_FAIL;
37
+ break;
38
default:
39
break;
40
}
41
--
42
2.18.0
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/30] target/arm: Adjust FPCR_MASK for FZ16
[PULL 16/16] target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Checks for UNDEF cases should go before the "is VFP enabled?" access
2
check, except in special cases. Move a stray UNDEF check in the VTBL
3
trans function up above the access check.
2
4
3
When support for FZ16 was added, we failed to include the bit
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
within FPCR_MASK, which means that it could never be set.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
7
Message-id: 20201109145324.2859-1-peter.maydell@linaro.org
8
---
9
target/arm/translate-neon.c.inc | 8 ++++----
10
1 file changed, 4 insertions(+), 4 deletions(-)
6
11
7
Fixes: d81ce0ef2c4
12
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
8
Cc: qemu-stable@nongnu.org (3.0.1)
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
13
Message-id: 20180810193129.1556-2-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/cpu.h | 2 +-
17
target/arm/helper.c | 5 +++++
18
2 files changed, 6 insertions(+), 1 deletion(-)
19
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
14
--- a/target/arm/translate-neon.c.inc
23
+++ b/target/arm/cpu.h
15
+++ b/target/arm/translate-neon.c.inc
24
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
16
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
25
* we store the underlying state in fpscr and just mask on read/write.
17
return false;
26
*/
18
}
27
#define FPSR_MASK 0xf800009f
19
28
-#define FPCR_MASK 0x07f79f00
20
- if (!vfp_access_check(s)) {
29
+#define FPCR_MASK 0x07ff9f00
21
- return true;
30
22
- }
31
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
23
-
32
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
24
if ((a->vn + a->len + 1) > 32) {
33
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
/*
34
index XXXXXXX..XXXXXXX 100644
26
* This is UNPREDICTABLE; we choose to UNDEF to avoid the
35
--- a/target/arm/helper.c
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)
36
+++ b/target/arm/helper.c
28
return false;
37
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
29
}
38
int i;
30
39
uint32_t changed;
31
+ if (!vfp_access_check(s)) {
40
32
+ return true;
41
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
42
+ if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
43
+ val &= ~FPCR_FZ16;
44
+ }
33
+ }
45
+
34
+
46
changed = env->vfp.xregs[ARM_VFP_FPSCR];
35
desc = tcg_const_i32((a->vn << 2) | a->len);
47
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
36
def = tcg_temp_new_i64();
48
env->vfp.vec_len = (val >> 16) & 7;
37
if (a->op) {
49
--
38
--
50
2.18.0
39
2.20.1
51
40
52
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/30] target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This makes float16_muladd correctly use FZ16 not FZ.
4
5
Fixes: 6ceabaad110
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20180810193129.1556-4-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/sve_helper.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/sve_helper.c
20
+++ b/target/arm/sve_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
22
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
23
e2 = *(uint16_t *)(vm + H1_2(i));
24
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
25
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
26
+ r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
27
*(uint16_t *)(vd + H1_2(i)) = r;
28
}
29
} while (i & 63);
30
--
31
2.18.0
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/30] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
We were using the wrong flush-to-zero bit for the non-half input.
4
5
Fixes: 46d33d1e3c9
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20180810193129.1556-5-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-sve.c | 4 ++--
15
1 file changed, 2 insertions(+), 2 deletions(-)
16
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
20
+++ b/target/arm/translate-sve.c
21
@@ -XXX,XX +XXX,XX @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
22
23
static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
24
{
25
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
26
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
27
}
28
29
static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
30
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
31
32
static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
33
{
34
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
35
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
36
}
37
38
static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
39
--
40
2.18.0
41
42
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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