1 | Less than a day of post-3.0 code review and already enough | 1 | Arm queue; some of the simpler stuff, things other have reviewed (thanks!), etc. |
---|---|---|---|
2 | patches for another pullreq :-) | ||
3 | 2 | ||
4 | thanks | ||
5 | -- PMM | 3 | -- PMM |
6 | 4 | ||
7 | The following changes since commit c542a9f9794ec8e0bc3fcf5956d3cc8bce667789: | 5 | The following changes since commit 5d2f557b47dfbf8f23277a5bdd8473d4607c681a: |
8 | 6 | ||
9 | Merge remote-tracking branch 'remotes/armbru/tags/pull-tests-2018-08-16' into staging (2018-08-16 09:50:54 +0100) | 7 | Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' into staging (2020-06-05 13:53:05 +0100) |
10 | 8 | ||
11 | are available in the Git repository at: | 9 | are available in the Git repository at: |
12 | 10 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180816 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200605 |
14 | 12 | ||
15 | for you to fetch changes up to fcf13ca556f462b52956059bf8fa622bc8575edb: | 13 | for you to fetch changes up to 2c35a39eda0b16c2ed85c94cec204bf5efb97812: |
16 | 14 | ||
17 | hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() (2018-08-16 14:29:58 +0100) | 15 | target/arm: Convert Neon one-register-and-immediate insns to decodetree (2020-06-05 17:23:10 +0100) |
18 | 16 | ||
19 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
20 | target-arm queue: | 18 | target-arm queue: |
21 | * Fixes for various bugs in SVE instructions | 19 | hw/ssi/imx_spi: Handle tx burst lengths other than 8 correctly |
22 | * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board | 20 | hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask() |
23 | * hw/arm: make bitbanded IO optional on ARMv7-M | 21 | hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() |
24 | * Add model of Cortex-M0 CPU | 22 | target/arm: Convert crypto insns to gvec |
25 | * Add support for loading Intel HEX files to the generic loader | 23 | hw/adc/stm32f2xx_adc: Correct memory region size and access size |
26 | * imx_spi: Unset XCH when TX FIFO becomes empty | 24 | tests/acceptance: Add a boot test for the xlnx-versal-virt machine |
27 | * aspeed_sdmc: fix various bugs | 25 | docs/system: Document Aspeed boards |
28 | * Fix bugs in Arm FP16 instruction support | 26 | raspi: Add model of the USB controller |
29 | * Fix aa64 FCADD and FCMLA decode | 27 | target/arm: Convert 2-reg-and-shift and 1-reg-imm Neon insns to decodetree |
30 | * softfloat: Fix missing inexact for floating-point add | ||
31 | * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() | ||
32 | 28 | ||
33 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
34 | Cédric Le Goater (1): | 30 | Cédric Le Goater (1): |
35 | aspeed: add a max_ram_size property to the memory controller | 31 | docs/system: Document Aspeed boards |
36 | 32 | ||
37 | Jean-Christophe Dubois (3): | 33 | Eden Mikitas (2): |
38 | i.MX6UL: Add i.MX6UL specific CCM device | 34 | hw/ssi/imx_spi: changed while statement to prevent underflow |
39 | i.MX6UL: Add i.MX6UL SOC | 35 | hw/ssi/imx_spi: Removed unnecessary cast of rx data received from slave |
40 | i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board | ||
41 | 36 | ||
42 | Joel Stanley (5): | 37 | Paul Zimmerman (7): |
43 | aspeed_sdmc: Extend number of valid registers | 38 | raspi: add BCM2835 SOC MPHI emulation |
44 | aspeed_sdmc: Fix saved values | 39 | dwc-hsotg (dwc2) USB host controller register definitions |
45 | aspeed_sdmc: Set 'cache initial sequence' always true | 40 | dwc-hsotg (dwc2) USB host controller state definitions |
46 | aspeed_sdmc: Init status always idle | 41 | dwc-hsotg (dwc2) USB host controller emulation |
47 | aspeed_sdmc: Handle ECC training | 42 | usb: add short-packet handling to usb-storage driver |
43 | wire in the dwc-hsotg (dwc2) USB host controller emulation | ||
44 | raspi2 acceptance test: add test for dwc-hsotg (dwc2) USB host | ||
48 | 45 | ||
49 | Richard Henderson (13): | 46 | Peter Maydell (9): |
50 | target/arm: Fix typo in helper_sve_ld1hss_r | 47 | target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree |
51 | target/arm: Fix sign-extension in sve do_ldr/do_str | 48 | target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree |
52 | target/arm: Fix offset for LD1R instructions | 49 | target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree |
53 | target/arm: Fix offset scaling for LD_zprr and ST_zprr | 50 | target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree |
54 | target/arm: Reformat integer register dump | 51 | target/arm: Convert Neon narrowing shifts with op==8 to decodetree |
55 | target/arm: Dump SVE state if enabled | 52 | target/arm: Convert Neon narrowing shifts with op==9 to decodetree |
56 | target/arm: Add sve-max-vq cpu property to -cpu max | 53 | target/arm: Convert Neon VSHLL, VMOVL to decodetree |
57 | target/arm: Adjust FPCR_MASK for FZ16 | 54 | target/arm: Convert VCVT fixed-point ops to decodetree |
58 | target/arm: Ignore float_flag_input_denormal from fp_status_f16 | 55 | target/arm: Convert Neon one-register-and-immediate insns to decodetree |
59 | target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h | ||
60 | target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half | ||
61 | target/arm: Fix aa64 FCADD and FCMLA decode | ||
62 | softfloat: Fix missing inexact for floating-point add | ||
63 | 56 | ||
64 | Stefan Hajnoczi (4): | 57 | Philippe Mathieu-Daudé (3): |
65 | hw/arm: make bitbanded IO optional on ARMv7-M | 58 | hw/input/pxa2xx_keypad: Replace hw_error() by qemu_log_mask() |
66 | target/arm: add "cortex-m0" CPU model | 59 | hw/arm/pxa2xx: Replace printf() call by qemu_log_mask() |
67 | loader: extract rom_free() function | 60 | hw/adc/stm32f2xx_adc: Correct memory region size and access size |
68 | loader: add rom transaction API | ||
69 | 61 | ||
70 | Su Hang (2): | 62 | Richard Henderson (6): |
71 | loader: Implement .hex file loader | 63 | target/arm: Convert aes and sm4 to gvec helpers |
72 | Add QTest testcase for the Intel Hexadecimal | 64 | target/arm: Convert rax1 to gvec helpers |
65 | target/arm: Convert sha512 and sm3 to gvec helpers | ||
66 | target/arm: Convert sha1 and sha256 to gvec helpers | ||
67 | target/arm: Split helper_crypto_sha1_3reg | ||
68 | target/arm: Split helper_crypto_sm3tt | ||
73 | 69 | ||
74 | Thomas Huth (1): | 70 | Thomas Huth (1): |
75 | hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() | 71 | tests/acceptance: Add a boot test for the xlnx-versal-virt machine |
76 | 72 | ||
77 | Trent Piepho (1): | 73 | docs/system/arm/aspeed.rst | 85 ++ |
78 | imx_spi: Unset XCH when TX FIFO becomes empty | 74 | docs/system/target-arm.rst | 1 + |
75 | hw/usb/hcd-dwc2.h | 190 +++++ | ||
76 | include/hw/arm/bcm2835_peripherals.h | 5 +- | ||
77 | include/hw/misc/bcm2835_mphi.h | 44 + | ||
78 | include/hw/usb/dwc2-regs.h | 899 ++++++++++++++++++++ | ||
79 | target/arm/helper.h | 45 +- | ||
80 | target/arm/translate-a64.h | 3 + | ||
81 | target/arm/vec_internal.h | 33 + | ||
82 | target/arm/neon-dp.decode | 214 ++++- | ||
83 | hw/adc/stm32f2xx_adc.c | 4 +- | ||
84 | hw/arm/bcm2835_peripherals.c | 38 +- | ||
85 | hw/arm/pxa2xx.c | 66 +- | ||
86 | hw/input/pxa2xx_keypad.c | 10 +- | ||
87 | hw/misc/bcm2835_mphi.c | 191 +++++ | ||
88 | hw/ssi/imx_spi.c | 4 +- | ||
89 | hw/usb/dev-storage.c | 15 +- | ||
90 | hw/usb/hcd-dwc2.c | 1417 ++++++++++++++++++++++++++++++++ | ||
91 | target/arm/crypto_helper.c | 267 ++++-- | ||
92 | target/arm/translate-a64.c | 198 ++--- | ||
93 | target/arm/translate-neon.inc.c | 796 ++++++++++++++---- | ||
94 | target/arm/translate.c | 539 +----------- | ||
95 | target/arm/vec_helper.c | 12 +- | ||
96 | hw/misc/Makefile.objs | 1 + | ||
97 | hw/usb/Kconfig | 5 + | ||
98 | hw/usb/Makefile.objs | 1 + | ||
99 | hw/usb/trace-events | 50 ++ | ||
100 | tests/acceptance/boot_linux_console.py | 35 +- | ||
101 | 28 files changed, 4258 insertions(+), 910 deletions(-) | ||
102 | create mode 100644 docs/system/arm/aspeed.rst | ||
103 | create mode 100644 hw/usb/hcd-dwc2.h | ||
104 | create mode 100644 include/hw/misc/bcm2835_mphi.h | ||
105 | create mode 100644 include/hw/usb/dwc2-regs.h | ||
106 | create mode 100644 target/arm/vec_internal.h | ||
107 | create mode 100644 hw/misc/bcm2835_mphi.c | ||
108 | create mode 100644 hw/usb/hcd-dwc2.c | ||
79 | 109 | ||
80 | configure | 4 + | ||
81 | hw/arm/Makefile.objs | 1 + | ||
82 | hw/misc/Makefile.objs | 1 + | ||
83 | tests/Makefile.include | 2 + | ||
84 | include/hw/arm/armv7m.h | 2 + | ||
85 | include/hw/arm/fsl-imx6ul.h | 339 ++++++++++++++ | ||
86 | include/hw/loader.h | 31 ++ | ||
87 | include/hw/misc/aspeed_sdmc.h | 4 +- | ||
88 | include/hw/misc/imx6ul_ccm.h | 226 +++++++++ | ||
89 | target/arm/cpu.h | 5 +- | ||
90 | fpu/softfloat.c | 2 +- | ||
91 | hw/arm/armv7m.c | 37 +- | ||
92 | hw/arm/aspeed.c | 31 ++ | ||
93 | hw/arm/aspeed_soc.c | 2 + | ||
94 | hw/arm/fsl-imx6ul.c | 617 ++++++++++++++++++++++++ | ||
95 | hw/arm/mcimx6ul-evk.c | 85 ++++ | ||
96 | hw/arm/mps2-tz.c | 32 +- | ||
97 | hw/arm/mps2.c | 1 + | ||
98 | hw/arm/msf2-soc.c | 1 + | ||
99 | hw/arm/stellaris.c | 1 + | ||
100 | hw/arm/stm32f205_soc.c | 1 + | ||
101 | hw/core/generic-loader.c | 4 + | ||
102 | hw/core/loader.c | 302 +++++++++++- | ||
103 | hw/misc/aspeed_sdmc.c | 55 ++- | ||
104 | hw/misc/imx6ul_ccm.c | 886 +++++++++++++++++++++++++++++++++++ | ||
105 | hw/ssi/imx_spi.c | 3 +- | ||
106 | linux-user/syscall.c | 19 +- | ||
107 | target/arm/cpu.c | 17 +- | ||
108 | target/arm/cpu64.c | 29 ++ | ||
109 | target/arm/helper.c | 18 +- | ||
110 | target/arm/sve_helper.c | 4 +- | ||
111 | target/arm/translate-a64.c | 120 ++++- | ||
112 | target/arm/translate-sve.c | 30 +- | ||
113 | tests/hexloader-test.c | 45 ++ | ||
114 | MAINTAINERS | 6 + | ||
115 | default-configs/arm-softmmu.mak | 1 + | ||
116 | hw/misc/trace-events | 7 + | ||
117 | tests/hex-loader-check-data/test.hex | 18 + | ||
118 | 38 files changed, 2863 insertions(+), 126 deletions(-) | ||
119 | create mode 100644 include/hw/arm/fsl-imx6ul.h | ||
120 | create mode 100644 include/hw/misc/imx6ul_ccm.h | ||
121 | create mode 100644 hw/arm/fsl-imx6ul.c | ||
122 | create mode 100644 hw/arm/mcimx6ul-evk.c | ||
123 | create mode 100644 hw/misc/imx6ul_ccm.c | ||
124 | create mode 100644 tests/hexloader-test.c | ||
125 | create mode 100644 tests/hex-loader-check-data/test.hex | ||
126 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Eden Mikitas <e.mikitas@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15 | 3 | The while statement in question only checked if tx_burst is not 0. |
4 | we dropped the sticky bit and so failed to raise inexact. | 4 | tx_burst is a signed int, which is assigned the value put by the |
5 | guest driver in ECSPI_CONREG. The burst length can be anywhere | ||
6 | between 1 and 4096, and since tx_burst is always decremented by 8 | ||
7 | it could possibly underflow, causing an infinite loop. | ||
5 | 8 | ||
6 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 9 | Signed-off-by: Eden Mikitas <e.mikitas@gmail.com> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
8 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
9 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
10 | Message-id: 20180810193129.1556-7-richard.henderson@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 12 | --- |
13 | fpu/softfloat.c | 2 +- | 13 | hw/ssi/imx_spi.c | 2 +- |
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
15 | 15 | ||
16 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c | 16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/fpu/softfloat.c | 18 | --- a/hw/ssi/imx_spi.c |
19 | +++ b/fpu/softfloat.c | 19 | +++ b/hw/ssi/imx_spi.c |
20 | @@ -XXX,XX +XXX,XX @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, | 20 | @@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s) |
21 | } | 21 | |
22 | a.frac += b.frac; | 22 | rx = 0; |
23 | if (a.frac & DECOMPOSED_OVERFLOW_BIT) { | 23 | |
24 | - a.frac >>= 1; | 24 | - while (tx_burst) { |
25 | + shift64RightJamming(a.frac, 1, &a.frac); | 25 | + while (tx_burst > 0) { |
26 | a.exp += 1; | 26 | uint8_t byte = tx & 0xff; |
27 | } | 27 | |
28 | return a; | 28 | DPRINTF("writing 0x%02x\n", (uint32_t)byte); |
29 | -- | 29 | -- |
30 | 2.18.0 | 30 | 2.20.1 |
31 | 31 | ||
32 | 32 | diff view generated by jsdifflib |
1 | From: Trent Piepho <tpiepho@impinj.com> | 1 | From: Eden Mikitas <e.mikitas@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | The current emulation will clear the XCH bit when a burst finishes. | 3 | When inserting the value retrieved (rx) from the spi slave, rx is pushed to |
4 | This is not quite correct. According to the i.MX7d referemce manual, | 4 | rx_fifo after being cast to uint8_t. rx_fifo is a fifo32, and the rx |
5 | Rev 0.1, §10.1.7.3: | 5 | register the driver uses is also 32 bit. This zeroes the 24 most |
6 | significant bits of rx. This proved problematic with devices that expect to | ||
7 | use the whole 32 bits of the rx register. | ||
6 | 8 | ||
7 | This bit [XCH] is cleared automatically when all data in the TXFIFO | 9 | Signed-off-by: Eden Mikitas <e.mikitas@gmail.com> |
8 | and the shift register has been shifted out. | 10 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
9 | |||
10 | So XCH should be cleared when the FIFO empties, not on completion of a | ||
11 | burst. The FIFO is 64 x 32 bits = 2048 bits, while the max burst size | ||
12 | is larger at 4096 bits. So it's possible that the burst is not finished | ||
13 | after the TXFIFO empties. | ||
14 | |||
15 | Sending a large block (> 2048 bits) with the Linux driver will use a | ||
16 | burst that is larger than the TXFIFO. After the TXFIFO has emptied XCH | ||
17 | does not become unset, as the burst is not yet finished. | ||
18 | |||
19 | What should happen after the TXFIFO empties is the driver will refill it | ||
20 | and set XCH. The rising edge of XCH will trigger another transfer to | ||
21 | begin. However, since the emulation does not set XCH to 0, there is no | ||
22 | rising edge and the next trasfer never begins. | ||
23 | |||
24 | Signed-off-by: Trent Piepho <tpiepho@impinj.com> | ||
25 | Message-id: 20180731201056.29257-1-tpiepho@impinj.com | ||
26 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
28 | --- | 12 | --- |
29 | hw/ssi/imx_spi.c | 3 +-- | 13 | hw/ssi/imx_spi.c | 2 +- |
30 | 1 file changed, 1 insertion(+), 2 deletions(-) | 14 | 1 file changed, 1 insertion(+), 1 deletion(-) |
31 | 15 | ||
32 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c | 16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c |
33 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
34 | --- a/hw/ssi/imx_spi.c | 18 | --- a/hw/ssi/imx_spi.c |
35 | +++ b/hw/ssi/imx_spi.c | 19 | +++ b/hw/ssi/imx_spi.c |
36 | @@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s) | 20 | @@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s) |
21 | if (fifo32_is_full(&s->rx_fifo)) { | ||
22 | s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO; | ||
23 | } else { | ||
24 | - fifo32_push(&s->rx_fifo, (uint8_t)rx); | ||
25 | + fifo32_push(&s->rx_fifo, rx); | ||
37 | } | 26 | } |
38 | 27 | ||
39 | if (s->burst_length <= 0) { | 28 | if (s->burst_length <= 0) { |
40 | - s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH; | ||
41 | - | ||
42 | if (!imx_spi_is_multiple_master_burst(s)) { | ||
43 | s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC; | ||
44 | break; | ||
45 | @@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s) | ||
46 | |||
47 | if (fifo32_is_empty(&s->tx_fifo)) { | ||
48 | s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC; | ||
49 | + s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH; | ||
50 | } | ||
51 | |||
52 | /* TODO: We should also use TDR and RDR bits */ | ||
53 | -- | 29 | -- |
54 | 2.18.0 | 30 | 2.20.1 |
55 | 31 | ||
56 | 32 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | The SDRAM training routine sets the 'Enable cache initial' bit, and then | 3 | hw_error() calls exit(). This a bit overkill when we can log |
4 | waits for the 'cache initial sequence' to be done. | 4 | the accesses as unimplemented or guest error. |
5 | 5 | ||
6 | Have it always return done, as there is no other side effects that the | 6 | When fuzzing the devices, we don't want the whole process to |
7 | model needs to implement. This allows the upstream u-boot training to | 7 | exit. Replace some hw_error() calls by qemu_log_mask() |
8 | proceed on the ast2500-evb board. | 8 | (missed in commit 5a0001ec7e). |
9 | 9 | ||
10 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 11 | Message-id: 20200525114123.21317-2-f4bug@amsat.org |
12 | Tested-by: Cédric Le Goater <clg@kaod.org> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Message-id: 20180807075757.7242-4-joel@jms.id.au | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 14 | --- |
16 | hw/misc/aspeed_sdmc.c | 1 + | 15 | hw/input/pxa2xx_keypad.c | 10 +++++++--- |
17 | 1 file changed, 1 insertion(+) | 16 | 1 file changed, 7 insertions(+), 3 deletions(-) |
18 | 17 | ||
19 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | 18 | diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c |
20 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/misc/aspeed_sdmc.c | 20 | --- a/hw/input/pxa2xx_keypad.c |
22 | +++ b/hw/misc/aspeed_sdmc.c | 21 | +++ b/hw/input/pxa2xx_keypad.c |
23 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) | 22 | @@ -XXX,XX +XXX,XX @@ |
24 | s->ram_bits = ast2500_rambits(s); | 23 | */ |
25 | s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | 24 | |
26 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | 25 | #include "qemu/osdep.h" |
27 | + ASPEED_SDMC_CACHE_INITIAL_DONE | | 26 | -#include "hw/hw.h" |
28 | ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | 27 | +#include "qemu/log.h" |
28 | #include "hw/irq.h" | ||
29 | #include "migration/vmstate.h" | ||
30 | #include "hw/arm/pxa.h" | ||
31 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset, | ||
32 | return s->kpkdi; | ||
29 | break; | 33 | break; |
30 | default: | 34 | default: |
35 | - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); | ||
36 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
37 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
38 | + __func__, offset); | ||
39 | } | ||
40 | |||
41 | return 0; | ||
42 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_keypad_write(void *opaque, hwaddr offset, | ||
43 | break; | ||
44 | |||
45 | default: | ||
46 | - hw_error("%s: Bad offset " REG_FMT "\n", __func__, offset); | ||
47 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
48 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
49 | + __func__, offset); | ||
50 | } | ||
51 | } | ||
52 | |||
31 | -- | 53 | -- |
32 | 2.18.0 | 54 | 2.20.1 |
33 | 55 | ||
34 | 56 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Cc: qemu-stable@nongnu.org (3.0.1) | 3 | Replace printf() calls by qemu_log_mask(), which is disabled |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | by default. This avoid flooding the terminal when fuzzing the |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | device. |
6 | |||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20200525114123.21317-3-f4bug@amsat.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/sve_helper.c | 2 +- | 12 | hw/arm/pxa2xx.c | 66 ++++++++++++++++++++++++++++++++++++------------- |
9 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | 1 file changed, 49 insertions(+), 17 deletions(-) |
10 | 14 | ||
11 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 15 | diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/sve_helper.c | 17 | --- a/hw/arm/pxa2xx.c |
14 | +++ b/target/arm/sve_helper.c | 18 | +++ b/hw/arm/pxa2xx.c |
15 | @@ -XXX,XX +XXX,XX @@ DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, ) | 19 | @@ -XXX,XX +XXX,XX @@ |
16 | DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, ) | 20 | #include "sysemu/blockdev.h" |
17 | 21 | #include "sysemu/qtest.h" | |
18 | DO_LD1(sve_ld1hsu_r, cpu_lduw_data_ra, uint32_t, uint16_t, H1_4) | 22 | #include "qemu/cutils.h" |
19 | -DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int8_t, H1_4) | 23 | +#include "qemu/log.h" |
20 | +DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int16_t, H1_4) | 24 | |
21 | DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, ) | 25 | static struct { |
22 | DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, ) | 26 | hwaddr io_base; |
27 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pm_read(void *opaque, hwaddr addr, | ||
28 | return s->pm_regs[addr >> 2]; | ||
29 | default: | ||
30 | fail: | ||
31 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
32 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
33 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
34 | + __func__, addr); | ||
35 | break; | ||
36 | } | ||
37 | return 0; | ||
38 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr, | ||
39 | s->pm_regs[addr >> 2] = value; | ||
40 | break; | ||
41 | } | ||
42 | - | ||
43 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
44 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
45 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
46 | + __func__, addr); | ||
47 | break; | ||
48 | } | ||
49 | } | ||
50 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_cm_read(void *opaque, hwaddr addr, | ||
51 | return s->cm_regs[CCCR >> 2] | (3 << 28); | ||
52 | |||
53 | default: | ||
54 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
55 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
56 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
57 | + __func__, addr); | ||
58 | break; | ||
59 | } | ||
60 | return 0; | ||
61 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr, | ||
62 | break; | ||
63 | |||
64 | default: | ||
65 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
66 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
67 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
68 | + __func__, addr); | ||
69 | break; | ||
70 | } | ||
71 | } | ||
72 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_mm_read(void *opaque, hwaddr addr, | ||
73 | return s->mm_regs[addr >> 2]; | ||
74 | /* fall through */ | ||
75 | default: | ||
76 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
77 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
78 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
79 | + __func__, addr); | ||
80 | break; | ||
81 | } | ||
82 | return 0; | ||
83 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr, | ||
84 | } | ||
85 | |||
86 | default: | ||
87 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
88 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
89 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
90 | + __func__, addr); | ||
91 | break; | ||
92 | } | ||
93 | } | ||
94 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_ssp_read(void *opaque, hwaddr addr, | ||
95 | case SSACD: | ||
96 | return s->ssacd; | ||
97 | default: | ||
98 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
99 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
100 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
101 | + __func__, addr); | ||
102 | break; | ||
103 | } | ||
104 | return 0; | ||
105 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr, | ||
106 | break; | ||
107 | |||
108 | default: | ||
109 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
110 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
111 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
112 | + __func__, addr); | ||
113 | break; | ||
114 | } | ||
115 | } | ||
116 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_rtc_read(void *opaque, hwaddr addr, | ||
117 | else | ||
118 | return s->last_swcr; | ||
119 | default: | ||
120 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
121 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
122 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
123 | + __func__, addr); | ||
124 | break; | ||
125 | } | ||
126 | return 0; | ||
127 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_rtc_write(void *opaque, hwaddr addr, | ||
128 | break; | ||
129 | |||
130 | default: | ||
131 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
132 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
133 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
134 | + __func__, addr); | ||
135 | } | ||
136 | } | ||
137 | |||
138 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2c_read(void *opaque, hwaddr addr, | ||
139 | s->ibmr = 0; | ||
140 | return s->ibmr; | ||
141 | default: | ||
142 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
143 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
144 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
145 | + __func__, addr); | ||
146 | break; | ||
147 | } | ||
148 | return 0; | ||
149 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2c_write(void *opaque, hwaddr addr, | ||
150 | break; | ||
151 | |||
152 | default: | ||
153 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
154 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
155 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
156 | + __func__, addr); | ||
157 | } | ||
158 | } | ||
159 | |||
160 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_i2s_read(void *opaque, hwaddr addr, | ||
161 | } | ||
162 | return 0; | ||
163 | default: | ||
164 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
165 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
166 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
167 | + __func__, addr); | ||
168 | break; | ||
169 | } | ||
170 | return 0; | ||
171 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_i2s_write(void *opaque, hwaddr addr, | ||
172 | } | ||
173 | break; | ||
174 | default: | ||
175 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
176 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
177 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
178 | + __func__, addr); | ||
179 | } | ||
180 | } | ||
181 | |||
182 | @@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_fir_read(void *opaque, hwaddr addr, | ||
183 | case ICFOR: | ||
184 | return s->rx_len; | ||
185 | default: | ||
186 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
187 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
188 | + "%s: Bad read offset 0x%"HWADDR_PRIx"\n", | ||
189 | + __func__, addr); | ||
190 | break; | ||
191 | } | ||
192 | return 0; | ||
193 | @@ -XXX,XX +XXX,XX @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr, | ||
194 | case ICFOR: | ||
195 | break; | ||
196 | default: | ||
197 | - printf("%s: Bad register " REG_FMT "\n", __func__, addr); | ||
198 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
199 | + "%s: Bad write offset 0x%"HWADDR_PRIx"\n", | ||
200 | + __func__, addr); | ||
201 | } | ||
202 | } | ||
23 | 203 | ||
24 | -- | 204 | -- |
25 | 2.18.0 | 205 | 2.20.1 |
26 | 206 | ||
27 | 207 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Also fold the FPCR/FPSR state onto the same line as PSTATE, | 3 | With this conversion, we will be able to use the same helpers |
4 | and mention but do not dump disabled FPU state. | 4 | with sve. In particular, pass 3 vector parameters for the |
5 | 5 | 3-operand operations; for advsimd the destination register | |
6 | Cc: qemu-stable@nongnu.org (3.0.1) | 6 | is also an input. |
7 | |||
8 | This also fixes a bug in which we failed to clear the high bits | ||
9 | of the SVE register after an AdvSIMD operation. | ||
10 | |||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 12 | Message-id: 20200514212831.31248-2-richard.henderson@linaro.org |
9 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 15 | --- |
12 | target/arm/translate-a64.c | 95 +++++++++++++++++++++++++++++++++----- | 16 | target/arm/helper.h | 6 ++-- |
13 | 1 file changed, 83 insertions(+), 12 deletions(-) | 17 | target/arm/vec_internal.h | 33 +++++++++++++++++ |
14 | 18 | target/arm/crypto_helper.c | 72 +++++++++++++++++++++++++++----------- | |
19 | target/arm/translate-a64.c | 55 ++++++++++++++++++----------- | ||
20 | target/arm/translate.c | 27 +++++++------- | ||
21 | target/arm/vec_helper.c | 12 +------ | ||
22 | 6 files changed, 138 insertions(+), 67 deletions(-) | ||
23 | create mode 100644 target/arm/vec_internal.h | ||
24 | |||
25 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/helper.h | ||
28 | +++ b/target/arm/helper.h | ||
29 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
30 | DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
31 | DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
32 | |||
33 | -DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
35 | DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
36 | |||
37 | DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
38 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32) | ||
39 | DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
40 | DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
41 | |||
42 | -DEF_HELPER_FLAGS_2(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
43 | -DEF_HELPER_FLAGS_3(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
44 | +DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
45 | +DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
46 | |||
47 | DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) | ||
48 | DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) | ||
49 | diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h | ||
50 | new file mode 100644 | ||
51 | index XXXXXXX..XXXXXXX | ||
52 | --- /dev/null | ||
53 | +++ b/target/arm/vec_internal.h | ||
54 | @@ -XXX,XX +XXX,XX @@ | ||
55 | +/* | ||
56 | + * ARM AdvSIMD / SVE Vector Helpers | ||
57 | + * | ||
58 | + * Copyright (c) 2020 Linaro | ||
59 | + * | ||
60 | + * This library is free software; you can redistribute it and/or | ||
61 | + * modify it under the terms of the GNU Lesser General Public | ||
62 | + * License as published by the Free Software Foundation; either | ||
63 | + * version 2 of the License, or (at your option) any later version. | ||
64 | + * | ||
65 | + * This library is distributed in the hope that it will be useful, | ||
66 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
67 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
68 | + * Lesser General Public License for more details. | ||
69 | + * | ||
70 | + * You should have received a copy of the GNU Lesser General Public | ||
71 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
72 | + */ | ||
73 | + | ||
74 | +#ifndef TARGET_ARM_VEC_INTERNALS_H | ||
75 | +#define TARGET_ARM_VEC_INTERNALS_H | ||
76 | + | ||
77 | +static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
78 | +{ | ||
79 | + uint64_t *d = vd + opr_sz; | ||
80 | + uintptr_t i; | ||
81 | + | ||
82 | + for (i = opr_sz; i < max_sz; i += 8) { | ||
83 | + *d++ = 0; | ||
84 | + } | ||
85 | +} | ||
86 | + | ||
87 | +#endif /* TARGET_ARM_VEC_INTERNALS_H */ | ||
88 | diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/arm/crypto_helper.c | ||
91 | +++ b/target/arm/crypto_helper.c | ||
92 | @@ -XXX,XX +XXX,XX @@ | ||
93 | |||
94 | #include "cpu.h" | ||
95 | #include "exec/helper-proto.h" | ||
96 | +#include "tcg/tcg-gvec-desc.h" | ||
97 | #include "crypto/aes.h" | ||
98 | +#include "vec_internal.h" | ||
99 | |||
100 | union CRYPTO_STATE { | ||
101 | uint8_t bytes[16]; | ||
102 | @@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE { | ||
103 | #define CR_ST_WORD(state, i) (state.words[i]) | ||
104 | #endif | ||
105 | |||
106 | -void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt) | ||
107 | +static void do_crypto_aese(uint64_t *rd, uint64_t *rn, | ||
108 | + uint64_t *rm, bool decrypt) | ||
109 | { | ||
110 | static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox }; | ||
111 | static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts }; | ||
112 | - uint64_t *rd = vd; | ||
113 | - uint64_t *rm = vm; | ||
114 | union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } }; | ||
115 | - union CRYPTO_STATE st = { .l = { rd[0], rd[1] } }; | ||
116 | + union CRYPTO_STATE st = { .l = { rn[0], rn[1] } }; | ||
117 | int i; | ||
118 | |||
119 | - assert(decrypt < 2); | ||
120 | - | ||
121 | /* xor state vector with round key */ | ||
122 | rk.l[0] ^= st.l[0]; | ||
123 | rk.l[1] ^= st.l[1]; | ||
124 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt) | ||
125 | rd[1] = st.l[1]; | ||
126 | } | ||
127 | |||
128 | -void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt) | ||
129 | +void HELPER(crypto_aese)(void *vd, void *vn, void *vm, uint32_t desc) | ||
130 | +{ | ||
131 | + intptr_t i, opr_sz = simd_oprsz(desc); | ||
132 | + bool decrypt = simd_data(desc); | ||
133 | + | ||
134 | + for (i = 0; i < opr_sz; i += 16) { | ||
135 | + do_crypto_aese(vd + i, vn + i, vm + i, decrypt); | ||
136 | + } | ||
137 | + clear_tail(vd, opr_sz, simd_maxsz(desc)); | ||
138 | +} | ||
139 | + | ||
140 | +static void do_crypto_aesmc(uint64_t *rd, uint64_t *rm, bool decrypt) | ||
141 | { | ||
142 | static uint32_t const mc[][256] = { { | ||
143 | /* MixColumns lookup table */ | ||
144 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt) | ||
145 | 0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d, | ||
146 | } }; | ||
147 | |||
148 | - uint64_t *rd = vd; | ||
149 | - uint64_t *rm = vm; | ||
150 | union CRYPTO_STATE st = { .l = { rm[0], rm[1] } }; | ||
151 | int i; | ||
152 | |||
153 | - assert(decrypt < 2); | ||
154 | - | ||
155 | for (i = 0; i < 16; i += 4) { | ||
156 | CR_ST_WORD(st, i >> 2) = | ||
157 | mc[decrypt][CR_ST_BYTE(st, i)] ^ | ||
158 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt) | ||
159 | rd[1] = st.l[1]; | ||
160 | } | ||
161 | |||
162 | +void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t desc) | ||
163 | +{ | ||
164 | + intptr_t i, opr_sz = simd_oprsz(desc); | ||
165 | + bool decrypt = simd_data(desc); | ||
166 | + | ||
167 | + for (i = 0; i < opr_sz; i += 16) { | ||
168 | + do_crypto_aesmc(vd + i, vm + i, decrypt); | ||
169 | + } | ||
170 | + clear_tail(vd, opr_sz, simd_maxsz(desc)); | ||
171 | +} | ||
172 | + | ||
173 | /* | ||
174 | * SHA-1 logical functions | ||
175 | */ | ||
176 | @@ -XXX,XX +XXX,XX @@ static uint8_t const sm4_sbox[] = { | ||
177 | 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, | ||
178 | }; | ||
179 | |||
180 | -void HELPER(crypto_sm4e)(void *vd, void *vn) | ||
181 | +static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm) | ||
182 | { | ||
183 | - uint64_t *rd = vd; | ||
184 | - uint64_t *rn = vn; | ||
185 | - union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; | ||
186 | - union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; | ||
187 | + union CRYPTO_STATE d = { .l = { rn[0], rn[1] } }; | ||
188 | + union CRYPTO_STATE n = { .l = { rm[0], rm[1] } }; | ||
189 | uint32_t t, i; | ||
190 | |||
191 | for (i = 0; i < 4; i++) { | ||
192 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4e)(void *vd, void *vn) | ||
193 | rd[1] = d.l[1]; | ||
194 | } | ||
195 | |||
196 | -void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm) | ||
197 | +void HELPER(crypto_sm4e)(void *vd, void *vn, void *vm, uint32_t desc) | ||
198 | +{ | ||
199 | + intptr_t i, opr_sz = simd_oprsz(desc); | ||
200 | + | ||
201 | + for (i = 0; i < opr_sz; i += 16) { | ||
202 | + do_crypto_sm4e(vd + i, vn + i, vm + i); | ||
203 | + } | ||
204 | + clear_tail(vd, opr_sz, simd_maxsz(desc)); | ||
205 | +} | ||
206 | + | ||
207 | +static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm) | ||
208 | { | ||
209 | - uint64_t *rd = vd; | ||
210 | - uint64_t *rn = vn; | ||
211 | - uint64_t *rm = vm; | ||
212 | union CRYPTO_STATE d; | ||
213 | union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; | ||
214 | union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; | ||
215 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm) | ||
216 | rd[0] = d.l[0]; | ||
217 | rd[1] = d.l[1]; | ||
218 | } | ||
219 | + | ||
220 | +void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc) | ||
221 | +{ | ||
222 | + intptr_t i, opr_sz = simd_oprsz(desc); | ||
223 | + | ||
224 | + for (i = 0; i < opr_sz; i += 16) { | ||
225 | + do_crypto_sm4ekey(vd + i, vn + i, vm + i); | ||
226 | + } | ||
227 | + clear_tail(vd, opr_sz, simd_maxsz(desc)); | ||
228 | +} | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 229 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
16 | index XXXXXXX..XXXXXXX 100644 | 230 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 231 | --- a/target/arm/translate-a64.c |
18 | +++ b/target/arm/translate-a64.c | 232 | +++ b/target/arm/translate-a64.c |
19 | @@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | 233 | @@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, int rd, int rn, int rm, |
20 | } else { | 234 | is_q ? 16 : 8, vec_full_reg_size(s)); |
21 | ns_status = ""; | 235 | } |
236 | |||
237 | +/* Expand a 2-operand operation using an out-of-line helper. */ | ||
238 | +static void gen_gvec_op2_ool(DisasContext *s, bool is_q, int rd, | ||
239 | + int rn, int data, gen_helper_gvec_2 *fn) | ||
240 | +{ | ||
241 | + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd), | ||
242 | + vec_full_reg_offset(s, rn), | ||
243 | + is_q ? 16 : 8, vec_full_reg_size(s), data, fn); | ||
244 | +} | ||
245 | + | ||
246 | /* Expand a 3-operand operation using an out-of-line helper. */ | ||
247 | static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd, | ||
248 | int rn, int rm, int data, gen_helper_gvec_3 *fn) | ||
249 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn) | ||
250 | int rn = extract32(insn, 5, 5); | ||
251 | int rd = extract32(insn, 0, 5); | ||
252 | int decrypt; | ||
253 | - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; | ||
254 | - TCGv_i32 tcg_decrypt; | ||
255 | - CryptoThreeOpIntFn *genfn; | ||
256 | + gen_helper_gvec_2 *genfn2 = NULL; | ||
257 | + gen_helper_gvec_3 *genfn3 = NULL; | ||
258 | |||
259 | if (!dc_isar_feature(aa64_aes, s) || size != 0) { | ||
260 | unallocated_encoding(s); | ||
261 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn) | ||
262 | switch (opcode) { | ||
263 | case 0x4: /* AESE */ | ||
264 | decrypt = 0; | ||
265 | - genfn = gen_helper_crypto_aese; | ||
266 | + genfn3 = gen_helper_crypto_aese; | ||
267 | break; | ||
268 | case 0x6: /* AESMC */ | ||
269 | decrypt = 0; | ||
270 | - genfn = gen_helper_crypto_aesmc; | ||
271 | + genfn2 = gen_helper_crypto_aesmc; | ||
272 | break; | ||
273 | case 0x5: /* AESD */ | ||
274 | decrypt = 1; | ||
275 | - genfn = gen_helper_crypto_aese; | ||
276 | + genfn3 = gen_helper_crypto_aese; | ||
277 | break; | ||
278 | case 0x7: /* AESIMC */ | ||
279 | decrypt = 1; | ||
280 | - genfn = gen_helper_crypto_aesmc; | ||
281 | + genfn2 = gen_helper_crypto_aesmc; | ||
282 | break; | ||
283 | default: | ||
284 | unallocated_encoding(s); | ||
285 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn) | ||
286 | if (!fp_access_check(s)) { | ||
287 | return; | ||
22 | } | 288 | } |
23 | - | 289 | - |
24 | - cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n", | 290 | - tcg_rd_ptr = vec_full_reg_ptr(s, rd); |
25 | + cpu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c", | 291 | - tcg_rn_ptr = vec_full_reg_ptr(s, rn); |
26 | psr, | 292 | - tcg_decrypt = tcg_const_i32(decrypt); |
27 | psr & PSTATE_N ? 'N' : '-', | 293 | - |
28 | psr & PSTATE_Z ? 'Z' : '-', | 294 | - genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt); |
29 | @@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | 295 | - |
30 | el, | 296 | - tcg_temp_free_ptr(tcg_rd_ptr); |
31 | psr & PSTATE_SP ? 'h' : 't'); | 297 | - tcg_temp_free_ptr(tcg_rn_ptr); |
32 | 298 | - tcg_temp_free_i32(tcg_decrypt); | |
33 | - if (flags & CPU_DUMP_FPU) { | 299 | + if (genfn2) { |
34 | - int numvfpregs = 32; | 300 | + gen_gvec_op2_ool(s, true, rd, rn, decrypt, genfn2); |
35 | - for (i = 0; i < numvfpregs; i++) { | 301 | + } else { |
36 | - uint64_t *q = aa64_vfp_qreg(env, i); | 302 | + gen_gvec_op3_ool(s, true, rd, rd, rn, decrypt, genfn3); |
37 | - uint64_t vlo = q[0]; | 303 | + } |
38 | - uint64_t vhi = q[1]; | 304 | } |
39 | - cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c", | 305 | |
40 | - i, vhi, vlo, (i & 1 ? '\n' : ' ')); | 306 | /* Crypto three-reg SHA |
41 | + if (!(flags & CPU_DUMP_FPU)) { | 307 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) |
42 | + cpu_fprintf(f, "\n"); | 308 | int rn = extract32(insn, 5, 5); |
309 | int rd = extract32(insn, 0, 5); | ||
310 | bool feature; | ||
311 | - CryptoThreeOpFn *genfn; | ||
312 | + CryptoThreeOpFn *genfn = NULL; | ||
313 | + gen_helper_gvec_3 *oolfn = NULL; | ||
314 | |||
315 | if (o == 0) { | ||
316 | switch (opcode) { | ||
317 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
318 | break; | ||
319 | case 2: /* SM4EKEY */ | ||
320 | feature = dc_isar_feature(aa64_sm4, s); | ||
321 | - genfn = gen_helper_crypto_sm4ekey; | ||
322 | + oolfn = gen_helper_crypto_sm4ekey; | ||
323 | break; | ||
324 | default: | ||
325 | unallocated_encoding(s); | ||
326 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
327 | return; | ||
328 | } | ||
329 | |||
330 | + if (oolfn) { | ||
331 | + gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | ||
43 | + return; | 332 | + return; |
44 | + } | 333 | + } |
45 | + cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n", | 334 | + |
46 | + vfp_get_fpcr(env), vfp_get_fpsr(env)); | 335 | if (genfn) { |
47 | + | 336 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; |
48 | + if (arm_feature(env, ARM_FEATURE_SVE)) { | 337 | |
49 | + int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */ | 338 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) |
50 | + | 339 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; |
51 | + for (i = 0; i <= FFR_PRED_NUM; i++) { | 340 | bool feature; |
52 | + bool eol; | 341 | CryptoTwoOpFn *genfn; |
53 | + if (i == FFR_PRED_NUM) { | 342 | + gen_helper_gvec_3 *oolfn = NULL; |
54 | + cpu_fprintf(f, "FFR="); | 343 | |
55 | + /* It's last, so end the line. */ | 344 | switch (opcode) { |
56 | + eol = true; | 345 | case 0: /* SHA512SU0 */ |
57 | + } else { | 346 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) |
58 | + cpu_fprintf(f, "P%02d=", i); | 347 | break; |
59 | + switch (zcr_len) { | 348 | case 1: /* SM4E */ |
60 | + case 0: | 349 | feature = dc_isar_feature(aa64_sm4, s); |
61 | + eol = i % 8 == 7; | 350 | - genfn = gen_helper_crypto_sm4e; |
62 | + break; | 351 | + oolfn = gen_helper_crypto_sm4e; |
63 | + case 1: | 352 | break; |
64 | + eol = i % 6 == 5; | 353 | default: |
65 | + break; | 354 | unallocated_encoding(s); |
66 | + case 2: | 355 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) |
67 | + case 3: | 356 | return; |
68 | + eol = i % 3 == 2; | ||
69 | + break; | ||
70 | + default: | ||
71 | + /* More than one quadword per predicate. */ | ||
72 | + eol = true; | ||
73 | + break; | ||
74 | + } | ||
75 | + } | ||
76 | + for (j = zcr_len / 4; j >= 0; j--) { | ||
77 | + int digits; | ||
78 | + if (j * 4 + 4 <= zcr_len + 1) { | ||
79 | + digits = 16; | ||
80 | + } else { | ||
81 | + digits = (zcr_len % 4 + 1) * 4; | ||
82 | + } | ||
83 | + cpu_fprintf(f, "%0*" PRIx64 "%s", digits, | ||
84 | + env->vfp.pregs[i].p[j], | ||
85 | + j ? ":" : eol ? "\n" : " "); | ||
86 | + } | ||
87 | + } | ||
88 | + | ||
89 | + for (i = 0; i < 32; i++) { | ||
90 | + if (zcr_len == 0) { | ||
91 | + cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", | ||
92 | + i, env->vfp.zregs[i].d[1], | ||
93 | + env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); | ||
94 | + } else if (zcr_len == 1) { | ||
95 | + cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 | ||
96 | + ":%016" PRIx64 ":%016" PRIx64 "\n", | ||
97 | + i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], | ||
98 | + env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); | ||
99 | + } else { | ||
100 | + for (j = zcr_len; j >= 0; j--) { | ||
101 | + bool odd = (zcr_len - j) % 2 != 0; | ||
102 | + if (j == zcr_len) { | ||
103 | + cpu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); | ||
104 | + } else if (!odd) { | ||
105 | + if (j > 0) { | ||
106 | + cpu_fprintf(f, " [%x-%x]=", j, j - 1); | ||
107 | + } else { | ||
108 | + cpu_fprintf(f, " [%x]=", j); | ||
109 | + } | ||
110 | + } | ||
111 | + cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", | ||
112 | + env->vfp.zregs[i].d[j * 2 + 1], | ||
113 | + env->vfp.zregs[i].d[j * 2], | ||
114 | + odd || j == 0 ? "\n" : ":"); | ||
115 | + } | ||
116 | + } | ||
117 | + } | ||
118 | + } else { | ||
119 | + for (i = 0; i < 32; i++) { | ||
120 | + uint64_t *q = aa64_vfp_qreg(env, i); | ||
121 | + cpu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s", | ||
122 | + i, q[1], q[0], (i & 1 ? "\n" : " ")); | ||
123 | } | ||
124 | - cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", | ||
125 | - vfp_get_fpcr(env), vfp_get_fpsr(env)); | ||
126 | } | 357 | } |
127 | } | 358 | |
128 | 359 | + if (oolfn) { | |
360 | + gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn); | ||
361 | + return; | ||
362 | + } | ||
363 | + | ||
364 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
365 | tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
366 | |||
367 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
368 | index XXXXXXX..XXXXXXX 100644 | ||
369 | --- a/target/arm/translate.c | ||
370 | +++ b/target/arm/translate.c | ||
371 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
372 | if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) { | ||
373 | return 1; | ||
374 | } | ||
375 | - ptr1 = vfp_reg_ptr(true, rd); | ||
376 | - ptr2 = vfp_reg_ptr(true, rm); | ||
377 | - | ||
378 | - /* Bit 6 is the lowest opcode bit; it distinguishes between | ||
379 | - * encryption (AESE/AESMC) and decryption (AESD/AESIMC) | ||
380 | - */ | ||
381 | - tmp3 = tcg_const_i32(extract32(insn, 6, 1)); | ||
382 | - | ||
383 | + /* | ||
384 | + * Bit 6 is the lowest opcode bit; it distinguishes | ||
385 | + * between encryption (AESE/AESMC) and decryption | ||
386 | + * (AESD/AESIMC). | ||
387 | + */ | ||
388 | if (op == NEON_2RM_AESE) { | ||
389 | - gen_helper_crypto_aese(ptr1, ptr2, tmp3); | ||
390 | + tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd), | ||
391 | + vfp_reg_offset(true, rd), | ||
392 | + vfp_reg_offset(true, rm), | ||
393 | + 16, 16, extract32(insn, 6, 1), | ||
394 | + gen_helper_crypto_aese); | ||
395 | } else { | ||
396 | - gen_helper_crypto_aesmc(ptr1, ptr2, tmp3); | ||
397 | + tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd), | ||
398 | + vfp_reg_offset(true, rm), | ||
399 | + 16, 16, extract32(insn, 6, 1), | ||
400 | + gen_helper_crypto_aesmc); | ||
401 | } | ||
402 | - tcg_temp_free_ptr(ptr1); | ||
403 | - tcg_temp_free_ptr(ptr2); | ||
404 | - tcg_temp_free_i32(tmp3); | ||
405 | break; | ||
406 | case NEON_2RM_SHA1H: | ||
407 | if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) { | ||
408 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
409 | index XXXXXXX..XXXXXXX 100644 | ||
410 | --- a/target/arm/vec_helper.c | ||
411 | +++ b/target/arm/vec_helper.c | ||
412 | @@ -XXX,XX +XXX,XX @@ | ||
413 | #include "exec/helper-proto.h" | ||
414 | #include "tcg/tcg-gvec-desc.h" | ||
415 | #include "fpu/softfloat.h" | ||
416 | - | ||
417 | +#include "vec_internal.h" | ||
418 | |||
419 | /* Note that vector data is stored in host-endian 64-bit chunks, | ||
420 | so addressing units smaller than that needs a host-endian fixup. */ | ||
421 | @@ -XXX,XX +XXX,XX @@ | ||
422 | #define H4(x) (x) | ||
423 | #endif | ||
424 | |||
425 | -static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) | ||
426 | -{ | ||
427 | - uint64_t *d = vd + opr_sz; | ||
428 | - uintptr_t i; | ||
429 | - | ||
430 | - for (i = opr_sz; i < max_sz; i += 8) { | ||
431 | - *d++ = 0; | ||
432 | - } | ||
433 | -} | ||
434 | - | ||
435 | /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */ | ||
436 | static int16_t inl_qrdmlah_s16(int16_t src1, int16_t src2, | ||
437 | int16_t src3, uint32_t *sat) | ||
129 | -- | 438 | -- |
130 | 2.18.0 | 439 | 2.20.1 |
131 | 440 | ||
132 | 441 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This allows the default (and maximum) vector length to be set | 3 | With this conversion, we will be able to use the same helpers |
4 | from the command-line. Which is extraordinarily helpful in | 4 | with sve. This also fixes a bug in which we failed to clear |
5 | debugging problems depending on vector length without having to | 5 | the high bits of the SVE register after an AdvSIMD operation. |
6 | bake knowledge of PR_SET_SVE_VL into every guest binary. | ||
7 | 6 | ||
8 | Cc: qemu-stable@nongnu.org (3.0.1) | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 8 | Message-id: 20200514212831.31248-3-richard.henderson@linaro.org |
11 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | target/arm/cpu.h | 3 +++ | 12 | target/arm/helper.h | 2 ++ |
15 | linux-user/syscall.c | 19 +++++++++++++------ | 13 | target/arm/translate-a64.h | 3 ++ |
16 | target/arm/cpu.c | 6 +++--- | 14 | target/arm/crypto_helper.c | 11 +++++++ |
17 | target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++ | 15 | target/arm/translate-a64.c | 59 ++++++++++++++++++++------------------ |
18 | target/arm/helper.c | 7 +++++-- | 16 | 4 files changed, 47 insertions(+), 28 deletions(-) |
19 | 5 files changed, 53 insertions(+), 11 deletions(-) | ||
20 | 17 | ||
21 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 18 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
22 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/cpu.h | 20 | --- a/target/arm/helper.h |
24 | +++ b/target/arm/cpu.h | 21 | +++ b/target/arm/helper.h |
25 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) |
26 | 23 | DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | |
27 | /* Used to synchronize KVM and QEMU in-kernel device levels */ | 24 | DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
28 | uint8_t device_irq_level; | 25 | |
26 | +DEF_HELPER_FLAGS_4(crypto_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
29 | + | 27 | + |
30 | + /* Used to set the maximum vector length the cpu will support. */ | 28 | DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) |
31 | + uint32_t sve_max_vq; | 29 | DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) |
32 | }; | 30 | |
33 | 31 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | |
34 | static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) | ||
35 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/linux-user/syscall.c | 33 | --- a/target/arm/translate-a64.h |
38 | +++ b/linux-user/syscall.c | 34 | +++ b/target/arm/translate-a64.h |
39 | @@ -XXX,XX +XXX,XX @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1, | 35 | @@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s) |
40 | #endif | 36 | |
41 | #ifdef TARGET_AARCH64 | 37 | bool disas_sve(DisasContext *, uint32_t); |
42 | case TARGET_PR_SVE_SET_VL: | 38 | |
43 | - /* We cannot support either PR_SVE_SET_VL_ONEXEC | 39 | +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
44 | - or PR_SVE_VL_INHERIT. Therefore, anything above | 40 | + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); |
45 | - ARM_MAX_VQ results in EINVAL. */ | ||
46 | + /* | ||
47 | + * We cannot support either PR_SVE_SET_VL_ONEXEC or | ||
48 | + * PR_SVE_VL_INHERIT. Note the kernel definition | ||
49 | + * of sve_vl_valid allows for VQ=512, i.e. VL=8192, | ||
50 | + * even though the current architectural maximum is VQ=16. | ||
51 | + */ | ||
52 | ret = -TARGET_EINVAL; | ||
53 | if (arm_feature(cpu_env, ARM_FEATURE_SVE) | ||
54 | - && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) { | ||
55 | + && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) { | ||
56 | CPUARMState *env = cpu_env; | ||
57 | - int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; | ||
58 | - int vq = MAX(arg2 / 16, 1); | ||
59 | + ARMCPU *cpu = arm_env_get_cpu(env); | ||
60 | + uint32_t vq, old_vq; | ||
61 | + | 41 | + |
62 | + old_vq = (env->vfp.zcr_el[1] & 0xf) + 1; | 42 | #endif /* TARGET_ARM_TRANSLATE_A64_H */ |
63 | + vq = MAX(arg2 / 16, 1); | 43 | diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c |
64 | + vq = MIN(vq, cpu->sve_max_vq); | ||
65 | |||
66 | if (vq < old_vq) { | ||
67 | aarch64_sve_narrow_vq(env, vq); | ||
68 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | 44 | index XXXXXXX..XXXXXXX 100644 |
70 | --- a/target/arm/cpu.c | 45 | --- a/target/arm/crypto_helper.c |
71 | +++ b/target/arm/cpu.c | 46 | +++ b/target/arm/crypto_helper.c |
72 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 47 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm4ekey)(void *vd, void *vn, void* vm, uint32_t desc) |
73 | env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); | 48 | } |
74 | env->cp15.cptr_el[3] |= CPTR_EZ; | 49 | clear_tail(vd, opr_sz, simd_maxsz(desc)); |
75 | /* with maximum vector length */ | 50 | } |
76 | - env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; | 51 | + |
77 | - env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; | 52 | +void HELPER(crypto_rax1)(void *vd, void *vn, void *vm, uint32_t desc) |
78 | - env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; | 53 | +{ |
79 | + env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; | 54 | + intptr_t i, opr_sz = simd_oprsz(desc); |
80 | + env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; | 55 | + uint64_t *d = vd, *n = vn, *m = vm; |
81 | + env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; | 56 | + |
82 | #else | 57 | + for (i = 0; i < opr_sz / 8; ++i) { |
83 | /* Reset into the highest available EL */ | 58 | + d[i] = n[i] ^ rol64(m[i], 1); |
84 | if (arm_feature(env, ARM_FEATURE_EL3)) { | 59 | + } |
85 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 60 | + clear_tail(vd, opr_sz, simd_maxsz(desc)); |
61 | +} | ||
62 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | 63 | index XXXXXXX..XXXXXXX 100644 |
87 | --- a/target/arm/cpu64.c | 64 | --- a/target/arm/translate-a64.c |
88 | +++ b/target/arm/cpu64.c | 65 | +++ b/target/arm/translate-a64.c |
89 | @@ -XXX,XX +XXX,XX @@ | 66 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) |
90 | #include "sysemu/sysemu.h" | 67 | tcg_temp_free_ptr(tcg_rn_ptr); |
91 | #include "sysemu/kvm.h" | ||
92 | #include "kvm_arm.h" | ||
93 | +#include "qapi/visitor.h" | ||
94 | |||
95 | static inline void set_feature(CPUARMState *env, int feature) | ||
96 | { | ||
97 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj) | ||
98 | define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); | ||
99 | } | 68 | } |
100 | 69 | ||
101 | +static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, | 70 | +static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) |
102 | + void *opaque, Error **errp) | ||
103 | +{ | 71 | +{ |
104 | + ARMCPU *cpu = ARM_CPU(obj); | 72 | + tcg_gen_rotli_i64(d, m, 1); |
105 | + visit_type_uint32(v, name, &cpu->sve_max_vq, errp); | 73 | + tcg_gen_xor_i64(d, d, n); |
106 | +} | 74 | +} |
107 | + | 75 | + |
108 | +static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, | 76 | +static void gen_rax1_vec(unsigned vece, TCGv_vec d, TCGv_vec n, TCGv_vec m) |
109 | + void *opaque, Error **errp) | ||
110 | +{ | 77 | +{ |
111 | + ARMCPU *cpu = ARM_CPU(obj); | 78 | + tcg_gen_rotli_vec(vece, d, m, 1); |
112 | + Error *err = NULL; | 79 | + tcg_gen_xor_vec(vece, d, d, n); |
113 | + | ||
114 | + visit_type_uint32(v, name, &cpu->sve_max_vq, &err); | ||
115 | + | ||
116 | + if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) { | ||
117 | + error_setg(&err, "unsupported SVE vector length"); | ||
118 | + error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", | ||
119 | + ARM_MAX_VQ); | ||
120 | + } | ||
121 | + error_propagate(errp, err); | ||
122 | +} | 80 | +} |
123 | + | 81 | + |
124 | /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); | 82 | +void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, |
125 | * otherwise, a CPU with as many features enabled as our emulation supports. | 83 | + uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz) |
126 | * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; | 84 | +{ |
127 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 85 | + static const TCGOpcode vecop_list[] = { INDEX_op_rotli_vec, 0 }; |
128 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | 86 | + static const GVecGen3 op = { |
129 | cpu->dcz_blocksize = 7; /* 512 bytes */ | 87 | + .fni8 = gen_rax1_i64, |
130 | #endif | 88 | + .fniv = gen_rax1_vec, |
89 | + .opt_opc = vecop_list, | ||
90 | + .fno = gen_helper_crypto_rax1, | ||
91 | + .vece = MO_64, | ||
92 | + }; | ||
93 | + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &op); | ||
94 | +} | ||
131 | + | 95 | + |
132 | + cpu->sve_max_vq = ARM_MAX_VQ; | 96 | /* Crypto three-reg SHA512 |
133 | + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq, | 97 | * 31 21 20 16 15 14 13 12 11 10 9 5 4 0 |
134 | + cpu_max_set_sve_vq, NULL, NULL, &error_fatal); | 98 | * +-----------------------+------+---+---+-----+--------+------+------+ |
99 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
100 | bool feature; | ||
101 | CryptoThreeOpFn *genfn = NULL; | ||
102 | gen_helper_gvec_3 *oolfn = NULL; | ||
103 | + GVecGen3Fn *gvecfn = NULL; | ||
104 | |||
105 | if (o == 0) { | ||
106 | switch (opcode) { | ||
107 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
108 | break; | ||
109 | case 3: /* RAX1 */ | ||
110 | feature = dc_isar_feature(aa64_sha3, s); | ||
111 | - genfn = NULL; | ||
112 | + gvecfn = gen_gvec_rax1; | ||
113 | break; | ||
114 | default: | ||
115 | g_assert_not_reached(); | ||
116 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
117 | |||
118 | if (oolfn) { | ||
119 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | ||
120 | - return; | ||
121 | - } | ||
122 | - | ||
123 | - if (genfn) { | ||
124 | + } else if (gvecfn) { | ||
125 | + gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); | ||
126 | + } else { | ||
127 | TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; | ||
128 | |||
129 | tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
130 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
131 | tcg_temp_free_ptr(tcg_rd_ptr); | ||
132 | tcg_temp_free_ptr(tcg_rn_ptr); | ||
133 | tcg_temp_free_ptr(tcg_rm_ptr); | ||
134 | - } else { | ||
135 | - TCGv_i64 tcg_op1, tcg_op2, tcg_res[2]; | ||
136 | - int pass; | ||
137 | - | ||
138 | - tcg_op1 = tcg_temp_new_i64(); | ||
139 | - tcg_op2 = tcg_temp_new_i64(); | ||
140 | - tcg_res[0] = tcg_temp_new_i64(); | ||
141 | - tcg_res[1] = tcg_temp_new_i64(); | ||
142 | - | ||
143 | - for (pass = 0; pass < 2; pass++) { | ||
144 | - read_vec_element(s, tcg_op1, rn, pass, MO_64); | ||
145 | - read_vec_element(s, tcg_op2, rm, pass, MO_64); | ||
146 | - | ||
147 | - tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1); | ||
148 | - tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1); | ||
149 | - } | ||
150 | - write_vec_element(s, tcg_res[0], rd, 0, MO_64); | ||
151 | - write_vec_element(s, tcg_res[1], rd, 1, MO_64); | ||
152 | - | ||
153 | - tcg_temp_free_i64(tcg_op1); | ||
154 | - tcg_temp_free_i64(tcg_op2); | ||
155 | - tcg_temp_free_i64(tcg_res[0]); | ||
156 | - tcg_temp_free_i64(tcg_res[1]); | ||
135 | } | 157 | } |
136 | } | 158 | } |
137 | 159 | ||
138 | @@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) | ||
139 | uint64_t pmask; | ||
140 | |||
141 | assert(vq >= 1 && vq <= ARM_MAX_VQ); | ||
142 | + assert(vq <= arm_env_get_cpu(env)->sve_max_vq); | ||
143 | |||
144 | /* Zap the high bits of the zregs. */ | ||
145 | for (i = 0; i < 32; i++) { | ||
146 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
147 | index XXXXXXX..XXXXXXX 100644 | ||
148 | --- a/target/arm/helper.c | ||
149 | +++ b/target/arm/helper.c | ||
150 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
151 | zcr_len = 0; | ||
152 | } else { | ||
153 | int current_el = arm_current_el(env); | ||
154 | + ARMCPU *cpu = arm_env_get_cpu(env); | ||
155 | |||
156 | - zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el]; | ||
157 | - zcr_len &= 0xf; | ||
158 | + zcr_len = cpu->sve_max_vq - 1; | ||
159 | + if (current_el <= 1) { | ||
160 | + zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); | ||
161 | + } | ||
162 | if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { | ||
163 | zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); | ||
164 | } | ||
165 | -- | 160 | -- |
166 | 2.18.0 | 161 | 2.20.1 |
167 | 162 | ||
168 | 163 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This makes float16_muladd correctly use FZ16 not FZ. | 3 | Do not yet convert the helpers to loop over opr_sz, but the |
4 | 4 | descriptor allows the vector tail to be cleared. Which fixes | |
5 | Fixes: 6ceabaad110 | 5 | an existing bug vs SVE. |
6 | Cc: qemu-stable@nongnu.org (3.0.1) | 6 | |
7 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 8 | Message-id: 20200514212831.31248-4-richard.henderson@linaro.org |
10 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20180810193129.1556-4-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | target/arm/sve_helper.c | 2 +- | 12 | target/arm/helper.h | 15 +++++++----- |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 13 | target/arm/crypto_helper.c | 37 +++++++++++++++++++++++----- |
16 | 14 | target/arm/translate-a64.c | 50 ++++++++++++-------------------------- | |
17 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 15 | 3 files changed, 55 insertions(+), 47 deletions(-) |
16 | |||
17 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/sve_helper.c | 19 | --- a/target/arm/helper.h |
20 | +++ b/target/arm/sve_helper.c | 20 | +++ b/target/arm/helper.h |
21 | @@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc, | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) |
22 | e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1; | 22 | DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr) |
23 | e2 = *(uint16_t *)(vm + H1_2(i)); | 23 | DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) |
24 | e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3; | 24 | |
25 | - r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status); | 25 | -DEF_HELPER_FLAGS_3(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) |
26 | + r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16); | 26 | -DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) |
27 | *(uint16_t *)(vd + H1_2(i)) = r; | 27 | -DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr) |
28 | } | 28 | -DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) |
29 | } while (i & 63); | 29 | +DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) |
30 | +DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, | ||
33 | + void, ptr, ptr, ptr, i32) | ||
34 | |||
35 | DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32) | ||
36 | -DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
37 | -DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
38 | +DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, | ||
39 | + void, ptr, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, | ||
41 | + void, ptr, ptr, ptr, i32) | ||
42 | |||
43 | DEF_HELPER_FLAGS_4(crypto_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
44 | DEF_HELPER_FLAGS_4(crypto_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
45 | diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/crypto_helper.c | ||
48 | +++ b/target/arm/crypto_helper.c | ||
49 | @@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE { | ||
50 | #define CR_ST_WORD(state, i) (state.words[i]) | ||
51 | #endif | ||
52 | |||
53 | +/* | ||
54 | + * The caller has not been converted to full gvec, and so only | ||
55 | + * modifies the low 16 bytes of the vector register. | ||
56 | + */ | ||
57 | +static void clear_tail_16(void *vd, uint32_t desc) | ||
58 | +{ | ||
59 | + int opr_sz = simd_oprsz(desc); | ||
60 | + int max_sz = simd_maxsz(desc); | ||
61 | + | ||
62 | + assert(opr_sz == 16); | ||
63 | + clear_tail(vd, opr_sz, max_sz); | ||
64 | +} | ||
65 | + | ||
66 | static void do_crypto_aese(uint64_t *rd, uint64_t *rn, | ||
67 | uint64_t *rm, bool decrypt) | ||
68 | { | ||
69 | @@ -XXX,XX +XXX,XX @@ static uint64_t s1_512(uint64_t x) | ||
70 | return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); | ||
71 | } | ||
72 | |||
73 | -void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm) | ||
74 | +void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm, uint32_t desc) | ||
75 | { | ||
76 | uint64_t *rd = vd; | ||
77 | uint64_t *rn = vn; | ||
78 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h)(void *vd, void *vn, void *vm) | ||
79 | |||
80 | rd[0] = d0; | ||
81 | rd[1] = d1; | ||
82 | + | ||
83 | + clear_tail_16(vd, desc); | ||
84 | } | ||
85 | |||
86 | -void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm) | ||
87 | +void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm, uint32_t desc) | ||
88 | { | ||
89 | uint64_t *rd = vd; | ||
90 | uint64_t *rn = vn; | ||
91 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512h2)(void *vd, void *vn, void *vm) | ||
92 | |||
93 | rd[0] = d0; | ||
94 | rd[1] = d1; | ||
95 | + | ||
96 | + clear_tail_16(vd, desc); | ||
97 | } | ||
98 | |||
99 | -void HELPER(crypto_sha512su0)(void *vd, void *vn) | ||
100 | +void HELPER(crypto_sha512su0)(void *vd, void *vn, uint32_t desc) | ||
101 | { | ||
102 | uint64_t *rd = vd; | ||
103 | uint64_t *rn = vn; | ||
104 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su0)(void *vd, void *vn) | ||
105 | |||
106 | rd[0] = d0; | ||
107 | rd[1] = d1; | ||
108 | + | ||
109 | + clear_tail_16(vd, desc); | ||
110 | } | ||
111 | |||
112 | -void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm) | ||
113 | +void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm, uint32_t desc) | ||
114 | { | ||
115 | uint64_t *rd = vd; | ||
116 | uint64_t *rn = vn; | ||
117 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm) | ||
118 | |||
119 | rd[0] += s1_512(rn[0]) + rm[0]; | ||
120 | rd[1] += s1_512(rn[1]) + rm[1]; | ||
121 | + | ||
122 | + clear_tail_16(vd, desc); | ||
123 | } | ||
124 | |||
125 | -void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm) | ||
126 | +void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm, uint32_t desc) | ||
127 | { | ||
128 | uint64_t *rd = vd; | ||
129 | uint64_t *rn = vn; | ||
130 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm) | ||
131 | |||
132 | rd[0] = d.l[0]; | ||
133 | rd[1] = d.l[1]; | ||
134 | + | ||
135 | + clear_tail_16(vd, desc); | ||
136 | } | ||
137 | |||
138 | -void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm) | ||
139 | +void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc) | ||
140 | { | ||
141 | uint64_t *rd = vd; | ||
142 | uint64_t *rn = vn; | ||
143 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm) | ||
144 | |||
145 | rd[0] = d.l[0]; | ||
146 | rd[1] = d.l[1]; | ||
147 | + | ||
148 | + clear_tail_16(vd, desc); | ||
149 | } | ||
150 | |||
151 | void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, | ||
152 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
153 | index XXXXXXX..XXXXXXX 100644 | ||
154 | --- a/target/arm/translate-a64.c | ||
155 | +++ b/target/arm/translate-a64.c | ||
156 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
157 | int rn = extract32(insn, 5, 5); | ||
158 | int rd = extract32(insn, 0, 5); | ||
159 | bool feature; | ||
160 | - CryptoThreeOpFn *genfn = NULL; | ||
161 | gen_helper_gvec_3 *oolfn = NULL; | ||
162 | GVecGen3Fn *gvecfn = NULL; | ||
163 | |||
164 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
165 | switch (opcode) { | ||
166 | case 0: /* SHA512H */ | ||
167 | feature = dc_isar_feature(aa64_sha512, s); | ||
168 | - genfn = gen_helper_crypto_sha512h; | ||
169 | + oolfn = gen_helper_crypto_sha512h; | ||
170 | break; | ||
171 | case 1: /* SHA512H2 */ | ||
172 | feature = dc_isar_feature(aa64_sha512, s); | ||
173 | - genfn = gen_helper_crypto_sha512h2; | ||
174 | + oolfn = gen_helper_crypto_sha512h2; | ||
175 | break; | ||
176 | case 2: /* SHA512SU1 */ | ||
177 | feature = dc_isar_feature(aa64_sha512, s); | ||
178 | - genfn = gen_helper_crypto_sha512su1; | ||
179 | + oolfn = gen_helper_crypto_sha512su1; | ||
180 | break; | ||
181 | case 3: /* RAX1 */ | ||
182 | feature = dc_isar_feature(aa64_sha3, s); | ||
183 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
184 | switch (opcode) { | ||
185 | case 0: /* SM3PARTW1 */ | ||
186 | feature = dc_isar_feature(aa64_sm3, s); | ||
187 | - genfn = gen_helper_crypto_sm3partw1; | ||
188 | + oolfn = gen_helper_crypto_sm3partw1; | ||
189 | break; | ||
190 | case 1: /* SM3PARTW2 */ | ||
191 | feature = dc_isar_feature(aa64_sm3, s); | ||
192 | - genfn = gen_helper_crypto_sm3partw2; | ||
193 | + oolfn = gen_helper_crypto_sm3partw2; | ||
194 | break; | ||
195 | case 2: /* SM4EKEY */ | ||
196 | feature = dc_isar_feature(aa64_sm4, s); | ||
197 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn) | ||
198 | |||
199 | if (oolfn) { | ||
200 | gen_gvec_op3_ool(s, true, rd, rn, rm, 0, oolfn); | ||
201 | - } else if (gvecfn) { | ||
202 | - gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); | ||
203 | } else { | ||
204 | - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; | ||
205 | - | ||
206 | - tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
207 | - tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
208 | - tcg_rm_ptr = vec_full_reg_ptr(s, rm); | ||
209 | - | ||
210 | - genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); | ||
211 | - | ||
212 | - tcg_temp_free_ptr(tcg_rd_ptr); | ||
213 | - tcg_temp_free_ptr(tcg_rn_ptr); | ||
214 | - tcg_temp_free_ptr(tcg_rm_ptr); | ||
215 | + gen_gvec_fn3(s, true, rd, rn, rm, gvecfn, MO_64); | ||
216 | } | ||
217 | } | ||
218 | |||
219 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | ||
220 | int opcode = extract32(insn, 10, 2); | ||
221 | int rn = extract32(insn, 5, 5); | ||
222 | int rd = extract32(insn, 0, 5); | ||
223 | - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; | ||
224 | bool feature; | ||
225 | - CryptoTwoOpFn *genfn; | ||
226 | - gen_helper_gvec_3 *oolfn = NULL; | ||
227 | |||
228 | switch (opcode) { | ||
229 | case 0: /* SHA512SU0 */ | ||
230 | feature = dc_isar_feature(aa64_sha512, s); | ||
231 | - genfn = gen_helper_crypto_sha512su0; | ||
232 | break; | ||
233 | case 1: /* SM4E */ | ||
234 | feature = dc_isar_feature(aa64_sm4, s); | ||
235 | - oolfn = gen_helper_crypto_sm4e; | ||
236 | break; | ||
237 | default: | ||
238 | unallocated_encoding(s); | ||
239 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn) | ||
240 | return; | ||
241 | } | ||
242 | |||
243 | - if (oolfn) { | ||
244 | - gen_gvec_op3_ool(s, true, rd, rd, rn, 0, oolfn); | ||
245 | - return; | ||
246 | + switch (opcode) { | ||
247 | + case 0: /* SHA512SU0 */ | ||
248 | + gen_gvec_op2_ool(s, true, rd, rn, 0, gen_helper_crypto_sha512su0); | ||
249 | + break; | ||
250 | + case 1: /* SM4E */ | ||
251 | + gen_gvec_op3_ool(s, true, rd, rd, rn, 0, gen_helper_crypto_sm4e); | ||
252 | + break; | ||
253 | + default: | ||
254 | + g_assert_not_reached(); | ||
255 | } | ||
256 | - | ||
257 | - tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
258 | - tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
259 | - | ||
260 | - genfn(tcg_rd_ptr, tcg_rn_ptr); | ||
261 | - | ||
262 | - tcg_temp_free_ptr(tcg_rd_ptr); | ||
263 | - tcg_temp_free_ptr(tcg_rn_ptr); | ||
264 | } | ||
265 | |||
266 | /* Crypto four-register | ||
30 | -- | 267 | -- |
31 | 2.18.0 | 268 | 2.20.1 |
32 | 269 | ||
33 | 270 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These insns require u=1; failed to include that in the switch | 3 | Do not yet convert the helpers to loop over opr_sz, but the |
4 | cases. This probably happened during one of the rebases just | 4 | descriptor allows the vector tail to be cleared. Which fixes |
5 | before final commit. | 5 | an existing bug vs SVE. |
6 | 6 | ||
7 | Fixes: d17b7cdcf4e | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 8 | Message-id: 20200514212831.31248-5-richard.henderson@linaro.org |
10 | Message-id: 20180810193129.1556-6-richard.henderson@linaro.org | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | target/arm/translate-a64.c | 12 ++++++------ | 12 | target/arm/helper.h | 12 ++-- |
14 | 1 file changed, 6 insertions(+), 6 deletions(-) | 13 | target/arm/neon-dp.decode | 12 ++-- |
14 | target/arm/crypto_helper.c | 24 +++++-- | ||
15 | target/arm/translate-a64.c | 34 ++++----- | ||
16 | target/arm/translate-neon.inc.c | 124 +++++--------------------------- | ||
17 | target/arm/translate.c | 24 ++----- | ||
18 | 6 files changed, 67 insertions(+), 163 deletions(-) | ||
15 | 19 | ||
20 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/target/arm/helper.h | ||
23 | +++ b/target/arm/helper.h | ||
24 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
25 | DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
26 | |||
27 | DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
28 | -DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
29 | -DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
30 | +DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
32 | |||
33 | -DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
34 | -DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
35 | -DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
36 | -DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) | ||
37 | +DEF_HELPER_FLAGS_4(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
38 | +DEF_HELPER_FLAGS_4(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_3(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
40 | +DEF_HELPER_FLAGS_4(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
41 | |||
42 | DEF_HELPER_FLAGS_4(crypto_sha512h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
43 | DEF_HELPER_FLAGS_4(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
44 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/neon-dp.decode | ||
47 | +++ b/target/arm/neon-dp.decode | ||
48 | @@ -XXX,XX +XXX,XX @@ VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0 | ||
49 | |||
50 | VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same | ||
51 | |||
52 | +@3same_crypto .... .... .... .... .... .... .... .... \ | ||
53 | + &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1 | ||
54 | + | ||
55 | SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \ | ||
56 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
57 | -SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \ | ||
58 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
59 | -SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \ | ||
60 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
61 | -SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \ | ||
62 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
63 | +SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
64 | +SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
65 | +SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
66 | |||
67 | VFMA_fp_3s 1111 001 0 0 . 0 . .... .... 1100 ... 1 .... @3same_fp | ||
68 | VFMS_fp_3s 1111 001 0 0 . 1 . .... .... 1100 ... 1 .... @3same_fp | ||
69 | diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/crypto_helper.c | ||
72 | +++ b/target/arm/crypto_helper.c | ||
73 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op) | ||
74 | rd[1] = d.l[1]; | ||
75 | } | ||
76 | |||
77 | -void HELPER(crypto_sha1h)(void *vd, void *vm) | ||
78 | +void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc) | ||
79 | { | ||
80 | uint64_t *rd = vd; | ||
81 | uint64_t *rm = vm; | ||
82 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1h)(void *vd, void *vm) | ||
83 | |||
84 | rd[0] = m.l[0]; | ||
85 | rd[1] = m.l[1]; | ||
86 | + | ||
87 | + clear_tail_16(vd, desc); | ||
88 | } | ||
89 | |||
90 | -void HELPER(crypto_sha1su1)(void *vd, void *vm) | ||
91 | +void HELPER(crypto_sha1su1)(void *vd, void *vm, uint32_t desc) | ||
92 | { | ||
93 | uint64_t *rd = vd; | ||
94 | uint64_t *rm = vm; | ||
95 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha1su1)(void *vd, void *vm) | ||
96 | |||
97 | rd[0] = d.l[0]; | ||
98 | rd[1] = d.l[1]; | ||
99 | + | ||
100 | + clear_tail_16(vd, desc); | ||
101 | } | ||
102 | |||
103 | /* | ||
104 | @@ -XXX,XX +XXX,XX @@ static uint32_t s1(uint32_t x) | ||
105 | return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); | ||
106 | } | ||
107 | |||
108 | -void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm) | ||
109 | +void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm, uint32_t desc) | ||
110 | { | ||
111 | uint64_t *rd = vd; | ||
112 | uint64_t *rn = vn; | ||
113 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm) | ||
114 | |||
115 | rd[0] = d.l[0]; | ||
116 | rd[1] = d.l[1]; | ||
117 | + | ||
118 | + clear_tail_16(vd, desc); | ||
119 | } | ||
120 | |||
121 | -void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm) | ||
122 | +void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm, uint32_t desc) | ||
123 | { | ||
124 | uint64_t *rd = vd; | ||
125 | uint64_t *rn = vn; | ||
126 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm) | ||
127 | |||
128 | rd[0] = d.l[0]; | ||
129 | rd[1] = d.l[1]; | ||
130 | + | ||
131 | + clear_tail_16(vd, desc); | ||
132 | } | ||
133 | |||
134 | -void HELPER(crypto_sha256su0)(void *vd, void *vm) | ||
135 | +void HELPER(crypto_sha256su0)(void *vd, void *vm, uint32_t desc) | ||
136 | { | ||
137 | uint64_t *rd = vd; | ||
138 | uint64_t *rm = vm; | ||
139 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su0)(void *vd, void *vm) | ||
140 | |||
141 | rd[0] = d.l[0]; | ||
142 | rd[1] = d.l[1]; | ||
143 | + | ||
144 | + clear_tail_16(vd, desc); | ||
145 | } | ||
146 | |||
147 | -void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm) | ||
148 | +void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm, uint32_t desc) | ||
149 | { | ||
150 | uint64_t *rd = vd; | ||
151 | uint64_t *rn = vn; | ||
152 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm) | ||
153 | |||
154 | rd[0] = d.l[0]; | ||
155 | rd[1] = d.l[1]; | ||
156 | + | ||
157 | + clear_tail_16(vd, desc); | ||
158 | } | ||
159 | |||
160 | /* | ||
16 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 161 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
17 | index XXXXXXX..XXXXXXX 100644 | 162 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate-a64.c | 163 | --- a/target/arm/translate-a64.c |
19 | +++ b/target/arm/translate-a64.c | 164 | +++ b/target/arm/translate-a64.c |
20 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) | 165 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) |
21 | } | 166 | int rm = extract32(insn, 16, 5); |
22 | feature = ARM_FEATURE_V8_DOTPROD; | 167 | int rn = extract32(insn, 5, 5); |
23 | break; | 168 | int rd = extract32(insn, 0, 5); |
24 | - case 0x8: /* FCMLA, #0 */ | 169 | - CryptoThreeOpFn *genfn; |
25 | - case 0x9: /* FCMLA, #90 */ | 170 | - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; |
26 | - case 0xa: /* FCMLA, #180 */ | 171 | + gen_helper_gvec_3 *genfn; |
27 | - case 0xb: /* FCMLA, #270 */ | 172 | bool feature; |
28 | - case 0xc: /* FCADD, #90 */ | 173 | |
29 | - case 0xe: /* FCADD, #270 */ | 174 | if (size != 0) { |
30 | + case 0x18: /* FCMLA, #0 */ | 175 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) |
31 | + case 0x19: /* FCMLA, #90 */ | 176 | return; |
32 | + case 0x1a: /* FCMLA, #180 */ | 177 | } |
33 | + case 0x1b: /* FCMLA, #270 */ | 178 | |
34 | + case 0x1c: /* FCADD, #90 */ | 179 | - tcg_rd_ptr = vec_full_reg_ptr(s, rd); |
35 | + case 0x1e: /* FCADD, #270 */ | 180 | - tcg_rn_ptr = vec_full_reg_ptr(s, rn); |
36 | if (size == 0 | 181 | - tcg_rm_ptr = vec_full_reg_ptr(s, rm); |
37 | || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) | 182 | - |
38 | || (size == 3 && !is_q)) { | 183 | if (genfn) { |
184 | - genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); | ||
185 | + gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); | ||
186 | } else { | ||
187 | TCGv_i32 tcg_opcode = tcg_const_i32(opcode); | ||
188 | + TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
189 | + TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
190 | + TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm); | ||
191 | |||
192 | gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr, | ||
193 | tcg_rm_ptr, tcg_opcode); | ||
194 | - tcg_temp_free_i32(tcg_opcode); | ||
195 | - } | ||
196 | |||
197 | - tcg_temp_free_ptr(tcg_rd_ptr); | ||
198 | - tcg_temp_free_ptr(tcg_rn_ptr); | ||
199 | - tcg_temp_free_ptr(tcg_rm_ptr); | ||
200 | + tcg_temp_free_i32(tcg_opcode); | ||
201 | + tcg_temp_free_ptr(tcg_rd_ptr); | ||
202 | + tcg_temp_free_ptr(tcg_rn_ptr); | ||
203 | + tcg_temp_free_ptr(tcg_rm_ptr); | ||
204 | + } | ||
205 | } | ||
206 | |||
207 | /* Crypto two-reg SHA | ||
208 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | ||
209 | int opcode = extract32(insn, 12, 5); | ||
210 | int rn = extract32(insn, 5, 5); | ||
211 | int rd = extract32(insn, 0, 5); | ||
212 | - CryptoTwoOpFn *genfn; | ||
213 | + gen_helper_gvec_2 *genfn; | ||
214 | bool feature; | ||
215 | - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; | ||
216 | |||
217 | if (size != 0) { | ||
218 | unallocated_encoding(s); | ||
219 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) | ||
220 | if (!fp_access_check(s)) { | ||
221 | return; | ||
222 | } | ||
223 | - | ||
224 | - tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
225 | - tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
226 | - | ||
227 | - genfn(tcg_rd_ptr, tcg_rn_ptr); | ||
228 | - | ||
229 | - tcg_temp_free_ptr(tcg_rd_ptr); | ||
230 | - tcg_temp_free_ptr(tcg_rn_ptr); | ||
231 | + gen_gvec_op2_ool(s, true, rd, rn, 0, genfn); | ||
232 | } | ||
233 | |||
234 | static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) | ||
235 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
236 | index XXXXXXX..XXXXXXX 100644 | ||
237 | --- a/target/arm/translate-neon.inc.c | ||
238 | +++ b/target/arm/translate-neon.inc.c | ||
239 | @@ -XXX,XX +XXX,XX @@ DO_3SAME_CMP(VCGE_S, TCG_COND_GE) | ||
240 | DO_3SAME_CMP(VCGE_U, TCG_COND_GEU) | ||
241 | DO_3SAME_CMP(VCEQ, TCG_COND_EQ) | ||
242 | |||
243 | -static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | ||
244 | - uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) | ||
245 | -{ | ||
246 | - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, | ||
247 | - 0, gen_helper_gvec_pmul_b); | ||
248 | -} | ||
249 | +#define WRAP_OOL_FN(WRAPNAME, FUNC) \ | ||
250 | + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, \ | ||
251 | + uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \ | ||
252 | + { \ | ||
253 | + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \ | ||
254 | + } | ||
255 | + | ||
256 | +WRAP_OOL_FN(gen_VMUL_p_3s, gen_helper_gvec_pmul_b) | ||
257 | |||
258 | static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) | ||
259 | { | ||
260 | @@ -XXX,XX +XXX,XX @@ static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a) | ||
261 | return true; | ||
262 | } | ||
263 | |||
264 | -static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a) | ||
265 | -{ | ||
266 | - TCGv_ptr ptr1, ptr2, ptr3; | ||
267 | - | ||
268 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
269 | - !dc_isar_feature(aa32_sha2, s)) { | ||
270 | - return false; | ||
271 | +#define DO_SHA2(NAME, FUNC) \ | ||
272 | + WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ | ||
273 | + static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ | ||
274 | + { \ | ||
275 | + if (!dc_isar_feature(aa32_sha2, s)) { \ | ||
276 | + return false; \ | ||
277 | + } \ | ||
278 | + return do_3same(s, a, gen_##NAME##_3s); \ | ||
279 | } | ||
280 | |||
281 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
282 | - if (!dc_isar_feature(aa32_simd_r32, s) && | ||
283 | - ((a->vd | a->vn | a->vm) & 0x10)) { | ||
284 | - return false; | ||
285 | - } | ||
286 | - | ||
287 | - if ((a->vn | a->vm | a->vd) & 1) { | ||
288 | - return false; | ||
289 | - } | ||
290 | - | ||
291 | - if (!vfp_access_check(s)) { | ||
292 | - return true; | ||
293 | - } | ||
294 | - | ||
295 | - ptr1 = vfp_reg_ptr(true, a->vd); | ||
296 | - ptr2 = vfp_reg_ptr(true, a->vn); | ||
297 | - ptr3 = vfp_reg_ptr(true, a->vm); | ||
298 | - gen_helper_crypto_sha256h(ptr1, ptr2, ptr3); | ||
299 | - tcg_temp_free_ptr(ptr1); | ||
300 | - tcg_temp_free_ptr(ptr2); | ||
301 | - tcg_temp_free_ptr(ptr3); | ||
302 | - | ||
303 | - return true; | ||
304 | -} | ||
305 | - | ||
306 | -static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a) | ||
307 | -{ | ||
308 | - TCGv_ptr ptr1, ptr2, ptr3; | ||
309 | - | ||
310 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
311 | - !dc_isar_feature(aa32_sha2, s)) { | ||
312 | - return false; | ||
313 | - } | ||
314 | - | ||
315 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
316 | - if (!dc_isar_feature(aa32_simd_r32, s) && | ||
317 | - ((a->vd | a->vn | a->vm) & 0x10)) { | ||
318 | - return false; | ||
319 | - } | ||
320 | - | ||
321 | - if ((a->vn | a->vm | a->vd) & 1) { | ||
322 | - return false; | ||
323 | - } | ||
324 | - | ||
325 | - if (!vfp_access_check(s)) { | ||
326 | - return true; | ||
327 | - } | ||
328 | - | ||
329 | - ptr1 = vfp_reg_ptr(true, a->vd); | ||
330 | - ptr2 = vfp_reg_ptr(true, a->vn); | ||
331 | - ptr3 = vfp_reg_ptr(true, a->vm); | ||
332 | - gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3); | ||
333 | - tcg_temp_free_ptr(ptr1); | ||
334 | - tcg_temp_free_ptr(ptr2); | ||
335 | - tcg_temp_free_ptr(ptr3); | ||
336 | - | ||
337 | - return true; | ||
338 | -} | ||
339 | - | ||
340 | -static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a) | ||
341 | -{ | ||
342 | - TCGv_ptr ptr1, ptr2, ptr3; | ||
343 | - | ||
344 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
345 | - !dc_isar_feature(aa32_sha2, s)) { | ||
346 | - return false; | ||
347 | - } | ||
348 | - | ||
349 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
350 | - if (!dc_isar_feature(aa32_simd_r32, s) && | ||
351 | - ((a->vd | a->vn | a->vm) & 0x10)) { | ||
352 | - return false; | ||
353 | - } | ||
354 | - | ||
355 | - if ((a->vn | a->vm | a->vd) & 1) { | ||
356 | - return false; | ||
357 | - } | ||
358 | - | ||
359 | - if (!vfp_access_check(s)) { | ||
360 | - return true; | ||
361 | - } | ||
362 | - | ||
363 | - ptr1 = vfp_reg_ptr(true, a->vd); | ||
364 | - ptr2 = vfp_reg_ptr(true, a->vn); | ||
365 | - ptr3 = vfp_reg_ptr(true, a->vm); | ||
366 | - gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3); | ||
367 | - tcg_temp_free_ptr(ptr1); | ||
368 | - tcg_temp_free_ptr(ptr2); | ||
369 | - tcg_temp_free_ptr(ptr3); | ||
370 | - | ||
371 | - return true; | ||
372 | -} | ||
373 | +DO_SHA2(SHA256H, gen_helper_crypto_sha256h) | ||
374 | +DO_SHA2(SHA256H2, gen_helper_crypto_sha256h2) | ||
375 | +DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1) | ||
376 | |||
377 | #define DO_3SAME_64(INSN, FUNC) \ | ||
378 | static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | ||
379 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
380 | index XXXXXXX..XXXXXXX 100644 | ||
381 | --- a/target/arm/translate.c | ||
382 | +++ b/target/arm/translate.c | ||
383 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
384 | int vec_size; | ||
385 | uint32_t imm; | ||
386 | TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; | ||
387 | - TCGv_ptr ptr1, ptr2; | ||
388 | + TCGv_ptr ptr1; | ||
389 | TCGv_i64 tmp64; | ||
390 | |||
391 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
392 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
393 | if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) { | ||
394 | return 1; | ||
395 | } | ||
396 | - ptr1 = vfp_reg_ptr(true, rd); | ||
397 | - ptr2 = vfp_reg_ptr(true, rm); | ||
398 | - | ||
399 | - gen_helper_crypto_sha1h(ptr1, ptr2); | ||
400 | - | ||
401 | - tcg_temp_free_ptr(ptr1); | ||
402 | - tcg_temp_free_ptr(ptr2); | ||
403 | + tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0, | ||
404 | + gen_helper_crypto_sha1h); | ||
405 | break; | ||
406 | case NEON_2RM_SHA1SU1: | ||
407 | if ((rm | rd) & 1) { | ||
408 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
409 | } else if (!dc_isar_feature(aa32_sha1, s)) { | ||
410 | return 1; | ||
411 | } | ||
412 | - ptr1 = vfp_reg_ptr(true, rd); | ||
413 | - ptr2 = vfp_reg_ptr(true, rm); | ||
414 | - if (q) { | ||
415 | - gen_helper_crypto_sha256su0(ptr1, ptr2); | ||
416 | - } else { | ||
417 | - gen_helper_crypto_sha1su1(ptr1, ptr2); | ||
418 | - } | ||
419 | - tcg_temp_free_ptr(ptr1); | ||
420 | - tcg_temp_free_ptr(ptr2); | ||
421 | + tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0, | ||
422 | + q ? gen_helper_crypto_sha256su0 | ||
423 | + : gen_helper_crypto_sha1su1); | ||
424 | break; | ||
425 | - | ||
426 | case NEON_2RM_VMVN: | ||
427 | tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size); | ||
428 | break; | ||
39 | -- | 429 | -- |
40 | 2.18.0 | 430 | 2.20.1 |
41 | 431 | ||
42 | 432 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We were using the wrong flush-to-zero bit for the non-half input. | 3 | Rather than passing an opcode to a helper, fully decode the |
4 | 4 | operation at translate time. Use clear_tail_16 to zap the | |
5 | Fixes: 46d33d1e3c9 | 5 | balance of the SVE register with the AdvSIMD write. |
6 | Cc: qemu-stable@nongnu.org (3.0.1) | 6 | |
7 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 8 | Message-id: 20200514212831.31248-6-richard.henderson@linaro.org |
10 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20180810193129.1556-5-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 11 | --- |
14 | target/arm/translate-sve.c | 4 ++-- | 12 | target/arm/helper.h | 5 +- |
15 | 1 file changed, 2 insertions(+), 2 deletions(-) | 13 | target/arm/neon-dp.decode | 6 +- |
16 | 14 | target/arm/crypto_helper.c | 99 +++++++++++++++++++++------------ | |
17 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 15 | target/arm/translate-a64.c | 29 ++++------ |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | target/arm/translate-neon.inc.c | 46 ++++----------- |
19 | --- a/target/arm/translate-sve.c | 17 | 5 files changed, 93 insertions(+), 92 deletions(-) |
20 | +++ b/target/arm/translate-sve.c | 18 | |
21 | @@ -XXX,XX +XXX,XX @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, | 19 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
22 | 20 | index XXXXXXX..XXXXXXX 100644 | |
23 | static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 21 | --- a/target/arm/helper.h |
22 | +++ b/target/arm/helper.h | ||
23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) | ||
24 | DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
25 | DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
26 | |||
27 | -DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(crypto_sha1su0, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_4(crypto_sha1c, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_4(crypto_sha1p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(crypto_sha1m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
32 | DEF_HELPER_FLAGS_3(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
33 | DEF_HELPER_FLAGS_3(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
34 | |||
35 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/neon-dp.decode | ||
38 | +++ b/target/arm/neon-dp.decode | ||
39 | @@ -XXX,XX +XXX,XX @@ VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same | ||
40 | @3same_crypto .... .... .... .... .... .... .... .... \ | ||
41 | &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 q=1 | ||
42 | |||
43 | -SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \ | ||
44 | - vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
45 | +SHA1C_3s 1111 001 0 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
46 | +SHA1P_3s 1111 001 0 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
47 | +SHA1M_3s 1111 001 0 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
48 | +SHA1SU0_3s 1111 001 0 0 . 11 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
49 | SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
50 | SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
51 | SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... @3same_crypto | ||
52 | diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/crypto_helper.c | ||
55 | +++ b/target/arm/crypto_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ union CRYPTO_STATE { | ||
57 | }; | ||
58 | |||
59 | #ifdef HOST_WORDS_BIGENDIAN | ||
60 | -#define CR_ST_BYTE(state, i) (state.bytes[(15 - (i)) ^ 8]) | ||
61 | -#define CR_ST_WORD(state, i) (state.words[(3 - (i)) ^ 2]) | ||
62 | +#define CR_ST_BYTE(state, i) ((state).bytes[(15 - (i)) ^ 8]) | ||
63 | +#define CR_ST_WORD(state, i) ((state).words[(3 - (i)) ^ 2]) | ||
64 | #else | ||
65 | -#define CR_ST_BYTE(state, i) (state.bytes[i]) | ||
66 | -#define CR_ST_WORD(state, i) (state.words[i]) | ||
67 | +#define CR_ST_BYTE(state, i) ((state).bytes[i]) | ||
68 | +#define CR_ST_WORD(state, i) ((state).words[i]) | ||
69 | #endif | ||
70 | |||
71 | /* | ||
72 | @@ -XXX,XX +XXX,XX @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z) | ||
73 | return (x & y) | ((x | y) & z); | ||
74 | } | ||
75 | |||
76 | -void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op) | ||
77 | +void HELPER(crypto_sha1su0)(void *vd, void *vn, void *vm, uint32_t desc) | ||
78 | +{ | ||
79 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
80 | + uint64_t d0, d1; | ||
81 | + | ||
82 | + d0 = d[1] ^ d[0] ^ m[0]; | ||
83 | + d1 = n[0] ^ d[1] ^ m[1]; | ||
84 | + d[0] = d0; | ||
85 | + d[1] = d1; | ||
86 | + | ||
87 | + clear_tail_16(vd, desc); | ||
88 | +} | ||
89 | + | ||
90 | +static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn, | ||
91 | + uint64_t *rm, uint32_t desc, | ||
92 | + uint32_t (*fn)(union CRYPTO_STATE *d)) | ||
24 | { | 93 | { |
25 | - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh); | 94 | - uint64_t *rd = vd; |
26 | + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); | 95 | - uint64_t *rn = vn; |
96 | - uint64_t *rm = vm; | ||
97 | union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; | ||
98 | union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; | ||
99 | union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; | ||
100 | + int i; | ||
101 | |||
102 | - if (op == 3) { /* sha1su0 */ | ||
103 | - d.l[0] ^= d.l[1] ^ m.l[0]; | ||
104 | - d.l[1] ^= n.l[0] ^ m.l[1]; | ||
105 | - } else { | ||
106 | - int i; | ||
107 | + for (i = 0; i < 4; i++) { | ||
108 | + uint32_t t = fn(&d); | ||
109 | |||
110 | - for (i = 0; i < 4; i++) { | ||
111 | - uint32_t t; | ||
112 | + t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0) | ||
113 | + + CR_ST_WORD(m, i); | ||
114 | |||
115 | - switch (op) { | ||
116 | - case 0: /* sha1c */ | ||
117 | - t = cho(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3)); | ||
118 | - break; | ||
119 | - case 1: /* sha1p */ | ||
120 | - t = par(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3)); | ||
121 | - break; | ||
122 | - case 2: /* sha1m */ | ||
123 | - t = maj(CR_ST_WORD(d, 1), CR_ST_WORD(d, 2), CR_ST_WORD(d, 3)); | ||
124 | - break; | ||
125 | - default: | ||
126 | - g_assert_not_reached(); | ||
127 | - } | ||
128 | - t += rol32(CR_ST_WORD(d, 0), 5) + CR_ST_WORD(n, 0) | ||
129 | - + CR_ST_WORD(m, i); | ||
130 | - | ||
131 | - CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3); | ||
132 | - CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2); | ||
133 | - CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2); | ||
134 | - CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0); | ||
135 | - CR_ST_WORD(d, 0) = t; | ||
136 | - } | ||
137 | + CR_ST_WORD(n, 0) = CR_ST_WORD(d, 3); | ||
138 | + CR_ST_WORD(d, 3) = CR_ST_WORD(d, 2); | ||
139 | + CR_ST_WORD(d, 2) = ror32(CR_ST_WORD(d, 1), 2); | ||
140 | + CR_ST_WORD(d, 1) = CR_ST_WORD(d, 0); | ||
141 | + CR_ST_WORD(d, 0) = t; | ||
142 | } | ||
143 | rd[0] = d.l[0]; | ||
144 | rd[1] = d.l[1]; | ||
145 | + | ||
146 | + clear_tail_16(rd, desc); | ||
147 | +} | ||
148 | + | ||
149 | +static uint32_t do_sha1c(union CRYPTO_STATE *d) | ||
150 | +{ | ||
151 | + return cho(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3)); | ||
152 | +} | ||
153 | + | ||
154 | +void HELPER(crypto_sha1c)(void *vd, void *vn, void *vm, uint32_t desc) | ||
155 | +{ | ||
156 | + crypto_sha1_3reg(vd, vn, vm, desc, do_sha1c); | ||
157 | +} | ||
158 | + | ||
159 | +static uint32_t do_sha1p(union CRYPTO_STATE *d) | ||
160 | +{ | ||
161 | + return par(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3)); | ||
162 | +} | ||
163 | + | ||
164 | +void HELPER(crypto_sha1p)(void *vd, void *vn, void *vm, uint32_t desc) | ||
165 | +{ | ||
166 | + crypto_sha1_3reg(vd, vn, vm, desc, do_sha1p); | ||
167 | +} | ||
168 | + | ||
169 | +static uint32_t do_sha1m(union CRYPTO_STATE *d) | ||
170 | +{ | ||
171 | + return maj(CR_ST_WORD(*d, 1), CR_ST_WORD(*d, 2), CR_ST_WORD(*d, 3)); | ||
172 | +} | ||
173 | + | ||
174 | +void HELPER(crypto_sha1m)(void *vd, void *vn, void *vm, uint32_t desc) | ||
175 | +{ | ||
176 | + crypto_sha1_3reg(vd, vn, vm, desc, do_sha1m); | ||
27 | } | 177 | } |
28 | 178 | ||
29 | static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 179 | void HELPER(crypto_sha1h)(void *vd, void *vm, uint32_t desc) |
30 | @@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 180 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
31 | 181 | index XXXXXXX..XXXXXXX 100644 | |
32 | static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 182 | --- a/target/arm/translate-a64.c |
33 | { | 183 | +++ b/target/arm/translate-a64.c |
34 | - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh); | 184 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) |
35 | + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); | 185 | |
186 | switch (opcode) { | ||
187 | case 0: /* SHA1C */ | ||
188 | + genfn = gen_helper_crypto_sha1c; | ||
189 | + feature = dc_isar_feature(aa64_sha1, s); | ||
190 | + break; | ||
191 | case 1: /* SHA1P */ | ||
192 | + genfn = gen_helper_crypto_sha1p; | ||
193 | + feature = dc_isar_feature(aa64_sha1, s); | ||
194 | + break; | ||
195 | case 2: /* SHA1M */ | ||
196 | + genfn = gen_helper_crypto_sha1m; | ||
197 | + feature = dc_isar_feature(aa64_sha1, s); | ||
198 | + break; | ||
199 | case 3: /* SHA1SU0 */ | ||
200 | - genfn = NULL; | ||
201 | + genfn = gen_helper_crypto_sha1su0; | ||
202 | feature = dc_isar_feature(aa64_sha1, s); | ||
203 | break; | ||
204 | case 4: /* SHA256H */ | ||
205 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) | ||
206 | if (!fp_access_check(s)) { | ||
207 | return; | ||
208 | } | ||
209 | - | ||
210 | - if (genfn) { | ||
211 | - gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); | ||
212 | - } else { | ||
213 | - TCGv_i32 tcg_opcode = tcg_const_i32(opcode); | ||
214 | - TCGv_ptr tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
215 | - TCGv_ptr tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
216 | - TCGv_ptr tcg_rm_ptr = vec_full_reg_ptr(s, rm); | ||
217 | - | ||
218 | - gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr, | ||
219 | - tcg_rm_ptr, tcg_opcode); | ||
220 | - | ||
221 | - tcg_temp_free_i32(tcg_opcode); | ||
222 | - tcg_temp_free_ptr(tcg_rd_ptr); | ||
223 | - tcg_temp_free_ptr(tcg_rn_ptr); | ||
224 | - tcg_temp_free_ptr(tcg_rm_ptr); | ||
225 | - } | ||
226 | + gen_gvec_op3_ool(s, true, rd, rn, rm, 0, genfn); | ||
36 | } | 227 | } |
37 | 228 | ||
38 | static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 229 | /* Crypto two-reg SHA |
230 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
231 | index XXXXXXX..XXXXXXX 100644 | ||
232 | --- a/target/arm/translate-neon.inc.c | ||
233 | +++ b/target/arm/translate-neon.inc.c | ||
234 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) | ||
235 | DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc) | ||
236 | DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc) | ||
237 | |||
238 | -static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a) | ||
239 | -{ | ||
240 | - TCGv_ptr ptr1, ptr2, ptr3; | ||
241 | - TCGv_i32 tmp; | ||
242 | - | ||
243 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
244 | - !dc_isar_feature(aa32_sha1, s)) { | ||
245 | - return false; | ||
246 | +#define DO_SHA1(NAME, FUNC) \ | ||
247 | + WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ | ||
248 | + static bool trans_##NAME##_3s(DisasContext *s, arg_3same *a) \ | ||
249 | + { \ | ||
250 | + if (!dc_isar_feature(aa32_sha1, s)) { \ | ||
251 | + return false; \ | ||
252 | + } \ | ||
253 | + return do_3same(s, a, gen_##NAME##_3s); \ | ||
254 | } | ||
255 | |||
256 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
257 | - if (!dc_isar_feature(aa32_simd_r32, s) && | ||
258 | - ((a->vd | a->vn | a->vm) & 0x10)) { | ||
259 | - return false; | ||
260 | - } | ||
261 | - | ||
262 | - if ((a->vn | a->vm | a->vd) & 1) { | ||
263 | - return false; | ||
264 | - } | ||
265 | - | ||
266 | - if (!vfp_access_check(s)) { | ||
267 | - return true; | ||
268 | - } | ||
269 | - | ||
270 | - ptr1 = vfp_reg_ptr(true, a->vd); | ||
271 | - ptr2 = vfp_reg_ptr(true, a->vn); | ||
272 | - ptr3 = vfp_reg_ptr(true, a->vm); | ||
273 | - tmp = tcg_const_i32(a->optype); | ||
274 | - gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp); | ||
275 | - tcg_temp_free_i32(tmp); | ||
276 | - tcg_temp_free_ptr(ptr1); | ||
277 | - tcg_temp_free_ptr(ptr2); | ||
278 | - tcg_temp_free_ptr(ptr3); | ||
279 | - | ||
280 | - return true; | ||
281 | -} | ||
282 | +DO_SHA1(SHA1C, gen_helper_crypto_sha1c) | ||
283 | +DO_SHA1(SHA1P, gen_helper_crypto_sha1p) | ||
284 | +DO_SHA1(SHA1M, gen_helper_crypto_sha1m) | ||
285 | +DO_SHA1(SHA1SU0, gen_helper_crypto_sha1su0) | ||
286 | |||
287 | #define DO_SHA2(NAME, FUNC) \ | ||
288 | WRAP_OOL_FN(gen_##NAME##_3s, FUNC) \ | ||
39 | -- | 289 | -- |
40 | 2.18.0 | 290 | 2.20.1 |
41 | 291 | ||
42 | 292 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | With PC, there are 33 registers. Three per line lines up nicely | 3 | Rather than passing an opcode to a helper, fully decode the |
4 | without overflowing 80 columns. | 4 | operation at translate time. Use clear_tail_16 to zap the |
5 | balance of the SVE register with the AdvSIMD write. | ||
5 | 6 | ||
6 | Cc: qemu-stable@nongnu.org (3.0.1) | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 8 | Message-id: 20200514212831.31248-7-richard.henderson@linaro.org |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 11 | --- |
11 | target/arm/translate-a64.c | 13 ++++++------- | 12 | target/arm/helper.h | 5 ++++- |
12 | 1 file changed, 6 insertions(+), 7 deletions(-) | 13 | target/arm/crypto_helper.c | 24 ++++++++++++++++++------ |
14 | target/arm/translate-a64.c | 21 +++++---------------- | ||
15 | 3 files changed, 27 insertions(+), 23 deletions(-) | ||
13 | 16 | ||
17 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/helper.h | ||
20 | +++ b/target/arm/helper.h | ||
21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_4(crypto_sha512su1, TCG_CALL_NO_RWG, | ||
23 | void, ptr, ptr, ptr, i32) | ||
24 | |||
25 | -DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32) | ||
26 | +DEF_HELPER_FLAGS_4(crypto_sm3tt1a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(crypto_sm3tt1b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(crypto_sm3tt2a, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_4(crypto_sm3tt2b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
30 | DEF_HELPER_FLAGS_4(crypto_sm3partw1, TCG_CALL_NO_RWG, | ||
31 | void, ptr, ptr, ptr, i32) | ||
32 | DEF_HELPER_FLAGS_4(crypto_sm3partw2, TCG_CALL_NO_RWG, | ||
33 | diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/crypto_helper.c | ||
36 | +++ b/target/arm/crypto_helper.c | ||
37 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm, uint32_t desc) | ||
38 | clear_tail_16(vd, desc); | ||
39 | } | ||
40 | |||
41 | -void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, | ||
42 | - uint32_t opcode) | ||
43 | +static inline void QEMU_ALWAYS_INLINE | ||
44 | +crypto_sm3tt(uint64_t *rd, uint64_t *rn, uint64_t *rm, | ||
45 | + uint32_t desc, uint32_t opcode) | ||
46 | { | ||
47 | - uint64_t *rd = vd; | ||
48 | - uint64_t *rn = vn; | ||
49 | - uint64_t *rm = vm; | ||
50 | union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; | ||
51 | union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; | ||
52 | union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; | ||
53 | + uint32_t imm2 = simd_data(desc); | ||
54 | uint32_t t; | ||
55 | |||
56 | assert(imm2 < 4); | ||
57 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, | ||
58 | /* SM3TT2B */ | ||
59 | t = cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1)); | ||
60 | } else { | ||
61 | - g_assert_not_reached(); | ||
62 | + qemu_build_not_reached(); | ||
63 | } | ||
64 | |||
65 | t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2); | ||
66 | @@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2, | ||
67 | |||
68 | rd[0] = d.l[0]; | ||
69 | rd[1] = d.l[1]; | ||
70 | + | ||
71 | + clear_tail_16(rd, desc); | ||
72 | } | ||
73 | |||
74 | +#define DO_SM3TT(NAME, OPCODE) \ | ||
75 | + void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ | ||
76 | + { crypto_sm3tt(vd, vn, vm, desc, OPCODE); } | ||
77 | + | ||
78 | +DO_SM3TT(crypto_sm3tt1a, 0) | ||
79 | +DO_SM3TT(crypto_sm3tt1b, 1) | ||
80 | +DO_SM3TT(crypto_sm3tt2a, 2) | ||
81 | +DO_SM3TT(crypto_sm3tt2b, 3) | ||
82 | + | ||
83 | +#undef DO_SM3TT | ||
84 | + | ||
85 | static uint8_t const sm4_sbox[] = { | ||
86 | 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7, | ||
87 | 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05, | ||
14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 88 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
15 | index XXXXXXX..XXXXXXX 100644 | 89 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate-a64.c | 90 | --- a/target/arm/translate-a64.c |
17 | +++ b/target/arm/translate-a64.c | 91 | +++ b/target/arm/translate-a64.c |
18 | @@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | 92 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn) |
19 | int el = arm_current_el(env); | 93 | */ |
20 | const char *ns_status; | 94 | static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) |
21 | 95 | { | |
22 | - cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", | 96 | + static gen_helper_gvec_3 * const fns[4] = { |
23 | - env->pc, env->xregs[31]); | 97 | + gen_helper_crypto_sm3tt1a, gen_helper_crypto_sm3tt1b, |
24 | - for (i = 0; i < 31; i++) { | 98 | + gen_helper_crypto_sm3tt2a, gen_helper_crypto_sm3tt2b, |
25 | - cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); | 99 | + }; |
26 | - if ((i % 4) == 3) { | 100 | int opcode = extract32(insn, 10, 2); |
27 | - cpu_fprintf(f, "\n"); | 101 | int imm2 = extract32(insn, 12, 2); |
28 | + cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc); | 102 | int rm = extract32(insn, 16, 5); |
29 | + for (i = 0; i < 32; i++) { | 103 | int rn = extract32(insn, 5, 5); |
30 | + if (i == 31) { | 104 | int rd = extract32(insn, 0, 5); |
31 | + cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]); | 105 | - TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; |
32 | } else { | 106 | - TCGv_i32 tcg_imm2, tcg_opcode; |
33 | - cpu_fprintf(f, " "); | 107 | |
34 | + cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i], | 108 | if (!dc_isar_feature(aa64_sm3, s)) { |
35 | + (i + 2) % 3 ? " " : "\n"); | 109 | unallocated_encoding(s); |
36 | } | 110 | @@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn) |
111 | return; | ||
37 | } | 112 | } |
38 | 113 | ||
114 | - tcg_rd_ptr = vec_full_reg_ptr(s, rd); | ||
115 | - tcg_rn_ptr = vec_full_reg_ptr(s, rn); | ||
116 | - tcg_rm_ptr = vec_full_reg_ptr(s, rm); | ||
117 | - tcg_imm2 = tcg_const_i32(imm2); | ||
118 | - tcg_opcode = tcg_const_i32(opcode); | ||
119 | - | ||
120 | - gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2, | ||
121 | - tcg_opcode); | ||
122 | - | ||
123 | - tcg_temp_free_ptr(tcg_rd_ptr); | ||
124 | - tcg_temp_free_ptr(tcg_rn_ptr); | ||
125 | - tcg_temp_free_ptr(tcg_rm_ptr); | ||
126 | - tcg_temp_free_i32(tcg_imm2); | ||
127 | - tcg_temp_free_i32(tcg_opcode); | ||
128 | + gen_gvec_op3_ool(s, true, rd, rn, rm, imm2, fns[opcode]); | ||
129 | } | ||
130 | |||
131 | /* C3.6 Data processing - SIMD, inc Crypto | ||
39 | -- | 132 | -- |
40 | 2.18.0 | 133 | 2.20.1 |
41 | 134 | ||
42 | 135 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | This fixes the intended protection of read-only values in the | 3 | The ADC region size is 256B, split as: |
4 | configuration register. They were being always set to zero by mistake. | 4 | - [0x00 - 0x4f] defined |
5 | - [0x50 - 0xff] reserved | ||
5 | 6 | ||
6 | The read-only fields depend on the configured memory size of the system, | 7 | All registers are 32-bit (thus when the datasheet mentions the |
7 | so they cannot be fixed at compile time. The most straight forward | 8 | last defined register is 0x4c, it means its address range is |
8 | option was to store them in the state structure. | 9 | 0x4c .. 0x4f. |
9 | 10 | ||
10 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 11 | This model implementation is also 32-bit. Set MemoryRegionOps |
11 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 12 | 'impl' fields. |
12 | Tested-by: Cédric Le Goater <clg@kaod.org> | 13 | |
13 | Message-id: 20180807075757.7242-3-joel@jms.id.au | 14 | See: |
15 | 'RM0033 Reference manual Rev 8', Table 10.13.18 "ADC register map". | ||
16 | |||
17 | Reported-by: Seth Kintigh <skintigh@gmail.com> | ||
18 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
20 | Message-id: 20200603055915.17678-1-f4bug@amsat.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 22 | --- |
16 | include/hw/misc/aspeed_sdmc.h | 1 + | 23 | hw/adc/stm32f2xx_adc.c | 4 +++- |
17 | hw/misc/aspeed_sdmc.c | 27 ++++++++------------------- | 24 | 1 file changed, 3 insertions(+), 1 deletion(-) |
18 | 2 files changed, 9 insertions(+), 19 deletions(-) | ||
19 | 25 | ||
20 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | 26 | diff --git a/hw/adc/stm32f2xx_adc.c b/hw/adc/stm32f2xx_adc.c |
21 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/misc/aspeed_sdmc.h | 28 | --- a/hw/adc/stm32f2xx_adc.c |
23 | +++ b/include/hw/misc/aspeed_sdmc.h | 29 | +++ b/hw/adc/stm32f2xx_adc.c |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState { | 30 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps stm32f2xx_adc_ops = { |
25 | uint32_t silicon_rev; | 31 | .read = stm32f2xx_adc_read, |
26 | uint32_t ram_bits; | 32 | .write = stm32f2xx_adc_write, |
27 | uint64_t ram_size; | 33 | .endianness = DEVICE_NATIVE_ENDIAN, |
28 | + uint32_t fixed_conf; | 34 | + .impl.min_access_size = 4, |
29 | 35 | + .impl.max_access_size = 4, | |
30 | } AspeedSDMCState; | 36 | }; |
31 | 37 | ||
32 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | 38 | static const VMStateDescription vmstate_stm32f2xx_adc = { |
33 | index XXXXXXX..XXXXXXX 100644 | 39 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_adc_init(Object *obj) |
34 | --- a/hw/misc/aspeed_sdmc.c | 40 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); |
35 | +++ b/hw/misc/aspeed_sdmc.c | 41 | |
36 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | 42 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_adc_ops, s, |
37 | case AST2400_A0_SILICON_REV: | 43 | - TYPE_STM32F2XX_ADC, 0xFF); |
38 | case AST2400_A1_SILICON_REV: | 44 | + TYPE_STM32F2XX_ADC, 0x100); |
39 | data &= ~ASPEED_SDMC_READONLY_MASK; | 45 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); |
40 | + data |= s->fixed_conf; | ||
41 | break; | ||
42 | case AST2500_A0_SILICON_REV: | ||
43 | case AST2500_A1_SILICON_REV: | ||
44 | data &= ~ASPEED_SDMC_AST2500_READONLY_MASK; | ||
45 | + data |= s->fixed_conf; | ||
46 | break; | ||
47 | default: | ||
48 | g_assert_not_reached(); | ||
49 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_reset(DeviceState *dev) | ||
50 | memset(s->regs, 0, sizeof(s->regs)); | ||
51 | |||
52 | /* Set ram size bit and defaults values */ | ||
53 | - switch (s->silicon_rev) { | ||
54 | - case AST2400_A0_SILICON_REV: | ||
55 | - case AST2400_A1_SILICON_REV: | ||
56 | - s->regs[R_CONF] |= | ||
57 | - ASPEED_SDMC_VGA_COMPAT | | ||
58 | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
59 | - break; | ||
60 | - | ||
61 | - case AST2500_A0_SILICON_REV: | ||
62 | - case AST2500_A1_SILICON_REV: | ||
63 | - s->regs[R_CONF] |= | ||
64 | - ASPEED_SDMC_HW_VERSION(1) | | ||
65 | - ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
66 | - ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
67 | - break; | ||
68 | - | ||
69 | - default: | ||
70 | - g_assert_not_reached(); | ||
71 | - } | ||
72 | + s->regs[R_CONF] = s->fixed_conf; | ||
73 | } | 46 | } |
74 | 47 | ||
75 | static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) | ||
76 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) | ||
77 | case AST2400_A0_SILICON_REV: | ||
78 | case AST2400_A1_SILICON_REV: | ||
79 | s->ram_bits = ast2400_rambits(s); | ||
80 | + s->fixed_conf = ASPEED_SDMC_VGA_COMPAT | | ||
81 | + ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
82 | break; | ||
83 | case AST2500_A0_SILICON_REV: | ||
84 | case AST2500_A1_SILICON_REV: | ||
85 | s->ram_bits = ast2500_rambits(s); | ||
86 | + s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | ||
87 | + ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
88 | + ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
89 | break; | ||
90 | default: | ||
91 | g_assert_not_reached(); | ||
92 | -- | 48 | -- |
93 | 2.18.0 | 49 | 2.20.1 |
94 | 50 | ||
95 | 51 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Thomas Huth <thuth@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | Now that we've got the common sysbus_init_child_obj() function, we do | 3 | As described by Edgar here: |
4 | not need the local init_sysbus_child() anymore. | ||
5 | 4 | ||
5 | https://www.mail-archive.com/qemu-devel@nongnu.org/msg605124.html | ||
6 | |||
7 | we can use the Ubuntu kernel for testing the xlnx-versal-virt machine. | ||
8 | So let's add a boot test for this now. | ||
9 | |||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
6 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 12 | Signed-off-by: Thomas Huth <thuth@redhat.com> |
7 | Message-id: 1534420566-15799-1-git-send-email-thuth@redhat.com | 13 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
15 | Message-id: 20200525141237.15243-1-thuth@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 17 | --- |
11 | hw/arm/mps2-tz.c | 32 +++++++++++--------------------- | 18 | tests/acceptance/boot_linux_console.py | 26 ++++++++++++++++++++++++++ |
12 | 1 file changed, 11 insertions(+), 21 deletions(-) | 19 | 1 file changed, 26 insertions(+) |
13 | 20 | ||
14 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 21 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py |
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/mps2-tz.c | 23 | --- a/tests/acceptance/boot_linux_console.py |
17 | +++ b/hw/arm/mps2-tz.c | 24 | +++ b/tests/acceptance/boot_linux_console.py |
18 | @@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name, | 25 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest): |
19 | memory_region_add_subregion(get_system_memory(), base, mr); | 26 | console_pattern = 'Kernel command line: %s' % kernel_command_line |
20 | } | 27 | self.wait_for_console_pattern(console_pattern) |
21 | 28 | ||
22 | -static void init_sysbus_child(Object *parent, const char *childname, | 29 | + def test_aarch64_xlnx_versal_virt(self): |
23 | - void *child, size_t childsize, | 30 | + """ |
24 | - const char *childtype) | 31 | + :avocado: tags=arch:aarch64 |
25 | -{ | 32 | + :avocado: tags=machine:xlnx-versal-virt |
26 | - object_initialize(child, childsize, childtype); | 33 | + :avocado: tags=device:pl011 |
27 | - object_property_add_child(parent, childname, OBJECT(child), &error_abort); | 34 | + :avocado: tags=device:arm_gicv3 |
28 | - qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); | 35 | + """ |
29 | - | 36 | + kernel_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/' |
30 | -} | 37 | + 'bionic-updates/main/installer-arm64/current/images/' |
31 | - | 38 | + 'netboot/ubuntu-installer/arm64/linux') |
32 | /* Most of the devices in the AN505 FPGA image sit behind | 39 | + kernel_hash = '5bfc54cf7ed8157d93f6e5b0241e727b6dc22c50' |
33 | * Peripheral Protection Controllers. These data structures | 40 | + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) |
34 | * define the layout of which devices sit behind which PPCs. | 41 | + |
35 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, | 42 | + initrd_url = ('http://ports.ubuntu.com/ubuntu-ports/dists/' |
36 | */ | 43 | + 'bionic-updates/main/installer-arm64/current/images/' |
37 | UnimplementedDeviceState *uds = opaque; | 44 | + 'netboot/ubuntu-installer/arm64/initrd.gz') |
38 | 45 | + initrd_hash = 'd385d3e88d53e2004c5d43cbe668b458a094f772' | |
39 | - init_sysbus_child(OBJECT(mms), name, uds, | 46 | + initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash) |
40 | - sizeof(UnimplementedDeviceState), | 47 | + |
41 | - TYPE_UNIMPLEMENTED_DEVICE); | 48 | + self.vm.set_console() |
42 | + sysbus_init_child_obj(OBJECT(mms), name, uds, | 49 | + self.vm.add_args('-m', '2G', |
43 | + sizeof(UnimplementedDeviceState), | 50 | + '-kernel', kernel_path, |
44 | + TYPE_UNIMPLEMENTED_DEVICE); | 51 | + '-initrd', initrd_path) |
45 | qdev_prop_set_string(DEVICE(uds), "name", name); | 52 | + self.vm.launch() |
46 | qdev_prop_set_uint64(DEVICE(uds), "size", size); | 53 | + self.wait_for_console_pattern('Checked W+X mappings: passed') |
47 | object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal); | 54 | + |
48 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, | 55 | def test_arm_virt(self): |
49 | DeviceState *iotkitdev = DEVICE(&mms->iotkit); | 56 | """ |
50 | DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); | 57 | :avocado: tags=arch:arm |
51 | |||
52 | - init_sysbus_child(OBJECT(mms), name, uart, | ||
53 | - sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); | ||
54 | + sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]), | ||
55 | + TYPE_CMSDK_APB_UART); | ||
56 | qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); | ||
57 | qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); | ||
58 | object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); | ||
59 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, | ||
60 | |||
61 | memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); | ||
62 | |||
63 | - init_sysbus_child(OBJECT(mms), mpcname, mpc, | ||
64 | - sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC); | ||
65 | + sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]), | ||
66 | + TYPE_TZ_MPC); | ||
67 | object_property_set_link(OBJECT(mpc), OBJECT(ssram), | ||
68 | "downstream", &error_fatal); | ||
69 | object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal); | ||
70 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
71 | exit(1); | ||
72 | } | ||
73 | |||
74 | - init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit, | ||
75 | - sizeof(mms->iotkit), TYPE_IOTKIT); | ||
76 | + sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, | ||
77 | + sizeof(mms->iotkit), TYPE_IOTKIT); | ||
78 | iotkitdev = DEVICE(&mms->iotkit); | ||
79 | object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | ||
80 | "memory", &error_abort); | ||
81 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
82 | int port; | ||
83 | char *gpioname; | ||
84 | |||
85 | - init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc, | ||
86 | - sizeof(TZPPC), TYPE_TZ_PPC); | ||
87 | + sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc, | ||
88 | + sizeof(TZPPC), TYPE_TZ_PPC); | ||
89 | ppcdev = DEVICE(ppc); | ||
90 | |||
91 | for (port = 0; port < TZ_NUM_PORTS; port++) { | ||
92 | -- | 58 | -- |
93 | 2.18.0 | 59 | 2.20.1 |
94 | 60 | ||
95 | 61 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Cédric Le Goater <clg@kaod.org> |
---|---|---|---|
2 | 2 | ||
3 | This will be used to construct a memory region beyond the RAM region | ||
4 | to let firmwares scan the address space with load/store to guess how | ||
5 | much RAM the SoC has. | ||
6 | |||
7 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 3 | Signed-off-by: Cédric Le Goater <clg@kaod.org> |
8 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 4 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
9 | Tested-by: Cédric Le Goater <clg@kaod.org> | 5 | Message-id: 20200602135050.593692-1-clg@kaod.org |
10 | Message-id: 20180807075757.7242-7-joel@jms.id.au | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 7 | --- |
14 | include/hw/misc/aspeed_sdmc.h | 1 + | 8 | docs/system/arm/aspeed.rst | 85 ++++++++++++++++++++++++++++++++++++++ |
15 | hw/arm/aspeed.c | 31 +++++++++++++++++++++++++++++++ | 9 | docs/system/target-arm.rst | 1 + |
16 | hw/arm/aspeed_soc.c | 2 ++ | 10 | 2 files changed, 86 insertions(+) |
17 | hw/misc/aspeed_sdmc.c | 3 +++ | 11 | create mode 100644 docs/system/arm/aspeed.rst |
18 | 4 files changed, 37 insertions(+) | ||
19 | 12 | ||
20 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | 13 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
14 | new file mode 100644 | ||
15 | index XXXXXXX..XXXXXXX | ||
16 | --- /dev/null | ||
17 | +++ b/docs/system/arm/aspeed.rst | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | +Aspeed family boards (``*-bmc``, ``ast2500-evb``, ``ast2600-evb``) | ||
20 | +================================================================== | ||
21 | + | ||
22 | +The QEMU Aspeed machines model BMCs of various OpenPOWER systems and | ||
23 | +Aspeed evaluation boards. They are based on different releases of the | ||
24 | +Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the | ||
25 | +AST2500 with an ARM1176JZS CPU (800MHz) and more recently the AST2600 | ||
26 | +with dual cores ARM Cortex A7 CPUs (1.2GHz). | ||
27 | + | ||
28 | +The SoC comes with RAM, Gigabit ethernet, USB, SD/MMC, USB, SPI, I2C, | ||
29 | +etc. | ||
30 | + | ||
31 | +AST2400 SoC based machines : | ||
32 | + | ||
33 | +- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC | ||
34 | + | ||
35 | +AST2500 SoC based machines : | ||
36 | + | ||
37 | +- ``ast2500-evb`` Aspeed AST2500 Evaluation board | ||
38 | +- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC | ||
39 | +- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC | ||
40 | +- ``sonorapass-bmc`` OCP SonoraPass BMC | ||
41 | +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 | ||
42 | + | ||
43 | +AST2600 SoC based machines : | ||
44 | + | ||
45 | +- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex A7) | ||
46 | +- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC | ||
47 | + | ||
48 | +Supported devices | ||
49 | +----------------- | ||
50 | + | ||
51 | + * SMP (for the AST2600 Cortex-A7) | ||
52 | + * Interrupt Controller (VIC) | ||
53 | + * Timer Controller | ||
54 | + * RTC Controller | ||
55 | + * I2C Controller | ||
56 | + * System Control Unit (SCU) | ||
57 | + * SRAM mapping | ||
58 | + * X-DMA Controller (basic interface) | ||
59 | + * Static Memory Controller (SMC or FMC) - Only SPI Flash support | ||
60 | + * SPI Memory Controller | ||
61 | + * USB 2.0 Controller | ||
62 | + * SD/MMC storage controllers | ||
63 | + * SDRAM controller (dummy interface for basic settings and training) | ||
64 | + * Watchdog Controller | ||
65 | + * GPIO Controller (Master only) | ||
66 | + * UART | ||
67 | + * Ethernet controllers | ||
68 | + | ||
69 | + | ||
70 | +Missing devices | ||
71 | +--------------- | ||
72 | + | ||
73 | + * Coprocessor support | ||
74 | + * ADC (out of tree implementation) | ||
75 | + * PWM and Fan Controller | ||
76 | + * LPC Bus Controller | ||
77 | + * Slave GPIO Controller | ||
78 | + * Super I/O Controller | ||
79 | + * Hash/Crypto Engine | ||
80 | + * PCI-Express 1 Controller | ||
81 | + * Graphic Display Controller | ||
82 | + * PECI Controller | ||
83 | + * MCTP Controller | ||
84 | + * Mailbox Controller | ||
85 | + * Virtual UART | ||
86 | + * eSPI Controller | ||
87 | + * I3C Controller | ||
88 | + | ||
89 | +Boot options | ||
90 | +------------ | ||
91 | + | ||
92 | +The Aspeed machines can be started using the -kernel option to load a | ||
93 | +Linux kernel or from a firmare image which can be downloaded from the | ||
94 | +OpenPOWER jenkins : | ||
95 | + | ||
96 | + https://openpower.xyz/ | ||
97 | + | ||
98 | +The image should be attached as an MTD drive. Run : | ||
99 | + | ||
100 | +.. code-block:: bash | ||
101 | + | ||
102 | + $ qemu-system-arm -M romulus-bmc -nic user \ | ||
103 | + -drive file=flash-romulus,format=raw,if=mtd -nographic | ||
104 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
21 | index XXXXXXX..XXXXXXX 100644 | 105 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/misc/aspeed_sdmc.h | 106 | --- a/docs/system/target-arm.rst |
23 | +++ b/include/hw/misc/aspeed_sdmc.h | 107 | +++ b/docs/system/target-arm.rst |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState { | 108 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
25 | uint32_t silicon_rev; | 109 | arm/realview |
26 | uint32_t ram_bits; | 110 | arm/versatile |
27 | uint64_t ram_size; | 111 | arm/vexpress |
28 | + uint64_t max_ram_size; | 112 | + arm/aspeed |
29 | uint32_t fixed_conf; | 113 | arm/musicpal |
30 | 114 | arm/nseries | |
31 | } AspeedSDMCState; | 115 | arm/orangepi |
32 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/hw/arm/aspeed.c | ||
35 | +++ b/hw/arm/aspeed.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = { | ||
37 | typedef struct AspeedBoardState { | ||
38 | AspeedSoCState soc; | ||
39 | MemoryRegion ram; | ||
40 | + MemoryRegion max_ram; | ||
41 | } AspeedBoardState; | ||
42 | |||
43 | typedef struct AspeedBoardConfig { | ||
44 | @@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = { | ||
45 | }, | ||
46 | }; | ||
47 | |||
48 | +/* | ||
49 | + * The max ram region is for firmwares that scan the address space | ||
50 | + * with load/store to guess how much RAM the SoC has. | ||
51 | + */ | ||
52 | +static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) | ||
53 | +{ | ||
54 | + return 0; | ||
55 | +} | ||
56 | + | ||
57 | +static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, | ||
58 | + unsigned size) | ||
59 | +{ | ||
60 | + /* Discard writes */ | ||
61 | +} | ||
62 | + | ||
63 | +static const MemoryRegionOps max_ram_ops = { | ||
64 | + .read = max_ram_read, | ||
65 | + .write = max_ram_write, | ||
66 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
67 | +}; | ||
68 | + | ||
69 | #define FIRMWARE_ADDR 0x0 | ||
70 | |||
71 | static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, | ||
72 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
73 | AspeedBoardState *bmc; | ||
74 | AspeedSoCClass *sc; | ||
75 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); | ||
76 | + ram_addr_t max_ram_size; | ||
77 | |||
78 | bmc = g_new0(AspeedBoardState, 1); | ||
79 | object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name); | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine, | ||
81 | object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram), | ||
82 | &error_abort); | ||
83 | |||
84 | + max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", | ||
85 | + &error_abort); | ||
86 | + memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, | ||
87 | + "max_ram", max_ram_size - ram_size); | ||
88 | + memory_region_add_subregion(get_system_memory(), | ||
89 | + sc->info->sdram_base + ram_size, | ||
90 | + &bmc->max_ram); | ||
91 | + | ||
92 | aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort); | ||
93 | aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort); | ||
94 | |||
95 | diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/hw/arm/aspeed_soc.c | ||
98 | +++ b/hw/arm/aspeed_soc.c | ||
99 | @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) | ||
100 | sc->info->silicon_rev); | ||
101 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), | ||
102 | "ram-size", &error_abort); | ||
103 | + object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), | ||
104 | + "max-ram-size", &error_abort); | ||
105 | |||
106 | for (i = 0; i < sc->info->wdts_num; i++) { | ||
107 | object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); | ||
108 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | ||
109 | index XXXXXXX..XXXXXXX 100644 | ||
110 | --- a/hw/misc/aspeed_sdmc.c | ||
111 | +++ b/hw/misc/aspeed_sdmc.c | ||
112 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) | ||
113 | case AST2400_A0_SILICON_REV: | ||
114 | case AST2400_A1_SILICON_REV: | ||
115 | s->ram_bits = ast2400_rambits(s); | ||
116 | + s->max_ram_size = 512 << 20; | ||
117 | s->fixed_conf = ASPEED_SDMC_VGA_COMPAT | | ||
118 | ASPEED_SDMC_DRAM_SIZE(s->ram_bits); | ||
119 | break; | ||
120 | case AST2500_A0_SILICON_REV: | ||
121 | case AST2500_A1_SILICON_REV: | ||
122 | s->ram_bits = ast2500_rambits(s); | ||
123 | + s->max_ram_size = 1024 << 20; | ||
124 | s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | | ||
125 | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | | ||
126 | ASPEED_SDMC_CACHE_INITIAL_DONE | | ||
127 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdmc = { | ||
128 | static Property aspeed_sdmc_properties[] = { | ||
129 | DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0), | ||
130 | DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), | ||
131 | + DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), | ||
132 | DEFINE_PROP_END_OF_LIST(), | ||
133 | }; | ||
134 | |||
135 | -- | 116 | -- |
136 | 2.18.0 | 117 | 2.20.1 |
137 | 118 | ||
138 | 119 | diff view generated by jsdifflib |
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | 3 | Add BCM2835 SOC MPHI (Message-based Parallel Host Interface) |
4 | Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net | 4 | emulation. It is very basic, only providing the FIQ interrupt |
5 | needed to allow the dwc-otg USB host controller driver in the | ||
6 | Raspbian kernel to function. | ||
7 | |||
8 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> | ||
9 | Acked-by: Philippe Mathieu-Daude <f4bug@amsat.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Message-id: 20200520235349.21215-2-pauldzim@gmail.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | hw/arm/Makefile.objs | 1 + | 14 | include/hw/arm/bcm2835_peripherals.h | 2 + |
9 | include/hw/arm/fsl-imx6ul.h | 339 ++++++++++++++++++ | 15 | include/hw/misc/bcm2835_mphi.h | 44 ++++++ |
10 | hw/arm/fsl-imx6ul.c | 617 ++++++++++++++++++++++++++++++++ | 16 | hw/arm/bcm2835_peripherals.c | 17 +++ |
11 | default-configs/arm-softmmu.mak | 1 + | 17 | hw/misc/bcm2835_mphi.c | 191 +++++++++++++++++++++++++++ |
12 | 4 files changed, 958 insertions(+) | 18 | hw/misc/Makefile.objs | 1 + |
13 | create mode 100644 include/hw/arm/fsl-imx6ul.h | 19 | 5 files changed, 255 insertions(+) |
14 | create mode 100644 hw/arm/fsl-imx6ul.c | 20 | create mode 100644 include/hw/misc/bcm2835_mphi.h |
15 | 21 | create mode 100644 hw/misc/bcm2835_mphi.c | |
16 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | 22 | |
23 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/hw/arm/Makefile.objs | 25 | --- a/include/hw/arm/bcm2835_peripherals.h |
19 | +++ b/hw/arm/Makefile.objs | 26 | +++ b/include/hw/arm/bcm2835_peripherals.h |
20 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | 27 | @@ -XXX,XX +XXX,XX @@ |
21 | obj-$(CONFIG_IOTKIT) += iotkit.o | 28 | #include "hw/misc/bcm2835_property.h" |
22 | obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o | 29 | #include "hw/misc/bcm2835_rng.h" |
23 | obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o | 30 | #include "hw/misc/bcm2835_mbox.h" |
24 | +obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o | 31 | +#include "hw/misc/bcm2835_mphi.h" |
25 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | 32 | #include "hw/misc/bcm2835_thermal.h" |
33 | #include "hw/sd/sdhci.h" | ||
34 | #include "hw/sd/bcm2835_sdhost.h" | ||
35 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState { | ||
36 | qemu_irq irq, fiq; | ||
37 | |||
38 | BCM2835SystemTimerState systmr; | ||
39 | + BCM2835MphiState mphi; | ||
40 | UnimplementedDeviceState armtmr; | ||
41 | UnimplementedDeviceState cprman; | ||
42 | UnimplementedDeviceState a2w; | ||
43 | diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h | ||
26 | new file mode 100644 | 44 | new file mode 100644 |
27 | index XXXXXXX..XXXXXXX | 45 | index XXXXXXX..XXXXXXX |
28 | --- /dev/null | 46 | --- /dev/null |
29 | +++ b/include/hw/arm/fsl-imx6ul.h | 47 | +++ b/include/hw/misc/bcm2835_mphi.h |
30 | @@ -XXX,XX +XXX,XX @@ | 48 | @@ -XXX,XX +XXX,XX @@ |
31 | +/* | 49 | +/* |
32 | + * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> | 50 | + * BCM2835 SOC MPHI state definitions |
33 | + * | 51 | + * |
34 | + * i.MX6ul SoC definitions | 52 | + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com> |
35 | + * | 53 | + * |
36 | + * This program is free software; you can redistribute it and/or modify | 54 | + * This program is free software; you can redistribute it and/or modify |
37 | + * it under the terms of the GNU General Public License as published by | 55 | + * it under the terms of the GNU General Public License as published by |
38 | + * the Free Software Foundation; either version 2 of the License, or | 56 | + * the Free Software Foundation; either version 2 of the License, or |
39 | + * (at your option) any later version. | 57 | + * (at your option) any later version. |
... | ... | ||
42 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | 60 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
43 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 61 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
44 | + * GNU General Public License for more details. | 62 | + * GNU General Public License for more details. |
45 | + */ | 63 | + */ |
46 | + | 64 | + |
47 | +#ifndef FSL_IMX6UL_H | 65 | +#ifndef HW_MISC_BCM2835_MPHI_H |
48 | +#define FSL_IMX6UL_H | 66 | +#define HW_MISC_BCM2835_MPHI_H |
49 | + | 67 | + |
50 | +#include "hw/arm/arm.h" | 68 | +#include "hw/irq.h" |
51 | +#include "hw/cpu/a15mpcore.h" | 69 | +#include "hw/sysbus.h" |
52 | +#include "hw/misc/imx6ul_ccm.h" | 70 | + |
53 | +#include "hw/misc/imx6_src.h" | 71 | +#define MPHI_MMIO_SIZE 0x1000 |
54 | +#include "hw/misc/imx7_snvs.h" | 72 | + |
55 | +#include "hw/misc/imx7_gpr.h" | 73 | +typedef struct BCM2835MphiState BCM2835MphiState; |
56 | +#include "hw/intc/imx_gpcv2.h" | 74 | + |
57 | +#include "hw/misc/imx2_wdt.h" | 75 | +struct BCM2835MphiState { |
58 | +#include "hw/gpio/imx_gpio.h" | 76 | + SysBusDevice parent_obj; |
59 | +#include "hw/char/imx_serial.h" | 77 | + qemu_irq irq; |
60 | +#include "hw/timer/imx_gpt.h" | 78 | + MemoryRegion iomem; |
61 | +#include "hw/timer/imx_epit.h" | 79 | + |
62 | +#include "hw/i2c/imx_i2c.h" | 80 | + uint32_t outdda; |
63 | +#include "hw/gpio/imx_gpio.h" | 81 | + uint32_t outddb; |
64 | +#include "hw/sd/sdhci.h" | 82 | + uint32_t ctrl; |
65 | +#include "hw/ssi/imx_spi.h" | 83 | + uint32_t intstat; |
66 | +#include "hw/net/imx_fec.h" | 84 | + uint32_t swirq; |
67 | +#include "exec/memory.h" | ||
68 | +#include "cpu.h" | ||
69 | + | ||
70 | +#define TYPE_FSL_IMX6UL "fsl,imx6ul" | ||
71 | +#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL) | ||
72 | + | ||
73 | +enum FslIMX6ULConfiguration { | ||
74 | + FSL_IMX6UL_NUM_CPUS = 1, | ||
75 | + FSL_IMX6UL_NUM_UARTS = 8, | ||
76 | + FSL_IMX6UL_NUM_ETHS = 2, | ||
77 | + FSL_IMX6UL_ETH_NUM_TX_RINGS = 2, | ||
78 | + FSL_IMX6UL_NUM_USDHCS = 2, | ||
79 | + FSL_IMX6UL_NUM_WDTS = 3, | ||
80 | + FSL_IMX6UL_NUM_GPTS = 2, | ||
81 | + FSL_IMX6UL_NUM_EPITS = 2, | ||
82 | + FSL_IMX6UL_NUM_IOMUXCS = 2, | ||
83 | + FSL_IMX6UL_NUM_GPIOS = 5, | ||
84 | + FSL_IMX6UL_NUM_I2CS = 4, | ||
85 | + FSL_IMX6UL_NUM_ECSPIS = 4, | ||
86 | + FSL_IMX6UL_NUM_ADCS = 2, | ||
87 | +}; | 85 | +}; |
88 | + | 86 | + |
89 | +typedef struct FslIMX6ULState { | 87 | +#define TYPE_BCM2835_MPHI "bcm2835-mphi" |
90 | + /*< private >*/ | 88 | + |
91 | + DeviceState parent_obj; | 89 | +#define BCM2835_MPHI(obj) \ |
92 | + | 90 | + OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI) |
93 | + /*< public >*/ | 91 | + |
94 | + ARMCPU cpu[FSL_IMX6UL_NUM_CPUS]; | 92 | +#endif |
95 | + A15MPPrivState a7mpcore; | 93 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c |
96 | + IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS]; | 94 | index XXXXXXX..XXXXXXX 100644 |
97 | + IMXEPITState epit[FSL_IMX6UL_NUM_EPITS]; | 95 | --- a/hw/arm/bcm2835_peripherals.c |
98 | + IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS]; | 96 | +++ b/hw/arm/bcm2835_peripherals.c |
99 | + IMX6ULCCMState ccm; | 97 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) |
100 | + IMX6SRCState src; | 98 | OBJECT(&s->sdhci.sdbus)); |
101 | + IMX7SNVSState snvs; | 99 | object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", |
102 | + IMXGPCv2State gpcv2; | 100 | OBJECT(&s->sdhost.sdbus)); |
103 | + IMX7GPRState gpr; | 101 | + |
104 | + IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; | 102 | + /* Mphi */ |
105 | + IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; | 103 | + sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi), |
106 | + IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; | 104 | + TYPE_BCM2835_MPHI); |
107 | + IMXFECState eth[FSL_IMX6UL_NUM_ETHS]; | 105 | } |
108 | + SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS]; | 106 | |
109 | + IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS]; | 107 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) |
110 | + MemoryRegion rom; | 108 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) |
111 | + MemoryRegion caam; | 109 | |
112 | + MemoryRegion ocram; | 110 | object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus"); |
113 | + MemoryRegion ocram_alias; | 111 | |
114 | +} FslIMX6ULState; | 112 | + /* Mphi */ |
115 | + | 113 | + object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err); |
116 | +enum FslIMX6ULMemoryMap { | 114 | + if (err) { |
117 | + FSL_IMX6UL_MMDC_ADDR = 0x80000000, | 115 | + error_propagate(errp, err); |
118 | + FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, | 116 | + return; |
119 | + | 117 | + } |
120 | + FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, | 118 | + |
121 | + FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, | 119 | + memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET, |
122 | + FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | 120 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0)); |
123 | + FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | 121 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, |
124 | + FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | 122 | + qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, |
125 | + | 123 | + INTERRUPT_HOSTPORT)); |
126 | + /* AIPS-2 */ | 124 | + |
127 | + FSL_IMX6UL_UART6_ADDR = 0x021FC000, | 125 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); |
128 | + FSL_IMX6UL_I2C4_ADDR = 0x021F8000, | 126 | create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); |
129 | + FSL_IMX6UL_UART5_ADDR = 0x021F4000, | 127 | create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); |
130 | + FSL_IMX6UL_UART4_ADDR = 0x021F0000, | 128 | diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c |
131 | + FSL_IMX6UL_UART3_ADDR = 0x021EC000, | ||
132 | + FSL_IMX6UL_UART2_ADDR = 0x021E8000, | ||
133 | + FSL_IMX6UL_WDOG3_ADDR = 0x021E4000, | ||
134 | + FSL_IMX6UL_QSPI_ADDR = 0x021E0000, | ||
135 | + FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000, | ||
136 | + FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000, | ||
137 | + FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000, | ||
138 | + FSL_IMX6UL_TZASC_ADDR = 0x021D0000, | ||
139 | + FSL_IMX6UL_PXP_ADDR = 0x021CC000, | ||
140 | + FSL_IMX6UL_LCDIF_ADDR = 0x021C8000, | ||
141 | + FSL_IMX6UL_CSI_ADDR = 0x021C4000, | ||
142 | + FSL_IMX6UL_CSU_ADDR = 0x021C0000, | ||
143 | + FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000, | ||
144 | + FSL_IMX6UL_EIM_ADDR = 0x021B8000, | ||
145 | + FSL_IMX6UL_SIM2_ADDR = 0x021B4000, | ||
146 | + FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000, | ||
147 | + FSL_IMX6UL_ROMCP_ADDR = 0x021AC000, | ||
148 | + FSL_IMX6UL_I2C3_ADDR = 0x021A8000, | ||
149 | + FSL_IMX6UL_I2C2_ADDR = 0x021A4000, | ||
150 | + FSL_IMX6UL_I2C1_ADDR = 0x021A0000, | ||
151 | + FSL_IMX6UL_ADC2_ADDR = 0x0219C000, | ||
152 | + FSL_IMX6UL_ADC1_ADDR = 0x02198000, | ||
153 | + FSL_IMX6UL_USDHC2_ADDR = 0x02194000, | ||
154 | + FSL_IMX6UL_USDHC1_ADDR = 0x02190000, | ||
155 | + FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
156 | + FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
157 | + FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
158 | + FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000, | ||
159 | + FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
160 | + FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
161 | + FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
162 | + FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
163 | + | ||
164 | + /* AIPS-1 */ | ||
165 | + FSL_IMX6UL_PWM8_ADDR = 0x020FC000, | ||
166 | + FSL_IMX6UL_PWM7_ADDR = 0x020F8000, | ||
167 | + FSL_IMX6UL_PWM6_ADDR = 0x020F4000, | ||
168 | + FSL_IMX6UL_PWM5_ADDR = 0x020F0000, | ||
169 | + FSL_IMX6UL_SDMA_ADDR = 0x020EC000, | ||
170 | + FSL_IMX6UL_GPT2_ADDR = 0x020E8000, | ||
171 | + FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000, | ||
172 | + FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000, | ||
173 | + FSL_IMX6UL_GPC_ADDR = 0x020DC000, | ||
174 | + FSL_IMX6UL_SRC_ADDR = 0x020D8000, | ||
175 | + FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, | ||
176 | + FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, | ||
177 | + FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, | ||
178 | + FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, | ||
179 | + FSL_IMX6UL_CCM_ADDR = 0x020C4000, | ||
180 | + FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, | ||
181 | + FSL_IMX6UL_WDOG1_ADDR = 0x020BC000, | ||
182 | + FSL_IMX6UL_KPP_ADDR = 0x020B8000, | ||
183 | + FSL_IMX6UL_ENET2_ADDR = 0x020B4000, | ||
184 | + FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000, | ||
185 | + FSL_IMX6UL_GPIO5_ADDR = 0x020AC000, | ||
186 | + FSL_IMX6UL_GPIO4_ADDR = 0x020A8000, | ||
187 | + FSL_IMX6UL_GPIO3_ADDR = 0x020A4000, | ||
188 | + FSL_IMX6UL_GPIO2_ADDR = 0x020A0000, | ||
189 | + FSL_IMX6UL_GPIO1_ADDR = 0x0209C000, | ||
190 | + FSL_IMX6UL_GPT1_ADDR = 0x02098000, | ||
191 | + FSL_IMX6UL_CAN2_ADDR = 0x02094000, | ||
192 | + FSL_IMX6UL_CAN1_ADDR = 0x02090000, | ||
193 | + FSL_IMX6UL_PWM4_ADDR = 0x0208C000, | ||
194 | + FSL_IMX6UL_PWM3_ADDR = 0x02088000, | ||
195 | + FSL_IMX6UL_PWM2_ADDR = 0x02084000, | ||
196 | + FSL_IMX6UL_PWM1_ADDR = 0x02080000, | ||
197 | + FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000, | ||
198 | + FSL_IMX6UL_BEE_ADDR = 0x02044000, | ||
199 | + FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000, | ||
200 | + FSL_IMX6UL_SPBA_ADDR = 0x0203C000, | ||
201 | + FSL_IMX6UL_ASRC_ADDR = 0x02034000, | ||
202 | + FSL_IMX6UL_SAI3_ADDR = 0x02030000, | ||
203 | + FSL_IMX6UL_SAI2_ADDR = 0x0202C000, | ||
204 | + FSL_IMX6UL_SAI1_ADDR = 0x02028000, | ||
205 | + FSL_IMX6UL_UART8_ADDR = 0x02024000, | ||
206 | + FSL_IMX6UL_UART1_ADDR = 0x02020000, | ||
207 | + FSL_IMX6UL_UART7_ADDR = 0x02018000, | ||
208 | + FSL_IMX6UL_ECSPI4_ADDR = 0x02014000, | ||
209 | + FSL_IMX6UL_ECSPI3_ADDR = 0x02010000, | ||
210 | + FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000, | ||
211 | + FSL_IMX6UL_ECSPI1_ADDR = 0x02008000, | ||
212 | + FSL_IMX6UL_SPDIF_ADDR = 0x02004000, | ||
213 | + | ||
214 | + FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000, | ||
215 | + FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024), | ||
216 | + | ||
217 | + FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000, | ||
218 | + | ||
219 | + FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000, | ||
220 | + FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000, | ||
221 | + FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000, | ||
222 | + FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000, | ||
223 | + FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000, | ||
224 | + FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000, | ||
225 | + FSL_IMX6UL_ROM_ADDR = 0x00000000, | ||
226 | + FSL_IMX6UL_ROM_SIZE = 0x00018000, | ||
227 | +}; | ||
228 | + | ||
229 | +enum FslIMX6ULIRQs { | ||
230 | + FSL_IMX6UL_IOMUXC_IRQ = 0, | ||
231 | + FSL_IMX6UL_DAP_IRQ = 1, | ||
232 | + FSL_IMX6UL_SDMA_IRQ = 2, | ||
233 | + FSL_IMX6UL_TSC_IRQ = 3, | ||
234 | + FSL_IMX6UL_SNVS_IRQ = 4, | ||
235 | + FSL_IMX6UL_LCDIF_IRQ = 5, | ||
236 | + FSL_IMX6UL_BEE_IRQ = 6, | ||
237 | + FSL_IMX6UL_CSI_IRQ = 7, | ||
238 | + FSL_IMX6UL_PXP_IRQ = 8, | ||
239 | + FSL_IMX6UL_SCTR1_IRQ = 9, | ||
240 | + FSL_IMX6UL_SCTR2_IRQ = 10, | ||
241 | + FSL_IMX6UL_WDOG3_IRQ = 11, | ||
242 | + FSL_IMX6UL_APBH_DMA_IRQ = 13, | ||
243 | + FSL_IMX6UL_WEIM_IRQ = 14, | ||
244 | + FSL_IMX6UL_RAWNAND1_IRQ = 15, | ||
245 | + FSL_IMX6UL_RAWNAND2_IRQ = 16, | ||
246 | + FSL_IMX6UL_UART6_IRQ = 17, | ||
247 | + FSL_IMX6UL_SRTC_IRQ = 19, | ||
248 | + FSL_IMX6UL_SRTC_SEC_IRQ = 20, | ||
249 | + FSL_IMX6UL_CSU_IRQ = 21, | ||
250 | + FSL_IMX6UL_USDHC1_IRQ = 22, | ||
251 | + FSL_IMX6UL_USDHC2_IRQ = 23, | ||
252 | + FSL_IMX6UL_SAI3_IRQ = 24, | ||
253 | + FSL_IMX6UL_SAI32_IRQ = 25, | ||
254 | + | ||
255 | + FSL_IMX6UL_UART1_IRQ = 26, | ||
256 | + FSL_IMX6UL_UART2_IRQ = 27, | ||
257 | + FSL_IMX6UL_UART3_IRQ = 28, | ||
258 | + FSL_IMX6UL_UART4_IRQ = 29, | ||
259 | + FSL_IMX6UL_UART5_IRQ = 30, | ||
260 | + | ||
261 | + FSL_IMX6UL_ECSPI1_IRQ = 31, | ||
262 | + FSL_IMX6UL_ECSPI2_IRQ = 32, | ||
263 | + FSL_IMX6UL_ECSPI3_IRQ = 33, | ||
264 | + FSL_IMX6UL_ECSPI4_IRQ = 34, | ||
265 | + | ||
266 | + FSL_IMX6UL_I2C4_IRQ = 35, | ||
267 | + FSL_IMX6UL_I2C1_IRQ = 36, | ||
268 | + FSL_IMX6UL_I2C2_IRQ = 37, | ||
269 | + FSL_IMX6UL_I2C3_IRQ = 38, | ||
270 | + | ||
271 | + FSL_IMX6UL_UART7_IRQ = 39, | ||
272 | + FSL_IMX6UL_UART8_IRQ = 40, | ||
273 | + | ||
274 | + FSL_IMX6UL_USB1_IRQ = 42, | ||
275 | + FSL_IMX6UL_USB2_IRQ = 43, | ||
276 | + FSL_IMX6UL_USB_PHY1_IRQ = 44, | ||
277 | + FSL_IMX6UL_USB_PHY2_IRQ = 44, | ||
278 | + | ||
279 | + FSL_IMX6UL_CAAM_JQ2_IRQ = 46, | ||
280 | + FSL_IMX6UL_CAAM_ERR_IRQ = 47, | ||
281 | + FSL_IMX6UL_CAAM_RTIC_IRQ = 48, | ||
282 | + FSL_IMX6UL_TEMP_IRQ = 49, | ||
283 | + FSL_IMX6UL_ASRC_IRQ = 50, | ||
284 | + FSL_IMX6UL_SPDIF_IRQ = 52, | ||
285 | + FSL_IMX6UL_PMU_REG_IRQ = 54, | ||
286 | + FSL_IMX6UL_GPT1_IRQ = 55, | ||
287 | + | ||
288 | + FSL_IMX6UL_EPIT1_IRQ = 56, | ||
289 | + FSL_IMX6UL_EPIT2_IRQ = 57, | ||
290 | + | ||
291 | + FSL_IMX6UL_GPIO1_INT7_IRQ = 58, | ||
292 | + FSL_IMX6UL_GPIO1_INT6_IRQ = 59, | ||
293 | + FSL_IMX6UL_GPIO1_INT5_IRQ = 60, | ||
294 | + FSL_IMX6UL_GPIO1_INT4_IRQ = 61, | ||
295 | + FSL_IMX6UL_GPIO1_INT3_IRQ = 62, | ||
296 | + FSL_IMX6UL_GPIO1_INT2_IRQ = 63, | ||
297 | + FSL_IMX6UL_GPIO1_INT1_IRQ = 64, | ||
298 | + FSL_IMX6UL_GPIO1_INT0_IRQ = 65, | ||
299 | + FSL_IMX6UL_GPIO1_LOW_IRQ = 66, | ||
300 | + FSL_IMX6UL_GPIO1_HIGH_IRQ = 67, | ||
301 | + FSL_IMX6UL_GPIO2_LOW_IRQ = 68, | ||
302 | + FSL_IMX6UL_GPIO2_HIGH_IRQ = 69, | ||
303 | + FSL_IMX6UL_GPIO3_LOW_IRQ = 70, | ||
304 | + FSL_IMX6UL_GPIO3_HIGH_IRQ = 71, | ||
305 | + FSL_IMX6UL_GPIO4_LOW_IRQ = 72, | ||
306 | + FSL_IMX6UL_GPIO4_HIGH_IRQ = 73, | ||
307 | + FSL_IMX6UL_GPIO5_LOW_IRQ = 74, | ||
308 | + FSL_IMX6UL_GPIO5_HIGH_IRQ = 75, | ||
309 | + | ||
310 | + FSL_IMX6UL_WDOG1_IRQ = 80, | ||
311 | + FSL_IMX6UL_WDOG2_IRQ = 81, | ||
312 | + | ||
313 | + FSL_IMX6UL_KPP_IRQ = 82, | ||
314 | + | ||
315 | + FSL_IMX6UL_PWM1_IRQ = 83, | ||
316 | + FSL_IMX6UL_PWM2_IRQ = 84, | ||
317 | + FSL_IMX6UL_PWM3_IRQ = 85, | ||
318 | + FSL_IMX6UL_PWM4_IRQ = 86, | ||
319 | + | ||
320 | + FSL_IMX6UL_CCM1_IRQ = 87, | ||
321 | + FSL_IMX6UL_CCM2_IRQ = 88, | ||
322 | + | ||
323 | + FSL_IMX6UL_GPC_IRQ = 89, | ||
324 | + | ||
325 | + FSL_IMX6UL_SRC_IRQ = 91, | ||
326 | + | ||
327 | + FSL_IMX6UL_CPU_PERF_IRQ = 94, | ||
328 | + FSL_IMX6UL_CPU_CTI_IRQ = 95, | ||
329 | + | ||
330 | + FSL_IMX6UL_SRC_WDOG_IRQ = 96, | ||
331 | + | ||
332 | + FSL_IMX6UL_SAI1_IRQ = 97, | ||
333 | + FSL_IMX6UL_SAI2_IRQ = 98, | ||
334 | + | ||
335 | + FSL_IMX6UL_ADC1_IRQ = 100, | ||
336 | + FSL_IMX6UL_ADC2_IRQ = 101, | ||
337 | + | ||
338 | + FSL_IMX6UL_SJC_IRQ = 104, | ||
339 | + | ||
340 | + FSL_IMX6UL_CAAM_RING0_IRQ = 105, | ||
341 | + FSL_IMX6UL_CAAM_RING1_IRQ = 106, | ||
342 | + | ||
343 | + FSL_IMX6UL_QSPI_IRQ = 107, | ||
344 | + | ||
345 | + FSL_IMX6UL_TZASC_IRQ = 108, | ||
346 | + | ||
347 | + FSL_IMX6UL_GPT2_IRQ = 109, | ||
348 | + | ||
349 | + FSL_IMX6UL_CAN1_IRQ = 110, | ||
350 | + FSL_IMX6UL_CAN2_IRQ = 111, | ||
351 | + | ||
352 | + FSL_IMX6UL_SIM1_IRQ = 112, | ||
353 | + FSL_IMX6UL_SIM2_IRQ = 113, | ||
354 | + | ||
355 | + FSL_IMX6UL_PWM5_IRQ = 114, | ||
356 | + FSL_IMX6UL_PWM6_IRQ = 115, | ||
357 | + FSL_IMX6UL_PWM7_IRQ = 116, | ||
358 | + FSL_IMX6UL_PWM8_IRQ = 117, | ||
359 | + | ||
360 | + FSL_IMX6UL_ENET1_IRQ = 118, | ||
361 | + FSL_IMX6UL_ENET1_TIMER_IRQ = 119, | ||
362 | + FSL_IMX6UL_ENET2_IRQ = 120, | ||
363 | + FSL_IMX6UL_ENET2_TIMER_IRQ = 121, | ||
364 | + | ||
365 | + FSL_IMX6UL_PMU_CORE_IRQ = 127, | ||
366 | + FSL_IMX6UL_MAX_IRQ = 128, | ||
367 | +}; | ||
368 | + | ||
369 | +#endif /* FSL_IMX6UL_H */ | ||
370 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
371 | new file mode 100644 | 129 | new file mode 100644 |
372 | index XXXXXXX..XXXXXXX | 130 | index XXXXXXX..XXXXXXX |
373 | --- /dev/null | 131 | --- /dev/null |
374 | +++ b/hw/arm/fsl-imx6ul.c | 132 | +++ b/hw/misc/bcm2835_mphi.c |
375 | @@ -XXX,XX +XXX,XX @@ | 133 | @@ -XXX,XX +XXX,XX @@ |
376 | +/* | 134 | +/* |
377 | + * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> | 135 | + * BCM2835 SOC MPHI emulation |
378 | + * | 136 | + * |
379 | + * i.MX6UL SOC emulation. | 137 | + * Very basic emulation, only providing the FIQ interrupt needed to |
380 | + * | 138 | + * allow the dwc-otg USB host controller driver in the Raspbian kernel |
381 | + * Based on hw/arm/fsl-imx7.c | 139 | + * to function. |
140 | + * | ||
141 | + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com> | ||
382 | + * | 142 | + * |
383 | + * This program is free software; you can redistribute it and/or modify | 143 | + * This program is free software; you can redistribute it and/or modify |
384 | + * it under the terms of the GNU General Public License as published by | 144 | + * it under the terms of the GNU General Public License as published by |
385 | + * the Free Software Foundation; either version 2 of the License, or | 145 | + * the Free Software Foundation; either version 2 of the License, or |
386 | + * (at your option) any later version. | 146 | + * (at your option) any later version. |
... | ... | ||
391 | + * GNU General Public License for more details. | 151 | + * GNU General Public License for more details. |
392 | + */ | 152 | + */ |
393 | + | 153 | + |
394 | +#include "qemu/osdep.h" | 154 | +#include "qemu/osdep.h" |
395 | +#include "qapi/error.h" | 155 | +#include "qapi/error.h" |
396 | +#include "qemu-common.h" | 156 | +#include "hw/misc/bcm2835_mphi.h" |
397 | +#include "hw/arm/fsl-imx6ul.h" | 157 | +#include "migration/vmstate.h" |
398 | +#include "hw/misc/unimp.h" | ||
399 | +#include "sysemu/sysemu.h" | ||
400 | +#include "qemu/error-report.h" | 158 | +#include "qemu/error-report.h" |
401 | + | 159 | +#include "qemu/log.h" |
402 | +#define NAME_SIZE 20 | 160 | +#include "qemu/main-loop.h" |
403 | + | 161 | + |
404 | +static void fsl_imx6ul_init(Object *obj) | 162 | +static inline void mphi_raise_irq(BCM2835MphiState *s) |
405 | +{ | 163 | +{ |
406 | + FslIMX6ULState *s = FSL_IMX6UL(obj); | 164 | + qemu_set_irq(s->irq, 1); |
407 | + char name[NAME_SIZE]; | 165 | +} |
408 | + int i; | 166 | + |
409 | + | 167 | +static inline void mphi_lower_irq(BCM2835MphiState *s) |
410 | + for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) { | 168 | +{ |
411 | + snprintf(name, NAME_SIZE, "cpu%d", i); | 169 | + qemu_set_irq(s->irq, 0); |
412 | + object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]), | 170 | +} |
413 | + "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL); | 171 | + |
414 | + } | 172 | +static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size) |
415 | + | 173 | +{ |
416 | + /* | 174 | + BCM2835MphiState *s = ptr; |
417 | + * A7MPCORE | 175 | + uint32_t val = 0; |
418 | + */ | 176 | + |
419 | + sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore), | 177 | + switch (addr) { |
420 | + TYPE_A15MPCORE_PRIV); | 178 | + case 0x28: /* outdda */ |
421 | + | 179 | + val = s->outdda; |
422 | + /* | 180 | + break; |
423 | + * CCM | 181 | + case 0x2c: /* outddb */ |
424 | + */ | 182 | + val = s->outddb; |
425 | + sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM); | 183 | + break; |
426 | + | 184 | + case 0x4c: /* ctrl */ |
427 | + /* | 185 | + val = s->ctrl; |
428 | + * SRC | 186 | + val |= 1 << 17; |
429 | + */ | 187 | + break; |
430 | + sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC); | 188 | + case 0x50: /* intstat */ |
431 | + | 189 | + val = s->intstat; |
432 | + /* | 190 | + break; |
433 | + * GPCv2 | 191 | + case 0x1f0: /* swirq_set */ |
434 | + */ | 192 | + val = s->swirq; |
435 | + sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2), | 193 | + break; |
436 | + TYPE_IMX_GPCV2); | 194 | + case 0x1f4: /* swirq_clr */ |
437 | + | 195 | + val = s->swirq; |
438 | + /* | 196 | + break; |
439 | + * SNVS | 197 | + default: |
440 | + */ | 198 | + qemu_log_mask(LOG_UNIMP, "read from unknown register"); |
441 | + sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs), | 199 | + break; |
442 | + TYPE_IMX7_SNVS); | 200 | + } |
443 | + | 201 | + |
444 | + /* | 202 | + return val; |
445 | + * GPR | 203 | +} |
446 | + */ | 204 | + |
447 | + sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), | 205 | +static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned size) |
448 | + TYPE_IMX7_GPR); | 206 | +{ |
449 | + | 207 | + BCM2835MphiState *s = ptr; |
450 | + /* | 208 | + int do_irq = 0; |
451 | + * GPIOs 1 to 5 | 209 | + |
452 | + */ | 210 | + switch (addr) { |
453 | + for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | 211 | + case 0x28: /* outdda */ |
454 | + snprintf(name, NAME_SIZE, "gpio%d", i); | 212 | + s->outdda = val; |
455 | + sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]), | 213 | + break; |
456 | + TYPE_IMX_GPIO); | 214 | + case 0x2c: /* outddb */ |
457 | + } | 215 | + s->outddb = val; |
458 | + | 216 | + if (val & (1 << 29)) { |
459 | + /* | 217 | + do_irq = 1; |
460 | + * GPT 1, 2 | 218 | + } |
461 | + */ | 219 | + break; |
462 | + for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | 220 | + case 0x4c: /* ctrl */ |
463 | + snprintf(name, NAME_SIZE, "gpt%d", i); | 221 | + s->ctrl = val; |
464 | + sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]), | 222 | + if (val & (1 << 16)) { |
465 | + TYPE_IMX7_GPT); | 223 | + do_irq = -1; |
466 | + } | 224 | + } |
467 | + | 225 | + break; |
468 | + /* | 226 | + case 0x50: /* intstat */ |
469 | + * EPIT 1, 2 | 227 | + s->intstat = val; |
470 | + */ | 228 | + if (val & ((1 << 16) | (1 << 29))) { |
471 | + for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | 229 | + do_irq = -1; |
472 | + snprintf(name, NAME_SIZE, "epit%d", i + 1); | 230 | + } |
473 | + sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]), | 231 | + break; |
474 | + TYPE_IMX_EPIT); | 232 | + case 0x1f0: /* swirq_set */ |
475 | + } | 233 | + s->swirq |= val; |
476 | + | 234 | + do_irq = 1; |
477 | + /* | 235 | + break; |
478 | + * eCSPI | 236 | + case 0x1f4: /* swirq_clr */ |
479 | + */ | 237 | + s->swirq &= ~val; |
480 | + for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | 238 | + do_irq = -1; |
481 | + snprintf(name, NAME_SIZE, "spi%d", i + 1); | 239 | + break; |
482 | + sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), | 240 | + default: |
483 | + TYPE_IMX_SPI); | 241 | + qemu_log_mask(LOG_UNIMP, "write to unknown register"); |
484 | + } | ||
485 | + | ||
486 | + /* | ||
487 | + * I2C | ||
488 | + */ | ||
489 | + for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
490 | + snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
491 | + sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]), | ||
492 | + TYPE_IMX_I2C); | ||
493 | + } | ||
494 | + | ||
495 | + /* | ||
496 | + * UART | ||
497 | + */ | ||
498 | + for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
499 | + snprintf(name, NAME_SIZE, "uart%d", i); | ||
500 | + sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]), | ||
501 | + TYPE_IMX_SERIAL); | ||
502 | + } | ||
503 | + | ||
504 | + /* | ||
505 | + * Ethernet | ||
506 | + */ | ||
507 | + for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { | ||
508 | + snprintf(name, NAME_SIZE, "eth%d", i); | ||
509 | + sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]), | ||
510 | + TYPE_IMX_ENET); | ||
511 | + } | ||
512 | + | ||
513 | + /* | ||
514 | + * SDHCI | ||
515 | + */ | ||
516 | + for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
517 | + snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
518 | + sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]), | ||
519 | + TYPE_IMX_USDHC); | ||
520 | + } | ||
521 | + | ||
522 | + /* | ||
523 | + * Watchdog | ||
524 | + */ | ||
525 | + for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
526 | + snprintf(name, NAME_SIZE, "wdt%d", i); | ||
527 | + sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]), | ||
528 | + TYPE_IMX2_WDT); | ||
529 | + } | ||
530 | +} | ||
531 | + | ||
532 | +static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
533 | +{ | ||
534 | + FslIMX6ULState *s = FSL_IMX6UL(dev); | ||
535 | + int i; | ||
536 | + qemu_irq irq; | ||
537 | + char name[NAME_SIZE]; | ||
538 | + | ||
539 | + if (smp_cpus > FSL_IMX6UL_NUM_CPUS) { | ||
540 | + error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", | ||
541 | + TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus); | ||
542 | + return; | 242 | + return; |
543 | + } | 243 | + } |
544 | + | 244 | + |
545 | + for (i = 0; i < smp_cpus; i++) { | 245 | + if (do_irq > 0) { |
546 | + Object *o = OBJECT(&s->cpu[i]); | 246 | + mphi_raise_irq(s); |
547 | + | 247 | + } else if (do_irq < 0) { |
548 | + object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC, | 248 | + mphi_lower_irq(s); |
549 | + "psci-conduit", &error_abort); | 249 | + } |
550 | + | 250 | +} |
551 | + /* On uniprocessor, the CBAR is set to 0 */ | 251 | + |
552 | + if (smp_cpus > 1) { | 252 | +static const MemoryRegionOps mphi_mmio_ops = { |
553 | + object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR, | 253 | + .read = mphi_reg_read, |
554 | + "reset-cbar", &error_abort); | 254 | + .write = mphi_reg_write, |
555 | + } | 255 | + .impl.min_access_size = 4, |
556 | + | 256 | + .impl.max_access_size = 4, |
557 | + if (i) { | 257 | + .endianness = DEVICE_LITTLE_ENDIAN, |
558 | + /* Secondary CPUs start in PSCI powered-down state */ | ||
559 | + object_property_set_bool(o, true, | ||
560 | + "start-powered-off", &error_abort); | ||
561 | + } | ||
562 | + | ||
563 | + object_property_set_bool(o, true, "realized", &error_abort); | ||
564 | + } | ||
565 | + | ||
566 | + /* | ||
567 | + * A7MPCORE | ||
568 | + */ | ||
569 | + object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu", | ||
570 | + &error_abort); | ||
571 | + object_property_set_int(OBJECT(&s->a7mpcore), | ||
572 | + FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, | ||
573 | + "num-irq", &error_abort); | ||
574 | + object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized", | ||
575 | + &error_abort); | ||
576 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); | ||
577 | + | ||
578 | + for (i = 0; i < smp_cpus; i++) { | ||
579 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); | ||
580 | + DeviceState *d = DEVICE(qemu_get_cpu(i)); | ||
581 | + | ||
582 | + irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | ||
583 | + sysbus_connect_irq(sbd, i, irq); | ||
584 | + sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ)); | ||
585 | + } | ||
586 | + | ||
587 | + /* | ||
588 | + * A7MPCORE DAP | ||
589 | + */ | ||
590 | + create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, | ||
591 | + 0x100000); | ||
592 | + | ||
593 | + /* | ||
594 | + * GPT 1, 2 | ||
595 | + */ | ||
596 | + for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
597 | + static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { | ||
598 | + FSL_IMX6UL_GPT1_ADDR, | ||
599 | + FSL_IMX6UL_GPT2_ADDR, | ||
600 | + }; | ||
601 | + | ||
602 | + static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = { | ||
603 | + FSL_IMX6UL_GPT1_IRQ, | ||
604 | + FSL_IMX6UL_GPT2_IRQ, | ||
605 | + }; | ||
606 | + | ||
607 | + s->gpt[i].ccm = IMX_CCM(&s->ccm); | ||
608 | + object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", | ||
609 | + &error_abort); | ||
610 | + | ||
611 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, | ||
612 | + FSL_IMX6UL_GPTn_ADDR[i]); | ||
613 | + | ||
614 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, | ||
615 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
616 | + FSL_IMX6UL_GPTn_IRQ[i])); | ||
617 | + } | ||
618 | + | ||
619 | + /* | ||
620 | + * EPIT 1, 2 | ||
621 | + */ | ||
622 | + for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
623 | + static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { | ||
624 | + FSL_IMX6UL_EPIT1_ADDR, | ||
625 | + FSL_IMX6UL_EPIT2_ADDR, | ||
626 | + }; | ||
627 | + | ||
628 | + static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = { | ||
629 | + FSL_IMX6UL_EPIT1_IRQ, | ||
630 | + FSL_IMX6UL_EPIT2_IRQ, | ||
631 | + }; | ||
632 | + | ||
633 | + s->epit[i].ccm = IMX_CCM(&s->ccm); | ||
634 | + object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", | ||
635 | + &error_abort); | ||
636 | + | ||
637 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, | ||
638 | + FSL_IMX6UL_EPITn_ADDR[i]); | ||
639 | + | ||
640 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, | ||
641 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
642 | + FSL_IMX6UL_EPITn_IRQ[i])); | ||
643 | + } | ||
644 | + | ||
645 | + /* | ||
646 | + * GPIO | ||
647 | + */ | ||
648 | + for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
649 | + static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { | ||
650 | + FSL_IMX6UL_GPIO1_ADDR, | ||
651 | + FSL_IMX6UL_GPIO2_ADDR, | ||
652 | + FSL_IMX6UL_GPIO3_ADDR, | ||
653 | + FSL_IMX6UL_GPIO4_ADDR, | ||
654 | + FSL_IMX6UL_GPIO5_ADDR, | ||
655 | + }; | ||
656 | + | ||
657 | + static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = { | ||
658 | + FSL_IMX6UL_GPIO1_LOW_IRQ, | ||
659 | + FSL_IMX6UL_GPIO2_LOW_IRQ, | ||
660 | + FSL_IMX6UL_GPIO3_LOW_IRQ, | ||
661 | + FSL_IMX6UL_GPIO4_LOW_IRQ, | ||
662 | + FSL_IMX6UL_GPIO5_LOW_IRQ, | ||
663 | + }; | ||
664 | + | ||
665 | + static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = { | ||
666 | + FSL_IMX6UL_GPIO1_HIGH_IRQ, | ||
667 | + FSL_IMX6UL_GPIO2_HIGH_IRQ, | ||
668 | + FSL_IMX6UL_GPIO3_HIGH_IRQ, | ||
669 | + FSL_IMX6UL_GPIO4_HIGH_IRQ, | ||
670 | + FSL_IMX6UL_GPIO5_HIGH_IRQ, | ||
671 | + }; | ||
672 | + | ||
673 | + object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", | ||
674 | + &error_abort); | ||
675 | + | ||
676 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, | ||
677 | + FSL_IMX6UL_GPIOn_ADDR[i]); | ||
678 | + | ||
679 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, | ||
680 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
681 | + FSL_IMX6UL_GPIOn_LOW_IRQ[i])); | ||
682 | + | ||
683 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, | ||
684 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
685 | + FSL_IMX6UL_GPIOn_HIGH_IRQ[i])); | ||
686 | + } | ||
687 | + | ||
688 | + /* | ||
689 | + * IOMUXC and IOMUXC_GPR | ||
690 | + */ | ||
691 | + for (i = 0; i < 1; i++) { | ||
692 | + static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { | ||
693 | + FSL_IMX6UL_IOMUXC_ADDR, | ||
694 | + FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
695 | + }; | ||
696 | + | ||
697 | + snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
698 | + create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); | ||
699 | + } | ||
700 | + | ||
701 | + /* | ||
702 | + * CCM | ||
703 | + */ | ||
704 | + object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort); | ||
705 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR); | ||
706 | + | ||
707 | + /* | ||
708 | + * SRC | ||
709 | + */ | ||
710 | + object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort); | ||
711 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR); | ||
712 | + | ||
713 | + /* | ||
714 | + * GPCv2 | ||
715 | + */ | ||
716 | + object_property_set_bool(OBJECT(&s->gpcv2), true, | ||
717 | + "realized", &error_abort); | ||
718 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); | ||
719 | + | ||
720 | + /* Initialize all ECSPI */ | ||
721 | + for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
722 | + static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { | ||
723 | + FSL_IMX6UL_ECSPI1_ADDR, | ||
724 | + FSL_IMX6UL_ECSPI2_ADDR, | ||
725 | + FSL_IMX6UL_ECSPI3_ADDR, | ||
726 | + FSL_IMX6UL_ECSPI4_ADDR, | ||
727 | + }; | ||
728 | + | ||
729 | + static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = { | ||
730 | + FSL_IMX6UL_ECSPI1_IRQ, | ||
731 | + FSL_IMX6UL_ECSPI2_IRQ, | ||
732 | + FSL_IMX6UL_ECSPI3_IRQ, | ||
733 | + FSL_IMX6UL_ECSPI4_IRQ, | ||
734 | + }; | ||
735 | + | ||
736 | + /* Initialize the SPI */ | ||
737 | + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", | ||
738 | + &error_abort); | ||
739 | + | ||
740 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, | ||
741 | + FSL_IMX6UL_SPIn_ADDR[i]); | ||
742 | + | ||
743 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, | ||
744 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
745 | + FSL_IMX6UL_SPIn_IRQ[i])); | ||
746 | + } | ||
747 | + | ||
748 | + /* | ||
749 | + * I2C | ||
750 | + */ | ||
751 | + for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
752 | + static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { | ||
753 | + FSL_IMX6UL_I2C1_ADDR, | ||
754 | + FSL_IMX6UL_I2C2_ADDR, | ||
755 | + FSL_IMX6UL_I2C3_ADDR, | ||
756 | + FSL_IMX6UL_I2C4_ADDR, | ||
757 | + }; | ||
758 | + | ||
759 | + static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = { | ||
760 | + FSL_IMX6UL_I2C1_IRQ, | ||
761 | + FSL_IMX6UL_I2C2_IRQ, | ||
762 | + FSL_IMX6UL_I2C3_IRQ, | ||
763 | + FSL_IMX6UL_I2C4_IRQ, | ||
764 | + }; | ||
765 | + | ||
766 | + object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", | ||
767 | + &error_abort); | ||
768 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); | ||
769 | + | ||
770 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, | ||
771 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
772 | + FSL_IMX6UL_I2Cn_IRQ[i])); | ||
773 | + } | ||
774 | + | ||
775 | + /* | ||
776 | + * UART | ||
777 | + */ | ||
778 | + for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
779 | + static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { | ||
780 | + FSL_IMX6UL_UART1_ADDR, | ||
781 | + FSL_IMX6UL_UART2_ADDR, | ||
782 | + FSL_IMX6UL_UART3_ADDR, | ||
783 | + FSL_IMX6UL_UART4_ADDR, | ||
784 | + FSL_IMX6UL_UART5_ADDR, | ||
785 | + FSL_IMX6UL_UART6_ADDR, | ||
786 | + FSL_IMX6UL_UART7_ADDR, | ||
787 | + FSL_IMX6UL_UART8_ADDR, | ||
788 | + }; | ||
789 | + | ||
790 | + static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = { | ||
791 | + FSL_IMX6UL_UART1_IRQ, | ||
792 | + FSL_IMX6UL_UART2_IRQ, | ||
793 | + FSL_IMX6UL_UART3_IRQ, | ||
794 | + FSL_IMX6UL_UART4_IRQ, | ||
795 | + FSL_IMX6UL_UART5_IRQ, | ||
796 | + FSL_IMX6UL_UART6_IRQ, | ||
797 | + FSL_IMX6UL_UART7_IRQ, | ||
798 | + FSL_IMX6UL_UART8_IRQ, | ||
799 | + }; | ||
800 | + | ||
801 | + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); | ||
802 | + | ||
803 | + object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", | ||
804 | + &error_abort); | ||
805 | + | ||
806 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, | ||
807 | + FSL_IMX6UL_UARTn_ADDR[i]); | ||
808 | + | ||
809 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, | ||
810 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
811 | + FSL_IMX6UL_UARTn_IRQ[i])); | ||
812 | + } | ||
813 | + | ||
814 | + /* | ||
815 | + * Ethernet | ||
816 | + */ | ||
817 | + for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { | ||
818 | + static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = { | ||
819 | + FSL_IMX6UL_ENET1_ADDR, | ||
820 | + FSL_IMX6UL_ENET2_ADDR, | ||
821 | + }; | ||
822 | + | ||
823 | + static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = { | ||
824 | + FSL_IMX6UL_ENET1_IRQ, | ||
825 | + FSL_IMX6UL_ENET2_IRQ, | ||
826 | + }; | ||
827 | + | ||
828 | + static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = { | ||
829 | + FSL_IMX6UL_ENET1_TIMER_IRQ, | ||
830 | + FSL_IMX6UL_ENET2_TIMER_IRQ, | ||
831 | + }; | ||
832 | + | ||
833 | + object_property_set_uint(OBJECT(&s->eth[i]), | ||
834 | + FSL_IMX6UL_ETH_NUM_TX_RINGS, | ||
835 | + "tx-ring-num", &error_abort); | ||
836 | + qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]); | ||
837 | + object_property_set_bool(OBJECT(&s->eth[i]), true, "realized", | ||
838 | + &error_abort); | ||
839 | + | ||
840 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, | ||
841 | + FSL_IMX6UL_ENETn_ADDR[i]); | ||
842 | + | ||
843 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, | ||
844 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
845 | + FSL_IMX6UL_ENETn_IRQ[i])); | ||
846 | + | ||
847 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, | ||
848 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
849 | + FSL_IMX6UL_ENETn_TIMER_IRQ[i])); | ||
850 | + } | ||
851 | + | ||
852 | + /* | ||
853 | + * USDHC | ||
854 | + */ | ||
855 | + for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
856 | + static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { | ||
857 | + FSL_IMX6UL_USDHC1_ADDR, | ||
858 | + FSL_IMX6UL_USDHC2_ADDR, | ||
859 | + }; | ||
860 | + | ||
861 | + static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = { | ||
862 | + FSL_IMX6UL_USDHC1_IRQ, | ||
863 | + FSL_IMX6UL_USDHC2_IRQ, | ||
864 | + }; | ||
865 | + | ||
866 | + object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized", | ||
867 | + &error_abort); | ||
868 | + | ||
869 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, | ||
870 | + FSL_IMX6UL_USDHCn_ADDR[i]); | ||
871 | + | ||
872 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, | ||
873 | + qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
874 | + FSL_IMX6UL_USDHCn_IRQ[i])); | ||
875 | + } | ||
876 | + | ||
877 | + /* | ||
878 | + * SNVS | ||
879 | + */ | ||
880 | + object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort); | ||
881 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); | ||
882 | + | ||
883 | + /* | ||
884 | + * Watchdog | ||
885 | + */ | ||
886 | + for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
887 | + static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { | ||
888 | + FSL_IMX6UL_WDOG1_ADDR, | ||
889 | + FSL_IMX6UL_WDOG2_ADDR, | ||
890 | + FSL_IMX6UL_WDOG3_ADDR, | ||
891 | + }; | ||
892 | + | ||
893 | + object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", | ||
894 | + &error_abort); | ||
895 | + | ||
896 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, | ||
897 | + FSL_IMX6UL_WDOGn_ADDR[i]); | ||
898 | + } | ||
899 | + | ||
900 | + /* | ||
901 | + * GPR | ||
902 | + */ | ||
903 | + object_property_set_bool(OBJECT(&s->gpr), true, "realized", | ||
904 | + &error_abort); | ||
905 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); | ||
906 | + | ||
907 | + /* | ||
908 | + * SDMA | ||
909 | + */ | ||
910 | + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); | ||
911 | + | ||
912 | + /* | ||
913 | + * APHB_DMA | ||
914 | + */ | ||
915 | + create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR, | ||
916 | + FSL_IMX6UL_APBH_DMA_SIZE); | ||
917 | + | ||
918 | + /* | ||
919 | + * ADCs | ||
920 | + */ | ||
921 | + for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) { | ||
922 | + static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = { | ||
923 | + FSL_IMX6UL_ADC1_ADDR, | ||
924 | + FSL_IMX6UL_ADC2_ADDR, | ||
925 | + }; | ||
926 | + | ||
927 | + snprintf(name, NAME_SIZE, "adc%d", i); | ||
928 | + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); | ||
929 | + } | ||
930 | + | ||
931 | + /* | ||
932 | + * LCD | ||
933 | + */ | ||
934 | + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); | ||
935 | + | ||
936 | + /* | ||
937 | + * ROM memory | ||
938 | + */ | ||
939 | + memory_region_init_rom(&s->rom, NULL, "imx6ul.rom", | ||
940 | + FSL_IMX6UL_ROM_SIZE, &error_abort); | ||
941 | + memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR, | ||
942 | + &s->rom); | ||
943 | + | ||
944 | + /* | ||
945 | + * CAAM memory | ||
946 | + */ | ||
947 | + memory_region_init_rom(&s->caam, NULL, "imx6ul.caam", | ||
948 | + FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort); | ||
949 | + memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR, | ||
950 | + &s->caam); | ||
951 | + | ||
952 | + /* | ||
953 | + * OCRAM memory | ||
954 | + */ | ||
955 | + memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram", | ||
956 | + FSL_IMX6UL_OCRAM_MEM_SIZE, | ||
957 | + &error_abort); | ||
958 | + memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR, | ||
959 | + &s->ocram); | ||
960 | + | ||
961 | + /* | ||
962 | + * internal OCRAM (128 KB) is aliased over 512 KB | ||
963 | + */ | ||
964 | + memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias", | ||
965 | + &s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE); | ||
966 | + memory_region_add_subregion(get_system_memory(), | ||
967 | + FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias); | ||
968 | +} | ||
969 | + | ||
970 | +static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) | ||
971 | +{ | ||
972 | + DeviceClass *dc = DEVICE_CLASS(oc); | ||
973 | + | ||
974 | + dc->realize = fsl_imx6ul_realize; | ||
975 | + dc->desc = "i.MX6UL SOC"; | ||
976 | + /* Reason: Uses serial_hds and nd_table in realize() directly */ | ||
977 | + dc->user_creatable = false; | ||
978 | +} | ||
979 | + | ||
980 | +static const TypeInfo fsl_imx6ul_type_info = { | ||
981 | + .name = TYPE_FSL_IMX6UL, | ||
982 | + .parent = TYPE_DEVICE, | ||
983 | + .instance_size = sizeof(FslIMX6ULState), | ||
984 | + .instance_init = fsl_imx6ul_init, | ||
985 | + .class_init = fsl_imx6ul_class_init, | ||
986 | +}; | 258 | +}; |
987 | + | 259 | + |
988 | +static void fsl_imx6ul_register_types(void) | 260 | +static void mphi_reset(DeviceState *dev) |
989 | +{ | 261 | +{ |
990 | + type_register_static(&fsl_imx6ul_type_info); | 262 | + BCM2835MphiState *s = BCM2835_MPHI(dev); |
991 | +} | 263 | + |
992 | +type_init(fsl_imx6ul_register_types) | 264 | + s->outdda = 0; |
993 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | 265 | + s->outddb = 0; |
266 | + s->ctrl = 0; | ||
267 | + s->intstat = 0; | ||
268 | + s->swirq = 0; | ||
269 | +} | ||
270 | + | ||
271 | +static void mphi_realize(DeviceState *dev, Error **errp) | ||
272 | +{ | ||
273 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
274 | + BCM2835MphiState *s = BCM2835_MPHI(dev); | ||
275 | + | ||
276 | + sysbus_init_irq(sbd, &s->irq); | ||
277 | +} | ||
278 | + | ||
279 | +static void mphi_init(Object *obj) | ||
280 | +{ | ||
281 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
282 | + BCM2835MphiState *s = BCM2835_MPHI(obj); | ||
283 | + | ||
284 | + memory_region_init_io(&s->iomem, obj, &mphi_mmio_ops, s, "mphi", MPHI_MMIO_SIZE); | ||
285 | + sysbus_init_mmio(sbd, &s->iomem); | ||
286 | +} | ||
287 | + | ||
288 | +const VMStateDescription vmstate_mphi_state = { | ||
289 | + .name = "mphi", | ||
290 | + .version_id = 1, | ||
291 | + .minimum_version_id = 1, | ||
292 | + .fields = (VMStateField[]) { | ||
293 | + VMSTATE_UINT32(outdda, BCM2835MphiState), | ||
294 | + VMSTATE_UINT32(outddb, BCM2835MphiState), | ||
295 | + VMSTATE_UINT32(ctrl, BCM2835MphiState), | ||
296 | + VMSTATE_UINT32(intstat, BCM2835MphiState), | ||
297 | + VMSTATE_UINT32(swirq, BCM2835MphiState), | ||
298 | + VMSTATE_END_OF_LIST() | ||
299 | + } | ||
300 | +}; | ||
301 | + | ||
302 | +static void mphi_class_init(ObjectClass *klass, void *data) | ||
303 | +{ | ||
304 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
305 | + | ||
306 | + dc->realize = mphi_realize; | ||
307 | + dc->reset = mphi_reset; | ||
308 | + dc->vmsd = &vmstate_mphi_state; | ||
309 | +} | ||
310 | + | ||
311 | +static const TypeInfo bcm2835_mphi_type_info = { | ||
312 | + .name = TYPE_BCM2835_MPHI, | ||
313 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
314 | + .instance_size = sizeof(BCM2835MphiState), | ||
315 | + .instance_init = mphi_init, | ||
316 | + .class_init = mphi_class_init, | ||
317 | +}; | ||
318 | + | ||
319 | +static void bcm2835_mphi_register_types(void) | ||
320 | +{ | ||
321 | + type_register_static(&bcm2835_mphi_type_info); | ||
322 | +} | ||
323 | + | ||
324 | +type_init(bcm2835_mphi_register_types) | ||
325 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | ||
994 | index XXXXXXX..XXXXXXX 100644 | 326 | index XXXXXXX..XXXXXXX 100644 |
995 | --- a/default-configs/arm-softmmu.mak | 327 | --- a/hw/misc/Makefile.objs |
996 | +++ b/default-configs/arm-softmmu.mak | 328 | +++ b/hw/misc/Makefile.objs |
997 | @@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX6=y | 329 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_OMAP) += omap_l4.o |
998 | CONFIG_FSL_IMX31=y | 330 | common-obj-$(CONFIG_OMAP) += omap_sdrc.o |
999 | CONFIG_FSL_IMX25=y | 331 | common-obj-$(CONFIG_OMAP) += omap_tap.o |
1000 | CONFIG_FSL_IMX7=y | 332 | common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o |
1001 | +CONFIG_FSL_IMX6UL=y | 333 | +common-obj-$(CONFIG_RASPI) += bcm2835_mphi.o |
1002 | 334 | common-obj-$(CONFIG_RASPI) += bcm2835_property.o | |
1003 | CONFIG_IMX_I2C=y | 335 | common-obj-$(CONFIG_RASPI) += bcm2835_rng.o |
1004 | 336 | common-obj-$(CONFIG_RASPI) += bcm2835_thermal.o | |
1005 | -- | 337 | -- |
1006 | 2.18.0 | 338 | 2.20.1 |
1007 | 339 | ||
1008 | 340 | diff view generated by jsdifflib |
1 | From: Su Hang <suhang16@mails.ucas.ac.cn> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | 'test.hex' file is a memory test pattern stored in Hexadecimal Object | 3 | Import the dwc-hsotg (dwc2) register definitions file from the |
4 | Format. It loads at 0x10000 in RAM and contains values from 0 through | 4 | Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the |
5 | 255. | 5 | mainline Linux kernel, the only changes being to the header, and |
6 | two instances of 'u32' changed to 'uint32_t' to allow it to | ||
7 | compile. Checkpatch throws a boatload of errors due to the tab | ||
8 | indentation, but I would rather import it as-is than reformat it. | ||
6 | 9 | ||
7 | The test case verifies that the expected memory test pattern was loaded. | 10 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> |
8 | 11 | Message-id: 20200520235349.21215-3-pauldzim@gmail.com | |
9 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | 12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Suggested-by: Steffen Gortz <qemu.ml@steffen-goertz.de> | ||
11 | Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
12 | Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn> | ||
13 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | [PMM: changed qtest_startf() to qtest_initf() to work with | ||
16 | current master after the refactoring in commit 88b988c895e3c2] | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 14 | --- |
19 | configure | 4 +++ | 15 | include/hw/usb/dwc2-regs.h | 899 +++++++++++++++++++++++++++++++++++++ |
20 | tests/Makefile.include | 2 ++ | 16 | 1 file changed, 899 insertions(+) |
21 | tests/hexloader-test.c | 45 ++++++++++++++++++++++++++++ | 17 | create mode 100644 include/hw/usb/dwc2-regs.h |
22 | MAINTAINERS | 6 ++++ | ||
23 | tests/hex-loader-check-data/test.hex | 18 +++++++++++ | ||
24 | 5 files changed, 75 insertions(+) | ||
25 | create mode 100644 tests/hexloader-test.c | ||
26 | create mode 100644 tests/hex-loader-check-data/test.hex | ||
27 | 18 | ||
28 | diff --git a/configure b/configure | 19 | diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h |
29 | index XXXXXXX..XXXXXXX 100755 | ||
30 | --- a/configure | ||
31 | +++ b/configure | ||
32 | @@ -XXX,XX +XXX,XX @@ for test_file in $(find $source_path/tests/acpi-test-data -type f) | ||
33 | do | ||
34 | FILES="$FILES tests/acpi-test-data$(echo $test_file | sed -e 's/.*acpi-test-data//')" | ||
35 | done | ||
36 | +for test_file in $(find $source_path/tests/hex-loader-check-data -type f) | ||
37 | +do | ||
38 | + FILES="$FILES tests/hex-loader-check-data$(echo $test_file | sed -e 's/.*hex-loader-check-data//')" | ||
39 | +done | ||
40 | mkdir -p $DIRS | ||
41 | for f in $FILES ; do | ||
42 | if [ -e "$source_path/$f" ] && [ "$pwd_is_source_path" != "y" ]; then | ||
43 | diff --git a/tests/Makefile.include b/tests/Makefile.include | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/tests/Makefile.include | ||
46 | +++ b/tests/Makefile.include | ||
47 | @@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF) | ||
48 | gcov-files-arm-y += hw/timer/arm_mptimer.c | ||
49 | check-qtest-arm-y += tests/boot-serial-test$(EXESUF) | ||
50 | check-qtest-arm-y += tests/sdhci-test$(EXESUF) | ||
51 | +check-qtest-arm-y += tests/hexloader-test$(EXESUF) | ||
52 | |||
53 | check-qtest-aarch64-y = tests/numa-test$(EXESUF) | ||
54 | check-qtest-aarch64-y += tests/sdhci-test$(EXESUF) | ||
55 | @@ -XXX,XX +XXX,XX @@ tests/qmp-test$(EXESUF): tests/qmp-test.o | ||
56 | tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o | ||
57 | tests/rtc-test$(EXESUF): tests/rtc-test.o | ||
58 | tests/m48t59-test$(EXESUF): tests/m48t59-test.o | ||
59 | +tests/hexloader-test$(EXESUF): tests/hexloader-test.o | ||
60 | tests/endianness-test$(EXESUF): tests/endianness-test.o | ||
61 | tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) | ||
62 | tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y) | ||
63 | diff --git a/tests/hexloader-test.c b/tests/hexloader-test.c | ||
64 | new file mode 100644 | 20 | new file mode 100644 |
65 | index XXXXXXX..XXXXXXX | 21 | index XXXXXXX..XXXXXXX |
66 | --- /dev/null | 22 | --- /dev/null |
67 | +++ b/tests/hexloader-test.c | 23 | +++ b/include/hw/usb/dwc2-regs.h |
68 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
25 | +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ | ||
69 | +/* | 26 | +/* |
70 | + * QTest testcase for the Intel Hexadecimal Object File Loader | 27 | + * Imported from the Linux kernel file drivers/usb/dwc2/hw.h, commit |
28 | + * a89bae709b3492b478480a2c9734e7e9393b279c ("usb: dwc2: Move | ||
29 | + * UTMI_PHY_DATA defines closer") | ||
71 | + * | 30 | + * |
72 | + * Authors: | 31 | + * hw.h - DesignWare HS OTG Controller hardware definitions |
73 | + * Su Hang <suhang16@mails.ucas.ac.cn> 2018 | ||
74 | + * | 32 | + * |
75 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 33 | + * Copyright 2004-2013 Synopsys, Inc. |
76 | + * See the COPYING file in the top-level directory. | ||
77 | + * | 34 | + * |
35 | + * Redistribution and use in source and binary forms, with or without | ||
36 | + * modification, are permitted provided that the following conditions | ||
37 | + * are met: | ||
38 | + * 1. Redistributions of source code must retain the above copyright | ||
39 | + * notice, this list of conditions, and the following disclaimer, | ||
40 | + * without modification. | ||
41 | + * 2. Redistributions in binary form must reproduce the above copyright | ||
42 | + * notice, this list of conditions and the following disclaimer in the | ||
43 | + * documentation and/or other materials provided with the distribution. | ||
44 | + * 3. The names of the above-listed copyright holders may not be used | ||
45 | + * to endorse or promote products derived from this software without | ||
46 | + * specific prior written permission. | ||
47 | + * | ||
48 | + * ALTERNATIVELY, this software may be distributed under the terms of the | ||
49 | + * GNU General Public License ("GPL") as published by the Free Software | ||
50 | + * Foundation; either version 2 of the License, or (at your option) any | ||
51 | + * later version. | ||
52 | + * | ||
53 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | ||
54 | + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | ||
55 | + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | ||
56 | + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | ||
57 | + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | ||
58 | + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | ||
59 | + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | ||
60 | + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | ||
61 | + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | ||
62 | + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | ||
63 | + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
78 | + */ | 64 | + */ |
79 | + | 65 | + |
80 | +#include "qemu/osdep.h" | 66 | +#ifndef __DWC2_HW_H__ |
81 | +#include "libqtest.h" | 67 | +#define __DWC2_HW_H__ |
82 | + | 68 | + |
83 | +/* Load 'test.hex' and verify that the in-memory contents are as expected. | 69 | +#define HSOTG_REG(x) (x) |
84 | + * 'test.hex' is a memory test pattern stored in Hexadecimal Object | 70 | + |
85 | + * format. It loads at 0x10000 in RAM and contains values from 0 through | 71 | +#define GOTGCTL HSOTG_REG(0x000) |
86 | + * 255. | 72 | +#define GOTGCTL_CHIRPEN BIT(27) |
73 | +#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) | ||
74 | +#define GOTGCTL_MULT_VALID_BC_SHIFT 22 | ||
75 | +#define GOTGCTL_OTGVER BIT(20) | ||
76 | +#define GOTGCTL_BSESVLD BIT(19) | ||
77 | +#define GOTGCTL_ASESVLD BIT(18) | ||
78 | +#define GOTGCTL_DBNC_SHORT BIT(17) | ||
79 | +#define GOTGCTL_CONID_B BIT(16) | ||
80 | +#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15) | ||
81 | +#define GOTGCTL_DEVHNPEN BIT(11) | ||
82 | +#define GOTGCTL_HSTSETHNPEN BIT(10) | ||
83 | +#define GOTGCTL_HNPREQ BIT(9) | ||
84 | +#define GOTGCTL_HSTNEGSCS BIT(8) | ||
85 | +#define GOTGCTL_SESREQ BIT(1) | ||
86 | +#define GOTGCTL_SESREQSCS BIT(0) | ||
87 | + | ||
88 | +#define GOTGINT HSOTG_REG(0x004) | ||
89 | +#define GOTGINT_DBNCE_DONE BIT(19) | ||
90 | +#define GOTGINT_A_DEV_TOUT_CHG BIT(18) | ||
91 | +#define GOTGINT_HST_NEG_DET BIT(17) | ||
92 | +#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9) | ||
93 | +#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8) | ||
94 | +#define GOTGINT_SES_END_DET BIT(2) | ||
95 | + | ||
96 | +#define GAHBCFG HSOTG_REG(0x008) | ||
97 | +#define GAHBCFG_AHB_SINGLE BIT(23) | ||
98 | +#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22) | ||
99 | +#define GAHBCFG_REM_MEM_SUPP BIT(21) | ||
100 | +#define GAHBCFG_P_TXF_EMP_LVL BIT(8) | ||
101 | +#define GAHBCFG_NP_TXF_EMP_LVL BIT(7) | ||
102 | +#define GAHBCFG_DMA_EN BIT(5) | ||
103 | +#define GAHBCFG_HBSTLEN_MASK (0xf << 1) | ||
104 | +#define GAHBCFG_HBSTLEN_SHIFT 1 | ||
105 | +#define GAHBCFG_HBSTLEN_SINGLE 0 | ||
106 | +#define GAHBCFG_HBSTLEN_INCR 1 | ||
107 | +#define GAHBCFG_HBSTLEN_INCR4 3 | ||
108 | +#define GAHBCFG_HBSTLEN_INCR8 5 | ||
109 | +#define GAHBCFG_HBSTLEN_INCR16 7 | ||
110 | +#define GAHBCFG_GLBL_INTR_EN BIT(0) | ||
111 | +#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ | ||
112 | + GAHBCFG_NP_TXF_EMP_LVL | \ | ||
113 | + GAHBCFG_DMA_EN | \ | ||
114 | + GAHBCFG_GLBL_INTR_EN) | ||
115 | + | ||
116 | +#define GUSBCFG HSOTG_REG(0x00C) | ||
117 | +#define GUSBCFG_FORCEDEVMODE BIT(30) | ||
118 | +#define GUSBCFG_FORCEHOSTMODE BIT(29) | ||
119 | +#define GUSBCFG_TXENDDELAY BIT(28) | ||
120 | +#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27) | ||
121 | +#define GUSBCFG_ICUSBCAP BIT(26) | ||
122 | +#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) | ||
123 | +#define GUSBCFG_INDICATORPASSTHROUGH BIT(24) | ||
124 | +#define GUSBCFG_INDICATORCOMPLEMENT BIT(23) | ||
125 | +#define GUSBCFG_TERMSELDLPULSE BIT(22) | ||
126 | +#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21) | ||
127 | +#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) | ||
128 | +#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19) | ||
129 | +#define GUSBCFG_ULPI_AUTO_RES BIT(18) | ||
130 | +#define GUSBCFG_ULPI_FS_LS BIT(17) | ||
131 | +#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16) | ||
132 | +#define GUSBCFG_PHY_LP_CLK_SEL BIT(15) | ||
133 | +#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) | ||
134 | +#define GUSBCFG_USBTRDTIM_SHIFT 10 | ||
135 | +#define GUSBCFG_HNPCAP BIT(9) | ||
136 | +#define GUSBCFG_SRPCAP BIT(8) | ||
137 | +#define GUSBCFG_DDRSEL BIT(7) | ||
138 | +#define GUSBCFG_PHYSEL BIT(6) | ||
139 | +#define GUSBCFG_FSINTF BIT(5) | ||
140 | +#define GUSBCFG_ULPI_UTMI_SEL BIT(4) | ||
141 | +#define GUSBCFG_PHYIF16 BIT(3) | ||
142 | +#define GUSBCFG_PHYIF8 (0 << 3) | ||
143 | +#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) | ||
144 | +#define GUSBCFG_TOUTCAL_SHIFT 0 | ||
145 | +#define GUSBCFG_TOUTCAL_LIMIT 0x7 | ||
146 | +#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) | ||
147 | + | ||
148 | +#define GRSTCTL HSOTG_REG(0x010) | ||
149 | +#define GRSTCTL_AHBIDLE BIT(31) | ||
150 | +#define GRSTCTL_DMAREQ BIT(30) | ||
151 | +#define GRSTCTL_TXFNUM_MASK (0x1f << 6) | ||
152 | +#define GRSTCTL_TXFNUM_SHIFT 6 | ||
153 | +#define GRSTCTL_TXFNUM_LIMIT 0x1f | ||
154 | +#define GRSTCTL_TXFNUM(_x) ((_x) << 6) | ||
155 | +#define GRSTCTL_TXFFLSH BIT(5) | ||
156 | +#define GRSTCTL_RXFFLSH BIT(4) | ||
157 | +#define GRSTCTL_IN_TKNQ_FLSH BIT(3) | ||
158 | +#define GRSTCTL_FRMCNTRRST BIT(2) | ||
159 | +#define GRSTCTL_HSFTRST BIT(1) | ||
160 | +#define GRSTCTL_CSFTRST BIT(0) | ||
161 | + | ||
162 | +#define GINTSTS HSOTG_REG(0x014) | ||
163 | +#define GINTMSK HSOTG_REG(0x018) | ||
164 | +#define GINTSTS_WKUPINT BIT(31) | ||
165 | +#define GINTSTS_SESSREQINT BIT(30) | ||
166 | +#define GINTSTS_DISCONNINT BIT(29) | ||
167 | +#define GINTSTS_CONIDSTSCHNG BIT(28) | ||
168 | +#define GINTSTS_LPMTRANRCVD BIT(27) | ||
169 | +#define GINTSTS_PTXFEMP BIT(26) | ||
170 | +#define GINTSTS_HCHINT BIT(25) | ||
171 | +#define GINTSTS_PRTINT BIT(24) | ||
172 | +#define GINTSTS_RESETDET BIT(23) | ||
173 | +#define GINTSTS_FET_SUSP BIT(22) | ||
174 | +#define GINTSTS_INCOMPL_IP BIT(21) | ||
175 | +#define GINTSTS_INCOMPL_SOOUT BIT(21) | ||
176 | +#define GINTSTS_INCOMPL_SOIN BIT(20) | ||
177 | +#define GINTSTS_OEPINT BIT(19) | ||
178 | +#define GINTSTS_IEPINT BIT(18) | ||
179 | +#define GINTSTS_EPMIS BIT(17) | ||
180 | +#define GINTSTS_RESTOREDONE BIT(16) | ||
181 | +#define GINTSTS_EOPF BIT(15) | ||
182 | +#define GINTSTS_ISOUTDROP BIT(14) | ||
183 | +#define GINTSTS_ENUMDONE BIT(13) | ||
184 | +#define GINTSTS_USBRST BIT(12) | ||
185 | +#define GINTSTS_USBSUSP BIT(11) | ||
186 | +#define GINTSTS_ERLYSUSP BIT(10) | ||
187 | +#define GINTSTS_I2CINT BIT(9) | ||
188 | +#define GINTSTS_ULPI_CK_INT BIT(8) | ||
189 | +#define GINTSTS_GOUTNAKEFF BIT(7) | ||
190 | +#define GINTSTS_GINNAKEFF BIT(6) | ||
191 | +#define GINTSTS_NPTXFEMP BIT(5) | ||
192 | +#define GINTSTS_RXFLVL BIT(4) | ||
193 | +#define GINTSTS_SOF BIT(3) | ||
194 | +#define GINTSTS_OTGINT BIT(2) | ||
195 | +#define GINTSTS_MODEMIS BIT(1) | ||
196 | +#define GINTSTS_CURMODE_HOST BIT(0) | ||
197 | + | ||
198 | +#define GRXSTSR HSOTG_REG(0x01C) | ||
199 | +#define GRXSTSP HSOTG_REG(0x020) | ||
200 | +#define GRXSTS_FN_MASK (0x7f << 25) | ||
201 | +#define GRXSTS_FN_SHIFT 25 | ||
202 | +#define GRXSTS_PKTSTS_MASK (0xf << 17) | ||
203 | +#define GRXSTS_PKTSTS_SHIFT 17 | ||
204 | +#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 | ||
205 | +#define GRXSTS_PKTSTS_OUTRX 2 | ||
206 | +#define GRXSTS_PKTSTS_HCHIN 2 | ||
207 | +#define GRXSTS_PKTSTS_OUTDONE 3 | ||
208 | +#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 | ||
209 | +#define GRXSTS_PKTSTS_SETUPDONE 4 | ||
210 | +#define GRXSTS_PKTSTS_DATATOGGLEERR 5 | ||
211 | +#define GRXSTS_PKTSTS_SETUPRX 6 | ||
212 | +#define GRXSTS_PKTSTS_HCHHALTED 7 | ||
213 | +#define GRXSTS_HCHNUM_MASK (0xf << 0) | ||
214 | +#define GRXSTS_HCHNUM_SHIFT 0 | ||
215 | +#define GRXSTS_DPID_MASK (0x3 << 15) | ||
216 | +#define GRXSTS_DPID_SHIFT 15 | ||
217 | +#define GRXSTS_BYTECNT_MASK (0x7ff << 4) | ||
218 | +#define GRXSTS_BYTECNT_SHIFT 4 | ||
219 | +#define GRXSTS_EPNUM_MASK (0xf << 0) | ||
220 | +#define GRXSTS_EPNUM_SHIFT 0 | ||
221 | + | ||
222 | +#define GRXFSIZ HSOTG_REG(0x024) | ||
223 | +#define GRXFSIZ_DEPTH_MASK (0xffff << 0) | ||
224 | +#define GRXFSIZ_DEPTH_SHIFT 0 | ||
225 | + | ||
226 | +#define GNPTXFSIZ HSOTG_REG(0x028) | ||
227 | +/* Use FIFOSIZE_* constants to access this register */ | ||
228 | + | ||
229 | +#define GNPTXSTS HSOTG_REG(0x02C) | ||
230 | +#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) | ||
231 | +#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 | ||
232 | +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) | ||
233 | +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 | ||
234 | +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) | ||
235 | +#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) | ||
236 | +#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 | ||
237 | +#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) | ||
238 | + | ||
239 | +#define GI2CCTL HSOTG_REG(0x0030) | ||
240 | +#define GI2CCTL_BSYDNE BIT(31) | ||
241 | +#define GI2CCTL_RW BIT(30) | ||
242 | +#define GI2CCTL_I2CDATSE0 BIT(28) | ||
243 | +#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) | ||
244 | +#define GI2CCTL_I2CDEVADDR_SHIFT 26 | ||
245 | +#define GI2CCTL_I2CSUSPCTL BIT(25) | ||
246 | +#define GI2CCTL_ACK BIT(24) | ||
247 | +#define GI2CCTL_I2CEN BIT(23) | ||
248 | +#define GI2CCTL_ADDR_MASK (0x7f << 16) | ||
249 | +#define GI2CCTL_ADDR_SHIFT 16 | ||
250 | +#define GI2CCTL_REGADDR_MASK (0xff << 8) | ||
251 | +#define GI2CCTL_REGADDR_SHIFT 8 | ||
252 | +#define GI2CCTL_RWDATA_MASK (0xff << 0) | ||
253 | +#define GI2CCTL_RWDATA_SHIFT 0 | ||
254 | + | ||
255 | +#define GPVNDCTL HSOTG_REG(0x0034) | ||
256 | +#define GGPIO HSOTG_REG(0x0038) | ||
257 | +#define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16) | ||
258 | + | ||
259 | +#define GUID HSOTG_REG(0x003c) | ||
260 | +#define GSNPSID HSOTG_REG(0x0040) | ||
261 | +#define GHWCFG1 HSOTG_REG(0x0044) | ||
262 | +#define GSNPSID_ID_MASK GENMASK(31, 16) | ||
263 | + | ||
264 | +#define GHWCFG2 HSOTG_REG(0x0048) | ||
265 | +#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31) | ||
266 | +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) | ||
267 | +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 | ||
268 | +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) | ||
269 | +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 | ||
270 | +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) | ||
271 | +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 | ||
272 | +#define GHWCFG2_MULTI_PROC_INT BIT(20) | ||
273 | +#define GHWCFG2_DYNAMIC_FIFO BIT(19) | ||
274 | +#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18) | ||
275 | +#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) | ||
276 | +#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 | ||
277 | +#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) | ||
278 | +#define GHWCFG2_NUM_DEV_EP_SHIFT 10 | ||
279 | +#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) | ||
280 | +#define GHWCFG2_FS_PHY_TYPE_SHIFT 8 | ||
281 | +#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 | ||
282 | +#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 | ||
283 | +#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 | ||
284 | +#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 | ||
285 | +#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) | ||
286 | +#define GHWCFG2_HS_PHY_TYPE_SHIFT 6 | ||
287 | +#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 | ||
288 | +#define GHWCFG2_HS_PHY_TYPE_UTMI 1 | ||
289 | +#define GHWCFG2_HS_PHY_TYPE_ULPI 2 | ||
290 | +#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 | ||
291 | +#define GHWCFG2_POINT2POINT BIT(5) | ||
292 | +#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) | ||
293 | +#define GHWCFG2_ARCHITECTURE_SHIFT 3 | ||
294 | +#define GHWCFG2_SLAVE_ONLY_ARCH 0 | ||
295 | +#define GHWCFG2_EXT_DMA_ARCH 1 | ||
296 | +#define GHWCFG2_INT_DMA_ARCH 2 | ||
297 | +#define GHWCFG2_OP_MODE_MASK (0x7 << 0) | ||
298 | +#define GHWCFG2_OP_MODE_SHIFT 0 | ||
299 | +#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 | ||
300 | +#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 | ||
301 | +#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 | ||
302 | +#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 | ||
303 | +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 | ||
304 | +#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 | ||
305 | +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 | ||
306 | +#define GHWCFG2_OP_MODE_UNDEFINED 7 | ||
307 | + | ||
308 | +#define GHWCFG3 HSOTG_REG(0x004c) | ||
309 | +#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) | ||
310 | +#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 | ||
311 | +#define GHWCFG3_OTG_LPM_EN BIT(15) | ||
312 | +#define GHWCFG3_BC_SUPPORT BIT(14) | ||
313 | +#define GHWCFG3_OTG_ENABLE_HSIC BIT(13) | ||
314 | +#define GHWCFG3_ADP_SUPP BIT(12) | ||
315 | +#define GHWCFG3_SYNCH_RESET_TYPE BIT(11) | ||
316 | +#define GHWCFG3_OPTIONAL_FEATURES BIT(10) | ||
317 | +#define GHWCFG3_VENDOR_CTRL_IF BIT(9) | ||
318 | +#define GHWCFG3_I2C BIT(8) | ||
319 | +#define GHWCFG3_OTG_FUNC BIT(7) | ||
320 | +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) | ||
321 | +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 | ||
322 | +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) | ||
323 | +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 | ||
324 | + | ||
325 | +#define GHWCFG4 HSOTG_REG(0x0050) | ||
326 | +#define GHWCFG4_DESC_DMA_DYN BIT(31) | ||
327 | +#define GHWCFG4_DESC_DMA BIT(30) | ||
328 | +#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) | ||
329 | +#define GHWCFG4_NUM_IN_EPS_SHIFT 26 | ||
330 | +#define GHWCFG4_DED_FIFO_EN BIT(25) | ||
331 | +#define GHWCFG4_DED_FIFO_SHIFT 25 | ||
332 | +#define GHWCFG4_SESSION_END_FILT_EN BIT(24) | ||
333 | +#define GHWCFG4_B_VALID_FILT_EN BIT(23) | ||
334 | +#define GHWCFG4_A_VALID_FILT_EN BIT(22) | ||
335 | +#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) | ||
336 | +#define GHWCFG4_IDDIG_FILT_EN BIT(20) | ||
337 | +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) | ||
338 | +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 | ||
339 | +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) | ||
340 | +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 | ||
341 | +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 | ||
342 | +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 | ||
343 | +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 | ||
344 | +#define GHWCFG4_ACG_SUPPORTED BIT(12) | ||
345 | +#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) | ||
346 | +#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) | ||
347 | +#define GHWCFG4_XHIBER BIT(7) | ||
348 | +#define GHWCFG4_HIBER BIT(6) | ||
349 | +#define GHWCFG4_MIN_AHB_FREQ BIT(5) | ||
350 | +#define GHWCFG4_POWER_OPTIMIZ BIT(4) | ||
351 | +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) | ||
352 | +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 | ||
353 | + | ||
354 | +#define GLPMCFG HSOTG_REG(0x0054) | ||
355 | +#define GLPMCFG_INVSELHSIC BIT(31) | ||
356 | +#define GLPMCFG_HSICCON BIT(30) | ||
357 | +#define GLPMCFG_RSTRSLPSTS BIT(29) | ||
358 | +#define GLPMCFG_ENBESL BIT(28) | ||
359 | +#define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25) | ||
360 | +#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25 | ||
361 | +#define GLPMCFG_SNDLPM BIT(24) | ||
362 | +#define GLPMCFG_RETRY_CNT_MASK (0x7 << 21) | ||
363 | +#define GLPMCFG_RETRY_CNT_SHIFT 21 | ||
364 | +#define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21) | ||
365 | +#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22) | ||
366 | +#define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17) | ||
367 | +#define GLPMCFG_LPM_CHNL_INDX_SHIFT 17 | ||
368 | +#define GLPMCFG_L1RESUMEOK BIT(16) | ||
369 | +#define GLPMCFG_SLPSTS BIT(15) | ||
370 | +#define GLPMCFG_COREL1RES_MASK (0x3 << 13) | ||
371 | +#define GLPMCFG_COREL1RES_SHIFT 13 | ||
372 | +#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) | ||
373 | +#define GLPMCFG_HIRD_THRES_SHIFT 8 | ||
374 | +#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) | ||
375 | +#define GLPMCFG_ENBLSLPM BIT(7) | ||
376 | +#define GLPMCFG_BREMOTEWAKE BIT(6) | ||
377 | +#define GLPMCFG_HIRD_MASK (0xf << 2) | ||
378 | +#define GLPMCFG_HIRD_SHIFT 2 | ||
379 | +#define GLPMCFG_APPL1RES BIT(1) | ||
380 | +#define GLPMCFG_LPMCAP BIT(0) | ||
381 | + | ||
382 | +#define GPWRDN HSOTG_REG(0x0058) | ||
383 | +#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) | ||
384 | +#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 | ||
385 | +#define GPWRDN_ADP_INT BIT(23) | ||
386 | +#define GPWRDN_BSESSVLD BIT(22) | ||
387 | +#define GPWRDN_IDSTS BIT(21) | ||
388 | +#define GPWRDN_LINESTATE_MASK (0x3 << 19) | ||
389 | +#define GPWRDN_LINESTATE_SHIFT 19 | ||
390 | +#define GPWRDN_STS_CHGINT_MSK BIT(18) | ||
391 | +#define GPWRDN_STS_CHGINT BIT(17) | ||
392 | +#define GPWRDN_SRP_DET_MSK BIT(16) | ||
393 | +#define GPWRDN_SRP_DET BIT(15) | ||
394 | +#define GPWRDN_CONNECT_DET_MSK BIT(14) | ||
395 | +#define GPWRDN_CONNECT_DET BIT(13) | ||
396 | +#define GPWRDN_DISCONN_DET_MSK BIT(12) | ||
397 | +#define GPWRDN_DISCONN_DET BIT(11) | ||
398 | +#define GPWRDN_RST_DET_MSK BIT(10) | ||
399 | +#define GPWRDN_RST_DET BIT(9) | ||
400 | +#define GPWRDN_LNSTSCHG_MSK BIT(8) | ||
401 | +#define GPWRDN_LNSTSCHG BIT(7) | ||
402 | +#define GPWRDN_DIS_VBUS BIT(6) | ||
403 | +#define GPWRDN_PWRDNSWTCH BIT(5) | ||
404 | +#define GPWRDN_PWRDNRSTN BIT(4) | ||
405 | +#define GPWRDN_PWRDNCLMP BIT(3) | ||
406 | +#define GPWRDN_RESTORE BIT(2) | ||
407 | +#define GPWRDN_PMUACTV BIT(1) | ||
408 | +#define GPWRDN_PMUINTSEL BIT(0) | ||
409 | + | ||
410 | +#define GDFIFOCFG HSOTG_REG(0x005c) | ||
411 | +#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) | ||
412 | +#define GDFIFOCFG_EPINFOBASE_SHIFT 16 | ||
413 | +#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) | ||
414 | +#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 | ||
415 | + | ||
416 | +#define ADPCTL HSOTG_REG(0x0060) | ||
417 | +#define ADPCTL_AR_MASK (0x3 << 27) | ||
418 | +#define ADPCTL_AR_SHIFT 27 | ||
419 | +#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26) | ||
420 | +#define ADPCTL_ADP_SNS_INT_MSK BIT(25) | ||
421 | +#define ADPCTL_ADP_PRB_INT_MSK BIT(24) | ||
422 | +#define ADPCTL_ADP_TMOUT_INT BIT(23) | ||
423 | +#define ADPCTL_ADP_SNS_INT BIT(22) | ||
424 | +#define ADPCTL_ADP_PRB_INT BIT(21) | ||
425 | +#define ADPCTL_ADPENA BIT(20) | ||
426 | +#define ADPCTL_ADPRES BIT(19) | ||
427 | +#define ADPCTL_ENASNS BIT(18) | ||
428 | +#define ADPCTL_ENAPRB BIT(17) | ||
429 | +#define ADPCTL_RTIM_MASK (0x7ff << 6) | ||
430 | +#define ADPCTL_RTIM_SHIFT 6 | ||
431 | +#define ADPCTL_PRB_PER_MASK (0x3 << 4) | ||
432 | +#define ADPCTL_PRB_PER_SHIFT 4 | ||
433 | +#define ADPCTL_PRB_DELTA_MASK (0x3 << 2) | ||
434 | +#define ADPCTL_PRB_DELTA_SHIFT 2 | ||
435 | +#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) | ||
436 | +#define ADPCTL_PRB_DSCHRG_SHIFT 0 | ||
437 | + | ||
438 | +#define GREFCLK HSOTG_REG(0x0064) | ||
439 | +#define GREFCLK_REFCLKPER_MASK (0x1ffff << 15) | ||
440 | +#define GREFCLK_REFCLKPER_SHIFT 15 | ||
441 | +#define GREFCLK_REF_CLK_MODE BIT(14) | ||
442 | +#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff) | ||
443 | +#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0 | ||
444 | + | ||
445 | +#define GINTMSK2 HSOTG_REG(0x0068) | ||
446 | +#define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0) | ||
447 | + | ||
448 | +#define GINTSTS2 HSOTG_REG(0x006c) | ||
449 | +#define GINTSTS2_WKUP_ALERT_INT BIT(0) | ||
450 | + | ||
451 | +#define HPTXFSIZ HSOTG_REG(0x100) | ||
452 | +/* Use FIFOSIZE_* constants to access this register */ | ||
453 | + | ||
454 | +#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) | ||
455 | +/* Use FIFOSIZE_* constants to access this register */ | ||
456 | + | ||
457 | +/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ | ||
458 | +#define FIFOSIZE_DEPTH_MASK (0xffff << 16) | ||
459 | +#define FIFOSIZE_DEPTH_SHIFT 16 | ||
460 | +#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) | ||
461 | +#define FIFOSIZE_STARTADDR_SHIFT 0 | ||
462 | +#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) | ||
463 | + | ||
464 | +/* Device mode registers */ | ||
465 | + | ||
466 | +#define DCFG HSOTG_REG(0x800) | ||
467 | +#define DCFG_DESCDMA_EN BIT(23) | ||
468 | +#define DCFG_EPMISCNT_MASK (0x1f << 18) | ||
469 | +#define DCFG_EPMISCNT_SHIFT 18 | ||
470 | +#define DCFG_EPMISCNT_LIMIT 0x1f | ||
471 | +#define DCFG_EPMISCNT(_x) ((_x) << 18) | ||
472 | +#define DCFG_IPG_ISOC_SUPPORDED BIT(17) | ||
473 | +#define DCFG_PERFRINT_MASK (0x3 << 11) | ||
474 | +#define DCFG_PERFRINT_SHIFT 11 | ||
475 | +#define DCFG_PERFRINT_LIMIT 0x3 | ||
476 | +#define DCFG_PERFRINT(_x) ((_x) << 11) | ||
477 | +#define DCFG_DEVADDR_MASK (0x7f << 4) | ||
478 | +#define DCFG_DEVADDR_SHIFT 4 | ||
479 | +#define DCFG_DEVADDR_LIMIT 0x7f | ||
480 | +#define DCFG_DEVADDR(_x) ((_x) << 4) | ||
481 | +#define DCFG_NZ_STS_OUT_HSHK BIT(2) | ||
482 | +#define DCFG_DEVSPD_MASK (0x3 << 0) | ||
483 | +#define DCFG_DEVSPD_SHIFT 0 | ||
484 | +#define DCFG_DEVSPD_HS 0 | ||
485 | +#define DCFG_DEVSPD_FS 1 | ||
486 | +#define DCFG_DEVSPD_LS 2 | ||
487 | +#define DCFG_DEVSPD_FS48 3 | ||
488 | + | ||
489 | +#define DCTL HSOTG_REG(0x804) | ||
490 | +#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19) | ||
491 | +#define DCTL_PWRONPRGDONE BIT(11) | ||
492 | +#define DCTL_CGOUTNAK BIT(10) | ||
493 | +#define DCTL_SGOUTNAK BIT(9) | ||
494 | +#define DCTL_CGNPINNAK BIT(8) | ||
495 | +#define DCTL_SGNPINNAK BIT(7) | ||
496 | +#define DCTL_TSTCTL_MASK (0x7 << 4) | ||
497 | +#define DCTL_TSTCTL_SHIFT 4 | ||
498 | +#define DCTL_GOUTNAKSTS BIT(3) | ||
499 | +#define DCTL_GNPINNAKSTS BIT(2) | ||
500 | +#define DCTL_SFTDISCON BIT(1) | ||
501 | +#define DCTL_RMTWKUPSIG BIT(0) | ||
502 | + | ||
503 | +#define DSTS HSOTG_REG(0x808) | ||
504 | +#define DSTS_SOFFN_MASK (0x3fff << 8) | ||
505 | +#define DSTS_SOFFN_SHIFT 8 | ||
506 | +#define DSTS_SOFFN_LIMIT 0x3fff | ||
507 | +#define DSTS_SOFFN(_x) ((_x) << 8) | ||
508 | +#define DSTS_ERRATICERR BIT(3) | ||
509 | +#define DSTS_ENUMSPD_MASK (0x3 << 1) | ||
510 | +#define DSTS_ENUMSPD_SHIFT 1 | ||
511 | +#define DSTS_ENUMSPD_HS 0 | ||
512 | +#define DSTS_ENUMSPD_FS 1 | ||
513 | +#define DSTS_ENUMSPD_LS 2 | ||
514 | +#define DSTS_ENUMSPD_FS48 3 | ||
515 | +#define DSTS_SUSPSTS BIT(0) | ||
516 | + | ||
517 | +#define DIEPMSK HSOTG_REG(0x810) | ||
518 | +#define DIEPMSK_NAKMSK BIT(13) | ||
519 | +#define DIEPMSK_BNAININTRMSK BIT(9) | ||
520 | +#define DIEPMSK_TXFIFOUNDRNMSK BIT(8) | ||
521 | +#define DIEPMSK_TXFIFOEMPTY BIT(7) | ||
522 | +#define DIEPMSK_INEPNAKEFFMSK BIT(6) | ||
523 | +#define DIEPMSK_INTKNEPMISMSK BIT(5) | ||
524 | +#define DIEPMSK_INTKNTXFEMPMSK BIT(4) | ||
525 | +#define DIEPMSK_TIMEOUTMSK BIT(3) | ||
526 | +#define DIEPMSK_AHBERRMSK BIT(2) | ||
527 | +#define DIEPMSK_EPDISBLDMSK BIT(1) | ||
528 | +#define DIEPMSK_XFERCOMPLMSK BIT(0) | ||
529 | + | ||
530 | +#define DOEPMSK HSOTG_REG(0x814) | ||
531 | +#define DOEPMSK_BNAMSK BIT(9) | ||
532 | +#define DOEPMSK_BACK2BACKSETUP BIT(6) | ||
533 | +#define DOEPMSK_STSPHSERCVDMSK BIT(5) | ||
534 | +#define DOEPMSK_OUTTKNEPDISMSK BIT(4) | ||
535 | +#define DOEPMSK_SETUPMSK BIT(3) | ||
536 | +#define DOEPMSK_AHBERRMSK BIT(2) | ||
537 | +#define DOEPMSK_EPDISBLDMSK BIT(1) | ||
538 | +#define DOEPMSK_XFERCOMPLMSK BIT(0) | ||
539 | + | ||
540 | +#define DAINT HSOTG_REG(0x818) | ||
541 | +#define DAINTMSK HSOTG_REG(0x81C) | ||
542 | +#define DAINT_OUTEP_SHIFT 16 | ||
543 | +#define DAINT_OUTEP(_x) (1 << ((_x) + 16)) | ||
544 | +#define DAINT_INEP(_x) (1 << (_x)) | ||
545 | + | ||
546 | +#define DTKNQR1 HSOTG_REG(0x820) | ||
547 | +#define DTKNQR2 HSOTG_REG(0x824) | ||
548 | +#define DTKNQR3 HSOTG_REG(0x830) | ||
549 | +#define DTKNQR4 HSOTG_REG(0x834) | ||
550 | +#define DIEPEMPMSK HSOTG_REG(0x834) | ||
551 | + | ||
552 | +#define DVBUSDIS HSOTG_REG(0x828) | ||
553 | +#define DVBUSPULSE HSOTG_REG(0x82C) | ||
554 | + | ||
555 | +#define DIEPCTL0 HSOTG_REG(0x900) | ||
556 | +#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) | ||
557 | + | ||
558 | +#define DOEPCTL0 HSOTG_REG(0xB00) | ||
559 | +#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) | ||
560 | + | ||
561 | +/* EP0 specialness: | ||
562 | + * bits[29..28] - reserved (no SetD0PID, SetD1PID) | ||
563 | + * bits[25..22] - should always be zero, this isn't a periodic endpoint | ||
564 | + * bits[10..0] - MPS setting different for EP0 | ||
87 | + */ | 565 | + */ |
88 | +static void hex_loader_test(void) | 566 | +#define D0EPCTL_MPS_MASK (0x3 << 0) |
89 | +{ | 567 | +#define D0EPCTL_MPS_SHIFT 0 |
90 | + unsigned int i; | 568 | +#define D0EPCTL_MPS_64 0 |
91 | + const unsigned int base_addr = 0x00010000; | 569 | +#define D0EPCTL_MPS_32 1 |
92 | + | 570 | +#define D0EPCTL_MPS_16 2 |
93 | + QTestState *s = qtest_initf( | 571 | +#define D0EPCTL_MPS_8 3 |
94 | + "-M vexpress-a9 -nographic -device loader,file=tests/hex-loader-check-data/test.hex"); | 572 | + |
95 | + | 573 | +#define DXEPCTL_EPENA BIT(31) |
96 | + for (i = 0; i < 256; ++i) { | 574 | +#define DXEPCTL_EPDIS BIT(30) |
97 | + uint8_t val = qtest_readb(s, base_addr + i); | 575 | +#define DXEPCTL_SETD1PID BIT(29) |
98 | + g_assert_cmpuint(i, ==, val); | 576 | +#define DXEPCTL_SETODDFR BIT(29) |
99 | + } | 577 | +#define DXEPCTL_SETD0PID BIT(28) |
100 | + qtest_quit(s); | 578 | +#define DXEPCTL_SETEVENFR BIT(28) |
101 | +} | 579 | +#define DXEPCTL_SNAK BIT(27) |
102 | + | 580 | +#define DXEPCTL_CNAK BIT(26) |
103 | +int main(int argc, char **argv) | 581 | +#define DXEPCTL_TXFNUM_MASK (0xf << 22) |
104 | +{ | 582 | +#define DXEPCTL_TXFNUM_SHIFT 22 |
105 | + int ret; | 583 | +#define DXEPCTL_TXFNUM_LIMIT 0xf |
106 | + | 584 | +#define DXEPCTL_TXFNUM(_x) ((_x) << 22) |
107 | + g_test_init(&argc, &argv, NULL); | 585 | +#define DXEPCTL_STALL BIT(21) |
108 | + | 586 | +#define DXEPCTL_SNP BIT(20) |
109 | + qtest_add_func("/tmp/hex_loader", hex_loader_test); | 587 | +#define DXEPCTL_EPTYPE_MASK (0x3 << 18) |
110 | + ret = g_test_run(); | 588 | +#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) |
111 | + | 589 | +#define DXEPCTL_EPTYPE_ISO (0x1 << 18) |
112 | + return ret; | 590 | +#define DXEPCTL_EPTYPE_BULK (0x2 << 18) |
113 | +} | 591 | +#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) |
114 | diff --git a/MAINTAINERS b/MAINTAINERS | 592 | + |
115 | index XXXXXXX..XXXXXXX 100644 | 593 | +#define DXEPCTL_NAKSTS BIT(17) |
116 | --- a/MAINTAINERS | 594 | +#define DXEPCTL_DPID BIT(16) |
117 | +++ b/MAINTAINERS | 595 | +#define DXEPCTL_EOFRNUM BIT(16) |
118 | @@ -XXX,XX +XXX,XX @@ F: hw/core/generic-loader.c | 596 | +#define DXEPCTL_USBACTEP BIT(15) |
119 | F: include/hw/core/generic-loader.h | 597 | +#define DXEPCTL_NEXTEP_MASK (0xf << 11) |
120 | F: docs/generic-loader.txt | 598 | +#define DXEPCTL_NEXTEP_SHIFT 11 |
121 | 599 | +#define DXEPCTL_NEXTEP_LIMIT 0xf | |
122 | +Intel Hexadecimal Object File Loader | 600 | +#define DXEPCTL_NEXTEP(_x) ((_x) << 11) |
123 | +M: Su Hang <suhang16@mails.ucas.ac.cn> | 601 | +#define DXEPCTL_MPS_MASK (0x7ff << 0) |
124 | +S: Maintained | 602 | +#define DXEPCTL_MPS_SHIFT 0 |
125 | +F: tests/hexloader-test.c | 603 | +#define DXEPCTL_MPS_LIMIT 0x7ff |
126 | +F: tests/hex-loader-check-data/test.hex | 604 | +#define DXEPCTL_MPS(_x) ((_x) << 0) |
127 | + | 605 | + |
128 | CHRP NVRAM | 606 | +#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) |
129 | M: Thomas Huth <thuth@redhat.com> | 607 | +#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) |
130 | S: Maintained | 608 | +#define DXEPINT_SETUP_RCVD BIT(15) |
131 | diff --git a/tests/hex-loader-check-data/test.hex b/tests/hex-loader-check-data/test.hex | 609 | +#define DXEPINT_NYETINTRPT BIT(14) |
132 | new file mode 100644 | 610 | +#define DXEPINT_NAKINTRPT BIT(13) |
133 | index XXXXXXX..XXXXXXX | 611 | +#define DXEPINT_BBLEERRINTRPT BIT(12) |
134 | --- /dev/null | 612 | +#define DXEPINT_PKTDRPSTS BIT(11) |
135 | +++ b/tests/hex-loader-check-data/test.hex | 613 | +#define DXEPINT_BNAINTR BIT(9) |
136 | @@ -XXX,XX +XXX,XX @@ | 614 | +#define DXEPINT_TXFIFOUNDRN BIT(8) |
137 | +:020000040001F9 | 615 | +#define DXEPINT_OUTPKTERR BIT(8) |
138 | +:10000000000102030405060708090a0b0c0d0e0f78 | 616 | +#define DXEPINT_TXFEMP BIT(7) |
139 | +:10001000101112131415161718191a1b1c1d1e1f68 | 617 | +#define DXEPINT_INEPNAKEFF BIT(6) |
140 | +:10002000202122232425262728292a2b2c2d2e2f58 | 618 | +#define DXEPINT_BACK2BACKSETUP BIT(6) |
141 | +:10003000303132333435363738393a3b3c3d3e3f48 | 619 | +#define DXEPINT_INTKNEPMIS BIT(5) |
142 | +:10004000404142434445464748494a4b4c4d4e4f38 | 620 | +#define DXEPINT_STSPHSERCVD BIT(5) |
143 | +:10005000505152535455565758595a5b5c5d5e5f28 | 621 | +#define DXEPINT_INTKNTXFEMP BIT(4) |
144 | +:10006000606162636465666768696a6b6c6d6e6f18 | 622 | +#define DXEPINT_OUTTKNEPDIS BIT(4) |
145 | +:10007000707172737475767778797a7b7c7d7e7f08 | 623 | +#define DXEPINT_TIMEOUT BIT(3) |
146 | +:10008000808182838485868788898a8b8c8d8e8ff8 | 624 | +#define DXEPINT_SETUP BIT(3) |
147 | +:10009000909192939495969798999a9b9c9d9e9fe8 | 625 | +#define DXEPINT_AHBERR BIT(2) |
148 | +:1000a000a0a1a2a3a4a5a6a7a8a9aaabacadaeafd8 | 626 | +#define DXEPINT_EPDISBLD BIT(1) |
149 | +:1000b000b0b1b2b3b4b5b6b7b8b9babbbcbdbebfc8 | 627 | +#define DXEPINT_XFERCOMPL BIT(0) |
150 | +:1000c000c0c1c2c3c4c5c6c7c8c9cacbcccdcecfb8 | 628 | + |
151 | +:1000d000d0d1d2d3d4d5d6d7d8d9dadbdcdddedfa8 | 629 | +#define DIEPTSIZ0 HSOTG_REG(0x910) |
152 | +:1000e000e0e1e2e3e4e5e6e7e8e9eaebecedeeef98 | 630 | +#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) |
153 | +:1000f000f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff88 | 631 | +#define DIEPTSIZ0_PKTCNT_SHIFT 19 |
154 | +:00000001FF | 632 | +#define DIEPTSIZ0_PKTCNT_LIMIT 0x3 |
633 | +#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) | ||
634 | +#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) | ||
635 | +#define DIEPTSIZ0_XFERSIZE_SHIFT 0 | ||
636 | +#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f | ||
637 | +#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) | ||
638 | + | ||
639 | +#define DOEPTSIZ0 HSOTG_REG(0xB10) | ||
640 | +#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) | ||
641 | +#define DOEPTSIZ0_SUPCNT_SHIFT 29 | ||
642 | +#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 | ||
643 | +#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) | ||
644 | +#define DOEPTSIZ0_PKTCNT BIT(19) | ||
645 | +#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) | ||
646 | +#define DOEPTSIZ0_XFERSIZE_SHIFT 0 | ||
647 | + | ||
648 | +#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) | ||
649 | +#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) | ||
650 | +#define DXEPTSIZ_MC_MASK (0x3 << 29) | ||
651 | +#define DXEPTSIZ_MC_SHIFT 29 | ||
652 | +#define DXEPTSIZ_MC_LIMIT 0x3 | ||
653 | +#define DXEPTSIZ_MC(_x) ((_x) << 29) | ||
654 | +#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) | ||
655 | +#define DXEPTSIZ_PKTCNT_SHIFT 19 | ||
656 | +#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff | ||
657 | +#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) | ||
658 | +#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) | ||
659 | +#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) | ||
660 | +#define DXEPTSIZ_XFERSIZE_SHIFT 0 | ||
661 | +#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff | ||
662 | +#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) | ||
663 | +#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) | ||
664 | + | ||
665 | +#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) | ||
666 | +#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) | ||
667 | + | ||
668 | +#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) | ||
669 | + | ||
670 | +#define PCGCTL HSOTG_REG(0x0e00) | ||
671 | +#define PCGCTL_IF_DEV_MODE BIT(31) | ||
672 | +#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) | ||
673 | +#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 | ||
674 | +#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) | ||
675 | +#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 | ||
676 | +#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) | ||
677 | +#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 | ||
678 | +#define PCGCTL_MAX_TERMSEL BIT(19) | ||
679 | +#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) | ||
680 | +#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 | ||
681 | +#define PCGCTL_PORT_POWER BIT(16) | ||
682 | +#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) | ||
683 | +#define PCGCTL_PRT_CLK_SEL_SHIFT 14 | ||
684 | +#define PCGCTL_ESS_REG_RESTORED BIT(13) | ||
685 | +#define PCGCTL_EXTND_HIBER_SWITCH BIT(12) | ||
686 | +#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11) | ||
687 | +#define PCGCTL_ENBL_EXTND_HIBER BIT(10) | ||
688 | +#define PCGCTL_RESTOREMODE BIT(9) | ||
689 | +#define PCGCTL_RESETAFTSUSP BIT(8) | ||
690 | +#define PCGCTL_DEEP_SLEEP BIT(7) | ||
691 | +#define PCGCTL_PHY_IN_SLEEP BIT(6) | ||
692 | +#define PCGCTL_ENBL_SLEEP_GATING BIT(5) | ||
693 | +#define PCGCTL_RSTPDWNMODULE BIT(3) | ||
694 | +#define PCGCTL_PWRCLMP BIT(2) | ||
695 | +#define PCGCTL_GATEHCLK BIT(1) | ||
696 | +#define PCGCTL_STOPPCLK BIT(0) | ||
697 | + | ||
698 | +#define PCGCCTL1 HSOTG_REG(0xe04) | ||
699 | +#define PCGCCTL1_TIMER (0x3 << 1) | ||
700 | +#define PCGCCTL1_GATEEN BIT(0) | ||
701 | + | ||
702 | +#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) | ||
703 | + | ||
704 | +/* Host Mode Registers */ | ||
705 | + | ||
706 | +#define HCFG HSOTG_REG(0x0400) | ||
707 | +#define HCFG_MODECHTIMEN BIT(31) | ||
708 | +#define HCFG_PERSCHEDENA BIT(26) | ||
709 | +#define HCFG_FRLISTEN_MASK (0x3 << 24) | ||
710 | +#define HCFG_FRLISTEN_SHIFT 24 | ||
711 | +#define HCFG_FRLISTEN_8 (0 << 24) | ||
712 | +#define FRLISTEN_8_SIZE 8 | ||
713 | +#define HCFG_FRLISTEN_16 BIT(24) | ||
714 | +#define FRLISTEN_16_SIZE 16 | ||
715 | +#define HCFG_FRLISTEN_32 (2 << 24) | ||
716 | +#define FRLISTEN_32_SIZE 32 | ||
717 | +#define HCFG_FRLISTEN_64 (3 << 24) | ||
718 | +#define FRLISTEN_64_SIZE 64 | ||
719 | +#define HCFG_DESCDMA BIT(23) | ||
720 | +#define HCFG_RESVALID_MASK (0xff << 8) | ||
721 | +#define HCFG_RESVALID_SHIFT 8 | ||
722 | +#define HCFG_ENA32KHZ BIT(7) | ||
723 | +#define HCFG_FSLSSUPP BIT(2) | ||
724 | +#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) | ||
725 | +#define HCFG_FSLSPCLKSEL_SHIFT 0 | ||
726 | +#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 | ||
727 | +#define HCFG_FSLSPCLKSEL_48_MHZ 1 | ||
728 | +#define HCFG_FSLSPCLKSEL_6_MHZ 2 | ||
729 | + | ||
730 | +#define HFIR HSOTG_REG(0x0404) | ||
731 | +#define HFIR_FRINT_MASK (0xffff << 0) | ||
732 | +#define HFIR_FRINT_SHIFT 0 | ||
733 | +#define HFIR_RLDCTRL BIT(16) | ||
734 | + | ||
735 | +#define HFNUM HSOTG_REG(0x0408) | ||
736 | +#define HFNUM_FRREM_MASK (0xffff << 16) | ||
737 | +#define HFNUM_FRREM_SHIFT 16 | ||
738 | +#define HFNUM_FRNUM_MASK (0xffff << 0) | ||
739 | +#define HFNUM_FRNUM_SHIFT 0 | ||
740 | +#define HFNUM_MAX_FRNUM 0x3fff | ||
741 | + | ||
742 | +#define HPTXSTS HSOTG_REG(0x0410) | ||
743 | +#define TXSTS_QTOP_ODD BIT(31) | ||
744 | +#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) | ||
745 | +#define TXSTS_QTOP_CHNEP_SHIFT 27 | ||
746 | +#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) | ||
747 | +#define TXSTS_QTOP_TOKEN_SHIFT 25 | ||
748 | +#define TXSTS_QTOP_TERMINATE BIT(24) | ||
749 | +#define TXSTS_QSPCAVAIL_MASK (0xff << 16) | ||
750 | +#define TXSTS_QSPCAVAIL_SHIFT 16 | ||
751 | +#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) | ||
752 | +#define TXSTS_FSPCAVAIL_SHIFT 0 | ||
753 | + | ||
754 | +#define HAINT HSOTG_REG(0x0414) | ||
755 | +#define HAINTMSK HSOTG_REG(0x0418) | ||
756 | +#define HFLBADDR HSOTG_REG(0x041c) | ||
757 | + | ||
758 | +#define HPRT0 HSOTG_REG(0x0440) | ||
759 | +#define HPRT0_SPD_MASK (0x3 << 17) | ||
760 | +#define HPRT0_SPD_SHIFT 17 | ||
761 | +#define HPRT0_SPD_HIGH_SPEED 0 | ||
762 | +#define HPRT0_SPD_FULL_SPEED 1 | ||
763 | +#define HPRT0_SPD_LOW_SPEED 2 | ||
764 | +#define HPRT0_TSTCTL_MASK (0xf << 13) | ||
765 | +#define HPRT0_TSTCTL_SHIFT 13 | ||
766 | +#define HPRT0_PWR BIT(12) | ||
767 | +#define HPRT0_LNSTS_MASK (0x3 << 10) | ||
768 | +#define HPRT0_LNSTS_SHIFT 10 | ||
769 | +#define HPRT0_RST BIT(8) | ||
770 | +#define HPRT0_SUSP BIT(7) | ||
771 | +#define HPRT0_RES BIT(6) | ||
772 | +#define HPRT0_OVRCURRCHG BIT(5) | ||
773 | +#define HPRT0_OVRCURRACT BIT(4) | ||
774 | +#define HPRT0_ENACHG BIT(3) | ||
775 | +#define HPRT0_ENA BIT(2) | ||
776 | +#define HPRT0_CONNDET BIT(1) | ||
777 | +#define HPRT0_CONNSTS BIT(0) | ||
778 | + | ||
779 | +#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) | ||
780 | +#define HCCHAR_CHENA BIT(31) | ||
781 | +#define HCCHAR_CHDIS BIT(30) | ||
782 | +#define HCCHAR_ODDFRM BIT(29) | ||
783 | +#define HCCHAR_DEVADDR_MASK (0x7f << 22) | ||
784 | +#define HCCHAR_DEVADDR_SHIFT 22 | ||
785 | +#define HCCHAR_MULTICNT_MASK (0x3 << 20) | ||
786 | +#define HCCHAR_MULTICNT_SHIFT 20 | ||
787 | +#define HCCHAR_EPTYPE_MASK (0x3 << 18) | ||
788 | +#define HCCHAR_EPTYPE_SHIFT 18 | ||
789 | +#define HCCHAR_LSPDDEV BIT(17) | ||
790 | +#define HCCHAR_EPDIR BIT(15) | ||
791 | +#define HCCHAR_EPNUM_MASK (0xf << 11) | ||
792 | +#define HCCHAR_EPNUM_SHIFT 11 | ||
793 | +#define HCCHAR_MPS_MASK (0x7ff << 0) | ||
794 | +#define HCCHAR_MPS_SHIFT 0 | ||
795 | + | ||
796 | +#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) | ||
797 | +#define HCSPLT_SPLTENA BIT(31) | ||
798 | +#define HCSPLT_COMPSPLT BIT(16) | ||
799 | +#define HCSPLT_XACTPOS_MASK (0x3 << 14) | ||
800 | +#define HCSPLT_XACTPOS_SHIFT 14 | ||
801 | +#define HCSPLT_XACTPOS_MID 0 | ||
802 | +#define HCSPLT_XACTPOS_END 1 | ||
803 | +#define HCSPLT_XACTPOS_BEGIN 2 | ||
804 | +#define HCSPLT_XACTPOS_ALL 3 | ||
805 | +#define HCSPLT_HUBADDR_MASK (0x7f << 7) | ||
806 | +#define HCSPLT_HUBADDR_SHIFT 7 | ||
807 | +#define HCSPLT_PRTADDR_MASK (0x7f << 0) | ||
808 | +#define HCSPLT_PRTADDR_SHIFT 0 | ||
809 | + | ||
810 | +#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) | ||
811 | +#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) | ||
812 | +#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) | ||
813 | +#define HCINTMSK_FRM_LIST_ROLL BIT(13) | ||
814 | +#define HCINTMSK_XCS_XACT BIT(12) | ||
815 | +#define HCINTMSK_BNA BIT(11) | ||
816 | +#define HCINTMSK_DATATGLERR BIT(10) | ||
817 | +#define HCINTMSK_FRMOVRUN BIT(9) | ||
818 | +#define HCINTMSK_BBLERR BIT(8) | ||
819 | +#define HCINTMSK_XACTERR BIT(7) | ||
820 | +#define HCINTMSK_NYET BIT(6) | ||
821 | +#define HCINTMSK_ACK BIT(5) | ||
822 | +#define HCINTMSK_NAK BIT(4) | ||
823 | +#define HCINTMSK_STALL BIT(3) | ||
824 | +#define HCINTMSK_AHBERR BIT(2) | ||
825 | +#define HCINTMSK_CHHLTD BIT(1) | ||
826 | +#define HCINTMSK_XFERCOMPL BIT(0) | ||
827 | + | ||
828 | +#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) | ||
829 | +#define TSIZ_DOPNG BIT(31) | ||
830 | +#define TSIZ_SC_MC_PID_MASK (0x3 << 29) | ||
831 | +#define TSIZ_SC_MC_PID_SHIFT 29 | ||
832 | +#define TSIZ_SC_MC_PID_DATA0 0 | ||
833 | +#define TSIZ_SC_MC_PID_DATA2 1 | ||
834 | +#define TSIZ_SC_MC_PID_DATA1 2 | ||
835 | +#define TSIZ_SC_MC_PID_MDATA 3 | ||
836 | +#define TSIZ_SC_MC_PID_SETUP 3 | ||
837 | +#define TSIZ_PKTCNT_MASK (0x3ff << 19) | ||
838 | +#define TSIZ_PKTCNT_SHIFT 19 | ||
839 | +#define TSIZ_NTD_MASK (0xff << 8) | ||
840 | +#define TSIZ_NTD_SHIFT 8 | ||
841 | +#define TSIZ_SCHINFO_MASK (0xff << 0) | ||
842 | +#define TSIZ_SCHINFO_SHIFT 0 | ||
843 | +#define TSIZ_XFERSIZE_MASK (0x7ffff << 0) | ||
844 | +#define TSIZ_XFERSIZE_SHIFT 0 | ||
845 | + | ||
846 | +#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) | ||
847 | + | ||
848 | +#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) | ||
849 | + | ||
850 | +#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) | ||
851 | + | ||
852 | +/** | ||
853 | + * struct dwc2_dma_desc - DMA descriptor structure, | ||
854 | + * used for both host and gadget modes | ||
855 | + * | ||
856 | + * @status: DMA descriptor status quadlet | ||
857 | + * @buf: DMA descriptor data buffer pointer | ||
858 | + * | ||
859 | + * DMA Descriptor structure contains two quadlets: | ||
860 | + * Status quadlet and Data buffer pointer. | ||
861 | + */ | ||
862 | +struct dwc2_dma_desc { | ||
863 | + uint32_t status; | ||
864 | + uint32_t buf; | ||
865 | +} __packed; | ||
866 | + | ||
867 | +/* Host Mode DMA descriptor status quadlet */ | ||
868 | + | ||
869 | +#define HOST_DMA_A BIT(31) | ||
870 | +#define HOST_DMA_STS_MASK (0x3 << 28) | ||
871 | +#define HOST_DMA_STS_SHIFT 28 | ||
872 | +#define HOST_DMA_STS_PKTERR BIT(28) | ||
873 | +#define HOST_DMA_EOL BIT(26) | ||
874 | +#define HOST_DMA_IOC BIT(25) | ||
875 | +#define HOST_DMA_SUP BIT(24) | ||
876 | +#define HOST_DMA_ALT_QTD BIT(23) | ||
877 | +#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) | ||
878 | +#define HOST_DMA_QTD_OFFSET_SHIFT 17 | ||
879 | +#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) | ||
880 | +#define HOST_DMA_ISOC_NBYTES_SHIFT 0 | ||
881 | +#define HOST_DMA_NBYTES_MASK (0x1ffff << 0) | ||
882 | +#define HOST_DMA_NBYTES_SHIFT 0 | ||
883 | +#define HOST_DMA_NBYTES_LIMIT 131071 | ||
884 | + | ||
885 | +/* Device Mode DMA descriptor status quadlet */ | ||
886 | + | ||
887 | +#define DEV_DMA_BUFF_STS_MASK (0x3 << 30) | ||
888 | +#define DEV_DMA_BUFF_STS_SHIFT 30 | ||
889 | +#define DEV_DMA_BUFF_STS_HREADY 0 | ||
890 | +#define DEV_DMA_BUFF_STS_DMABUSY 1 | ||
891 | +#define DEV_DMA_BUFF_STS_DMADONE 2 | ||
892 | +#define DEV_DMA_BUFF_STS_HBUSY 3 | ||
893 | +#define DEV_DMA_STS_MASK (0x3 << 28) | ||
894 | +#define DEV_DMA_STS_SHIFT 28 | ||
895 | +#define DEV_DMA_STS_SUCC 0 | ||
896 | +#define DEV_DMA_STS_BUFF_FLUSH 1 | ||
897 | +#define DEV_DMA_STS_BUFF_ERR 3 | ||
898 | +#define DEV_DMA_L BIT(27) | ||
899 | +#define DEV_DMA_SHORT BIT(26) | ||
900 | +#define DEV_DMA_IOC BIT(25) | ||
901 | +#define DEV_DMA_SR BIT(24) | ||
902 | +#define DEV_DMA_MTRF BIT(23) | ||
903 | +#define DEV_DMA_ISOC_PID_MASK (0x3 << 23) | ||
904 | +#define DEV_DMA_ISOC_PID_SHIFT 23 | ||
905 | +#define DEV_DMA_ISOC_PID_DATA0 0 | ||
906 | +#define DEV_DMA_ISOC_PID_DATA2 1 | ||
907 | +#define DEV_DMA_ISOC_PID_DATA1 2 | ||
908 | +#define DEV_DMA_ISOC_PID_MDATA 3 | ||
909 | +#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12) | ||
910 | +#define DEV_DMA_ISOC_FRNUM_SHIFT 12 | ||
911 | +#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0) | ||
912 | +#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff | ||
913 | +#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0) | ||
914 | +#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff | ||
915 | +#define DEV_DMA_ISOC_NBYTES_SHIFT 0 | ||
916 | +#define DEV_DMA_NBYTES_MASK (0xffff << 0) | ||
917 | +#define DEV_DMA_NBYTES_SHIFT 0 | ||
918 | +#define DEV_DMA_NBYTES_LIMIT 0xffff | ||
919 | + | ||
920 | +#define MAX_DMA_DESC_NUM_GENERIC 64 | ||
921 | +#define MAX_DMA_DESC_NUM_HS_ISOC 256 | ||
922 | + | ||
923 | +#endif /* __DWC2_HW_H__ */ | ||
155 | -- | 924 | -- |
156 | 2.18.0 | 925 | 2.20.1 |
157 | 926 | ||
158 | 927 | diff view generated by jsdifflib |
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Tested by booting linux 4.18 (built using imx_v6_v7_defconfig) on the | 3 | Add the dwc-hsotg (dwc2) USB host controller state definitions. |
4 | emulated board. | 4 | Mostly based on hw/usb/hcd-ehci.h. |
5 | 5 | ||
6 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | 6 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> |
7 | Message-id: 3f8eb4300206634dc01e04b12f65b73c0ad2f955.1532984236.git.jcd@tribudubois.net | 7 | Message-id: 20200520235349.21215-4-pauldzim@gmail.com |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | hw/arm/Makefile.objs | 2 +- | 11 | hw/usb/hcd-dwc2.h | 190 ++++++++++++++++++++++++++++++++++++++++++++++ |
12 | hw/arm/mcimx6ul-evk.c | 85 +++++++++++++++++++++++++++++++++++++++++++ | 12 | 1 file changed, 190 insertions(+) |
13 | 2 files changed, 86 insertions(+), 1 deletion(-) | 13 | create mode 100644 hw/usb/hcd-dwc2.h |
14 | create mode 100644 hw/arm/mcimx6ul-evk.c | 14 | |
15 | 15 | diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h | |
16 | diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/arm/Makefile.objs | ||
19 | +++ b/hw/arm/Makefile.objs | ||
20 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o | ||
21 | obj-$(CONFIG_IOTKIT) += iotkit.o | ||
22 | obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o | ||
23 | obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o | ||
24 | -obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o | ||
25 | +obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o | ||
26 | diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c | ||
27 | new file mode 100644 | 16 | new file mode 100644 |
28 | index XXXXXXX..XXXXXXX | 17 | index XXXXXXX..XXXXXXX |
29 | --- /dev/null | 18 | --- /dev/null |
30 | +++ b/hw/arm/mcimx6ul-evk.c | 19 | +++ b/hw/usb/hcd-dwc2.h |
31 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
32 | +/* | 21 | +/* |
33 | + * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> | 22 | + * dwc-hsotg (dwc2) USB host controller state definitions |
34 | + * | 23 | + * |
35 | + * MCIMX6UL_EVK Board System emulation. | 24 | + * Based on hw/usb/hcd-ehci.h |
36 | + * | 25 | + * |
37 | + * This code is licensed under the GPL, version 2 or later. | 26 | + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com> |
38 | + * See the file `COPYING' in the top level directory. | 27 | + * |
39 | + * | 28 | + * This program is free software; you can redistribute it and/or modify |
40 | + * It (partially) emulates a mcimx6ul_evk board, with a Freescale | 29 | + * it under the terms of the GNU General Public License as published by |
41 | + * i.MX6ul SoC | 30 | + * the Free Software Foundation; either version 2 of the License, or |
31 | + * (at your option) any later version. | ||
32 | + * | ||
33 | + * This program is distributed in the hope that it will be useful, | ||
34 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
35 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
36 | + * GNU General Public License for more details. | ||
42 | + */ | 37 | + */ |
43 | + | 38 | + |
44 | +#include "qemu/osdep.h" | 39 | +#ifndef HW_USB_DWC2_H |
45 | +#include "qapi/error.h" | 40 | +#define HW_USB_DWC2_H |
46 | +#include "qemu-common.h" | 41 | + |
47 | +#include "hw/arm/fsl-imx6ul.h" | 42 | +#include "qemu/timer.h" |
48 | +#include "hw/boards.h" | 43 | +#include "hw/irq.h" |
49 | +#include "sysemu/sysemu.h" | 44 | +#include "hw/sysbus.h" |
50 | +#include "qemu/error-report.h" | 45 | +#include "hw/usb.h" |
51 | +#include "sysemu/qtest.h" | 46 | +#include "sysemu/dma.h" |
52 | + | 47 | + |
53 | +typedef struct { | 48 | +#define DWC2_MMIO_SIZE 0x11000 |
54 | + FslIMX6ULState soc; | 49 | + |
55 | + MemoryRegion ram; | 50 | +#define DWC2_NB_CHAN 8 /* Number of host channels */ |
56 | +} MCIMX6ULEVK; | 51 | +#define DWC2_MAX_XFER_SIZE 65536 /* Max transfer size expected in HCTSIZ */ |
57 | + | 52 | + |
58 | +static void mcimx6ul_evk_init(MachineState *machine) | 53 | +typedef struct DWC2Packet DWC2Packet; |
59 | +{ | 54 | +typedef struct DWC2State DWC2State; |
60 | + static struct arm_boot_info boot_info; | 55 | +typedef struct DWC2Class DWC2Class; |
61 | + MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1); | 56 | + |
62 | + int i; | 57 | +enum async_state { |
63 | + | 58 | + DWC2_ASYNC_NONE = 0, |
64 | + if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) { | 59 | + DWC2_ASYNC_INITIALIZED, |
65 | + error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)", | 60 | + DWC2_ASYNC_INFLIGHT, |
66 | + machine->ram_size, FSL_IMX6UL_MMDC_SIZE); | 61 | + DWC2_ASYNC_FINISHED, |
67 | + exit(1); | 62 | +}; |
68 | + } | 63 | + |
69 | + | 64 | +struct DWC2Packet { |
70 | + boot_info = (struct arm_boot_info) { | 65 | + USBPacket packet; |
71 | + .loader_start = FSL_IMX6UL_MMDC_ADDR, | 66 | + uint32_t devadr; |
72 | + .board_id = -1, | 67 | + uint32_t epnum; |
73 | + .ram_size = machine->ram_size, | 68 | + uint32_t epdir; |
74 | + .kernel_filename = machine->kernel_filename, | 69 | + uint32_t mps; |
75 | + .kernel_cmdline = machine->kernel_cmdline, | 70 | + uint32_t pid; |
76 | + .initrd_filename = machine->initrd_filename, | 71 | + uint32_t index; |
77 | + .nb_cpus = smp_cpus, | 72 | + uint32_t pcnt; |
78 | + }; | 73 | + uint32_t len; |
79 | + | 74 | + int32_t async; |
80 | + object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), | 75 | + bool small; |
81 | + TYPE_FSL_IMX6UL, &error_fatal, NULL); | 76 | + bool needs_service; |
82 | + | 77 | +}; |
83 | + object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); | 78 | + |
84 | + | 79 | +struct DWC2State { |
85 | + memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram", | 80 | + /*< private >*/ |
86 | + machine->ram_size); | 81 | + SysBusDevice parent_obj; |
87 | + memory_region_add_subregion(get_system_memory(), | 82 | + |
88 | + FSL_IMX6UL_MMDC_ADDR, &s->ram); | 83 | + /*< public >*/ |
89 | + | 84 | + USBBus bus; |
90 | + for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | 85 | + qemu_irq irq; |
91 | + BusState *bus; | 86 | + MemoryRegion *dma_mr; |
92 | + DeviceState *carddev; | 87 | + AddressSpace dma_as; |
93 | + DriveInfo *di; | 88 | + MemoryRegion container; |
94 | + BlockBackend *blk; | 89 | + MemoryRegion hsotg; |
95 | + | 90 | + MemoryRegion fifos; |
96 | + di = drive_get_next(IF_SD); | 91 | + |
97 | + blk = di ? blk_by_legacy_dinfo(di) : NULL; | 92 | + union { |
98 | + bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); | 93 | +#define DWC2_GLBREG_SIZE 0x70 |
99 | + carddev = qdev_create(bus, TYPE_SD_CARD); | 94 | + uint32_t glbreg[DWC2_GLBREG_SIZE / sizeof(uint32_t)]; |
100 | + qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); | 95 | + struct { |
101 | + object_property_set_bool(OBJECT(carddev), true, | 96 | + uint32_t gotgctl; /* 00 */ |
102 | + "realized", &error_fatal); | 97 | + uint32_t gotgint; /* 04 */ |
103 | + } | 98 | + uint32_t gahbcfg; /* 08 */ |
104 | + | 99 | + uint32_t gusbcfg; /* 0c */ |
105 | + if (!qtest_enabled()) { | 100 | + uint32_t grstctl; /* 10 */ |
106 | + arm_load_kernel(&s->soc.cpu[0], &boot_info); | 101 | + uint32_t gintsts; /* 14 */ |
107 | + } | 102 | + uint32_t gintmsk; /* 18 */ |
108 | +} | 103 | + uint32_t grxstsr; /* 1c */ |
109 | + | 104 | + uint32_t grxstsp; /* 20 */ |
110 | +static void mcimx6ul_evk_machine_init(MachineClass *mc) | 105 | + uint32_t grxfsiz; /* 24 */ |
111 | +{ | 106 | + uint32_t gnptxfsiz; /* 28 */ |
112 | + mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)"; | 107 | + uint32_t gnptxsts; /* 2c */ |
113 | + mc->init = mcimx6ul_evk_init; | 108 | + uint32_t gi2cctl; /* 30 */ |
114 | + mc->max_cpus = FSL_IMX6UL_NUM_CPUS; | 109 | + uint32_t gpvndctl; /* 34 */ |
115 | +} | 110 | + uint32_t ggpio; /* 38 */ |
116 | +DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init) | 111 | + uint32_t guid; /* 3c */ |
112 | + uint32_t gsnpsid; /* 40 */ | ||
113 | + uint32_t ghwcfg1; /* 44 */ | ||
114 | + uint32_t ghwcfg2; /* 48 */ | ||
115 | + uint32_t ghwcfg3; /* 4c */ | ||
116 | + uint32_t ghwcfg4; /* 50 */ | ||
117 | + uint32_t glpmcfg; /* 54 */ | ||
118 | + uint32_t gpwrdn; /* 58 */ | ||
119 | + uint32_t gdfifocfg; /* 5c */ | ||
120 | + uint32_t gadpctl; /* 60 */ | ||
121 | + uint32_t grefclk; /* 64 */ | ||
122 | + uint32_t gintmsk2; /* 68 */ | ||
123 | + uint32_t gintsts2; /* 6c */ | ||
124 | + }; | ||
125 | + }; | ||
126 | + | ||
127 | + union { | ||
128 | +#define DWC2_FSZREG_SIZE 0x04 | ||
129 | + uint32_t fszreg[DWC2_FSZREG_SIZE / sizeof(uint32_t)]; | ||
130 | + struct { | ||
131 | + uint32_t hptxfsiz; /* 100 */ | ||
132 | + }; | ||
133 | + }; | ||
134 | + | ||
135 | + union { | ||
136 | +#define DWC2_HREG0_SIZE 0x44 | ||
137 | + uint32_t hreg0[DWC2_HREG0_SIZE / sizeof(uint32_t)]; | ||
138 | + struct { | ||
139 | + uint32_t hcfg; /* 400 */ | ||
140 | + uint32_t hfir; /* 404 */ | ||
141 | + uint32_t hfnum; /* 408 */ | ||
142 | + uint32_t rsvd0; /* 40c */ | ||
143 | + uint32_t hptxsts; /* 410 */ | ||
144 | + uint32_t haint; /* 414 */ | ||
145 | + uint32_t haintmsk; /* 418 */ | ||
146 | + uint32_t hflbaddr; /* 41c */ | ||
147 | + uint32_t rsvd1[8]; /* 420-43c */ | ||
148 | + uint32_t hprt0; /* 440 */ | ||
149 | + }; | ||
150 | + }; | ||
151 | + | ||
152 | +#define DWC2_HREG1_SIZE (0x20 * DWC2_NB_CHAN) | ||
153 | + uint32_t hreg1[DWC2_HREG1_SIZE / sizeof(uint32_t)]; | ||
154 | + | ||
155 | +#define hcchar(_ch) hreg1[((_ch) << 3) + 0] /* 500, 520, ... */ | ||
156 | +#define hcsplt(_ch) hreg1[((_ch) << 3) + 1] /* 504, 524, ... */ | ||
157 | +#define hcint(_ch) hreg1[((_ch) << 3) + 2] /* 508, 528, ... */ | ||
158 | +#define hcintmsk(_ch) hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */ | ||
159 | +#define hctsiz(_ch) hreg1[((_ch) << 3) + 4] /* 510, 530, ... */ | ||
160 | +#define hcdma(_ch) hreg1[((_ch) << 3) + 5] /* 514, 534, ... */ | ||
161 | +#define hcdmab(_ch) hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */ | ||
162 | + | ||
163 | + union { | ||
164 | +#define DWC2_PCGREG_SIZE 0x08 | ||
165 | + uint32_t pcgreg[DWC2_PCGREG_SIZE / sizeof(uint32_t)]; | ||
166 | + struct { | ||
167 | + uint32_t pcgctl; /* e00 */ | ||
168 | + uint32_t pcgcctl1; /* e04 */ | ||
169 | + }; | ||
170 | + }; | ||
171 | + | ||
172 | + /* TODO - implement FIFO registers for slave mode */ | ||
173 | +#define DWC2_HFIFO_SIZE (0x1000 * DWC2_NB_CHAN) | ||
174 | + | ||
175 | + /* | ||
176 | + * Internal state | ||
177 | + */ | ||
178 | + QEMUTimer *eof_timer; | ||
179 | + QEMUTimer *frame_timer; | ||
180 | + QEMUBH *async_bh; | ||
181 | + int64_t sof_time; | ||
182 | + int64_t usb_frame_time; | ||
183 | + int64_t usb_bit_time; | ||
184 | + uint32_t usb_version; | ||
185 | + uint16_t frame_number; | ||
186 | + uint16_t fi; | ||
187 | + uint16_t next_chan; | ||
188 | + bool working; | ||
189 | + USBPort uport; | ||
190 | + DWC2Packet packet[DWC2_NB_CHAN]; /* one packet per chan */ | ||
191 | + uint8_t usb_buf[DWC2_NB_CHAN][DWC2_MAX_XFER_SIZE]; /* one buffer per chan */ | ||
192 | +}; | ||
193 | + | ||
194 | +struct DWC2Class { | ||
195 | + /*< private >*/ | ||
196 | + SysBusDeviceClass parent_class; | ||
197 | + ResettablePhases parent_phases; | ||
198 | + | ||
199 | + /*< public >*/ | ||
200 | +}; | ||
201 | + | ||
202 | +#define TYPE_DWC2_USB "dwc2-usb" | ||
203 | +#define DWC2_USB(obj) \ | ||
204 | + OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB) | ||
205 | +#define DWC2_CLASS(klass) \ | ||
206 | + OBJECT_CLASS_CHECK(DWC2Class, (klass), TYPE_DWC2_USB) | ||
207 | +#define DWC2_GET_CLASS(obj) \ | ||
208 | + OBJECT_GET_CLASS(DWC2Class, (obj), TYPE_DWC2_USB) | ||
209 | + | ||
210 | +#endif | ||
117 | -- | 211 | -- |
118 | 2.18.0 | 212 | 2.20.1 |
119 | 213 | ||
120 | 214 | diff view generated by jsdifflib |
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | 3 | Add the dwc-hsotg (dwc2) USB host controller emulation code. |
4 | Message-id: 34b6704ceb81b49e35ce1ad162bf758e5141ff87.1532984236.git.jcd@tribudubois.net | 4 | Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c. |
5 | [PMM: fixed some comment typos etc] | 5 | |
6 | Note that to use this with the dwc-otg driver in the Raspbian | ||
7 | kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" on | ||
8 | the kernel command line. | ||
9 | |||
10 | Emulation of slave mode and of descriptor-DMA mode has not been | ||
11 | implemented yet. These modes are seldom used. | ||
12 | |||
13 | I have used some on-line sources of information while developing | ||
14 | this emulation, including: | ||
15 | |||
16 | http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf | ||
17 | which has a pretty complete description of the controller starting | ||
18 | on page 370. | ||
19 | |||
20 | https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf | ||
21 | which has a description of the controller registers starting on | ||
22 | page 130. | ||
23 | |||
24 | Thanks to Felippe Mathieu-Daude for providing a cleaner method | ||
25 | of implementing the memory regions for the controller registers. | ||
26 | |||
27 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> | ||
28 | Message-id: 20200520235349.21215-5-pauldzim@gmail.com | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 30 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 31 | --- |
9 | hw/misc/Makefile.objs | 1 + | 32 | hw/usb/hcd-dwc2.c | 1417 ++++++++++++++++++++++++++++++++++++++++++ |
10 | include/hw/misc/imx6ul_ccm.h | 226 +++++++++ | 33 | hw/usb/Kconfig | 5 + |
11 | hw/misc/imx6ul_ccm.c | 886 +++++++++++++++++++++++++++++++++++ | 34 | hw/usb/Makefile.objs | 1 + |
12 | hw/misc/trace-events | 7 + | 35 | hw/usb/trace-events | 50 ++ |
13 | 4 files changed, 1120 insertions(+) | 36 | 4 files changed, 1473 insertions(+) |
14 | create mode 100644 include/hw/misc/imx6ul_ccm.h | 37 | create mode 100644 hw/usb/hcd-dwc2.c |
15 | create mode 100644 hw/misc/imx6ul_ccm.c | ||
16 | 38 | ||
17 | diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs | 39 | diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c |
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/misc/Makefile.objs | ||
20 | +++ b/hw/misc/Makefile.objs | ||
21 | @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IMX) += imx_ccm.o | ||
22 | obj-$(CONFIG_IMX) += imx31_ccm.o | ||
23 | obj-$(CONFIG_IMX) += imx25_ccm.o | ||
24 | obj-$(CONFIG_IMX) += imx6_ccm.o | ||
25 | +obj-$(CONFIG_IMX) += imx6ul_ccm.o | ||
26 | obj-$(CONFIG_IMX) += imx6_src.o | ||
27 | obj-$(CONFIG_IMX) += imx7_ccm.o | ||
28 | obj-$(CONFIG_IMX) += imx2_wdt.o | ||
29 | diff --git a/include/hw/misc/imx6ul_ccm.h b/include/hw/misc/imx6ul_ccm.h | ||
30 | new file mode 100644 | 40 | new file mode 100644 |
31 | index XXXXXXX..XXXXXXX | 41 | index XXXXXXX..XXXXXXX |
32 | --- /dev/null | 42 | --- /dev/null |
33 | +++ b/include/hw/misc/imx6ul_ccm.h | 43 | +++ b/hw/usb/hcd-dwc2.c |
34 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ |
35 | +/* | 45 | +/* |
36 | + * IMX6UL Clock Control Module | 46 | + * dwc-hsotg (dwc2) USB host controller emulation |
37 | + * | 47 | + * |
38 | + * Copyright (C) 2018 by Jean-Christophe Dubois <jcd@tribudubois.net> | 48 | + * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c |
39 | + * | 49 | + * |
40 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 50 | + * Note that to use this emulation with the dwc-otg driver in the |
41 | + * See the COPYING file in the top-level directory. | 51 | + * Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=0" |
52 | + * on the kernel command line. | ||
53 | + * | ||
54 | + * Some useful documentation used to develop this emulation can be | ||
55 | + * found online (as of April 2020) at: | ||
56 | + * | ||
57 | + * http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf | ||
58 | + * which has a pretty complete description of the controller starting | ||
59 | + * on page 370. | ||
60 | + * | ||
61 | + * https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets/RT3050_5x_V2.0_081408_0902.pdf | ||
62 | + * which has a description of the controller registers starting on | ||
63 | + * page 130. | ||
64 | + * | ||
65 | + * Copyright (c) 2020 Paul Zimmerman <pauldzim@gmail.com> | ||
66 | + * | ||
67 | + * This program is free software; you can redistribute it and/or modify | ||
68 | + * it under the terms of the GNU General Public License as published by | ||
69 | + * the Free Software Foundation; either version 2 of the License, or | ||
70 | + * (at your option) any later version. | ||
71 | + * | ||
72 | + * This program is distributed in the hope that it will be useful, | ||
73 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
74 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
75 | + * GNU General Public License for more details. | ||
42 | + */ | 76 | + */ |
43 | + | 77 | + |
44 | +#ifndef IMX6UL_CCM_H | ||
45 | +#define IMX6UL_CCM_H | ||
46 | + | ||
47 | +#include "hw/misc/imx_ccm.h" | ||
48 | +#include "qemu/bitops.h" | ||
49 | + | ||
50 | +#define CCM_CCR 0 | ||
51 | +#define CCM_CCDR 1 | ||
52 | +#define CCM_CSR 2 | ||
53 | +#define CCM_CCSR 3 | ||
54 | +#define CCM_CACRR 4 | ||
55 | +#define CCM_CBCDR 5 | ||
56 | +#define CCM_CBCMR 6 | ||
57 | +#define CCM_CSCMR1 7 | ||
58 | +#define CCM_CSCMR2 8 | ||
59 | +#define CCM_CSCDR1 9 | ||
60 | +#define CCM_CS1CDR 10 | ||
61 | +#define CCM_CS2CDR 11 | ||
62 | +#define CCM_CDCDR 12 | ||
63 | +#define CCM_CHSCCDR 13 | ||
64 | +#define CCM_CSCDR2 14 | ||
65 | +#define CCM_CSCDR3 15 | ||
66 | +#define CCM_CDHIPR 18 | ||
67 | +#define CCM_CTOR 20 | ||
68 | +#define CCM_CLPCR 21 | ||
69 | +#define CCM_CISR 22 | ||
70 | +#define CCM_CIMR 23 | ||
71 | +#define CCM_CCOSR 24 | ||
72 | +#define CCM_CGPR 25 | ||
73 | +#define CCM_CCGR0 26 | ||
74 | +#define CCM_CCGR1 27 | ||
75 | +#define CCM_CCGR2 28 | ||
76 | +#define CCM_CCGR3 29 | ||
77 | +#define CCM_CCGR4 30 | ||
78 | +#define CCM_CCGR5 31 | ||
79 | +#define CCM_CCGR6 32 | ||
80 | +#define CCM_CMEOR 34 | ||
81 | +#define CCM_MAX 35 | ||
82 | + | ||
83 | +#define CCM_ANALOG_PLL_ARM 0 | ||
84 | +#define CCM_ANALOG_PLL_ARM_SET 1 | ||
85 | +#define CCM_ANALOG_PLL_ARM_CLR 2 | ||
86 | +#define CCM_ANALOG_PLL_ARM_TOG 3 | ||
87 | +#define CCM_ANALOG_PLL_USB1 4 | ||
88 | +#define CCM_ANALOG_PLL_USB1_SET 5 | ||
89 | +#define CCM_ANALOG_PLL_USB1_CLR 6 | ||
90 | +#define CCM_ANALOG_PLL_USB1_TOG 7 | ||
91 | +#define CCM_ANALOG_PLL_USB2 8 | ||
92 | +#define CCM_ANALOG_PLL_USB2_SET 9 | ||
93 | +#define CCM_ANALOG_PLL_USB2_CLR 10 | ||
94 | +#define CCM_ANALOG_PLL_USB2_TOG 11 | ||
95 | +#define CCM_ANALOG_PLL_SYS 12 | ||
96 | +#define CCM_ANALOG_PLL_SYS_SET 13 | ||
97 | +#define CCM_ANALOG_PLL_SYS_CLR 14 | ||
98 | +#define CCM_ANALOG_PLL_SYS_TOG 15 | ||
99 | +#define CCM_ANALOG_PLL_SYS_SS 16 | ||
100 | +#define CCM_ANALOG_PLL_SYS_NUM 20 | ||
101 | +#define CCM_ANALOG_PLL_SYS_DENOM 24 | ||
102 | +#define CCM_ANALOG_PLL_AUDIO 28 | ||
103 | +#define CCM_ANALOG_PLL_AUDIO_SET 29 | ||
104 | +#define CCM_ANALOG_PLL_AUDIO_CLR 30 | ||
105 | +#define CCM_ANALOG_PLL_AUDIO_TOG 31 | ||
106 | +#define CCM_ANALOG_PLL_AUDIO_NUM 32 | ||
107 | +#define CCM_ANALOG_PLL_AUDIO_DENOM 36 | ||
108 | +#define CCM_ANALOG_PLL_VIDEO 40 | ||
109 | +#define CCM_ANALOG_PLL_VIDEO_SET 41 | ||
110 | +#define CCM_ANALOG_PLL_VIDEO_CLR 42 | ||
111 | +#define CCM_ANALOG_PLL_VIDEO_TOG 44 | ||
112 | +#define CCM_ANALOG_PLL_VIDEO_NUM 46 | ||
113 | +#define CCM_ANALOG_PLL_VIDEO_DENOM 48 | ||
114 | +#define CCM_ANALOG_PLL_ENET 56 | ||
115 | +#define CCM_ANALOG_PLL_ENET_SET 57 | ||
116 | +#define CCM_ANALOG_PLL_ENET_CLR 58 | ||
117 | +#define CCM_ANALOG_PLL_ENET_TOG 59 | ||
118 | +#define CCM_ANALOG_PFD_480 60 | ||
119 | +#define CCM_ANALOG_PFD_480_SET 61 | ||
120 | +#define CCM_ANALOG_PFD_480_CLR 62 | ||
121 | +#define CCM_ANALOG_PFD_480_TOG 63 | ||
122 | +#define CCM_ANALOG_PFD_528 64 | ||
123 | +#define CCM_ANALOG_PFD_528_SET 65 | ||
124 | +#define CCM_ANALOG_PFD_528_CLR 66 | ||
125 | +#define CCM_ANALOG_PFD_528_TOG 67 | ||
126 | + | ||
127 | +/* PMU registers */ | ||
128 | +#define PMU_REG_1P1 68 | ||
129 | +#define PMU_REG_3P0 72 | ||
130 | +#define PMU_REG_2P5 76 | ||
131 | +#define PMU_REG_CORE 80 | ||
132 | + | ||
133 | +#define CCM_ANALOG_MISC0 84 | ||
134 | +#define PMU_MISC0 CCM_ANALOG_MISC0 | ||
135 | +#define CCM_ANALOG_MISC0_SET 85 | ||
136 | +#define PMU_MISC0_SET CCM_ANALOG_MISC0_SET | ||
137 | +#define CCM_ANALOG_MISC0_CLR 86 | ||
138 | +#define PMU_MISC0_CLR CCM_ANALOG_MISC0_CLR | ||
139 | +#define CCM_ANALOG_MISC0_TOG 87 | ||
140 | +#define PMU_MISC0_TOG CCM_ANALOG_MISC0_TOG | ||
141 | + | ||
142 | +#define CCM_ANALOG_MISC1 88 | ||
143 | +#define PMU_MISC1 CCM_ANALOG_MISC1 | ||
144 | +#define CCM_ANALOG_MISC1_SET 89 | ||
145 | +#define PMU_MISC1_SET CCM_ANALOG_MISC1_SET | ||
146 | +#define CCM_ANALOG_MISC1_CLR 90 | ||
147 | +#define PMU_MISC1_CLR CCM_ANALOG_MISC1_CLR | ||
148 | +#define CCM_ANALOG_MISC1_TOG 91 | ||
149 | +#define PMU_MISC1_TOG CCM_ANALOG_MISC1_TOG | ||
150 | + | ||
151 | +#define CCM_ANALOG_MISC2 92 | ||
152 | +#define PMU_MISC2 CCM_ANALOG_MISC2 | ||
153 | +#define CCM_ANALOG_MISC2_SET 93 | ||
154 | +#define PMU_MISC2_SET CCM_ANALOG_MISC2_SET | ||
155 | +#define CCM_ANALOG_MISC2_CLR 94 | ||
156 | +#define PMU_MISC2_CLR CCM_ANALOG_MISC2_CLR | ||
157 | +#define CCM_ANALOG_MISC2_TOG 95 | ||
158 | +#define PMU_MISC2_TOG CCM_ANALOG_MISC2_TOG | ||
159 | + | ||
160 | +#define TEMPMON_TEMPSENSE0 96 | ||
161 | +#define TEMPMON_TEMPSENSE0_SET 97 | ||
162 | +#define TEMPMON_TEMPSENSE0_CLR 98 | ||
163 | +#define TEMPMON_TEMPSENSE0_TOG 99 | ||
164 | +#define TEMPMON_TEMPSENSE1 100 | ||
165 | +#define TEMPMON_TEMPSENSE1_SET 101 | ||
166 | +#define TEMPMON_TEMPSENSE1_CLR 102 | ||
167 | +#define TEMPMON_TEMPSENSE1_TOG 103 | ||
168 | +#define TEMPMON_TEMPSENSE2 164 | ||
169 | +#define TEMPMON_TEMPSENSE2_SET 165 | ||
170 | +#define TEMPMON_TEMPSENSE2_CLR 166 | ||
171 | +#define TEMPMON_TEMPSENSE2_TOG 167 | ||
172 | + | ||
173 | +#define PMU_LOWPWR_CTRL 155 | ||
174 | +#define PMU_LOWPWR_CTRL_SET 156 | ||
175 | +#define PMU_LOWPWR_CTRL_CLR 157 | ||
176 | +#define PMU_LOWPWR_CTRL_TOG 158 | ||
177 | + | ||
178 | +#define USB_ANALOG_USB1_VBUS_DETECT 104 | ||
179 | +#define USB_ANALOG_USB1_VBUS_DETECT_SET 105 | ||
180 | +#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106 | ||
181 | +#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107 | ||
182 | +#define USB_ANALOG_USB1_CHRG_DETECT 108 | ||
183 | +#define USB_ANALOG_USB1_CHRG_DETECT_SET 109 | ||
184 | +#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110 | ||
185 | +#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111 | ||
186 | +#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112 | ||
187 | +#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116 | ||
188 | +#define USB_ANALOG_USB1_MISC 124 | ||
189 | +#define USB_ANALOG_USB1_MISC_SET 125 | ||
190 | +#define USB_ANALOG_USB1_MISC_CLR 126 | ||
191 | +#define USB_ANALOG_USB1_MISC_TOG 127 | ||
192 | +#define USB_ANALOG_USB2_VBUS_DETECT 128 | ||
193 | +#define USB_ANALOG_USB2_VBUS_DETECT_SET 129 | ||
194 | +#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130 | ||
195 | +#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131 | ||
196 | +#define USB_ANALOG_USB2_CHRG_DETECT 132 | ||
197 | +#define USB_ANALOG_USB2_CHRG_DETECT_SET 133 | ||
198 | +#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134 | ||
199 | +#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135 | ||
200 | +#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136 | ||
201 | +#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140 | ||
202 | +#define USB_ANALOG_USB2_MISC 148 | ||
203 | +#define USB_ANALOG_USB2_MISC_SET 149 | ||
204 | +#define USB_ANALOG_USB2_MISC_CLR 150 | ||
205 | +#define USB_ANALOG_USB2_MISC_TOG 151 | ||
206 | +#define USB_ANALOG_DIGPROG 152 | ||
207 | +#define CCM_ANALOG_MAX 4096 | ||
208 | + | ||
209 | +/* CCM_CBCMR */ | ||
210 | +#define R_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18) | ||
211 | +#define R_CBCMR_PRE_PERIPH_CLK_SEL_LENGTH (2) | ||
212 | +#define R_CBCMR_PERIPH_CLK2_SEL_SHIFT (12) | ||
213 | +#define R_CBCMR_PERIPH_CLK2_SEL_LENGTH (2) | ||
214 | + | ||
215 | +/* CCM_CBCDR */ | ||
216 | +#define R_CBCDR_AHB_PODF_SHIFT (10) | ||
217 | +#define R_CBCDR_AHB_PODF_LENGTH (3) | ||
218 | +#define R_CBCDR_IPG_PODF_SHIFT (8) | ||
219 | +#define R_CBCDR_IPG_PODF_LENGTH (2) | ||
220 | +#define R_CBCDR_PERIPH_CLK_SEL_SHIFT (25) | ||
221 | +#define R_CBCDR_PERIPH_CLK_SEL_LENGTH (1) | ||
222 | +#define R_CBCDR_PERIPH_CLK2_PODF_SHIFT (27) | ||
223 | +#define R_CBCDR_PERIPH_CLK2_PODF_LENGTH (3) | ||
224 | + | ||
225 | +/* CCM_CSCMR1 */ | ||
226 | +#define R_CSCMR1_PERCLK_PODF_SHIFT (0) | ||
227 | +#define R_CSCMR1_PERCLK_PODF_LENGTH (6) | ||
228 | +#define R_CSCMR1_PERCLK_CLK_SEL_SHIFT (6) | ||
229 | +#define R_CSCMR1_PERCLK_CLK_SEL_LENGTH (1) | ||
230 | + | ||
231 | +/* CCM_ANALOG_PFD_528 */ | ||
232 | +#define R_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0) | ||
233 | +#define R_ANALOG_PFD_528_PFD0_FRAC_LENGTH (6) | ||
234 | +#define R_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16) | ||
235 | +#define R_ANALOG_PFD_528_PFD2_FRAC_LENGTH (6) | ||
236 | + | ||
237 | +/* CCM_ANALOG_PLL_SYS */ | ||
238 | +#define R_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0) | ||
239 | +#define R_ANALOG_PLL_SYS_DIV_SELECT_LENGTH (1) | ||
240 | + | ||
241 | +#define CCM_ANALOG_PLL_LOCK (1 << 31); | ||
242 | + | ||
243 | +#define TYPE_IMX6UL_CCM "imx6ul.ccm" | ||
244 | +#define IMX6UL_CCM(obj) OBJECT_CHECK(IMX6ULCCMState, (obj), TYPE_IMX6UL_CCM) | ||
245 | + | ||
246 | +typedef struct IMX6ULCCMState { | ||
247 | + /* <private> */ | ||
248 | + IMXCCMState parent_obj; | ||
249 | + | ||
250 | + /* <public> */ | ||
251 | + MemoryRegion container; | ||
252 | + MemoryRegion ioccm; | ||
253 | + MemoryRegion ioanalog; | ||
254 | + | ||
255 | + uint32_t ccm[CCM_MAX]; | ||
256 | + uint32_t analog[CCM_ANALOG_MAX]; | ||
257 | + | ||
258 | +} IMX6ULCCMState; | ||
259 | + | ||
260 | +#endif /* IMX6UL_CCM_H */ | ||
261 | diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c | ||
262 | new file mode 100644 | ||
263 | index XXXXXXX..XXXXXXX | ||
264 | --- /dev/null | ||
265 | +++ b/hw/misc/imx6ul_ccm.c | ||
266 | @@ -XXX,XX +XXX,XX @@ | ||
267 | +/* | ||
268 | + * IMX6UL Clock Control Module | ||
269 | + * | ||
270 | + * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net> | ||
271 | + * | ||
272 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
273 | + * See the COPYING file in the top-level directory. | ||
274 | + * | ||
275 | + * To get the timer frequencies right, we need to emulate at least part of | ||
276 | + * the CCM. | ||
277 | + */ | ||
278 | + | ||
279 | +#include "qemu/osdep.h" | 78 | +#include "qemu/osdep.h" |
280 | +#include "hw/registerfields.h" | 79 | +#include "qemu/units.h" |
281 | +#include "hw/misc/imx6ul_ccm.h" | 80 | +#include "qapi/error.h" |
81 | +#include "hw/usb/dwc2-regs.h" | ||
82 | +#include "hw/usb/hcd-dwc2.h" | ||
83 | +#include "migration/vmstate.h" | ||
84 | +#include "trace.h" | ||
282 | +#include "qemu/log.h" | 85 | +#include "qemu/log.h" |
283 | + | 86 | +#include "qemu/error-report.h" |
284 | +#include "trace.h" | 87 | +#include "qemu/main-loop.h" |
285 | + | 88 | +#include "hw/qdev-properties.h" |
286 | +static const char *imx6ul_ccm_reg_name(uint32_t reg) | 89 | + |
287 | +{ | 90 | +#define USB_HZ_FS 12000000 |
288 | + static char unknown[20]; | 91 | +#define USB_HZ_HS 96000000 |
289 | + | 92 | +#define USB_FRMINTVL 12000 |
290 | + switch (reg) { | 93 | + |
291 | + case CCM_CCR: | 94 | +/* nifty macros from Arnon's EHCI version */ |
292 | + return "CCR"; | 95 | +#define get_field(data, field) \ |
293 | + case CCM_CCDR: | 96 | + (((data) & field##_MASK) >> field##_SHIFT) |
294 | + return "CCDR"; | 97 | + |
295 | + case CCM_CSR: | 98 | +#define set_field(data, newval, field) do { \ |
296 | + return "CSR"; | 99 | + uint32_t val = *(data); \ |
297 | + case CCM_CCSR: | 100 | + val &= ~field##_MASK; \ |
298 | + return "CCSR"; | 101 | + val |= ((newval) << field##_SHIFT) & field##_MASK; \ |
299 | + case CCM_CACRR: | 102 | + *(data) = val; \ |
300 | + return "CACRR"; | 103 | +} while (0) |
301 | + case CCM_CBCDR: | 104 | + |
302 | + return "CBCDR"; | 105 | +#define get_bit(data, bitmask) \ |
303 | + case CCM_CBCMR: | 106 | + (!!((data) & (bitmask))) |
304 | + return "CBCMR"; | 107 | + |
305 | + case CCM_CSCMR1: | 108 | +/* update irq line */ |
306 | + return "CSCMR1"; | 109 | +static inline void dwc2_update_irq(DWC2State *s) |
307 | + case CCM_CSCMR2: | 110 | +{ |
308 | + return "CSCMR2"; | 111 | + static int oldlevel; |
309 | + case CCM_CSCDR1: | 112 | + int level = 0; |
310 | + return "CSCDR1"; | 113 | + |
311 | + case CCM_CS1CDR: | 114 | + if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) { |
312 | + return "CS1CDR"; | 115 | + level = 1; |
313 | + case CCM_CS2CDR: | 116 | + } |
314 | + return "CS2CDR"; | 117 | + if (level != oldlevel) { |
315 | + case CCM_CDCDR: | 118 | + oldlevel = level; |
316 | + return "CDCDR"; | 119 | + trace_usb_dwc2_update_irq(level); |
317 | + case CCM_CHSCCDR: | 120 | + qemu_set_irq(s->irq, level); |
318 | + return "CHSCCDR"; | 121 | + } |
319 | + case CCM_CSCDR2: | 122 | +} |
320 | + return "CSCDR2"; | 123 | + |
321 | + case CCM_CSCDR3: | 124 | +/* flag interrupt condition */ |
322 | + return "CSCDR3"; | 125 | +static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr) |
323 | + case CCM_CDHIPR: | 126 | +{ |
324 | + return "CDHIPR"; | 127 | + if (!(s->gintsts & intr)) { |
325 | + case CCM_CTOR: | 128 | + s->gintsts |= intr; |
326 | + return "CTOR"; | 129 | + trace_usb_dwc2_raise_global_irq(intr); |
327 | + case CCM_CLPCR: | 130 | + dwc2_update_irq(s); |
328 | + return "CLPCR"; | 131 | + } |
329 | + case CCM_CISR: | 132 | +} |
330 | + return "CISR"; | 133 | + |
331 | + case CCM_CIMR: | 134 | +static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr) |
332 | + return "CIMR"; | 135 | +{ |
333 | + case CCM_CCOSR: | 136 | + if (s->gintsts & intr) { |
334 | + return "CCOSR"; | 137 | + s->gintsts &= ~intr; |
335 | + case CCM_CGPR: | 138 | + trace_usb_dwc2_lower_global_irq(intr); |
336 | + return "CGPR"; | 139 | + dwc2_update_irq(s); |
337 | + case CCM_CCGR0: | 140 | + } |
338 | + return "CCGR0"; | 141 | +} |
339 | + case CCM_CCGR1: | 142 | + |
340 | + return "CCGR1"; | 143 | +static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t host_intr) |
341 | + case CCM_CCGR2: | 144 | +{ |
342 | + return "CCGR2"; | 145 | + if (!(s->haint & host_intr)) { |
343 | + case CCM_CCGR3: | 146 | + s->haint |= host_intr; |
344 | + return "CCGR3"; | 147 | + s->haint &= 0xffff; |
345 | + case CCM_CCGR4: | 148 | + trace_usb_dwc2_raise_host_irq(host_intr); |
346 | + return "CCGR4"; | 149 | + if (s->haint & s->haintmsk) { |
347 | + case CCM_CCGR5: | 150 | + dwc2_raise_global_irq(s, GINTSTS_HCHINT); |
348 | + return "CCGR5"; | 151 | + } |
349 | + case CCM_CCGR6: | 152 | + } |
350 | + return "CCGR6"; | 153 | +} |
351 | + case CCM_CMEOR: | 154 | + |
352 | + return "CMEOR"; | 155 | +static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t host_intr) |
156 | +{ | ||
157 | + if (s->haint & host_intr) { | ||
158 | + s->haint &= ~host_intr; | ||
159 | + trace_usb_dwc2_lower_host_irq(host_intr); | ||
160 | + if (!(s->haint & s->haintmsk)) { | ||
161 | + dwc2_lower_global_irq(s, GINTSTS_HCHINT); | ||
162 | + } | ||
163 | + } | ||
164 | +} | ||
165 | + | ||
166 | +static inline void dwc2_update_hc_irq(DWC2State *s, int index) | ||
167 | +{ | ||
168 | + uint32_t host_intr = 1 << (index >> 3); | ||
169 | + | ||
170 | + if (s->hreg1[index + 2] & s->hreg1[index + 3]) { | ||
171 | + dwc2_raise_host_irq(s, host_intr); | ||
172 | + } else { | ||
173 | + dwc2_lower_host_irq(s, host_intr); | ||
174 | + } | ||
175 | +} | ||
176 | + | ||
177 | +/* set a timer for EOF */ | ||
178 | +static void dwc2_eof_timer(DWC2State *s) | ||
179 | +{ | ||
180 | + timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time); | ||
181 | +} | ||
182 | + | ||
183 | +/* Set a timer for EOF and generate SOF event */ | ||
184 | +static void dwc2_sof(DWC2State *s) | ||
185 | +{ | ||
186 | + s->sof_time += s->usb_frame_time; | ||
187 | + trace_usb_dwc2_sof(s->sof_time); | ||
188 | + dwc2_eof_timer(s); | ||
189 | + dwc2_raise_global_irq(s, GINTSTS_SOF); | ||
190 | +} | ||
191 | + | ||
192 | +/* Do frame processing on frame boundary */ | ||
193 | +static void dwc2_frame_boundary(void *opaque) | ||
194 | +{ | ||
195 | + DWC2State *s = opaque; | ||
196 | + int64_t now; | ||
197 | + uint16_t frcnt; | ||
198 | + | ||
199 | + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
200 | + | ||
201 | + /* Frame boundary, so do EOF stuff here */ | ||
202 | + | ||
203 | + /* Increment frame number */ | ||
204 | + frcnt = (uint16_t)((now - s->sof_time) / s->fi); | ||
205 | + s->frame_number = (s->frame_number + frcnt) & 0xffff; | ||
206 | + s->hfnum = s->frame_number & HFNUM_MAX_FRNUM; | ||
207 | + | ||
208 | + /* Do SOF stuff here */ | ||
209 | + dwc2_sof(s); | ||
210 | +} | ||
211 | + | ||
212 | +/* Start sending SOF tokens on the USB bus */ | ||
213 | +static void dwc2_bus_start(DWC2State *s) | ||
214 | +{ | ||
215 | + trace_usb_dwc2_bus_start(); | ||
216 | + s->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
217 | + dwc2_eof_timer(s); | ||
218 | +} | ||
219 | + | ||
220 | +/* Stop sending SOF tokens on the USB bus */ | ||
221 | +static void dwc2_bus_stop(DWC2State *s) | ||
222 | +{ | ||
223 | + trace_usb_dwc2_bus_stop(); | ||
224 | + timer_del(s->eof_timer); | ||
225 | +} | ||
226 | + | ||
227 | +static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr) | ||
228 | +{ | ||
229 | + USBDevice *dev; | ||
230 | + | ||
231 | + trace_usb_dwc2_find_device(addr); | ||
232 | + | ||
233 | + if (!(s->hprt0 & HPRT0_ENA)) { | ||
234 | + trace_usb_dwc2_port_disabled(0); | ||
235 | + } else { | ||
236 | + dev = usb_find_device(&s->uport, addr); | ||
237 | + if (dev != NULL) { | ||
238 | + trace_usb_dwc2_device_found(0); | ||
239 | + return dev; | ||
240 | + } | ||
241 | + } | ||
242 | + | ||
243 | + trace_usb_dwc2_device_not_found(); | ||
244 | + return NULL; | ||
245 | +} | ||
246 | + | ||
247 | +static const char *pstatus[] = { | ||
248 | + "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL", | ||
249 | + "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC", | ||
250 | + "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE" | ||
251 | +}; | ||
252 | + | ||
253 | +static uint32_t pintr[] = { | ||
254 | + HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL, | ||
255 | + HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, | ||
256 | + HCINTMSK_XACTERR | ||
257 | +}; | ||
258 | + | ||
259 | +static const char *types[] = { | ||
260 | + "Ctrl", "Isoc", "Bulk", "Intr" | ||
261 | +}; | ||
262 | + | ||
263 | +static const char *dirs[] = { | ||
264 | + "Out", "In" | ||
265 | +}; | ||
266 | + | ||
267 | +static void dwc2_handle_packet(DWC2State *s, uint32_t devadr, USBDevice *dev, | ||
268 | + USBEndpoint *ep, uint32_t index, bool send) | ||
269 | +{ | ||
270 | + DWC2Packet *p; | ||
271 | + uint32_t hcchar = s->hreg1[index]; | ||
272 | + uint32_t hctsiz = s->hreg1[index + 4]; | ||
273 | + uint32_t hcdma = s->hreg1[index + 5]; | ||
274 | + uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = 0; | ||
275 | + uint32_t tpcnt, stsidx, actual = 0; | ||
276 | + bool do_intr = false, done = false; | ||
277 | + | ||
278 | + epnum = get_field(hcchar, HCCHAR_EPNUM); | ||
279 | + epdir = get_bit(hcchar, HCCHAR_EPDIR); | ||
280 | + eptype = get_field(hcchar, HCCHAR_EPTYPE); | ||
281 | + mps = get_field(hcchar, HCCHAR_MPS); | ||
282 | + pid = get_field(hctsiz, TSIZ_SC_MC_PID); | ||
283 | + pcnt = get_field(hctsiz, TSIZ_PKTCNT); | ||
284 | + len = get_field(hctsiz, TSIZ_XFERSIZE); | ||
285 | + assert(len <= DWC2_MAX_XFER_SIZE); | ||
286 | + chan = index >> 3; | ||
287 | + p = &s->packet[chan]; | ||
288 | + | ||
289 | + trace_usb_dwc2_handle_packet(chan, dev, &p->packet, epnum, types[eptype], | ||
290 | + dirs[epdir], mps, len, pcnt); | ||
291 | + | ||
292 | + if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) { | ||
293 | + pid = USB_TOKEN_SETUP; | ||
294 | + } else { | ||
295 | + pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT; | ||
296 | + } | ||
297 | + | ||
298 | + if (send) { | ||
299 | + tlen = len; | ||
300 | + if (p->small) { | ||
301 | + if (tlen > mps) { | ||
302 | + tlen = mps; | ||
303 | + } | ||
304 | + } | ||
305 | + | ||
306 | + if (pid != USB_TOKEN_IN) { | ||
307 | + trace_usb_dwc2_memory_read(hcdma, tlen); | ||
308 | + if (dma_memory_read(&s->dma_as, hcdma, | ||
309 | + s->usb_buf[chan], tlen) != MEMTX_OK) { | ||
310 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed\n", | ||
311 | + __func__); | ||
312 | + } | ||
313 | + } | ||
314 | + | ||
315 | + usb_packet_init(&p->packet); | ||
316 | + usb_packet_setup(&p->packet, pid, ep, 0, hcdma, | ||
317 | + pid != USB_TOKEN_IN, true); | ||
318 | + usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen); | ||
319 | + p->async = DWC2_ASYNC_NONE; | ||
320 | + usb_handle_packet(dev, &p->packet); | ||
321 | + } else { | ||
322 | + tlen = p->len; | ||
323 | + } | ||
324 | + | ||
325 | + stsidx = -p->packet.status; | ||
326 | + assert(stsidx < sizeof(pstatus) / sizeof(*pstatus)); | ||
327 | + actual = p->packet.actual_length; | ||
328 | + trace_usb_dwc2_packet_status(pstatus[stsidx], actual); | ||
329 | + | ||
330 | +babble: | ||
331 | + if (p->packet.status != USB_RET_SUCCESS && | ||
332 | + p->packet.status != USB_RET_NAK && | ||
333 | + p->packet.status != USB_RET_STALL && | ||
334 | + p->packet.status != USB_RET_ASYNC) { | ||
335 | + trace_usb_dwc2_packet_error(pstatus[stsidx]); | ||
336 | + } | ||
337 | + | ||
338 | + if (p->packet.status == USB_RET_ASYNC) { | ||
339 | + trace_usb_dwc2_async_packet(&p->packet, chan, dev, epnum, | ||
340 | + dirs[epdir], tlen); | ||
341 | + usb_device_flush_ep_queue(dev, ep); | ||
342 | + assert(p->async != DWC2_ASYNC_INFLIGHT); | ||
343 | + p->devadr = devadr; | ||
344 | + p->epnum = epnum; | ||
345 | + p->epdir = epdir; | ||
346 | + p->mps = mps; | ||
347 | + p->pid = pid; | ||
348 | + p->index = index; | ||
349 | + p->pcnt = pcnt; | ||
350 | + p->len = tlen; | ||
351 | + p->async = DWC2_ASYNC_INFLIGHT; | ||
352 | + p->needs_service = false; | ||
353 | + return; | ||
354 | + } | ||
355 | + | ||
356 | + if (p->packet.status == USB_RET_SUCCESS) { | ||
357 | + if (actual > tlen) { | ||
358 | + p->packet.status = USB_RET_BABBLE; | ||
359 | + goto babble; | ||
360 | + } | ||
361 | + | ||
362 | + if (pid == USB_TOKEN_IN) { | ||
363 | + trace_usb_dwc2_memory_write(hcdma, actual); | ||
364 | + if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan], | ||
365 | + actual) != MEMTX_OK) { | ||
366 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write failed\n", | ||
367 | + __func__); | ||
368 | + } | ||
369 | + } | ||
370 | + | ||
371 | + tpcnt = actual / mps; | ||
372 | + if (actual % mps) { | ||
373 | + tpcnt++; | ||
374 | + if (pid == USB_TOKEN_IN) { | ||
375 | + done = true; | ||
376 | + } | ||
377 | + } | ||
378 | + | ||
379 | + pcnt -= tpcnt < pcnt ? tpcnt : pcnt; | ||
380 | + set_field(&hctsiz, pcnt, TSIZ_PKTCNT); | ||
381 | + len -= actual < len ? actual : len; | ||
382 | + set_field(&hctsiz, len, TSIZ_XFERSIZE); | ||
383 | + s->hreg1[index + 4] = hctsiz; | ||
384 | + hcdma += actual; | ||
385 | + s->hreg1[index + 5] = hcdma; | ||
386 | + | ||
387 | + if (!pcnt || len == 0 || actual == 0) { | ||
388 | + done = true; | ||
389 | + } | ||
390 | + } else { | ||
391 | + intr |= pintr[stsidx]; | ||
392 | + if (p->packet.status == USB_RET_NAK && | ||
393 | + (eptype == USB_ENDPOINT_XFER_CONTROL || | ||
394 | + eptype == USB_ENDPOINT_XFER_BULK)) { | ||
395 | + /* | ||
396 | + * for ctrl/bulk, automatically retry on NAK, | ||
397 | + * but send the interrupt anyway | ||
398 | + */ | ||
399 | + intr &= ~HCINTMSK_RESERVED14_31; | ||
400 | + s->hreg1[index + 2] |= intr; | ||
401 | + do_intr = true; | ||
402 | + } else { | ||
403 | + intr |= HCINTMSK_CHHLTD; | ||
404 | + done = true; | ||
405 | + } | ||
406 | + } | ||
407 | + | ||
408 | + usb_packet_cleanup(&p->packet); | ||
409 | + | ||
410 | + if (done) { | ||
411 | + hcchar &= ~HCCHAR_CHENA; | ||
412 | + s->hreg1[index] = hcchar; | ||
413 | + if (!(intr & HCINTMSK_CHHLTD)) { | ||
414 | + intr |= HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL; | ||
415 | + } | ||
416 | + intr &= ~HCINTMSK_RESERVED14_31; | ||
417 | + s->hreg1[index + 2] |= intr; | ||
418 | + p->needs_service = false; | ||
419 | + trace_usb_dwc2_packet_done(pstatus[stsidx], actual, len, pcnt); | ||
420 | + dwc2_update_hc_irq(s, index); | ||
421 | + return; | ||
422 | + } | ||
423 | + | ||
424 | + p->devadr = devadr; | ||
425 | + p->epnum = epnum; | ||
426 | + p->epdir = epdir; | ||
427 | + p->mps = mps; | ||
428 | + p->pid = pid; | ||
429 | + p->index = index; | ||
430 | + p->pcnt = pcnt; | ||
431 | + p->len = len; | ||
432 | + p->needs_service = true; | ||
433 | + trace_usb_dwc2_packet_next(pstatus[stsidx], len, pcnt); | ||
434 | + if (do_intr) { | ||
435 | + dwc2_update_hc_irq(s, index); | ||
436 | + } | ||
437 | +} | ||
438 | + | ||
439 | +/* Attach or detach a device on root hub */ | ||
440 | + | ||
441 | +static const char *speeds[] = { | ||
442 | + "low", "full", "high" | ||
443 | +}; | ||
444 | + | ||
445 | +static void dwc2_attach(USBPort *port) | ||
446 | +{ | ||
447 | + DWC2State *s = port->opaque; | ||
448 | + int hispd = 0; | ||
449 | + | ||
450 | + trace_usb_dwc2_attach(port); | ||
451 | + assert(port->index == 0); | ||
452 | + | ||
453 | + if (!port->dev || !port->dev->attached) { | ||
454 | + return; | ||
455 | + } | ||
456 | + | ||
457 | + assert(port->dev->speed <= USB_SPEED_HIGH); | ||
458 | + trace_usb_dwc2_attach_speed(speeds[port->dev->speed]); | ||
459 | + s->hprt0 &= ~HPRT0_SPD_MASK; | ||
460 | + | ||
461 | + switch (port->dev->speed) { | ||
462 | + case USB_SPEED_LOW: | ||
463 | + s->hprt0 |= HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT; | ||
464 | + break; | ||
465 | + case USB_SPEED_FULL: | ||
466 | + s->hprt0 |= HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT; | ||
467 | + break; | ||
468 | + case USB_SPEED_HIGH: | ||
469 | + s->hprt0 |= HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT; | ||
470 | + hispd = 1; | ||
471 | + break; | ||
472 | + } | ||
473 | + | ||
474 | + if (hispd) { | ||
475 | + s->usb_frame_time = NANOSECONDS_PER_SECOND / 8000; /* 125000 */ | ||
476 | + if (NANOSECONDS_PER_SECOND >= USB_HZ_HS) { | ||
477 | + s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.4 */ | ||
478 | + } else { | ||
479 | + s->usb_bit_time = 1; | ||
480 | + } | ||
481 | + } else { | ||
482 | + s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000; /* 1000000 */ | ||
483 | + if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) { | ||
484 | + s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */ | ||
485 | + } else { | ||
486 | + s->usb_bit_time = 1; | ||
487 | + } | ||
488 | + } | ||
489 | + | ||
490 | + s->fi = USB_FRMINTVL - 1; | ||
491 | + s->hprt0 |= HPRT0_CONNDET | HPRT0_CONNSTS; | ||
492 | + | ||
493 | + dwc2_bus_start(s); | ||
494 | + dwc2_raise_global_irq(s, GINTSTS_PRTINT); | ||
495 | +} | ||
496 | + | ||
497 | +static void dwc2_detach(USBPort *port) | ||
498 | +{ | ||
499 | + DWC2State *s = port->opaque; | ||
500 | + | ||
501 | + trace_usb_dwc2_detach(port); | ||
502 | + assert(port->index == 0); | ||
503 | + | ||
504 | + dwc2_bus_stop(s); | ||
505 | + | ||
506 | + s->hprt0 &= ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNSTS); | ||
507 | + s->hprt0 |= HPRT0_CONNDET | HPRT0_ENACHG; | ||
508 | + | ||
509 | + dwc2_raise_global_irq(s, GINTSTS_PRTINT); | ||
510 | +} | ||
511 | + | ||
512 | +static void dwc2_child_detach(USBPort *port, USBDevice *child) | ||
513 | +{ | ||
514 | + trace_usb_dwc2_child_detach(port, child); | ||
515 | + assert(port->index == 0); | ||
516 | +} | ||
517 | + | ||
518 | +static void dwc2_wakeup(USBPort *port) | ||
519 | +{ | ||
520 | + DWC2State *s = port->opaque; | ||
521 | + | ||
522 | + trace_usb_dwc2_wakeup(port); | ||
523 | + assert(port->index == 0); | ||
524 | + | ||
525 | + if (s->hprt0 & HPRT0_SUSP) { | ||
526 | + s->hprt0 |= HPRT0_RES; | ||
527 | + dwc2_raise_global_irq(s, GINTSTS_PRTINT); | ||
528 | + } | ||
529 | + | ||
530 | + qemu_bh_schedule(s->async_bh); | ||
531 | +} | ||
532 | + | ||
533 | +static void dwc2_async_packet_complete(USBPort *port, USBPacket *packet) | ||
534 | +{ | ||
535 | + DWC2State *s = port->opaque; | ||
536 | + DWC2Packet *p; | ||
537 | + USBDevice *dev; | ||
538 | + USBEndpoint *ep; | ||
539 | + | ||
540 | + assert(port->index == 0); | ||
541 | + p = container_of(packet, DWC2Packet, packet); | ||
542 | + dev = dwc2_find_device(s, p->devadr); | ||
543 | + ep = usb_ep_get(dev, p->pid, p->epnum); | ||
544 | + trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev, | ||
545 | + p->epnum, dirs[p->epdir], p->len); | ||
546 | + assert(p->async == DWC2_ASYNC_INFLIGHT); | ||
547 | + | ||
548 | + if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { | ||
549 | + usb_cancel_packet(packet); | ||
550 | + usb_packet_cleanup(packet); | ||
551 | + return; | ||
552 | + } | ||
553 | + | ||
554 | + dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false); | ||
555 | + | ||
556 | + p->async = DWC2_ASYNC_FINISHED; | ||
557 | + qemu_bh_schedule(s->async_bh); | ||
558 | +} | ||
559 | + | ||
560 | +static USBPortOps dwc2_port_ops = { | ||
561 | + .attach = dwc2_attach, | ||
562 | + .detach = dwc2_detach, | ||
563 | + .child_detach = dwc2_child_detach, | ||
564 | + .wakeup = dwc2_wakeup, | ||
565 | + .complete = dwc2_async_packet_complete, | ||
566 | +}; | ||
567 | + | ||
568 | +static uint32_t dwc2_get_frame_remaining(DWC2State *s) | ||
569 | +{ | ||
570 | + uint32_t fr = 0; | ||
571 | + int64_t tks; | ||
572 | + | ||
573 | + tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time; | ||
574 | + if (tks < 0) { | ||
575 | + tks = 0; | ||
576 | + } | ||
577 | + | ||
578 | + /* avoid muldiv if possible */ | ||
579 | + if (tks >= s->usb_frame_time) { | ||
580 | + goto out; | ||
581 | + } | ||
582 | + if (tks < s->usb_bit_time) { | ||
583 | + fr = s->fi; | ||
584 | + goto out; | ||
585 | + } | ||
586 | + | ||
587 | + /* tks = number of ns since SOF, divided by 83 (fs) or 10 (hs) */ | ||
588 | + tks = tks / s->usb_bit_time; | ||
589 | + if (tks >= (int64_t)s->fi) { | ||
590 | + goto out; | ||
591 | + } | ||
592 | + | ||
593 | + /* remaining = frame interval minus tks */ | ||
594 | + fr = (uint32_t)((int64_t)s->fi - tks); | ||
595 | + | ||
596 | +out: | ||
597 | + return fr; | ||
598 | +} | ||
599 | + | ||
600 | +static void dwc2_work_bh(void *opaque) | ||
601 | +{ | ||
602 | + DWC2State *s = opaque; | ||
603 | + DWC2Packet *p; | ||
604 | + USBDevice *dev; | ||
605 | + USBEndpoint *ep; | ||
606 | + int64_t t_now, expire_time; | ||
607 | + int chan; | ||
608 | + bool found = false; | ||
609 | + | ||
610 | + trace_usb_dwc2_work_bh(); | ||
611 | + if (s->working) { | ||
612 | + return; | ||
613 | + } | ||
614 | + s->working = true; | ||
615 | + | ||
616 | + t_now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | ||
617 | + chan = s->next_chan; | ||
618 | + | ||
619 | + do { | ||
620 | + p = &s->packet[chan]; | ||
621 | + if (p->needs_service) { | ||
622 | + dev = dwc2_find_device(s, p->devadr); | ||
623 | + ep = usb_ep_get(dev, p->pid, p->epnum); | ||
624 | + trace_usb_dwc2_work_bh_service(s->next_chan, chan, dev, p->epnum); | ||
625 | + dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true); | ||
626 | + found = true; | ||
627 | + } | ||
628 | + if (++chan == DWC2_NB_CHAN) { | ||
629 | + chan = 0; | ||
630 | + } | ||
631 | + if (found) { | ||
632 | + s->next_chan = chan; | ||
633 | + trace_usb_dwc2_work_bh_next(chan); | ||
634 | + } | ||
635 | + } while (chan != s->next_chan); | ||
636 | + | ||
637 | + if (found) { | ||
638 | + expire_time = t_now + NANOSECONDS_PER_SECOND / 4000; | ||
639 | + timer_mod(s->frame_timer, expire_time); | ||
640 | + } | ||
641 | + s->working = false; | ||
642 | +} | ||
643 | + | ||
644 | +static void dwc2_enable_chan(DWC2State *s, uint32_t index) | ||
645 | +{ | ||
646 | + USBDevice *dev; | ||
647 | + USBEndpoint *ep; | ||
648 | + uint32_t hcchar; | ||
649 | + uint32_t hctsiz; | ||
650 | + uint32_t devadr, epnum, epdir, eptype, pid, len; | ||
651 | + DWC2Packet *p; | ||
652 | + | ||
653 | + assert((index >> 3) < DWC2_NB_CHAN); | ||
654 | + p = &s->packet[index >> 3]; | ||
655 | + hcchar = s->hreg1[index]; | ||
656 | + hctsiz = s->hreg1[index + 4]; | ||
657 | + devadr = get_field(hcchar, HCCHAR_DEVADDR); | ||
658 | + epnum = get_field(hcchar, HCCHAR_EPNUM); | ||
659 | + epdir = get_bit(hcchar, HCCHAR_EPDIR); | ||
660 | + eptype = get_field(hcchar, HCCHAR_EPTYPE); | ||
661 | + pid = get_field(hctsiz, TSIZ_SC_MC_PID); | ||
662 | + len = get_field(hctsiz, TSIZ_XFERSIZE); | ||
663 | + | ||
664 | + dev = dwc2_find_device(s, devadr); | ||
665 | + | ||
666 | + trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum); | ||
667 | + if (dev == NULL) { | ||
668 | + return; | ||
669 | + } | ||
670 | + | ||
671 | + if (eptype == USB_ENDPOINT_XFER_CONTROL && pid == TSIZ_SC_MC_PID_SETUP) { | ||
672 | + pid = USB_TOKEN_SETUP; | ||
673 | + } else { | ||
674 | + pid = epdir ? USB_TOKEN_IN : USB_TOKEN_OUT; | ||
675 | + } | ||
676 | + | ||
677 | + ep = usb_ep_get(dev, pid, epnum); | ||
678 | + | ||
679 | + /* | ||
680 | + * Hack: Networking doesn't like us delivering large transfers, it kind | ||
681 | + * of works but the latency is horrible. So if the transfer is <= the mtu | ||
682 | + * size, we take that as a hint that this might be a network transfer, | ||
683 | + * and do the transfer packet-by-packet. | ||
684 | + */ | ||
685 | + if (len > 1536) { | ||
686 | + p->small = false; | ||
687 | + } else { | ||
688 | + p->small = true; | ||
689 | + } | ||
690 | + | ||
691 | + dwc2_handle_packet(s, devadr, dev, ep, index, true); | ||
692 | + qemu_bh_schedule(s->async_bh); | ||
693 | +} | ||
694 | + | ||
695 | +static const char *glbregnm[] = { | ||
696 | + "GOTGCTL ", "GOTGINT ", "GAHBCFG ", "GUSBCFG ", "GRSTCTL ", | ||
697 | + "GINTSTS ", "GINTMSK ", "GRXSTSR ", "GRXSTSP ", "GRXFSIZ ", | ||
698 | + "GNPTXFSIZ", "GNPTXSTS ", "GI2CCTL ", "GPVNDCTL ", "GGPIO ", | ||
699 | + "GUID ", "GSNPSID ", "GHWCFG1 ", "GHWCFG2 ", "GHWCFG3 ", | ||
700 | + "GHWCFG4 ", "GLPMCFG ", "GPWRDN ", "GDFIFOCFG", "GADPCTL ", | ||
701 | + "GREFCLK ", "GINTMSK2 ", "GINTSTS2 " | ||
702 | +}; | ||
703 | + | ||
704 | +static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index, | ||
705 | + unsigned size) | ||
706 | +{ | ||
707 | + DWC2State *s = ptr; | ||
708 | + uint32_t val; | ||
709 | + | ||
710 | + assert(addr <= GINTSTS2); | ||
711 | + val = s->glbreg[index]; | ||
712 | + | ||
713 | + switch (addr) { | ||
714 | + case GRSTCTL: | ||
715 | + /* clear any self-clearing bits that were set */ | ||
716 | + val &= ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLSH | | ||
717 | + GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST); | ||
718 | + s->glbreg[index] = val; | ||
719 | + break; | ||
353 | + default: | 720 | + default: |
354 | + sprintf(unknown, "%d ?", reg); | 721 | + break; |
355 | + return unknown; | 722 | + } |
356 | + } | 723 | + |
357 | +} | 724 | + trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val); |
358 | + | 725 | + return val; |
359 | +static const char *imx6ul_analog_reg_name(uint32_t reg) | 726 | +} |
360 | +{ | 727 | + |
361 | + static char unknown[20]; | 728 | +static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val, |
362 | + | 729 | + unsigned size) |
363 | + switch (reg) { | 730 | +{ |
364 | + case CCM_ANALOG_PLL_ARM: | 731 | + DWC2State *s = ptr; |
365 | + return "PLL_ARM"; | 732 | + uint64_t orig = val; |
366 | + case CCM_ANALOG_PLL_ARM_SET: | 733 | + uint32_t *mmio; |
367 | + return "PLL_ARM_SET"; | 734 | + uint32_t old; |
368 | + case CCM_ANALOG_PLL_ARM_CLR: | 735 | + int iflg = 0; |
369 | + return "PLL_ARM_CLR"; | 736 | + |
370 | + case CCM_ANALOG_PLL_ARM_TOG: | 737 | + assert(addr <= GINTSTS2); |
371 | + return "PLL_ARM_TOG"; | 738 | + mmio = &s->glbreg[index]; |
372 | + case CCM_ANALOG_PLL_USB1: | 739 | + old = *mmio; |
373 | + return "PLL_USB1"; | 740 | + |
374 | + case CCM_ANALOG_PLL_USB1_SET: | 741 | + switch (addr) { |
375 | + return "PLL_USB1_SET"; | 742 | + case GOTGCTL: |
376 | + case CCM_ANALOG_PLL_USB1_CLR: | 743 | + /* don't allow setting of read-only bits */ |
377 | + return "PLL_USB1_CLR"; | 744 | + val &= ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD | |
378 | + case CCM_ANALOG_PLL_USB1_TOG: | 745 | + GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B | |
379 | + return "PLL_USB1_TOG"; | 746 | + GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS); |
380 | + case CCM_ANALOG_PLL_USB2: | 747 | + /* don't allow clearing of read-only bits */ |
381 | + return "PLL_USB2"; | 748 | + val |= old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD | |
382 | + case CCM_ANALOG_PLL_USB2_SET: | 749 | + GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B | |
383 | + return "PLL_USB2_SET"; | 750 | + GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS); |
384 | + case CCM_ANALOG_PLL_USB2_CLR: | 751 | + break; |
385 | + return "PLL_USB2_CLR"; | 752 | + case GAHBCFG: |
386 | + case CCM_ANALOG_PLL_USB2_TOG: | 753 | + if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN)) { |
387 | + return "PLL_USB2_TOG"; | 754 | + iflg = 1; |
388 | + case CCM_ANALOG_PLL_SYS: | 755 | + } |
389 | + return "PLL_SYS"; | 756 | + break; |
390 | + case CCM_ANALOG_PLL_SYS_SET: | 757 | + case GRSTCTL: |
391 | + return "PLL_SYS_SET"; | 758 | + val |= GRSTCTL_AHBIDLE; |
392 | + case CCM_ANALOG_PLL_SYS_CLR: | 759 | + val &= ~GRSTCTL_DMAREQ; |
393 | + return "PLL_SYS_CLR"; | 760 | + if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) { |
394 | + case CCM_ANALOG_PLL_SYS_TOG: | 761 | + /* TODO - TX fifo flush */ |
395 | + return "PLL_SYS_TOG"; | 762 | + qemu_log_mask(LOG_UNIMP, "Tx FIFO flush not implemented\n"); |
396 | + case CCM_ANALOG_PLL_SYS_SS: | 763 | + } |
397 | + return "PLL_SYS_SS"; | 764 | + if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) { |
398 | + case CCM_ANALOG_PLL_SYS_NUM: | 765 | + /* TODO - RX fifo flush */ |
399 | + return "PLL_SYS_NUM"; | 766 | + qemu_log_mask(LOG_UNIMP, "Rx FIFO flush not implemented\n"); |
400 | + case CCM_ANALOG_PLL_SYS_DENOM: | 767 | + } |
401 | + return "PLL_SYS_DENOM"; | 768 | + if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH)) { |
402 | + case CCM_ANALOG_PLL_AUDIO: | 769 | + /* TODO - device IN token queue flush */ |
403 | + return "PLL_AUDIO"; | 770 | + qemu_log_mask(LOG_UNIMP, "Token queue flush not implemented\n"); |
404 | + case CCM_ANALOG_PLL_AUDIO_SET: | 771 | + } |
405 | + return "PLL_AUDIO_SET"; | 772 | + if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) { |
406 | + case CCM_ANALOG_PLL_AUDIO_CLR: | 773 | + /* TODO - host frame counter reset */ |
407 | + return "PLL_AUDIO_CLR"; | 774 | + qemu_log_mask(LOG_UNIMP, "Frame counter reset not implemented\n"); |
408 | + case CCM_ANALOG_PLL_AUDIO_TOG: | 775 | + } |
409 | + return "PLL_AUDIO_TOG"; | 776 | + if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) { |
410 | + case CCM_ANALOG_PLL_AUDIO_NUM: | 777 | + /* TODO - host soft reset */ |
411 | + return "PLL_AUDIO_NUM"; | 778 | + qemu_log_mask(LOG_UNIMP, "Host soft reset not implemented\n"); |
412 | + case CCM_ANALOG_PLL_AUDIO_DENOM: | 779 | + } |
413 | + return "PLL_AUDIO_DENOM"; | 780 | + if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) { |
414 | + case CCM_ANALOG_PLL_VIDEO: | 781 | + /* TODO - core soft reset */ |
415 | + return "PLL_VIDEO"; | 782 | + qemu_log_mask(LOG_UNIMP, "Core soft reset not implemented\n"); |
416 | + case CCM_ANALOG_PLL_VIDEO_SET: | 783 | + } |
417 | + return "PLL_VIDEO_SET"; | 784 | + /* don't allow clearing of self-clearing bits */ |
418 | + case CCM_ANALOG_PLL_VIDEO_CLR: | 785 | + val |= old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | |
419 | + return "PLL_VIDEO_CLR"; | 786 | + GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST | |
420 | + case CCM_ANALOG_PLL_VIDEO_TOG: | 787 | + GRSTCTL_HSFTRST | GRSTCTL_CSFTRST); |
421 | + return "PLL_VIDEO_TOG"; | 788 | + break; |
422 | + case CCM_ANALOG_PLL_VIDEO_NUM: | 789 | + case GINTSTS: |
423 | + return "PLL_VIDEO_NUM"; | 790 | + /* clear the write-1-to-clear bits */ |
424 | + case CCM_ANALOG_PLL_VIDEO_DENOM: | 791 | + val |= ~old; |
425 | + return "PLL_VIDEO_DENOM"; | 792 | + val = ~val; |
426 | + case CCM_ANALOG_PLL_ENET: | 793 | + /* don't allow clearing of read-only bits */ |
427 | + return "PLL_ENET"; | 794 | + val |= old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT | |
428 | + case CCM_ANALOG_PLL_ENET_SET: | 795 | + GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF | |
429 | + return "PLL_ENET_SET"; | 796 | + GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLVL | |
430 | + case CCM_ANALOG_PLL_ENET_CLR: | 797 | + GINTSTS_OTGINT | GINTSTS_CURMODE_HOST); |
431 | + return "PLL_ENET_CLR"; | 798 | + iflg = 1; |
432 | + case CCM_ANALOG_PLL_ENET_TOG: | 799 | + break; |
433 | + return "PLL_ENET_TOG"; | 800 | + case GINTMSK: |
434 | + case CCM_ANALOG_PFD_480: | 801 | + iflg = 1; |
435 | + return "PFD_480"; | 802 | + break; |
436 | + case CCM_ANALOG_PFD_480_SET: | ||
437 | + return "PFD_480_SET"; | ||
438 | + case CCM_ANALOG_PFD_480_CLR: | ||
439 | + return "PFD_480_CLR"; | ||
440 | + case CCM_ANALOG_PFD_480_TOG: | ||
441 | + return "PFD_480_TOG"; | ||
442 | + case CCM_ANALOG_PFD_528: | ||
443 | + return "PFD_528"; | ||
444 | + case CCM_ANALOG_PFD_528_SET: | ||
445 | + return "PFD_528_SET"; | ||
446 | + case CCM_ANALOG_PFD_528_CLR: | ||
447 | + return "PFD_528_CLR"; | ||
448 | + case CCM_ANALOG_PFD_528_TOG: | ||
449 | + return "PFD_528_TOG"; | ||
450 | + case CCM_ANALOG_MISC0: | ||
451 | + return "MISC0"; | ||
452 | + case CCM_ANALOG_MISC0_SET: | ||
453 | + return "MISC0_SET"; | ||
454 | + case CCM_ANALOG_MISC0_CLR: | ||
455 | + return "MISC0_CLR"; | ||
456 | + case CCM_ANALOG_MISC0_TOG: | ||
457 | + return "MISC0_TOG"; | ||
458 | + case CCM_ANALOG_MISC2: | ||
459 | + return "MISC2"; | ||
460 | + case CCM_ANALOG_MISC2_SET: | ||
461 | + return "MISC2_SET"; | ||
462 | + case CCM_ANALOG_MISC2_CLR: | ||
463 | + return "MISC2_CLR"; | ||
464 | + case CCM_ANALOG_MISC2_TOG: | ||
465 | + return "MISC2_TOG"; | ||
466 | + case PMU_REG_1P1: | ||
467 | + return "PMU_REG_1P1"; | ||
468 | + case PMU_REG_3P0: | ||
469 | + return "PMU_REG_3P0"; | ||
470 | + case PMU_REG_2P5: | ||
471 | + return "PMU_REG_2P5"; | ||
472 | + case PMU_REG_CORE: | ||
473 | + return "PMU_REG_CORE"; | ||
474 | + case PMU_MISC1: | ||
475 | + return "PMU_MISC1"; | ||
476 | + case PMU_MISC1_SET: | ||
477 | + return "PMU_MISC1_SET"; | ||
478 | + case PMU_MISC1_CLR: | ||
479 | + return "PMU_MISC1_CLR"; | ||
480 | + case PMU_MISC1_TOG: | ||
481 | + return "PMU_MISC1_TOG"; | ||
482 | + case USB_ANALOG_DIGPROG: | ||
483 | + return "USB_ANALOG_DIGPROG"; | ||
484 | + default: | 803 | + default: |
485 | + sprintf(unknown, "%d ?", reg); | 804 | + break; |
486 | + return unknown; | 805 | + } |
487 | + } | 806 | + |
488 | +} | 807 | + trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val); |
489 | + | 808 | + *mmio = val; |
490 | +#define CKIH_FREQ 24000000 /* 24MHz crystal input */ | 809 | + |
491 | + | 810 | + if (iflg) { |
492 | +static const VMStateDescription vmstate_imx6ul_ccm = { | 811 | + dwc2_update_irq(s); |
493 | + .name = TYPE_IMX6UL_CCM, | 812 | + } |
813 | +} | ||
814 | + | ||
815 | +static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index, | ||
816 | + unsigned size) | ||
817 | +{ | ||
818 | + DWC2State *s = ptr; | ||
819 | + uint32_t val; | ||
820 | + | ||
821 | + assert(addr == HPTXFSIZ); | ||
822 | + val = s->fszreg[index]; | ||
823 | + | ||
824 | + trace_usb_dwc2_fszreg_read(addr, val); | ||
825 | + return val; | ||
826 | +} | ||
827 | + | ||
828 | +static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val, | ||
829 | + unsigned size) | ||
830 | +{ | ||
831 | + DWC2State *s = ptr; | ||
832 | + uint64_t orig = val; | ||
833 | + uint32_t *mmio; | ||
834 | + uint32_t old; | ||
835 | + | ||
836 | + assert(addr == HPTXFSIZ); | ||
837 | + mmio = &s->fszreg[index]; | ||
838 | + old = *mmio; | ||
839 | + | ||
840 | + trace_usb_dwc2_fszreg_write(addr, orig, old, val); | ||
841 | + *mmio = val; | ||
842 | +} | ||
843 | + | ||
844 | +static const char *hreg0nm[] = { | ||
845 | + "HCFG ", "HFIR ", "HFNUM ", "<rsvd> ", "HPTXSTS ", | ||
846 | + "HAINT ", "HAINTMSK ", "HFLBADDR ", "<rsvd> ", "<rsvd> ", | ||
847 | + "<rsvd> ", "<rsvd> ", "<rsvd> ", "<rsvd> ", "<rsvd> ", | ||
848 | + "<rsvd> ", "HPRT0 " | ||
849 | +}; | ||
850 | + | ||
851 | +static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index, | ||
852 | + unsigned size) | ||
853 | +{ | ||
854 | + DWC2State *s = ptr; | ||
855 | + uint32_t val; | ||
856 | + | ||
857 | + assert(addr >= HCFG && addr <= HPRT0); | ||
858 | + val = s->hreg0[index]; | ||
859 | + | ||
860 | + switch (addr) { | ||
861 | + case HFNUM: | ||
862 | + val = (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) | | ||
863 | + (s->hfnum << HFNUM_FRNUM_SHIFT); | ||
864 | + break; | ||
865 | + default: | ||
866 | + break; | ||
867 | + } | ||
868 | + | ||
869 | + trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val); | ||
870 | + return val; | ||
871 | +} | ||
872 | + | ||
873 | +static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val, | ||
874 | + unsigned size) | ||
875 | +{ | ||
876 | + DWC2State *s = ptr; | ||
877 | + USBDevice *dev = s->uport.dev; | ||
878 | + uint64_t orig = val; | ||
879 | + uint32_t *mmio; | ||
880 | + uint32_t tval, told, old; | ||
881 | + int prst = 0; | ||
882 | + int iflg = 0; | ||
883 | + | ||
884 | + assert(addr >= HCFG && addr <= HPRT0); | ||
885 | + mmio = &s->hreg0[index]; | ||
886 | + old = *mmio; | ||
887 | + | ||
888 | + switch (addr) { | ||
889 | + case HFIR: | ||
890 | + break; | ||
891 | + case HFNUM: | ||
892 | + case HPTXSTS: | ||
893 | + case HAINT: | ||
894 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n", | ||
895 | + __func__); | ||
896 | + return; | ||
897 | + case HAINTMSK: | ||
898 | + val &= 0xffff; | ||
899 | + break; | ||
900 | + case HPRT0: | ||
901 | + /* don't allow clearing of read-only bits */ | ||
902 | + val |= old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRACT | | ||
903 | + HPRT0_CONNSTS); | ||
904 | + /* don't allow clearing of self-clearing bits */ | ||
905 | + val |= old & (HPRT0_SUSP | HPRT0_RES); | ||
906 | + /* don't allow setting of self-setting bits */ | ||
907 | + if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) { | ||
908 | + val &= ~HPRT0_ENA; | ||
909 | + } | ||
910 | + /* clear the write-1-to-clear bits */ | ||
911 | + tval = val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | | ||
912 | + HPRT0_CONNDET); | ||
913 | + told = old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | | ||
914 | + HPRT0_CONNDET); | ||
915 | + tval |= ~told; | ||
916 | + tval = ~tval; | ||
917 | + tval &= (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | | ||
918 | + HPRT0_CONNDET); | ||
919 | + val &= ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | | ||
920 | + HPRT0_CONNDET); | ||
921 | + val |= tval; | ||
922 | + if (!(val & HPRT0_RST) && (old & HPRT0_RST)) { | ||
923 | + if (dev && dev->attached) { | ||
924 | + val |= HPRT0_ENA | HPRT0_ENACHG; | ||
925 | + prst = 1; | ||
926 | + } | ||
927 | + } | ||
928 | + if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) { | ||
929 | + iflg = 1; | ||
930 | + } else { | ||
931 | + iflg = -1; | ||
932 | + } | ||
933 | + break; | ||
934 | + default: | ||
935 | + break; | ||
936 | + } | ||
937 | + | ||
938 | + if (prst) { | ||
939 | + trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, | ||
940 | + val & ~HPRT0_CONNDET); | ||
941 | + trace_usb_dwc2_hreg0_action("call usb_port_reset"); | ||
942 | + usb_port_reset(&s->uport); | ||
943 | + val &= ~HPRT0_CONNDET; | ||
944 | + } else { | ||
945 | + trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val); | ||
946 | + } | ||
947 | + | ||
948 | + *mmio = val; | ||
949 | + | ||
950 | + if (iflg > 0) { | ||
951 | + trace_usb_dwc2_hreg0_action("enable PRTINT"); | ||
952 | + dwc2_raise_global_irq(s, GINTSTS_PRTINT); | ||
953 | + } else if (iflg < 0) { | ||
954 | + trace_usb_dwc2_hreg0_action("disable PRTINT"); | ||
955 | + dwc2_lower_global_irq(s, GINTSTS_PRTINT); | ||
956 | + } | ||
957 | +} | ||
958 | + | ||
959 | +static const char *hreg1nm[] = { | ||
960 | + "HCCHAR ", "HCSPLT ", "HCINT ", "HCINTMSK", "HCTSIZ ", "HCDMA ", | ||
961 | + "<rsvd> ", "HCDMAB " | ||
962 | +}; | ||
963 | + | ||
964 | +static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index, | ||
965 | + unsigned size) | ||
966 | +{ | ||
967 | + DWC2State *s = ptr; | ||
968 | + uint32_t val; | ||
969 | + | ||
970 | + assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1)); | ||
971 | + val = s->hreg1[index]; | ||
972 | + | ||
973 | + trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val); | ||
974 | + return val; | ||
975 | +} | ||
976 | + | ||
977 | +static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val, | ||
978 | + unsigned size) | ||
979 | +{ | ||
980 | + DWC2State *s = ptr; | ||
981 | + uint64_t orig = val; | ||
982 | + uint32_t *mmio; | ||
983 | + uint32_t old; | ||
984 | + int iflg = 0; | ||
985 | + int enflg = 0; | ||
986 | + int disflg = 0; | ||
987 | + | ||
988 | + assert(addr >= HCCHAR(0) && addr <= HCDMAB(DWC2_NB_CHAN - 1)); | ||
989 | + mmio = &s->hreg1[index]; | ||
990 | + old = *mmio; | ||
991 | + | ||
992 | + switch (HSOTG_REG(0x500) + (addr & 0x1c)) { | ||
993 | + case HCCHAR(0): | ||
994 | + if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) { | ||
995 | + val &= ~(HCCHAR_CHENA | HCCHAR_CHDIS); | ||
996 | + disflg = 1; | ||
997 | + } else { | ||
998 | + val |= old & HCCHAR_CHDIS; | ||
999 | + if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) { | ||
1000 | + val &= ~HCCHAR_CHDIS; | ||
1001 | + enflg = 1; | ||
1002 | + } else { | ||
1003 | + val |= old & HCCHAR_CHENA; | ||
1004 | + } | ||
1005 | + } | ||
1006 | + break; | ||
1007 | + case HCINT(0): | ||
1008 | + /* clear the write-1-to-clear bits */ | ||
1009 | + val |= ~old; | ||
1010 | + val = ~val; | ||
1011 | + val &= ~HCINTMSK_RESERVED14_31; | ||
1012 | + iflg = 1; | ||
1013 | + break; | ||
1014 | + case HCINTMSK(0): | ||
1015 | + val &= ~HCINTMSK_RESERVED14_31; | ||
1016 | + iflg = 1; | ||
1017 | + break; | ||
1018 | + case HCDMAB(0): | ||
1019 | + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to read-only register\n", | ||
1020 | + __func__); | ||
1021 | + return; | ||
1022 | + default: | ||
1023 | + break; | ||
1024 | + } | ||
1025 | + | ||
1026 | + trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig, | ||
1027 | + old, val); | ||
1028 | + *mmio = val; | ||
1029 | + | ||
1030 | + if (disflg) { | ||
1031 | + /* set ChHltd in HCINT */ | ||
1032 | + s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD; | ||
1033 | + iflg = 1; | ||
1034 | + } | ||
1035 | + | ||
1036 | + if (enflg) { | ||
1037 | + dwc2_enable_chan(s, index & ~7); | ||
1038 | + } | ||
1039 | + | ||
1040 | + if (iflg) { | ||
1041 | + dwc2_update_hc_irq(s, index & ~7); | ||
1042 | + } | ||
1043 | +} | ||
1044 | + | ||
1045 | +static const char *pcgregnm[] = { | ||
1046 | + "PCGCTL ", "PCGCCTL1 " | ||
1047 | +}; | ||
1048 | + | ||
1049 | +static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index, | ||
1050 | + unsigned size) | ||
1051 | +{ | ||
1052 | + DWC2State *s = ptr; | ||
1053 | + uint32_t val; | ||
1054 | + | ||
1055 | + assert(addr >= PCGCTL && addr <= PCGCCTL1); | ||
1056 | + val = s->pcgreg[index]; | ||
1057 | + | ||
1058 | + trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val); | ||
1059 | + return val; | ||
1060 | +} | ||
1061 | + | ||
1062 | +static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index, | ||
1063 | + uint64_t val, unsigned size) | ||
1064 | +{ | ||
1065 | + DWC2State *s = ptr; | ||
1066 | + uint64_t orig = val; | ||
1067 | + uint32_t *mmio; | ||
1068 | + uint32_t old; | ||
1069 | + | ||
1070 | + assert(addr >= PCGCTL && addr <= PCGCCTL1); | ||
1071 | + mmio = &s->pcgreg[index]; | ||
1072 | + old = *mmio; | ||
1073 | + | ||
1074 | + trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val); | ||
1075 | + *mmio = val; | ||
1076 | +} | ||
1077 | + | ||
1078 | +static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size) | ||
1079 | +{ | ||
1080 | + uint64_t val; | ||
1081 | + | ||
1082 | + switch (addr) { | ||
1083 | + case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc): | ||
1084 | + val = dwc2_glbreg_read(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, size); | ||
1085 | + break; | ||
1086 | + case HSOTG_REG(0x100): | ||
1087 | + val = dwc2_fszreg_read(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, size); | ||
1088 | + break; | ||
1089 | + case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc): | ||
1090 | + /* Gadget-mode registers, just return 0 for now */ | ||
1091 | + val = 0; | ||
1092 | + break; | ||
1093 | + case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc): | ||
1094 | + val = dwc2_hreg0_read(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, size); | ||
1095 | + break; | ||
1096 | + case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc): | ||
1097 | + val = dwc2_hreg1_read(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, size); | ||
1098 | + break; | ||
1099 | + case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc): | ||
1100 | + /* Gadget-mode registers, just return 0 for now */ | ||
1101 | + val = 0; | ||
1102 | + break; | ||
1103 | + case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc): | ||
1104 | + val = dwc2_pcgreg_read(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, size); | ||
1105 | + break; | ||
1106 | + default: | ||
1107 | + g_assert_not_reached(); | ||
1108 | + } | ||
1109 | + | ||
1110 | + return val; | ||
1111 | +} | ||
1112 | + | ||
1113 | +static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val, | ||
1114 | + unsigned size) | ||
1115 | +{ | ||
1116 | + switch (addr) { | ||
1117 | + case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc): | ||
1118 | + dwc2_glbreg_write(ptr, addr, (addr - HSOTG_REG(0x000)) >> 2, val, size); | ||
1119 | + break; | ||
1120 | + case HSOTG_REG(0x100): | ||
1121 | + dwc2_fszreg_write(ptr, addr, (addr - HSOTG_REG(0x100)) >> 2, val, size); | ||
1122 | + break; | ||
1123 | + case HSOTG_REG(0x104) ... HSOTG_REG(0x3fc): | ||
1124 | + /* Gadget-mode registers, do nothing for now */ | ||
1125 | + break; | ||
1126 | + case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc): | ||
1127 | + dwc2_hreg0_write(ptr, addr, (addr - HSOTG_REG(0x400)) >> 2, val, size); | ||
1128 | + break; | ||
1129 | + case HSOTG_REG(0x500) ... HSOTG_REG(0x7fc): | ||
1130 | + dwc2_hreg1_write(ptr, addr, (addr - HSOTG_REG(0x500)) >> 2, val, size); | ||
1131 | + break; | ||
1132 | + case HSOTG_REG(0x800) ... HSOTG_REG(0xdfc): | ||
1133 | + /* Gadget-mode registers, do nothing for now */ | ||
1134 | + break; | ||
1135 | + case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc): | ||
1136 | + dwc2_pcgreg_write(ptr, addr, (addr - HSOTG_REG(0xe00)) >> 2, val, size); | ||
1137 | + break; | ||
1138 | + default: | ||
1139 | + g_assert_not_reached(); | ||
1140 | + } | ||
1141 | +} | ||
1142 | + | ||
1143 | +static const MemoryRegionOps dwc2_mmio_hsotg_ops = { | ||
1144 | + .read = dwc2_hsotg_read, | ||
1145 | + .write = dwc2_hsotg_write, | ||
1146 | + .impl.min_access_size = 4, | ||
1147 | + .impl.max_access_size = 4, | ||
1148 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
1149 | +}; | ||
1150 | + | ||
1151 | +static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size) | ||
1152 | +{ | ||
1153 | + /* TODO - implement FIFOs to support slave mode */ | ||
1154 | + trace_usb_dwc2_hreg2_read(addr, addr >> 12, 0); | ||
1155 | + qemu_log_mask(LOG_UNIMP, "FIFO read not implemented\n"); | ||
1156 | + return 0; | ||
1157 | +} | ||
1158 | + | ||
1159 | +static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val, | ||
1160 | + unsigned size) | ||
1161 | +{ | ||
1162 | + uint64_t orig = val; | ||
1163 | + | ||
1164 | + /* TODO - implement FIFOs to support slave mode */ | ||
1165 | + trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val); | ||
1166 | + qemu_log_mask(LOG_UNIMP, "FIFO write not implemented\n"); | ||
1167 | +} | ||
1168 | + | ||
1169 | +static const MemoryRegionOps dwc2_mmio_hreg2_ops = { | ||
1170 | + .read = dwc2_hreg2_read, | ||
1171 | + .write = dwc2_hreg2_write, | ||
1172 | + .impl.min_access_size = 4, | ||
1173 | + .impl.max_access_size = 4, | ||
1174 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
1175 | +}; | ||
1176 | + | ||
1177 | +static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, | ||
1178 | + unsigned int stream) | ||
1179 | +{ | ||
1180 | + DWC2State *s = container_of(bus, DWC2State, bus); | ||
1181 | + | ||
1182 | + trace_usb_dwc2_wakeup_endpoint(ep, stream); | ||
1183 | + | ||
1184 | + /* TODO - do something here? */ | ||
1185 | + qemu_bh_schedule(s->async_bh); | ||
1186 | +} | ||
1187 | + | ||
1188 | +static USBBusOps dwc2_bus_ops = { | ||
1189 | + .wakeup_endpoint = dwc2_wakeup_endpoint, | ||
1190 | +}; | ||
1191 | + | ||
1192 | +static void dwc2_work_timer(void *opaque) | ||
1193 | +{ | ||
1194 | + DWC2State *s = opaque; | ||
1195 | + | ||
1196 | + trace_usb_dwc2_work_timer(); | ||
1197 | + qemu_bh_schedule(s->async_bh); | ||
1198 | +} | ||
1199 | + | ||
1200 | +static void dwc2_reset_enter(Object *obj, ResetType type) | ||
1201 | +{ | ||
1202 | + DWC2Class *c = DWC2_GET_CLASS(obj); | ||
1203 | + DWC2State *s = DWC2_USB(obj); | ||
1204 | + int i; | ||
1205 | + | ||
1206 | + trace_usb_dwc2_reset_enter(); | ||
1207 | + | ||
1208 | + if (c->parent_phases.enter) { | ||
1209 | + c->parent_phases.enter(obj, type); | ||
1210 | + } | ||
1211 | + | ||
1212 | + timer_del(s->frame_timer); | ||
1213 | + qemu_bh_cancel(s->async_bh); | ||
1214 | + | ||
1215 | + if (s->uport.dev && s->uport.dev->attached) { | ||
1216 | + usb_detach(&s->uport); | ||
1217 | + } | ||
1218 | + | ||
1219 | + dwc2_bus_stop(s); | ||
1220 | + | ||
1221 | + s->gotgctl = GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B; | ||
1222 | + s->gotgint = 0; | ||
1223 | + s->gahbcfg = 0; | ||
1224 | + s->gusbcfg = 5 << GUSBCFG_USBTRDTIM_SHIFT; | ||
1225 | + s->grstctl = GRSTCTL_AHBIDLE; | ||
1226 | + s->gintsts = GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | | ||
1227 | + GINTSTS_CURMODE_HOST; | ||
1228 | + s->gintmsk = 0; | ||
1229 | + s->grxstsr = 0; | ||
1230 | + s->grxstsp = 0; | ||
1231 | + s->grxfsiz = 1024; | ||
1232 | + s->gnptxfsiz = 1024 << FIFOSIZE_DEPTH_SHIFT; | ||
1233 | + s->gnptxsts = (4 << FIFOSIZE_DEPTH_SHIFT) | 1024; | ||
1234 | + s->gi2cctl = GI2CCTL_I2CDATSE0 | GI2CCTL_ACK; | ||
1235 | + s->gpvndctl = 0; | ||
1236 | + s->ggpio = 0; | ||
1237 | + s->guid = 0; | ||
1238 | + s->gsnpsid = 0x4f54294a; | ||
1239 | + s->ghwcfg1 = 0; | ||
1240 | + s->ghwcfg2 = (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) | | ||
1241 | + (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) | | ||
1242 | + (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) | | ||
1243 | + GHWCFG2_DYNAMIC_FIFO | | ||
1244 | + GHWCFG2_PERIO_EP_SUPPORTED | | ||
1245 | + ((DWC2_NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) | | ||
1246 | + (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) | | ||
1247 | + (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_SHIFT); | ||
1248 | + s->ghwcfg3 = (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) | | ||
1249 | + (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) | | ||
1250 | + (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT); | ||
1251 | + s->ghwcfg4 = 0; | ||
1252 | + s->glpmcfg = 0; | ||
1253 | + s->gpwrdn = GPWRDN_PWRDNRSTN; | ||
1254 | + s->gdfifocfg = 0; | ||
1255 | + s->gadpctl = 0; | ||
1256 | + s->grefclk = 0; | ||
1257 | + s->gintmsk2 = 0; | ||
1258 | + s->gintsts2 = 0; | ||
1259 | + | ||
1260 | + s->hptxfsiz = 500 << FIFOSIZE_DEPTH_SHIFT; | ||
1261 | + | ||
1262 | + s->hcfg = 2 << HCFG_RESVALID_SHIFT; | ||
1263 | + s->hfir = 60000; | ||
1264 | + s->hfnum = 0x3fff; | ||
1265 | + s->hptxsts = (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768; | ||
1266 | + s->haint = 0; | ||
1267 | + s->haintmsk = 0; | ||
1268 | + s->hprt0 = 0; | ||
1269 | + | ||
1270 | + memset(s->hreg1, 0, sizeof(s->hreg1)); | ||
1271 | + memset(s->pcgreg, 0, sizeof(s->pcgreg)); | ||
1272 | + | ||
1273 | + s->sof_time = 0; | ||
1274 | + s->frame_number = 0; | ||
1275 | + s->fi = USB_FRMINTVL - 1; | ||
1276 | + s->next_chan = 0; | ||
1277 | + s->working = false; | ||
1278 | + | ||
1279 | + for (i = 0; i < DWC2_NB_CHAN; i++) { | ||
1280 | + s->packet[i].needs_service = false; | ||
1281 | + } | ||
1282 | +} | ||
1283 | + | ||
1284 | +static void dwc2_reset_hold(Object *obj) | ||
1285 | +{ | ||
1286 | + DWC2Class *c = DWC2_GET_CLASS(obj); | ||
1287 | + DWC2State *s = DWC2_USB(obj); | ||
1288 | + | ||
1289 | + trace_usb_dwc2_reset_hold(); | ||
1290 | + | ||
1291 | + if (c->parent_phases.hold) { | ||
1292 | + c->parent_phases.hold(obj); | ||
1293 | + } | ||
1294 | + | ||
1295 | + dwc2_update_irq(s); | ||
1296 | +} | ||
1297 | + | ||
1298 | +static void dwc2_reset_exit(Object *obj) | ||
1299 | +{ | ||
1300 | + DWC2Class *c = DWC2_GET_CLASS(obj); | ||
1301 | + DWC2State *s = DWC2_USB(obj); | ||
1302 | + | ||
1303 | + trace_usb_dwc2_reset_exit(); | ||
1304 | + | ||
1305 | + if (c->parent_phases.exit) { | ||
1306 | + c->parent_phases.exit(obj); | ||
1307 | + } | ||
1308 | + | ||
1309 | + s->hprt0 = HPRT0_PWR; | ||
1310 | + if (s->uport.dev && s->uport.dev->attached) { | ||
1311 | + usb_attach(&s->uport); | ||
1312 | + usb_device_reset(s->uport.dev); | ||
1313 | + } | ||
1314 | +} | ||
1315 | + | ||
1316 | +static void dwc2_realize(DeviceState *dev, Error **errp) | ||
1317 | +{ | ||
1318 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
1319 | + DWC2State *s = DWC2_USB(dev); | ||
1320 | + Object *obj; | ||
1321 | + Error *err = NULL; | ||
1322 | + | ||
1323 | + obj = object_property_get_link(OBJECT(dev), "dma-mr", &err); | ||
1324 | + if (err) { | ||
1325 | + error_setg(errp, "dwc2: required dma-mr link not found: %s", | ||
1326 | + error_get_pretty(err)); | ||
1327 | + return; | ||
1328 | + } | ||
1329 | + assert(obj != NULL); | ||
1330 | + | ||
1331 | + s->dma_mr = MEMORY_REGION(obj); | ||
1332 | + address_space_init(&s->dma_as, s->dma_mr, "dwc2"); | ||
1333 | + | ||
1334 | + usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev); | ||
1335 | + usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops, | ||
1336 | + USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL | | ||
1337 | + (s->usb_version == 2 ? USB_SPEED_MASK_HIGH : 0)); | ||
1338 | + s->uport.dev = 0; | ||
1339 | + | ||
1340 | + s->usb_frame_time = NANOSECONDS_PER_SECOND / 1000; /* 1000000 */ | ||
1341 | + if (NANOSECONDS_PER_SECOND >= USB_HZ_FS) { | ||
1342 | + s->usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 */ | ||
1343 | + } else { | ||
1344 | + s->usb_bit_time = 1; | ||
1345 | + } | ||
1346 | + | ||
1347 | + s->fi = USB_FRMINTVL - 1; | ||
1348 | + s->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_frame_boundary, s); | ||
1349 | + s->frame_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s); | ||
1350 | + s->async_bh = qemu_bh_new(dwc2_work_bh, s); | ||
1351 | + | ||
1352 | + sysbus_init_irq(sbd, &s->irq); | ||
1353 | +} | ||
1354 | + | ||
1355 | +static void dwc2_init(Object *obj) | ||
1356 | +{ | ||
1357 | + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
1358 | + DWC2State *s = DWC2_USB(obj); | ||
1359 | + | ||
1360 | + memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE); | ||
1361 | + sysbus_init_mmio(sbd, &s->container); | ||
1362 | + | ||
1363 | + memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s, | ||
1364 | + "dwc2-io", 4 * KiB); | ||
1365 | + memory_region_add_subregion(&s->container, 0x0000, &s->hsotg); | ||
1366 | + | ||
1367 | + memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s, | ||
1368 | + "dwc2-fifo", 64 * KiB); | ||
1369 | + memory_region_add_subregion(&s->container, 0x1000, &s->fifos); | ||
1370 | +} | ||
1371 | + | ||
1372 | +static const VMStateDescription vmstate_dwc2_state_packet = { | ||
1373 | + .name = "dwc2/packet", | ||
494 | + .version_id = 1, | 1374 | + .version_id = 1, |
495 | + .minimum_version_id = 1, | 1375 | + .minimum_version_id = 1, |
496 | + .fields = (VMStateField[]) { | 1376 | + .fields = (VMStateField[]) { |
497 | + VMSTATE_UINT32_ARRAY(ccm, IMX6ULCCMState, CCM_MAX), | 1377 | + VMSTATE_UINT32(devadr, DWC2Packet), |
498 | + VMSTATE_UINT32_ARRAY(analog, IMX6ULCCMState, CCM_ANALOG_MAX), | 1378 | + VMSTATE_UINT32(epnum, DWC2Packet), |
1379 | + VMSTATE_UINT32(epdir, DWC2Packet), | ||
1380 | + VMSTATE_UINT32(mps, DWC2Packet), | ||
1381 | + VMSTATE_UINT32(pid, DWC2Packet), | ||
1382 | + VMSTATE_UINT32(index, DWC2Packet), | ||
1383 | + VMSTATE_UINT32(pcnt, DWC2Packet), | ||
1384 | + VMSTATE_UINT32(len, DWC2Packet), | ||
1385 | + VMSTATE_INT32(async, DWC2Packet), | ||
1386 | + VMSTATE_BOOL(small, DWC2Packet), | ||
1387 | + VMSTATE_BOOL(needs_service, DWC2Packet), | ||
499 | + VMSTATE_END_OF_LIST() | 1388 | + VMSTATE_END_OF_LIST() |
500 | + }, | 1389 | + }, |
501 | +}; | 1390 | +}; |
502 | + | 1391 | + |
503 | +static uint64_t imx6ul_analog_get_osc_clk(IMX6ULCCMState *dev) | 1392 | +const VMStateDescription vmstate_dwc2_state = { |
504 | +{ | 1393 | + .name = "dwc2", |
505 | + uint64_t freq = CKIH_FREQ; | 1394 | + .version_id = 1, |
506 | + | 1395 | + .minimum_version_id = 1, |
507 | + trace_ccm_freq((uint32_t)freq); | 1396 | + .fields = (VMStateField[]) { |
508 | + | 1397 | + VMSTATE_UINT32_ARRAY(glbreg, DWC2State, |
509 | + return freq; | 1398 | + DWC2_GLBREG_SIZE / sizeof(uint32_t)), |
510 | +} | 1399 | + VMSTATE_UINT32_ARRAY(fszreg, DWC2State, |
511 | + | 1400 | + DWC2_FSZREG_SIZE / sizeof(uint32_t)), |
512 | +static uint64_t imx6ul_analog_get_pll2_clk(IMX6ULCCMState *dev) | 1401 | + VMSTATE_UINT32_ARRAY(hreg0, DWC2State, |
513 | +{ | 1402 | + DWC2_HREG0_SIZE / sizeof(uint32_t)), |
514 | + uint64_t freq = imx6ul_analog_get_osc_clk(dev); | 1403 | + VMSTATE_UINT32_ARRAY(hreg1, DWC2State, |
515 | + | 1404 | + DWC2_HREG1_SIZE / sizeof(uint32_t)), |
516 | + if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS], | 1405 | + VMSTATE_UINT32_ARRAY(pcgreg, DWC2State, |
517 | + ANALOG_PLL_SYS, DIV_SELECT)) { | 1406 | + DWC2_PCGREG_SIZE / sizeof(uint32_t)), |
518 | + freq *= 22; | 1407 | + |
519 | + } else { | 1408 | + VMSTATE_TIMER_PTR(eof_timer, DWC2State), |
520 | + freq *= 20; | 1409 | + VMSTATE_TIMER_PTR(frame_timer, DWC2State), |
521 | + } | 1410 | + VMSTATE_INT64(sof_time, DWC2State), |
522 | + | 1411 | + VMSTATE_INT64(usb_frame_time, DWC2State), |
523 | + trace_ccm_freq((uint32_t)freq); | 1412 | + VMSTATE_INT64(usb_bit_time, DWC2State), |
524 | + | 1413 | + VMSTATE_UINT32(usb_version, DWC2State), |
525 | + return freq; | 1414 | + VMSTATE_UINT16(frame_number, DWC2State), |
526 | +} | 1415 | + VMSTATE_UINT16(fi, DWC2State), |
527 | + | 1416 | + VMSTATE_UINT16(next_chan, DWC2State), |
528 | +static uint64_t imx6ul_analog_get_pll3_clk(IMX6ULCCMState *dev) | 1417 | + VMSTATE_BOOL(working, DWC2State), |
529 | +{ | 1418 | + |
530 | + uint64_t freq = imx6ul_analog_get_osc_clk(dev) * 20; | 1419 | + VMSTATE_STRUCT_ARRAY(packet, DWC2State, DWC2_NB_CHAN, 1, |
531 | + | 1420 | + vmstate_dwc2_state_packet, DWC2Packet), |
532 | + trace_ccm_freq((uint32_t)freq); | 1421 | + VMSTATE_UINT8_2DARRAY(usb_buf, DWC2State, DWC2_NB_CHAN, |
533 | + | 1422 | + DWC2_MAX_XFER_SIZE), |
534 | + return freq; | 1423 | + |
535 | +} | 1424 | + VMSTATE_END_OF_LIST() |
536 | + | 1425 | + } |
537 | +static uint64_t imx6ul_analog_get_pll2_pfd0_clk(IMX6ULCCMState *dev) | 1426 | +}; |
538 | +{ | 1427 | + |
539 | + uint64_t freq = 0; | 1428 | +static Property dwc2_usb_properties[] = { |
540 | + | 1429 | + DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2), |
541 | + freq = imx6ul_analog_get_pll2_clk(dev) * 18 | 1430 | + DEFINE_PROP_END_OF_LIST(), |
542 | + / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528], | 1431 | +}; |
543 | + ANALOG_PFD_528, PFD0_FRAC); | 1432 | + |
544 | + | 1433 | +static void dwc2_class_init(ObjectClass *klass, void *data) |
545 | + trace_ccm_freq((uint32_t)freq); | ||
546 | + | ||
547 | + return freq; | ||
548 | +} | ||
549 | + | ||
550 | +static uint64_t imx6ul_analog_get_pll2_pfd2_clk(IMX6ULCCMState *dev) | ||
551 | +{ | ||
552 | + uint64_t freq = 0; | ||
553 | + | ||
554 | + freq = imx6ul_analog_get_pll2_clk(dev) * 18 | ||
555 | + / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528], | ||
556 | + ANALOG_PFD_528, PFD2_FRAC); | ||
557 | + | ||
558 | + trace_ccm_freq((uint32_t)freq); | ||
559 | + | ||
560 | + return freq; | ||
561 | +} | ||
562 | + | ||
563 | +static uint64_t imx6ul_analog_pll2_bypass_clk(IMX6ULCCMState *dev) | ||
564 | +{ | ||
565 | + uint64_t freq = 0; | ||
566 | + | ||
567 | + trace_ccm_freq((uint32_t)freq); | ||
568 | + | ||
569 | + return freq; | ||
570 | +} | ||
571 | + | ||
572 | +static uint64_t imx6ul_ccm_get_periph_clk2_sel_clk(IMX6ULCCMState *dev) | ||
573 | +{ | ||
574 | + uint64_t freq = 0; | ||
575 | + | ||
576 | + switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) { | ||
577 | + case 0: | ||
578 | + freq = imx6ul_analog_get_pll3_clk(dev); | ||
579 | + break; | ||
580 | + case 1: | ||
581 | + freq = imx6ul_analog_get_osc_clk(dev); | ||
582 | + break; | ||
583 | + case 2: | ||
584 | + freq = imx6ul_analog_pll2_bypass_clk(dev); | ||
585 | + break; | ||
586 | + case 3: | ||
587 | + /* We should never get there as 3 is a reserved value */ | ||
588 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
589 | + "[%s]%s: unsupported PERIPH_CLK2_SEL value 3\n", | ||
590 | + TYPE_IMX6UL_CCM, __func__); | ||
591 | + /* freq is set to 0 as we don't know what it should be */ | ||
592 | + break; | ||
593 | + default: | ||
594 | + g_assert_not_reached(); | ||
595 | + } | ||
596 | + | ||
597 | + trace_ccm_freq((uint32_t)freq); | ||
598 | + | ||
599 | + return freq; | ||
600 | +} | ||
601 | + | ||
602 | +static uint64_t imx6ul_ccm_get_periph_clk_sel_clk(IMX6ULCCMState *dev) | ||
603 | +{ | ||
604 | + uint64_t freq = 0; | ||
605 | + | ||
606 | + switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) { | ||
607 | + case 0: | ||
608 | + freq = imx6ul_analog_get_pll2_clk(dev); | ||
609 | + break; | ||
610 | + case 1: | ||
611 | + freq = imx6ul_analog_get_pll2_pfd2_clk(dev); | ||
612 | + break; | ||
613 | + case 2: | ||
614 | + freq = imx6ul_analog_get_pll2_pfd0_clk(dev); | ||
615 | + break; | ||
616 | + case 3: | ||
617 | + freq = imx6ul_analog_get_pll2_pfd2_clk(dev) / 2; | ||
618 | + break; | ||
619 | + default: | ||
620 | + g_assert_not_reached(); | ||
621 | + } | ||
622 | + | ||
623 | + trace_ccm_freq((uint32_t)freq); | ||
624 | + | ||
625 | + return freq; | ||
626 | +} | ||
627 | + | ||
628 | +static uint64_t imx6ul_ccm_get_periph_clk2_clk(IMX6ULCCMState *dev) | ||
629 | +{ | ||
630 | + uint64_t freq = 0; | ||
631 | + | ||
632 | + freq = imx6ul_ccm_get_periph_clk2_sel_clk(dev) | ||
633 | + / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF)); | ||
634 | + | ||
635 | + trace_ccm_freq((uint32_t)freq); | ||
636 | + | ||
637 | + return freq; | ||
638 | +} | ||
639 | + | ||
640 | +static uint64_t imx6ul_ccm_get_periph_sel_clk(IMX6ULCCMState *dev) | ||
641 | +{ | ||
642 | + uint64_t freq = 0; | ||
643 | + | ||
644 | + switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) { | ||
645 | + case 0: | ||
646 | + freq = imx6ul_ccm_get_periph_clk_sel_clk(dev); | ||
647 | + break; | ||
648 | + case 1: | ||
649 | + freq = imx6ul_ccm_get_periph_clk2_clk(dev); | ||
650 | + break; | ||
651 | + default: | ||
652 | + g_assert_not_reached(); | ||
653 | + } | ||
654 | + | ||
655 | + trace_ccm_freq((uint32_t)freq); | ||
656 | + | ||
657 | + return freq; | ||
658 | +} | ||
659 | + | ||
660 | +static uint64_t imx6ul_ccm_get_ahb_clk(IMX6ULCCMState *dev) | ||
661 | +{ | ||
662 | + uint64_t freq = 0; | ||
663 | + | ||
664 | + freq = imx6ul_ccm_get_periph_sel_clk(dev) | ||
665 | + / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF)); | ||
666 | + | ||
667 | + trace_ccm_freq((uint32_t)freq); | ||
668 | + | ||
669 | + return freq; | ||
670 | +} | ||
671 | + | ||
672 | +static uint64_t imx6ul_ccm_get_ipg_clk(IMX6ULCCMState *dev) | ||
673 | +{ | ||
674 | + uint64_t freq = 0; | ||
675 | + | ||
676 | + freq = imx6ul_ccm_get_ahb_clk(dev) | ||
677 | + / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF)); | ||
678 | + | ||
679 | + trace_ccm_freq((uint32_t)freq); | ||
680 | + | ||
681 | + return freq; | ||
682 | +} | ||
683 | + | ||
684 | +static uint64_t imx6ul_ccm_get_per_sel_clk(IMX6ULCCMState *dev) | ||
685 | +{ | ||
686 | + uint64_t freq = 0; | ||
687 | + | ||
688 | + switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) { | ||
689 | + case 0: | ||
690 | + freq = imx6ul_ccm_get_ipg_clk(dev); | ||
691 | + break; | ||
692 | + case 1: | ||
693 | + freq = imx6ul_analog_get_osc_clk(dev); | ||
694 | + break; | ||
695 | + default: | ||
696 | + g_assert_not_reached(); | ||
697 | + } | ||
698 | + | ||
699 | + trace_ccm_freq((uint32_t)freq); | ||
700 | + | ||
701 | + return freq; | ||
702 | +} | ||
703 | + | ||
704 | +static uint64_t imx6ul_ccm_get_per_clk(IMX6ULCCMState *dev) | ||
705 | +{ | ||
706 | + uint64_t freq = 0; | ||
707 | + | ||
708 | + freq = imx6ul_ccm_get_per_sel_clk(dev) | ||
709 | + / (1 + FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_PODF)); | ||
710 | + | ||
711 | + trace_ccm_freq((uint32_t)freq); | ||
712 | + | ||
713 | + return freq; | ||
714 | +} | ||
715 | + | ||
716 | +static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock) | ||
717 | +{ | ||
718 | + uint32_t freq = 0; | ||
719 | + IMX6ULCCMState *s = IMX6UL_CCM(dev); | ||
720 | + | ||
721 | + switch (clock) { | ||
722 | + case CLK_NONE: | ||
723 | + break; | ||
724 | + case CLK_IPG: | ||
725 | + freq = imx6ul_ccm_get_ipg_clk(s); | ||
726 | + break; | ||
727 | + case CLK_IPG_HIGH: | ||
728 | + freq = imx6ul_ccm_get_per_clk(s); | ||
729 | + break; | ||
730 | + case CLK_32k: | ||
731 | + freq = CKIL_FREQ; | ||
732 | + break; | ||
733 | + case CLK_HIGH: | ||
734 | + freq = CKIH_FREQ; | ||
735 | + break; | ||
736 | + case CLK_HIGH_DIV: | ||
737 | + freq = CKIH_FREQ / 8; | ||
738 | + break; | ||
739 | + default: | ||
740 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n", | ||
741 | + TYPE_IMX6UL_CCM, __func__, clock); | ||
742 | + break; | ||
743 | + } | ||
744 | + | ||
745 | + trace_ccm_clock_freq(clock, freq); | ||
746 | + | ||
747 | + return freq; | ||
748 | +} | ||
749 | + | ||
750 | +static void imx6ul_ccm_reset(DeviceState *dev) | ||
751 | +{ | ||
752 | + IMX6ULCCMState *s = IMX6UL_CCM(dev); | ||
753 | + | ||
754 | + trace_ccm_entry(); | ||
755 | + | ||
756 | + s->ccm[CCM_CCR] = 0x0401167F; | ||
757 | + s->ccm[CCM_CCDR] = 0x00000000; | ||
758 | + s->ccm[CCM_CSR] = 0x00000010; | ||
759 | + s->ccm[CCM_CCSR] = 0x00000100; | ||
760 | + s->ccm[CCM_CACRR] = 0x00000000; | ||
761 | + s->ccm[CCM_CBCDR] = 0x00018D00; | ||
762 | + s->ccm[CCM_CBCMR] = 0x24860324; | ||
763 | + s->ccm[CCM_CSCMR1] = 0x04900080; | ||
764 | + s->ccm[CCM_CSCMR2] = 0x03192F06; | ||
765 | + s->ccm[CCM_CSCDR1] = 0x00490B00; | ||
766 | + s->ccm[CCM_CS1CDR] = 0x0EC102C1; | ||
767 | + s->ccm[CCM_CS2CDR] = 0x000336C1; | ||
768 | + s->ccm[CCM_CDCDR] = 0x33F71F92; | ||
769 | + s->ccm[CCM_CHSCCDR] = 0x000248A4; | ||
770 | + s->ccm[CCM_CSCDR2] = 0x00029B48; | ||
771 | + s->ccm[CCM_CSCDR3] = 0x00014841; | ||
772 | + s->ccm[CCM_CDHIPR] = 0x00000000; | ||
773 | + s->ccm[CCM_CTOR] = 0x00000000; | ||
774 | + s->ccm[CCM_CLPCR] = 0x00000079; | ||
775 | + s->ccm[CCM_CISR] = 0x00000000; | ||
776 | + s->ccm[CCM_CIMR] = 0xFFFFFFFF; | ||
777 | + s->ccm[CCM_CCOSR] = 0x000A0001; | ||
778 | + s->ccm[CCM_CGPR] = 0x0000FE62; | ||
779 | + s->ccm[CCM_CCGR0] = 0xFFFFFFFF; | ||
780 | + s->ccm[CCM_CCGR1] = 0xFFFFFFFF; | ||
781 | + s->ccm[CCM_CCGR2] = 0xFC3FFFFF; | ||
782 | + s->ccm[CCM_CCGR3] = 0xFFFFFFFF; | ||
783 | + s->ccm[CCM_CCGR4] = 0xFFFFFFFF; | ||
784 | + s->ccm[CCM_CCGR5] = 0xFFFFFFFF; | ||
785 | + s->ccm[CCM_CCGR6] = 0xFFFFFFFF; | ||
786 | + s->ccm[CCM_CMEOR] = 0xFFFFFFFF; | ||
787 | + | ||
788 | + s->analog[CCM_ANALOG_PLL_ARM] = 0x00013063; | ||
789 | + s->analog[CCM_ANALOG_PLL_USB1] = 0x00012000; | ||
790 | + s->analog[CCM_ANALOG_PLL_USB2] = 0x00012000; | ||
791 | + s->analog[CCM_ANALOG_PLL_SYS] = 0x00013001; | ||
792 | + s->analog[CCM_ANALOG_PLL_SYS_SS] = 0x00000000; | ||
793 | + s->analog[CCM_ANALOG_PLL_SYS_NUM] = 0x00000000; | ||
794 | + s->analog[CCM_ANALOG_PLL_SYS_DENOM] = 0x00000012; | ||
795 | + s->analog[CCM_ANALOG_PLL_AUDIO] = 0x00011006; | ||
796 | + s->analog[CCM_ANALOG_PLL_AUDIO_NUM] = 0x05F5E100; | ||
797 | + s->analog[CCM_ANALOG_PLL_AUDIO_DENOM] = 0x2964619C; | ||
798 | + s->analog[CCM_ANALOG_PLL_VIDEO] = 0x0001100C; | ||
799 | + s->analog[CCM_ANALOG_PLL_VIDEO_NUM] = 0x05F5E100; | ||
800 | + s->analog[CCM_ANALOG_PLL_VIDEO_DENOM] = 0x10A24447; | ||
801 | + s->analog[CCM_ANALOG_PLL_ENET] = 0x00011001; | ||
802 | + s->analog[CCM_ANALOG_PFD_480] = 0x1311100C; | ||
803 | + s->analog[CCM_ANALOG_PFD_528] = 0x1018101B; | ||
804 | + | ||
805 | + s->analog[PMU_REG_1P1] = 0x00001073; | ||
806 | + s->analog[PMU_REG_3P0] = 0x00000F74; | ||
807 | + s->analog[PMU_REG_2P5] = 0x00001073; | ||
808 | + s->analog[PMU_REG_CORE] = 0x00482012; | ||
809 | + s->analog[PMU_MISC0] = 0x04000000; | ||
810 | + s->analog[PMU_MISC1] = 0x00000000; | ||
811 | + s->analog[PMU_MISC2] = 0x00272727; | ||
812 | + s->analog[PMU_LOWPWR_CTRL] = 0x00004009; | ||
813 | + | ||
814 | + s->analog[USB_ANALOG_USB1_VBUS_DETECT] = 0x01000004; | ||
815 | + s->analog[USB_ANALOG_USB1_CHRG_DETECT] = 0x00000000; | ||
816 | + s->analog[USB_ANALOG_USB1_VBUS_DETECT_STAT] = 0x00000000; | ||
817 | + s->analog[USB_ANALOG_USB1_CHRG_DETECT_STAT] = 0x00000000; | ||
818 | + s->analog[USB_ANALOG_USB1_MISC] = 0x00000002; | ||
819 | + s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x01000004; | ||
820 | + s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000; | ||
821 | + s->analog[USB_ANALOG_USB2_MISC] = 0x00000002; | ||
822 | + s->analog[USB_ANALOG_DIGPROG] = 0x00640000; | ||
823 | + | ||
824 | + /* all PLLs need to be locked */ | ||
825 | + s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK; | ||
826 | + s->analog[CCM_ANALOG_PLL_USB1] |= CCM_ANALOG_PLL_LOCK; | ||
827 | + s->analog[CCM_ANALOG_PLL_USB2] |= CCM_ANALOG_PLL_LOCK; | ||
828 | + s->analog[CCM_ANALOG_PLL_SYS] |= CCM_ANALOG_PLL_LOCK; | ||
829 | + s->analog[CCM_ANALOG_PLL_AUDIO] |= CCM_ANALOG_PLL_LOCK; | ||
830 | + s->analog[CCM_ANALOG_PLL_VIDEO] |= CCM_ANALOG_PLL_LOCK; | ||
831 | + s->analog[CCM_ANALOG_PLL_ENET] |= CCM_ANALOG_PLL_LOCK; | ||
832 | + | ||
833 | + s->analog[TEMPMON_TEMPSENSE0] = 0x00000001; | ||
834 | + s->analog[TEMPMON_TEMPSENSE1] = 0x00000001; | ||
835 | + s->analog[TEMPMON_TEMPSENSE2] = 0x00000000; | ||
836 | +} | ||
837 | + | ||
838 | +static uint64_t imx6ul_ccm_read(void *opaque, hwaddr offset, unsigned size) | ||
839 | +{ | ||
840 | + uint32_t value = 0; | ||
841 | + uint32_t index = offset >> 2; | ||
842 | + IMX6ULCCMState *s = (IMX6ULCCMState *)opaque; | ||
843 | + | ||
844 | + assert(index < CCM_MAX); | ||
845 | + | ||
846 | + value = s->ccm[index]; | ||
847 | + | ||
848 | + trace_ccm_read_reg(imx6ul_ccm_reg_name(index), (uint32_t)value); | ||
849 | + | ||
850 | + return (uint64_t)value; | ||
851 | +} | ||
852 | + | ||
853 | +static void imx6ul_ccm_write(void *opaque, hwaddr offset, uint64_t value, | ||
854 | + unsigned size) | ||
855 | +{ | ||
856 | + uint32_t index = offset >> 2; | ||
857 | + IMX6ULCCMState *s = (IMX6ULCCMState *)opaque; | ||
858 | + | ||
859 | + assert(index < CCM_MAX); | ||
860 | + | ||
861 | + trace_ccm_write_reg(imx6ul_ccm_reg_name(index), (uint32_t)value); | ||
862 | + | ||
863 | + /* | ||
864 | + * We will do a better implementation later. In particular some bits | ||
865 | + * cannot be written to. | ||
866 | + */ | ||
867 | + s->ccm[index] = (uint32_t)value; | ||
868 | +} | ||
869 | + | ||
870 | +static uint64_t imx6ul_analog_read(void *opaque, hwaddr offset, unsigned size) | ||
871 | +{ | ||
872 | + uint32_t value; | ||
873 | + uint32_t index = offset >> 2; | ||
874 | + IMX6ULCCMState *s = (IMX6ULCCMState *)opaque; | ||
875 | + | ||
876 | + assert(index < CCM_ANALOG_MAX); | ||
877 | + | ||
878 | + switch (index) { | ||
879 | + case CCM_ANALOG_PLL_ARM_SET: | ||
880 | + case CCM_ANALOG_PLL_USB1_SET: | ||
881 | + case CCM_ANALOG_PLL_USB2_SET: | ||
882 | + case CCM_ANALOG_PLL_SYS_SET: | ||
883 | + case CCM_ANALOG_PLL_AUDIO_SET: | ||
884 | + case CCM_ANALOG_PLL_VIDEO_SET: | ||
885 | + case CCM_ANALOG_PLL_ENET_SET: | ||
886 | + case CCM_ANALOG_PFD_480_SET: | ||
887 | + case CCM_ANALOG_PFD_528_SET: | ||
888 | + case CCM_ANALOG_MISC0_SET: | ||
889 | + case PMU_MISC1_SET: | ||
890 | + case CCM_ANALOG_MISC2_SET: | ||
891 | + case USB_ANALOG_USB1_VBUS_DETECT_SET: | ||
892 | + case USB_ANALOG_USB1_CHRG_DETECT_SET: | ||
893 | + case USB_ANALOG_USB1_MISC_SET: | ||
894 | + case USB_ANALOG_USB2_VBUS_DETECT_SET: | ||
895 | + case USB_ANALOG_USB2_CHRG_DETECT_SET: | ||
896 | + case USB_ANALOG_USB2_MISC_SET: | ||
897 | + case TEMPMON_TEMPSENSE0_SET: | ||
898 | + case TEMPMON_TEMPSENSE1_SET: | ||
899 | + case TEMPMON_TEMPSENSE2_SET: | ||
900 | + /* | ||
901 | + * All REG_NAME_SET register access are in fact targeting | ||
902 | + * the REG_NAME register. | ||
903 | + */ | ||
904 | + value = s->analog[index - 1]; | ||
905 | + break; | ||
906 | + case CCM_ANALOG_PLL_ARM_CLR: | ||
907 | + case CCM_ANALOG_PLL_USB1_CLR: | ||
908 | + case CCM_ANALOG_PLL_USB2_CLR: | ||
909 | + case CCM_ANALOG_PLL_SYS_CLR: | ||
910 | + case CCM_ANALOG_PLL_AUDIO_CLR: | ||
911 | + case CCM_ANALOG_PLL_VIDEO_CLR: | ||
912 | + case CCM_ANALOG_PLL_ENET_CLR: | ||
913 | + case CCM_ANALOG_PFD_480_CLR: | ||
914 | + case CCM_ANALOG_PFD_528_CLR: | ||
915 | + case CCM_ANALOG_MISC0_CLR: | ||
916 | + case PMU_MISC1_CLR: | ||
917 | + case CCM_ANALOG_MISC2_CLR: | ||
918 | + case USB_ANALOG_USB1_VBUS_DETECT_CLR: | ||
919 | + case USB_ANALOG_USB1_CHRG_DETECT_CLR: | ||
920 | + case USB_ANALOG_USB1_MISC_CLR: | ||
921 | + case USB_ANALOG_USB2_VBUS_DETECT_CLR: | ||
922 | + case USB_ANALOG_USB2_CHRG_DETECT_CLR: | ||
923 | + case USB_ANALOG_USB2_MISC_CLR: | ||
924 | + case TEMPMON_TEMPSENSE0_CLR: | ||
925 | + case TEMPMON_TEMPSENSE1_CLR: | ||
926 | + case TEMPMON_TEMPSENSE2_CLR: | ||
927 | + /* | ||
928 | + * All REG_NAME_CLR register access are in fact targeting | ||
929 | + * the REG_NAME register. | ||
930 | + */ | ||
931 | + value = s->analog[index - 2]; | ||
932 | + break; | ||
933 | + case CCM_ANALOG_PLL_ARM_TOG: | ||
934 | + case CCM_ANALOG_PLL_USB1_TOG: | ||
935 | + case CCM_ANALOG_PLL_USB2_TOG: | ||
936 | + case CCM_ANALOG_PLL_SYS_TOG: | ||
937 | + case CCM_ANALOG_PLL_AUDIO_TOG: | ||
938 | + case CCM_ANALOG_PLL_VIDEO_TOG: | ||
939 | + case CCM_ANALOG_PLL_ENET_TOG: | ||
940 | + case CCM_ANALOG_PFD_480_TOG: | ||
941 | + case CCM_ANALOG_PFD_528_TOG: | ||
942 | + case CCM_ANALOG_MISC0_TOG: | ||
943 | + case PMU_MISC1_TOG: | ||
944 | + case CCM_ANALOG_MISC2_TOG: | ||
945 | + case USB_ANALOG_USB1_VBUS_DETECT_TOG: | ||
946 | + case USB_ANALOG_USB1_CHRG_DETECT_TOG: | ||
947 | + case USB_ANALOG_USB1_MISC_TOG: | ||
948 | + case USB_ANALOG_USB2_VBUS_DETECT_TOG: | ||
949 | + case USB_ANALOG_USB2_CHRG_DETECT_TOG: | ||
950 | + case USB_ANALOG_USB2_MISC_TOG: | ||
951 | + case TEMPMON_TEMPSENSE0_TOG: | ||
952 | + case TEMPMON_TEMPSENSE1_TOG: | ||
953 | + case TEMPMON_TEMPSENSE2_TOG: | ||
954 | + /* | ||
955 | + * All REG_NAME_TOG register access are in fact targeting | ||
956 | + * the REG_NAME register. | ||
957 | + */ | ||
958 | + value = s->analog[index - 3]; | ||
959 | + break; | ||
960 | + default: | ||
961 | + value = s->analog[index]; | ||
962 | + break; | ||
963 | + } | ||
964 | + | ||
965 | + trace_ccm_read_reg(imx6ul_analog_reg_name(index), (uint32_t)value); | ||
966 | + | ||
967 | + return (uint64_t)value; | ||
968 | +} | ||
969 | + | ||
970 | +static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value, | ||
971 | + unsigned size) | ||
972 | +{ | ||
973 | + uint32_t index = offset >> 2; | ||
974 | + IMX6ULCCMState *s = (IMX6ULCCMState *)opaque; | ||
975 | + | ||
976 | + assert(index < CCM_ANALOG_MAX); | ||
977 | + | ||
978 | + trace_ccm_write_reg(imx6ul_analog_reg_name(index), (uint32_t)value); | ||
979 | + | ||
980 | + switch (index) { | ||
981 | + case CCM_ANALOG_PLL_ARM_SET: | ||
982 | + case CCM_ANALOG_PLL_USB1_SET: | ||
983 | + case CCM_ANALOG_PLL_USB2_SET: | ||
984 | + case CCM_ANALOG_PLL_SYS_SET: | ||
985 | + case CCM_ANALOG_PLL_AUDIO_SET: | ||
986 | + case CCM_ANALOG_PLL_VIDEO_SET: | ||
987 | + case CCM_ANALOG_PLL_ENET_SET: | ||
988 | + case CCM_ANALOG_PFD_480_SET: | ||
989 | + case CCM_ANALOG_PFD_528_SET: | ||
990 | + case CCM_ANALOG_MISC0_SET: | ||
991 | + case PMU_MISC1_SET: | ||
992 | + case CCM_ANALOG_MISC2_SET: | ||
993 | + case USB_ANALOG_USB1_VBUS_DETECT_SET: | ||
994 | + case USB_ANALOG_USB1_CHRG_DETECT_SET: | ||
995 | + case USB_ANALOG_USB1_MISC_SET: | ||
996 | + case USB_ANALOG_USB2_VBUS_DETECT_SET: | ||
997 | + case USB_ANALOG_USB2_CHRG_DETECT_SET: | ||
998 | + case USB_ANALOG_USB2_MISC_SET: | ||
999 | + /* | ||
1000 | + * All REG_NAME_SET register access are in fact targeting | ||
1001 | + * the REG_NAME register. So we change the value of the | ||
1002 | + * REG_NAME register, setting bits passed in the value. | ||
1003 | + */ | ||
1004 | + s->analog[index - 1] |= value; | ||
1005 | + break; | ||
1006 | + case CCM_ANALOG_PLL_ARM_CLR: | ||
1007 | + case CCM_ANALOG_PLL_USB1_CLR: | ||
1008 | + case CCM_ANALOG_PLL_USB2_CLR: | ||
1009 | + case CCM_ANALOG_PLL_SYS_CLR: | ||
1010 | + case CCM_ANALOG_PLL_AUDIO_CLR: | ||
1011 | + case CCM_ANALOG_PLL_VIDEO_CLR: | ||
1012 | + case CCM_ANALOG_PLL_ENET_CLR: | ||
1013 | + case CCM_ANALOG_PFD_480_CLR: | ||
1014 | + case CCM_ANALOG_PFD_528_CLR: | ||
1015 | + case CCM_ANALOG_MISC0_CLR: | ||
1016 | + case PMU_MISC1_CLR: | ||
1017 | + case CCM_ANALOG_MISC2_CLR: | ||
1018 | + case USB_ANALOG_USB1_VBUS_DETECT_CLR: | ||
1019 | + case USB_ANALOG_USB1_CHRG_DETECT_CLR: | ||
1020 | + case USB_ANALOG_USB1_MISC_CLR: | ||
1021 | + case USB_ANALOG_USB2_VBUS_DETECT_CLR: | ||
1022 | + case USB_ANALOG_USB2_CHRG_DETECT_CLR: | ||
1023 | + case USB_ANALOG_USB2_MISC_CLR: | ||
1024 | + /* | ||
1025 | + * All REG_NAME_CLR register access are in fact targeting | ||
1026 | + * the REG_NAME register. So we change the value of the | ||
1027 | + * REG_NAME register, unsetting bits passed in the value. | ||
1028 | + */ | ||
1029 | + s->analog[index - 2] &= ~value; | ||
1030 | + break; | ||
1031 | + case CCM_ANALOG_PLL_ARM_TOG: | ||
1032 | + case CCM_ANALOG_PLL_USB1_TOG: | ||
1033 | + case CCM_ANALOG_PLL_USB2_TOG: | ||
1034 | + case CCM_ANALOG_PLL_SYS_TOG: | ||
1035 | + case CCM_ANALOG_PLL_AUDIO_TOG: | ||
1036 | + case CCM_ANALOG_PLL_VIDEO_TOG: | ||
1037 | + case CCM_ANALOG_PLL_ENET_TOG: | ||
1038 | + case CCM_ANALOG_PFD_480_TOG: | ||
1039 | + case CCM_ANALOG_PFD_528_TOG: | ||
1040 | + case CCM_ANALOG_MISC0_TOG: | ||
1041 | + case PMU_MISC1_TOG: | ||
1042 | + case CCM_ANALOG_MISC2_TOG: | ||
1043 | + case USB_ANALOG_USB1_VBUS_DETECT_TOG: | ||
1044 | + case USB_ANALOG_USB1_CHRG_DETECT_TOG: | ||
1045 | + case USB_ANALOG_USB1_MISC_TOG: | ||
1046 | + case USB_ANALOG_USB2_VBUS_DETECT_TOG: | ||
1047 | + case USB_ANALOG_USB2_CHRG_DETECT_TOG: | ||
1048 | + case USB_ANALOG_USB2_MISC_TOG: | ||
1049 | + /* | ||
1050 | + * All REG_NAME_TOG register access are in fact targeting | ||
1051 | + * the REG_NAME register. So we change the value of the | ||
1052 | + * REG_NAME register, toggling bits passed in the value. | ||
1053 | + */ | ||
1054 | + s->analog[index - 3] ^= value; | ||
1055 | + break; | ||
1056 | + default: | ||
1057 | + /* | ||
1058 | + * We will do a better implementation later. In particular some bits | ||
1059 | + * cannot be written to. | ||
1060 | + */ | ||
1061 | + s->analog[index] = value; | ||
1062 | + break; | ||
1063 | + } | ||
1064 | +} | ||
1065 | + | ||
1066 | +static const struct MemoryRegionOps imx6ul_ccm_ops = { | ||
1067 | + .read = imx6ul_ccm_read, | ||
1068 | + .write = imx6ul_ccm_write, | ||
1069 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
1070 | + .valid = { | ||
1071 | + /* | ||
1072 | + * Our device would not work correctly if the guest was doing | ||
1073 | + * unaligned access. This might not be a limitation on the real | ||
1074 | + * device but in practice there is no reason for a guest to access | ||
1075 | + * this device unaligned. | ||
1076 | + */ | ||
1077 | + .min_access_size = 4, | ||
1078 | + .max_access_size = 4, | ||
1079 | + .unaligned = false, | ||
1080 | + }, | ||
1081 | +}; | ||
1082 | + | ||
1083 | +static const struct MemoryRegionOps imx6ul_analog_ops = { | ||
1084 | + .read = imx6ul_analog_read, | ||
1085 | + .write = imx6ul_analog_write, | ||
1086 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
1087 | + .valid = { | ||
1088 | + /* | ||
1089 | + * Our device would not work correctly if the guest was doing | ||
1090 | + * unaligned access. This might not be a limitation on the real | ||
1091 | + * device but in practice there is no reason for a guest to access | ||
1092 | + * this device unaligned. | ||
1093 | + */ | ||
1094 | + .min_access_size = 4, | ||
1095 | + .max_access_size = 4, | ||
1096 | + .unaligned = false, | ||
1097 | + }, | ||
1098 | +}; | ||
1099 | + | ||
1100 | +static void imx6ul_ccm_init(Object *obj) | ||
1101 | +{ | ||
1102 | + DeviceState *dev = DEVICE(obj); | ||
1103 | + SysBusDevice *sd = SYS_BUS_DEVICE(obj); | ||
1104 | + IMX6ULCCMState *s = IMX6UL_CCM(obj); | ||
1105 | + | ||
1106 | + /* initialize a container for the all memory range */ | ||
1107 | + memory_region_init(&s->container, OBJECT(dev), TYPE_IMX6UL_CCM, 0x8000); | ||
1108 | + | ||
1109 | + /* We initialize an IO memory region for the CCM part */ | ||
1110 | + memory_region_init_io(&s->ioccm, OBJECT(dev), &imx6ul_ccm_ops, s, | ||
1111 | + TYPE_IMX6UL_CCM ".ccm", CCM_MAX * sizeof(uint32_t)); | ||
1112 | + | ||
1113 | + /* Add the CCM as a subregion at offset 0 */ | ||
1114 | + memory_region_add_subregion(&s->container, 0, &s->ioccm); | ||
1115 | + | ||
1116 | + /* We initialize an IO memory region for the ANALOG part */ | ||
1117 | + memory_region_init_io(&s->ioanalog, OBJECT(dev), &imx6ul_analog_ops, s, | ||
1118 | + TYPE_IMX6UL_CCM ".analog", | ||
1119 | + CCM_ANALOG_MAX * sizeof(uint32_t)); | ||
1120 | + | ||
1121 | + /* Add the ANALOG as a subregion at offset 0x4000 */ | ||
1122 | + memory_region_add_subregion(&s->container, 0x4000, &s->ioanalog); | ||
1123 | + | ||
1124 | + sysbus_init_mmio(sd, &s->container); | ||
1125 | +} | ||
1126 | + | ||
1127 | +static void imx6ul_ccm_class_init(ObjectClass *klass, void *data) | ||
1128 | +{ | 1434 | +{ |
1129 | + DeviceClass *dc = DEVICE_CLASS(klass); | 1435 | + DeviceClass *dc = DEVICE_CLASS(klass); |
1130 | + IMXCCMClass *ccm = IMX_CCM_CLASS(klass); | 1436 | + DWC2Class *c = DWC2_CLASS(klass); |
1131 | + | 1437 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
1132 | + dc->reset = imx6ul_ccm_reset; | 1438 | + |
1133 | + dc->vmsd = &vmstate_imx6ul_ccm; | 1439 | + dc->realize = dwc2_realize; |
1134 | + dc->desc = "i.MX6UL Clock Control Module"; | 1440 | + dc->vmsd = &vmstate_dwc2_state; |
1135 | + | 1441 | + set_bit(DEVICE_CATEGORY_USB, dc->categories); |
1136 | + ccm->get_clock_frequency = imx6ul_ccm_get_clock_frequency; | 1442 | + device_class_set_props(dc, dwc2_usb_properties); |
1137 | +} | 1443 | + resettable_class_set_parent_phases(rc, dwc2_reset_enter, dwc2_reset_hold, |
1138 | + | 1444 | + dwc2_reset_exit, &c->parent_phases); |
1139 | +static const TypeInfo imx6ul_ccm_info = { | 1445 | +} |
1140 | + .name = TYPE_IMX6UL_CCM, | 1446 | + |
1141 | + .parent = TYPE_IMX_CCM, | 1447 | +static const TypeInfo dwc2_usb_type_info = { |
1142 | + .instance_size = sizeof(IMX6ULCCMState), | 1448 | + .name = TYPE_DWC2_USB, |
1143 | + .instance_init = imx6ul_ccm_init, | 1449 | + .parent = TYPE_SYS_BUS_DEVICE, |
1144 | + .class_init = imx6ul_ccm_class_init, | 1450 | + .instance_size = sizeof(DWC2State), |
1145 | +}; | 1451 | + .instance_init = dwc2_init, |
1146 | + | 1452 | + .class_size = sizeof(DWC2Class), |
1147 | +static void imx6ul_ccm_register_types(void) | 1453 | + .class_init = dwc2_class_init, |
1148 | +{ | 1454 | +}; |
1149 | + type_register_static(&imx6ul_ccm_info); | 1455 | + |
1150 | +} | 1456 | +static void dwc2_usb_register_types(void) |
1151 | + | 1457 | +{ |
1152 | +type_init(imx6ul_ccm_register_types) | 1458 | + type_register_static(&dwc2_usb_type_info); |
1153 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | 1459 | +} |
1460 | + | ||
1461 | +type_init(dwc2_usb_register_types) | ||
1462 | diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig | ||
1154 | index XXXXXXX..XXXXXXX 100644 | 1463 | index XXXXXXX..XXXXXXX 100644 |
1155 | --- a/hw/misc/trace-events | 1464 | --- a/hw/usb/Kconfig |
1156 | +++ b/hw/misc/trace-events | 1465 | +++ b/hw/usb/Kconfig |
1157 | @@ -XXX,XX +XXX,XX @@ iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec | 1466 | @@ -XXX,XX +XXX,XX @@ config USB_MUSB |
1158 | iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u" | 1467 | bool |
1159 | iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" | 1468 | select USB |
1160 | iotkit_secctl_reset(void) "IoTKit SecCtl: reset" | 1469 | |
1161 | + | 1470 | +config USB_DWC2 |
1162 | +# hw/misc/imx6ul_ccm.c | 1471 | + bool |
1163 | +ccm_entry(void) "\n" | 1472 | + default y |
1164 | +ccm_freq(uint32_t freq) "freq = %d\n" | 1473 | + select USB |
1165 | +ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d\n" | 1474 | + |
1166 | +ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 "\n" | 1475 | config TUSB6010 |
1167 | +ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 "\n" | 1476 | bool |
1477 | select USB_MUSB | ||
1478 | diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs | ||
1479 | index XXXXXXX..XXXXXXX 100644 | ||
1480 | --- a/hw/usb/Makefile.objs | ||
1481 | +++ b/hw/usb/Makefile.objs | ||
1482 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) += hcd-ehci-sysbus.o | ||
1483 | common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o | ||
1484 | common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o | ||
1485 | common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o | ||
1486 | +common-obj-$(CONFIG_USB_DWC2) += hcd-dwc2.o | ||
1487 | |||
1488 | common-obj-$(CONFIG_TUSB6010) += tusb6010.o | ||
1489 | common-obj-$(CONFIG_IMX) += chipidea.o | ||
1490 | diff --git a/hw/usb/trace-events b/hw/usb/trace-events | ||
1491 | index XXXXXXX..XXXXXXX 100644 | ||
1492 | --- a/hw/usb/trace-events | ||
1493 | +++ b/hw/usb/trace-events | ||
1494 | @@ -XXX,XX +XXX,XX @@ usb_xhci_xfer_error(void *xfer, uint32_t ret) "%p: ret %d" | ||
1495 | usb_xhci_unimplemented(const char *item, int nr) "%s (0x%x)" | ||
1496 | usb_xhci_enforced_limit(const char *item) "%s" | ||
1497 | |||
1498 | +# hcd-dwc2.c | ||
1499 | +usb_dwc2_update_irq(uint32_t level) "level=%d" | ||
1500 | +usb_dwc2_raise_global_irq(uint32_t intr) "0x%08x" | ||
1501 | +usb_dwc2_lower_global_irq(uint32_t intr) "0x%08x" | ||
1502 | +usb_dwc2_raise_host_irq(uint32_t intr) "0x%04x" | ||
1503 | +usb_dwc2_lower_host_irq(uint32_t intr) "0x%04x" | ||
1504 | +usb_dwc2_sof(int64_t next) "next SOF %" PRId64 | ||
1505 | +usb_dwc2_bus_start(void) "start SOFs" | ||
1506 | +usb_dwc2_bus_stop(void) "stop SOFs" | ||
1507 | +usb_dwc2_find_device(uint8_t addr) "%d" | ||
1508 | +usb_dwc2_port_disabled(uint32_t pnum) "port %d disabled" | ||
1509 | +usb_dwc2_device_found(uint32_t pnum) "device found on port %d" | ||
1510 | +usb_dwc2_device_not_found(void) "device not found" | ||
1511 | +usb_dwc2_handle_packet(uint32_t chan, void *dev, void *pkt, uint32_t ep, const char *type, const char *dir, uint32_t mps, uint32_t len, uint32_t pcnt) "ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt %d" | ||
1512 | +usb_dwc2_memory_read(uint32_t addr, uint32_t len) "addr %d len %d" | ||
1513 | +usb_dwc2_packet_status(const char *status, uint32_t len) "status %s len %d" | ||
1514 | +usb_dwc2_packet_error(const char *status) "ERROR %s" | ||
1515 | +usb_dwc2_async_packet(void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "pkt %p ch %d dev %p ep %d %s len %d" | ||
1516 | +usb_dwc2_memory_write(uint32_t addr, uint32_t len) "addr %d len %d" | ||
1517 | +usb_dwc2_packet_done(const char *status, uint32_t actual, uint32_t len, uint32_t pcnt) "status %s actual %d len %d pcnt %d" | ||
1518 | +usb_dwc2_packet_next(const char *status, uint32_t len, uint32_t pcnt) "status %s len %d pcnt %d" | ||
1519 | +usb_dwc2_attach(void *port) "port %p" | ||
1520 | +usb_dwc2_attach_speed(const char *speed) "%s-speed device attached" | ||
1521 | +usb_dwc2_detach(void *port) "port %p" | ||
1522 | +usb_dwc2_child_detach(void *port, void *child) "port %p child %p" | ||
1523 | +usb_dwc2_wakeup(void *port) "port %p" | ||
1524 | +usb_dwc2_async_packet_complete(void *port, void *pkt, uint32_t chan, void *dev, uint32_t ep, const char *dir, uint32_t len) "port %p packet %p ch %d dev %p ep %d %s len %d" | ||
1525 | +usb_dwc2_work_bh(void) "" | ||
1526 | +usb_dwc2_work_bh_service(uint32_t first, uint32_t current, void *dev, uint32_t ep) "first %d servicing %d dev %p ep %d" | ||
1527 | +usb_dwc2_work_bh_next(uint32_t chan) "next %d" | ||
1528 | +usb_dwc2_enable_chan(uint32_t chan, void *dev, void *pkt, uint32_t ep) "ch %d dev %p pkt %p ep %d" | ||
1529 | +usb_dwc2_glbreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x" | ||
1530 | +usb_dwc2_glbreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64 | ||
1531 | +usb_dwc2_fszreg_read(uint64_t addr, uint32_t val) " 0x%04" PRIx64 " HPTXFSIZ val 0x%08x" | ||
1532 | +usb_dwc2_fszreg_write(uint64_t addr, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " HPTXFSIZ val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64 | ||
1533 | +usb_dwc2_hreg0_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x" | ||
1534 | +usb_dwc2_hreg0_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64 | ||
1535 | +usb_dwc2_hreg1_read(uint64_t addr, const char *reg, uint64_t chan, uint32_t val) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08x" | ||
1536 | +usb_dwc2_hreg1_write(uint64_t addr, const char *reg, uint64_t chan, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " %s%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64 | ||
1537 | +usb_dwc2_pcgreg_read(uint64_t addr, const char *reg, uint32_t val) " 0x%04" PRIx64 " %s val 0x%08x" | ||
1538 | +usb_dwc2_pcgreg_write(uint64_t addr, const char *reg, uint64_t val, uint32_t old, uint64_t result) "0x%04" PRIx64 " %s val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64 | ||
1539 | +usb_dwc2_hreg2_read(uint64_t addr, uint64_t fifo, uint32_t val) " 0x%04" PRIx64 " FIFO%" PRId64 " val 0x%08x" | ||
1540 | +usb_dwc2_hreg2_write(uint64_t addr, uint64_t fifo, uint64_t val, uint32_t old, uint64_t result) " 0x%04" PRIx64 " FIFO%" PRId64 " val 0x%08" PRIx64 " old 0x%08x result 0x%08" PRIx64 | ||
1541 | +usb_dwc2_hreg0_action(const char *s) "%s" | ||
1542 | +usb_dwc2_wakeup_endpoint(void *ep, uint32_t stream) "endp %p stream %d" | ||
1543 | +usb_dwc2_work_timer(void) "" | ||
1544 | +usb_dwc2_reset_enter(void) "=== RESET enter ===" | ||
1545 | +usb_dwc2_reset_hold(void) "=== RESET hold ===" | ||
1546 | +usb_dwc2_reset_exit(void) "=== RESET exit ===" | ||
1547 | + | ||
1548 | # desc.c | ||
1549 | usb_desc_device(int addr, int len, int ret) "dev %d query device, len %d, ret %d" | ||
1550 | usb_desc_device_qualifier(int addr, int len, int ret) "dev %d query device qualifier, len %d, ret %d" | ||
1168 | -- | 1551 | -- |
1169 | 2.18.0 | 1552 | 2.20.1 |
1170 | 1553 | ||
1171 | 1554 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | When FZ is set, input_denormal exceptions are recognized, but this does | 3 | The dwc-hsotg (dwc2) USB host depends on a short packet to |
4 | not happen with FZ16. The softfloat code has no way to distinguish | 4 | indicate the end of an IN transfer. The usb-storage driver |
5 | these bits and will raise such exceptions into fp_status_f16.flags, | 5 | currently doesn't provide this, so fix it. |
6 | so ignore them when computing the accumulated flags. | ||
7 | 6 | ||
8 | Cc: qemu-stable@nongnu.org (3.0.1) | 7 | I have tested this change rather extensively using a PC |
9 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 8 | emulation with xhci, ehci, and uhci controllers, and have |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | not observed any regressions. |
11 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 10 | |
12 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 11 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> |
13 | Message-id: 20180810193129.1556-3-richard.henderson@linaro.org | 12 | Message-id: 20200520235349.21215-6-pauldzim@gmail.com |
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 14 | --- |
16 | target/arm/helper.c | 6 +++++- | 15 | hw/usb/dev-storage.c | 15 ++++++++++++++- |
17 | 1 file changed, 5 insertions(+), 1 deletion(-) | 16 | 1 file changed, 14 insertions(+), 1 deletion(-) |
18 | 17 | ||
19 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 18 | diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c |
20 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/helper.c | 20 | --- a/hw/usb/dev-storage.c |
22 | +++ b/target/arm/helper.c | 21 | +++ b/hw/usb/dev-storage.c |
23 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | 22 | @@ -XXX,XX +XXX,XX @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p) |
24 | fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | 23 | usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len); |
25 | | (env->vfp.vec_len << 16) | 24 | s->scsi_len -= len; |
26 | | (env->vfp.vec_stride << 20); | 25 | s->scsi_off += len; |
27 | + | 26 | + if (len > s->data_len) { |
28 | i = get_float_exception_flags(&env->vfp.fp_status); | 27 | + len = s->data_len; |
29 | i |= get_float_exception_flags(&env->vfp.standard_fp_status); | 28 | + } |
30 | - i |= get_float_exception_flags(&env->vfp.fp_status_f16); | 29 | s->data_len -= len; |
31 | + /* FZ16 does not generate an input denormal exception. */ | 30 | if (s->scsi_len == 0 || s->data_len == 0) { |
32 | + i |= (get_float_exception_flags(&env->vfp.fp_status_f16) | 31 | scsi_req_continue(s->req); |
33 | + & ~float_flag_input_denormal); | 32 | @@ -XXX,XX +XXX,XX @@ static void usb_msd_command_complete(SCSIRequest *req, uint32_t status, size_t r |
34 | + | 33 | if (s->data_len) { |
35 | fpscr |= vfp_exceptbits_from_host(i); | 34 | int len = (p->iov.size - p->actual_length); |
36 | return fpscr; | 35 | usb_packet_skip(p, len); |
37 | } | 36 | + if (len > s->data_len) { |
37 | + len = s->data_len; | ||
38 | + } | ||
39 | s->data_len -= len; | ||
40 | } | ||
41 | if (s->data_len == 0) { | ||
42 | @@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p) | ||
43 | int len = p->iov.size - p->actual_length; | ||
44 | if (len) { | ||
45 | usb_packet_skip(p, len); | ||
46 | + if (len > s->data_len) { | ||
47 | + len = s->data_len; | ||
48 | + } | ||
49 | s->data_len -= len; | ||
50 | if (s->data_len == 0) { | ||
51 | s->mode = USB_MSDM_CSW; | ||
52 | @@ -XXX,XX +XXX,XX @@ static void usb_msd_handle_data(USBDevice *dev, USBPacket *p) | ||
53 | int len = p->iov.size - p->actual_length; | ||
54 | if (len) { | ||
55 | usb_packet_skip(p, len); | ||
56 | + if (len > s->data_len) { | ||
57 | + len = s->data_len; | ||
58 | + } | ||
59 | s->data_len -= len; | ||
60 | if (s->data_len == 0) { | ||
61 | s->mode = USB_MSDM_CSW; | ||
62 | } | ||
63 | } | ||
64 | } | ||
65 | - if (p->actual_length < p->iov.size) { | ||
66 | + if (p->actual_length < p->iov.size && (p->short_not_ok || | ||
67 | + s->scsi_len >= p->ep->max_packet_size)) { | ||
68 | DPRINTF("Deferring packet %p [wait data-in]\n", p); | ||
69 | s->packet = p; | ||
70 | p->status = USB_RET_ASYNC; | ||
38 | -- | 71 | -- |
39 | 2.18.0 | 72 | 2.20.1 |
40 | 73 | ||
41 | 74 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | The expression (int) imm + (uint32_t) len_align turns into uint32_t | 3 | Wire the dwc-hsotg (dwc2) emulation into Qemu |
4 | and thus with negative imm produces a memory operation at the wrong | ||
5 | offset. None of the numbers involved are particularly large, so | ||
6 | change everything to use int. | ||
7 | 4 | ||
8 | Cc: qemu-stable@nongnu.org (3.0.1) | 5 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> |
9 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 6 | Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Message-id: 20200520235349.21215-7-pauldzim@gmail.com |
11 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 9 | --- |
14 | target/arm/translate-sve.c | 18 ++++++++---------- | 10 | include/hw/arm/bcm2835_peripherals.h | 3 ++- |
15 | 1 file changed, 8 insertions(+), 10 deletions(-) | 11 | hw/arm/bcm2835_peripherals.c | 21 ++++++++++++++++++++- |
12 | 2 files changed, 22 insertions(+), 2 deletions(-) | ||
16 | 13 | ||
17 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 14 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/translate-sve.c | 16 | --- a/include/hw/arm/bcm2835_peripherals.h |
20 | +++ b/target/arm/translate-sve.c | 17 | +++ b/include/hw/arm/bcm2835_peripherals.h |
21 | @@ -XXX,XX +XXX,XX @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 18 | @@ -XXX,XX +XXX,XX @@ |
22 | * The load should begin at the address Rn + IMM. | 19 | #include "hw/sd/bcm2835_sdhost.h" |
23 | */ | 20 | #include "hw/gpio/bcm2835_gpio.h" |
24 | 21 | #include "hw/timer/bcm2835_systmr.h" | |
25 | -static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, | 22 | +#include "hw/usb/hcd-dwc2.h" |
26 | - int rn, int imm) | 23 | #include "hw/misc/unimp.h" |
27 | +static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | 24 | |
28 | { | 25 | #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" |
29 | - uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); | 26 | @@ -XXX,XX +XXX,XX @@ typedef struct BCM2835PeripheralState { |
30 | - uint32_t len_remain = len % 8; | 27 | UnimplementedDeviceState ave0; |
31 | - uint32_t nparts = len / 8 + ctpop8(len_remain); | 28 | UnimplementedDeviceState bscsl; |
32 | + int len_align = QEMU_ALIGN_DOWN(len, 8); | 29 | UnimplementedDeviceState smi; |
33 | + int len_remain = len % 8; | 30 | - UnimplementedDeviceState dwc2; |
34 | + int nparts = len / 8 + ctpop8(len_remain); | 31 | + DWC2State dwc2; |
35 | int midx = get_mem_index(s); | 32 | UnimplementedDeviceState sdramc; |
36 | TCGv_i64 addr, t0, t1; | 33 | } BCM2835PeripheralState; |
37 | 34 | ||
38 | @@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len, | 35 | diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c |
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/hw/arm/bcm2835_peripherals.c | ||
38 | +++ b/hw/arm/bcm2835_peripherals.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj) | ||
40 | /* Mphi */ | ||
41 | sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi), | ||
42 | TYPE_BCM2835_MPHI); | ||
43 | + | ||
44 | + /* DWC2 */ | ||
45 | + sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2), | ||
46 | + TYPE_DWC2_USB); | ||
47 | + | ||
48 | + object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", | ||
49 | + OBJECT(&s->gpu_bus_mr)); | ||
39 | } | 50 | } |
40 | 51 | ||
41 | /* Similarly for stores. */ | 52 | static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) |
42 | -static void do_str(DisasContext *s, uint32_t vofs, uint32_t len, | 53 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) |
43 | - int rn, int imm) | 54 | qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, |
44 | +static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm) | 55 | INTERRUPT_HOSTPORT)); |
45 | { | 56 | |
46 | - uint32_t len_align = QEMU_ALIGN_DOWN(len, 8); | 57 | + /* DWC2 */ |
47 | - uint32_t len_remain = len % 8; | 58 | + object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err); |
48 | - uint32_t nparts = len / 8 + ctpop8(len_remain); | 59 | + if (err) { |
49 | + int len_align = QEMU_ALIGN_DOWN(len, 8); | 60 | + error_propagate(errp, err); |
50 | + int len_remain = len % 8; | 61 | + return; |
51 | + int nparts = len / 8 + ctpop8(len_remain); | 62 | + } |
52 | int midx = get_mem_index(s); | 63 | + |
53 | TCGv_i64 addr, t0; | 64 | + memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET, |
65 | + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0)); | ||
66 | + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0, | ||
67 | + qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, | ||
68 | + INTERRUPT_USB)); | ||
69 | + | ||
70 | create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40); | ||
71 | create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); | ||
72 | create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); | ||
73 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) | ||
74 | create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80); | ||
75 | create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); | ||
76 | create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); | ||
77 | - create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000); | ||
78 | create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); | ||
79 | } | ||
54 | 80 | ||
55 | -- | 81 | -- |
56 | 2.18.0 | 82 | 2.20.1 |
57 | 83 | ||
58 | 84 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
2 | 1 | ||
3 | The immediate should be scaled by the size of the memory reference, | ||
4 | not the size of the elements into which it is loaded. | ||
5 | |||
6 | Cc: qemu-stable@nongnu.org (3.0.1) | ||
7 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/translate-sve.c | 3 ++- | ||
14 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate-sve.c | ||
19 | +++ b/target/arm/translate-sve.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) | ||
21 | unsigned vsz = vec_full_reg_size(s); | ||
22 | unsigned psz = pred_full_reg_size(s); | ||
23 | unsigned esz = dtype_esz[a->dtype]; | ||
24 | + unsigned msz = dtype_msz(a->dtype); | ||
25 | TCGLabel *over = gen_new_label(); | ||
26 | TCGv_i64 temp; | ||
27 | |||
28 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) | ||
29 | |||
30 | /* Load the data. */ | ||
31 | temp = tcg_temp_new_i64(); | ||
32 | - tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz); | ||
33 | + tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); | ||
34 | tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), | ||
35 | s->be_data | dtype_mop[a->dtype]); | ||
36 | |||
37 | -- | ||
38 | 2.18.0 | ||
39 | |||
40 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Paul Zimmerman <pauldzim@gmail.com> |
---|---|---|---|
2 | 2 | ||
3 | This is required to ensure u-boot SDRAM training completes. | 3 | Add a check for functional dwc-hsotg (dwc2) USB host emulation to |
4 | the Raspi 2 acceptance test | ||
4 | 5 | ||
5 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 6 | Signed-off-by: Paul Zimmerman <pauldzim@gmail.com> |
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 7 | Reviewed-by: Philippe Mathieu-Daude <f4bug@amsat.org> |
7 | Tested-by: Cédric Le Goater <clg@kaod.org> | 8 | Message-id: 20200520235349.21215-8-pauldzim@gmail.com |
8 | Message-id: 20180807075757.7242-6-joel@jms.id.au | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | hw/misc/aspeed_sdmc.c | 9 +++++++++ | 11 | tests/acceptance/boot_linux_console.py | 9 +++++++-- |
12 | 1 file changed, 9 insertions(+) | 12 | 1 file changed, 7 insertions(+), 2 deletions(-) |
13 | 13 | ||
14 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | 14 | diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/misc/aspeed_sdmc.c | 16 | --- a/tests/acceptance/boot_linux_console.py |
17 | +++ b/hw/misc/aspeed_sdmc.c | 17 | +++ b/tests/acceptance/boot_linux_console.py |
18 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ class BootLinuxConsole(LinuxKernelTest): |
19 | #define R_STATUS1 (0x60 / 4) | 19 | |
20 | #define PHY_BUSY_STATE BIT(0) | 20 | self.vm.set_console() |
21 | 21 | kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE + | |
22 | +#define R_ECC_TEST_CTRL (0x70 / 4) | 22 | - serial_kernel_cmdline[uart_id]) |
23 | +#define ECC_TEST_FINISHED BIT(12) | 23 | + serial_kernel_cmdline[uart_id] + |
24 | +#define ECC_TEST_FAIL BIT(13) | 24 | + ' root=/dev/mmcblk0p2 rootwait ' + |
25 | + | 25 | + 'dwc_otg.fiq_fsm_enable=0') |
26 | /* | 26 | self.vm.add_args('-kernel', kernel_path, |
27 | * Configuration register Ox4 (for Aspeed AST2400 SOC) | 27 | '-dtb', dtb_path, |
28 | * | 28 | - '-append', kernel_command_line) |
29 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | 29 | + '-append', kernel_command_line, |
30 | /* Will never return 'busy' */ | 30 | + '-device', 'usb-kbd') |
31 | data &= ~PHY_BUSY_STATE; | 31 | self.vm.launch() |
32 | break; | 32 | console_pattern = 'Kernel command line: %s' % kernel_command_line |
33 | + case R_ECC_TEST_CTRL: | 33 | self.wait_for_console_pattern(console_pattern) |
34 | + /* Always done, always happy */ | 34 | + console_pattern = 'Product: QEMU USB Keyboard' |
35 | + data |= ECC_TEST_FINISHED; | 35 | + self.wait_for_console_pattern(console_pattern) |
36 | + data &= ~ECC_TEST_FAIL; | 36 | |
37 | + break; | 37 | def test_arm_raspi2_uart0(self): |
38 | default: | 38 | """ |
39 | break; | ||
40 | } | ||
41 | -- | 39 | -- |
42 | 2.18.0 | 40 | 2.20.1 |
43 | 41 | ||
44 | 42 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift |
---|---|---|---|
2 | group to decodetree. | ||
2 | 3 | ||
3 | When support for FZ16 was added, we failed to include the bit | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | within FPCR_MASK, which means that it could never be set. | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Continue to zero FZ16 when ARMv8.2-FP16 is not enabled. | 6 | Message-id: 20200522145520.6778-2-peter.maydell@linaro.org |
7 | --- | ||
8 | target/arm/neon-dp.decode | 25 ++++++++++++++++++++++ | ||
9 | target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 18 +++++++--------- | ||
11 | 3 files changed, 71 insertions(+), 10 deletions(-) | ||
6 | 12 | ||
7 | Fixes: d81ce0ef2c4 | 13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode |
8 | Cc: qemu-stable@nongnu.org (3.0.1) | ||
9 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
12 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
13 | Message-id: 20180810193129.1556-2-richard.henderson@linaro.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | target/arm/cpu.h | 2 +- | ||
17 | target/arm/helper.c | 5 +++++ | ||
18 | 2 files changed, 6 insertions(+), 1 deletion(-) | ||
19 | |||
20 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/neon-dp.decode |
23 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/neon-dp.decode |
24 | @@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); | 17 | @@ -XXX,XX +XXX,XX @@ VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp |
25 | * we store the underlying state in fpscr and just mask on read/write. | 18 | VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp |
26 | */ | 19 | VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp |
27 | #define FPSR_MASK 0xf800009f | 20 | VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp |
28 | -#define FPCR_MASK 0x07f79f00 | 21 | + |
29 | +#define FPCR_MASK 0x07ff9f00 | 22 | +###################################################################### |
30 | 23 | +# 2-reg-and-shift grouping: | |
31 | #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ | 24 | +# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4 |
32 | #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ | 25 | +###################################################################### |
33 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 26 | +&2reg_shift vm vd q shift size |
27 | + | ||
28 | +@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \ | ||
29 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=3 | ||
30 | +@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \ | ||
31 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=2 | ||
32 | +@2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \ | ||
33 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=1 | ||
34 | +@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \ | ||
35 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=0 | ||
36 | + | ||
37 | +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d | ||
38 | +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s | ||
39 | +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h | ||
40 | +VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b | ||
41 | + | ||
42 | +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d | ||
43 | +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s | ||
44 | +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h | ||
45 | +VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b | ||
46 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | 47 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/helper.c | 48 | --- a/target/arm/translate-neon.inc.c |
36 | +++ b/target/arm/helper.c | 49 | +++ b/target/arm/translate-neon.inc.c |
37 | @@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) | 50 | @@ -XXX,XX +XXX,XX @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn) |
38 | int i; | 51 | DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) |
39 | uint32_t changed; | 52 | DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) |
40 | 53 | DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) | |
41 | + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ | 54 | + |
42 | + if (!arm_feature(env, ARM_FEATURE_V8_FP16)) { | 55 | +static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) |
43 | + val &= ~FPCR_FZ16; | 56 | +{ |
57 | + /* Handle a 2-reg-shift insn which can be vectorized. */ | ||
58 | + int vec_size = a->q ? 16 : 8; | ||
59 | + int rd_ofs = neon_reg_offset(a->vd, 0); | ||
60 | + int rm_ofs = neon_reg_offset(a->vm, 0); | ||
61 | + | ||
62 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
63 | + return false; | ||
44 | + } | 64 | + } |
45 | + | 65 | + |
46 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | 66 | + /* UNDEF accesses to D16-D31 if they don't exist. */ |
47 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | 67 | + if (!dc_isar_feature(aa32_simd_r32, s) && |
48 | env->vfp.vec_len = (val >> 16) & 7; | 68 | + ((a->vd | a->vm) & 0x10)) { |
69 | + return false; | ||
70 | + } | ||
71 | + | ||
72 | + if ((a->vm | a->vd) & a->q) { | ||
73 | + return false; | ||
74 | + } | ||
75 | + | ||
76 | + if (!vfp_access_check(s)) { | ||
77 | + return true; | ||
78 | + } | ||
79 | + | ||
80 | + fn(a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size); | ||
81 | + return true; | ||
82 | +} | ||
83 | + | ||
84 | +#define DO_2SH(INSN, FUNC) \ | ||
85 | + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ | ||
86 | + { \ | ||
87 | + return do_vector_2sh(s, a, FUNC); \ | ||
88 | + } \ | ||
89 | + | ||
90 | +DO_2SH(VSHL, tcg_gen_gvec_shli) | ||
91 | +DO_2SH(VSLI, gen_gvec_sli) | ||
92 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/target/arm/translate.c | ||
95 | +++ b/target/arm/translate.c | ||
96 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
97 | if ((insn & 0x00380080) != 0) { | ||
98 | /* Two registers and shift. */ | ||
99 | op = (insn >> 8) & 0xf; | ||
100 | + | ||
101 | + switch (op) { | ||
102 | + case 5: /* VSHL, VSLI */ | ||
103 | + return 1; /* handled by decodetree */ | ||
104 | + default: | ||
105 | + break; | ||
106 | + } | ||
107 | + | ||
108 | if (insn & (1 << 7)) { | ||
109 | /* 64-bit shift. */ | ||
110 | if (op > 7) { | ||
111 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
112 | gen_gvec_sri(size, rd_ofs, rm_ofs, shift, | ||
113 | vec_size, vec_size); | ||
114 | return 0; | ||
115 | - | ||
116 | - case 5: /* VSHL, VSLI */ | ||
117 | - if (u) { /* VSLI */ | ||
118 | - gen_gvec_sli(size, rd_ofs, rm_ofs, shift, | ||
119 | - vec_size, vec_size); | ||
120 | - } else { /* VSHL */ | ||
121 | - tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift, | ||
122 | - vec_size, vec_size); | ||
123 | - } | ||
124 | - return 0; | ||
125 | } | ||
126 | |||
127 | if (size == 3) { | ||
49 | -- | 128 | -- |
50 | 2.18.0 | 129 | 2.20.1 |
51 | 130 | ||
52 | 131 | diff view generated by jsdifflib |
1 | From: Stefan Hajnoczi <stefanha@redhat.com> | 1 | Convert the VSHR 2-reg-shift insns to decodetree. |
---|---|---|---|
2 | 2 | ||
3 | Define a "cortex-m0" ARMv6-M CPU model. | 3 | Note that unlike the legacy decoder, we present the right shift |
4 | amount to the trans_ function as a positive integer. | ||
4 | 5 | ||
5 | Most of the register reset values set by other CPU models are not | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | relevant for the cut-down ARMv6-M architecture. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20200522145520.6778-3-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/neon-dp.decode | 25 ++++++++++++++++++++ | ||
11 | target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++ | ||
12 | target/arm/translate.c | 21 +---------------- | ||
13 | 3 files changed, 67 insertions(+), 20 deletions(-) | ||
7 | 14 | ||
8 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | 15 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Message-id: 20180814162739.11814-3-stefanha@redhat.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/cpu.c | 11 +++++++++++ | ||
15 | 1 file changed, 11 insertions(+) | ||
16 | |||
17 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.c | 17 | --- a/target/arm/neon-dp.decode |
20 | +++ b/target/arm/cpu.c | 18 | +++ b/target/arm/neon-dp.decode |
21 | @@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj) | 19 | @@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp |
22 | cpu->reset_auxcr = 1; | 20 | ###################################################################### |
21 | &2reg_shift vm vd q shift size | ||
22 | |||
23 | +# Right shifts are encoded as N - shift, where N is the element size in bits. | ||
24 | +%neon_rshift_i6 16:6 !function=rsub_64 | ||
25 | +%neon_rshift_i5 16:5 !function=rsub_32 | ||
26 | +%neon_rshift_i4 16:4 !function=rsub_16 | ||
27 | +%neon_rshift_i3 16:3 !function=rsub_8 | ||
28 | + | ||
29 | +@2reg_shr_d .... ... . . . ...... .... .... 1 q:1 . . .... \ | ||
30 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6 | ||
31 | +@2reg_shr_s .... ... . . . 1 ..... .... .... 0 q:1 . . .... \ | ||
32 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5 | ||
33 | +@2reg_shr_h .... ... . . . 01 .... .... .... 0 q:1 . . .... \ | ||
34 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4 | ||
35 | +@2reg_shr_b .... ... . . . 001 ... .... .... 0 q:1 . . .... \ | ||
36 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3 | ||
37 | + | ||
38 | @2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \ | ||
39 | &2reg_shift vm=%vm_dp vd=%vd_dp size=3 | ||
40 | @2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \ | ||
41 | @@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp | ||
42 | @2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \ | ||
43 | &2reg_shift vm=%vm_dp vd=%vd_dp size=0 | ||
44 | |||
45 | +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d | ||
46 | +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s | ||
47 | +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h | ||
48 | +VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b | ||
49 | + | ||
50 | +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d | ||
51 | +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s | ||
52 | +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h | ||
53 | +VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b | ||
54 | + | ||
55 | VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d | ||
56 | VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s | ||
57 | VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h | ||
58 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate-neon.inc.c | ||
61 | +++ b/target/arm/translate-neon.inc.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x) | ||
63 | return x + 1; | ||
23 | } | 64 | } |
24 | 65 | ||
25 | +static void cortex_m0_initfn(Object *obj) | 66 | +static inline int rsub_64(DisasContext *s, int x) |
26 | +{ | 67 | +{ |
27 | + ARMCPU *cpu = ARM_CPU(obj); | 68 | + return 64 - x; |
28 | + set_feature(&cpu->env, ARM_FEATURE_V6); | ||
29 | + set_feature(&cpu->env, ARM_FEATURE_M); | ||
30 | + | ||
31 | + cpu->midr = 0x410cc200; | ||
32 | +} | 69 | +} |
33 | + | 70 | + |
34 | static void cortex_m3_initfn(Object *obj) | 71 | +static inline int rsub_32(DisasContext *s, int x) |
35 | { | 72 | +{ |
36 | ARMCPU *cpu = ARM_CPU(obj); | 73 | + return 32 - x; |
37 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | 74 | +} |
38 | { .name = "arm1136", .initfn = arm1136_initfn }, | 75 | +static inline int rsub_16(DisasContext *s, int x) |
39 | { .name = "arm1176", .initfn = arm1176_initfn }, | 76 | +{ |
40 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | 77 | + return 16 - x; |
41 | + { .name = "cortex-m0", .initfn = cortex_m0_initfn, | 78 | +} |
42 | + .class_init = arm_v7m_class_init }, | 79 | +static inline int rsub_8(DisasContext *s, int x) |
43 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, | 80 | +{ |
44 | .class_init = arm_v7m_class_init }, | 81 | + return 8 - x; |
45 | { .name = "cortex-m4", .initfn = cortex_m4_initfn, | 82 | +} |
83 | + | ||
84 | /* Include the generated Neon decoder */ | ||
85 | #include "decode-neon-dp.inc.c" | ||
86 | #include "decode-neon-ls.inc.c" | ||
87 | @@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) | ||
88 | |||
89 | DO_2SH(VSHL, tcg_gen_gvec_shli) | ||
90 | DO_2SH(VSLI, gen_gvec_sli) | ||
91 | + | ||
92 | +static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) | ||
93 | +{ | ||
94 | + /* Signed shift out of range results in all-sign-bits */ | ||
95 | + a->shift = MIN(a->shift, (8 << a->size) - 1); | ||
96 | + return do_vector_2sh(s, a, tcg_gen_gvec_sari); | ||
97 | +} | ||
98 | + | ||
99 | +static void gen_zero_rd_2sh(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, | ||
100 | + int64_t shift, uint32_t oprsz, uint32_t maxsz) | ||
101 | +{ | ||
102 | + tcg_gen_gvec_dup_imm(vece, rd_ofs, oprsz, maxsz, 0); | ||
103 | +} | ||
104 | + | ||
105 | +static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) | ||
106 | +{ | ||
107 | + /* Shift out of range is architecturally valid and results in zero. */ | ||
108 | + if (a->shift >= (8 << a->size)) { | ||
109 | + return do_vector_2sh(s, a, gen_zero_rd_2sh); | ||
110 | + } else { | ||
111 | + return do_vector_2sh(s, a, tcg_gen_gvec_shri); | ||
112 | + } | ||
113 | +} | ||
114 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
115 | index XXXXXXX..XXXXXXX 100644 | ||
116 | --- a/target/arm/translate.c | ||
117 | +++ b/target/arm/translate.c | ||
118 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
119 | op = (insn >> 8) & 0xf; | ||
120 | |||
121 | switch (op) { | ||
122 | + case 0: /* VSHR */ | ||
123 | case 5: /* VSHL, VSLI */ | ||
124 | return 1; /* handled by decodetree */ | ||
125 | default: | ||
126 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
127 | } | ||
128 | |||
129 | switch (op) { | ||
130 | - case 0: /* VSHR */ | ||
131 | - /* Right shift comes here negative. */ | ||
132 | - shift = -shift; | ||
133 | - /* Shifts larger than the element size are architecturally | ||
134 | - * valid. Unsigned results in all zeros; signed results | ||
135 | - * in all sign bits. | ||
136 | - */ | ||
137 | - if (!u) { | ||
138 | - tcg_gen_gvec_sari(size, rd_ofs, rm_ofs, | ||
139 | - MIN(shift, (8 << size) - 1), | ||
140 | - vec_size, vec_size); | ||
141 | - } else if (shift >= 8 << size) { | ||
142 | - tcg_gen_gvec_dup_imm(MO_8, rd_ofs, vec_size, | ||
143 | - vec_size, 0); | ||
144 | - } else { | ||
145 | - tcg_gen_gvec_shri(size, rd_ofs, rm_ofs, shift, | ||
146 | - vec_size, vec_size); | ||
147 | - } | ||
148 | - return 0; | ||
149 | - | ||
150 | case 1: /* VSRA */ | ||
151 | /* Right shift comes here negative. */ | ||
152 | shift = -shift; | ||
46 | -- | 153 | -- |
47 | 2.18.0 | 154 | 2.20.1 |
48 | 155 | ||
49 | 156 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | Convert the VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree. |
---|---|---|---|
2 | (These are the last instructions in the group that are vectorized; | ||
3 | the rest all require looping over each element.) | ||
2 | 4 | ||
3 | The ast2500 SDRAM training routine busy waits on the 'init cycle busy | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | state' bit in DDR PHY Control/Status register #1 (MCR60). | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20200522145520.6778-4-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/neon-dp.decode | 35 ++++++++++++++++++++++ | ||
10 | target/arm/translate-neon.inc.c | 7 +++++ | ||
11 | target/arm/translate.c | 52 +++------------------------------ | ||
12 | 3 files changed, 46 insertions(+), 48 deletions(-) | ||
5 | 13 | ||
6 | This ensures the bit always reads zero, and allows training to | 14 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode |
7 | complete with upstream u-boot on the ast2500-evb. | ||
8 | |||
9 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
10 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
11 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
12 | Message-id: 20180807075757.7242-5-joel@jms.id.au | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/misc/aspeed_sdmc.c | 15 +++++++++++++++ | ||
16 | 1 file changed, 15 insertions(+) | ||
17 | |||
18 | diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/misc/aspeed_sdmc.c | 16 | --- a/target/arm/neon-dp.decode |
21 | +++ b/hw/misc/aspeed_sdmc.c | 17 | +++ b/target/arm/neon-dp.decode |
22 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s |
23 | /* Configuration Register */ | 19 | VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h |
24 | #define R_CONF (0x04 / 4) | 20 | VSHR_U_2sh 1111 001 1 1 . ...... .... 0000 . . . 1 .... @2reg_shr_b |
25 | 21 | ||
26 | +/* Control/Status Register #1 (ast2500) */ | 22 | +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d |
27 | +#define R_STATUS1 (0x60 / 4) | 23 | +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s |
28 | +#define PHY_BUSY_STATE BIT(0) | 24 | +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h |
25 | +VSRA_S_2sh 1111 001 0 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b | ||
29 | + | 26 | + |
30 | /* | 27 | +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_d |
31 | * Configuration register Ox4 (for Aspeed AST2400 SOC) | 28 | +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_s |
32 | * | 29 | +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_h |
33 | @@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, | 30 | +VSRA_U_2sh 1111 001 1 1 . ...... .... 0001 . . . 1 .... @2reg_shr_b |
34 | g_assert_not_reached(); | 31 | + |
35 | } | 32 | +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d |
36 | } | 33 | +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s |
37 | + if (s->silicon_rev == AST2500_A0_SILICON_REV || | 34 | +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h |
38 | + s->silicon_rev == AST2500_A1_SILICON_REV) { | 35 | +VRSHR_S_2sh 1111 001 0 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b |
39 | + switch (addr) { | 36 | + |
40 | + case R_STATUS1: | 37 | +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_d |
41 | + /* Will never return 'busy' */ | 38 | +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_s |
42 | + data &= ~PHY_BUSY_STATE; | 39 | +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_h |
43 | + break; | 40 | +VRSHR_U_2sh 1111 001 1 1 . ...... .... 0010 . . . 1 .... @2reg_shr_b |
44 | + default: | 41 | + |
45 | + break; | 42 | +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d |
46 | + } | 43 | +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s |
47 | + } | 44 | +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h |
48 | 45 | +VRSRA_S_2sh 1111 001 0 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b | |
49 | s->regs[addr] = data; | 46 | + |
50 | } | 47 | +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_d |
48 | +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_s | ||
49 | +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_h | ||
50 | +VRSRA_U_2sh 1111 001 1 1 . ...... .... 0011 . . . 1 .... @2reg_shr_b | ||
51 | + | ||
52 | +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_d | ||
53 | +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_s | ||
54 | +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_h | ||
55 | +VSRI_2sh 1111 001 1 1 . ...... .... 0100 . . . 1 .... @2reg_shr_b | ||
56 | + | ||
57 | VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d | ||
58 | VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s | ||
59 | VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h | ||
60 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/translate-neon.inc.c | ||
63 | +++ b/target/arm/translate-neon.inc.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn) | ||
65 | |||
66 | DO_2SH(VSHL, tcg_gen_gvec_shli) | ||
67 | DO_2SH(VSLI, gen_gvec_sli) | ||
68 | +DO_2SH(VSRI, gen_gvec_sri) | ||
69 | +DO_2SH(VSRA_S, gen_gvec_ssra) | ||
70 | +DO_2SH(VSRA_U, gen_gvec_usra) | ||
71 | +DO_2SH(VRSHR_S, gen_gvec_srshr) | ||
72 | +DO_2SH(VRSHR_U, gen_gvec_urshr) | ||
73 | +DO_2SH(VRSRA_S, gen_gvec_srsra) | ||
74 | +DO_2SH(VRSRA_U, gen_gvec_ursra) | ||
75 | |||
76 | static bool trans_VSHR_S_2sh(DisasContext *s, arg_2reg_shift *a) | ||
77 | { | ||
78 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/target/arm/translate.c | ||
81 | +++ b/target/arm/translate.c | ||
82 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
83 | |||
84 | switch (op) { | ||
85 | case 0: /* VSHR */ | ||
86 | + case 1: /* VSRA */ | ||
87 | + case 2: /* VRSHR */ | ||
88 | + case 3: /* VRSRA */ | ||
89 | + case 4: /* VSRI */ | ||
90 | case 5: /* VSHL, VSLI */ | ||
91 | return 1; /* handled by decodetree */ | ||
92 | default: | ||
93 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
94 | shift = shift - (1 << (size + 3)); | ||
95 | } | ||
96 | |||
97 | - switch (op) { | ||
98 | - case 1: /* VSRA */ | ||
99 | - /* Right shift comes here negative. */ | ||
100 | - shift = -shift; | ||
101 | - if (u) { | ||
102 | - gen_gvec_usra(size, rd_ofs, rm_ofs, shift, | ||
103 | - vec_size, vec_size); | ||
104 | - } else { | ||
105 | - gen_gvec_ssra(size, rd_ofs, rm_ofs, shift, | ||
106 | - vec_size, vec_size); | ||
107 | - } | ||
108 | - return 0; | ||
109 | - | ||
110 | - case 2: /* VRSHR */ | ||
111 | - /* Right shift comes here negative. */ | ||
112 | - shift = -shift; | ||
113 | - if (u) { | ||
114 | - gen_gvec_urshr(size, rd_ofs, rm_ofs, shift, | ||
115 | - vec_size, vec_size); | ||
116 | - } else { | ||
117 | - gen_gvec_srshr(size, rd_ofs, rm_ofs, shift, | ||
118 | - vec_size, vec_size); | ||
119 | - } | ||
120 | - return 0; | ||
121 | - | ||
122 | - case 3: /* VRSRA */ | ||
123 | - /* Right shift comes here negative. */ | ||
124 | - shift = -shift; | ||
125 | - if (u) { | ||
126 | - gen_gvec_ursra(size, rd_ofs, rm_ofs, shift, | ||
127 | - vec_size, vec_size); | ||
128 | - } else { | ||
129 | - gen_gvec_srsra(size, rd_ofs, rm_ofs, shift, | ||
130 | - vec_size, vec_size); | ||
131 | - } | ||
132 | - return 0; | ||
133 | - | ||
134 | - case 4: /* VSRI */ | ||
135 | - if (!u) { | ||
136 | - return 1; | ||
137 | - } | ||
138 | - /* Right shift comes here negative. */ | ||
139 | - shift = -shift; | ||
140 | - gen_gvec_sri(size, rd_ofs, rm_ofs, shift, | ||
141 | - vec_size, vec_size); | ||
142 | - return 0; | ||
143 | - } | ||
144 | - | ||
145 | if (size == 3) { | ||
146 | count = q + 1; | ||
147 | } else { | ||
51 | -- | 148 | -- |
52 | 2.18.0 | 149 | 2.20.1 |
53 | 150 | ||
54 | 151 | diff view generated by jsdifflib |
1 | From: Su Hang <suhang16@mails.ucas.ac.cn> | 1 | Convert the VQSHLU and QVSHL 2-reg-shift insns to decodetree. |
---|---|---|---|
2 | 2 | These are the last of the simple shift-by-immediate insns. | |
3 | This patch adds Intel Hexadecimal Object File format support to the | 3 | |
4 | generic loader device. The file format specification is available here: | ||
5 | http://www.piclist.com/techref/fileext/hex/intel.htm | ||
6 | |||
7 | This file format is often used with microcontrollers such as the | ||
8 | micro:bit, Arduino, STM32, etc. Users expect to be able to run .hex | ||
9 | files directly with without first converting them to ELF. Most | ||
10 | micro:bit code is developed in web-based IDEs without direct user access | ||
11 | to binutils so it is important for QEMU to handle this file format | ||
12 | natively. | ||
13 | |||
14 | Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn> | ||
15 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
16 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | ||
17 | Message-id: 20180814162739.11814-6-stefanha@redhat.com | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200522145520.6778-5-peter.maydell@linaro.org | ||
19 | --- | 7 | --- |
20 | include/hw/loader.h | 12 ++ | 8 | target/arm/neon-dp.decode | 15 +++++ |
21 | hw/core/generic-loader.c | 4 + | 9 | target/arm/translate-neon.inc.c | 108 +++++++++++++++++++++++++++++++ |
22 | hw/core/loader.c | 249 +++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/translate.c | 110 +------------------------------- |
23 | 3 files changed, 265 insertions(+) | 11 | 3 files changed, 126 insertions(+), 107 deletions(-) |
24 | 12 | ||
25 | diff --git a/include/hw/loader.h b/include/hw/loader.h | 13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode |
26 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/include/hw/loader.h | 15 | --- a/target/arm/neon-dp.decode |
28 | +++ b/include/hw/loader.h | 16 | +++ b/target/arm/neon-dp.decode |
29 | @@ -XXX,XX +XXX,XX @@ ssize_t load_image_size(const char *filename, void *addr, size_t size); | 17 | @@ -XXX,XX +XXX,XX @@ VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d |
30 | int load_image_targphys_as(const char *filename, | 18 | VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s |
31 | hwaddr addr, uint64_t max_sz, AddressSpace *as); | 19 | VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h |
32 | 20 | VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b | |
33 | +/**load_targphys_hex_as: | 21 | + |
34 | + * @filename: Path to the .hex file | 22 | +VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d |
35 | + * @entry: Store the entry point given by the .hex file | 23 | +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s |
36 | + * @as: The AddressSpace to load the .hex file to. The value of | 24 | +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h |
37 | + * address_space_memory is used if nothing is supplied here. | 25 | +VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b |
38 | + * | 26 | + |
39 | + * Load a fixed .hex file into memory. | 27 | +VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d |
40 | + * | 28 | +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s |
41 | + * Returns the size of the loaded .hex file on success, -1 otherwise. | 29 | +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h |
42 | + */ | 30 | +VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b |
43 | +int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as); | 31 | + |
44 | + | 32 | +VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d |
45 | /** load_image_targphys: | 33 | +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s |
46 | * Same as load_image_targphys_as(), but doesn't allow the caller to specify | 34 | +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h |
47 | * an AddressSpace. | 35 | +VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b |
48 | diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c | 36 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c |
49 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/hw/core/generic-loader.c | 38 | --- a/target/arm/translate-neon.inc.c |
51 | +++ b/hw/core/generic-loader.c | 39 | +++ b/target/arm/translate-neon.inc.c |
52 | @@ -XXX,XX +XXX,XX @@ static void generic_loader_realize(DeviceState *dev, Error **errp) | 40 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHR_U_2sh(DisasContext *s, arg_2reg_shift *a) |
53 | size = load_uimage_as(s->file, &entry, NULL, NULL, NULL, NULL, | 41 | return do_vector_2sh(s, a, tcg_gen_gvec_shri); |
54 | as); | ||
55 | } | ||
56 | + | ||
57 | + if (size < 0) { | ||
58 | + size = load_targphys_hex_as(s->file, &entry, as); | ||
59 | + } | ||
60 | } | ||
61 | |||
62 | if (size < 0 || s->force_raw) { | ||
63 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/core/loader.c | ||
66 | +++ b/hw/core/loader.c | ||
67 | @@ -XXX,XX +XXX,XX @@ void hmp_info_roms(Monitor *mon, const QDict *qdict) | ||
68 | } | ||
69 | } | 42 | } |
70 | } | 43 | } |
71 | + | 44 | + |
72 | +typedef enum HexRecord HexRecord; | 45 | +static bool do_2shift_env_64(DisasContext *s, arg_2reg_shift *a, |
73 | +enum HexRecord { | 46 | + NeonGenTwo64OpEnvFn *fn) |
74 | + DATA_RECORD = 0, | ||
75 | + EOF_RECORD, | ||
76 | + EXT_SEG_ADDR_RECORD, | ||
77 | + START_SEG_ADDR_RECORD, | ||
78 | + EXT_LINEAR_ADDR_RECORD, | ||
79 | + START_LINEAR_ADDR_RECORD, | ||
80 | +}; | ||
81 | + | ||
82 | +/* Each record contains a 16-bit address which is combined with the upper 16 | ||
83 | + * bits of the implicit "next address" to form a 32-bit address. | ||
84 | + */ | ||
85 | +#define NEXT_ADDR_MASK 0xffff0000 | ||
86 | + | ||
87 | +#define DATA_FIELD_MAX_LEN 0xff | ||
88 | +#define LEN_EXCEPT_DATA 0x5 | ||
89 | +/* 0x5 = sizeof(byte_count) + sizeof(address) + sizeof(record_type) + | ||
90 | + * sizeof(checksum) */ | ||
91 | +typedef struct { | ||
92 | + uint8_t byte_count; | ||
93 | + uint16_t address; | ||
94 | + uint8_t record_type; | ||
95 | + uint8_t data[DATA_FIELD_MAX_LEN]; | ||
96 | + uint8_t checksum; | ||
97 | +} HexLine; | ||
98 | + | ||
99 | +/* return 0 or -1 if error */ | ||
100 | +static bool parse_record(HexLine *line, uint8_t *our_checksum, const uint8_t c, | ||
101 | + uint32_t *index, const bool in_process) | ||
102 | +{ | 47 | +{ |
103 | + /* +-------+---------------+-------+---------------------+--------+ | 48 | + /* |
104 | + * | byte | |record | | | | 49 | + * 2-reg-and-shift operations, size == 3 case, where the |
105 | + * | count | address | type | data |checksum| | 50 | + * function needs to be passed cpu_env. |
106 | + * +-------+---------------+-------+---------------------+--------+ | 51 | + */ |
107 | + * ^ ^ ^ ^ ^ ^ | 52 | + TCGv_i64 constimm; |
108 | + * |1 byte | 2 bytes |1 byte | 0-255 bytes | 1 byte | | 53 | + int pass; |
109 | + */ | 54 | + |
110 | + uint8_t value = 0; | 55 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
111 | + uint32_t idx = *index; | 56 | + return false; |
112 | + /* ignore space */ | 57 | + } |
113 | + if (g_ascii_isspace(c)) { | 58 | + |
59 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
60 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
61 | + ((a->vd | a->vm) & 0x10)) { | ||
62 | + return false; | ||
63 | + } | ||
64 | + | ||
65 | + if ((a->vm | a->vd) & a->q) { | ||
66 | + return false; | ||
67 | + } | ||
68 | + | ||
69 | + if (!vfp_access_check(s)) { | ||
114 | + return true; | 70 | + return true; |
115 | + } | 71 | + } |
116 | + if (!g_ascii_isxdigit(c) || !in_process) { | 72 | + |
117 | + return false; | 73 | + /* |
118 | + } | 74 | + * To avoid excessive duplication of ops we implement shift |
119 | + value = g_ascii_xdigit_value(c); | 75 | + * by immediate using the variable shift operations. |
120 | + value = (idx & 0x1) ? (value & 0xf) : (value << 4); | 76 | + */ |
121 | + if (idx < 2) { | 77 | + constimm = tcg_const_i64(dup_const(a->size, a->shift)); |
122 | + line->byte_count |= value; | 78 | + |
123 | + } else if (2 <= idx && idx < 6) { | 79 | + for (pass = 0; pass < a->q + 1; pass++) { |
124 | + line->address <<= 4; | 80 | + TCGv_i64 tmp = tcg_temp_new_i64(); |
125 | + line->address += g_ascii_xdigit_value(c); | 81 | + |
126 | + } else if (6 <= idx && idx < 8) { | 82 | + neon_load_reg64(tmp, a->vm + pass); |
127 | + line->record_type |= value; | 83 | + fn(tmp, cpu_env, tmp, constimm); |
128 | + } else if (8 <= idx && idx < 8 + 2 * line->byte_count) { | 84 | + neon_store_reg64(tmp, a->vd + pass); |
129 | + line->data[(idx - 8) >> 1] |= value; | 85 | + } |
130 | + } else if (8 + 2 * line->byte_count <= idx && | 86 | + tcg_temp_free_i64(constimm); |
131 | + idx < 10 + 2 * line->byte_count) { | ||
132 | + line->checksum |= value; | ||
133 | + } else { | ||
134 | + return false; | ||
135 | + } | ||
136 | + *our_checksum += value; | ||
137 | + ++(*index); | ||
138 | + return true; | 87 | + return true; |
139 | +} | 88 | +} |
140 | + | 89 | + |
141 | +typedef struct { | 90 | +static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, |
142 | + const char *filename; | 91 | + NeonGenTwoOpEnvFn *fn) |
143 | + HexLine line; | ||
144 | + uint8_t *bin_buf; | ||
145 | + hwaddr *start_addr; | ||
146 | + int total_size; | ||
147 | + uint32_t next_address_to_write; | ||
148 | + uint32_t current_address; | ||
149 | + uint32_t current_rom_index; | ||
150 | + uint32_t rom_start_address; | ||
151 | + AddressSpace *as; | ||
152 | +} HexParser; | ||
153 | + | ||
154 | +/* return size or -1 if error */ | ||
155 | +static int handle_record_type(HexParser *parser) | ||
156 | +{ | 92 | +{ |
157 | + HexLine *line = &(parser->line); | 93 | + /* |
158 | + switch (line->record_type) { | 94 | + * 2-reg-and-shift operations, size < 3 case, where the |
159 | + case DATA_RECORD: | 95 | + * helper needs to be passed cpu_env. |
160 | + parser->current_address = | 96 | + */ |
161 | + (parser->next_address_to_write & NEXT_ADDR_MASK) | line->address; | 97 | + TCGv_i32 constimm; |
162 | + /* verify this is a contiguous block of memory */ | 98 | + int pass; |
163 | + if (parser->current_address != parser->next_address_to_write) { | 99 | + |
164 | + if (parser->current_rom_index != 0) { | 100 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
165 | + rom_add_blob_fixed_as(parser->filename, parser->bin_buf, | 101 | + return false; |
166 | + parser->current_rom_index, | 102 | + } |
167 | + parser->rom_start_address, parser->as); | 103 | + |
168 | + } | 104 | + /* UNDEF accesses to D16-D31 if they don't exist. */ |
169 | + parser->rom_start_address = parser->current_address; | 105 | + if (!dc_isar_feature(aa32_simd_r32, s) && |
170 | + parser->current_rom_index = 0; | 106 | + ((a->vd | a->vm) & 0x10)) { |
171 | + } | 107 | + return false; |
172 | + | 108 | + } |
173 | + /* copy from line buffer to output bin_buf */ | 109 | + |
174 | + memcpy(parser->bin_buf + parser->current_rom_index, line->data, | 110 | + if ((a->vm | a->vd) & a->q) { |
175 | + line->byte_count); | 111 | + return false; |
176 | + parser->current_rom_index += line->byte_count; | 112 | + } |
177 | + parser->total_size += line->byte_count; | 113 | + |
178 | + /* save next address to write */ | 114 | + if (!vfp_access_check(s)) { |
179 | + parser->next_address_to_write = | 115 | + return true; |
180 | + parser->current_address + line->byte_count; | 116 | + } |
181 | + break; | 117 | + |
182 | + | 118 | + /* |
183 | + case EOF_RECORD: | 119 | + * To avoid excessive duplication of ops we implement shift |
184 | + if (parser->current_rom_index != 0) { | 120 | + * by immediate using the variable shift operations. |
185 | + rom_add_blob_fixed_as(parser->filename, parser->bin_buf, | 121 | + */ |
186 | + parser->current_rom_index, | 122 | + constimm = tcg_const_i32(dup_const(a->size, a->shift)); |
187 | + parser->rom_start_address, parser->as); | 123 | + |
188 | + } | 124 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { |
189 | + return parser->total_size; | 125 | + TCGv_i32 tmp = neon_load_reg(a->vm, pass); |
190 | + case EXT_SEG_ADDR_RECORD: | 126 | + fn(tmp, cpu_env, tmp, constimm); |
191 | + case EXT_LINEAR_ADDR_RECORD: | 127 | + neon_store_reg(a->vd, pass, tmp); |
192 | + if (line->byte_count != 2 && line->address != 0) { | 128 | + } |
193 | + return -1; | 129 | + tcg_temp_free_i32(constimm); |
194 | + } | 130 | + return true; |
195 | + | ||
196 | + if (parser->current_rom_index != 0) { | ||
197 | + rom_add_blob_fixed_as(parser->filename, parser->bin_buf, | ||
198 | + parser->current_rom_index, | ||
199 | + parser->rom_start_address, parser->as); | ||
200 | + } | ||
201 | + | ||
202 | + /* save next address to write, | ||
203 | + * in case of non-contiguous block of memory */ | ||
204 | + parser->next_address_to_write = (line->data[0] << 12) | | ||
205 | + (line->data[1] << 4); | ||
206 | + if (line->record_type == EXT_LINEAR_ADDR_RECORD) { | ||
207 | + parser->next_address_to_write <<= 12; | ||
208 | + } | ||
209 | + | ||
210 | + parser->rom_start_address = parser->next_address_to_write; | ||
211 | + parser->current_rom_index = 0; | ||
212 | + break; | ||
213 | + | ||
214 | + case START_SEG_ADDR_RECORD: | ||
215 | + if (line->byte_count != 4 && line->address != 0) { | ||
216 | + return -1; | ||
217 | + } | ||
218 | + | ||
219 | + /* x86 16-bit CS:IP segmented addressing */ | ||
220 | + *(parser->start_addr) = (((line->data[0] << 8) | line->data[1]) << 4) + | ||
221 | + ((line->data[2] << 8) | line->data[3]); | ||
222 | + break; | ||
223 | + | ||
224 | + case START_LINEAR_ADDR_RECORD: | ||
225 | + if (line->byte_count != 4 && line->address != 0) { | ||
226 | + return -1; | ||
227 | + } | ||
228 | + | ||
229 | + *(parser->start_addr) = ldl_be_p(line->data); | ||
230 | + break; | ||
231 | + | ||
232 | + default: | ||
233 | + return -1; | ||
234 | + } | ||
235 | + | ||
236 | + return parser->total_size; | ||
237 | +} | 131 | +} |
238 | + | 132 | + |
239 | +/* return size or -1 if error */ | 133 | +#define DO_2SHIFT_ENV(INSN, FUNC) \ |
240 | +static int parse_hex_blob(const char *filename, hwaddr *addr, uint8_t *hex_blob, | 134 | + static bool trans_##INSN##_64_2sh(DisasContext *s, arg_2reg_shift *a) \ |
241 | + size_t hex_blob_size, AddressSpace *as) | 135 | + { \ |
242 | +{ | 136 | + return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \ |
243 | + bool in_process = false; /* avoid re-enter and | 137 | + } \ |
244 | + * check whether record begin with ':' */ | 138 | + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ |
245 | + uint8_t *end = hex_blob + hex_blob_size; | 139 | + { \ |
246 | + uint8_t our_checksum = 0; | 140 | + static NeonGenTwoOpEnvFn * const fns[] = { \ |
247 | + uint32_t record_index = 0; | 141 | + gen_helper_neon_##FUNC##8, \ |
248 | + HexParser parser = { | 142 | + gen_helper_neon_##FUNC##16, \ |
249 | + .filename = filename, | 143 | + gen_helper_neon_##FUNC##32, \ |
250 | + .bin_buf = g_malloc(hex_blob_size), | 144 | + }; \ |
251 | + .start_addr = addr, | 145 | + assert(a->size < ARRAY_SIZE(fns)); \ |
252 | + .as = as, | 146 | + return do_2shift_env_32(s, a, fns[a->size]); \ |
253 | + }; | 147 | + } |
254 | + | 148 | + |
255 | + rom_transaction_begin(); | 149 | +DO_2SHIFT_ENV(VQSHLU, qshlu_s) |
256 | + | 150 | +DO_2SHIFT_ENV(VQSHL_U, qshl_u) |
257 | + for (; hex_blob < end; ++hex_blob) { | 151 | +DO_2SHIFT_ENV(VQSHL_S, qshl_s) |
258 | + switch (*hex_blob) { | 152 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
259 | + case '\r': | 153 | index XXXXXXX..XXXXXXX 100644 |
260 | + case '\n': | 154 | --- a/target/arm/translate.c |
261 | + if (!in_process) { | 155 | +++ b/target/arm/translate.c |
262 | + break; | 156 | @@ -XXX,XX +XXX,XX @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1) |
263 | + } | 157 | } |
264 | + | 158 | } |
265 | + in_process = false; | 159 | |
266 | + if ((LEN_EXCEPT_DATA + parser.line.byte_count) * 2 != | 160 | -#define GEN_NEON_INTEGER_OP_ENV(name) do { \ |
267 | + record_index || | 161 | - switch ((size << 1) | u) { \ |
268 | + our_checksum != 0) { | 162 | - case 0: \ |
269 | + parser.total_size = -1; | 163 | - gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \ |
270 | + goto out; | 164 | - break; \ |
271 | + } | 165 | - case 1: \ |
272 | + | 166 | - gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \ |
273 | + if (handle_record_type(&parser) == -1) { | 167 | - break; \ |
274 | + parser.total_size = -1; | 168 | - case 2: \ |
275 | + goto out; | 169 | - gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \ |
276 | + } | 170 | - break; \ |
277 | + break; | 171 | - case 3: \ |
278 | + | 172 | - gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \ |
279 | + /* start of a new record. */ | 173 | - break; \ |
280 | + case ':': | 174 | - case 4: \ |
281 | + memset(&parser.line, 0, sizeof(HexLine)); | 175 | - gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \ |
282 | + in_process = true; | 176 | - break; \ |
283 | + record_index = 0; | 177 | - case 5: \ |
284 | + break; | 178 | - gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \ |
285 | + | 179 | - break; \ |
286 | + /* decoding lines */ | 180 | - default: return 1; \ |
287 | + default: | 181 | - }} while (0) |
288 | + if (!parse_record(&parser.line, &our_checksum, *hex_blob, | 182 | - |
289 | + &record_index, in_process)) { | 183 | static TCGv_i32 neon_load_scratch(int scratch) |
290 | + parser.total_size = -1; | 184 | { |
291 | + goto out; | 185 | TCGv_i32 tmp = tcg_temp_new_i32(); |
292 | + } | 186 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) |
293 | + break; | 187 | int size; |
294 | + } | 188 | int shift; |
295 | + } | 189 | int pass; |
296 | + | 190 | - int count; |
297 | +out: | 191 | int u; |
298 | + g_free(parser.bin_buf); | 192 | int vec_size; |
299 | + rom_transaction_end(parser.total_size != -1); | 193 | uint32_t imm; |
300 | + return parser.total_size; | 194 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) |
301 | +} | 195 | case 3: /* VRSRA */ |
302 | + | 196 | case 4: /* VSRI */ |
303 | +/* return size or -1 if error */ | 197 | case 5: /* VSHL, VSLI */ |
304 | +int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as) | 198 | + case 6: /* VQSHLU */ |
305 | +{ | 199 | + case 7: /* VQSHL */ |
306 | + gsize hex_blob_size; | 200 | return 1; /* handled by decodetree */ |
307 | + gchar *hex_blob; | 201 | default: |
308 | + int total_size = 0; | 202 | break; |
309 | + | 203 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) |
310 | + if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) { | 204 | size--; |
311 | + return -1; | 205 | } |
312 | + } | 206 | shift = (insn >> 16) & ((1 << (3 + size)) - 1); |
313 | + | 207 | - if (op < 8) { |
314 | + total_size = parse_hex_blob(filename, entry, (uint8_t *)hex_blob, | 208 | - /* Shift by immediate: |
315 | + hex_blob_size, as); | 209 | - VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ |
316 | + | 210 | - if (q && ((rd | rm) & 1)) { |
317 | + g_free(hex_blob); | 211 | - return 1; |
318 | + return total_size; | 212 | - } |
319 | +} | 213 | - if (!u && (op == 4 || op == 6)) { |
214 | - return 1; | ||
215 | - } | ||
216 | - /* Right shifts are encoded as N - shift, where N is the | ||
217 | - element size in bits. */ | ||
218 | - if (op <= 4) { | ||
219 | - shift = shift - (1 << (size + 3)); | ||
220 | - } | ||
221 | - | ||
222 | - if (size == 3) { | ||
223 | - count = q + 1; | ||
224 | - } else { | ||
225 | - count = q ? 4: 2; | ||
226 | - } | ||
227 | - | ||
228 | - /* To avoid excessive duplication of ops we implement shift | ||
229 | - * by immediate using the variable shift operations. | ||
230 | - */ | ||
231 | - imm = dup_const(size, shift); | ||
232 | - | ||
233 | - for (pass = 0; pass < count; pass++) { | ||
234 | - if (size == 3) { | ||
235 | - neon_load_reg64(cpu_V0, rm + pass); | ||
236 | - tcg_gen_movi_i64(cpu_V1, imm); | ||
237 | - switch (op) { | ||
238 | - case 6: /* VQSHLU */ | ||
239 | - gen_helper_neon_qshlu_s64(cpu_V0, cpu_env, | ||
240 | - cpu_V0, cpu_V1); | ||
241 | - break; | ||
242 | - case 7: /* VQSHL */ | ||
243 | - if (u) { | ||
244 | - gen_helper_neon_qshl_u64(cpu_V0, cpu_env, | ||
245 | - cpu_V0, cpu_V1); | ||
246 | - } else { | ||
247 | - gen_helper_neon_qshl_s64(cpu_V0, cpu_env, | ||
248 | - cpu_V0, cpu_V1); | ||
249 | - } | ||
250 | - break; | ||
251 | - default: | ||
252 | - g_assert_not_reached(); | ||
253 | - } | ||
254 | - neon_store_reg64(cpu_V0, rd + pass); | ||
255 | - } else { /* size < 3 */ | ||
256 | - /* Operands in T0 and T1. */ | ||
257 | - tmp = neon_load_reg(rm, pass); | ||
258 | - tmp2 = tcg_temp_new_i32(); | ||
259 | - tcg_gen_movi_i32(tmp2, imm); | ||
260 | - switch (op) { | ||
261 | - case 6: /* VQSHLU */ | ||
262 | - switch (size) { | ||
263 | - case 0: | ||
264 | - gen_helper_neon_qshlu_s8(tmp, cpu_env, | ||
265 | - tmp, tmp2); | ||
266 | - break; | ||
267 | - case 1: | ||
268 | - gen_helper_neon_qshlu_s16(tmp, cpu_env, | ||
269 | - tmp, tmp2); | ||
270 | - break; | ||
271 | - case 2: | ||
272 | - gen_helper_neon_qshlu_s32(tmp, cpu_env, | ||
273 | - tmp, tmp2); | ||
274 | - break; | ||
275 | - default: | ||
276 | - abort(); | ||
277 | - } | ||
278 | - break; | ||
279 | - case 7: /* VQSHL */ | ||
280 | - GEN_NEON_INTEGER_OP_ENV(qshl); | ||
281 | - break; | ||
282 | - default: | ||
283 | - g_assert_not_reached(); | ||
284 | - } | ||
285 | - tcg_temp_free_i32(tmp2); | ||
286 | - neon_store_reg(rd, pass, tmp); | ||
287 | - } | ||
288 | - } /* for pass */ | ||
289 | - } else if (op < 10) { | ||
290 | + if (op < 10) { | ||
291 | /* Shift by immediate and narrow: | ||
292 | VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ | ||
293 | int input_unsigned = (op == 8) ? !u : u; | ||
320 | -- | 294 | -- |
321 | 2.18.0 | 295 | 2.20.1 |
322 | 296 | ||
323 | 297 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | Convert the Neon narrowing shifts where op==8 to decodetree: |
---|---|---|---|
2 | 2 | * VSHRN | |
3 | The SDMC on the ast2500 has 170 registers. | 3 | * VRSHRN |
4 | 4 | * VQSHRUN | |
5 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 5 | * VQRSHRUN |
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 6 | |
7 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
8 | Message-id: 20180807075757.7242-2-joel@jms.id.au | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200522145520.6778-6-peter.maydell@linaro.org | ||
10 | --- | 10 | --- |
11 | include/hw/misc/aspeed_sdmc.h | 2 +- | 11 | target/arm/neon-dp.decode | 27 ++++++ |
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | target/arm/translate-neon.inc.c | 167 ++++++++++++++++++++++++++++++++ |
13 | 13 | target/arm/translate.c | 1 + | |
14 | diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h | 14 | 3 files changed, 195 insertions(+) |
15 | |||
16 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/misc/aspeed_sdmc.h | 18 | --- a/target/arm/neon-dp.decode |
17 | +++ b/include/hw/misc/aspeed_sdmc.h | 19 | +++ b/target/arm/neon-dp.decode |
18 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp |
19 | #define TYPE_ASPEED_SDMC "aspeed.sdmc" | 21 | @2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \ |
20 | #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC) | 22 | &2reg_shift vm=%vm_dp vd=%vd_dp size=0 |
21 | 23 | ||
22 | -#define ASPEED_SDMC_NR_REGS (0x8 >> 2) | 24 | +# Narrowing right shifts: here the Q bit is part of the opcode decode |
23 | +#define ASPEED_SDMC_NR_REGS (0x174 >> 2) | 25 | +@2reg_shrn_d .... ... . . . 1 ..... .... .... 0 . . . .... \ |
24 | 26 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \ | |
25 | typedef struct AspeedSDMCState { | 27 | + shift=%neon_rshift_i5 |
26 | /*< private >*/ | 28 | +@2reg_shrn_s .... ... . . . 01 .... .... .... 0 . . . .... \ |
29 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 \ | ||
30 | + shift=%neon_rshift_i4 | ||
31 | +@2reg_shrn_h .... ... . . . 001 ... .... .... 0 . . . .... \ | ||
32 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \ | ||
33 | + shift=%neon_rshift_i3 | ||
34 | + | ||
35 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d | ||
36 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s | ||
37 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h | ||
38 | @@ -XXX,XX +XXX,XX @@ VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d | ||
39 | VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s | ||
40 | VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h | ||
41 | VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b | ||
42 | + | ||
43 | +VSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d | ||
44 | +VSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s | ||
45 | +VSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h | ||
46 | + | ||
47 | +VRSHRN_64_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d | ||
48 | +VRSHRN_32_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s | ||
49 | +VRSHRN_16_2sh 1111 001 0 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h | ||
50 | + | ||
51 | +VQSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_d | ||
52 | +VQSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_s | ||
53 | +VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h | ||
54 | + | ||
55 | +VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d | ||
56 | +VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s | ||
57 | +VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h | ||
58 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate-neon.inc.c | ||
61 | +++ b/target/arm/translate-neon.inc.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static bool do_2shift_env_32(DisasContext *s, arg_2reg_shift *a, | ||
63 | DO_2SHIFT_ENV(VQSHLU, qshlu_s) | ||
64 | DO_2SHIFT_ENV(VQSHL_U, qshl_u) | ||
65 | DO_2SHIFT_ENV(VQSHL_S, qshl_s) | ||
66 | + | ||
67 | +static bool do_2shift_narrow_64(DisasContext *s, arg_2reg_shift *a, | ||
68 | + NeonGenTwo64OpFn *shiftfn, | ||
69 | + NeonGenNarrowEnvFn *narrowfn) | ||
70 | +{ | ||
71 | + /* 2-reg-and-shift narrowing-shift operations, size == 3 case */ | ||
72 | + TCGv_i64 constimm, rm1, rm2; | ||
73 | + TCGv_i32 rd; | ||
74 | + | ||
75 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
76 | + return false; | ||
77 | + } | ||
78 | + | ||
79 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
80 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
81 | + ((a->vd | a->vm) & 0x10)) { | ||
82 | + return false; | ||
83 | + } | ||
84 | + | ||
85 | + if (a->vm & 1) { | ||
86 | + return false; | ||
87 | + } | ||
88 | + | ||
89 | + if (!vfp_access_check(s)) { | ||
90 | + return true; | ||
91 | + } | ||
92 | + | ||
93 | + /* | ||
94 | + * This is always a right shift, and the shiftfn is always a | ||
95 | + * left-shift helper, which thus needs the negated shift count. | ||
96 | + */ | ||
97 | + constimm = tcg_const_i64(-a->shift); | ||
98 | + rm1 = tcg_temp_new_i64(); | ||
99 | + rm2 = tcg_temp_new_i64(); | ||
100 | + | ||
101 | + /* Load both inputs first to avoid potential overwrite if rm == rd */ | ||
102 | + neon_load_reg64(rm1, a->vm); | ||
103 | + neon_load_reg64(rm2, a->vm + 1); | ||
104 | + | ||
105 | + shiftfn(rm1, rm1, constimm); | ||
106 | + rd = tcg_temp_new_i32(); | ||
107 | + narrowfn(rd, cpu_env, rm1); | ||
108 | + neon_store_reg(a->vd, 0, rd); | ||
109 | + | ||
110 | + shiftfn(rm2, rm2, constimm); | ||
111 | + rd = tcg_temp_new_i32(); | ||
112 | + narrowfn(rd, cpu_env, rm2); | ||
113 | + neon_store_reg(a->vd, 1, rd); | ||
114 | + | ||
115 | + tcg_temp_free_i64(rm1); | ||
116 | + tcg_temp_free_i64(rm2); | ||
117 | + tcg_temp_free_i64(constimm); | ||
118 | + | ||
119 | + return true; | ||
120 | +} | ||
121 | + | ||
122 | +static bool do_2shift_narrow_32(DisasContext *s, arg_2reg_shift *a, | ||
123 | + NeonGenTwoOpFn *shiftfn, | ||
124 | + NeonGenNarrowEnvFn *narrowfn) | ||
125 | +{ | ||
126 | + /* 2-reg-and-shift narrowing-shift operations, size < 3 case */ | ||
127 | + TCGv_i32 constimm, rm1, rm2, rm3, rm4; | ||
128 | + TCGv_i64 rtmp; | ||
129 | + uint32_t imm; | ||
130 | + | ||
131 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
132 | + return false; | ||
133 | + } | ||
134 | + | ||
135 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
136 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
137 | + ((a->vd | a->vm) & 0x10)) { | ||
138 | + return false; | ||
139 | + } | ||
140 | + | ||
141 | + if (a->vm & 1) { | ||
142 | + return false; | ||
143 | + } | ||
144 | + | ||
145 | + if (!vfp_access_check(s)) { | ||
146 | + return true; | ||
147 | + } | ||
148 | + | ||
149 | + /* | ||
150 | + * This is always a right shift, and the shiftfn is always a | ||
151 | + * left-shift helper, which thus needs the negated shift count | ||
152 | + * duplicated into each lane of the immediate value. | ||
153 | + */ | ||
154 | + if (a->size == 1) { | ||
155 | + imm = (uint16_t)(-a->shift); | ||
156 | + imm |= imm << 16; | ||
157 | + } else { | ||
158 | + /* size == 2 */ | ||
159 | + imm = -a->shift; | ||
160 | + } | ||
161 | + constimm = tcg_const_i32(imm); | ||
162 | + | ||
163 | + /* Load all inputs first to avoid potential overwrite */ | ||
164 | + rm1 = neon_load_reg(a->vm, 0); | ||
165 | + rm2 = neon_load_reg(a->vm, 1); | ||
166 | + rm3 = neon_load_reg(a->vm + 1, 0); | ||
167 | + rm4 = neon_load_reg(a->vm + 1, 1); | ||
168 | + rtmp = tcg_temp_new_i64(); | ||
169 | + | ||
170 | + shiftfn(rm1, rm1, constimm); | ||
171 | + shiftfn(rm2, rm2, constimm); | ||
172 | + | ||
173 | + tcg_gen_concat_i32_i64(rtmp, rm1, rm2); | ||
174 | + tcg_temp_free_i32(rm2); | ||
175 | + | ||
176 | + narrowfn(rm1, cpu_env, rtmp); | ||
177 | + neon_store_reg(a->vd, 0, rm1); | ||
178 | + | ||
179 | + shiftfn(rm3, rm3, constimm); | ||
180 | + shiftfn(rm4, rm4, constimm); | ||
181 | + tcg_temp_free_i32(constimm); | ||
182 | + | ||
183 | + tcg_gen_concat_i32_i64(rtmp, rm3, rm4); | ||
184 | + tcg_temp_free_i32(rm4); | ||
185 | + | ||
186 | + narrowfn(rm3, cpu_env, rtmp); | ||
187 | + tcg_temp_free_i64(rtmp); | ||
188 | + neon_store_reg(a->vd, 1, rm3); | ||
189 | + return true; | ||
190 | +} | ||
191 | + | ||
192 | +#define DO_2SN_64(INSN, FUNC, NARROWFUNC) \ | ||
193 | + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ | ||
194 | + { \ | ||
195 | + return do_2shift_narrow_64(s, a, FUNC, NARROWFUNC); \ | ||
196 | + } | ||
197 | +#define DO_2SN_32(INSN, FUNC, NARROWFUNC) \ | ||
198 | + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ | ||
199 | + { \ | ||
200 | + return do_2shift_narrow_32(s, a, FUNC, NARROWFUNC); \ | ||
201 | + } | ||
202 | + | ||
203 | +static void gen_neon_narrow_u32(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) | ||
204 | +{ | ||
205 | + tcg_gen_extrl_i64_i32(dest, src); | ||
206 | +} | ||
207 | + | ||
208 | +static void gen_neon_narrow_u16(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) | ||
209 | +{ | ||
210 | + gen_helper_neon_narrow_u16(dest, src); | ||
211 | +} | ||
212 | + | ||
213 | +static void gen_neon_narrow_u8(TCGv_i32 dest, TCGv_ptr env, TCGv_i64 src) | ||
214 | +{ | ||
215 | + gen_helper_neon_narrow_u8(dest, src); | ||
216 | +} | ||
217 | + | ||
218 | +DO_2SN_64(VSHRN_64, gen_ushl_i64, gen_neon_narrow_u32) | ||
219 | +DO_2SN_32(VSHRN_32, gen_ushl_i32, gen_neon_narrow_u16) | ||
220 | +DO_2SN_32(VSHRN_16, gen_helper_neon_shl_u16, gen_neon_narrow_u8) | ||
221 | + | ||
222 | +DO_2SN_64(VRSHRN_64, gen_helper_neon_rshl_u64, gen_neon_narrow_u32) | ||
223 | +DO_2SN_32(VRSHRN_32, gen_helper_neon_rshl_u32, gen_neon_narrow_u16) | ||
224 | +DO_2SN_32(VRSHRN_16, gen_helper_neon_rshl_u16, gen_neon_narrow_u8) | ||
225 | + | ||
226 | +DO_2SN_64(VQSHRUN_64, gen_sshl_i64, gen_helper_neon_unarrow_sat32) | ||
227 | +DO_2SN_32(VQSHRUN_32, gen_sshl_i32, gen_helper_neon_unarrow_sat16) | ||
228 | +DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8) | ||
229 | + | ||
230 | +DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32) | ||
231 | +DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16) | ||
232 | +DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8) | ||
233 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
234 | index XXXXXXX..XXXXXXX 100644 | ||
235 | --- a/target/arm/translate.c | ||
236 | +++ b/target/arm/translate.c | ||
237 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
238 | case 5: /* VSHL, VSLI */ | ||
239 | case 6: /* VQSHLU */ | ||
240 | case 7: /* VQSHL */ | ||
241 | + case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ | ||
242 | return 1; /* handled by decodetree */ | ||
243 | default: | ||
244 | break; | ||
27 | -- | 245 | -- |
28 | 2.18.0 | 246 | 2.20.1 |
29 | 247 | ||
30 | 248 | diff view generated by jsdifflib |
1 | From: Stefan Hajnoczi <stefanha@redhat.com> | 1 | Convert the remaining Neon narrowing shifts to decodetree: |
---|---|---|---|
2 | 2 | * VQSHRN | |
3 | Some ARM CPUs have bitbanded IO, a memory region that allows convenient | 3 | * VQRSHRN |
4 | bit access via 32-bit memory loads/stores. This eliminates the need for | 4 | |
5 | read-modify-update instruction sequences. | ||
6 | |||
7 | This patch makes this optional feature an ARMv7MState qdev property, | ||
8 | allowing boards to choose whether they want bitbanding or not. | ||
9 | |||
10 | Status of boards: | ||
11 | * iotkit (Cortex M33), no bitband | ||
12 | * mps2 (Cortex M3), bitband | ||
13 | * msf2 (Cortex M3), bitband | ||
14 | * stellaris (Cortex M3), bitband | ||
15 | * stm32f205 (Cortex M3), bitband | ||
16 | |||
17 | As a side-effect of this patch, Peter Maydell noted that the Ethernet | ||
18 | controller on mps2 board is now accessible. Previously they were hidden | ||
19 | by the bitband region (which does not exist on the real board). | ||
20 | |||
21 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
22 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
23 | Message-id: 20180814162739.11814-2-stefanha@redhat.com | ||
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200522145520.6778-7-peter.maydell@linaro.org | ||
25 | --- | 8 | --- |
26 | include/hw/arm/armv7m.h | 2 ++ | 9 | target/arm/neon-dp.decode | 20 ++++++ |
27 | hw/arm/armv7m.c | 37 ++++++++++++++++++++----------------- | 10 | target/arm/translate-neon.inc.c | 15 +++++ |
28 | hw/arm/mps2.c | 1 + | 11 | target/arm/translate.c | 110 +------------------------------- |
29 | hw/arm/msf2-soc.c | 1 + | 12 | 3 files changed, 37 insertions(+), 108 deletions(-) |
30 | hw/arm/stellaris.c | 1 + | 13 | |
31 | hw/arm/stm32f205_soc.c | 1 + | 14 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode |
32 | 6 files changed, 26 insertions(+), 17 deletions(-) | ||
33 | |||
34 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
36 | --- a/include/hw/arm/armv7m.h | 16 | --- a/target/arm/neon-dp.decode |
37 | +++ b/include/hw/arm/armv7m.h | 17 | +++ b/target/arm/neon-dp.decode |
38 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 18 | @@ -XXX,XX +XXX,XX @@ VQSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 0 . 1 .... @2reg_shrn_h |
39 | * devices will be automatically layered on top of this view.) | 19 | VQRSHRUN_64_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_d |
40 | * + Property "idau": IDAU interface (forwarded to CPU object) | 20 | VQRSHRUN_32_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_s |
41 | * + Property "init-svtor": secure VTOR reset value (forwarded to CPU object) | 21 | VQRSHRUN_16_2sh 1111 001 1 1 . ...... .... 1000 . 1 . 1 .... @2reg_shrn_h |
42 | + * + Property "enable-bitband": expose bitbanded IO | 22 | + |
43 | */ | 23 | +# VQSHRN with signed input |
44 | typedef struct ARMv7MState { | 24 | +VQSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d |
45 | /*< private >*/ | 25 | +VQSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s |
46 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState { | 26 | +VQSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h |
47 | MemoryRegion *board_memory; | 27 | + |
48 | Object *idau; | 28 | +# VQRSHRN with signed input |
49 | uint32_t init_svtor; | 29 | +VQRSHRN_S64_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d |
50 | + bool enable_bitband; | 30 | +VQRSHRN_S32_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s |
51 | } ARMv7MState; | 31 | +VQRSHRN_S16_2sh 1111 001 0 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h |
52 | 32 | + | |
53 | #endif | 33 | +# VQSHRN with unsigned input |
54 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 34 | +VQSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_d |
35 | +VQSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_s | ||
36 | +VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h | ||
37 | + | ||
38 | +# VQRSHRN with unsigned input | ||
39 | +VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d | ||
40 | +VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s | ||
41 | +VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h | ||
42 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
56 | --- a/hw/arm/armv7m.c | 44 | --- a/target/arm/translate-neon.inc.c |
57 | +++ b/hw/arm/armv7m.c | 45 | +++ b/target/arm/translate-neon.inc.c |
58 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 46 | @@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16, gen_helper_neon_unarrow_sat8) |
59 | memory_region_add_subregion(&s->container, 0xe000e000, | 47 | DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32) |
60 | sysbus_mmio_get_region(sbd, 0)); | 48 | DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16) |
61 | 49 | DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8) | |
62 | - for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { | 50 | +DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32) |
63 | - Object *obj = OBJECT(&s->bitband[i]); | 51 | +DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16) |
64 | - SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]); | 52 | +DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8) |
65 | + if (s->enable_bitband) { | 53 | + |
66 | + for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { | 54 | +DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64, gen_helper_neon_narrow_sat_s32) |
67 | + Object *obj = OBJECT(&s->bitband[i]); | 55 | +DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32, gen_helper_neon_narrow_sat_s16) |
68 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]); | 56 | +DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8) |
69 | 57 | + | |
70 | - object_property_set_int(obj, bitband_input_addr[i], "base", &err); | 58 | +DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32) |
71 | - if (err != NULL) { | 59 | +DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16) |
72 | - error_propagate(errp, err); | 60 | +DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8) |
73 | - return; | 61 | + |
74 | - } | 62 | +DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32) |
75 | - object_property_set_link(obj, OBJECT(s->board_memory), | 63 | +DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16) |
76 | - "source-memory", &error_abort); | 64 | +DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8) |
77 | - object_property_set_bool(obj, true, "realized", &err); | 65 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
78 | - if (err != NULL) { | 66 | index XXXXXXX..XXXXXXX 100644 |
79 | - error_propagate(errp, err); | 67 | --- a/target/arm/translate.c |
80 | - return; | 68 | +++ b/target/arm/translate.c |
81 | - } | 69 | @@ -XXX,XX +XXX,XX @@ static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src) |
82 | + object_property_set_int(obj, bitband_input_addr[i], "base", &err); | ||
83 | + if (err != NULL) { | ||
84 | + error_propagate(errp, err); | ||
85 | + return; | ||
86 | + } | ||
87 | + object_property_set_link(obj, OBJECT(s->board_memory), | ||
88 | + "source-memory", &error_abort); | ||
89 | + object_property_set_bool(obj, true, "realized", &err); | ||
90 | + if (err != NULL) { | ||
91 | + error_propagate(errp, err); | ||
92 | + return; | ||
93 | + } | ||
94 | |||
95 | - memory_region_add_subregion(&s->container, bitband_output_addr[i], | ||
96 | - sysbus_mmio_get_region(sbd, 0)); | ||
97 | + memory_region_add_subregion(&s->container, bitband_output_addr[i], | ||
98 | + sysbus_mmio_get_region(sbd, 0)); | ||
99 | + } | ||
100 | } | 70 | } |
101 | } | 71 | } |
102 | 72 | ||
103 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { | 73 | -static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32 shift, |
104 | MemoryRegion *), | 74 | - int q, int u) |
105 | DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *), | 75 | -{ |
106 | DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0), | 76 | - if (q) { |
107 | + DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false), | 77 | - if (u) { |
108 | DEFINE_PROP_END_OF_LIST(), | 78 | - switch (size) { |
109 | }; | 79 | - case 1: gen_helper_neon_rshl_u16(var, var, shift); break; |
110 | 80 | - case 2: gen_helper_neon_rshl_u32(var, var, shift); break; | |
111 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 81 | - default: abort(); |
112 | index XXXXXXX..XXXXXXX 100644 | 82 | - } |
113 | --- a/hw/arm/mps2.c | 83 | - } else { |
114 | +++ b/hw/arm/mps2.c | 84 | - switch (size) { |
115 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 85 | - case 1: gen_helper_neon_rshl_s16(var, var, shift); break; |
116 | g_assert_not_reached(); | 86 | - case 2: gen_helper_neon_rshl_s32(var, var, shift); break; |
117 | } | 87 | - default: abort(); |
118 | qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); | 88 | - } |
119 | + qdev_prop_set_bit(armv7m, "enable-bitband", true); | 89 | - } |
120 | object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), | 90 | - } else { |
121 | "memory", &error_abort); | 91 | - if (u) { |
122 | object_property_set_bool(OBJECT(&mms->armv7m), true, "realized", | 92 | - switch (size) { |
123 | diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c | 93 | - case 1: gen_helper_neon_shl_u16(var, var, shift); break; |
124 | index XXXXXXX..XXXXXXX 100644 | 94 | - case 2: gen_ushl_i32(var, var, shift); break; |
125 | --- a/hw/arm/msf2-soc.c | 95 | - default: abort(); |
126 | +++ b/hw/arm/msf2-soc.c | 96 | - } |
127 | @@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) | 97 | - } else { |
128 | armv7m = DEVICE(&s->armv7m); | 98 | - switch (size) { |
129 | qdev_prop_set_uint32(armv7m, "num-irq", 81); | 99 | - case 1: gen_helper_neon_shl_s16(var, var, shift); break; |
130 | qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); | 100 | - case 2: gen_sshl_i32(var, var, shift); break; |
131 | + qdev_prop_set_bit(armv7m, "enable-bitband", true); | 101 | - default: abort(); |
132 | object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), | 102 | - } |
133 | "memory", &error_abort); | 103 | - } |
134 | object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | 104 | - } |
135 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 105 | -} |
136 | index XXXXXXX..XXXXXXX 100644 | 106 | - |
137 | --- a/hw/arm/stellaris.c | 107 | static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u) |
138 | +++ b/hw/arm/stellaris.c | 108 | { |
139 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 109 | if (u) { |
140 | nvic = qdev_create(NULL, TYPE_ARMV7M); | 110 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) |
141 | qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); | 111 | case 6: /* VQSHLU */ |
142 | qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); | 112 | case 7: /* VQSHL */ |
143 | + qdev_prop_set_bit(nvic, "enable-bitband", true); | 113 | case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ |
144 | object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), | 114 | + case 9: /* VQSHRN, VQRSHRN */ |
145 | "memory", &error_abort); | 115 | return 1; /* handled by decodetree */ |
146 | /* This will exit with an error if the user passed us a bad cpu_type */ | 116 | default: |
147 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | 117 | break; |
148 | index XXXXXXX..XXXXXXX 100644 | 118 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) |
149 | --- a/hw/arm/stm32f205_soc.c | 119 | size--; |
150 | +++ b/hw/arm/stm32f205_soc.c | 120 | } |
151 | @@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | 121 | shift = (insn >> 16) & ((1 << (3 + size)) - 1); |
152 | armv7m = DEVICE(&s->armv7m); | 122 | - if (op < 10) { |
153 | qdev_prop_set_uint32(armv7m, "num-irq", 96); | 123 | - /* Shift by immediate and narrow: |
154 | qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); | 124 | - VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ |
155 | + qdev_prop_set_bit(armv7m, "enable-bitband", true); | 125 | - int input_unsigned = (op == 8) ? !u : u; |
156 | object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()), | 126 | - if (rm & 1) { |
157 | "memory", &error_abort); | 127 | - return 1; |
158 | object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); | 128 | - } |
129 | - shift = shift - (1 << (size + 3)); | ||
130 | - size++; | ||
131 | - if (size == 3) { | ||
132 | - tmp64 = tcg_const_i64(shift); | ||
133 | - neon_load_reg64(cpu_V0, rm); | ||
134 | - neon_load_reg64(cpu_V1, rm + 1); | ||
135 | - for (pass = 0; pass < 2; pass++) { | ||
136 | - TCGv_i64 in; | ||
137 | - if (pass == 0) { | ||
138 | - in = cpu_V0; | ||
139 | - } else { | ||
140 | - in = cpu_V1; | ||
141 | - } | ||
142 | - if (q) { | ||
143 | - if (input_unsigned) { | ||
144 | - gen_helper_neon_rshl_u64(cpu_V0, in, tmp64); | ||
145 | - } else { | ||
146 | - gen_helper_neon_rshl_s64(cpu_V0, in, tmp64); | ||
147 | - } | ||
148 | - } else { | ||
149 | - if (input_unsigned) { | ||
150 | - gen_ushl_i64(cpu_V0, in, tmp64); | ||
151 | - } else { | ||
152 | - gen_sshl_i64(cpu_V0, in, tmp64); | ||
153 | - } | ||
154 | - } | ||
155 | - tmp = tcg_temp_new_i32(); | ||
156 | - gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); | ||
157 | - neon_store_reg(rd, pass, tmp); | ||
158 | - } /* for pass */ | ||
159 | - tcg_temp_free_i64(tmp64); | ||
160 | - } else { | ||
161 | - if (size == 1) { | ||
162 | - imm = (uint16_t)shift; | ||
163 | - imm |= imm << 16; | ||
164 | - } else { | ||
165 | - /* size == 2 */ | ||
166 | - imm = (uint32_t)shift; | ||
167 | - } | ||
168 | - tmp2 = tcg_const_i32(imm); | ||
169 | - tmp4 = neon_load_reg(rm + 1, 0); | ||
170 | - tmp5 = neon_load_reg(rm + 1, 1); | ||
171 | - for (pass = 0; pass < 2; pass++) { | ||
172 | - if (pass == 0) { | ||
173 | - tmp = neon_load_reg(rm, 0); | ||
174 | - } else { | ||
175 | - tmp = tmp4; | ||
176 | - } | ||
177 | - gen_neon_shift_narrow(size, tmp, tmp2, q, | ||
178 | - input_unsigned); | ||
179 | - if (pass == 0) { | ||
180 | - tmp3 = neon_load_reg(rm, 1); | ||
181 | - } else { | ||
182 | - tmp3 = tmp5; | ||
183 | - } | ||
184 | - gen_neon_shift_narrow(size, tmp3, tmp2, q, | ||
185 | - input_unsigned); | ||
186 | - tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); | ||
187 | - tcg_temp_free_i32(tmp); | ||
188 | - tcg_temp_free_i32(tmp3); | ||
189 | - tmp = tcg_temp_new_i32(); | ||
190 | - gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0); | ||
191 | - neon_store_reg(rd, pass, tmp); | ||
192 | - } /* for pass */ | ||
193 | - tcg_temp_free_i32(tmp2); | ||
194 | - } | ||
195 | - } else if (op == 10) { | ||
196 | + if (op == 10) { | ||
197 | /* VSHLL, VMOVL */ | ||
198 | if (q || (rd & 1)) { | ||
199 | return 1; | ||
159 | -- | 200 | -- |
160 | 2.18.0 | 201 | 2.20.1 |
161 | 202 | ||
162 | 203 | diff view generated by jsdifflib |
1 | From: Stefan Hajnoczi <stefanha@redhat.com> | 1 | Convert the VSHLL and VMOVL insns from the 2-reg-shift group |
---|---|---|---|
2 | 2 | to decodetree. Since the loop always has two passes, we unroll | |
3 | Image file loaders may add a series of roms. If an error occurs partway | 3 | it to avoid the awkward reassignment of one TCGv to another. |
4 | through loading there is no easy way to drop previously added roms. | 4 | |
5 | |||
6 | This patch adds a transaction mechanism that works like this: | ||
7 | |||
8 | rom_transaction_begin(); | ||
9 | ...call rom_add_*()... | ||
10 | rom_transaction_end(ok); | ||
11 | |||
12 | If ok is false then roms added in this transaction are dropped. | ||
13 | |||
14 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
16 | Message-id: 20180814162739.11814-5-stefanha@redhat.com | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200522145520.6778-8-peter.maydell@linaro.org | ||
18 | --- | 8 | --- |
19 | include/hw/loader.h | 19 +++++++++++++++++++ | 9 | target/arm/neon-dp.decode | 16 +++++++ |
20 | hw/core/loader.c | 32 ++++++++++++++++++++++++++++++++ | 10 | target/arm/translate-neon.inc.c | 81 +++++++++++++++++++++++++++++++++ |
21 | 2 files changed, 51 insertions(+) | 11 | target/arm/translate.c | 46 +------------------ |
22 | 12 | 3 files changed, 99 insertions(+), 44 deletions(-) | |
23 | diff --git a/include/hw/loader.h b/include/hw/loader.h | 13 | |
14 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
24 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/include/hw/loader.h | 16 | --- a/target/arm/neon-dp.decode |
26 | +++ b/include/hw/loader.h | 17 | +++ b/target/arm/neon-dp.decode |
27 | @@ -XXX,XX +XXX,XX @@ int rom_check_and_register_reset(void); | 18 | @@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp |
28 | void rom_set_fw(FWCfgState *f); | 19 | &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 \ |
29 | void rom_set_order_override(int order); | 20 | shift=%neon_rshift_i3 |
30 | void rom_reset_order_override(void); | 21 | |
31 | + | 22 | +# Long left shifts: again Q is part of opcode decode |
32 | +/** | 23 | +@2reg_shll_s .... ... . . . 1 shift:5 .... .... 0 . . . .... \ |
33 | + * rom_transaction_begin: | 24 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=2 q=0 |
34 | + * | 25 | +@2reg_shll_h .... ... . . . 01 shift:4 .... .... 0 . . . .... \ |
35 | + * Call this before of a series of rom_add_*() calls. Call | 26 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=1 q=0 |
36 | + * rom_transaction_end() afterwards to commit or abort. These functions are | 27 | +@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \ |
37 | + * useful for undoing a series of rom_add_*() calls if image file loading fails | 28 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0 |
38 | + * partway through. | 29 | + |
39 | + */ | 30 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d |
40 | +void rom_transaction_begin(void); | 31 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s |
41 | + | 32 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h |
42 | +/** | 33 | @@ -XXX,XX +XXX,XX @@ VQSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 0 . 1 .... @2reg_shrn_h |
43 | + * rom_transaction_end: | 34 | VQRSHRN_U64_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_d |
44 | + * @commit: true to commit added roms, false to drop added roms | 35 | VQRSHRN_U32_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_s |
45 | + * | 36 | VQRSHRN_U16_2sh 1111 001 1 1 . ...... .... 1001 . 1 . 1 .... @2reg_shrn_h |
46 | + * Call this after a series of rom_add_*() calls. See rom_transaction_begin(). | 37 | + |
47 | + */ | 38 | +VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s |
48 | +void rom_transaction_end(bool commit); | 39 | +VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h |
49 | + | 40 | +VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b |
50 | int rom_copy(uint8_t *dest, hwaddr addr, size_t size); | 41 | + |
51 | void *rom_ptr(hwaddr addr, size_t size); | 42 | +VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s |
52 | void hmp_info_roms(Monitor *mon, const QDict *qdict); | 43 | +VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h |
53 | diff --git a/hw/core/loader.c b/hw/core/loader.c | 44 | +VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b |
45 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/hw/core/loader.c | 47 | --- a/target/arm/translate-neon.inc.c |
56 | +++ b/hw/core/loader.c | 48 | +++ b/target/arm/translate-neon.inc.c |
57 | @@ -XXX,XX +XXX,XX @@ struct Rom { | 49 | @@ -XXX,XX +XXX,XX @@ DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8) |
58 | char *fw_dir; | 50 | DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64, gen_helper_neon_narrow_sat_u32) |
59 | char *fw_file; | 51 | DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32, gen_helper_neon_narrow_sat_u16) |
60 | 52 | DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8) | |
61 | + bool committed; | 53 | + |
62 | + | 54 | +static bool do_vshll_2sh(DisasContext *s, arg_2reg_shift *a, |
63 | hwaddr addr; | 55 | + NeonGenWidenFn *widenfn, bool u) |
64 | QTAILQ_ENTRY(Rom) next; | ||
65 | }; | ||
66 | @@ -XXX,XX +XXX,XX @@ static void rom_insert(Rom *rom) | ||
67 | rom->as = &address_space_memory; | ||
68 | } | ||
69 | |||
70 | + rom->committed = false; | ||
71 | + | ||
72 | /* List is ordered by load address in the same address space */ | ||
73 | QTAILQ_FOREACH(item, &roms, next) { | ||
74 | if (rom_order_compare(rom, item)) { | ||
75 | @@ -XXX,XX +XXX,XX @@ void rom_reset_order_override(void) | ||
76 | fw_cfg_reset_order_override(fw_cfg); | ||
77 | } | ||
78 | |||
79 | +void rom_transaction_begin(void) | ||
80 | +{ | 56 | +{ |
81 | + Rom *rom; | 57 | + TCGv_i64 tmp; |
82 | + | 58 | + TCGv_i32 rm0, rm1; |
83 | + /* Ignore ROMs added without the transaction API */ | 59 | + uint64_t widen_mask = 0; |
84 | + QTAILQ_FOREACH(rom, &roms, next) { | 60 | + |
85 | + rom->committed = true; | 61 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
86 | + } | 62 | + return false; |
63 | + } | ||
64 | + | ||
65 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
66 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
67 | + ((a->vd | a->vm) & 0x10)) { | ||
68 | + return false; | ||
69 | + } | ||
70 | + | ||
71 | + if (a->vd & 1) { | ||
72 | + return false; | ||
73 | + } | ||
74 | + | ||
75 | + if (!vfp_access_check(s)) { | ||
76 | + return true; | ||
77 | + } | ||
78 | + | ||
79 | + /* | ||
80 | + * This is a widen-and-shift operation. The shift is always less | ||
81 | + * than the width of the source type, so after widening the input | ||
82 | + * vector we can simply shift the whole 64-bit widened register, | ||
83 | + * and then clear the potential overflow bits resulting from left | ||
84 | + * bits of the narrow input appearing as right bits of the left | ||
85 | + * neighbour narrow input. Calculate a mask of bits to clear. | ||
86 | + */ | ||
87 | + if ((a->shift != 0) && (a->size < 2 || u)) { | ||
88 | + int esize = 8 << a->size; | ||
89 | + widen_mask = MAKE_64BIT_MASK(0, esize); | ||
90 | + widen_mask >>= esize - a->shift; | ||
91 | + widen_mask = dup_const(a->size + 1, widen_mask); | ||
92 | + } | ||
93 | + | ||
94 | + rm0 = neon_load_reg(a->vm, 0); | ||
95 | + rm1 = neon_load_reg(a->vm, 1); | ||
96 | + tmp = tcg_temp_new_i64(); | ||
97 | + | ||
98 | + widenfn(tmp, rm0); | ||
99 | + if (a->shift != 0) { | ||
100 | + tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
101 | + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
102 | + } | ||
103 | + neon_store_reg64(tmp, a->vd); | ||
104 | + | ||
105 | + widenfn(tmp, rm1); | ||
106 | + if (a->shift != 0) { | ||
107 | + tcg_gen_shli_i64(tmp, tmp, a->shift); | ||
108 | + tcg_gen_andi_i64(tmp, tmp, ~widen_mask); | ||
109 | + } | ||
110 | + neon_store_reg64(tmp, a->vd + 1); | ||
111 | + tcg_temp_free_i64(tmp); | ||
112 | + return true; | ||
87 | +} | 113 | +} |
88 | + | 114 | + |
89 | +void rom_transaction_end(bool commit) | 115 | +static bool trans_VSHLL_S_2sh(DisasContext *s, arg_2reg_shift *a) |
90 | +{ | 116 | +{ |
91 | + Rom *rom; | 117 | + NeonGenWidenFn *widenfn[] = { |
92 | + Rom *tmp; | 118 | + gen_helper_neon_widen_s8, |
93 | + | 119 | + gen_helper_neon_widen_s16, |
94 | + QTAILQ_FOREACH_SAFE(rom, &roms, next, tmp) { | 120 | + tcg_gen_ext_i32_i64, |
95 | + if (rom->committed) { | 121 | + }; |
96 | + continue; | 122 | + return do_vshll_2sh(s, a, widenfn[a->size], false); |
97 | + } | ||
98 | + if (commit) { | ||
99 | + rom->committed = true; | ||
100 | + } else { | ||
101 | + QTAILQ_REMOVE(&roms, rom, next); | ||
102 | + rom_free(rom); | ||
103 | + } | ||
104 | + } | ||
105 | +} | 123 | +} |
106 | + | 124 | + |
107 | static Rom *find_rom(hwaddr addr, size_t size) | 125 | +static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) |
108 | { | 126 | +{ |
109 | Rom *rom; | 127 | + NeonGenWidenFn *widenfn[] = { |
128 | + gen_helper_neon_widen_u8, | ||
129 | + gen_helper_neon_widen_u16, | ||
130 | + tcg_gen_extu_i32_i64, | ||
131 | + }; | ||
132 | + return do_vshll_2sh(s, a, widenfn[a->size], true); | ||
133 | +} | ||
134 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/target/arm/translate.c | ||
137 | +++ b/target/arm/translate.c | ||
138 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
139 | case 7: /* VQSHL */ | ||
140 | case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ | ||
141 | case 9: /* VQSHRN, VQRSHRN */ | ||
142 | + case 10: /* VSHLL, including VMOVL */ | ||
143 | return 1; /* handled by decodetree */ | ||
144 | default: | ||
145 | break; | ||
146 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
147 | size--; | ||
148 | } | ||
149 | shift = (insn >> 16) & ((1 << (3 + size)) - 1); | ||
150 | - if (op == 10) { | ||
151 | - /* VSHLL, VMOVL */ | ||
152 | - if (q || (rd & 1)) { | ||
153 | - return 1; | ||
154 | - } | ||
155 | - tmp = neon_load_reg(rm, 0); | ||
156 | - tmp2 = neon_load_reg(rm, 1); | ||
157 | - for (pass = 0; pass < 2; pass++) { | ||
158 | - if (pass == 1) | ||
159 | - tmp = tmp2; | ||
160 | - | ||
161 | - gen_neon_widen(cpu_V0, tmp, size, u); | ||
162 | - | ||
163 | - if (shift != 0) { | ||
164 | - /* The shift is less than the width of the source | ||
165 | - type, so we can just shift the whole register. */ | ||
166 | - tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); | ||
167 | - /* Widen the result of shift: we need to clear | ||
168 | - * the potential overflow bits resulting from | ||
169 | - * left bits of the narrow input appearing as | ||
170 | - * right bits of left the neighbour narrow | ||
171 | - * input. */ | ||
172 | - if (size < 2 || !u) { | ||
173 | - uint64_t imm64; | ||
174 | - if (size == 0) { | ||
175 | - imm = (0xffu >> (8 - shift)); | ||
176 | - imm |= imm << 16; | ||
177 | - } else if (size == 1) { | ||
178 | - imm = 0xffff >> (16 - shift); | ||
179 | - } else { | ||
180 | - /* size == 2 */ | ||
181 | - imm = 0xffffffff >> (32 - shift); | ||
182 | - } | ||
183 | - if (size < 2) { | ||
184 | - imm64 = imm | (((uint64_t)imm) << 32); | ||
185 | - } else { | ||
186 | - imm64 = imm; | ||
187 | - } | ||
188 | - tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64); | ||
189 | - } | ||
190 | - } | ||
191 | - neon_store_reg64(cpu_V0, rd + pass); | ||
192 | - } | ||
193 | - } else if (op >= 14) { | ||
194 | + if (op >= 14) { | ||
195 | /* VCVT fixed-point. */ | ||
196 | TCGv_ptr fpst; | ||
197 | TCGv_i32 shiftv; | ||
110 | -- | 198 | -- |
111 | 2.18.0 | 199 | 2.20.1 |
112 | 200 | ||
113 | 201 | diff view generated by jsdifflib |
1 | From: Stefan Hajnoczi <stefanha@redhat.com> | 1 | Convert the VCVT fixed-point conversion operations in the |
---|---|---|---|
2 | Neon 2-regs-and-shift group to decodetree. | ||
2 | 3 | ||
3 | The next patch will need to free a rom. There is already code to do | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | this in rom_add_file(). | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20200522145520.6778-9-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 11 +++++ | ||
9 | target/arm/translate-neon.inc.c | 49 +++++++++++++++++++++ | ||
10 | target/arm/translate.c | 75 +-------------------------------- | ||
11 | 3 files changed, 62 insertions(+), 73 deletions(-) | ||
5 | 12 | ||
6 | Note that rom_add_file() uses: | 13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode |
7 | |||
8 | rom = g_malloc0(sizeof(*rom)); | ||
9 | ... | ||
10 | if (rom->fw_dir) { | ||
11 | g_free(rom->fw_dir); | ||
12 | g_free(rom->fw_file); | ||
13 | } | ||
14 | |||
15 | The conditional is unnecessary since g_free(NULL) is a no-op. | ||
16 | |||
17 | Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
18 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
19 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
20 | Message-id: 20180814162739.11814-4-stefanha@redhat.com | ||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | --- | ||
23 | hw/core/loader.c | 21 ++++++++++++--------- | ||
24 | 1 file changed, 12 insertions(+), 9 deletions(-) | ||
25 | |||
26 | diff --git a/hw/core/loader.c b/hw/core/loader.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/hw/core/loader.c | 15 | --- a/target/arm/neon-dp.decode |
29 | +++ b/hw/core/loader.c | 16 | +++ b/target/arm/neon-dp.decode |
30 | @@ -XXX,XX +XXX,XX @@ struct Rom { | 17 | @@ -XXX,XX +XXX,XX @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp |
31 | static FWCfgState *fw_cfg; | 18 | @2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \ |
32 | static QTAILQ_HEAD(, Rom) roms = QTAILQ_HEAD_INITIALIZER(roms); | 19 | &2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0 |
33 | 20 | ||
34 | +/* rom->data must be heap-allocated (do not use with rom_add_elf_program()) */ | 21 | +# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings. |
35 | +static void rom_free(Rom *rom) | 22 | +@2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \ |
23 | + &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5 | ||
24 | + | ||
25 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_d | ||
26 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_s | ||
27 | VSHR_S_2sh 1111 001 0 1 . ...... .... 0000 . . . 1 .... @2reg_shr_h | ||
28 | @@ -XXX,XX +XXX,XX @@ VSHLL_S_2sh 1111 001 0 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b | ||
29 | VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_s | ||
30 | VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_h | ||
31 | VSHLL_U_2sh 1111 001 1 1 . ...... .... 1010 . 0 . 1 .... @2reg_shll_b | ||
32 | + | ||
33 | +# VCVT fixed<->float conversions | ||
34 | +# TODO: FP16 fixed<->float conversions are opc==0b1100 and 0b1101 | ||
35 | +VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt | ||
36 | +VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt | ||
37 | +VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt | ||
38 | +VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt | ||
39 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/translate-neon.inc.c | ||
42 | +++ b/target/arm/translate-neon.inc.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) | ||
44 | }; | ||
45 | return do_vshll_2sh(s, a, widenfn[a->size], true); | ||
46 | } | ||
47 | + | ||
48 | +static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, | ||
49 | + NeonGenTwoSingleOPFn *fn) | ||
36 | +{ | 50 | +{ |
37 | + g_free(rom->data); | 51 | + /* FP operations in 2-reg-and-shift group */ |
38 | + g_free(rom->path); | 52 | + TCGv_i32 tmp, shiftv; |
39 | + g_free(rom->name); | 53 | + TCGv_ptr fpstatus; |
40 | + g_free(rom->fw_dir); | 54 | + int pass; |
41 | + g_free(rom->fw_file); | 55 | + |
42 | + g_free(rom); | 56 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { |
57 | + return false; | ||
58 | + } | ||
59 | + | ||
60 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
61 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
62 | + ((a->vd | a->vm) & 0x10)) { | ||
63 | + return false; | ||
64 | + } | ||
65 | + | ||
66 | + if ((a->vm | a->vd) & a->q) { | ||
67 | + return false; | ||
68 | + } | ||
69 | + | ||
70 | + if (!vfp_access_check(s)) { | ||
71 | + return true; | ||
72 | + } | ||
73 | + | ||
74 | + fpstatus = get_fpstatus_ptr(1); | ||
75 | + shiftv = tcg_const_i32(a->shift); | ||
76 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
77 | + tmp = neon_load_reg(a->vm, pass); | ||
78 | + fn(tmp, tmp, shiftv, fpstatus); | ||
79 | + neon_store_reg(a->vd, pass, tmp); | ||
80 | + } | ||
81 | + tcg_temp_free_ptr(fpstatus); | ||
82 | + tcg_temp_free_i32(shiftv); | ||
83 | + return true; | ||
43 | +} | 84 | +} |
44 | + | 85 | + |
45 | static inline bool rom_order_compare(Rom *rom, Rom *item) | 86 | +#define DO_FP_2SH(INSN, FUNC) \ |
46 | { | 87 | + static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \ |
47 | return ((uintptr_t)(void *)rom->as > (uintptr_t)(void *)item->as) || | 88 | + { \ |
48 | @@ -XXX,XX +XXX,XX @@ err: | 89 | + return do_fp_2sh(s, a, FUNC); \ |
49 | if (fd != -1) | 90 | + } |
50 | close(fd); | 91 | + |
51 | 92 | +DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) | |
52 | - g_free(rom->data); | 93 | +DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) |
53 | - g_free(rom->path); | 94 | +DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) |
54 | - g_free(rom->name); | 95 | +DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) |
55 | - if (fw_dir) { | 96 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
56 | - g_free(rom->fw_dir); | 97 | index XXXXXXX..XXXXXXX 100644 |
57 | - g_free(rom->fw_file); | 98 | --- a/target/arm/translate.c |
58 | - } | 99 | +++ b/target/arm/translate.c |
59 | - g_free(rom); | 100 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) |
101 | int q; | ||
102 | int rd, rn, rm, rd_ofs, rn_ofs, rm_ofs; | ||
103 | int size; | ||
104 | - int shift; | ||
105 | int pass; | ||
106 | int u; | ||
107 | int vec_size; | ||
108 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
109 | return 1; | ||
110 | } else if (insn & (1 << 4)) { | ||
111 | if ((insn & 0x00380080) != 0) { | ||
112 | - /* Two registers and shift. */ | ||
113 | - op = (insn >> 8) & 0xf; | ||
60 | - | 114 | - |
61 | + rom_free(rom); | 115 | - switch (op) { |
62 | return -1; | 116 | - case 0: /* VSHR */ |
63 | } | 117 | - case 1: /* VSRA */ |
118 | - case 2: /* VRSHR */ | ||
119 | - case 3: /* VRSRA */ | ||
120 | - case 4: /* VSRI */ | ||
121 | - case 5: /* VSHL, VSLI */ | ||
122 | - case 6: /* VQSHLU */ | ||
123 | - case 7: /* VQSHL */ | ||
124 | - case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */ | ||
125 | - case 9: /* VQSHRN, VQRSHRN */ | ||
126 | - case 10: /* VSHLL, including VMOVL */ | ||
127 | - return 1; /* handled by decodetree */ | ||
128 | - default: | ||
129 | - break; | ||
130 | - } | ||
131 | - | ||
132 | - if (insn & (1 << 7)) { | ||
133 | - /* 64-bit shift. */ | ||
134 | - if (op > 7) { | ||
135 | - return 1; | ||
136 | - } | ||
137 | - size = 3; | ||
138 | - } else { | ||
139 | - size = 2; | ||
140 | - while ((insn & (1 << (size + 19))) == 0) | ||
141 | - size--; | ||
142 | - } | ||
143 | - shift = (insn >> 16) & ((1 << (3 + size)) - 1); | ||
144 | - if (op >= 14) { | ||
145 | - /* VCVT fixed-point. */ | ||
146 | - TCGv_ptr fpst; | ||
147 | - TCGv_i32 shiftv; | ||
148 | - VFPGenFixPointFn *fn; | ||
149 | - | ||
150 | - if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) { | ||
151 | - return 1; | ||
152 | - } | ||
153 | - | ||
154 | - if (!(op & 1)) { | ||
155 | - if (u) { | ||
156 | - fn = gen_helper_vfp_ultos; | ||
157 | - } else { | ||
158 | - fn = gen_helper_vfp_sltos; | ||
159 | - } | ||
160 | - } else { | ||
161 | - if (u) { | ||
162 | - fn = gen_helper_vfp_touls_round_to_zero; | ||
163 | - } else { | ||
164 | - fn = gen_helper_vfp_tosls_round_to_zero; | ||
165 | - } | ||
166 | - } | ||
167 | - | ||
168 | - /* We have already masked out the must-be-1 top bit of imm6, | ||
169 | - * hence this 32-shift where the ARM ARM has 64-imm6. | ||
170 | - */ | ||
171 | - shift = 32 - shift; | ||
172 | - fpst = get_fpstatus_ptr(1); | ||
173 | - shiftv = tcg_const_i32(shift); | ||
174 | - for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
175 | - TCGv_i32 tmpf = neon_load_reg(rm, pass); | ||
176 | - fn(tmpf, tmpf, shiftv, fpst); | ||
177 | - neon_store_reg(rd, pass, tmpf); | ||
178 | - } | ||
179 | - tcg_temp_free_ptr(fpst); | ||
180 | - tcg_temp_free_i32(shiftv); | ||
181 | - } else { | ||
182 | - return 1; | ||
183 | - } | ||
184 | + /* Two registers and shift: handled by decodetree */ | ||
185 | + return 1; | ||
186 | } else { /* (insn & 0x00380080) == 0 */ | ||
187 | int invert, reg_ofs, vec_size; | ||
64 | 188 | ||
65 | -- | 189 | -- |
66 | 2.18.0 | 190 | 2.20.1 |
67 | 191 | ||
68 | 192 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Convert the insns in the one-register-and-immediate group to decodetree. |
---|---|---|---|
2 | 2 | ||
3 | The scaling should be solely on the memory operation size; the number | 3 | In the new decode, our asimd_imm_const() function returns a 64-bit value |
4 | of registers being loaded does not come in to the initial computation. | 4 | rather than a 32-bit one, which means we don't need to treat cmode=14 op=1 |
5 | 5 | as a special case in the decoder (it is the only encoding where the two | |
6 | Cc: qemu-stable@nongnu.org (3.0.1) | 6 | halves of the 64-bit value are different). |
7 | Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 7 | |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
10 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20200522145520.6778-10-peter.maydell@linaro.org | ||
12 | --- | 11 | --- |
13 | target/arm/translate-sve.c | 5 ++--- | 12 | target/arm/neon-dp.decode | 22 ++++++ |
14 | 1 file changed, 2 insertions(+), 3 deletions(-) | 13 | target/arm/translate-neon.inc.c | 118 ++++++++++++++++++++++++++++++++ |
15 | 14 | target/arm/translate.c | 101 +-------------------------- | |
16 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 15 | 3 files changed, 142 insertions(+), 99 deletions(-) |
16 | |||
17 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate-sve.c | 19 | --- a/target/arm/neon-dp.decode |
19 | +++ b/target/arm/translate-sve.c | 20 | +++ b/target/arm/neon-dp.decode |
20 | @@ -XXX,XX +XXX,XX @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn) | 21 | @@ -XXX,XX +XXX,XX @@ VCVT_SF_2sh 1111 001 0 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt |
21 | } | 22 | VCVT_UF_2sh 1111 001 1 1 . ...... .... 1110 0 . . 1 .... @2reg_vcvt |
22 | if (sve_access_check(s)) { | 23 | VCVT_FS_2sh 1111 001 0 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt |
23 | TCGv_i64 addr = new_tmp_a64(s); | 24 | VCVT_FU_2sh 1111 001 1 1 . ...... .... 1111 0 . . 1 .... @2reg_vcvt |
24 | - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), | 25 | + |
25 | - (a->nreg + 1) << dtype_msz(a->dtype)); | 26 | +###################################################################### |
26 | + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); | 27 | +# 1-reg-and-modified-immediate grouping: |
27 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | 28 | +# 1111 001 i 1 D 000 imm:3 Vd:4 cmode:4 0 Q op 1 Vm:4 |
28 | do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg); | 29 | +###################################################################### |
29 | } | 30 | + |
30 | @@ -XXX,XX +XXX,XX @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn) | 31 | +&1reg_imm vd q imm cmode op |
31 | } | 32 | + |
32 | if (sve_access_check(s)) { | 33 | +%asimd_imm_value 24:1 16:3 0:4 |
33 | TCGv_i64 addr = new_tmp_a64(s); | 34 | + |
34 | - tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz); | 35 | +@1reg_imm .... ... . . . ... ... .... .... . q:1 . . .... \ |
35 | + tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz); | 36 | + &1reg_imm imm=%asimd_imm_value vd=%vd_dp |
36 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | 37 | + |
37 | do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg); | 38 | +# The cmode/op bits here decode VORR/VBIC/VMOV/VMNV, but |
38 | } | 39 | +# not in a way we can conveniently represent in decodetree without |
40 | +# a lot of repetition: | ||
41 | +# VORR: op=0, (cmode & 1) && cmode < 12 | ||
42 | +# VBIC: op=1, (cmode & 1) && cmode < 12 | ||
43 | +# VMOV: everything else | ||
44 | +# So we have a single decode line and check the cmode/op in the | ||
45 | +# trans function. | ||
46 | +Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
47 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/translate-neon.inc.c | ||
50 | +++ b/target/arm/translate-neon.inc.c | ||
51 | @@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos) | ||
52 | DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos) | ||
53 | DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero) | ||
54 | DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero) | ||
55 | + | ||
56 | +static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op) | ||
57 | +{ | ||
58 | + /* | ||
59 | + * Expand the encoded constant. | ||
60 | + * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
61 | + * We choose to not special-case this and will behave as if a | ||
62 | + * valid constant encoding of 0 had been given. | ||
63 | + * cmode = 15 op = 1 must UNDEF; we assume decode has handled that. | ||
64 | + */ | ||
65 | + switch (cmode) { | ||
66 | + case 0: case 1: | ||
67 | + /* no-op */ | ||
68 | + break; | ||
69 | + case 2: case 3: | ||
70 | + imm <<= 8; | ||
71 | + break; | ||
72 | + case 4: case 5: | ||
73 | + imm <<= 16; | ||
74 | + break; | ||
75 | + case 6: case 7: | ||
76 | + imm <<= 24; | ||
77 | + break; | ||
78 | + case 8: case 9: | ||
79 | + imm |= imm << 16; | ||
80 | + break; | ||
81 | + case 10: case 11: | ||
82 | + imm = (imm << 8) | (imm << 24); | ||
83 | + break; | ||
84 | + case 12: | ||
85 | + imm = (imm << 8) | 0xff; | ||
86 | + break; | ||
87 | + case 13: | ||
88 | + imm = (imm << 16) | 0xffff; | ||
89 | + break; | ||
90 | + case 14: | ||
91 | + if (op) { | ||
92 | + /* | ||
93 | + * This is the only case where the top and bottom 32 bits | ||
94 | + * of the encoded constant differ. | ||
95 | + */ | ||
96 | + uint64_t imm64 = 0; | ||
97 | + int n; | ||
98 | + | ||
99 | + for (n = 0; n < 8; n++) { | ||
100 | + if (imm & (1 << n)) { | ||
101 | + imm64 |= (0xffULL << (n * 8)); | ||
102 | + } | ||
103 | + } | ||
104 | + return imm64; | ||
105 | + } | ||
106 | + imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
107 | + break; | ||
108 | + case 15: | ||
109 | + imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
110 | + | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
111 | + break; | ||
112 | + } | ||
113 | + if (op) { | ||
114 | + imm = ~imm; | ||
115 | + } | ||
116 | + return dup_const(MO_32, imm); | ||
117 | +} | ||
118 | + | ||
119 | +static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a, | ||
120 | + GVecGen2iFn *fn) | ||
121 | +{ | ||
122 | + uint64_t imm; | ||
123 | + int reg_ofs, vec_size; | ||
124 | + | ||
125 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
126 | + return false; | ||
127 | + } | ||
128 | + | ||
129 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
130 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
131 | + return false; | ||
132 | + } | ||
133 | + | ||
134 | + if (a->vd & a->q) { | ||
135 | + return false; | ||
136 | + } | ||
137 | + | ||
138 | + if (!vfp_access_check(s)) { | ||
139 | + return true; | ||
140 | + } | ||
141 | + | ||
142 | + reg_ofs = neon_reg_offset(a->vd, 0); | ||
143 | + vec_size = a->q ? 16 : 8; | ||
144 | + imm = asimd_imm_const(a->imm, a->cmode, a->op); | ||
145 | + | ||
146 | + fn(MO_64, reg_ofs, reg_ofs, imm, vec_size, vec_size); | ||
147 | + return true; | ||
148 | +} | ||
149 | + | ||
150 | +static void gen_VMOV_1r(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
151 | + int64_t c, uint32_t oprsz, uint32_t maxsz) | ||
152 | +{ | ||
153 | + tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); | ||
154 | +} | ||
155 | + | ||
156 | +static bool trans_Vimm_1r(DisasContext *s, arg_1reg_imm *a) | ||
157 | +{ | ||
158 | + /* Handle decode of cmode/op here between VORR/VBIC/VMOV */ | ||
159 | + GVecGen2iFn *fn; | ||
160 | + | ||
161 | + if ((a->cmode & 1) && a->cmode < 12) { | ||
162 | + /* for op=1, the imm will be inverted, so BIC becomes AND. */ | ||
163 | + fn = a->op ? tcg_gen_gvec_andi : tcg_gen_gvec_ori; | ||
164 | + } else { | ||
165 | + /* There is one unallocated cmode/op combination in this space */ | ||
166 | + if (a->cmode == 15 && a->op == 1) { | ||
167 | + return false; | ||
168 | + } | ||
169 | + fn = gen_VMOV_1r; | ||
170 | + } | ||
171 | + return do_1reg_imm(s, a, fn); | ||
172 | +} | ||
173 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
174 | index XXXXXXX..XXXXXXX 100644 | ||
175 | --- a/target/arm/translate.c | ||
176 | +++ b/target/arm/translate.c | ||
177 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
178 | /* Three register same length: handled by decodetree */ | ||
179 | return 1; | ||
180 | } else if (insn & (1 << 4)) { | ||
181 | - if ((insn & 0x00380080) != 0) { | ||
182 | - /* Two registers and shift: handled by decodetree */ | ||
183 | - return 1; | ||
184 | - } else { /* (insn & 0x00380080) == 0 */ | ||
185 | - int invert, reg_ofs, vec_size; | ||
186 | - | ||
187 | - if (q && (rd & 1)) { | ||
188 | - return 1; | ||
189 | - } | ||
190 | - | ||
191 | - op = (insn >> 8) & 0xf; | ||
192 | - /* One register and immediate. */ | ||
193 | - imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); | ||
194 | - invert = (insn & (1 << 5)) != 0; | ||
195 | - /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE. | ||
196 | - * We choose to not special-case this and will behave as if a | ||
197 | - * valid constant encoding of 0 had been given. | ||
198 | - */ | ||
199 | - switch (op) { | ||
200 | - case 0: case 1: | ||
201 | - /* no-op */ | ||
202 | - break; | ||
203 | - case 2: case 3: | ||
204 | - imm <<= 8; | ||
205 | - break; | ||
206 | - case 4: case 5: | ||
207 | - imm <<= 16; | ||
208 | - break; | ||
209 | - case 6: case 7: | ||
210 | - imm <<= 24; | ||
211 | - break; | ||
212 | - case 8: case 9: | ||
213 | - imm |= imm << 16; | ||
214 | - break; | ||
215 | - case 10: case 11: | ||
216 | - imm = (imm << 8) | (imm << 24); | ||
217 | - break; | ||
218 | - case 12: | ||
219 | - imm = (imm << 8) | 0xff; | ||
220 | - break; | ||
221 | - case 13: | ||
222 | - imm = (imm << 16) | 0xffff; | ||
223 | - break; | ||
224 | - case 14: | ||
225 | - imm |= (imm << 8) | (imm << 16) | (imm << 24); | ||
226 | - if (invert) { | ||
227 | - imm = ~imm; | ||
228 | - } | ||
229 | - break; | ||
230 | - case 15: | ||
231 | - if (invert) { | ||
232 | - return 1; | ||
233 | - } | ||
234 | - imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ||
235 | - | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); | ||
236 | - break; | ||
237 | - } | ||
238 | - if (invert) { | ||
239 | - imm = ~imm; | ||
240 | - } | ||
241 | - | ||
242 | - reg_ofs = neon_reg_offset(rd, 0); | ||
243 | - vec_size = q ? 16 : 8; | ||
244 | - | ||
245 | - if (op & 1 && op < 12) { | ||
246 | - if (invert) { | ||
247 | - /* The immediate value has already been inverted, | ||
248 | - * so BIC becomes AND. | ||
249 | - */ | ||
250 | - tcg_gen_gvec_andi(MO_32, reg_ofs, reg_ofs, imm, | ||
251 | - vec_size, vec_size); | ||
252 | - } else { | ||
253 | - tcg_gen_gvec_ori(MO_32, reg_ofs, reg_ofs, imm, | ||
254 | - vec_size, vec_size); | ||
255 | - } | ||
256 | - } else { | ||
257 | - /* VMOV, VMVN. */ | ||
258 | - if (op == 14 && invert) { | ||
259 | - TCGv_i64 t64 = tcg_temp_new_i64(); | ||
260 | - | ||
261 | - for (pass = 0; pass <= q; ++pass) { | ||
262 | - uint64_t val = 0; | ||
263 | - int n; | ||
264 | - | ||
265 | - for (n = 0; n < 8; n++) { | ||
266 | - if (imm & (1 << (n + pass * 8))) { | ||
267 | - val |= 0xffull << (n * 8); | ||
268 | - } | ||
269 | - } | ||
270 | - tcg_gen_movi_i64(t64, val); | ||
271 | - neon_store_reg64(t64, rd + pass); | ||
272 | - } | ||
273 | - tcg_temp_free_i64(t64); | ||
274 | - } else { | ||
275 | - tcg_gen_gvec_dup_imm(MO_32, reg_ofs, vec_size, | ||
276 | - vec_size, imm); | ||
277 | - } | ||
278 | - } | ||
279 | - } | ||
280 | + /* Two registers and shift or reg and imm: handled by decodetree */ | ||
281 | + return 1; | ||
282 | } else { /* (insn & 0x00800010 == 0x00800000) */ | ||
283 | if (size != 3) { | ||
284 | op = (insn >> 8) & 0xf; | ||
39 | -- | 285 | -- |
40 | 2.18.0 | 286 | 2.20.1 |
41 | 287 | ||
42 | 288 | diff view generated by jsdifflib |