ARMv7VE introduced the ERET instruction, which is necessary to
return from an exception taken to Hyp mode. Implement this.
In A32 encoding it is a completely new encoding; in T32 it
is an adjustment of the behaviour of the existing
"SUBS PC, LR, #<imm8>" instruction.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 31 +++++++++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3f5751d4826..5ecc24f12fb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8887,6 +8887,25 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
tcg_temp_free_i32(tmp2);
store_reg(s, rd, tmp);
break;
+ case 0x6: /* ERET */
+ if (op1 != 3) {
+ goto illegal_op;
+ }
+ if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
+ goto illegal_op;
+ }
+ if ((insn & 0x000fff0f) != 0x0000000e) {
+ /* UNPREDICTABLE; we choose to UNDEF */
+ goto illegal_op;
+ }
+
+ if (s->current_el == 2) {
+ tmp = load_cpu_field(elr_el[2]);
+ } else {
+ tmp = load_reg(s, 14);
+ }
+ gen_exception_return(s, tmp);
+ break;
case 7:
{
int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
@@ -11144,8 +11163,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
if (rn != 14 || rd != 15) {
goto illegal_op;
}
- tmp = load_reg(s, rn);
- tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
+ if (s->current_el == 2) {
+ /* ERET from Hyp uses ELR_Hyp, not LR */
+ if (insn & 0xff) {
+ goto illegal_op;
+ }
+ tmp = load_cpu_field(elr_el[2]);
+ } else {
+ tmp = load_reg(s, rn);
+ tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
+ }
gen_exception_return(s, tmp);
break;
case 6: /* MRS */
--
2.18.0
On Tue, Aug 14, 2018 at 01:42:53PM +0100, Peter Maydell wrote:
> ARMv7VE introduced the ERET instruction, which is necessary to
> return from an exception taken to Hyp mode. Implement this.
> In A32 encoding it is a completely new encoding; in T32 it
> is an adjustment of the behaviour of the existing
> "SUBS PC, LR, #<imm8>" instruction.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/translate.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 3f5751d4826..5ecc24f12fb 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8887,6 +8887,25 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> + case 0x6: /* ERET */
> + if (op1 != 3) {
> + goto illegal_op;
> + }
> + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
> + goto illegal_op;
> + }
> + if ((insn & 0x000fff0f) != 0x0000000e) {
> + /* UNPREDICTABLE; we choose to UNDEF */
> + goto illegal_op;
> + }
> +
> + if (s->current_el == 2) {
> + tmp = load_cpu_field(elr_el[2]);
> + } else {
> + tmp = load_reg(s, 14);
> + }
> + gen_exception_return(s, tmp);
> + break;
> case 7:
> {
> int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
> @@ -11144,8 +11163,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> if (rn != 14 || rd != 15) {
> goto illegal_op;
> }
> - tmp = load_reg(s, rn);
> - tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
> + if (s->current_el == 2) {
> + /* ERET from Hyp uses ELR_Hyp, not LR */
> + if (insn & 0xff) {
> + goto illegal_op;
> + }
> + tmp = load_cpu_field(elr_el[2]);
> + } else {
> + tmp = load_reg(s, rn);
> + tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
> + }
> gen_exception_return(s, tmp);
> break;
> case 6: /* MRS */
> --
> 2.18.0
>
On 8/14/18 2:42 PM, Peter Maydell wrote:
> ARMv7VE introduced the ERET instruction, which is necessary to
> return from an exception taken to Hyp mode. Implement this.
> In A32 encoding it is a completely new encoding; in T32 it
> is an adjustment of the behaviour of the existing
> "SUBS PC, LR, #<imm8>" instruction.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-By: Luc Michel <luc.michel@greensocs.com>
> ---
> target/arm/translate.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 3f5751d4826..5ecc24f12fb 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8887,6 +8887,25 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> tcg_temp_free_i32(tmp2);
> store_reg(s, rd, tmp);
> break;
> + case 0x6: /* ERET */
> + if (op1 != 3) {
> + goto illegal_op;
> + }
> + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) {
> + goto illegal_op;
> + }
> + if ((insn & 0x000fff0f) != 0x0000000e) {
> + /* UNPREDICTABLE; we choose to UNDEF */
> + goto illegal_op;
> + }
> +
> + if (s->current_el == 2) {
> + tmp = load_cpu_field(elr_el[2]);
> + } else {
> + tmp = load_reg(s, 14);
> + }
> + gen_exception_return(s, tmp);
> + break;
> case 7:
> {
> int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4);
> @@ -11144,8 +11163,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
> if (rn != 14 || rd != 15) {
> goto illegal_op;
> }
> - tmp = load_reg(s, rn);
> - tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
> + if (s->current_el == 2) {
> + /* ERET from Hyp uses ELR_Hyp, not LR */
> + if (insn & 0xff) {
> + goto illegal_op;
> + }
> + tmp = load_cpu_field(elr_el[2]);
> + } else {
> + tmp = load_reg(s, rn);
> + tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
> + }
> gen_exception_return(s, tmp);
> break;
> case 6: /* MRS */
>
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