[Qemu-devel] [PULL 0/6] target-arm queue
[PULL v2 00/57] target-arm queue
1
A set of small bugfixes for arm for 3.0; the "migration was
1
Squashed in a trivial fix for 32-bit hosts:
2
broken" fixes for SMMUv3 and v7M NVIC with security extensions
3
are the most significant.
4
2
5
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
6
-- PMM
15
-- PMM
7
16
8
The following changes since commit 6d9dd5fb9d0e9f4a174f53a0e20a39fbe809c71e:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
9
18
10
Merge remote-tracking branch 'remotes/armbru/tags/pull-qobject-2018-07-27-v2' into staging (2018-07-30 09:55:47 +0100)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
11
20
12
are available in the Git repository at:
21
are available in the Git repository at:
13
22
14
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180730
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
15
24
16
for you to fetch changes up to 0261fb805c00a6f97d143235e7b06b0906bdf898:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
17
26
18
target/arm: Remove duplicate 'host' entry in '-cpu ?' output (2018-07-30 15:07:08 +0100)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
19
28
20
----------------------------------------------------------------
29
----------------------------------------------------------------
21
target-arm queue:
30
target-arm queue:
22
* arm/smmuv3: Fix broken VM state migration
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
23
* armv7m_nvic: Fix broken VM state migration
32
* docs: Document which architecture extensions we emulate
24
* hw/arm/sysbus-fdt: Fix assertion in copy_properties_from_host()
33
* Fix bugs in M-profile FPCXT_NS accesses
25
* hw/arm/iotkit: Fix IRQ number for timer1
34
* First slice of MVE patches
26
* hw/misc/tz-mpc: Zero the LUT on initialization, not just reset
35
* Implement MTE3
27
* target/arm: Remove duplicate 'host' entry in '-cpu ?' output
36
* docs/system: arm: Add nRF boards description
28
37
29
----------------------------------------------------------------
38
----------------------------------------------------------------
30
Dr. David Alan Gilbert (1):
39
Alexandre Iooss (1):
31
arm/smmuv3: Fix missing VMSD terminator
40
docs/system: arm: Add nRF boards description
32
41
33
Geert Uytterhoeven (1):
42
Peter Collingbourne (1):
34
hw/arm/sysbus-fdt: Fix assertion in copy_properties_from_host()
43
target/arm: Implement MTE3
35
44
36
Peter Maydell (3):
45
Peter Maydell (55):
37
armv7m_nvic: Fix m-security subsection name
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
38
hw/arm/iotkit: Fix IRQ number for timer1
47
hw/acpi: Provide function acpi_ghes_present()
39
hw/misc/tz-mpc: Zero the LUT on initialization, not just reset
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
40
101
41
Philippe Mathieu-Daudé (1):
102
docs/system/arm/emulation.rst | 103 ++++
42
target/arm: Remove duplicate 'host' entry in '-cpu ?' output
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
43
135
44
hw/arm/iotkit.c | 2 +-
45
hw/arm/smmuv3.c | 1 +
46
hw/arm/sysbus-fdt.c | 1 +
47
hw/intc/armv7m_nvic.c | 2 +-
48
hw/misc/tz-mpc.c | 2 +-
49
target/arm/helper.c | 6 ------
50
6 files changed, 5 insertions(+), 9 deletions(-)
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/6] arm/smmuv3: Fix missing VMSD terminator
Deleted patch
1
From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
2
1
3
The 'vmstate_smmuv3_queue' is missing the end-of-list marker.
4
5
Fixes: 10a83cb9887
6
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
7
Message-id: 20180727135406.15132-1-dgilbert@redhat.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
[PMM: dropped stray blank line]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/smmuv3.c | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/smmuv3.c
18
+++ b/hw/arm/smmuv3.c
19
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
20
VMSTATE_UINT32(prod, SMMUQueue),
21
VMSTATE_UINT32(cons, SMMUQueue),
22
VMSTATE_UINT8(log2size, SMMUQueue),
23
+ VMSTATE_END_OF_LIST(),
24
},
25
};
26
27
--
28
2.17.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/6] hw/arm/sysbus-fdt: Fix assertion in copy_properties_from_host()
Deleted patch
1
From: Geert Uytterhoeven <geert+renesas@glider.be>
2
1
3
When copy_properties_from_host() ignores the error for an optional
4
property, it frees the error, but fails to reset it.
5
6
Hence if two or more optional properties are missing, an assertion is
7
triggered:
8
9
util/error.c:57: error_setv: Assertion `*errp == NULL' failed.
10
11
Fis this by resetting err to NULL after ignoring the error.
12
13
Fixes: 9481cf2e5f2f2bb6 ("hw/arm/sysbus-fdt: helpers for clock node generation")
14
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
15
Message-id: 20180725113000.11014-1-geert+renesas@glider.be
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
hw/arm/sysbus-fdt.c | 1 +
20
1 file changed, 1 insertion(+)
21
22
diff --git a/hw/arm/sysbus-fdt.c b/hw/arm/sysbus-fdt.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/arm/sysbus-fdt.c
25
+++ b/hw/arm/sysbus-fdt.c
26
@@ -XXX,XX +XXX,XX @@ static void copy_properties_from_host(HostProperty *props, int nb_props,
27
/* mandatory property not found: bail out */
28
exit(1);
29
}
30
+ err = NULL;
31
}
32
}
33
}
34
--
35
2.17.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/6] armv7m_nvic: Fix m-security subsection name
Deleted patch
1
The vmstate save/load code insists that subsections of a VMState must
2
have names which include their parent VMState's name as a leading
3
substring. Unfortunately it neither documents this nor checks it on
4
device init or state save, but instead fails state load with a
5
confusing error message ("Missing section footer for armv7m_nvic").
6
1
7
Fix the name of the m-security subsection of the NVIC, so that
8
state save/load works correctly for the security-enabled NVIC.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20180727113854.20283-2-peter.maydell@linaro.org
13
---
14
hw/intc/armv7m_nvic.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
20
+++ b/hw/intc/armv7m_nvic.c
21
@@ -XXX,XX +XXX,XX @@ static int nvic_security_post_load(void *opaque, int version_id)
22
}
23
24
static const VMStateDescription vmstate_nvic_security = {
25
- .name = "nvic/m-security",
26
+ .name = "armv7m_nvic/m-security",
27
.version_id = 1,
28
.minimum_version_id = 1,
29
.needed = nvic_security_needed,
30
--
31
2.17.1
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/6] hw/arm/iotkit: Fix IRQ number for timer1
Deleted patch
1
A cut-and-paste error meant we were incorrectly wiring up the timer1
2
IRQ to IRQ3. IRQ3 is the interrupt for timer0 -- move timer0 to
3
IRQ4 where it belongs.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180727113854.20283-3-peter.maydell@linaro.org
8
---
9
hw/arm/iotkit.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/hw/arm/iotkit.c b/hw/arm/iotkit.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/arm/iotkit.c
15
+++ b/hw/arm/iotkit.c
16
@@ -XXX,XX +XXX,XX @@ static void iotkit_realize(DeviceState *dev, Error **errp)
17
return;
18
}
19
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer1), 0,
20
- qdev_get_gpio_in(DEVICE(&s->armv7m), 3));
21
+ qdev_get_gpio_in(DEVICE(&s->armv7m), 4));
22
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->timer1), 0);
23
object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr), "port[1]", &err);
24
if (err) {
25
--
26
2.17.1
27
28
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/6] hw/misc/tz-mpc: Zero the LUT on initialization, not just reset
Deleted patch
1
In the tz-mpc device we allocate a data block for the LUT,
2
which we then clear to zero in the device's reset method.
3
This is conceptually fine, but unfortunately results in a
4
valgrind complaint about use of uninitialized data on startup:
5
1
6
==30906== Conditional jump or move depends on uninitialised value(s)
7
==30906== at 0x503609: tz_mpc_translate (tz-mpc.c:439)
8
==30906== by 0x3F3D90: address_space_translate_iommu (exec.c:511)
9
==30906== by 0x3F3FF8: flatview_do_translate (exec.c:584)
10
==30906== by 0x3F4292: flatview_translate (exec.c:644)
11
==30906== by 0x3F2120: address_space_translate (memory.h:1962)
12
==30906== by 0x3FB753: address_space_ldl_internal (memory_ldst.inc.c:36)
13
==30906== by 0x3FB8A6: address_space_ldl (memory_ldst.inc.c:80)
14
==30906== by 0x619037: ldl_phys (memory_ldst_phys.inc.h:25)
15
==30906== by 0x61985D: arm_cpu_reset (cpu.c:255)
16
==30906== by 0x98791B: cpu_reset (cpu.c:249)
17
==30906== by 0x57FFDB: armv7m_reset (armv7m.c:265)
18
==30906== by 0x7B1775: qemu_devices_reset (reset.c:69)
19
20
This is because of a reset ordering problem -- the TZ MPC
21
resets after the CPU, but an M-profile CPU's reset function
22
includes memory loads to get the initial PC and SP, which
23
then go through an MPC that hasn't yet been reset.
24
25
The simplest fix for this is to zero the LUT when we
26
initialize the data, which will result in the MPC's
27
translate function giving the right answers for these
28
early memory accesses.
29
30
Reported-by: Thomas Huth <thuth@redhat.com>
31
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Tested-by: Thomas Huth <thuth@redhat.com>
33
Message-id: 20180724153616.32352-1-peter.maydell@linaro.org
34
---
35
hw/misc/tz-mpc.c | 2 +-
36
1 file changed, 1 insertion(+), 1 deletion(-)
37
38
diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/misc/tz-mpc.c
41
+++ b/hw/misc/tz-mpc.c
42
@@ -XXX,XX +XXX,XX @@ static void tz_mpc_realize(DeviceState *dev, Error **errp)
43
address_space_init(&s->blocked_io_as, &s->blocked_io,
44
"tz-mpc-blocked-io");
45
46
- s->blk_lut = g_new(uint32_t, s->blk_max);
47
+ s->blk_lut = g_new0(uint32_t, s->blk_max);
48
}
49
50
static int tz_mpc_post_load(void *opaque, int version_id)
51
--
52
2.17.1
53
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 6/6] target/arm: Remove duplicate 'host' entry in '-cpu ?' output
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Since 86f0a186d6f the TYPE_ARM_HOST_CPU is only compiled when CONFIG_KVM
4
is enabled.
5
6
Remove the now redundant special-case introduced in a96c0514ab7, to avoid:
7
8
$ qemu-system-aarch64 -machine virt -cpu \? | fgrep host
9
host
10
host (only available in KVM mode)
11
12
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180727132311.2777-1-f4bug@amsat.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/helper.c | 6 ------
18
1 file changed, 6 deletions(-)
19
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper.c
23
+++ b/target/arm/helper.c
24
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
25
(*cpu_fprintf)(f, "Available CPUs:\n");
26
g_slist_foreach(list, arm_cpu_list_entry, &s);
27
g_slist_free(list);
28
-#ifdef CONFIG_KVM
29
- /* The 'host' CPU type is dynamically registered only if KVM is
30
- * enabled, so we have to special-case it here:
31
- */
32
- (*cpu_fprintf)(f, " host (only available in KVM mode)\n");
33
-#endif
34
}
35
36
static void arm_cpu_add_definition(gpointer data, gpointer user_data)
37
--
38
2.17.1
39
40
diff view generated by jsdifflib

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