[Qemu-devel] [PULL 0/5] target-arm queue
[PULL 0/9] target-arm queue
1
target-arm queue for 3.0:
1
This one's almost all docs fixes.
2
3
Thomas' fixes for instrospection issues with a handful of
4
devices (including one microblaze one that I include in this
5
pullreq for convenience's sake), plus my bugfix for a
6
corner case of small MPU region support.
7
2
8
thanks
3
thanks
9
-- PMM
4
-- PMM
10
5
11
The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e:
6
The following changes since commit ba54a7e6b86884e43bed2d2f5a79c719059652a8:
12
7
13
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100)
8
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-11-26 14:06:40 +0000)
14
9
15
are available in the Git repository at:
10
are available in the Git repository at:
16
11
17
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241126
18
13
19
for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87:
14
for you to fetch changes up to d8790ead55a2ef1e65332ebec63ae3c5db598942:
20
15
21
hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100)
16
docs/system/arm/aspeed: add missing model supermicrox11spi-bmc (2024-11-26 16:22:38 +0000)
22
17
23
----------------------------------------------------------------
18
----------------------------------------------------------------
24
target-arm queue:
19
target-arm queue:
25
* spitz, exynos: fix bugs when introspecting some devices
20
* target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
26
* hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
21
* docs/system/arm: Fix broken links and missing feature names
27
* target/arm: Correctly handle overlapping small MPU regions
28
* hw/sd/bcm2835_sdhost: Fix PIO mode writes
29
22
30
----------------------------------------------------------------
23
----------------------------------------------------------------
31
Guenter Roeck (1):
24
Michael Tokarev (1):
32
hw/sd/bcm2835_sdhost: Fix PIO mode writes
25
target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
33
26
34
Peter Maydell (1):
27
Pierrick Bouvier (8):
35
target/arm: Correctly handle overlapping small MPU regions
28
docs/system/arm/emulation: mention armv9
29
docs/system/arm/emulation: fix typo in feature name
30
docs/system/arm/emulation: add FEAT_SSBS2
31
target/arm/tcg/: fix typo in FEAT name
32
docs/system/arm/: add FEAT_MTE_ASYNC
33
docs/system/arm/: add FEAT_DoubleLock
34
docs/system/arm/fby35: update link to product page
35
docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
36
36
37
Thomas Huth (3):
37
docs/system/arm/aspeed.rst | 7 ++++---
38
hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
38
docs/system/arm/emulation.rst | 11 +++++++----
39
hw/arm/spitz: Move problematic nand_init() code to realize function
39
docs/system/arm/fby35.rst | 2 +-
40
hw/intc/exynos4210_gic: Turn instance_init into realize function
40
target/arm/tcg/cpu32.c | 6 +++---
41
41
4 files changed, 15 insertions(+), 11 deletions(-)
42
hw/arm/spitz.c | 15 ++++++++++----
43
hw/intc/exynos4210_gic.c | 6 +++---
44
hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++-----
45
hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++----
46
target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++
47
5 files changed, 80 insertions(+), 17 deletions(-)
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/5] hw/arm/spitz: Move problematic nand_init() code to realize function
[PULL 1/9] target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
1
From: Thomas Huth <thuth@redhat.com>
1
From: Michael Tokarev <mjt@tls.msk.ru>
2
2
3
nand_init() does not only create the NAND device, it also realizes
3
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
4
the device with qdev_init_nofail() already. So we must not call
4
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
5
nand_init() from an instance_init function like sl_nand_init(),
5
qemu labels them. Just swap the labels to avoid confusion, -
6
otherwise we get superfluous NAND devices in the QOM tree after
6
both registers are implemented as always-zero.
7
introspecting the 'sl-nand' device. So move the nand_init() to the
8
realize function of 'sl-nand' instead.
9
7
10
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 1532006134-7701-1-git-send-email-thuth@redhat.com
10
Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
12
---
16
hw/arm/spitz.c | 15 +++++++++++----
13
target/arm/tcg/cpu32.c | 4 ++--
17
1 file changed, 11 insertions(+), 4 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
18
15
19
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
16
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
20
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/spitz.c
18
--- a/target/arm/tcg/cpu32.c
22
+++ b/hw/arm/spitz.c
19
+++ b/target/arm/tcg/cpu32.c
23
@@ -XXX,XX +XXX,XX @@ static void sl_nand_init(Object *obj)
20
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
24
{
21
25
SLNANDState *s = SL_NAND(obj);
22
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
26
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
23
/* Dummy the TCM region regs for the moment */
27
- DriveInfo *nand;
24
- { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
28
25
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
29
s->ctl = 0;
26
.access = PL1_RW, .type = ARM_CP_CONST },
30
+
27
- { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
31
+ memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40);
28
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
32
+ sysbus_init_mmio(dev, &s->iomem);
29
.access = PL1_RW, .type = ARM_CP_CONST },
33
+}
30
{ .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
34
+
31
.opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
35
+static void sl_nand_realize(DeviceState *dev, Error **errp)
36
+{
37
+ SLNANDState *s = SL_NAND(dev);
38
+ DriveInfo *nand;
39
+
40
/* FIXME use a qdev drive property instead of drive_get() */
41
nand = drive_get(IF_MTD, 0, 0);
42
s->nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
43
s->manf_id, s->chip_id);
44
-
45
- memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40);
46
- sysbus_init_mmio(dev, &s->iomem);
47
}
48
49
/* Spitz Keyboard */
50
@@ -XXX,XX +XXX,XX @@ static void sl_nand_class_init(ObjectClass *klass, void *data)
51
52
dc->vmsd = &vmstate_sl_nand_info;
53
dc->props = sl_nand_properties;
54
+ dc->realize = sl_nand_realize;
55
/* Reason: init() method uses drive_get() */
56
dc->user_creatable = false;
57
}
58
--
32
--
59
2.17.1
33
2.34.1
60
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/5] hw/intc/exynos4210_gic: Turn instance_init into realize function
[PULL 2/9] docs/system/arm/emulation: mention armv9
1
From: Thomas Huth <thuth@redhat.com>
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
2
3
The instance_init function of the "exynos4210.gic" device creates a
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
new "arm_gic" device and immediately realizes it with qdev_init_nofail().
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
This will leave a lot of object in the QOM tree during introspection of
5
Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org
6
the "exynos4210.gic" device, e.g. reproducible by starting QEMU like this:
7
8
qemu-system-aarch64 -M none -nodefaults -nographic -monitor stdio
9
10
And then by running "info qom-tree" at the HMP monitor, followed by
11
"device_add exynos4210.gic,help" and finally checking "info qom-tree"
12
again.
13
14
Also note that qdev_init_nofail() can exit QEMU in case of errors - and
15
this must never happen during an instance_init function, otherwise QEMU
16
could terminate unexpectedly during introspection of a device.
17
18
Since most of the code that follows the qdev_init_nofail() depends on
19
the realized "gicbusdev", the easiest solution to the problem is to
20
turn the whole instance_init function into a realize function instead.
21
22
Signed-off-by: Thomas Huth <thuth@redhat.com>
23
Message-id: 1532337784-334-1-git-send-email-thuth@redhat.com
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
7
---
27
hw/intc/exynos4210_gic.c | 6 +++---
8
docs/system/arm/emulation.rst | 6 +++---
28
1 file changed, 3 insertions(+), 3 deletions(-)
9
1 file changed, 3 insertions(+), 3 deletions(-)
29
10
30
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
11
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
31
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/exynos4210_gic.c
13
--- a/docs/system/arm/emulation.rst
33
+++ b/hw/intc/exynos4210_gic.c
14
+++ b/docs/system/arm/emulation.rst
34
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
15
@@ -XXX,XX +XXX,XX @@
35
qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level);
16
A-profile CPU architecture support
36
}
17
==================================
37
18
38
-static void exynos4210_gic_init(Object *obj)
19
-QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and
39
+static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
20
-Armv8 versions of the A-profile architecture. It also has support for
40
{
21
+QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7,
41
- DeviceState *dev = DEVICE(obj);
22
+Armv8 and Armv9 versions of the A-profile architecture. It also has support for
42
+ Object *obj = OBJECT(dev);
23
the following architecture extensions:
43
Exynos4210GicState *s = EXYNOS4210_GIC(obj);
24
44
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
25
- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
45
const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
26
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
46
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_class_init(ObjectClass *klass, void *data)
27
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
47
DeviceClass *dc = DEVICE_CLASS(klass);
28
48
29
For information on the specifics of these extensions, please refer
49
dc->props = exynos4210_gic_properties;
30
-to the `Armv8-A Arm Architecture Reference Manual
50
+ dc->realize = exynos4210_gic_realize;
31
+to the `Arm Architecture Reference Manual for A-profile architecture
51
}
32
<https://developer.arm.com/documentation/ddi0487/latest>`_.
52
33
53
static const TypeInfo exynos4210_gic_info = {
34
When a specific named CPU is being emulated, only those features which
54
.name = TYPE_EXYNOS4210_GIC,
55
.parent = TYPE_SYS_BUS_DEVICE,
56
.instance_size = sizeof(Exynos4210GicState),
57
- .instance_init = exynos4210_gic_init,
58
.class_init = exynos4210_gic_class_init,
59
};
60
61
--
35
--
62
2.17.1
36
2.34.1
63
64
diff view generated by jsdifflib
New patch
[PULL 3/9] docs/system/arm/emulation: fix typo in feature name
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
docs/system/arm/emulation.rst | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
12
index XXXXXXX..XXXXXXX 100644
13
--- a/docs/system/arm/emulation.rst
14
+++ b/docs/system/arm/emulation.rst
15
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
16
- FEAT_LSE2 (Large System Extensions v2)
17
- FEAT_LVA (Large Virtual Address space)
18
- FEAT_MixedEnd (Mixed-endian support)
19
-- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
20
+- FEAT_MixedEndEL0 (Mixed-endian support at EL0)
21
- FEAT_MOPS (Standardization of memory operations)
22
- FEAT_MTE (Memory Tagging Extension)
23
- FEAT_MTE2 (Memory Tagging Extension)
24
--
25
2.34.1
diff view generated by jsdifflib
New patch
[PULL 4/9] docs/system/arm/emulation: add FEAT_SSBS2
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
We implemented this at the same times as FEAT_SSBS, but forgot
4
to list it in the documentation.
5
6
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
[PMM: improve commit message]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
docs/system/arm/emulation.rst | 1 +
14
1 file changed, 1 insertion(+)
15
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
18
--- a/docs/system/arm/emulation.rst
19
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
- FEAT_SVE2 (Scalable Vector Extension version 2)
22
- FEAT_SPECRES (Speculation restriction instructions)
23
- FEAT_SSBS (Speculative Store Bypass Safe)
24
+- FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2)
25
- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
26
- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
27
- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
28
--
29
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/5] target/arm: Correctly handle overlapping small MPU regions
[PULL 5/9] target/arm/tcg/: fix typo in FEAT name
1
To correctly handle small (less than TARGET_PAGE_SIZE) MPU regions,
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
we must correctly handle the case where the address being looked
3
up hits in an MPU region that is not small but the address is
4
in the same page as a small region. For instance if MPU region
5
1 covers an entire page from 0x2000 to 0x2400 and MPU region
6
2 is small and covers only 0x2200 to 0x2280, then for an access
7
to 0x2000 we must not return a result covering the full page
8
even though we hit the page-sized region 1. Otherwise we will
9
then cache that result in the TLB and accesses that should
10
hit region 2 will incorrectly find the region 1 information.
11
2
12
Check for the case where we miss an MPU region but it is still
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
13
within the same page, and in that case narrow the size we will
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
pass to tlb_set_page_with_attrs() for whatever the final
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
outcome is of the MPU lookup.
6
Message-id: 20241122225049.1617774-5-pierrick.bouvier@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/tcg/cpu32.c | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
16
11
17
Reported-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
12
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20180716133302.25989-1-peter.maydell@linaro.org
21
---
22
target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++++++
23
1 file changed, 46 insertions(+)
24
25
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper.c
14
--- a/target/arm/tcg/cpu32.c
28
+++ b/target/arm/helper.c
15
+++ b/target/arm/tcg/cpu32.c
29
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
30
#include "exec/semihost.h"
17
cpu->isar.id_mmfr5 = t;
31
#include "sysemu/kvm.h"
18
32
#include "fpu/softfloat.h"
19
t = cpu->isar.id_pfr0;
33
+#include "qemu/range.h"
20
- t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
34
21
+ t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
35
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
22
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
36
23
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
37
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
24
cpu->isar.id_pfr0 = t;
38
}
39
40
if (address < base || address > base + rmask) {
41
+ /*
42
+ * Address not in this region. We must check whether the
43
+ * region covers addresses in the same page as our address.
44
+ * In that case we must not report a size that covers the
45
+ * whole page for a subsequent hit against a different MPU
46
+ * region or the background region, because it would result in
47
+ * incorrect TLB hits for subsequent accesses to addresses that
48
+ * are in this MPU region.
49
+ */
50
+ if (ranges_overlap(base, rmask,
51
+ address & TARGET_PAGE_MASK,
52
+ TARGET_PAGE_SIZE)) {
53
+ *page_size = 1;
54
+ }
55
continue;
56
}
57
58
@@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address,
59
sattrs->srvalid = true;
60
sattrs->sregion = r;
61
}
62
+ } else {
63
+ /*
64
+ * Address not in this region. We must check whether the
65
+ * region covers addresses in the same page as our address.
66
+ * In that case we must not report a size that covers the
67
+ * whole page for a subsequent hit against a different MPU
68
+ * region or the background region, because it would result
69
+ * in incorrect TLB hits for subsequent accesses to
70
+ * addresses that are in this MPU region.
71
+ */
72
+ if (limit >= base &&
73
+ ranges_overlap(base, limit - base + 1,
74
+ addr_page_base,
75
+ TARGET_PAGE_SIZE)) {
76
+ sattrs->subpage = true;
77
+ }
78
}
79
}
80
}
81
@@ -XXX,XX +XXX,XX @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
82
}
83
84
if (address < base || address > limit) {
85
+ /*
86
+ * Address not in this region. We must check whether the
87
+ * region covers addresses in the same page as our address.
88
+ * In that case we must not report a size that covers the
89
+ * whole page for a subsequent hit against a different MPU
90
+ * region or the background region, because it would result in
91
+ * incorrect TLB hits for subsequent accesses to addresses that
92
+ * are in this MPU region.
93
+ */
94
+ if (limit >= base &&
95
+ ranges_overlap(base, limit - base + 1,
96
+ addr_page_base,
97
+ TARGET_PAGE_SIZE)) {
98
+ *is_subpage = true;
99
+ }
100
continue;
101
}
102
103
--
25
--
104
2.17.1
26
2.34.1
105
27
106
28
diff view generated by jsdifflib
New patch
[PULL 6/9] docs/system/arm/: add FEAT_MTE_ASYNC
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
We already implement FEAT_MTE_ASYNC; we just forgot to list it
4
in the documentation.
5
6
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org
9
[PMM: expand commit message]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
docs/system/arm/emulation.rst | 1 +
13
1 file changed, 1 insertion(+)
14
15
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
17
--- a/docs/system/arm/emulation.rst
18
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
- FEAT_MTE2 (Memory Tagging Extension)
21
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
22
- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
23
+- FEAT_MTE_ASYNC (Asynchronous reporting of Tag Check Fault)
24
- FEAT_NMI (Non-maskable Interrupt)
25
- FEAT_NV (Nested Virtualization)
26
- FEAT_NV2 (Enhanced nested virtualization support)
27
--
28
2.34.1
diff view generated by jsdifflib
New patch
[PULL 7/9] docs/system/arm/: add FEAT_DoubleLock
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
1
2
3
We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when
4
the ID registers call for it. This feature is actually one that must
5
*not* be implemented in v9.0, but since our documentation lists
6
everything we can emulate, we should include FEAT_DoubleLock in the
7
list.
8
9
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
10
Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: expand commit message]
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
docs/system/arm/emulation.rst | 1 +
16
1 file changed, 1 insertion(+)
17
18
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
19
index XXXXXXX..XXXXXXX 100644
20
--- a/docs/system/arm/emulation.rst
21
+++ b/docs/system/arm/emulation.rst
22
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
23
- FEAT_CSV3 (Cache speculation variant 3)
24
- FEAT_DGH (Data gathering hint)
25
- FEAT_DIT (Data Independent Timing instructions)
26
+- FEAT_DoubleLock (Double Lock)
27
- FEAT_DPB (DC CVAP instruction)
28
- FEAT_DPB2 (DC CVADP instruction)
29
- FEAT_Debugv8p1 (Debug with VHE)
30
--
31
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/5] hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc'
[PULL 8/9] docs/system/arm/fby35: update link to product page
1
From: Thomas Huth <thuth@redhat.com>
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
2
3
Valgrind complains:
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
"'arguments':{'typename':'xlnx,zynqmp-pmu-soc'}}" \
6
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
"{'execute': 'human-monitor-command', " \
7
Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org
8
"'arguments': {'command-line': 'info qtree'}}" | \
9
valgrind -q microblazeel-softmmu/qemu-system-microblazeel -M none,accel=qtest -qmp stdio
10
[...]
11
==13605== Invalid read of size 8
12
==13605== at 0x2AC69A: qdev_print (qdev-monitor.c:686)
13
==13605== by 0x2AC69A: qbus_print (qdev-monitor.c:719)
14
==13605== by 0x2591E8: handle_hmp_command (monitor.c:3446)
15
16
Use the new object_initialize_child() and sysbus_init_child_obj() to
17
fix the issue.
18
19
Signed-off-by: Thomas Huth <thuth@redhat.com>
20
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
21
Message-id: 1531839343-13828-1-git-send-email-thuth@redhat.com
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
9
---
24
hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++------
10
docs/system/arm/fby35.rst | 2 +-
25
1 file changed, 4 insertions(+), 6 deletions(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
26
12
27
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
13
diff --git a/docs/system/arm/fby35.rst b/docs/system/arm/fby35.rst
28
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
15
--- a/docs/system/arm/fby35.rst
30
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
16
+++ b/docs/system/arm/fby35.rst
31
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_pmu_soc_init(Object *obj)
17
@@ -XXX,XX +XXX,XX @@ include various compute accelerators (video, inferencing, etc). At the moment,
32
{
18
only the first server slot's BIC is included.
33
XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj);
19
34
20
Yosemite v3.5 is itself a sled which fits into a 40U chassis, and 3 sleds
35
- object_initialize(&s->cpu, sizeof(s->cpu),
21
-can be fit into a chassis. See `here <https://www.opencompute.org/products/423/wiwynn-yosemite-v3-server>`__
36
- TYPE_MICROBLAZE_CPU);
22
+can be fit into a chassis. See `here <https://www.opencompute.org/products-chiplets/237/wiwynn-yosemite-v3-server>`__
37
- object_property_add_child(obj, "pmu-cpu", OBJECT(&s->cpu),
23
for an example.
38
- &error_abort);
24
39
+ object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu),
25
In this generation, the BMC is an AST2600 and each BIC is an AST1030. The BMC
40
+ TYPE_MICROBLAZE_CPU, &error_abort, NULL);
41
42
- object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC);
43
- qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default());
44
+ sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
45
+ TYPE_XLNX_PMU_IO_INTC);
46
}
47
48
static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp)
49
--
26
--
50
2.17.1
27
2.34.1
51
28
52
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/5] hw/sd/bcm2835_sdhost: Fix PIO mode writes
[PULL 9/9] docs/system/arm/aspeed: add missing model supermicrox11spi-bmc
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
2
2
3
Writes in PIO mode have two requirements:
3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
4
4
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
5
- A data interrupt must be generated after a write command has been
5
Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org
6
issued to indicate that the chip is ready to receive data.
7
- A block interrupt must be generated after each block to indicate
8
that the chip is ready to receive the next data block.
9
10
Rearrange the code to make this happen. Tested on raspi3 (in PIO mode)
11
and raspi2 (in DMA mode).
12
13
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
14
Message-id: 1531779837-20557-1-git-send-email-linux@roeck-us.net
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
7
---
18
hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++++----
8
docs/system/arm/aspeed.rst | 7 ++++---
19
1 file changed, 16 insertions(+), 4 deletions(-)
9
1 file changed, 4 insertions(+), 3 deletions(-)
20
10
21
diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
11
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
22
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/sd/bcm2835_sdhost.c
13
--- a/docs/system/arm/aspeed.rst
24
+++ b/hw/sd/bcm2835_sdhost.c
14
+++ b/docs/system/arm/aspeed.rst
25
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
15
@@ -XXX,XX +XXX,XX @@
26
uint32_t value = 0;
16
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
27
int n;
17
-========================================================================================================================================================================================================================================================================================================================================================================================================
28
int is_read;
18
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``tacoma-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
29
+ int is_write;
19
+==================================================================================================================================================================================================================================================================================================================================================================================================================================
30
20
31
is_read = (s->cmd & SDCMD_READ_CMD) != 0;
21
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
32
- if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))) {
22
Aspeed evaluation boards. They are based on different releases of the
33
+ is_write = (s->cmd & SDCMD_WRITE_CMD) != 0;
23
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
34
+ if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) {
24
35
if (is_read) {
25
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
36
n = 0;
26
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
37
while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) {
27
-- ``supermicrox11-bmc`` Supermicro X11 BMC
38
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
28
+- ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
39
if (n != 0) {
29
+- ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
40
bcm2835_sdhost_fifo_push(s, value);
30
41
s->status |= SDHSTS_DATA_FLAG;
31
AST2500 SoC based machines :
42
+ if (s->config & SDHCFG_DATA_IRPT_EN) {
43
+ s->status |= SDHSTS_SDIO_IRPT;
44
+ }
45
}
46
- } else { /* write */
47
+ } else if (is_write) { /* write */
48
n = 0;
49
while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
50
if (n == 0) {
51
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
52
s->edm &= ~SDEDM_FSM_MASK;
53
s->edm |= SDEDM_FSM_DATAMODE;
54
trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
55
-
56
- if ((s->cmd & SDCMD_WRITE_CMD) &&
57
+ }
58
+ if (is_write) {
59
+ /* set block interrupt at end of each block transfer */
60
+ if (s->hbct && s->datacnt % s->hbct == 0 &&
61
(s->config & SDHCFG_BLOCK_IRPT_EN)) {
62
s->status |= SDHSTS_BLOCK_IRPT;
63
}
64
+ /* set data interrupt after each transfer */
65
+ s->status |= SDHSTS_DATA_FLAG;
66
+ if (s->config & SDHCFG_DATA_IRPT_EN) {
67
+ s->status |= SDHSTS_SDIO_IRPT;
68
+ }
69
}
70
}
71
32
72
--
33
--
73
2.17.1
34
2.34.1
74
75
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.