1 | target-arm queue for 3.0: | 1 | Patches for rc1: nothing major, just some minor bugfixes and |
---|---|---|---|
2 | code cleanups. | ||
2 | 3 | ||
3 | Thomas' fixes for instrospection issues with a handful of | ||
4 | devices (including one microblaze one that I include in this | ||
5 | pullreq for convenience's sake), plus my bugfix for a | ||
6 | corner case of small MPU region support. | ||
7 | |||
8 | thanks | ||
9 | -- PMM | 4 | -- PMM |
10 | 5 | ||
11 | The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e: | 6 | The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f: |
12 | 7 | ||
13 | Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100) | 8 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000) |
14 | 9 | ||
15 | are available in the Git repository at: | 10 | are available in the Git repository at: |
16 | 11 | ||
17 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110 |
18 | 13 | ||
19 | for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87: | 14 | for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa: |
20 | 15 | ||
21 | hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100) | 16 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000) |
22 | 17 | ||
23 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
24 | target-arm queue: | 19 | target-arm queue: |
25 | * spitz, exynos: fix bugs when introspecting some devices | 20 | * hw/arm/Kconfig: ARM_V7M depends on PTIMER |
26 | * hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc' | 21 | * Minor coding style fixes |
27 | * target/arm: Correctly handle overlapping small MPU regions | 22 | * docs: add some notes on the sbsa-ref machine |
28 | * hw/sd/bcm2835_sdhost: Fix PIO mode writes | 23 | * hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals |
24 | * target/arm: Fix neon VTBL/VTBX for len > 1 | ||
25 | * hw/arm/armsse: Correct expansion MPC interrupt lines | ||
26 | * hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | ||
27 | * hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
28 | * hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
29 | * hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
30 | * hw/arm/nseries: Check return value from load_image_targphys() | ||
31 | * tests/qtest/npcm7xx_rng-test: count runs properly | ||
32 | * target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
29 | 33 | ||
30 | ---------------------------------------------------------------- | 34 | ---------------------------------------------------------------- |
31 | Guenter Roeck (1): | 35 | Alex Bennée (1): |
32 | hw/sd/bcm2835_sdhost: Fix PIO mode writes | 36 | docs: add some notes on the sbsa-ref machine |
33 | 37 | ||
34 | Peter Maydell (1): | 38 | AlexChen (1): |
35 | target/arm: Correctly handle overlapping small MPU regions | 39 | ssi: Fix bad printf format specifiers |
36 | 40 | ||
37 | Thomas Huth (3): | 41 | Andrew Jones (1): |
38 | hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc' | 42 | hw/arm/Kconfig: ARM_V7M depends on PTIMER |
39 | hw/arm/spitz: Move problematic nand_init() code to realize function | ||
40 | hw/intc/exynos4210_gic: Turn instance_init into realize function | ||
41 | 43 | ||
42 | hw/arm/spitz.c | 15 ++++++++++---- | 44 | Havard Skinnemoen (1): |
43 | hw/intc/exynos4210_gic.c | 6 +++--- | 45 | tests/qtest/npcm7xx_rng-test: count runs properly |
44 | hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++----- | ||
45 | hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++---- | ||
46 | target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++ | ||
47 | 5 files changed, 80 insertions(+), 17 deletions(-) | ||
48 | 46 | ||
47 | Peter Maydell (2): | ||
48 | hw/arm/nseries: Check return value from load_image_targphys() | ||
49 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
50 | |||
51 | Philippe Mathieu-Daudé (6): | ||
52 | hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | ||
53 | hw/arm/armsse: Correct expansion MPC interrupt lines | ||
54 | hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | ||
55 | hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
56 | hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
57 | hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
58 | |||
59 | Richard Henderson (1): | ||
60 | target/arm: Fix neon VTBL/VTBX for len > 1 | ||
61 | |||
62 | Xinhao Zhang (3): | ||
63 | target/arm: add spaces around operator | ||
64 | target/arm: Don't use '#' flag of printf format | ||
65 | target/arm: add space before the open parenthesis '(' | ||
66 | |||
67 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++ | ||
68 | docs/system/target-arm.rst | 1 + | ||
69 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
70 | target/arm/helper.h | 2 +- | ||
71 | hw/arm/armsse.c | 3 +- | ||
72 | hw/arm/musicpal.c | 40 +++++++++++++++++---------- | ||
73 | hw/arm/nseries.c | 26 ++++++++---------- | ||
74 | hw/arm/stm32f205_soc.c | 1 - | ||
75 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
76 | hw/ssi/imx_spi.c | 2 +- | ||
77 | hw/ssi/xilinx_spi.c | 2 +- | ||
78 | target/arm/arch_dump.c | 8 +++--- | ||
79 | target/arm/arm-semi.c | 8 +++--- | ||
80 | target/arm/helper.c | 2 +- | ||
81 | target/arm/op_helper.c | 23 +++++++++------- | ||
82 | target/arm/translate-a64.c | 4 +-- | ||
83 | target/arm/translate.c | 2 +- | ||
84 | tests/qtest/npcm7xx_rng-test.c | 2 +- | ||
85 | hw/arm/Kconfig | 3 +- | ||
86 | target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------ | ||
87 | 20 files changed, 123 insertions(+), 98 deletions(-) | ||
88 | create mode 100644 docs/system/arm/sbsa.rst | ||
89 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
1 | 2 | ||
3 | commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers") | ||
4 | changed armv7m_systick to build on ptimers. Make sure we have ptimers | ||
5 | in the build when building armv7m_systick. | ||
6 | |||
7 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20201104103343.30392-1-drjones@redhat.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/Kconfig | 1 + | ||
13 | 1 file changed, 1 insertion(+) | ||
14 | |||
15 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/Kconfig | ||
18 | +++ b/hw/arm/Kconfig | ||
19 | @@ -XXX,XX +XXX,XX @@ config ZYNQ | ||
20 | |||
21 | config ARM_V7M | ||
22 | bool | ||
23 | + select PTIMER | ||
24 | |||
25 | config ALLWINNER_A10 | ||
26 | bool | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: AlexChen <alex.chen@huawei.com> | ||
1 | 2 | ||
3 | We should use printf format specifier "%u" instead of "%d" for | ||
4 | argument of type "unsigned int". | ||
5 | |||
6 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | ||
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Message-id: 5FA280F5.8060902@huawei.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/ssi/imx_spi.c | 2 +- | ||
13 | hw/ssi/xilinx_spi.c | 2 +- | ||
14 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
15 | |||
16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/ssi/imx_spi.c | ||
19 | +++ b/hw/ssi/imx_spi.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg) | ||
21 | case ECSPI_MSGDATA: | ||
22 | return "ECSPI_MSGDATA"; | ||
23 | default: | ||
24 | - sprintf(unknown, "%d ?", reg); | ||
25 | + sprintf(unknown, "%u ?", reg); | ||
26 | return unknown; | ||
27 | } | ||
28 | } | ||
29 | diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/ssi/xilinx_spi.c | ||
32 | +++ b/hw/ssi/xilinx_spi.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s) | ||
34 | irq chain unless things really changed. */ | ||
35 | if (pending != s->irqline) { | ||
36 | s->irqline = pending; | ||
37 | - DB_PRINT("irq_change of state %d ISR:%x IER:%X\n", | ||
38 | + DB_PRINT("irq_change of state %u ISR:%x IER:%X\n", | ||
39 | pending, s->regs[R_IPISR], s->regs[R_IPIER]); | ||
40 | qemu_set_irq(s->irq, pending); | ||
41 | } | ||
42 | -- | ||
43 | 2.20.1 | ||
44 | |||
45 | diff view generated by jsdifflib |
1 | To correctly handle small (less than TARGET_PAGE_SIZE) MPU regions, | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
---|---|---|---|
2 | we must correctly handle the case where the address being looked | ||
3 | up hits in an MPU region that is not small but the address is | ||
4 | in the same page as a small region. For instance if MPU region | ||
5 | 1 covers an entire page from 0x2000 to 0x2400 and MPU region | ||
6 | 2 is small and covers only 0x2200 to 0x2280, then for an access | ||
7 | to 0x2000 we must not return a result covering the full page | ||
8 | even though we hit the page-sized region 1. Otherwise we will | ||
9 | then cache that result in the TLB and accesses that should | ||
10 | hit region 2 will incorrectly find the region 1 information. | ||
11 | 2 | ||
12 | Check for the case where we miss an MPU region but it is still | 3 | Fix code style. Operator needs spaces both sides. |
13 | within the same page, and in that case narrow the size we will | ||
14 | pass to tlb_set_page_with_attrs() for whatever the final | ||
15 | outcome is of the MPU lookup. | ||
16 | 4 | ||
17 | Reported-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com> | 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
7 | Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20180716133302.25989-1-peter.maydell@linaro.org | ||
21 | --- | 10 | --- |
22 | target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++++++ | 11 | target/arm/arch_dump.c | 8 ++++---- |
23 | 1 file changed, 46 insertions(+) | 12 | target/arm/arm-semi.c | 8 ++++---- |
13 | target/arm/helper.c | 2 +- | ||
14 | 3 files changed, 9 insertions(+), 9 deletions(-) | ||
24 | 15 | ||
16 | diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/arch_dump.c | ||
19 | +++ b/target/arm/arch_dump.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | ||
21 | |||
22 | for (i = 0; i < 32; ++i) { | ||
23 | uint64_t *q = aa64_vfp_qreg(env, i); | ||
24 | - note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]); | ||
25 | - note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]); | ||
26 | + note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]); | ||
27 | + note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]); | ||
28 | } | ||
29 | |||
30 | if (s->dump_info.d_endian == ELFDATA2MSB) { | ||
31 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | ||
32 | */ | ||
33 | for (i = 0; i < 32; ++i) { | ||
34 | uint64_t tmp = note.vfp.vregs[2*i]; | ||
35 | - note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1]; | ||
36 | - note.vfp.vregs[2*i+1] = tmp; | ||
37 | + note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1]; | ||
38 | + note.vfp.vregs[2 * i + 1] = tmp; | ||
39 | } | ||
40 | } | ||
41 | |||
42 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/arm-semi.c | ||
45 | +++ b/target/arm/arm-semi.c | ||
46 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
47 | if (use_gdb_syscalls()) { | ||
48 | arm_semi_open_guestfd = guestfd; | ||
49 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
50 | - (int)arg2+1, gdb_open_modeflags[arg1]); | ||
51 | + (int)arg2 + 1, gdb_open_modeflags[arg1]); | ||
52 | } else { | ||
53 | ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); | ||
54 | if (ret == (uint32_t)-1) { | ||
55 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
56 | GET_ARG(1); | ||
57 | if (use_gdb_syscalls()) { | ||
58 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", | ||
59 | - arg0, (int)arg1+1); | ||
60 | + arg0, (int)arg1 + 1); | ||
61 | } else { | ||
62 | s = lock_user_string(arg0); | ||
63 | if (!s) { | ||
64 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
65 | GET_ARG(3); | ||
66 | if (use_gdb_syscalls()) { | ||
67 | return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", | ||
68 | - arg0, (int)arg1+1, arg2, (int)arg3+1); | ||
69 | + arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); | ||
70 | } else { | ||
71 | char *s2; | ||
72 | s = lock_user_string(arg0); | ||
73 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
74 | GET_ARG(1); | ||
75 | if (use_gdb_syscalls()) { | ||
76 | return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", | ||
77 | - arg0, (int)arg1+1); | ||
78 | + arg0, (int)arg1 + 1); | ||
79 | } else { | ||
80 | s = lock_user_string(arg0); | ||
81 | if (!s) { | ||
25 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 82 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
26 | index XXXXXXX..XXXXXXX 100644 | 83 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/helper.c | 84 | --- a/target/arm/helper.c |
28 | +++ b/target/arm/helper.c | 85 | +++ b/target/arm/helper.c |
29 | @@ -XXX,XX +XXX,XX @@ | 86 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b) |
30 | #include "exec/semihost.h" | 87 | uint32_t sum; |
31 | #include "sysemu/kvm.h" | 88 | sum = do_usad(a, b); |
32 | #include "fpu/softfloat.h" | 89 | sum += do_usad(a >> 8, b >> 8); |
33 | +#include "qemu/range.h" | 90 | - sum += do_usad(a >> 16, b >>16); |
34 | 91 | + sum += do_usad(a >> 16, b >> 16); | |
35 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ | 92 | sum += do_usad(a >> 24, b >> 24); |
36 | 93 | return sum; | |
37 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | 94 | } |
38 | } | ||
39 | |||
40 | if (address < base || address > base + rmask) { | ||
41 | + /* | ||
42 | + * Address not in this region. We must check whether the | ||
43 | + * region covers addresses in the same page as our address. | ||
44 | + * In that case we must not report a size that covers the | ||
45 | + * whole page for a subsequent hit against a different MPU | ||
46 | + * region or the background region, because it would result in | ||
47 | + * incorrect TLB hits for subsequent accesses to addresses that | ||
48 | + * are in this MPU region. | ||
49 | + */ | ||
50 | + if (ranges_overlap(base, rmask, | ||
51 | + address & TARGET_PAGE_MASK, | ||
52 | + TARGET_PAGE_SIZE)) { | ||
53 | + *page_size = 1; | ||
54 | + } | ||
55 | continue; | ||
56 | } | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | ||
59 | sattrs->srvalid = true; | ||
60 | sattrs->sregion = r; | ||
61 | } | ||
62 | + } else { | ||
63 | + /* | ||
64 | + * Address not in this region. We must check whether the | ||
65 | + * region covers addresses in the same page as our address. | ||
66 | + * In that case we must not report a size that covers the | ||
67 | + * whole page for a subsequent hit against a different MPU | ||
68 | + * region or the background region, because it would result | ||
69 | + * in incorrect TLB hits for subsequent accesses to | ||
70 | + * addresses that are in this MPU region. | ||
71 | + */ | ||
72 | + if (limit >= base && | ||
73 | + ranges_overlap(base, limit - base + 1, | ||
74 | + addr_page_base, | ||
75 | + TARGET_PAGE_SIZE)) { | ||
76 | + sattrs->subpage = true; | ||
77 | + } | ||
78 | } | ||
79 | } | ||
80 | } | ||
81 | @@ -XXX,XX +XXX,XX @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, | ||
82 | } | ||
83 | |||
84 | if (address < base || address > limit) { | ||
85 | + /* | ||
86 | + * Address not in this region. We must check whether the | ||
87 | + * region covers addresses in the same page as our address. | ||
88 | + * In that case we must not report a size that covers the | ||
89 | + * whole page for a subsequent hit against a different MPU | ||
90 | + * region or the background region, because it would result in | ||
91 | + * incorrect TLB hits for subsequent accesses to addresses that | ||
92 | + * are in this MPU region. | ||
93 | + */ | ||
94 | + if (limit >= base && | ||
95 | + ranges_overlap(base, limit - base + 1, | ||
96 | + addr_page_base, | ||
97 | + TARGET_PAGE_SIZE)) { | ||
98 | + *is_subpage = true; | ||
99 | + } | ||
100 | continue; | ||
101 | } | ||
102 | |||
103 | -- | 95 | -- |
104 | 2.17.1 | 96 | 2.20.1 |
105 | 97 | ||
106 | 98 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> |
---|---|---|---|
2 | 2 | ||
3 | Writes in PIO mode have two requirements: | 3 | Fix code style. Don't use '#' flag of printf format ('%#') in |
4 | format strings, use '0x' prefix instead | ||
4 | 5 | ||
5 | - A data interrupt must be generated after a write command has been | 6 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> |
6 | issued to indicate that the chip is ready to receive data. | 7 | Signed-off-by: Kai Deng <dengkai1@huawei.com> |
7 | - A block interrupt must be generated after each block to indicate | 8 | Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com |
8 | that the chip is ready to receive the next data block. | ||
9 | |||
10 | Rearrange the code to make this happen. Tested on raspi3 (in PIO mode) | ||
11 | and raspi2 (in DMA mode). | ||
12 | |||
13 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
14 | Message-id: 1531779837-20557-1-git-send-email-linux@roeck-us.net | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 11 | --- |
18 | hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++++---- | 12 | target/arm/translate-a64.c | 4 ++-- |
19 | 1 file changed, 16 insertions(+), 4 deletions(-) | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
20 | 14 | ||
21 | diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c | 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/sd/bcm2835_sdhost.c | 17 | --- a/target/arm/translate-a64.c |
24 | +++ b/hw/sd/bcm2835_sdhost.c | 18 | +++ b/target/arm/translate-a64.c |
25 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) | 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) |
26 | uint32_t value = 0; | 20 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); |
27 | int n; | 21 | break; |
28 | int is_read; | 22 | default: |
29 | + int is_write; | 23 | - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", |
30 | 24 | + fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", | |
31 | is_read = (s->cmd & SDCMD_READ_CMD) != 0; | 25 | __func__, insn, fpopcode, s->pc_curr); |
32 | - if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))) { | 26 | g_assert_not_reached(); |
33 | + is_write = (s->cmd & SDCMD_WRITE_CMD) != 0; | ||
34 | + if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) { | ||
35 | if (is_read) { | ||
36 | n = 0; | ||
37 | while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) { | ||
38 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) | ||
39 | if (n != 0) { | ||
40 | bcm2835_sdhost_fifo_push(s, value); | ||
41 | s->status |= SDHSTS_DATA_FLAG; | ||
42 | + if (s->config & SDHCFG_DATA_IRPT_EN) { | ||
43 | + s->status |= SDHSTS_SDIO_IRPT; | ||
44 | + } | ||
45 | } | 27 | } |
46 | - } else { /* write */ | 28 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) |
47 | + } else if (is_write) { /* write */ | 29 | case 0x7f: /* FSQRT (vector) */ |
48 | n = 0; | 30 | break; |
49 | while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { | 31 | default: |
50 | if (n == 0) { | 32 | - fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); |
51 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) | 33 | + fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); |
52 | s->edm &= ~SDEDM_FSM_MASK; | 34 | g_assert_not_reached(); |
53 | s->edm |= SDEDM_FSM_DATAMODE; | ||
54 | trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm); | ||
55 | - | ||
56 | - if ((s->cmd & SDCMD_WRITE_CMD) && | ||
57 | + } | ||
58 | + if (is_write) { | ||
59 | + /* set block interrupt at end of each block transfer */ | ||
60 | + if (s->hbct && s->datacnt % s->hbct == 0 && | ||
61 | (s->config & SDHCFG_BLOCK_IRPT_EN)) { | ||
62 | s->status |= SDHSTS_BLOCK_IRPT; | ||
63 | } | ||
64 | + /* set data interrupt after each transfer */ | ||
65 | + s->status |= SDHSTS_DATA_FLAG; | ||
66 | + if (s->config & SDHCFG_DATA_IRPT_EN) { | ||
67 | + s->status |= SDHSTS_SDIO_IRPT; | ||
68 | + } | ||
69 | } | ||
70 | } | 35 | } |
71 | 36 | ||
72 | -- | 37 | -- |
73 | 2.17.1 | 38 | 2.20.1 |
74 | 39 | ||
75 | 40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
1 | 2 | ||
3 | Fix code style. Space required before the open parenthesis '('. | ||
4 | |||
5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
7 | Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/translate.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.c | ||
17 | +++ b/target/arm/translate.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
19 | - Hardware watchpoints. | ||
20 | Hardware breakpoints have already been handled and skip this code. | ||
21 | */ | ||
22 | - switch(dc->base.is_jmp) { | ||
23 | + switch (dc->base.is_jmp) { | ||
24 | case DISAS_NEXT: | ||
25 | case DISAS_TOO_MANY: | ||
26 | gen_goto_tb(dc, 1, dc->base.pc_next); | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
1 | 2 | ||
3 | We should at least document what this machine is about. | ||
4 | |||
5 | Reviewed-by: Graeme Gregory <graeme@nuviainc.com> | ||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Message-id: 20201104165254.24822-1-alex.bennee@linaro.org | ||
8 | Cc: Leif Lindholm <leif@nuviainc.com> | ||
9 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | ||
10 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | [PMM: fixed filename mismatch] | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++ | ||
15 | docs/system/target-arm.rst | 1 + | ||
16 | 2 files changed, 33 insertions(+) | ||
17 | create mode 100644 docs/system/arm/sbsa.rst | ||
18 | |||
19 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | ||
20 | new file mode 100644 | ||
21 | index XXXXXXX..XXXXXXX | ||
22 | --- /dev/null | ||
23 | +++ b/docs/system/arm/sbsa.rst | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | +Arm Server Base System Architecture Reference board (``sbsa-ref``) | ||
26 | +================================================================== | ||
27 | + | ||
28 | +While the `virt` board is a generic board platform that doesn't match | ||
29 | +any real hardware the `sbsa-ref` board intends to look like real | ||
30 | +hardware. The `Server Base System Architecture | ||
31 | +<https://developer.arm.com/documentation/den0029/latest>` defines a | ||
32 | +minimum base line of hardware support and importantly how the firmware | ||
33 | +reports that to any operating system. It is a static system that | ||
34 | +reports a very minimal DT to the firmware for non-discoverable | ||
35 | +information about components affected by the qemu command line (i.e. | ||
36 | +cpus and memory). As a result it must have a firmware specifically | ||
37 | +built to expect a certain hardware layout (as you would in a real | ||
38 | +machine). | ||
39 | + | ||
40 | +It is intended to be a machine for developing firmware and testing | ||
41 | +standards compliance with operating systems. | ||
42 | + | ||
43 | +Supported devices | ||
44 | +""""""""""""""""" | ||
45 | + | ||
46 | +The sbsa-ref board supports: | ||
47 | + | ||
48 | + - A configurable number of AArch64 CPUs | ||
49 | + - GIC version 3 | ||
50 | + - System bus AHCI controller | ||
51 | + - System bus EHCI controller | ||
52 | + - CDROM and hard disc on AHCI bus | ||
53 | + - E1000E ethernet card on PCIe bus | ||
54 | + - VGA display adaptor on PCIe bus | ||
55 | + - A generic SBSA watchdog device | ||
56 | + | ||
57 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/docs/system/target-arm.rst | ||
60 | +++ b/docs/system/target-arm.rst | ||
61 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
62 | arm/mps2 | ||
63 | arm/musca | ||
64 | arm/realview | ||
65 | + arm/sbsa | ||
66 | arm/versatile | ||
67 | arm/vexpress | ||
68 | arm/aspeed | ||
69 | -- | ||
70 | 2.20.1 | ||
71 | |||
72 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
1 | 2 | ||
3 | When using a Cortex-A15, the Virt machine does not use any | ||
4 | MPCore peripherals. Remove the dependency. | ||
5 | |||
6 | Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig") | ||
7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20201107114852.271922-1-philmd@redhat.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/arm/Kconfig | 1 - | ||
14 | 1 file changed, 1 deletion(-) | ||
15 | |||
16 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/arm/Kconfig | ||
19 | +++ b/hw/arm/Kconfig | ||
20 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | ||
21 | imply VFIO_PLATFORM | ||
22 | imply VFIO_XGMAC | ||
23 | imply TPM_TIS_SYSBUS | ||
24 | - select A15MPCORE | ||
25 | select ACPI | ||
26 | select ARM_SMMUV3 | ||
27 | select GPIO_KEY | ||
28 | -- | ||
29 | 2.20.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | nand_init() does not only create the NAND device, it also realizes | 3 | The helper function did not get updated when we reorganized |
4 | the device with qdev_init_nofail() already. So we must not call | 4 | the vector register file for SVE. Since then, the neon dregs |
5 | nand_init() from an instance_init function like sl_nand_init(), | 5 | are non-sequential and cannot be simply indexed. |
6 | otherwise we get superfluous NAND devices in the QOM tree after | ||
7 | introspecting the 'sl-nand' device. So move the nand_init() to the | ||
8 | realize function of 'sl-nand' instead. | ||
9 | 6 | ||
10 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 7 | At the same time, make the helper function operate on 64-bit |
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | quantities so that we do not have to call it twice. |
12 | Message-id: 1532006134-7701-1-git-send-email-thuth@redhat.com | 9 | |
10 | Fixes: c39c2b9043e | ||
11 | Reported-by: Ard Biesheuvel <ardb@kernel.org> | ||
12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | [PMM: use aa32_vfp_dreg() rather than opencoding] | ||
14 | Message-id: 20201105171126.88014-1-richard.henderson@linaro.org | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 17 | --- |
16 | hw/arm/spitz.c | 15 +++++++++++---- | 18 | target/arm/helper.h | 2 +- |
17 | 1 file changed, 11 insertions(+), 4 deletions(-) | 19 | target/arm/op_helper.c | 23 +++++++++-------- |
20 | target/arm/translate-neon.c.inc | 44 +++++++++++---------------------- | ||
21 | 3 files changed, 29 insertions(+), 40 deletions(-) | ||
18 | 22 | ||
19 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
20 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/spitz.c | 25 | --- a/target/arm/helper.h |
22 | +++ b/hw/arm/spitz.c | 26 | +++ b/target/arm/helper.h |
23 | @@ -XXX,XX +XXX,XX @@ static void sl_nand_init(Object *obj) | 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) |
28 | DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) | ||
29 | DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) | ||
30 | DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) | ||
31 | -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) | ||
33 | |||
34 | DEF_HELPER_3(shl_cc, i32, env, i32, i32) | ||
35 | DEF_HELPER_3(shr_cc, i32, env, i32, i32) | ||
36 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/op_helper.c | ||
39 | +++ b/target/arm/op_helper.c | ||
40 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
41 | cpu_loop_exit_restore(cs, ra); | ||
42 | } | ||
43 | |||
44 | -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, | ||
45 | - uint32_t maxindex) | ||
46 | +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, | ||
47 | + uint64_t ireg, uint64_t def) | ||
24 | { | 48 | { |
25 | SLNANDState *s = SL_NAND(obj); | 49 | - uint32_t val, shift; |
26 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | 50 | - uint64_t *table = vn; |
27 | - DriveInfo *nand; | 51 | + uint64_t tmp, val = 0; |
28 | 52 | + uint32_t maxindex = ((desc & 3) + 1) * 8; | |
29 | s->ctl = 0; | 53 | + uint32_t base_reg = desc >> 2; |
54 | + uint32_t shift, index, reg; | ||
55 | |||
56 | - val = 0; | ||
57 | - for (shift = 0; shift < 32; shift += 8) { | ||
58 | - uint32_t index = (ireg >> shift) & 0xff; | ||
59 | + for (shift = 0; shift < 64; shift += 8) { | ||
60 | + index = (ireg >> shift) & 0xff; | ||
61 | if (index < maxindex) { | ||
62 | - uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; | ||
63 | - val |= tmp << shift; | ||
64 | + reg = base_reg + (index >> 3); | ||
65 | + tmp = *aa32_vfp_dreg(env, reg); | ||
66 | + tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; | ||
67 | } else { | ||
68 | - val |= def & (0xff << shift); | ||
69 | + tmp = def & (0xffull << shift); | ||
70 | } | ||
71 | + val |= tmp; | ||
72 | } | ||
73 | return val; | ||
74 | } | ||
75 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/translate-neon.c.inc | ||
78 | +++ b/target/arm/translate-neon.c.inc | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
80 | |||
81 | static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
82 | { | ||
83 | - int n; | ||
84 | - TCGv_i32 tmp, tmp2, tmp3, tmp4; | ||
85 | - TCGv_ptr ptr1; | ||
86 | + TCGv_i64 val, def; | ||
87 | + TCGv_i32 desc; | ||
88 | |||
89 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
90 | return false; | ||
91 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
92 | return true; | ||
93 | } | ||
94 | |||
95 | - n = a->len + 1; | ||
96 | - if ((a->vn + n) > 32) { | ||
97 | + if ((a->vn + a->len + 1) > 32) { | ||
98 | /* | ||
99 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
100 | * helper function running off the end of the register file. | ||
101 | */ | ||
102 | return false; | ||
103 | } | ||
104 | - n <<= 3; | ||
105 | - tmp = tcg_temp_new_i32(); | ||
106 | - if (a->op) { | ||
107 | - read_neon_element32(tmp, a->vd, 0, MO_32); | ||
108 | - } else { | ||
109 | - tcg_gen_movi_i32(tmp, 0); | ||
110 | - } | ||
111 | - tmp2 = tcg_temp_new_i32(); | ||
112 | - read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
113 | - ptr1 = vfp_reg_ptr(true, a->vn); | ||
114 | - tmp4 = tcg_const_i32(n); | ||
115 | - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
116 | |||
117 | + desc = tcg_const_i32((a->vn << 2) | a->len); | ||
118 | + def = tcg_temp_new_i64(); | ||
119 | if (a->op) { | ||
120 | - read_neon_element32(tmp, a->vd, 1, MO_32); | ||
121 | + read_neon_element64(def, a->vd, 0, MO_64); | ||
122 | } else { | ||
123 | - tcg_gen_movi_i32(tmp, 0); | ||
124 | + tcg_gen_movi_i64(def, 0); | ||
125 | } | ||
126 | - tmp3 = tcg_temp_new_i32(); | ||
127 | - read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
128 | - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
129 | - tcg_temp_free_i32(tmp); | ||
130 | - tcg_temp_free_i32(tmp4); | ||
131 | - tcg_temp_free_ptr(ptr1); | ||
132 | + val = tcg_temp_new_i64(); | ||
133 | + read_neon_element64(val, a->vm, 0, MO_64); | ||
134 | |||
135 | - write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
136 | - write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
137 | - tcg_temp_free_i32(tmp2); | ||
138 | - tcg_temp_free_i32(tmp3); | ||
139 | + gen_helper_neon_tbl(val, cpu_env, desc, val, def); | ||
140 | + write_neon_element64(val, a->vd, 0, MO_64); | ||
30 | + | 141 | + |
31 | + memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40); | 142 | + tcg_temp_free_i64(def); |
32 | + sysbus_init_mmio(dev, &s->iomem); | 143 | + tcg_temp_free_i64(val); |
33 | +} | 144 | + tcg_temp_free_i32(desc); |
34 | + | 145 | return true; |
35 | +static void sl_nand_realize(DeviceState *dev, Error **errp) | ||
36 | +{ | ||
37 | + SLNANDState *s = SL_NAND(dev); | ||
38 | + DriveInfo *nand; | ||
39 | + | ||
40 | /* FIXME use a qdev drive property instead of drive_get() */ | ||
41 | nand = drive_get(IF_MTD, 0, 0); | ||
42 | s->nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL, | ||
43 | s->manf_id, s->chip_id); | ||
44 | - | ||
45 | - memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40); | ||
46 | - sysbus_init_mmio(dev, &s->iomem); | ||
47 | } | 146 | } |
48 | 147 | ||
49 | /* Spitz Keyboard */ | ||
50 | @@ -XXX,XX +XXX,XX @@ static void sl_nand_class_init(ObjectClass *klass, void *data) | ||
51 | |||
52 | dc->vmsd = &vmstate_sl_nand_info; | ||
53 | dc->props = sl_nand_properties; | ||
54 | + dc->realize = sl_nand_realize; | ||
55 | /* Reason: init() method uses drive_get() */ | ||
56 | dc->user_creatable = false; | ||
57 | } | ||
58 | -- | 148 | -- |
59 | 2.17.1 | 149 | 2.20.1 |
60 | 150 | ||
61 | 151 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | We can use one MPC per SRAM bank, but we currently only wire the | ||
4 | IRQ from the first expansion MPC to the IRQ splitter. Fix that. | ||
5 | |||
6 | Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines") | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20201107193403.436146-2-f4bug@amsat.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/arm/armsse.c | 3 ++- | ||
13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/hw/arm/armsse.c | ||
18 | +++ b/hw/arm/armsse.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
20 | qdev_get_gpio_in(dev_splitter, 0)); | ||
21 | qdev_connect_gpio_out(dev_splitter, 0, | ||
22 | qdev_get_gpio_in_named(dev_secctl, | ||
23 | - "mpc_status", 0)); | ||
24 | + "mpc_status", | ||
25 | + i - IOTS_NUM_EXP_MPC)); | ||
26 | } | ||
27 | |||
28 | qdev_connect_gpio_out(dev_splitter, 1, | ||
29 | -- | ||
30 | 2.20.1 | ||
31 | |||
32 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | The system configuration controller (SYSCFG) doesn't have | ||
4 | any output IRQ (and the INTC input #71 belongs to the UART6). | ||
5 | Remove the invalid code. | ||
6 | |||
7 | Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC") | ||
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 20201107193403.436146-3-f4bug@amsat.org | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
14 | hw/arm/stm32f205_soc.c | 1 - | ||
15 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
16 | 3 files changed, 5 deletions(-) | ||
17 | |||
18 | diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/misc/stm32f2xx_syscfg.h | ||
21 | +++ b/include/hw/misc/stm32f2xx_syscfg.h | ||
22 | @@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState { | ||
23 | uint32_t syscfg_exticr3; | ||
24 | uint32_t syscfg_exticr4; | ||
25 | uint32_t syscfg_cmpcr; | ||
26 | - | ||
27 | - qemu_irq irq; | ||
28 | }; | ||
29 | |||
30 | #endif /* HW_STM32F2XX_SYSCFG_H */ | ||
31 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/hw/arm/stm32f205_soc.c | ||
34 | +++ b/hw/arm/stm32f205_soc.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | ||
36 | } | ||
37 | busdev = SYS_BUS_DEVICE(dev); | ||
38 | sysbus_mmio_map(busdev, 0, 0x40013800); | ||
39 | - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); | ||
40 | |||
41 | /* Attach UART (uses USART registers) and USART controllers */ | ||
42 | for (i = 0; i < STM_NUM_USARTS; i++) { | ||
43 | diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/misc/stm32f2xx_syscfg.c | ||
46 | +++ b/hw/misc/stm32f2xx_syscfg.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj) | ||
48 | { | ||
49 | STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj); | ||
50 | |||
51 | - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | ||
52 | - | ||
53 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s, | ||
54 | TYPE_STM32F2XX_SYSCFG, 0x400); | ||
55 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | ||
56 | -- | ||
57 | 2.20.1 | ||
58 | |||
59 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic | ||
4 | OMAP2 chip support") takes care of creating the 3 UARTs. | ||
5 | |||
6 | Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+ | ||
7 | extensions and attach to n8x0's UART") added n8x0_uart_setup() | ||
8 | which create the UART and connects it to an IRQ output, | ||
9 | overwritting the existing peripheral and its IRQ connection. | ||
10 | This is incorrect. | ||
11 | |||
12 | Fortunately we don't need to fix this, because commit 6da68df7f9b | ||
13 | ("hw/arm/nseries: Replace the bluetooth chardev with a "null" | ||
14 | chardev") removed the use of this peripheral. We can simply | ||
15 | remove the code. | ||
16 | |||
17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
18 | Message-id: 20201107193403.436146-4-f4bug@amsat.org | ||
19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | --- | ||
22 | hw/arm/nseries.c | 11 ----------- | ||
23 | 1 file changed, 11 deletions(-) | ||
24 | |||
25 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/hw/arm/nseries.c | ||
28 | +++ b/hw/arm/nseries.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s) | ||
30 | cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); | ||
31 | } | ||
32 | |||
33 | -static void n8x0_uart_setup(struct n800_s *s) | ||
34 | -{ | ||
35 | - Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL); | ||
36 | - /* | ||
37 | - * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO | ||
38 | - * here, but this code has been removed with the bluetooth backend. | ||
39 | - */ | ||
40 | - omap_uart_attach(s->mpu->uart[BT_UART], radio); | ||
41 | -} | ||
42 | - | ||
43 | static void n8x0_usb_setup(struct n800_s *s) | ||
44 | { | ||
45 | SysBusDevice *dev; | ||
46 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
47 | n8x0_spi_setup(s); | ||
48 | n8x0_dss_setup(s); | ||
49 | n8x0_cbus_setup(s); | ||
50 | - n8x0_uart_setup(s); | ||
51 | if (machine_usb(machine)) { | ||
52 | n8x0_usb_setup(s); | ||
53 | } | ||
54 | -- | ||
55 | 2.20.1 | ||
56 | |||
57 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
1 | 2 | ||
3 | The MusicPal board code connects both of the IRQ outputs of the UART | ||
4 | to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly | ||
5 | to the same input is not valid as it produces subtly wrong behaviour | ||
6 | (for instance if both the IRQ lines are high, and then one goes | ||
7 | low, the INTC input will see this as a high-to-low transition | ||
8 | even though the second IRQ line should still be holding it high). | ||
9 | |||
10 | This kind of wiring needs an explicitly created OR gate; add one. | ||
11 | |||
12 | Inspired-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 20201107193403.436146-5-f4bug@amsat.org | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | --- | ||
18 | hw/arm/musicpal.c | 17 +++++++++++++---- | ||
19 | hw/arm/Kconfig | 1 + | ||
20 | 2 files changed, 14 insertions(+), 4 deletions(-) | ||
21 | |||
22 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/arm/musicpal.c | ||
25 | +++ b/hw/arm/musicpal.c | ||
26 | @@ -XXX,XX +XXX,XX @@ | ||
27 | #include "ui/console.h" | ||
28 | #include "hw/i2c/i2c.h" | ||
29 | #include "hw/irq.h" | ||
30 | +#include "hw/or-irq.h" | ||
31 | #include "hw/audio/wm8750.h" | ||
32 | #include "sysemu/block-backend.h" | ||
33 | #include "sysemu/runstate.h" | ||
34 | @@ -XXX,XX +XXX,XX @@ | ||
35 | #define MP_TIMER4_IRQ 7 | ||
36 | #define MP_EHCI_IRQ 8 | ||
37 | #define MP_ETH_IRQ 9 | ||
38 | -#define MP_UART1_IRQ 11 | ||
39 | -#define MP_UART2_IRQ 11 | ||
40 | +#define MP_UART_SHARED_IRQ 11 | ||
41 | #define MP_GPIO_IRQ 12 | ||
42 | #define MP_RTC_IRQ 28 | ||
43 | #define MP_AUDIO_IRQ 30 | ||
44 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
45 | ARMCPU *cpu; | ||
46 | qemu_irq pic[32]; | ||
47 | DeviceState *dev; | ||
48 | + DeviceState *uart_orgate; | ||
49 | DeviceState *i2c_dev; | ||
50 | DeviceState *lcd_dev; | ||
51 | DeviceState *key_dev; | ||
52 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
53 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
54 | pic[MP_TIMER4_IRQ], NULL); | ||
55 | |||
56 | - serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], | ||
57 | + /* Logically OR both UART IRQs together */ | ||
58 | + uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
59 | + object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
60 | + qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
61 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
62 | + | ||
63 | + serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
64 | + qdev_get_gpio_in(uart_orgate, 0), | ||
65 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); | ||
66 | - serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], | ||
67 | + serial_mm_init(address_space_mem, MP_UART2_BASE, 2, | ||
68 | + qdev_get_gpio_in(uart_orgate, 1), | ||
69 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); | ||
70 | |||
71 | /* Register flash */ | ||
72 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/arm/Kconfig | ||
75 | +++ b/hw/arm/Kconfig | ||
76 | @@ -XXX,XX +XXX,XX @@ config MUSCA | ||
77 | |||
78 | config MUSICPAL | ||
79 | bool | ||
80 | + select OR_IRQ | ||
81 | select BITBANG_I2C | ||
82 | select MARVELL_88W8618 | ||
83 | select PTIMER | ||
84 | -- | ||
85 | 2.20.1 | ||
86 | |||
87 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> |
---|---|---|---|
2 | 2 | ||
3 | Valgrind complains: | 3 | We don't need to fill the full pic[] array if we only use |
4 | few of the interrupt lines. Directly call qdev_get_gpio_in() | ||
5 | when necessary. | ||
4 | 6 | ||
5 | echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \ | 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | "'arguments':{'typename':'xlnx,zynqmp-pmu-soc'}}" \ | 8 | Message-id: 20201107193403.436146-6-f4bug@amsat.org |
7 | "{'execute': 'human-monitor-command', " \ | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | "'arguments': {'command-line': 'info qtree'}}" | \ | ||
9 | valgrind -q microblazeel-softmmu/qemu-system-microblazeel -M none,accel=qtest -qmp stdio | ||
10 | [...] | ||
11 | ==13605== Invalid read of size 8 | ||
12 | ==13605== at 0x2AC69A: qdev_print (qdev-monitor.c:686) | ||
13 | ==13605== by 0x2AC69A: qbus_print (qdev-monitor.c:719) | ||
14 | ==13605== by 0x2591E8: handle_hmp_command (monitor.c:3446) | ||
15 | |||
16 | Use the new object_initialize_child() and sysbus_init_child_obj() to | ||
17 | fix the issue. | ||
18 | |||
19 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
20 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
21 | Message-id: 1531839343-13828-1-git-send-email-thuth@redhat.com | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | --- | 11 | --- |
24 | hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++------ | 12 | hw/arm/musicpal.c | 25 +++++++++++++------------ |
25 | 1 file changed, 4 insertions(+), 6 deletions(-) | 13 | 1 file changed, 13 insertions(+), 12 deletions(-) |
26 | 14 | ||
27 | diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c | 15 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
28 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/microblaze/xlnx-zynqmp-pmu.c | 17 | --- a/hw/arm/musicpal.c |
30 | +++ b/hw/microblaze/xlnx-zynqmp-pmu.c | 18 | +++ b/hw/arm/musicpal.c |
31 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_pmu_soc_init(Object *obj) | 19 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = { |
20 | static void musicpal_init(MachineState *machine) | ||
32 | { | 21 | { |
33 | XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj); | 22 | ARMCPU *cpu; |
34 | 23 | - qemu_irq pic[32]; | |
35 | - object_initialize(&s->cpu, sizeof(s->cpu), | 24 | DeviceState *dev; |
36 | - TYPE_MICROBLAZE_CPU); | 25 | + DeviceState *pic; |
37 | - object_property_add_child(obj, "pmu-cpu", OBJECT(&s->cpu), | 26 | DeviceState *uart_orgate; |
38 | - &error_abort); | 27 | DeviceState *i2c_dev; |
39 | + object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu), | 28 | DeviceState *lcd_dev; |
40 | + TYPE_MICROBLAZE_CPU, &error_abort, NULL); | 29 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) |
41 | 30 | &error_fatal); | |
42 | - object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC); | 31 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); |
43 | - qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default()); | 32 | |
44 | + sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), | 33 | - dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, |
45 | + TYPE_XLNX_PMU_IO_INTC); | 34 | + pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, |
46 | } | 35 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
47 | 36 | - for (i = 0; i < 32; i++) { | |
48 | static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) | 37 | - pic[i] = qdev_get_gpio_in(dev, i); |
38 | - } | ||
39 | - sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], | ||
40 | - pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
41 | - pic[MP_TIMER4_IRQ], NULL); | ||
42 | + sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, | ||
43 | + qdev_get_gpio_in(pic, MP_TIMER1_IRQ), | ||
44 | + qdev_get_gpio_in(pic, MP_TIMER2_IRQ), | ||
45 | + qdev_get_gpio_in(pic, MP_TIMER3_IRQ), | ||
46 | + qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); | ||
47 | |||
48 | /* Logically OR both UART IRQs together */ | ||
49 | uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
50 | object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
51 | qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
52 | - qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
53 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, | ||
54 | + qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); | ||
55 | |||
56 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
57 | qdev_get_gpio_in(uart_orgate, 0), | ||
58 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
59 | OBJECT(get_system_memory()), &error_fatal); | ||
60 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
61 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); | ||
62 | - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | ||
63 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | ||
64 | + qdev_get_gpio_in(pic, MP_ETH_IRQ)); | ||
65 | |||
66 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); | ||
67 | |||
68 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); | ||
69 | |||
70 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, | ||
71 | - pic[MP_GPIO_IRQ]); | ||
72 | + qdev_get_gpio_in(pic, MP_GPIO_IRQ)); | ||
73 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); | ||
74 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); | ||
75 | |||
76 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
77 | NULL); | ||
78 | sysbus_realize_and_unref(s, &error_fatal); | ||
79 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); | ||
80 | - sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | ||
81 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); | ||
82 | |||
83 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; | ||
84 | arm_load_kernel(cpu, machine, &musicpal_binfo); | ||
49 | -- | 85 | -- |
50 | 2.17.1 | 86 | 2.20.1 |
51 | 87 | ||
52 | 88 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The nseries machines have a codepath that allows them to load a | ||
2 | secondary bootloader. This code wasn't checking that the | ||
3 | load_image_targphys() succeeded. Check the return value and report | ||
4 | the error to the user. | ||
1 | 5 | ||
6 | While we're in the vicinity, fix the comment style of the | ||
7 | comment documenting what this image load is doing. | ||
8 | |||
9 | Fixes: Coverity CID 1192904 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Message-id: 20201103114918.11807-1-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/nseries.c | 15 +++++++++++---- | ||
15 | 1 file changed, 11 insertions(+), 4 deletions(-) | ||
16 | |||
17 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/nseries.c | ||
20 | +++ b/hw/arm/nseries.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
22 | /* No, wait, better start at the ROM. */ | ||
23 | s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; | ||
24 | |||
25 | - /* This is intended for loading the `secondary.bin' program from | ||
26 | + /* | ||
27 | + * This is intended for loading the `secondary.bin' program from | ||
28 | * Nokia images (the NOLO bootloader). The entry point seems | ||
29 | * to be at OMAP2_Q2_BASE + 0x400000. | ||
30 | * | ||
31 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
32 | * for them the entry point needs to be set to OMAP2_SRAM_BASE. | ||
33 | * | ||
34 | * The code above is for loading the `zImage' file from Nokia | ||
35 | - * images. */ | ||
36 | - load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, | ||
37 | - machine->ram_size - 0x400000); | ||
38 | + * images. | ||
39 | + */ | ||
40 | + if (load_image_targphys(option_rom[0].name, | ||
41 | + OMAP2_Q2_BASE + 0x400000, | ||
42 | + machine->ram_size - 0x400000) < 0) { | ||
43 | + error_report("Failed to load secondary bootloader %s", | ||
44 | + option_rom[0].name); | ||
45 | + exit(EXIT_FAILURE); | ||
46 | + } | ||
47 | |||
48 | n800_setup_nolo_tags(nolo_tags); | ||
49 | cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); | ||
50 | -- | ||
51 | 2.20.1 | ||
52 | |||
53 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Havard Skinnemoen <hskinnemoen@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The instance_init function of the "exynos4210.gic" device creates a | 3 | The number of runs is equal to the number of 0-1 and 1-0 transitions, |
4 | new "arm_gic" device and immediately realizes it with qdev_init_nofail(). | 4 | plus one. Currently, it's counting the number of times these transitions |
5 | This will leave a lot of object in the QOM tree during introspection of | 5 | do _not_ happen, plus one. |
6 | the "exynos4210.gic" device, e.g. reproducible by starting QEMU like this: | ||
7 | 6 | ||
8 | qemu-system-aarch64 -M none -nodefaults -nographic -monitor stdio | 7 | Source: |
8 | https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf | ||
9 | section 2.3.4 point (3). | ||
9 | 10 | ||
10 | And then by running "info qom-tree" at the HMP monitor, followed by | 11 | Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> |
11 | "device_add exynos4210.gic,help" and finally checking "info qom-tree" | 12 | Message-id: 20201103011457.2959989-2-hskinnemoen@google.com |
12 | again. | ||
13 | |||
14 | Also note that qdev_init_nofail() can exit QEMU in case of errors - and | ||
15 | this must never happen during an instance_init function, otherwise QEMU | ||
16 | could terminate unexpectedly during introspection of a device. | ||
17 | |||
18 | Since most of the code that follows the qdev_init_nofail() depends on | ||
19 | the realized "gicbusdev", the easiest solution to the problem is to | ||
20 | turn the whole instance_init function into a realize function instead. | ||
21 | |||
22 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
23 | Message-id: 1532337784-334-1-git-send-email-thuth@redhat.com | ||
24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 15 | --- |
27 | hw/intc/exynos4210_gic.c | 6 +++--- | 16 | tests/qtest/npcm7xx_rng-test.c | 2 +- |
28 | 1 file changed, 3 insertions(+), 3 deletions(-) | 17 | 1 file changed, 1 insertion(+), 1 deletion(-) |
29 | 18 | ||
30 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 19 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c |
31 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/intc/exynos4210_gic.c | 21 | --- a/tests/qtest/npcm7xx_rng-test.c |
33 | +++ b/hw/intc/exynos4210_gic.c | 22 | +++ b/tests/qtest/npcm7xx_rng-test.c |
34 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_set_irq(void *opaque, int irq, int level) | 23 | @@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits) |
35 | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); | 24 | pi = (double)nr_ones / nr_bits; |
36 | } | 25 | |
37 | 26 | for (k = 0; k < nr_bits - 1; k++) { | |
38 | -static void exynos4210_gic_init(Object *obj) | 27 | - vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf)); |
39 | +static void exynos4210_gic_realize(DeviceState *dev, Error **errp) | 28 | + vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf)); |
40 | { | 29 | } |
41 | - DeviceState *dev = DEVICE(obj); | 30 | vn_obs += 1; |
42 | + Object *obj = OBJECT(dev); | ||
43 | Exynos4210GicState *s = EXYNOS4210_GIC(obj); | ||
44 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | ||
45 | const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; | ||
46 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_class_init(ObjectClass *klass, void *data) | ||
47 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
48 | |||
49 | dc->props = exynos4210_gic_properties; | ||
50 | + dc->realize = exynos4210_gic_realize; | ||
51 | } | ||
52 | |||
53 | static const TypeInfo exynos4210_gic_info = { | ||
54 | .name = TYPE_EXYNOS4210_GIC, | ||
55 | .parent = TYPE_SYS_BUS_DEVICE, | ||
56 | .instance_size = sizeof(Exynos4210GicState), | ||
57 | - .instance_init = exynos4210_gic_init, | ||
58 | .class_init = exynos4210_gic_class_init, | ||
59 | }; | ||
60 | 31 | ||
61 | -- | 32 | -- |
62 | 2.17.1 | 33 | 2.20.1 |
63 | 34 | ||
64 | 35 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Checks for UNDEF cases should go before the "is VFP enabled?" access | ||
2 | check, except in special cases. Move a stray UNDEF check in the VTBL | ||
3 | trans function up above the access check. | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20201109145324.2859-1-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate-neon.c.inc | 8 ++++---- | ||
10 | 1 file changed, 4 insertions(+), 4 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/translate-neon.c.inc | ||
15 | +++ b/target/arm/translate-neon.c.inc | ||
16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
17 | return false; | ||
18 | } | ||
19 | |||
20 | - if (!vfp_access_check(s)) { | ||
21 | - return true; | ||
22 | - } | ||
23 | - | ||
24 | if ((a->vn + a->len + 1) > 32) { | ||
25 | /* | ||
26 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
28 | return false; | ||
29 | } | ||
30 | |||
31 | + if (!vfp_access_check(s)) { | ||
32 | + return true; | ||
33 | + } | ||
34 | + | ||
35 | desc = tcg_const_i32((a->vn << 2) | a->len); | ||
36 | def = tcg_temp_new_i64(); | ||
37 | if (a->op) { | ||
38 | -- | ||
39 | 2.20.1 | ||
40 | |||
41 | diff view generated by jsdifflib |