1 | target-arm queue for 3.0: | 1 | Arm patches for rc3 : just a handful of bug fixes. |
---|---|---|---|
2 | |||
3 | Thomas' fixes for instrospection issues with a handful of | ||
4 | devices (including one microblaze one that I include in this | ||
5 | pullreq for convenience's sake), plus my bugfix for a | ||
6 | corner case of small MPU region support. | ||
7 | 2 | ||
8 | thanks | 3 | thanks |
9 | -- PMM | 4 | -- PMM |
10 | 5 | ||
11 | The following changes since commit 55b1f14cefcb19ce6d5e28c4c83404230888aa7e: | ||
12 | 6 | ||
13 | Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-07-23 14:03:14 +0100) | 7 | The following changes since commit 4ecc984210ca1bf508a96a550ec8a93a5f833f6c: |
8 | |||
9 | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.2-rc3' into staging (2019-11-26 12:36:40 +0000) | ||
14 | 10 | ||
15 | are available in the Git repository at: | 11 | are available in the Git repository at: |
16 | 12 | ||
17 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180723 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191126 |
18 | 14 | ||
19 | for you to fetch changes up to 1ddc9b98c3cb89fe23a55ba924000fd645253e87: | 15 | for you to fetch changes up to 6a4ef4e5d1084ce41fafa7d470a644b0fd3d9317: |
20 | 16 | ||
21 | hw/intc/exynos4210_gic: Turn instance_init into realize function (2018-07-23 15:21:27 +0100) | 17 | target/arm: Honor HCR_EL2.TID3 trapping requirements (2019-11-26 13:55:37 +0000) |
22 | 18 | ||
23 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
24 | target-arm queue: | 20 | target-arm queue: |
25 | * spitz, exynos: fix bugs when introspecting some devices | 21 | * handle FTYPE flag correctly in v7M exception return |
26 | * hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc' | 22 | for v7M CPUs with an FPU (v8M CPUs were already correct) |
27 | * target/arm: Correctly handle overlapping small MPU regions | 23 | * versal: Add the CRP as unimplemented |
28 | * hw/sd/bcm2835_sdhost: Fix PIO mode writes | 24 | * Fix ISR_EL1 tracking when executing at EL2 |
25 | * Honor HCR_EL2.TID3 trapping requirements | ||
29 | 26 | ||
30 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
31 | Guenter Roeck (1): | 28 | Edgar E. Iglesias (1): |
32 | hw/sd/bcm2835_sdhost: Fix PIO mode writes | 29 | hw/arm: versal: Add the CRP as unimplemented |
33 | 30 | ||
34 | Peter Maydell (1): | 31 | Jean-Hugues Deschênes (1): |
35 | target/arm: Correctly handle overlapping small MPU regions | 32 | target/arm: Fix handling of cortex-m FTYPE flag in EXCRET |
36 | 33 | ||
37 | Thomas Huth (3): | 34 | Marc Zyngier (2): |
38 | hw/microblaze/xlnx-zynqmp-pmu: Fix introspection problem in 'xlnx, zynqmp-pmu-soc' | 35 | target/arm: Fix ISR_EL1 tracking when executing at EL2 |
39 | hw/arm/spitz: Move problematic nand_init() code to realize function | 36 | target/arm: Honor HCR_EL2.TID3 trapping requirements |
40 | hw/intc/exynos4210_gic: Turn instance_init into realize function | ||
41 | 37 | ||
42 | hw/arm/spitz.c | 15 ++++++++++---- | 38 | include/hw/arm/xlnx-versal.h | 3 ++ |
43 | hw/intc/exynos4210_gic.c | 6 +++--- | 39 | hw/arm/xlnx-versal.c | 2 ++ |
44 | hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++----- | 40 | target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++++++++-- |
45 | hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++---- | 41 | target/arm/m_helper.c | 7 ++-- |
46 | target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++ | 42 | 4 files changed, 89 insertions(+), 6 deletions(-) |
47 | 5 files changed, 80 insertions(+), 17 deletions(-) | ||
48 | 43 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Thomas Huth <thuth@redhat.com> | ||
2 | 1 | ||
3 | Valgrind complains: | ||
4 | |||
5 | echo "{'execute':'qmp_capabilities'} {'execute':'device-list-properties'," \ | ||
6 | "'arguments':{'typename':'xlnx,zynqmp-pmu-soc'}}" \ | ||
7 | "{'execute': 'human-monitor-command', " \ | ||
8 | "'arguments': {'command-line': 'info qtree'}}" | \ | ||
9 | valgrind -q microblazeel-softmmu/qemu-system-microblazeel -M none,accel=qtest -qmp stdio | ||
10 | [...] | ||
11 | ==13605== Invalid read of size 8 | ||
12 | ==13605== at 0x2AC69A: qdev_print (qdev-monitor.c:686) | ||
13 | ==13605== by 0x2AC69A: qbus_print (qdev-monitor.c:719) | ||
14 | ==13605== by 0x2591E8: handle_hmp_command (monitor.c:3446) | ||
15 | |||
16 | Use the new object_initialize_child() and sysbus_init_child_obj() to | ||
17 | fix the issue. | ||
18 | |||
19 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
20 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
21 | Message-id: 1531839343-13828-1-git-send-email-thuth@redhat.com | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | --- | ||
24 | hw/microblaze/xlnx-zynqmp-pmu.c | 10 ++++------ | ||
25 | 1 file changed, 4 insertions(+), 6 deletions(-) | ||
26 | |||
27 | diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/microblaze/xlnx-zynqmp-pmu.c | ||
30 | +++ b/hw/microblaze/xlnx-zynqmp-pmu.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_pmu_soc_init(Object *obj) | ||
32 | { | ||
33 | XlnxZynqMPPMUSoCState *s = XLNX_ZYNQMP_PMU_SOC(obj); | ||
34 | |||
35 | - object_initialize(&s->cpu, sizeof(s->cpu), | ||
36 | - TYPE_MICROBLAZE_CPU); | ||
37 | - object_property_add_child(obj, "pmu-cpu", OBJECT(&s->cpu), | ||
38 | - &error_abort); | ||
39 | + object_initialize_child(obj, "pmu-cpu", &s->cpu, sizeof(s->cpu), | ||
40 | + TYPE_MICROBLAZE_CPU, &error_abort, NULL); | ||
41 | |||
42 | - object_initialize(&s->intc, sizeof(s->intc), TYPE_XLNX_PMU_IO_INTC); | ||
43 | - qdev_set_parent_bus(DEVICE(&s->intc), sysbus_get_default()); | ||
44 | + sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc), | ||
45 | + TYPE_XLNX_PMU_IO_INTC); | ||
46 | } | ||
47 | |||
48 | static void xlnx_zynqmp_pmu_soc_realize(DeviceState *dev, Error **errp) | ||
49 | -- | ||
50 | 2.17.1 | ||
51 | |||
52 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Jean-Hugues Deschênes <Jean-Hugues.Deschenes@ossiaco.com> |
---|---|---|---|
2 | 2 | ||
3 | Writes in PIO mode have two requirements: | 3 | According to the PushStack() pseudocode in the armv7m RM, |
4 | bit 4 of the LR should be set to NOT(CONTROL.PFCA) when | ||
5 | an FPU is present. Current implementation is doing it for | ||
6 | armv8, but not for armv7. This patch makes the existing | ||
7 | logic applicable to both code paths. | ||
4 | 8 | ||
5 | - A data interrupt must be generated after a write command has been | 9 | Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@ossiaco.com> |
6 | issued to indicate that the chip is ready to receive data. | ||
7 | - A block interrupt must be generated after each block to indicate | ||
8 | that the chip is ready to receive the next data block. | ||
9 | |||
10 | Rearrange the code to make this happen. Tested on raspi3 (in PIO mode) | ||
11 | and raspi2 (in DMA mode). | ||
12 | |||
13 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
14 | Message-id: 1531779837-20557-1-git-send-email-linux@roeck-us.net | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 12 | --- |
18 | hw/sd/bcm2835_sdhost.c | 20 ++++++++++++++++---- | 13 | target/arm/m_helper.c | 7 +++---- |
19 | 1 file changed, 16 insertions(+), 4 deletions(-) | 14 | 1 file changed, 3 insertions(+), 4 deletions(-) |
20 | 15 | ||
21 | diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c | 16 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
22 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/sd/bcm2835_sdhost.c | 18 | --- a/target/arm/m_helper.c |
24 | +++ b/hw/sd/bcm2835_sdhost.c | 19 | +++ b/target/arm/m_helper.c |
25 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) | 20 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) |
26 | uint32_t value = 0; | 21 | if (env->v7m.secure) { |
27 | int n; | 22 | lr |= R_V7M_EXCRET_S_MASK; |
28 | int is_read; | 23 | } |
29 | + int is_write; | 24 | - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { |
30 | 25 | - lr |= R_V7M_EXCRET_FTYPE_MASK; | |
31 | is_read = (s->cmd & SDCMD_READ_CMD) != 0; | 26 | - } |
32 | - if (s->datacnt != 0 && (!is_read || sdbus_data_ready(&s->sdbus))) { | 27 | } else { |
33 | + is_write = (s->cmd & SDCMD_WRITE_CMD) != 0; | 28 | lr = R_V7M_EXCRET_RES1_MASK | |
34 | + if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) { | 29 | R_V7M_EXCRET_S_MASK | |
35 | if (is_read) { | 30 | R_V7M_EXCRET_DCRS_MASK | |
36 | n = 0; | 31 | - R_V7M_EXCRET_FTYPE_MASK | |
37 | while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) { | 32 | R_V7M_EXCRET_ES_MASK; |
38 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) | 33 | if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { |
39 | if (n != 0) { | 34 | lr |= R_V7M_EXCRET_SPSEL_MASK; |
40 | bcm2835_sdhost_fifo_push(s, value); | ||
41 | s->status |= SDHSTS_DATA_FLAG; | ||
42 | + if (s->config & SDHCFG_DATA_IRPT_EN) { | ||
43 | + s->status |= SDHSTS_SDIO_IRPT; | ||
44 | + } | ||
45 | } | ||
46 | - } else { /* write */ | ||
47 | + } else if (is_write) { /* write */ | ||
48 | n = 0; | ||
49 | while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { | ||
50 | if (n == 0) { | ||
51 | @@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) | ||
52 | s->edm &= ~SDEDM_FSM_MASK; | ||
53 | s->edm |= SDEDM_FSM_DATAMODE; | ||
54 | trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm); | ||
55 | - | ||
56 | - if ((s->cmd & SDCMD_WRITE_CMD) && | ||
57 | + } | ||
58 | + if (is_write) { | ||
59 | + /* set block interrupt at end of each block transfer */ | ||
60 | + if (s->hbct && s->datacnt % s->hbct == 0 && | ||
61 | (s->config & SDHCFG_BLOCK_IRPT_EN)) { | ||
62 | s->status |= SDHSTS_BLOCK_IRPT; | ||
63 | } | ||
64 | + /* set data interrupt after each transfer */ | ||
65 | + s->status |= SDHSTS_DATA_FLAG; | ||
66 | + if (s->config & SDHCFG_DATA_IRPT_EN) { | ||
67 | + s->status |= SDHSTS_SDIO_IRPT; | ||
68 | + } | ||
69 | } | 35 | } |
70 | } | 36 | } |
71 | 37 | + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { | |
38 | + lr |= R_V7M_EXCRET_FTYPE_MASK; | ||
39 | + } | ||
40 | if (!arm_v7m_is_handler_mode(env)) { | ||
41 | lr |= R_V7M_EXCRET_MODE_MASK; | ||
42 | } | ||
72 | -- | 43 | -- |
73 | 2.17.1 | 44 | 2.20.1 |
74 | 45 | ||
75 | 46 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> |
---|---|---|---|
2 | 2 | ||
3 | The instance_init function of the "exynos4210.gic" device creates a | 3 | Add the CRP as unimplemented thus avoiding bus errors when |
4 | new "arm_gic" device and immediately realizes it with qdev_init_nofail(). | 4 | guests access these registers. |
5 | This will leave a lot of object in the QOM tree during introspection of | ||
6 | the "exynos4210.gic" device, e.g. reproducible by starting QEMU like this: | ||
7 | 5 | ||
8 | qemu-system-aarch64 -M none -nodefaults -nographic -monitor stdio | 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
9 | 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | |
10 | And then by running "info qom-tree" at the HMP monitor, followed by | 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> |
11 | "device_add exynos4210.gic,help" and finally checking "info qom-tree" | 9 | Message-id: 20191115154734.26449-2-edgar.iglesias@gmail.com |
12 | again. | ||
13 | |||
14 | Also note that qdev_init_nofail() can exit QEMU in case of errors - and | ||
15 | this must never happen during an instance_init function, otherwise QEMU | ||
16 | could terminate unexpectedly during introspection of a device. | ||
17 | |||
18 | Since most of the code that follows the qdev_init_nofail() depends on | ||
19 | the realized "gicbusdev", the easiest solution to the problem is to | ||
20 | turn the whole instance_init function into a realize function instead. | ||
21 | |||
22 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
23 | Message-id: 1532337784-334-1-git-send-email-thuth@redhat.com | ||
24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
26 | --- | 11 | --- |
27 | hw/intc/exynos4210_gic.c | 6 +++--- | 12 | include/hw/arm/xlnx-versal.h | 3 +++ |
28 | 1 file changed, 3 insertions(+), 3 deletions(-) | 13 | hw/arm/xlnx-versal.c | 2 ++ |
14 | 2 files changed, 5 insertions(+) | ||
29 | 15 | ||
30 | diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c | 16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
31 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
32 | --- a/hw/intc/exynos4210_gic.c | 18 | --- a/include/hw/arm/xlnx-versal.h |
33 | +++ b/hw/intc/exynos4210_gic.c | 19 | +++ b/include/hw/arm/xlnx-versal.h |
34 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_set_irq(void *opaque, int irq, int level) | 20 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { |
35 | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); | 21 | #define MM_IOU_SCNTRS_SIZE 0x10000 |
36 | } | 22 | #define MM_FPD_CRF 0xfd1a0000U |
37 | 23 | #define MM_FPD_CRF_SIZE 0x140000 | |
38 | -static void exynos4210_gic_init(Object *obj) | 24 | + |
39 | +static void exynos4210_gic_realize(DeviceState *dev, Error **errp) | 25 | +#define MM_PMC_CRP 0xf1260000U |
40 | { | 26 | +#define MM_PMC_CRP_SIZE 0x10000 |
41 | - DeviceState *dev = DEVICE(obj); | 27 | #endif |
42 | + Object *obj = OBJECT(dev); | 28 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c |
43 | Exynos4210GicState *s = EXYNOS4210_GIC(obj); | 29 | index XXXXXXX..XXXXXXX 100644 |
44 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | 30 | --- a/hw/arm/xlnx-versal.c |
45 | const char cpu_prefix[] = "exynos4210-gic-alias_cpu"; | 31 | +++ b/hw/arm/xlnx-versal.c |
46 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_class_init(ObjectClass *klass, void *data) | 32 | @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) |
47 | DeviceClass *dc = DEVICE_CLASS(klass); | 33 | MM_CRL, MM_CRL_SIZE); |
48 | 34 | versal_unimp_area(s, "crf", &s->mr_ps, | |
49 | dc->props = exynos4210_gic_properties; | 35 | MM_FPD_CRF, MM_FPD_CRF_SIZE); |
50 | + dc->realize = exynos4210_gic_realize; | 36 | + versal_unimp_area(s, "crp", &s->mr_ps, |
51 | } | 37 | + MM_PMC_CRP, MM_PMC_CRP_SIZE); |
52 | 38 | versal_unimp_area(s, "iou-scntr", &s->mr_ps, | |
53 | static const TypeInfo exynos4210_gic_info = { | 39 | MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); |
54 | .name = TYPE_EXYNOS4210_GIC, | 40 | versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, |
55 | .parent = TYPE_SYS_BUS_DEVICE, | ||
56 | .instance_size = sizeof(Exynos4210GicState), | ||
57 | - .instance_init = exynos4210_gic_init, | ||
58 | .class_init = exynos4210_gic_class_init, | ||
59 | }; | ||
60 | |||
61 | -- | 41 | -- |
62 | 2.17.1 | 42 | 2.20.1 |
63 | 43 | ||
64 | 44 | diff view generated by jsdifflib |
1 | To correctly handle small (less than TARGET_PAGE_SIZE) MPU regions, | 1 | From: Marc Zyngier <maz@kernel.org> |
---|---|---|---|
2 | we must correctly handle the case where the address being looked | ||
3 | up hits in an MPU region that is not small but the address is | ||
4 | in the same page as a small region. For instance if MPU region | ||
5 | 1 covers an entire page from 0x2000 to 0x2400 and MPU region | ||
6 | 2 is small and covers only 0x2200 to 0x2280, then for an access | ||
7 | to 0x2000 we must not return a result covering the full page | ||
8 | even though we hit the page-sized region 1. Otherwise we will | ||
9 | then cache that result in the TLB and accesses that should | ||
10 | hit region 2 will incorrectly find the region 1 information. | ||
11 | 2 | ||
12 | Check for the case where we miss an MPU region but it is still | 3 | The ARMv8 ARM states when executing at EL2, EL3 or Secure EL1, |
13 | within the same page, and in that case narrow the size we will | 4 | ISR_EL1 shows the pending status of the physical IRQ, FIQ, or |
14 | pass to tlb_set_page_with_attrs() for whatever the final | 5 | SError interrupts. |
15 | outcome is of the MPU lookup. | ||
16 | 6 | ||
17 | Reported-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com> | 7 | Unfortunately, QEMU's implementation only considers the HCR_EL2 |
8 | bits, and ignores the current exception level. This means a hypervisor | ||
9 | trying to look at its own interrupt state actually sees the guest | ||
10 | state, which is unexpected and breaks KVM as of Linux 5.3. | ||
11 | |||
12 | Instead, check for the running EL and return the physical bits | ||
13 | if not running in a virtualized context. | ||
14 | |||
15 | Fixes: 636540e9c40b | ||
16 | Cc: qemu-stable@nongnu.org | ||
17 | Reported-by: Quentin Perret <qperret@google.com> | ||
18 | Signed-off-by: Marc Zyngier <maz@kernel.org> | ||
19 | Message-id: 20191122135833.28953-1-maz@kernel.org | ||
20 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
21 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
20 | Message-id: 20180716133302.25989-1-peter.maydell@linaro.org | ||
21 | --- | 23 | --- |
22 | target/arm/helper.c | 46 +++++++++++++++++++++++++++++++++++++++++++++ | 24 | target/arm/helper.c | 7 +++++-- |
23 | 1 file changed, 46 insertions(+) | 25 | 1 file changed, 5 insertions(+), 2 deletions(-) |
24 | 26 | ||
25 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 27 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
26 | index XXXXXXX..XXXXXXX 100644 | 28 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/helper.c | 29 | --- a/target/arm/helper.c |
28 | +++ b/target/arm/helper.c | 30 | +++ b/target/arm/helper.c |
29 | @@ -XXX,XX +XXX,XX @@ | 31 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
30 | #include "exec/semihost.h" | 32 | CPUState *cs = env_cpu(env); |
31 | #include "sysemu/kvm.h" | 33 | uint64_t hcr_el2 = arm_hcr_el2_eff(env); |
32 | #include "fpu/softfloat.h" | 34 | uint64_t ret = 0; |
33 | +#include "qemu/range.h" | 35 | + bool allow_virt = (arm_current_el(env) == 1 && |
34 | 36 | + (!arm_is_secure_below_el3(env) || | |
35 | #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ | 37 | + (env->cp15.scr_el3 & SCR_EEL2))); |
36 | 38 | ||
37 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | 39 | - if (hcr_el2 & HCR_IMO) { |
38 | } | 40 | + if (allow_virt && (hcr_el2 & HCR_IMO)) { |
39 | 41 | if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { | |
40 | if (address < base || address > base + rmask) { | 42 | ret |= CPSR_I; |
41 | + /* | ||
42 | + * Address not in this region. We must check whether the | ||
43 | + * region covers addresses in the same page as our address. | ||
44 | + * In that case we must not report a size that covers the | ||
45 | + * whole page for a subsequent hit against a different MPU | ||
46 | + * region or the background region, because it would result in | ||
47 | + * incorrect TLB hits for subsequent accesses to addresses that | ||
48 | + * are in this MPU region. | ||
49 | + */ | ||
50 | + if (ranges_overlap(base, rmask, | ||
51 | + address & TARGET_PAGE_MASK, | ||
52 | + TARGET_PAGE_SIZE)) { | ||
53 | + *page_size = 1; | ||
54 | + } | ||
55 | continue; | ||
56 | } | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, | ||
59 | sattrs->srvalid = true; | ||
60 | sattrs->sregion = r; | ||
61 | } | ||
62 | + } else { | ||
63 | + /* | ||
64 | + * Address not in this region. We must check whether the | ||
65 | + * region covers addresses in the same page as our address. | ||
66 | + * In that case we must not report a size that covers the | ||
67 | + * whole page for a subsequent hit against a different MPU | ||
68 | + * region or the background region, because it would result | ||
69 | + * in incorrect TLB hits for subsequent accesses to | ||
70 | + * addresses that are in this MPU region. | ||
71 | + */ | ||
72 | + if (limit >= base && | ||
73 | + ranges_overlap(base, limit - base + 1, | ||
74 | + addr_page_base, | ||
75 | + TARGET_PAGE_SIZE)) { | ||
76 | + sattrs->subpage = true; | ||
77 | + } | ||
78 | } | ||
79 | } | ||
80 | } | 43 | } |
81 | @@ -XXX,XX +XXX,XX @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, | 44 | @@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) |
82 | } | 45 | } |
83 | 46 | } | |
84 | if (address < base || address > limit) { | 47 | |
85 | + /* | 48 | - if (hcr_el2 & HCR_FMO) { |
86 | + * Address not in this region. We must check whether the | 49 | + if (allow_virt && (hcr_el2 & HCR_FMO)) { |
87 | + * region covers addresses in the same page as our address. | 50 | if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { |
88 | + * In that case we must not report a size that covers the | 51 | ret |= CPSR_F; |
89 | + * whole page for a subsequent hit against a different MPU | 52 | } |
90 | + * region or the background region, because it would result in | ||
91 | + * incorrect TLB hits for subsequent accesses to addresses that | ||
92 | + * are in this MPU region. | ||
93 | + */ | ||
94 | + if (limit >= base && | ||
95 | + ranges_overlap(base, limit - base + 1, | ||
96 | + addr_page_base, | ||
97 | + TARGET_PAGE_SIZE)) { | ||
98 | + *is_subpage = true; | ||
99 | + } | ||
100 | continue; | ||
101 | } | ||
102 | |||
103 | -- | 53 | -- |
104 | 2.17.1 | 54 | 2.20.1 |
105 | 55 | ||
106 | 56 | diff view generated by jsdifflib |
1 | From: Thomas Huth <thuth@redhat.com> | 1 | From: Marc Zyngier <maz@kernel.org> |
---|---|---|---|
2 | 2 | ||
3 | nand_init() does not only create the NAND device, it also realizes | 3 | HCR_EL2.TID3 mandates that access from EL1 to a long list of id |
4 | the device with qdev_init_nofail() already. So we must not call | 4 | registers traps to EL2, and QEMU has so far ignored this requirement. |
5 | nand_init() from an instance_init function like sl_nand_init(), | 5 | |
6 | otherwise we get superfluous NAND devices in the QOM tree after | 6 | This breaks (among other things) KVM guests that have PtrAuth enabled, |
7 | introspecting the 'sl-nand' device. So move the nand_init() to the | 7 | while the hypervisor doesn't want to expose the feature to its guest. |
8 | realize function of 'sl-nand' instead. | 8 | To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this |
9 | 9 | case), and masks out the unsupported feature. | |
10 | Signed-off-by: Thomas Huth <thuth@redhat.com> | 10 | |
11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | QEMU not honoring the trap request means that the guest observes |
12 | Message-id: 1532006134-7701-1-git-send-email-thuth@redhat.com | 12 | that the feature is present in the HW, starts using it, and dies |
13 | a horrible death when KVM injects an UNDEF, because the feature | ||
14 | *really* isn't supported. | ||
15 | |||
16 | Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set. | ||
17 | |||
18 | Note that this change does not include trapping of the MVFR | ||
19 | registers from AArch32 (they are accessed via the VMRS | ||
20 | instruction and need to be handled in a different way). | ||
21 | |||
22 | Reported-by: Will Deacon <will@kernel.org> | ||
23 | Signed-off-by: Marc Zyngier <maz@kernel.org> | ||
24 | Tested-by: Will Deacon <will@kernel.org> | ||
25 | Message-id: 20191123115618.29230-1-maz@kernel.org | ||
26 | [PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED; | ||
27 | changed names of access functions to include _tid3] | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 29 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 30 | --- |
16 | hw/arm/spitz.c | 15 +++++++++++---- | 31 | target/arm/helper.c | 76 +++++++++++++++++++++++++++++++++++++++++++++ |
17 | 1 file changed, 11 insertions(+), 4 deletions(-) | 32 | 1 file changed, 76 insertions(+) |
18 | 33 | ||
19 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | 34 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
20 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/spitz.c | 36 | --- a/target/arm/helper.c |
22 | +++ b/hw/arm/spitz.c | 37 | +++ b/target/arm/helper.c |
23 | @@ -XXX,XX +XXX,XX @@ static void sl_nand_init(Object *obj) | 38 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo predinv_reginfo[] = { |
24 | { | 39 | REGINFO_SENTINEL |
25 | SLNANDState *s = SL_NAND(obj); | 40 | }; |
26 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | 41 | |
27 | - DriveInfo *nand; | 42 | +static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
28 | 43 | + bool isread) | |
29 | s->ctl = 0; | 44 | +{ |
45 | + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { | ||
46 | + return CP_ACCESS_TRAP_EL2; | ||
47 | + } | ||
30 | + | 48 | + |
31 | + memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40); | 49 | + return CP_ACCESS_OK; |
32 | + sysbus_init_mmio(dev, &s->iomem); | ||
33 | +} | 50 | +} |
34 | + | 51 | + |
35 | +static void sl_nand_realize(DeviceState *dev, Error **errp) | 52 | +static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri, |
53 | + bool isread) | ||
36 | +{ | 54 | +{ |
37 | + SLNANDState *s = SL_NAND(dev); | 55 | + if (arm_feature(env, ARM_FEATURE_V8)) { |
38 | + DriveInfo *nand; | 56 | + return access_aa64_tid3(env, ri, isread); |
57 | + } | ||
39 | + | 58 | + |
40 | /* FIXME use a qdev drive property instead of drive_get() */ | 59 | + return CP_ACCESS_OK; |
41 | nand = drive_get(IF_MTD, 0, 0); | 60 | +} |
42 | s->nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL, | 61 | + |
43 | s->manf_id, s->chip_id); | 62 | void register_cp_regs_for_features(ARMCPU *cpu) |
44 | - | 63 | { |
45 | - memory_region_init_io(&s->iomem, obj, &sl_ops, s, "sl", 0x40); | 64 | /* Register all the coprocessor registers based on feature bits */ |
46 | - sysbus_init_mmio(dev, &s->iomem); | 65 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
47 | } | 66 | { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH, |
48 | 67 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0, | |
49 | /* Spitz Keyboard */ | 68 | .access = PL1_R, .type = ARM_CP_CONST, |
50 | @@ -XXX,XX +XXX,XX @@ static void sl_nand_class_init(ObjectClass *klass, void *data) | 69 | + .accessfn = access_aa32_tid3, |
51 | 70 | .resetvalue = cpu->id_pfr0 }, | |
52 | dc->vmsd = &vmstate_sl_nand_info; | 71 | /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know |
53 | dc->props = sl_nand_properties; | 72 | * the value of the GIC field until after we define these regs. |
54 | + dc->realize = sl_nand_realize; | 73 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
55 | /* Reason: init() method uses drive_get() */ | 74 | { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH, |
56 | dc->user_creatable = false; | 75 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, |
57 | } | 76 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
77 | + .accessfn = access_aa32_tid3, | ||
78 | .readfn = id_pfr1_read, | ||
79 | .writefn = arm_cp_write_ignore }, | ||
80 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
81 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
82 | .access = PL1_R, .type = ARM_CP_CONST, | ||
83 | + .accessfn = access_aa32_tid3, | ||
84 | .resetvalue = cpu->id_dfr0 }, | ||
85 | { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH, | ||
86 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3, | ||
87 | .access = PL1_R, .type = ARM_CP_CONST, | ||
88 | + .accessfn = access_aa32_tid3, | ||
89 | .resetvalue = cpu->id_afr0 }, | ||
90 | { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH, | ||
91 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4, | ||
92 | .access = PL1_R, .type = ARM_CP_CONST, | ||
93 | + .accessfn = access_aa32_tid3, | ||
94 | .resetvalue = cpu->id_mmfr0 }, | ||
95 | { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH, | ||
96 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5, | ||
97 | .access = PL1_R, .type = ARM_CP_CONST, | ||
98 | + .accessfn = access_aa32_tid3, | ||
99 | .resetvalue = cpu->id_mmfr1 }, | ||
100 | { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH, | ||
101 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6, | ||
102 | .access = PL1_R, .type = ARM_CP_CONST, | ||
103 | + .accessfn = access_aa32_tid3, | ||
104 | .resetvalue = cpu->id_mmfr2 }, | ||
105 | { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH, | ||
106 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7, | ||
107 | .access = PL1_R, .type = ARM_CP_CONST, | ||
108 | + .accessfn = access_aa32_tid3, | ||
109 | .resetvalue = cpu->id_mmfr3 }, | ||
110 | { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH, | ||
111 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, | ||
112 | .access = PL1_R, .type = ARM_CP_CONST, | ||
113 | + .accessfn = access_aa32_tid3, | ||
114 | .resetvalue = cpu->isar.id_isar0 }, | ||
115 | { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH, | ||
116 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1, | ||
117 | .access = PL1_R, .type = ARM_CP_CONST, | ||
118 | + .accessfn = access_aa32_tid3, | ||
119 | .resetvalue = cpu->isar.id_isar1 }, | ||
120 | { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH, | ||
121 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2, | ||
122 | .access = PL1_R, .type = ARM_CP_CONST, | ||
123 | + .accessfn = access_aa32_tid3, | ||
124 | .resetvalue = cpu->isar.id_isar2 }, | ||
125 | { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH, | ||
126 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3, | ||
127 | .access = PL1_R, .type = ARM_CP_CONST, | ||
128 | + .accessfn = access_aa32_tid3, | ||
129 | .resetvalue = cpu->isar.id_isar3 }, | ||
130 | { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH, | ||
131 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4, | ||
132 | .access = PL1_R, .type = ARM_CP_CONST, | ||
133 | + .accessfn = access_aa32_tid3, | ||
134 | .resetvalue = cpu->isar.id_isar4 }, | ||
135 | { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH, | ||
136 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5, | ||
137 | .access = PL1_R, .type = ARM_CP_CONST, | ||
138 | + .accessfn = access_aa32_tid3, | ||
139 | .resetvalue = cpu->isar.id_isar5 }, | ||
140 | { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH, | ||
141 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6, | ||
142 | .access = PL1_R, .type = ARM_CP_CONST, | ||
143 | + .accessfn = access_aa32_tid3, | ||
144 | .resetvalue = cpu->id_mmfr4 }, | ||
145 | { .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH, | ||
146 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7, | ||
147 | .access = PL1_R, .type = ARM_CP_CONST, | ||
148 | + .accessfn = access_aa32_tid3, | ||
149 | .resetvalue = cpu->isar.id_isar6 }, | ||
150 | REGINFO_SENTINEL | ||
151 | }; | ||
152 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
153 | { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
154 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0, | ||
155 | .access = PL1_R, .type = ARM_CP_NO_RAW, | ||
156 | + .accessfn = access_aa64_tid3, | ||
157 | .readfn = id_aa64pfr0_read, | ||
158 | .writefn = arm_cp_write_ignore }, | ||
159 | { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
160 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1, | ||
161 | .access = PL1_R, .type = ARM_CP_CONST, | ||
162 | + .accessfn = access_aa64_tid3, | ||
163 | .resetvalue = cpu->isar.id_aa64pfr1}, | ||
164 | { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
165 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2, | ||
166 | .access = PL1_R, .type = ARM_CP_CONST, | ||
167 | + .accessfn = access_aa64_tid3, | ||
168 | .resetvalue = 0 }, | ||
169 | { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
170 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3, | ||
171 | .access = PL1_R, .type = ARM_CP_CONST, | ||
172 | + .accessfn = access_aa64_tid3, | ||
173 | .resetvalue = 0 }, | ||
174 | { .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
175 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4, | ||
176 | .access = PL1_R, .type = ARM_CP_CONST, | ||
177 | + .accessfn = access_aa64_tid3, | ||
178 | /* At present, only SVEver == 0 is defined anyway. */ | ||
179 | .resetvalue = 0 }, | ||
180 | { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
181 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5, | ||
182 | .access = PL1_R, .type = ARM_CP_CONST, | ||
183 | + .accessfn = access_aa64_tid3, | ||
184 | .resetvalue = 0 }, | ||
185 | { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
186 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6, | ||
187 | .access = PL1_R, .type = ARM_CP_CONST, | ||
188 | + .accessfn = access_aa64_tid3, | ||
189 | .resetvalue = 0 }, | ||
190 | { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
191 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7, | ||
192 | .access = PL1_R, .type = ARM_CP_CONST, | ||
193 | + .accessfn = access_aa64_tid3, | ||
194 | .resetvalue = 0 }, | ||
195 | { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
196 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, | ||
197 | .access = PL1_R, .type = ARM_CP_CONST, | ||
198 | + .accessfn = access_aa64_tid3, | ||
199 | .resetvalue = cpu->id_aa64dfr0 }, | ||
200 | { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
201 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, | ||
202 | .access = PL1_R, .type = ARM_CP_CONST, | ||
203 | + .accessfn = access_aa64_tid3, | ||
204 | .resetvalue = cpu->id_aa64dfr1 }, | ||
205 | { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
206 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2, | ||
207 | .access = PL1_R, .type = ARM_CP_CONST, | ||
208 | + .accessfn = access_aa64_tid3, | ||
209 | .resetvalue = 0 }, | ||
210 | { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
211 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3, | ||
212 | .access = PL1_R, .type = ARM_CP_CONST, | ||
213 | + .accessfn = access_aa64_tid3, | ||
214 | .resetvalue = 0 }, | ||
215 | { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
216 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4, | ||
217 | .access = PL1_R, .type = ARM_CP_CONST, | ||
218 | + .accessfn = access_aa64_tid3, | ||
219 | .resetvalue = cpu->id_aa64afr0 }, | ||
220 | { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
221 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5, | ||
222 | .access = PL1_R, .type = ARM_CP_CONST, | ||
223 | + .accessfn = access_aa64_tid3, | ||
224 | .resetvalue = cpu->id_aa64afr1 }, | ||
225 | { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
226 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6, | ||
227 | .access = PL1_R, .type = ARM_CP_CONST, | ||
228 | + .accessfn = access_aa64_tid3, | ||
229 | .resetvalue = 0 }, | ||
230 | { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
231 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7, | ||
232 | .access = PL1_R, .type = ARM_CP_CONST, | ||
233 | + .accessfn = access_aa64_tid3, | ||
234 | .resetvalue = 0 }, | ||
235 | { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64, | ||
236 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0, | ||
237 | .access = PL1_R, .type = ARM_CP_CONST, | ||
238 | + .accessfn = access_aa64_tid3, | ||
239 | .resetvalue = cpu->isar.id_aa64isar0 }, | ||
240 | { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64, | ||
241 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1, | ||
242 | .access = PL1_R, .type = ARM_CP_CONST, | ||
243 | + .accessfn = access_aa64_tid3, | ||
244 | .resetvalue = cpu->isar.id_aa64isar1 }, | ||
245 | { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
246 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, | ||
247 | .access = PL1_R, .type = ARM_CP_CONST, | ||
248 | + .accessfn = access_aa64_tid3, | ||
249 | .resetvalue = 0 }, | ||
250 | { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
251 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, | ||
252 | .access = PL1_R, .type = ARM_CP_CONST, | ||
253 | + .accessfn = access_aa64_tid3, | ||
254 | .resetvalue = 0 }, | ||
255 | { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
256 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4, | ||
257 | .access = PL1_R, .type = ARM_CP_CONST, | ||
258 | + .accessfn = access_aa64_tid3, | ||
259 | .resetvalue = 0 }, | ||
260 | { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
261 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5, | ||
262 | .access = PL1_R, .type = ARM_CP_CONST, | ||
263 | + .accessfn = access_aa64_tid3, | ||
264 | .resetvalue = 0 }, | ||
265 | { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
266 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6, | ||
267 | .access = PL1_R, .type = ARM_CP_CONST, | ||
268 | + .accessfn = access_aa64_tid3, | ||
269 | .resetvalue = 0 }, | ||
270 | { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
271 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7, | ||
272 | .access = PL1_R, .type = ARM_CP_CONST, | ||
273 | + .accessfn = access_aa64_tid3, | ||
274 | .resetvalue = 0 }, | ||
275 | { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
276 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, | ||
277 | .access = PL1_R, .type = ARM_CP_CONST, | ||
278 | + .accessfn = access_aa64_tid3, | ||
279 | .resetvalue = cpu->isar.id_aa64mmfr0 }, | ||
280 | { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
281 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, | ||
282 | .access = PL1_R, .type = ARM_CP_CONST, | ||
283 | + .accessfn = access_aa64_tid3, | ||
284 | .resetvalue = cpu->isar.id_aa64mmfr1 }, | ||
285 | { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
286 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, | ||
287 | .access = PL1_R, .type = ARM_CP_CONST, | ||
288 | + .accessfn = access_aa64_tid3, | ||
289 | .resetvalue = 0 }, | ||
290 | { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
291 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, | ||
292 | .access = PL1_R, .type = ARM_CP_CONST, | ||
293 | + .accessfn = access_aa64_tid3, | ||
294 | .resetvalue = 0 }, | ||
295 | { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
296 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, | ||
297 | .access = PL1_R, .type = ARM_CP_CONST, | ||
298 | + .accessfn = access_aa64_tid3, | ||
299 | .resetvalue = 0 }, | ||
300 | { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
301 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5, | ||
302 | .access = PL1_R, .type = ARM_CP_CONST, | ||
303 | + .accessfn = access_aa64_tid3, | ||
304 | .resetvalue = 0 }, | ||
305 | { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
306 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6, | ||
307 | .access = PL1_R, .type = ARM_CP_CONST, | ||
308 | + .accessfn = access_aa64_tid3, | ||
309 | .resetvalue = 0 }, | ||
310 | { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
311 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7, | ||
312 | .access = PL1_R, .type = ARM_CP_CONST, | ||
313 | + .accessfn = access_aa64_tid3, | ||
314 | .resetvalue = 0 }, | ||
315 | { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, | ||
316 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, | ||
317 | .access = PL1_R, .type = ARM_CP_CONST, | ||
318 | + .accessfn = access_aa64_tid3, | ||
319 | .resetvalue = cpu->isar.mvfr0 }, | ||
320 | { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, | ||
321 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, | ||
322 | .access = PL1_R, .type = ARM_CP_CONST, | ||
323 | + .accessfn = access_aa64_tid3, | ||
324 | .resetvalue = cpu->isar.mvfr1 }, | ||
325 | { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, | ||
326 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, | ||
327 | .access = PL1_R, .type = ARM_CP_CONST, | ||
328 | + .accessfn = access_aa64_tid3, | ||
329 | .resetvalue = cpu->isar.mvfr2 }, | ||
330 | { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
331 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, | ||
332 | .access = PL1_R, .type = ARM_CP_CONST, | ||
333 | + .accessfn = access_aa64_tid3, | ||
334 | .resetvalue = 0 }, | ||
335 | { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
336 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, | ||
337 | .access = PL1_R, .type = ARM_CP_CONST, | ||
338 | + .accessfn = access_aa64_tid3, | ||
339 | .resetvalue = 0 }, | ||
340 | { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
341 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, | ||
342 | .access = PL1_R, .type = ARM_CP_CONST, | ||
343 | + .accessfn = access_aa64_tid3, | ||
344 | .resetvalue = 0 }, | ||
345 | { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
346 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6, | ||
347 | .access = PL1_R, .type = ARM_CP_CONST, | ||
348 | + .accessfn = access_aa64_tid3, | ||
349 | .resetvalue = 0 }, | ||
350 | { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64, | ||
351 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7, | ||
352 | .access = PL1_R, .type = ARM_CP_CONST, | ||
353 | + .accessfn = access_aa64_tid3, | ||
354 | .resetvalue = 0 }, | ||
355 | { .name = "PMCEID0", .state = ARM_CP_STATE_AA32, | ||
356 | .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6, | ||
58 | -- | 357 | -- |
59 | 2.17.1 | 358 | 2.20.1 |
60 | 359 | ||
61 | 360 | diff view generated by jsdifflib |