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[Qemu-devel] [PATCH for-3.0] i386: Rename enum CacheType members

Eduardo Habkost posted 1 patch 7 years, 3 months ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20180717194010.30096-1-ehabkost@redhat.com
Test checkpatch passed
Test docker-mingw@fedora passed
Test docker-quick@centos7 passed
target/i386/cpu.h |   4 +-
target/i386/cpu.c | 128 +++++++++++++++++++++++-----------------------
2 files changed, 66 insertions(+), 66 deletions(-)
[Qemu-devel] [PATCH for-3.0] i386: Rename enum CacheType members
Posted by Eduardo Habkost 7 years, 3 months ago 
Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE.
This avoids conflict with Linux asm/cachectl.h macros and fixes
build failure on mips hosts.

Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target/i386/cpu.h |   4 +-
 target/i386/cpu.c | 128 +++++++++++++++++++++++-----------------------
 2 files changed, 66 insertions(+), 66 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d90a6..194e2e6b92 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1050,8 +1050,8 @@ typedef enum TPRAccess {
 /* Cache information data structures: */
 
 enum CacheType {
-    DCACHE,
-    ICACHE,
+    DATA_CACHE,
+    INSTRUCTION_CACHE,
     UNIFIED_CACHE
 };
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e0e2f2eea1..f454d4beb3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -71,123 +71,123 @@ struct CPUID2CacheDescriptorInfo {
  * From Intel SDM Volume 2A, CPUID instruction
  */
 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
-    [0x06] = { .level = 1, .type = ICACHE,        .size =   8 * KiB,
+    [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size =   8 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x08] = { .level = 1, .type = ICACHE,        .size =  16 * KiB,
+    [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  16 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x09] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,
+    [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x0A] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,
+    [0x0A] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
                .associativity = 2,  .line_size = 32, },
-    [0x0C] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x0C] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x0D] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x0D] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x0E] = { .level = 1, .type = DCACHE,        .size =  24 * KiB,
+    [0x0E] = { .level = 1, .type = DATA_CACHE,        .size =  24 * KiB,
                .associativity = 6,  .line_size = 64, },
-    [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
+    [0x1D] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
                .associativity = 2,  .line_size = 64, },
-    [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
+    [0x21] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
                .associativity = 8,  .line_size = 64, },
     /* lines per sector is not supported cpuid2_cache_descriptor(),
     * so descriptors 0x22, 0x23 are not included
     */
-    [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x24] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 16, .line_size = 64, },
     /* lines per sector is not supported cpuid2_cache_descriptor(),
     * so descriptors 0x25, 0x20 are not included
     */
-    [0x2C] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,
+    [0x2C] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x30] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,
+    [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
+    [0x41] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
+    [0x42] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x43] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x44] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 4,  .line_size = 32, },
-    [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0x45] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 4,  .line_size = 32, },
-    [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
+    [0x46] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
                .associativity = 4,  .line_size = 64, },
-    [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
+    [0x47] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size =   3 * MiB,
+    [0x48] = { .level = 2, .type = UNIFIED_CACHE,     .size =   3 * MiB,
                .associativity = 12, .line_size = 64, },
     /* Descriptor 0x49 depends on CPU family/model, so it is not included */
-    [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size =   6 * MiB,
+    [0x4A] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
+    [0x4B] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size =  12 * MiB,
+    [0x4C] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size =  16 * MiB,
+    [0x4D] = { .level = 3, .type = UNIFIED_CACHE,     .size =  16 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size =   6 * MiB,
+    [0x4E] = { .level = 2, .type = UNIFIED_CACHE,     .size =   6 * MiB,
                .associativity = 24, .line_size = 64, },
-    [0x60] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x60] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x66] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,
+    [0x66] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x67] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x67] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x68] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,
+    [0x68] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x78] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 4,  .line_size = 64, },
     /* lines per sector is not supported cpuid2_cache_descriptor(),
     * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
     */
-    [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0x7D] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x7F] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 2,  .line_size = 64, },
-    [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x80] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
+    [0x82] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
                .associativity = 8,  .line_size = 32, },
-    [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x83] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 8,  .line_size = 32, },
-    [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x84] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 8,  .line_size = 32, },
-    [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0x85] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 8,  .line_size = 32, },
-    [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x86] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x87] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0xD0] = { .level = 3, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0xD1] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 4,  .line_size = 64, },
-    [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0xD2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 4,  .line_size = 64, },
-    [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0xD6] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0xD7] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
+    [0xD8] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
+    [0xDC] = { .level = 3, .type = UNIFIED_CACHE,     .size = 1.5 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size =   3 * MiB,
+    [0xDD] = { .level = 3, .type = UNIFIED_CACHE,     .size =   3 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size =   6 * MiB,
+    [0xDE] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0xE2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
+    [0xE3] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
+    [0xE4] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size =  12 * MiB,
+    [0xEA] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
                .associativity = 24, .line_size = 64, },
-    [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size =  18 * MiB,
+    [0xEB] = { .level = 3, .type = UNIFIED_CACHE,     .size =  18 * MiB,
                .associativity = 24, .line_size = 64, },
-    [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size =  24 * MiB,
+    [0xEC] = { .level = 3, .type = UNIFIED_CACHE,     .size =  24 * MiB,
                .associativity = 24, .line_size = 64, },
 };
 
@@ -238,10 +238,10 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
 #define CACHE_COMPLEX_IDX     (1 << 2)
 
 /* Encode CacheType for CPUID[4].EAX */
-#define CACHE_TYPE(t) (((t) == DCACHE)  ? CACHE_TYPE_D  : \
-                         ((t) == ICACHE)  ? CACHE_TYPE_I  : \
-                         ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
-                         0 /* Invalid value */)
+#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
+                       ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
+                       ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
+                       0 /* Invalid value */)
 
 
 /* Encode cache info for CPUID[4] */
@@ -538,7 +538,7 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
 
 /* L1 data cache: */
 static CPUCacheInfo legacy_l1d_cache = {
-    .type = DCACHE,
+    .type = DATA_CACHE,
     .level = 1,
     .size = 32 * KiB,
     .self_init = 1,
@@ -551,7 +551,7 @@ static CPUCacheInfo legacy_l1d_cache = {
 
 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 static CPUCacheInfo legacy_l1d_cache_amd = {
-    .type = DCACHE,
+    .type = DATA_CACHE,
     .level = 1,
     .size = 64 * KiB,
     .self_init = 1,
@@ -565,7 +565,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = {
 
 /* L1 instruction cache: */
 static CPUCacheInfo legacy_l1i_cache = {
-    .type = ICACHE,
+    .type = INSTRUCTION_CACHE,
     .level = 1,
     .size = 32 * KiB,
     .self_init = 1,
@@ -578,7 +578,7 @@ static CPUCacheInfo legacy_l1i_cache = {
 
 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 static CPUCacheInfo legacy_l1i_cache_amd = {
-    .type = ICACHE,
+    .type = INSTRUCTION_CACHE,
     .level = 1,
     .size = 64 * KiB,
     .self_init = 1,
@@ -1310,7 +1310,7 @@ struct X86CPUDefinition {
 
 static CPUCaches epyc_cache_info = {
     .l1d_cache = &(CPUCacheInfo) {
-        .type = DCACHE,
+        .type = DATA_CACHE,
         .level = 1,
         .size = 32 * KiB,
         .line_size = 64,
@@ -1322,7 +1322,7 @@ static CPUCaches epyc_cache_info = {
         .no_invd_sharing = true,
     },
     .l1i_cache = &(CPUCacheInfo) {
-        .type = ICACHE,
+        .type = INSTRUCTION_CACHE,
         .level = 1,
         .size = 64 * KiB,
         .line_size = 64,
-- 
2.18.0.rc1.1.g3f1ff2140
Re: [Qemu-devel] [PATCH for-3.0] i386: Rename enum CacheType members
Posted by Philippe Mathieu-Daudé 7 years, 3 months ago 
On 07/17/2018 04:40 PM, Eduardo Habkost wrote:
> Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE.

Effective, thanks.

> This avoids conflict with Linux asm/cachectl.h macros and fixes
> build failure on mips hosts.
> 
> Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/i386/cpu.h |   4 +-
>  target/i386/cpu.c | 128 +++++++++++++++++++++++-----------------------
>  2 files changed, 66 insertions(+), 66 deletions(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 2c5a0d90a6..194e2e6b92 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1050,8 +1050,8 @@ typedef enum TPRAccess {
>  /* Cache information data structures: */
>  
>  enum CacheType {
> -    DCACHE,
> -    ICACHE,
> +    DATA_CACHE,
> +    INSTRUCTION_CACHE,
>      UNIFIED_CACHE
>  };
>  
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index e0e2f2eea1..f454d4beb3 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -71,123 +71,123 @@ struct CPUID2CacheDescriptorInfo {
>   * From Intel SDM Volume 2A, CPUID instruction
>   */
>  struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
> -    [0x06] = { .level = 1, .type = ICACHE,        .size =   8 * KiB,
> +    [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size =   8 * KiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x08] = { .level = 1, .type = ICACHE,        .size =  16 * KiB,
> +    [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  16 * KiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x09] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,
> +    [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x0A] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,
> +    [0x0A] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
>                 .associativity = 2,  .line_size = 32, },
> -    [0x0C] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
> +    [0x0C] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x0D] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
> +    [0x0D] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x0E] = { .level = 1, .type = DCACHE,        .size =  24 * KiB,
> +    [0x0E] = { .level = 1, .type = DATA_CACHE,        .size =  24 * KiB,
>                 .associativity = 6,  .line_size = 64, },
> -    [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
> +    [0x1D] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
>                 .associativity = 2,  .line_size = 64, },
> -    [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
> +    [0x21] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
>                 .associativity = 8,  .line_size = 64, },
>      /* lines per sector is not supported cpuid2_cache_descriptor(),
>      * so descriptors 0x22, 0x23 are not included
>      */
> -    [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0x24] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 16, .line_size = 64, },
>      /* lines per sector is not supported cpuid2_cache_descriptor(),
>      * so descriptors 0x25, 0x20 are not included
>      */
> -    [0x2C] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,
> +    [0x2C] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0x30] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,
> +    [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
> +    [0x41] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
> +    [0x42] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
> +    [0x43] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0x44] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
> +    [0x45] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
>                 .associativity = 4,  .line_size = 32, },
> -    [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
> +    [0x46] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
> +    [0x47] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size =   3 * MiB,
> +    [0x48] = { .level = 2, .type = UNIFIED_CACHE,     .size =   3 * MiB,
>                 .associativity = 12, .line_size = 64, },
>      /* Descriptor 0x49 depends on CPU family/model, so it is not included */
> -    [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size =   6 * MiB,
> +    [0x4A] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
>                 .associativity = 12, .line_size = 64, },
> -    [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
> +    [0x4B] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
>                 .associativity = 16, .line_size = 64, },
> -    [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size =  12 * MiB,
> +    [0x4C] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
>                 .associativity = 12, .line_size = 64, },
> -    [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size =  16 * MiB,
> +    [0x4D] = { .level = 3, .type = UNIFIED_CACHE,     .size =  16 * MiB,
>                 .associativity = 16, .line_size = 64, },
> -    [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size =   6 * MiB,
> +    [0x4E] = { .level = 2, .type = UNIFIED_CACHE,     .size =   6 * MiB,
>                 .associativity = 24, .line_size = 64, },
> -    [0x60] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
> +    [0x60] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0x66] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,
> +    [0x66] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x67] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
> +    [0x67] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x68] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,
> +    [0x68] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0x78] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 4,  .line_size = 64, },
>      /* lines per sector is not supported cpuid2_cache_descriptor(),
>      * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
>      */
> -    [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
> +    [0x7D] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
> +    [0x7F] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
>                 .associativity = 2,  .line_size = 64, },
> -    [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
> +    [0x80] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
> +    [0x82] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
>                 .associativity = 8,  .line_size = 32, },
> -    [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
> +    [0x83] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
>                 .associativity = 8,  .line_size = 32, },
> -    [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0x84] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 8,  .line_size = 32, },
> -    [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
> +    [0x85] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
>                 .associativity = 8,  .line_size = 32, },
> -    [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
> +    [0x86] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0x87] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
> +    [0xD0] = { .level = 3, .type = UNIFIED_CACHE,     .size = 512 * KiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0xD1] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
> +    [0xD2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
>                 .associativity = 4,  .line_size = 64, },
> -    [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size =   1 * MiB,
> +    [0xD6] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
> +    [0xD7] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
> +    [0xD8] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
>                 .associativity = 8,  .line_size = 64, },
> -    [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
> +    [0xDC] = { .level = 3, .type = UNIFIED_CACHE,     .size = 1.5 * MiB,
>                 .associativity = 12, .line_size = 64, },
> -    [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size =   3 * MiB,
> +    [0xDD] = { .level = 3, .type = UNIFIED_CACHE,     .size =   3 * MiB,
>                 .associativity = 12, .line_size = 64, },
> -    [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size =   6 * MiB,
> +    [0xDE] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
>                 .associativity = 12, .line_size = 64, },
> -    [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
> +    [0xE2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
>                 .associativity = 16, .line_size = 64, },
> -    [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
> +    [0xE3] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
>                 .associativity = 16, .line_size = 64, },
> -    [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
> +    [0xE4] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
>                 .associativity = 16, .line_size = 64, },
> -    [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size =  12 * MiB,
> +    [0xEA] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
>                 .associativity = 24, .line_size = 64, },
> -    [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size =  18 * MiB,
> +    [0xEB] = { .level = 3, .type = UNIFIED_CACHE,     .size =  18 * MiB,
>                 .associativity = 24, .line_size = 64, },
> -    [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size =  24 * MiB,
> +    [0xEC] = { .level = 3, .type = UNIFIED_CACHE,     .size =  24 * MiB,
>                 .associativity = 24, .line_size = 64, },
>  };
>  
> @@ -238,10 +238,10 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
>  #define CACHE_COMPLEX_IDX     (1 << 2)
>  
>  /* Encode CacheType for CPUID[4].EAX */
> -#define CACHE_TYPE(t) (((t) == DCACHE)  ? CACHE_TYPE_D  : \
> -                         ((t) == ICACHE)  ? CACHE_TYPE_I  : \
> -                         ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
> -                         0 /* Invalid value */)
> +#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
> +                       ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
> +                       ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
> +                       0 /* Invalid value */)
>  
>  
>  /* Encode cache info for CPUID[4] */
> @@ -538,7 +538,7 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
>  
>  /* L1 data cache: */
>  static CPUCacheInfo legacy_l1d_cache = {
> -    .type = DCACHE,
> +    .type = DATA_CACHE,
>      .level = 1,
>      .size = 32 * KiB,
>      .self_init = 1,
> @@ -551,7 +551,7 @@ static CPUCacheInfo legacy_l1d_cache = {
>  
>  /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
>  static CPUCacheInfo legacy_l1d_cache_amd = {
> -    .type = DCACHE,
> +    .type = DATA_CACHE,
>      .level = 1,
>      .size = 64 * KiB,
>      .self_init = 1,
> @@ -565,7 +565,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = {
>  
>  /* L1 instruction cache: */
>  static CPUCacheInfo legacy_l1i_cache = {
> -    .type = ICACHE,
> +    .type = INSTRUCTION_CACHE,
>      .level = 1,
>      .size = 32 * KiB,
>      .self_init = 1,
> @@ -578,7 +578,7 @@ static CPUCacheInfo legacy_l1i_cache = {
>  
>  /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
>  static CPUCacheInfo legacy_l1i_cache_amd = {
> -    .type = ICACHE,
> +    .type = INSTRUCTION_CACHE,
>      .level = 1,
>      .size = 64 * KiB,
>      .self_init = 1,
> @@ -1310,7 +1310,7 @@ struct X86CPUDefinition {
>  
>  static CPUCaches epyc_cache_info = {
>      .l1d_cache = &(CPUCacheInfo) {
> -        .type = DCACHE,
> +        .type = DATA_CACHE,
>          .level = 1,
>          .size = 32 * KiB,
>          .line_size = 64,
> @@ -1322,7 +1322,7 @@ static CPUCaches epyc_cache_info = {
>          .no_invd_sharing = true,
>      },
>      .l1i_cache = &(CPUCacheInfo) {
> -        .type = ICACHE,
> +        .type = INSTRUCTION_CACHE,
>          .level = 1,
>          .size = 64 * KiB,
>          .line_size = 64,
>
Re: [Qemu-devel] [PATCH for-3.0] i386: Rename enum CacheType members
Posted by Aleksandar Markovic 7 years, 3 months ago 
On 07/17/2018 04:40 PM, Eduardo Habkost wrote:
> Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE.
>
> This avoids conflict with Linux asm/cachectl.h macros and fixes
> build failure on mips hosts.
>
> Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

Acked-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Re: [Qemu-devel] [PATCH for-3.0] i386: Rename enum CacheType members
Posted by Moger, Babu 7 years, 3 months ago 
> -----Original Message-----
> From: Aleksandar Markovic [mailto:amarkovic@wavecomp.com]
> Sent: Wednesday, July 18, 2018 8:35 AM
> To: Philippe Mathieu-Daudé <f4bug@amsat.org>; Eduardo Habkost
> <ehabkost@redhat.com>; qemu-devel@nongnu.org
> Cc: Moger, Babu <Babu.Moger@amd.com>; Paolo Bonzini
> <pbonzini@redhat.com>; Aurelien Jarno <aurelien@aurel32.net>; Richard
> Henderson <rth@twiddle.net>
> Subject: Re: [PATCH for-3.0] i386: Rename enum CacheType members
> 
> 
> On 07/17/2018 04:40 PM, Eduardo Habkost wrote:
> > Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE.
> >
> > This avoids conflict with Linux asm/cachectl.h macros and fixes
> > build failure on mips hosts.
> >
> > Reported-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> 
> Acked-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
Reviewed-by: Babu Moger <babu.moger@amd.com>

Patchew 2.1-devel-b67e4c2

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