Series comparison

-[Qemu-devel] [PULL 0/8] target-arm queue
+[PULL 00/30] target-arm queue
-target-arm queue: a smallish set of patches for rc1 tomorrow.
+The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:
 I've included the tcg patches because RTH has no others that
 would merit a pullreq.
-I haven't included Thomas Huth's 17-patch set to deal with
+  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)
 the introspection crashes, to give that a little more time
 on-list for review.
 thanks
 -- PMM
 The following changes since commit 102ad0a80f5110483efd06877c29c4236be267f9:
   Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-07-16' into staging (2018-07-16 15:34:38 +0100)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180716
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216
-for you to fetch changes up to 3474c98a2a2afcefa7c665f02ad2bed2a43ab0f7:
+for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:
-  accel/tcg: Assert that tlb fill gave us a valid TLB entry (2018-07-16 17:26:01 +0100)
+  tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * accel/tcg: Use correct test when looking in victim TLB for code
+ * Some mostly M-profile-related code cleanups
- * bcm2835_aux: Swap RX and TX interrupt assignments
+ * avocado: Retire the boot_linux.py AArch64 TCG tests
- * hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false
+ * hw/arm/smmuv3: Add GBPA register
- * hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
+ * arm/virt: don't try to spell out the accelerator
- * hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()
+ * hw/arm: Attach PSPI module to NPCM7XX SoC
- * aspeed: Implement write-1-{set, clear} for AST2500 strapping
+ * Some cleanup/refactoring patches aiming towards
- * target/arm: Fix LD1W and LDFF1W (scalar plus vector)
+   allowing building Arm targets without CONFIG_TCG
 ----------------------------------------------------------------
-Andrew Jeffery (1):
+Alex Bennée (1):
-      aspeed: Implement write-1-{set, clear} for AST2500 strapping
+      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
-Guenter Roeck (1):
+Claudio Fontana (3):
-      bcm2835_aux: Swap RX and TX interrupt assignments
+      target/arm: rename handle_semihosting to tcg_handle_semihosting
       target/arm: wrap psci call with tcg_enabled
       target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
-Peter Maydell (4):
+Cornelia Huck (1):
-      hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()
+      arm/virt: don't try to spell out the accelerator
       hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
       accel/tcg: Use correct test when looking in victim TLB for code
       accel/tcg: Assert that tlb fill gave us a valid TLB entry
-Richard Henderson (1):
+Fabiano Rosas (7):
-      target/arm: Fix LD1W and LDFF1W (scalar plus vector)
+      target/arm: Move PC alignment check
       target/arm: Move cpregs code out of cpu.h
       tests/avocado: Skip tests that require a missing accelerator
       tests/avocado: Tag TCG tests with accel:tcg
       target/arm: Use "max" as default cpu for the virt machine with KVM
       tests/qtest: arm-cpu-features: Match tests to required accelerators
       tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
-Thomas Huth (1):
+Hao Wu (3):
-      hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false
+      MAINTAINERS: Add myself to maintainers and remove Havard
       hw/ssi: Add Nuvoton PSPI Module
       hw/arm: Attach PSPI module to NPCM7XX SoC
- include/hw/misc/aspeed_scu.h |  2 ++
+Jean-Philippe Brucker (2):
- accel/tcg/cputlb.c           |  6 +++---
+      hw/arm/smmu-common: Support 64-bit addresses
- hw/arm/bcm2836.c             |  2 ++
+      hw/arm/smmu-common: Fix TTB1 handling
  hw/char/bcm2835_aux.c        |  4 ++--
  hw/intc/arm_gic.c            | 22 +++++++++++++++++++---
  hw/misc/aspeed_scu.c         | 19 +++++++++++++++++--
  target/arm/sve_helper.c      |  4 ++--
 files changed, 47 insertions(+), 12 deletions(-)
+Mostafa Saleh (1):
+      hw/arm/smmuv3: Add GBPA register
+Philippe Mathieu-Daudé (12):
+      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
+      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
+      target/arm: Constify ID_PFR1 on user emulation
+      target/arm: Convert CPUARMState::eabi to boolean
+      target/arm: Avoid resetting CPUARMState::eabi field
+      target/arm: Restrict CPUARMState::gicv3state to sysemu
+      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
+      target/arm: Restrict CPUARMState::nvic to sysemu
+      target/arm: Store CPUARMState::nvic as NVICState*
+      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+ MAINTAINERS                            |   8 +-
+ docs/system/arm/nuvoton.rst            |   2 +-
+ hw/arm/smmuv3-internal.h               |   7 +
+ include/hw/arm/npcm7xx.h               |   2 +
+ include/hw/arm/smmu-common.h           |   2 -
+ include/hw/arm/smmuv3.h                |   1 +
+ include/hw/intc/armv7m_nvic.h          | 128 +++++++++++++++++-
+ include/hw/ssi/npcm_pspi.h             |  53 ++++++++
+ linux-user/user-internals.h            |   2 +-
+ target/arm/cpregs.h                    |  98 ++++++++++++++
+ target/arm/cpu.h                       | 228 ++-------------------------------
+ target/arm/internals.h                 |  14 --
+ hw/arm/npcm7xx.c                       |  25 +++-
+ hw/arm/smmu-common.c                   |   4 +-
+ hw/arm/smmuv3.c                        |  43 ++++++-
+ hw/arm/virt.c                          |  10 +-
+ hw/intc/armv7m_nvic.c                  |  38 ++----
+ hw/ssi/npcm_pspi.c                     | 221 ++++++++++++++++++++++++++++++++
+ linux-user/arm/cpu_loop.c              |   4 +-
+ target/arm/cpu.c                       |   5 +-
+ target/arm/cpu_tcg.c                   |   3 +
+ target/arm/helper.c                    |  31 +++--
+ target/arm/m_helper.c                  |  86 +++++++------
+ target/arm/machine.c                   |  18 +--
+ tests/qtest/arm-cpu-features.c         |  28 ++--
+ hw/arm/Kconfig                         |   1 +
+ hw/ssi/meson.build                     |   2 +-
+ hw/ssi/trace-events                    |   5 +
+ tests/avocado/avocado_qemu/__init__.py |   4 +
+ tests/avocado/boot_linux.py            |  48 ++-----
+ tests/avocado/boot_linux_console.py    |   1 +
+ tests/avocado/machine_aarch64_virt.py  |  63 ++++++++-
+ tests/avocado/reverse_debugging.py     |   8 ++
+ tests/qtest/meson.build                |   4 +-
+files changed, 798 insertions(+), 399 deletions(-)
+ create mode 100644 include/hw/ssi/npcm_pspi.h
+ create mode 100644 hw/ssi/npcm_pspi.c

-New patch
+[PULL 01/30] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
+similarly to automatic conversion from commit 8063396bf3
+("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-2-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/intc/armv7m_nvic.h | 5 +----
+file changed, 1 insertion(+), 4 deletions(-)
+diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/intc/armv7m_nvic.h
++++ b/include/hw/intc/armv7m_nvic.h
+@@ -XXX,XX +XXX,XX @@
+ #include "qom/object.h"
+ #define TYPE_NVIC "armv7m_nvic"
+-
+-typedef struct NVICState NVICState;
+-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
+-                         TYPE_NVIC)
++OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
+ /* Highest permitted number of exceptions (architectural limit) */
+ #define NVIC_MAX_VECTORS 512
+--
+.34.1

-New patch
+[PULL 02/30] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-3-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/m_helper.c | 11 ++++++++---
+file changed, 8 insertions(+), 3 deletions(-)
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return 0;
+ }
+-#else
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    return ARMMMUIdx_MUser;
++}
++
++#else /* !CONFIG_USER_ONLY */
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-#endif /* !CONFIG_USER_ONLY */
+-
+ ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                               bool secstate, bool priv, bool negpri)
+ {
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+ }
++
++#endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 03/30] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
+are only used for system emulation in m_helper.c.
+Move the definitions to avoid prototype forward declarations.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-4-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/internals.h | 14 --------
+ target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
+files changed, 37 insertions(+), 51 deletions(-)
+diff --git a/target/arm/internals.h b/target/arm/internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
++++ b/target/arm/internals.h
+@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
+ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
+-/*
+- * Return the MMU index for a v7M CPU with all relevant information
+- * manually specified.
+- */
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+-                              bool secstate, bool priv, bool negpri);
+-
+-/*
+- * Return the MMU index for a v7M CPU in the specified security and
+- * privilege state.
+- */
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+-                                                bool secstate, bool priv);
+-
+ /* Return the MMU index for a v7M CPU in the specified security state */
+ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
+diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/m_helper.c
++++ b/target/arm/m_helper.c
+@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+ #else /* !CONFIG_USER_ONLY */
++static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
++                                     bool secstate, bool priv, bool negpri)
++{
++    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
++
++    if (priv) {
++        mmu_idx |= ARM_MMU_IDX_M_PRIV;
++    }
++
++    if (negpri) {
++        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
++    }
++
++    if (secstate) {
++        mmu_idx |= ARM_MMU_IDX_M_S;
++    }
++
++    return mmu_idx;
++}
++
++static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
++                                                       bool secstate, bool priv)
++{
++    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
++
++    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
++}
++
++/* Return the MMU index for a v7M CPU in the specified security state */
++ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
++{
++    bool priv = arm_v7m_is_handler_mode(env) ||
++        !(env->v7m.control[secstate] & 1);
++
++    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
++}
++
+ /*
+  * What kind of stack write are we doing? This affects how exceptions
+  * generated during the stacking are treated.
+@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
+     return tt_resp;
+ }
+-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+-                              bool secstate, bool priv, bool negpri)
+-{
+-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+-
+-    if (priv) {
+-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+-    }
+-
+-    if (negpri) {
+-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+-    }
+-
+-    if (secstate) {
+-        mmu_idx |= ARM_MMU_IDX_M_S;
+-    }
+-
+-    return mmu_idx;
+-}
+-
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+-                                                bool secstate, bool priv)
+-{
+-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+-
+-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+-}
+-
+-/* Return the MMU index for a v7M CPU in the specified security state */
+-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+-{
+-    bool priv = arm_v7m_is_handler_mode(env) ||
+-        !(env->v7m.control[secstate] & 1);
+-
+-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+-}
+-
+ #endif /* !CONFIG_USER_ONLY */
+--
+.34.1

-[Qemu-devel] [PULL 5/8] hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false
+[PULL 04/30] target/arm: Constify ID_PFR1 on user emulation
-From: Thomas Huth <thuth@redhat.com>
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
-These devices are currently causing some problems when a user is trying
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-to hot-plug or introspect them during runtime. Since these devices can
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-not be instantiated by the user at all (they need to be wired up in code
+Message-id: 20230206223502.25122-5-philmd@linaro.org
 instead), we should mark them with user_creatable = false anyway, then we
 avoid at least the crashes with the hot-plugging. The introspection problem
 will be handled by a separate patch.
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Message-id: 1531415537-26037-1-git-send-email-thuth@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Markus Armbruster <armbru@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/bcm2836.c | 2 ++
+ target/arm/helper.c | 12 ++++++++++--
-file changed, 2 insertions(+)
+file changed, 10 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/bcm2836.c
+--- a/target/arm/helper.c
-+++ b/hw/arm/bcm2836.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void bcm283x_class_init(ObjectClass *oc, void *data)
+@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
-     bc->info = data;
+     }
      dc->realize = bcm2836_realize;
      dc->props = bcm2836_props;
 +    /* Reason: Must be wired up in code (see raspi_init() function) */
 +    dc->user_creatable = false;
  }
- static const TypeInfo bcm283x_type_info = {
++#ifndef CONFIG_USER_ONLY
  /*
   * We don't know until after realize whether there's a GICv3
   * attached, and that is what registers the gicv3 sysregs.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
      return pfr1;
  }
 -#ifndef CONFIG_USER_ONLY
  static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
                .access = PL1_R, .type = ARM_CP_NO_RAW,
                .accessfn = access_aa32_tid3,
 +#ifdef CONFIG_USER_ONLY
 +              .type = ARM_CP_CONST,
 +              .resetvalue = cpu->isar.id_pfr1,
 +#else
 +              .type = ARM_CP_NO_RAW,
 +              .accessfn = access_aa32_tid3,
                .readfn = id_pfr1_read,
 -              .writefn = arm_cp_write_ignore },
 +              .writefn = arm_cp_write_ignore
 +#endif
 +            },
              { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
                .access = PL1_R, .type = ARM_CP_CONST,
 --
-.17.1
+.34.1

-New patch
+[PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-6-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ linux-user/user-internals.h | 2 +-
+ target/arm/cpu.h            | 2 +-
+ linux-user/arm/cpu_loop.c   | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/user-internals.h
++++ b/linux-user/user-internals.h
+@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
+ #ifdef TARGET_ARM
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
+ {
+-    return cpu_env->eabi == 1;
++    return cpu_env->eabi;
+ }
+ #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
+ static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+ #if defined(CONFIG_USER_ONLY)
+     /* For usermode syscall translation.  */
+-    int eabi;
++    bool eabi;
+ #endif
+     struct CPUBreakpoint *cpu_breakpoint[16];
+diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
+index XXXXXXX..XXXXXXX 100644
+--- a/linux-user/arm/cpu_loop.c
++++ b/linux-user/arm/cpu_loop.c
+@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+             break;
+         case EXCP_SWI:
+             {
+-                env->eabi = 1;
++                env->eabi = true;
+                 /* system call */
+                 if (env->thumb) {
+                     /* Thumb is always EABI style with syscall number in r7 */
+@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
+                          * > 0xfffff and are handled below as out-of-range.
+                          */
+                         n ^= ARM_SYSCALL_BASE;
+-                        env->eabi = 0;
++                        env->eabi = false;
+                     }
+                 }
+--
+.34.1

-New patch
+[PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Although the 'eabi' field is only used in user emulation where
+CPU reset doesn't occur, it doesn't belong to the area to reset.
+Move it after the 'end_reset_fields' for consistency.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-7-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 9 ++++-----
+file changed, 4 insertions(+), 5 deletions(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     ARMVectorReg zarray[ARM_MAX_VQ * 16];
+ #endif
+-#if defined(CONFIG_USER_ONLY)
+-    /* For usermode syscall translation.  */
+-    bool eabi;
+-#endif
+-
+     struct CPUBreakpoint *cpu_breakpoint[16];
+     struct CPUWatchpoint *cpu_watchpoint[16];
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
++#if defined(CONFIG_USER_ONLY)
++    /* For usermode syscall translation.  */
++    bool eabi;
++#endif /* CONFIG_USER_ONLY */
+ #ifdef TARGET_TAGGED_ADDRESSES
+     /* Linux syscall tagged address support */
+--
+.34.1

-New patch
+[PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-8-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     void *nvic;
+     const struct arm_boot_info *boot_info;
++#if !defined(CONFIG_USER_ONLY)
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+-#if defined(CONFIG_USER_ONLY)
++#else /* CONFIG_USER_ONLY */
+     /* For usermode syscall translation.  */
+     bool eabi;
+ #endif /* CONFIG_USER_ONLY */
+--
+.34.1

-New patch
+[PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230206223502.25122-9-philmd@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
+     } sau;
+     void *nvic;
+-    const struct arm_boot_info *boot_info;
+ #if !defined(CONFIG_USER_ONLY)
++    const struct arm_boot_info *boot_info;
+     /* Store GICv3CPUState to access from this struct */
+     void *gicv3state;
+ #else /* CONFIG_USER_ONLY */
+--
+.34.1

-[Qemu-devel] [PULL 7/8] accel/tcg: Use correct test when looking in victim TLB for code
+[PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu
-In get_page_addr_code(), we were incorrectly looking in the victim
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 TLB for an entry which matched the target address for reads, not
 for code accesses. This meant that we could hit on a victim TLB
 entry that indicated that the address was readable but not
 executable, and incorrectly bypass the call to tlb_fill() which
 should generate the guest MMU exception. Fix this bug.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230206223502.25122-10-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180713141636.18665-2-peter.maydell@linaro.org
 ---
- accel/tcg/cputlb.c | 2 +-
+ target/arm/cpu.h | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/target/arm/cpu.h
-+++ b/accel/tcg/cputlb.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
+@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
-     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+         uint32_t ctrl;
-     mmu_idx = cpu_mmu_index(env, true);
+     } sau;
-     if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))) {
--        if (!VICTIM_TLB_HIT(addr_read, addr)) {
+-    void *nvic;
-+        if (!VICTIM_TLB_HIT(addr_code, addr)) {
+ #if !defined(CONFIG_USER_ONLY)
-             tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
++    void *nvic;
-         }
+     const struct arm_boot_info *boot_info;
-     }
+     /* Store GICv3CPUState to access from this struct */
      void *gicv3state;
 --
-.17.1
+.34.1

-New patch
+[PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 There is no point in using a void pointer to access the NVIC.
 Use the real type to avoid casting it while debugging.
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230206223502.25122-11-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
  hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
  target/arm/cpu.c      |  1 +
  target/arm/m_helper.c |  2 +-
 files changed, 39 insertions(+), 48 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
  typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 +typedef struct NVICState NVICState;
 +
  typedef struct CPUArchState {
      /* Regs for current mode.  */
      uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
      } sau;
  #if !defined(CONFIG_USER_ONLY)
 -    void *nvic;
 +    NVICState *nvic;
      const struct arm_boot_info *boot_info;
      /* Store GICv3CPUState to access from this struct */
      void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
  /* Interface between CPU and Interrupt controller.  */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(void *opaque);
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
  #else
 -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
      return true;
  }
  #endif
  /**
   * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
   * exceptions (exceptions generated in the course of trying to take
   * a different exception).
   */
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
   * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
   * generated in the course of lazy stacking of FP registers.
   */
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_pending_irq_info: return highest priority pending
   *    exception, and whether it targets Secure state
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @pirq: set to pending exception number
   * @ptargets_secure: set to whether pending exception targets Secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
   * to true if the current highest priority pending exception should
   * be taken to Secure state, false for NS.
   */
 -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                        bool *ptargets_secure);
  /**
   * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Move the current highest priority pending exception from the pending
   * state to the active state, and update v7m.exception to indicate that
   * it is the exception currently being handled.
   */
 -void armv7m_nvic_acknowledge_irq(void *opaque);
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
  /**
   * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to complete
   * @secure: true if this exception was secure
   *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
   *           0 if there is still an irq active after this one was completed
   * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
   */
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @irq: the exception number to mark pending
   * @secure: false for non-banked exceptions or for the nonsecure
   * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
   * interrupt the current execution priority. This controls whether the
   * RDY bit for it in the FPCCR is set.
   */
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
  /**
   * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @opaque: the NVIC
 + * @s: the NVIC
   *
   * Returns: the raw execution priority as defined by the v8M architecture.
   * This is the execution priority minus the effects of AIRCR.PRIS,
   * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
   * (v8M ARM ARM I_PKLD.)
   */
 -int armv7m_nvic_raw_execution_priority(void *opaque);
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
  /**
   * armv7m_nvic_neg_prio_requested: return true if the requested execution
   * priority is negative for the specified security state.
 - * @opaque: the NVIC
 + * @s: the NVIC
   * @secure: the security state to test
   * This corresponds to the pseudocode IsReqExecPriNeg().
   */
  #ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
  #else
 -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      return false;
  }
 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
      return MIN(running, s->exception_prio);
  }
 -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
  {
      /* Return true if the requested execution priority is negative
       * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
       * mean we don't allow FAULTMASK_NS to actually make the execution
       * priority negative). Compare pseudocode IsReqExcPriNeg().
       */
 -    NVICState *s = opaque;
 -
      if (s->cpu->env.v7m.faultmask[secure]) {
          return true;
      }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      return false;
  }
 -bool armv7m_nvic_can_take_pending_exception(void *opaque)
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return nvic_exec_prio(s) > nvic_pending_prio(s);
  }
 -int armv7m_nvic_raw_execution_priority(void *opaque)
 +int armv7m_nvic_raw_execution_priority(NVICState *s)
  {
 -    NVICState *s = opaque;
 -
      return s->exception_prio;
  }
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
   * if @secure is true and @irq does not specify one of the fixed set
   * of architecturally banked exceptions.
   */
 -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
 +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec;
      assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
      }
  }
 -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
 +    do_armv7m_nvic_set_pending(s, irq, secure, false);
  }
 -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
  {
 -    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
 +    do_armv7m_nvic_set_pending(s, irq, secure, true);
  }
 -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
  {
      /*
       * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
       * whether we should escalate depends on the saved context
       * in the FPCCR register, not on the current state of the CPU/NVIC.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
  }
  /* Make pending IRQ active.  */
 -void armv7m_nvic_acknowledge_irq(void *opaque)
 +void armv7m_nvic_acknowledge_irq(NVICState *s)
  {
 -    NVICState *s = (NVICState *)opaque;
      CPUARMState *env = &s->cpu->env;
      const int pending = s->vectpending;
      const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
          exc_targets_secure(s, s->vectpending);
  }
 -void armv7m_nvic_get_pending_irq_info(void *opaque,
 +void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                        int *pirq, bool *ptargets_secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      const int pending = s->vectpending;
      bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
      *pirq = pending;
  }
 -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
  {
 -    NVICState *s = (NVICState *)opaque;
      VecInfo *vec = NULL;
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
      return ret;
  }
 -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
  {
      /*
       * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
       * for non-banked exceptions secure is always false; for banked exceptions
       * it indicates which of the exceptions is required.
       */
 -    NVICState *s = (NVICState *)opaque;
      bool banked = exc_is_banked(irq);
      VecInfo *vec;
      int running = nvic_exec_prio(s);
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#include "hw/intc/armv7m_nvic.h"
  #endif
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
       * that we will need later in order to do lazy FP reg stacking.
       */
      bool is_secure = env->v7m.secure;
 -    void *nvic = env->nvic;
 +    NVICState *nvic = env->nvic;
      /*
       * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
       * are banked and we want to update the bit in the bank for the
 --
 .34.1

-New patch
+[PULL 11/30] target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
 While dozens of files include "cpu.h", only 3 files require
 these NVIC helper declarations.
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230206223502.25122-12-philmd@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
  target/arm/cpu.h              | 123 ----------------------------------
  target/arm/cpu.c              |   4 +-
  target/arm/cpu_tcg.c          |   3 +
  target/arm/m_helper.c         |   3 +
 files changed, 132 insertions(+), 124 deletions(-)
 diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/intc/armv7m_nvic.h
 +++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
      qemu_irq sysresetreq;
  };
 +/* Interface between CPU and Interrupt controller.  */
 +/**
 + * armv7m_nvic_set_pending: mark the specified exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Marks the specified exception as pending. Note that we will assert()
 + * if @secure is true and @irq does not specify one of the fixed set
 + * of architecturally banked exceptions.
 + */
 +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for derived
 + * exceptions (exceptions generated in the course of trying to take
 + * a different exception).
 + */
 +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 + * generated in the course of lazy stacking of FP registers.
 + */
 +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_pending_irq_info: return highest priority pending
 + *    exception, and whether it targets Secure state
 + * @s: the NVIC
 + * @pirq: set to pending exception number
 + * @ptargets_secure: set to whether pending exception targets Secure
 + *
 + * This function writes the number of the highest priority pending
 + * exception (the one which would be made active by
 + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 + * to true if the current highest priority pending exception should
 + * be taken to Secure state, false for NS.
 + */
 +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 +                                      bool *ptargets_secure);
 +/**
 + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 + * @s: the NVIC
 + *
 + * Move the current highest priority pending exception from the pending
 + * state to the active state, and update v7m.exception to indicate that
 + * it is the exception currently being handled.
 + */
 +void armv7m_nvic_acknowledge_irq(NVICState *s);
 +/**
 + * armv7m_nvic_complete_irq: complete specified interrupt or exception
 + * @s: the NVIC
 + * @irq: the exception number to complete
 + * @secure: true if this exception was secure
 + *
 + * Returns: -1 if the irq was not active
 + *           1 if completing this irq brought us back to base (no active irqs)
 + *           0 if there is still an irq active after this one was completed
 + * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 + */
 +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 + * @s: the NVIC
 + * @irq: the exception number to mark pending
 + * @secure: false for non-banked exceptions or for the nonsecure
 + * version of a banked exception, true for the secure version of a banked
 + * exception.
 + *
 + * Return whether an exception is "ready", i.e. whether the exception is
 + * enabled and is configured at a priority which would allow it to
 + * interrupt the current execution priority. This controls whether the
 + * RDY bit for it in the FPCCR is set.
 + */
 +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 +/**
 + * armv7m_nvic_raw_execution_priority: return the raw execution priority
 + * @s: the NVIC
 + *
 + * Returns: the raw execution priority as defined by the v8M architecture.
 + * This is the execution priority minus the effects of AIRCR.PRIS,
 + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 + * (v8M ARM ARM I_PKLD.)
 + */
 +int armv7m_nvic_raw_execution_priority(NVICState *s);
 +/**
 + * armv7m_nvic_neg_prio_requested: return true if the requested execution
 + * priority is negative for the specified security state.
 + * @s: the NVIC
 + * @secure: the security state to test
 + * This corresponds to the pseudocode IsReqExecPriNeg().
 + */
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 +#else
 +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 +{
 +    return false;
 +}
 +#endif
 +#ifndef CONFIG_USER_ONLY
 +bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 +#else
 +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 +{
 +    return true;
 +}
 +#endif
 +
  #endif
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface between CPU and Interrupt controller.  */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 -#else
 -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 -{
 -    return true;
 -}
 -#endif
 -/**
 - * armv7m_nvic_set_pending: mark the specified exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Marks the specified exception as pending. Note that we will assert()
 - * if @secure is true and @irq does not specify one of the fixed set
 - * of architecturally banked exceptions.
 - */
 -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_derived: mark this derived exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for derived
 - * exceptions (exceptions generated in the course of trying to take
 - * a different exception).
 - */
 -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
 - * generated in the course of lazy stacking of FP registers.
 - */
 -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_pending_irq_info: return highest priority pending
 - *    exception, and whether it targets Secure state
 - * @s: the NVIC
 - * @pirq: set to pending exception number
 - * @ptargets_secure: set to whether pending exception targets Secure
 - *
 - * This function writes the number of the highest priority pending
 - * exception (the one which would be made active by
 - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
 - * to true if the current highest priority pending exception should
 - * be taken to Secure state, false for NS.
 - */
 -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
 -                                      bool *ptargets_secure);
 -/**
 - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
 - * @s: the NVIC
 - *
 - * Move the current highest priority pending exception from the pending
 - * state to the active state, and update v7m.exception to indicate that
 - * it is the exception currently being handled.
 - */
 -void armv7m_nvic_acknowledge_irq(NVICState *s);
 -/**
 - * armv7m_nvic_complete_irq: complete specified interrupt or exception
 - * @s: the NVIC
 - * @irq: the exception number to complete
 - * @secure: true if this exception was secure
 - *
 - * Returns: -1 if the irq was not active
 - *           1 if completing this irq brought us back to base (no active irqs)
 - *           0 if there is still an irq active after this one was completed
 - * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
 - */
 -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
 - * @s: the NVIC
 - * @irq: the exception number to mark pending
 - * @secure: false for non-banked exceptions or for the nonsecure
 - * version of a banked exception, true for the secure version of a banked
 - * exception.
 - *
 - * Return whether an exception is "ready", i.e. whether the exception is
 - * enabled and is configured at a priority which would allow it to
 - * interrupt the current execution priority. This controls whether the
 - * RDY bit for it in the FPCCR is set.
 - */
 -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 -/**
 - * armv7m_nvic_raw_execution_priority: return the raw execution priority
 - * @s: the NVIC
 - *
 - * Returns: the raw execution priority as defined by the v8M architecture.
 - * This is the execution priority minus the effects of AIRCR.PRIS,
 - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
 - * (v8M ARM ARM I_PKLD.)
 - */
 -int armv7m_nvic_raw_execution_priority(NVICState *s);
 -/**
 - * armv7m_nvic_neg_prio_requested: return true if the requested execution
 - * priority is negative for the specified security state.
 - * @s: the NVIC
 - * @secure: the security state to test
 - * This corresponds to the pseudocode IsReqExecPriNeg().
 - */
 -#ifndef CONFIG_USER_ONLY
 -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 -#else
 -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 -{
 -    return false;
 -}
 -#endif
 -
  /* Interface for defining coprocessor registers.
   * Registers are defined in tables of arm_cp_reginfo structs
   * which are passed to define_arm_cp_regs().
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
  #if !defined(CONFIG_USER_ONLY)
  #include "hw/loader.h"
  #include "hw/boards.h"
 +#ifdef CONFIG_TCG
  #include "hw/intc/armv7m_nvic.h"
 -#endif
 +#endif /* CONFIG_TCG */
 +#endif /* !CONFIG_USER_ONLY */
  #include "sysemu/tcg.h"
  #include "sysemu/qtest.h"
  #include "sysemu/hw_accel.h"
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/boards.h"
  #endif
  #include "cpregs.h"
 +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  /* Share AArch32 -cpu max features with AArch64. */
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #include "semihosting/common-semi.h"
  #endif
 +#if !defined(CONFIG_USER_ONLY)
 +#include "hw/intc/armv7m_nvic.h"
 +#endif
  static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                           uint32_t reg, uint32_t val)
 --
 .34.1

-New patch
+[PULL 12/30] tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
+From: Alex Bennée <alex.bennee@linaro.org>
 The two TCG tests for GICv2 and GICv3 are very heavy weight distros
 that take a long time to boot up, especially for an --enable-debug
 build. The total code coverage they give is:
   Overall coverage rate:
     lines......: 11.2% (59584 of 530123 lines)
     functions..: 15.0% (7436 of 49443 functions)
     branches...: 6.3% (19273 of 303933 branches)
 We already get pretty close to that with the machine_aarch64_virt
 tests which only does one full boot (~120s vs ~600s) of alpine. We
 expand the kernel+initrd boot (~8s) to test both GICs and also add an
 RNG device and a block device to generate a few IRQs and exercise the
 storage layer. With that we get to a coverage of:
   Overall coverage rate:
     lines......: 11.0% (58121 of 530123 lines)
     functions..: 14.9% (7343 of 49443 functions)
     branches...: 6.0% (18269 of 303933 branches)
 which I feel is close enough given the massive time saving. If we want
 to target any more sub-systems we can use lighter weight more directed
 tests.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Fabiano Rosas <farosas@suse.de>
 Acked-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
 Cc: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  tests/avocado/boot_linux.py           | 48 ++++----------------
  tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 files changed, 65 insertions(+), 46 deletions(-)
 diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/boot_linux.py
 +++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
          self.launch_and_wait(set_up_ssh_connection=False)
 -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
 -# heavyweight. There are lighter weight distros which we use in the
 -# machine_aarch64_virt.py tests.
 +# For Aarch64 we only boot KVM tests in CI as booting the current
 +# Fedora OS in TCG tests is very heavyweight. There are lighter weight
 +# distros which we use in the machine_aarch64_virt.py tests.
  class BootLinuxAarch64(LinuxTest):
      """
      :avocado: tags=arch:aarch64
      :avocado: tags=machine:virt
 -    :avocado: tags=machine:gic-version=2
      """
      timeout = 720
 -    def add_common_args(self):
 -        self.vm.add_args('-bios',
 -                         os.path.join(BUILD_DIR, 'pc-bios',
 -                                      'edk2-aarch64-code.fd'))
 -        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 -        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv2(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv2
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=2")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
 -    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
 -    def test_fedora_cloud_tcg_gicv3(self):
 -        """
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 -        :avocado: tags=device:gicv3
 -        """
 -        self.require_accelerator("tcg")
 -        self.vm.add_args("-accel", "tcg")
 -        self.vm.add_args("-cpu", "max,lpa2=off")
 -        self.vm.add_args("-machine", "virt,gic-version=3")
 -        self.add_common_args()
 -        self.launch_and_wait(set_up_ssh_connection=False)
 -
      def test_virt_kvm(self):
          """
          :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
          self.require_accelerator("kvm")
          self.vm.add_args("-accel", "kvm")
          self.vm.add_args("-machine", "virt,gic-version=host")
 -        self.add_common_args()
 +        self.vm.add_args('-bios',
 +                         os.path.join(BUILD_DIR, 'pc-bios',
 +                                      'edk2-aarch64-code.fd'))
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
          self.launch_and_wait(set_up_ssh_connection=False)
 diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/avocado/machine_aarch64_virt.py
 +++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
  import time
  import os
 +import logging
  from avocado_qemu import QemuSystemTest
  from avocado_qemu import wait_for_console_pattern
  from avocado_qemu import exec_command
  from avocado_qemu import BUILD_DIR
 +from avocado.utils import process
 +from avocado.utils.path import find_command
  class Aarch64VirtMachine(QemuSystemTest):
      KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
          self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 -    def test_aarch64_virt(self):
 +    def common_aarch64_virt(self, machine):
          """
 -        :avocado: tags=arch:aarch64
 -        :avocado: tags=machine:virt
 -        :avocado: tags=accel:tcg
 -        :avocado: tags=cpu:max
 +        Common code to launch basic virt machine with kernel+initrd
 +        and a scratch disk.
          """
 +        logger = logging.getLogger('aarch64_virt')
 +
          kernel_url = ('https://fileserver.linaro.org/s/'
                        'z6B2ARM7DQT3HWN/download')
 -
          kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
          kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                 'console=ttyAMA0')
          self.require_accelerator("tcg")
          self.vm.add_args('-cpu', 'max,pauth-impdef=on',
 +                         '-machine', machine,
                           '-accel', 'tcg',
                           '-kernel', kernel_path,
                           '-append', kernel_command_line)
 +
 +        # A RNG offers an easy way to generate a few IRQs
 +        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
 +        self.vm.add_args('-object',
 +                         'rng-random,id=rng0,filename=/dev/urandom')
 +
 +        # Also add a scratch block device
 +        logger.info('creating scratch qcow2 image')
 +        image_path = os.path.join(self.workdir, 'scratch.qcow2')
 +        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
 +        if not os.path.exists(qemu_img):
 +            qemu_img = find_command('qemu-img', False)
 +        if qemu_img is False:
 +            self.cancel('Could not find "qemu-img", which is required to '
 +                        'create the temporary qcow2 image')
 +        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
 +        process.run(cmd)
 +
 +        # Add the device
 +        self.vm.add_args('-blockdev',
 +                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
 +        self.vm.add_args('-device',
 +                         'virtio-blk-device,drive=scratch')
 +
          self.vm.launch()
          self.wait_for_console_pattern('Welcome to Buildroot')
          time.sleep(0.1)
          exec_command(self, 'root')
          time.sleep(0.1)
 +        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
 +        time.sleep(0.1)
 +        exec_command(self, 'md5sum /dev/vda')
 +        time.sleep(0.1)
 +        exec_command(self, 'cat /proc/interrupts')
 +        time.sleep(0.1)
          exec_command(self, 'cat /proc/self/maps')
          time.sleep(0.1)
 +
 +    def test_aarch64_virt_gicv3(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic_version=3")
 +
 +    def test_aarch64_virt_gicv2(self):
 +        """
 +        :avocado: tags=arch:aarch64
 +        :avocado: tags=machine:virt
 +        :avocado: tags=accel:tcg
 +        :avocado: tags=cpu:max
 +        """
 +        self.common_aarch64_virt("virt,gic-version=2")
 --
 .34.1

-New patch
+[PULL 13/30] hw/arm/smmuv3: Add GBPA register
+From: Mostafa Saleh <smostafa@google.com>
+GBPA register can be used to globally abort all
+transactions.
+It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
+ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
+be zero(Do not abort incoming transactions).
+Other fields have default values of Use Incoming.
+If UPDATE is not set, the write is ignored. This is the only permitted
+behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)
+As this patch adds a new state to the SMMU (GBPA), it is added
+in a new subsection for forward migration compatibility.
+GBPA is only migrated if its value is different from the reset value.
+It does this to be backward migration compatible if SW didn't write
+the register.
+Signed-off-by: Mostafa Saleh <smostafa@google.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230214094009.2445653-1-smostafa@google.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/smmuv3-internal.h |  7 +++++++
+ include/hw/arm/smmuv3.h  |  1 +
+ hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
+files changed, 50 insertions(+), 1 deletion(-)
+diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3-internal.h
++++ b/hw/arm/smmuv3-internal.h
+@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
+ REG32(CR1,                 0x28)
+ REG32(CR2,                 0x2c)
+ REG32(STATUSR,             0x40)
++REG32(GBPA,                0x44)
++    FIELD(GBPA, ABORT,        20, 1)
++    FIELD(GBPA, UPDATE,       31, 1)
++
++/* Use incoming. */
++#define SMMU_GBPA_RESET_VAL 0x1000
++
+ REG32(IRQ_CTRL,            0x50)
+     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
+     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
+diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmuv3.h
++++ b/include/hw/arm/smmuv3.h
+@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
+     uint32_t cr[3];
+     uint32_t cr0ack;
+     uint32_t statusr;
++    uint32_t gbpa;
+     uint32_t irq_ctrl;
+     uint32_t gerror;
+     uint32_t gerrorn;
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3.c
++++ b/hw/arm/smmuv3.c
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
+     s->gerror = 0;
+     s->gerrorn = 0;
+     s->statusr = 0;
++    s->gbpa = SMMU_GBPA_RESET_VAL;
+ }
+ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
+@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
+     qemu_mutex_lock(&s->mutex);
+     if (!smmu_enabled(s)) {
+-        status = SMMU_TRANS_DISABLE;
++        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
++            status = SMMU_TRANS_ABORT;
++        } else {
++            status = SMMU_TRANS_DISABLE;
++        }
+         goto epilogue;
+     }
+@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
+     case A_GERROR_IRQ_CFG2:
+         s->gerror_irq_cfg2 = data;
+         return MEMTX_OK;
++    case A_GBPA:
++        /*
++         * If UPDATE is not set, the write is ignored. This is the only
++         * permitted behavior in SMMUv3.2 and later.
++         */
++        if (data & R_GBPA_UPDATE_MASK) {
++            /* Ignore update bit as write is synchronous. */
++            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
++        }
++        return MEMTX_OK;
+     case A_STRTAB_BASE: /* 64b */
+         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
+         return MEMTX_OK;
+@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
+     case A_STATUSR:
+         *data = s->statusr;
+         return MEMTX_OK;
++    case A_GBPA:
++        *data = s->gbpa;
++        return MEMTX_OK;
+     case A_IRQ_CTRL:
+     case A_IRQ_CTRL_ACK:
+         *data = s->irq_ctrl;
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
+     },
+ };
++static bool smmuv3_gbpa_needed(void *opaque)
++{
++    SMMUv3State *s = opaque;
++
++    /* Only migrate GBPA if it has different reset value. */
++    return s->gbpa != SMMU_GBPA_RESET_VAL;
++}
++
++static const VMStateDescription vmstate_gbpa = {
++    .name = "smmuv3/gbpa",
++    .version_id = 1,
++    .minimum_version_id = 1,
++    .needed = smmuv3_gbpa_needed,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINT32(gbpa, SMMUv3State),
++        VMSTATE_END_OF_LIST()
++    }
++};
++
+ static const VMStateDescription vmstate_smmuv3 = {
+     .name = "smmuv3",
+     .version_id = 1,
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
+         VMSTATE_END_OF_LIST(),
+     },
++    .subsections = (const VMStateDescription * []) {
++        &vmstate_gbpa,
++        NULL
++    }
+ };
+ static void smmuv3_instance_init(Object *obj)
+--
+.34.1

-New patch
+[PULL 14/30] hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
+From: Philippe Mathieu-Daudé <philmd@linaro.org>
+Since commit acc0b8b05a when running the ZynqMP ZCU102 board with
+a QEMU configured using --without-default-devices, we get:
+  $ qemu-system-aarch64 -M xlnx-zcu102
+  qemu-system-aarch64: missing object type 'usb_dwc3'
+  Abort trap: 6
+Fix by adding the missing Kconfig dependency.
+Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers")
+Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230216092327.2203-1-philmd@linaro.org
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/Kconfig | 1 +
+file changed, 1 insertion(+)
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/Kconfig
++++ b/hw/arm/Kconfig
+@@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM
+     select XLNX_CSU_DMA
+     select XLNX_ZYNQMP
+     select XLNX_ZDMA
++    select USB_DWC3
+ config XLNX_VERSAL
+     bool
+--
+.34.1

-New patch
+[PULL 15/30] arm/virt: don't try to spell out the accelerator
+From: Cornelia Huck <cohuck@redhat.com>
+Just use current_accel_name() directly.
+Signed-off-by: Cornelia Huck <cohuck@redhat.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/virt.c | 6 +++---
+file changed, 3 insertions(+), 3 deletions(-)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Security extensions (TrustZone) to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Virtualization extensions to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "MTE to the guest CPU",
+-                     kvm_enabled() ? "KVM" : "HVF");
++                     current_accel_name());
+         exit(1);
+     }
+--
+.34.1

-New patch
+[PULL 16/30] MAINTAINERS: Add myself to maintainers and remove Havard
+From: Hao Wu <wuhaotsh@google.com>
+Havard is no longer working on the Nuvoton systems for a while
+and won't be able to do any work on it in the future. So I'll
+take over maintaining the Nuvoton system from him.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Acked-by: Havard Skinnemoen <hskinnemoen@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-2-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h
+ F: docs/system/arm/musicpal.rst
+ Nuvoton NPCM7xx
+-M: Havard Skinnemoen <hskinnemoen@google.com>
+ M: Tyrone Ting <kfting@nuvoton.com>
++M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+ F: hw/*/npcm7xx*
+--
+.34.1

-New patch
+[PULL 17/30] hw/ssi: Add Nuvoton PSPI Module
+From: Hao Wu <wuhaotsh@google.com>
+Nuvoton's PSPI is a general purpose SPI module which enables
+connections to SPI-based peripheral devices.
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Chris Rauer <crauer@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ MAINTAINERS                |   6 +-
+ include/hw/ssi/npcm_pspi.h |  53 +++++++++
+ hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
+ hw/ssi/meson.build         |   2 +-
+ hw/ssi/trace-events        |   5 +
+files changed, 283 insertions(+), 4 deletions(-)
+ create mode 100644 include/hw/ssi/npcm_pspi.h
+ create mode 100644 hw/ssi/npcm_pspi.c
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
+ M: Hao Wu <wuhaotsh@google.com>
+ L: qemu-arm@nongnu.org
+ S: Supported
+-F: hw/*/npcm7xx*
+-F: include/hw/*/npcm7xx*
+-F: tests/qtest/npcm7xx*
++F: hw/*/npcm*
++F: include/hw/*/npcm*
++F: tests/qtest/npcm*
+ F: pc-bios/npcm7xx_bootrom.bin
+ F: roms/vbootrom
+ F: docs/system/arm/nuvoton.rst
+diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/ssi/npcm_pspi.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton Peripheral SPI Module
++ *
++ * Copyright 2023 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++#ifndef NPCM_PSPI_H
++#define NPCM_PSPI_H
++
++#include "hw/ssi/ssi.h"
++#include "hw/sysbus.h"
++
++/*
++ * Number of registers in our device state structure. Don't change this without
++ * incrementing the version_id in the vmstate.
++ */
++#define NPCM_PSPI_NR_REGS 3
++
++/**
++ * NPCMPSPIState - Device state for one Flash Interface Unit.
++ * @parent: System bus device.
++ * @mmio: Memory region for register access.
++ * @spi: The SPI bus mastered by this controller.
++ * @regs: Register contents.
++ * @irq: The interrupt request queue for this module.
++ *
++ * Each PSPI has a shared bank of registers, and controls up to four chip
++ * selects. Each chip select has a dedicated memory region which may be used to
++ * read and write the flash connected to that chip select as if it were memory.
++ */
++typedef struct NPCMPSPIState {
++    SysBusDevice parent;
++
++    MemoryRegion mmio;
++
++    SSIBus *spi;
++    uint16_t regs[NPCM_PSPI_NR_REGS];
++    qemu_irq irq;
++} NPCMPSPIState;
++
++#define TYPE_NPCM_PSPI "npcm-pspi"
++OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
++
++#endif /* NPCM_PSPI_H */
+diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/hw/ssi/npcm_pspi.c
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Nuvoton NPCM Peripheral SPI Module (PSPI)
++ *
++ * Copyright 2023 Google LLC
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include "qemu/osdep.h"
++
++#include "hw/irq.h"
++#include "hw/registerfields.h"
++#include "hw/ssi/npcm_pspi.h"
++#include "migration/vmstate.h"
++#include "qapi/error.h"
++#include "qemu/error-report.h"
++#include "qemu/log.h"
++#include "qemu/module.h"
++#include "qemu/units.h"
++
++#include "trace.h"
++
++REG16(PSPI_DATA, 0x0)
++REG16(PSPI_CTL1, 0x2)
++    FIELD(PSPI_CTL1, SPIEN, 0,  1)
++    FIELD(PSPI_CTL1, MOD,   2,  1)
++    FIELD(PSPI_CTL1, EIR,   5,  1)
++    FIELD(PSPI_CTL1, EIW,   6,  1)
++    FIELD(PSPI_CTL1, SCM,   7,  1)
++    FIELD(PSPI_CTL1, SCIDL, 8,  1)
++    FIELD(PSPI_CTL1, SCDV,  9,  7)
++REG16(PSPI_STAT, 0x4)
++    FIELD(PSPI_STAT, BSY,  0,  1)
++    FIELD(PSPI_STAT, RBF,  1,  1)
++
++static void npcm_pspi_update_irq(NPCMPSPIState *s)
++{
++    int level = 0;
++
++    /* Only fire IRQ when the module is enabled. */
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
++        /* Update interrupt as BSY is cleared. */
++        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
++            level = 1;
++        }
++
++        /* Update interrupt as RBF is set. */
++        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
++            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
++            level = 1;
++        }
++    }
++    qemu_set_irq(s->irq, level);
++}
++
++static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
++{
++    uint16_t value = s->regs[R_PSPI_DATA];
++
++    /* Clear stat bits as the value are read out. */
++    s->regs[R_PSPI_STAT] = 0;
++
++    return value;
++}
++
++static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
++{
++    uint16_t value = 0;
++
++    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
++        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
++    }
++    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
++    s->regs[R_PSPI_DATA] = value;
++
++    /* Mark data as available */
++    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
++}
++
++/* Control register read handler. */
++static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
++                                    unsigned int size)
++{
++    NPCMPSPIState *s = opaque;
++    uint16_t value;
++
++    switch (addr) {
++    case A_PSPI_DATA:
++        value = npcm_pspi_read_data(s);
++        break;
++
++    case A_PSPI_CTL1:
++        value = s->regs[R_PSPI_CTL1];
++        break;
++
++    case A_PSPI_STAT:
++        value = s->regs[R_PSPI_STAT];
++        break;
++
++    default:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
++                      DEVICE(s)->canonical_path, addr);
++        return 0;
++    }
++    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
++    npcm_pspi_update_irq(s);
++
++    return value;
++}
++
++/* Control register write handler. */
++static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
++                                 unsigned int size)
++{
++    NPCMPSPIState *s = opaque;
++    uint16_t value = v;
++
++    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
++
++    switch (addr) {
++    case A_PSPI_DATA:
++        npcm_pspi_write_data(s, value);
++        break;
++
++    case A_PSPI_CTL1:
++        s->regs[R_PSPI_CTL1] = value;
++        break;
++
++    case A_PSPI_STAT:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to read-only register PSPI_STAT: 0x%08"
++                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
++        break;
++
++    default:
++        qemu_log_mask(LOG_GUEST_ERROR,
++                      "%s: write to invalid offset 0x%" PRIx64 "\n",
++                      DEVICE(s)->canonical_path, addr);
++        return;
++    }
++    npcm_pspi_update_irq(s);
++}
++
++static const MemoryRegionOps npcm_pspi_ctrl_ops = {
++    .read = npcm_pspi_ctrl_read,
++    .write = npcm_pspi_ctrl_write,
++    .endianness = DEVICE_LITTLE_ENDIAN,
++    .valid = {
++        .min_access_size = 1,
++        .max_access_size = 2,
++        .unaligned = false,
++    },
++    .impl = {
++        .min_access_size = 2,
++        .max_access_size = 2,
++        .unaligned = false,
++    },
++};
++
++static void npcm_pspi_enter_reset(Object *obj, ResetType type)
++{
++    NPCMPSPIState *s = NPCM_PSPI(obj);
++
++    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
++    memset(s->regs, 0, sizeof(s->regs));
++}
++
++static void npcm_pspi_realize(DeviceState *dev, Error **errp)
++{
++    NPCMPSPIState *s = NPCM_PSPI(dev);
++    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
++    Object *obj = OBJECT(dev);
++
++    s->spi = ssi_create_bus(dev, "pspi");
++    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
++                          "mmio", 4 * KiB);
++    sysbus_init_mmio(sbd, &s->mmio);
++    sysbus_init_irq(sbd, &s->irq);
++}
++
++static const VMStateDescription vmstate_npcm_pspi = {
++    .name = "npcm-pspi",
++    .version_id = 0,
++    .minimum_version_id = 0,
++    .fields = (VMStateField[]) {
++        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
++        VMSTATE_END_OF_LIST(),
++    },
++};
++
++
++static void npcm_pspi_class_init(ObjectClass *klass, void *data)
++{
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
++    DeviceClass *dc = DEVICE_CLASS(klass);
++
++    dc->desc = "NPCM Peripheral SPI Module";
++    dc->realize = npcm_pspi_realize;
++    dc->vmsd = &vmstate_npcm_pspi;
++    rc->phases.enter = npcm_pspi_enter_reset;
++}
++
++static const TypeInfo npcm_pspi_types[] = {
++    {
++        .name = TYPE_NPCM_PSPI,
++        .parent = TYPE_SYS_BUS_DEVICE,
++        .instance_size = sizeof(NPCMPSPIState),
++        .class_init = npcm_pspi_class_init,
++    },
++};
++DEFINE_TYPES(npcm_pspi_types);
+diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/meson.build
++++ b/hw/ssi/meson.build
+@@ -XXX,XX +XXX,XX @@
+ softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
+ softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
+-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
++softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
+ softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
+ softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
+ softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
+diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/ssi/trace-events
++++ b/hw/ssi/trace-events
+@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
+ npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+ npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
++# npcm_pspi.c
++npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
++npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
++npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
++
+ # ibex_spi_host.c
+ ibex_spi_host_reset(const char *msg) "%s"
+--
+.34.1

-New patch
+[PULL 18/30] hw/arm: Attach PSPI module to NPCM7XX SoC
+From: Hao Wu <wuhaotsh@google.com>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
+Reviewed-by: Titus Rwantare <titusr@google.com>
+Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
+Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/nuvoton.rst |  2 +-
+ include/hw/arm/npcm7xx.h    |  2 ++
+ hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
+files changed, 26 insertions(+), 3 deletions(-)
+diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/nuvoton.rst
++++ b/docs/system/arm/nuvoton.rst
+@@ -XXX,XX +XXX,XX @@ Supported devices
+  * SMBus controller (SMBF)
+  * Ethernet controller (EMC)
+  * Tachometer
++ * Peripheral SPI controller (PSPI)
+ Missing devices
+ ---------------
+@@ -XXX,XX +XXX,XX @@ Missing devices
+  * Ethernet controller (GMAC)
+  * USB device (USBD)
+- * Peripheral SPI controller (PSPI)
+  * SD/MMC host
+  * PECI interface
+  * PCI and PCIe root complex and bridges
+diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/npcm7xx.h
++++ b/include/hw/arm/npcm7xx.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/nvram/npcm7xx_otp.h"
+ #include "hw/timer/npcm7xx_timer.h"
+ #include "hw/ssi/npcm7xx_fiu.h"
++#include "hw/ssi/npcm_pspi.h"
+ #include "hw/usb/hcd-ehci.h"
+ #include "hw/usb/hcd-ohci.h"
+ #include "target/arm/cpu.h"
+@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
+     NPCM7xxFIUState     fiu[2];
+     NPCM7xxEMCState     emc[2];
+     NPCM7xxSDHCIState   mmc;
++    NPCMPSPIState       pspi[2];
+ };
+ #define TYPE_NPCM7XX    "npcm7xx"
+diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/npcm7xx.c
++++ b/hw/arm/npcm7xx.c
+@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
+     NPCM7XX_EMC1RX_IRQ          = 15,
+     NPCM7XX_EMC1TX_IRQ,
+     NPCM7XX_MMC_IRQ             = 26,
++    NPCM7XX_PSPI2_IRQ           = 28,
++    NPCM7XX_PSPI1_IRQ           = 31,
+     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
+     NPCM7XX_TIMER1_IRQ,
+     NPCM7XX_TIMER2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
+xf0826000,
+ };
++/* Register base address for each PSPI Module */
++static const hwaddr npcm7xx_pspi_addr[] = {
++    0xf0200000,
++    0xf0201000,
++};
++
+ static const struct {
+     hwaddr regs_addr;
+     uint32_t unconnected_pins;
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
+         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
+     }
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
++    }
++
+     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
+ }
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
+             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
++    /* PSPI */
++    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
++    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
++        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
++        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
++
++        sysbus_realize(sbd, &error_abort);
++        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
++        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
++    }
++
+     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
+-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
+     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
+     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
+     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
+--
+.34.1

-New patch
+[PULL 19/30] hw/arm/smmu-common: Support 64-bit addresses
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Addresses targeting the second translation table (TTB1) in the SMMU have
+all upper bits set. Ensure the IOMMU region covers all 64 bits.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/smmu-common.h | 2 --
+ hw/arm/smmu-common.c         | 2 +-
+files changed, 1 insertion(+), 3 deletions(-)
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmu-common.h
++++ b/include/hw/arm/smmu-common.h
+@@ -XXX,XX +XXX,XX @@
+ #define SMMU_PCI_DEVFN_MAX    256
+ #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
+-#define SMMU_MAX_VA_BITS      48
+-
+ /*
+  * Page table walk error types
+  */
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
+         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
+                                  s->mrtypename,
+-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
++                                 OBJECT(s), name, UINT64_MAX);
+         address_space_init(&sdev->as,
+                            MEMORY_REGION(&sdev->iommu), name);
+         trace_smmu_add_mr(name);
+--
+.34.1

-New patch
+[PULL 20/30] hw/arm/smmu-common: Fix TTB1 handling
+From: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Addresses targeting the second translation table (TTB1) in the SMMU have
+all upper bits set (except for the top byte when TBI is enabled). Fix
+the TTB1 check.
+Reported-by: Ola Hugosson <ola.hugosson@arm.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
+Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/smmu-common.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
+         /* there is a ttbr0 region and we are in it (high bits all zero) */
+         return &cfg->tt[0];
+     } else if (cfg->tt[1].tsz &&
+-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
++        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
+         /* there is a ttbr1 region and we are in it (high bits all one) */
+         return &cfg->tt[1];
+     } else if (!cfg->tt[0].tsz) {
+--
+.34.1

-[Qemu-devel] [PULL 6/8] bcm2835_aux: Swap RX and TX interrupt assignments
+[PULL 21/30] target/arm: rename handle_semihosting to tcg_handle_semihosting
-From: Guenter Roeck <linux@roeck-us.net>
+From: Claudio Fontana <cfontana@suse.de>
-RX and TX interrupt bits were reversed, resulting in an endless sequence
+make it clearer from the name that this is a tcg-only function.
 of serial interupts in the emulated system and the following repeated
 error message when booting Linux.
-serial8250: too much work for irq61
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
-This results in a boot failure most of the time.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Qemu command line used to reproduce the problem:
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
     qemu-system-aarch64 -M raspi3 -m 1024 \
     -kernel arch/arm64/boot/Image \
     --append "rdinit=/sbin/init console=ttyS1,115200"
     -initrd rootfs.cpio \
     -dtb arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dtb \
     -nographic -monitor null -serial null -serial stdio
 This is with arm64:defconfig. The root file system was generated using
 buildroot.
 NB that this error likely arises from an erratum in the
 BCM2835 datasheet where the TX and RX bits were swapped
 in the AU_MU_IER_REG description (but correct for IIR):
  https://elinux.org/BCM2835_datasheet_errata#p12
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 1529355846-25102-1-git-send-email-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: added NB about datasheet]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/char/bcm2835_aux.c | 4 ++--
+ target/arm/helper.c | 4 ++--
 file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/char/bcm2835_aux.c
+--- a/target/arm/helper.c
-+++ b/hw/char/bcm2835_aux.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
- #define AUX_MU_BAUD_REG 0x68
+  * trapped to the hypervisor in KVM.
+  */
- /* bits in IER/IIR registers */
+ #ifdef CONFIG_TCG
--#define TX_INT  0x1
+-static void handle_semihosting(CPUState *cs)
--#define RX_INT  0x2
++static void tcg_handle_semihosting(CPUState *cs)
 +#define RX_INT  0x1
 +#define TX_INT  0x2
  static void bcm2835_aux_update(BCM2835AuxState *s)
  {
+     ARMCPU *cpu = ARM_CPU(cs);
+     CPUARMState *env = &cpu->env;
+@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
+      */
+ #ifdef CONFIG_TCG
+     if (cs->exception_index == EXCP_SEMIHOST) {
+-        handle_semihosting(cs);
++        tcg_handle_semihosting(cs);
+         return;
+     }
+ #endif
 --
-.17.1
+.34.1

-[Qemu-devel] [PULL 8/8] accel/tcg: Assert that tlb fill gave us a valid TLB entry
+[PULL 22/30] target/arm: wrap psci call with tcg_enabled
-In commit 4b1a3e1e34ad97 we added a check for whether the TLB entry
+From: Claudio Fontana <cfontana@suse.de>
 we had following a tlb_fill had the INVALID bit set.  This could
 happen in some circumstances because a stale or wrong TLB entry was
 pulled out of the victim cache.  However, after commit
 fea038553039e (which prevents stale entries being in the victim
 cache) and the previous commit (which ensures we don't incorrectly
 hit in the victim cache)) this should never be possible.
-Drop the check on TLB_INVALID_MASK from the "is this a TLB_RECHECK?"
+for "all" builds (tcg + kvm), we want to avoid doing
-condition, and instead assert that the tlb fill procedure has given
+the psci check if tcg is built-in, but not enabled.
 us a valid TLB entry (or longjumped out with a guest exception).
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180713141636.18665-3-peter.maydell@linaro.org
 ---
- accel/tcg/cputlb.c | 4 ++--
+ target/arm/helper.c | 3 ++-
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/cputlb.c
+--- a/target/arm/helper.c
-+++ b/accel/tcg/cputlb.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
+@@ -XXX,XX +XXX,XX @@
-         if (!VICTIM_TLB_HIT(addr_code, addr)) {
+ #include "hw/irq.h"
-             tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
+ #include "sysemu/cpu-timers.h"
-         }
+ #include "sysemu/kvm.h"
-+        assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
++#include "sysemu/tcg.h"
  #include "qapi/qapi-commands-machine-target.h"
  #include "qapi/error.h"
  #include "qemu/guest-random.h"
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
                        env->exception.syndrome);
      }
--    if (unlikely((env->tlb_table[mmu_idx][index].addr_code &
+-    if (arm_is_psci_call(cpu, cs->exception_index)) {
--                  (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) {
++    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
-+    if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) {
+         arm_handle_psci_call(cpu);
-         /*
+         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
-          * This is a TLB_RECHECK access, where the MMU protection
+         return;
           * covers a smaller range than a target page, and we must
 --
-.17.1
+.34.1

-[Qemu-devel] [PULL 4/8] hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
+[PULL 23/30] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
-The GICD_ITARGETSR implementation still has some 11MPCore behaviour
+From: Claudio Fontana <cfontana@suse.de>
 that we were incorrectly using in our GICv1 and GICv2 implementations
 for the case where the interrupt number is less than GIC_INTERNAL.
 The desired behaviour here is:
  * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the
    CPU doing the read for irqs 29..31
  * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a
    number matching the CPU doing the read for all irqs < 32
-Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this
+Signed-off-by: Claudio Fontana <cfontana@suse.de>
-is an 11MPCore GIC.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/helper.c | 12 +++++++-----
 file changed, 7 insertions(+), 5 deletions(-)
-Reported-by: Jan Kiszka <jan.kiszka@web.de>
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
 Message-id: 20180712154152.32183-3-peter.maydell@linaro.org
 ---
  hw/intc/arm_gic.c | 6 ++++--
 file changed, 4 insertions(+), 2 deletions(-)
 diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic.c
+--- a/target/arm/helper.c
-+++ b/hw/intc/arm_gic.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
-             if (irq >= s->num_irq) {
+     unsigned int cur_el = arm_current_el(env);
-                 goto bad_reg;
+     int rt;
-             }
--            if (irq >= 29 && irq <= 31) {
+-    /*
-+            if (irq < 29 && s->revision == REV_11MPCORE) {
+-     * Note that new_el can never be 0.  If cur_el is 0, then
-+                res = 0;
+-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-+            } else if (irq < GIC_INTERNAL) {
+-     */
-                 res = cm;
+-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
-             } else {
++    if (tcg_enabled()) {
-                 res = GIC_TARGET(irq);
++        /*
-@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
++         * Note that new_el can never be 0.  If cur_el is 0, then
-             if (irq >= s->num_irq) {
++         * el0_a64 is is_a64(), else el0_a64 is ignored.
-                 goto bad_reg;
++         */
-             }
++        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
--            if (irq < 29) {
++    }
-+            if (irq < 29 && s->revision == REV_11MPCORE) {
-                 value = 0;
+     if (cur_el < new_el) {
-             } else if (irq < GIC_INTERNAL) {
+         /*
                  value = ALL_CPU_MASK;
 --
-.17.1
+.34.1

-[Qemu-devel] [PULL 3/8] hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()
+[PULL 24/30] target/arm: Move PC alignment check
-In gic_deactivate_irq() the interrupt number comes from the guest
+From: Fabiano Rosas <farosas@suse.de>
 (on a write to the GICC_DIR register), so we need to sanity check
 that it isn't out of range before we use it as an array index.
 Handle this in a similar manner to the check we do in
 gic_complete_irq() for the GICC_EOI register.
-The array overrun is not disastrous because the calling code
+Move this earlier to make the next patch diff cleaner. While here
-uses (value & 0x3ff) to extract the interrupt field, so the
+update the comment slightly to not give the impression that the
-only out-of-range values possible are 1020..1023, which allow
+misalignment affects only TCG.
 overrunning only from irq_state[] into the following
 irq_target[] array which the guest can already manipulate.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20180712154152.32183-2-peter.maydell@linaro.org
 ---
- hw/intc/arm_gic.c | 16 +++++++++++++++-
+ target/arm/machine.c | 18 +++++++++---------
-file changed, 15 insertions(+), 1 deletion(-)
+file changed, 9 insertions(+), 9 deletions(-)
-diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
+diff --git a/target/arm/machine.c b/target/arm/machine.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic.c
+--- a/target/arm/machine.c
-+++ b/hw/intc/arm_gic.c
++++ b/target/arm/machine.c
-@@ -XXX,XX +XXX,XX @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
- static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
+         }
- {
+     }
-     int cm = 1 << cpu;
--    int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
++    /*
-+    int group;
++     * Misaligned thumb pc is architecturally impossible. Fail the
-+
++     * incoming migration. For TCG it would trigger the assert in
-+    if (irq >= s->num_irq) {
++     * thumb_tr_translate_insn().
-+        /*
++     */
-+         * This handles two cases:
++    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-+         * 1. If software writes the ID of a spurious interrupt [ie 1023]
++        return -1;
 +         * to the GICC_DIR, the GIC ignores that write.
 +         * 2. If software writes the number of a non-existent interrupt
 +         * this must be a subcase of "value written is not an active interrupt"
 +         * and so this is UNPREDICTABLE. We choose to ignore it.
 +         */
 +        return;
 +    }
 +
-+    group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
+     hw_breakpoint_update_all(cpu);
+     hw_watchpoint_update_all(cpu);
-     if (!gic_eoi_split(s, cpu, attrs)) {
-         /* This is UNPREDICTABLE; we choose to ignore it */
+@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
          }
      }
 -    /*
 -     * Misaligned thumb pc is architecturally impossible.
 -     * We have an assert in thumb_tr_translate_insn to verify this.
 -     * Fail an incoming migrate to avoid this assert.
 -     */
 -    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
 -        return -1;
 -    }
 -
      if (!kvm_enabled()) {
          pmu_op_finish(&cpu->env);
      }
 --
-.17.1
+.34.1

-New patch
+[PULL 25/30] target/arm: Move cpregs code out of cpu.h
+From: Fabiano Rosas <farosas@suse.de>
 Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
 a cpregs.h header which is more suitable for this code.
 Code moved verbatim.
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
  target/arm/cpu.h    | 91 -----------------------------------------
 files changed, 98 insertions(+), 91 deletions(-)
 diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpregs.h
 +++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
      ARM_CP_SME                   = 1 << 19,
  };
 +/*
 + * Interface for defining coprocessor registers.
 + * Registers are defined in tables of arm_cp_reginfo structs
 + * which are passed to define_arm_cp_regs().
 + */
 +
 +/*
 + * When looking up a coprocessor register we look for it
 + * via an integer which encodes all of:
 + *  coprocessor number
 + *  Crn, Crm, opc1, opc2 fields
 + *  32 or 64 bit register (ie is it accessed via MRC/MCR
 + *    or via MRRC/MCRR?)
 + *  non-secure/secure bank (AArch32 only)
 + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 + * (In this case crn and opc2 should be zero.)
 + * For AArch64, there is no 32/64 bit size distinction;
 + * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 + * and 4 bit CRn and CRm. The encoding patterns are chosen
 + * to be easy to convert to and from the KVM encodings, and also
 + * so that the hashtable can contain both AArch32 and AArch64
 + * registers (to allow for interprocessing where we might run
 + * 32 bit code on a 64 bit core).
 + */
 +/*
 + * This bit is private to our hashtable cpreg; in KVM register
 + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 + * in the upper bits of the 64 bit ID.
 + */
 +#define CP_REG_AA64_SHIFT 28
 +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 +
 +/*
 + * To enable banking of coprocessor registers depending on ns-bit we
 + * add a bit to distinguish between secure and non-secure cpregs in the
 + * hashtable.
 + */
 +#define CP_REG_NS_SHIFT 29
 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 +
 +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 +    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 +     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 +
 +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 +    (CP_REG_AA64_MASK |                                 \
 +     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 +     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 +     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 +     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 +     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 +     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 +
 +/*
 + * Convert a full 64 bit KVM register ID to the truncated 32 bit
 + * version used as a key for the coprocessor register hashtable
 + */
 +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 +{
 +    uint32_t cpregid = kvmid;
 +    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 +        cpregid |= CP_REG_AA64_MASK;
 +    } else {
 +        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 +            cpregid |= (1 << 15);
 +        }
 +
 +        /*
 +         * KVM is always non-secure so add the NS flag on AArch32 register
 +         * entries.
 +         */
 +         cpregid |= 1 << CP_REG_NS_SHIFT;
 +    }
 +    return cpregid;
 +}
 +
 +/*
 + * Convert a truncated 32 bit hashtable key into the full
 + * 64 bit KVM register ID.
 + */
 +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 +{
 +    uint64_t kvmid;
 +
 +    if (cpregid & CP_REG_AA64_MASK) {
 +        kvmid = cpregid & ~CP_REG_AA64_MASK;
 +        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 +    } else {
 +        kvmid = cpregid & ~(1 << 15);
 +        if (cpregid & (1 << 15)) {
 +            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 +        } else {
 +            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 +        }
 +    }
 +    return kvmid;
 +}
 +
  /*
   * Valid values for ARMCPRegInfo state field, indicating which of
   * the AArch32 and AArch64 execution states this register is visible in.
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
  uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                   uint32_t cur_el, bool secure);
 -/* Interface for defining coprocessor registers.
 - * Registers are defined in tables of arm_cp_reginfo structs
 - * which are passed to define_arm_cp_regs().
 - */
 -
 -/* When looking up a coprocessor register we look for it
 - * via an integer which encodes all of:
 - *  coprocessor number
 - *  Crn, Crm, opc1, opc2 fields
 - *  32 or 64 bit register (ie is it accessed via MRC/MCR
 - *    or via MRRC/MCRR?)
 - *  non-secure/secure bank (AArch32 only)
 - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 - * (In this case crn and opc2 should be zero.)
 - * For AArch64, there is no 32/64 bit size distinction;
 - * instead all registers have a 2 bit op0, 3 bit op1 and op2,
 - * and 4 bit CRn and CRm. The encoding patterns are chosen
 - * to be easy to convert to and from the KVM encodings, and also
 - * so that the hashtable can contain both AArch32 and AArch64
 - * registers (to allow for interprocessing where we might run
 - * 32 bit code on a 64 bit core).
 - */
 -/* This bit is private to our hashtable cpreg; in KVM register
 - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
 - * in the upper bits of the 64 bit ID.
 - */
 -#define CP_REG_AA64_SHIFT 28
 -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
 -
 -/* To enable banking of coprocessor registers depending on ns-bit we
 - * add a bit to distinguish between secure and non-secure cpregs in the
 - * hashtable.
 - */
 -#define CP_REG_NS_SHIFT 29
 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
 -
 -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
 -    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
 -     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
 -
 -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
 -    (CP_REG_AA64_MASK |                                 \
 -     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
 -     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
 -     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
 -     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
 -     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
 -     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
 -
 -/* Convert a full 64 bit KVM register ID to the truncated 32 bit
 - * version used as a key for the coprocessor register hashtable
 - */
 -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 -{
 -    uint32_t cpregid = kvmid;
 -    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
 -        cpregid |= CP_REG_AA64_MASK;
 -    } else {
 -        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 -            cpregid |= (1 << 15);
 -        }
 -
 -        /* KVM is always non-secure so add the NS flag on AArch32 register
 -         * entries.
 -         */
 -         cpregid |= 1 << CP_REG_NS_SHIFT;
 -    }
 -    return cpregid;
 -}
 -
 -/* Convert a truncated 32 bit hashtable key into the full
 - * 64 bit KVM register ID.
 - */
 -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 -{
 -    uint64_t kvmid;
 -
 -    if (cpregid & CP_REG_AA64_MASK) {
 -        kvmid = cpregid & ~CP_REG_AA64_MASK;
 -        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
 -    } else {
 -        kvmid = cpregid & ~(1 << 15);
 -        if (cpregid & (1 << 15)) {
 -            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 -        } else {
 -            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 -        }
 -    }
 -    return kvmid;
 -}
 -
  /* Return the highest implemented Exception Level */
  static inline int arm_highest_el(CPUARMState *env)
  {
 --
 .34.1

-[Qemu-devel] [PULL 2/8] aspeed: Implement write-1-{set, clear} for AST2500 strapping
+[PULL 26/30] tests/avocado: Skip tests that require a missing accelerator
-From: Andrew Jeffery <andrew@aj.id.au>
+From: Fabiano Rosas <farosas@suse.de>
-The AST2500 SoC family changes the runtime behaviour of the hardware
+If a test was tagged with the "accel" tag and the specified
-strapping register (SCU70) to write-1-set/write-1-clear, with
+accelerator it not present in the qemu binary, cancel the test.
 write-1-clear implemented on the "read-only" SoC revision register
 (SCU7C). For the the AST2400, the hardware strapping is
 runtime-configured with read-modify-write semantics.
-Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
+We can now write tests without explicit calls to require_accelerator,
-Reviewed-by: Joel Stanley <joel@jms.id.au>
+just the tag is enough.
-Message-id: 20180709143524.17480-1-andrew@aj.id.au
 Signed-off-by: Fabiano Rosas <farosas@suse.de>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/misc/aspeed_scu.h |  2 ++
+ tests/avocado/avocado_qemu/__init__.py | 4 ++++
- hw/misc/aspeed_scu.c         | 19 +++++++++++++++++--
+file changed, 4 insertions(+)
 files changed, 19 insertions(+), 2 deletions(-)
-diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
+diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/aspeed_scu.h
+--- a/tests/avocado/avocado_qemu/__init__.py
-+++ b/include/hw/misc/aspeed_scu.h
++++ b/tests/avocado/avocado_qemu/__init__.py
-@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
+@@ -XXX,XX +XXX,XX @@ def setUp(self):
- #define AST2500_A0_SILICON_REV   0x04000303U
- #define AST2500_A1_SILICON_REV   0x04010303U
+         super().setUp('qemu-system-')
-+#define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
++        accel_required = self._get_unique_tag_val('accel')
 +        if accel_required:
 +            self.require_accelerator(accel_required)
 +
- extern bool is_supported_silicon_rev(uint32_t silicon_rev);
+         self.machine = self.params.get('machine',
+                                        default=self._get_unique_tag_val('machine'))
- #define ASPEED_SCU_PROT_KEY      0x1688A8A8
 diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/aspeed_scu.c
 +++ b/hw/misc/aspeed_scu.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
          s->regs[reg] = data;
          aspeed_scu_set_apb_freq(s);
          break;
 -
 +    case HW_STRAP1:
 +        if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
 +            s->regs[HW_STRAP1] |= data;
 +            return;
 +        }
 +        /* Jump to assignment below */
 +        break;
 +    case SILICON_REV:
 +        if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
 +            s->regs[HW_STRAP1] &= ~data;
 +        } else {
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
 +                          __func__, offset);
 +        }
 +        /* Avoid assignment below, we've handled everything */
 +        return;
      case FREQ_CNTR_EVAL:
      case VGA_SCRATCH1 ... VGA_SCRATCH8:
      case RNG_DATA:
 -    case SILICON_REV:
      case FREE_CNTR4:
      case FREE_CNTR4_EXT:
          qemu_log_mask(LOG_GUEST_ERROR,
 --
-.17.1
+.34.1

-[Qemu-devel] [PULL 1/8] target/arm: Fix LD1W and LDFF1W (scalar plus vector)
+[PULL 27/30] tests/avocado: Tag TCG tests with accel:tcg
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Fabiano Rosas <farosas@suse.de>
-'I' was being double-incremented; correctly within the inner loop
+This allows the test to be skipped when TCG is not present in the QEMU
-and incorrectly within the outer loop.
+binary.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20180711103957.3040-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/sve_helper.c | 4 ++--
+ tests/avocado/boot_linux_console.py | 1 +
-file changed, 2 insertions(+), 2 deletions(-)
+ tests/avocado/reverse_debugging.py  | 8 ++++++++
 files changed, 9 insertions(+)
-diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
+diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/sve_helper.c
+--- a/tests/avocado/boot_linux_console.py
-+++ b/target/arm/sve_helper.c
++++ b/tests/avocado/boot_linux_console.py
-@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm,       \
+@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
-     intptr_t i, oprsz = simd_oprsz(desc);                               \
-     unsigned scale = simd_data(desc);                                   \
+     def test_aarch64_raspi3_atf(self):
-     uintptr_t ra = GETPC();                                             \
+         """
--    for (i = 0; i < oprsz; i++) {                                       \
++        :avocado: tags=accel:tcg
-+    for (i = 0; i < oprsz; ) {                                          \
+         :avocado: tags=arch:aarch64
-         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
+         :avocado: tags=machine:raspi3b
-         do {                                                            \
+         :avocado: tags=cpu:cortex-a53
-             TYPEM m = 0;                                                \
+diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
-@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm,       \
+index XXXXXXX..XXXXXXX 100644
-     uintptr_t ra = GETPC();                                             \
+--- a/tests/avocado/reverse_debugging.py
-     bool first = true;                                                  \
++++ b/tests/avocado/reverse_debugging.py
-     mmap_lock();                                                        \
+@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
--    for (i = 0; i < oprsz; i++) {                                       \
+         vm.shutdown()
-+    for (i = 0; i < oprsz; ) {                                          \
-         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
+ class ReverseDebugging_X86_64(ReverseDebugging):
-         do {                                                            \
++    """
-             TYPEM m = 0;                                                \
++    :avocado: tags=accel:tcg
 +    """
 +
      REG_PC = 0x10
      REG_CS = 0x12
      def get_pc(self, g):
@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
          self.reverse_debugging()
  class ReverseDebugging_AArch64(ReverseDebugging):
 +    """
 +    :avocado: tags=accel:tcg
 +    """
 +
      REG_PC = 32
      # unidentified gitlab timeout problem
 --
-.17.1
+.34.1

-New patch
+[PULL 28/30] target/arm: Use "max" as default cpu for the virt machine with KVM
+From: Fabiano Rosas <farosas@suse.de>
+Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
+KVM-only build the 'max' cpu.
+Note that we cannot use 'host' here because the qtests can run without
+any other accelerator (than qtest) and 'host' depends on KVM being
+enabled.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/virt.c | 4 ++++
+file changed, 4 insertions(+)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+     mc->minimum_page_bits = 12;
+     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
+     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
++#ifdef CONFIG_TCG
+     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
++#else
++    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
++#endif
+     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
+     mc->kvm_type = virt_kvm_type;
+     assert(!mc->get_hotplug_handler);
+--
+.34.1

-New patch
+[PULL 29/30] tests/qtest: arm-cpu-features: Match tests to required accelerators
+From: Fabiano Rosas <farosas@suse.de>
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Acked-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
+file changed, 18 insertions(+), 10 deletions(-)
+diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/arm-cpu-features.c
++++ b/tests/qtest/arm-cpu-features.c
+@@ -XXX,XX +XXX,XX @@
+ #define SVE_MAX_VQ 16
+ #define MACHINE     "-machine virt,gic-version=max -accel tcg "
+-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
++#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
+ #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+                     "  'arguments': { 'type': 'full', "
+ #define QUERY_TAIL  "}}"
+@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
+ {
+     g_test_init(&argc, &argv, NULL);
+-    qtest_add_data_func("/arm/query-cpu-model-expansion",
+-                        NULL, test_query_cpu_model_expansion);
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/query-cpu-model-expansion",
++                            NULL, test_query_cpu_model_expansion);
++    }
++
++    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
++        goto out;
++    }
+     /*
+      * For now we only run KVM specific tests with AArch64 QEMU in
+      * order avoid attempting to run an AArch32 QEMU with KVM on
+      * AArch64 hosts. That won't work and isn't easy to detect.
+      */
+-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
++    if (qtest_has_accel("kvm")) {
+         /*
+          * This tests target the 'host' CPU type, so register it only if
+          * KVM is available.
+          */
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                             NULL, test_query_cpu_model_expansion_kvm);
+-    }
+-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+-                            NULL, sve_tests_sve_max_vq_8);
+-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+-                            NULL, sve_tests_sve_off);
+         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+                             NULL, sve_tests_sve_off_kvm);
+     }
++    if (qtest_has_accel("tcg")) {
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
++                            NULL, sve_tests_sve_max_vq_8);
++        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
++                            NULL, sve_tests_sve_off);
++    }
++
++out:
+     return g_test_run();
+ }
+--
+.34.1

-New patch
+[PULL 30/30] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
+From: Fabiano Rosas <farosas@suse.de>
+These tests set -accel tcg, so restrict them to when TCG is present.
+Signed-off-by: Fabiano Rosas <farosas@suse.de>
+Acked-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Thomas Huth <thuth@redhat.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ tests/qtest/meson.build | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/qtest/meson.build
++++ b/tests/qtest/meson.build
+@@ -XXX,XX +XXX,XX @@ qtests_arm = \
+ # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
+ qtests_aarch64 = \
+   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
+-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
++  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
++    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
+   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
+   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
+   ['arm-cpu-features',
+--
+.34.1

target-arm queue: a smallish set of patches for rc1 tomorrow.
I've included the tcg patches because RTH has no others that
would merit a pullreq.

I haven't included Thomas Huth's 17-patch set to deal with
the introspection crashes, to give that a little more time
on-list for review.

thanks
-- PMM

The following changes since commit 102ad0a80f5110483efd06877c29c4236be267f9:

Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-07-16' into staging (2018-07-16 15:34:38 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180716

for you to fetch changes up to 3474c98a2a2afcefa7c665f02ad2bed2a43ab0f7:

accel/tcg: Assert that tlb fill gave us a valid TLB entry (2018-07-16 17:26:01 +0100)

----------------------------------------------------------------
target-arm queue:
 * accel/tcg: Use correct test when looking in victim TLB for code
 * bcm2835_aux: Swap RX and TX interrupt assignments
 * hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false
 * hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
 * hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()
 * aspeed: Implement write-1-{set, clear} for AST2500 strapping
 * target/arm: Fix LD1W and LDFF1W (scalar plus vector)

----------------------------------------------------------------
Andrew Jeffery (1):
      aspeed: Implement write-1-{set, clear} for AST2500 strapping

Guenter Roeck (1):
      bcm2835_aux: Swap RX and TX interrupt assignments

Peter Maydell (4):
      hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()
      hw/intc/arm_gic: Fix handling of GICD_ITARGETSR
      accel/tcg: Use correct test when looking in victim TLB for code
      accel/tcg: Assert that tlb fill gave us a valid TLB entry

Richard Henderson (1):
      target/arm: Fix LD1W and LDFF1W (scalar plus vector)

Thomas Huth (1):
      hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false

From: Richard Henderson <richard.henderson@linaro.org>

'I' was being double-incremented; correctly within the inner loop
and incorrectly within the outer loop.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180711103957.3040-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/sve_helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm,       \
     intptr_t i, oprsz = simd_oprsz(desc);                               \
     unsigned scale = simd_data(desc);                                   \
     uintptr_t ra = GETPC();                                             \
-    for (i = 0; i < oprsz; i++) {                                       \
+    for (i = 0; i < oprsz; ) {                                          \
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
         do {                                                            \
             TYPEM m = 0;                                                \
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(CPUARMState *env, void *vd, void *vg, void *vm,       \
     uintptr_t ra = GETPC();                                             \
     bool first = true;                                                  \
     mmap_lock();                                                        \
-    for (i = 0; i < oprsz; i++) {                                       \
+    for (i = 0; i < oprsz; ) {                                          \
         uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3));                 \
         do {                                                            \
             TYPEM m = 0;                                                \
-- 
2.17.1

From: Andrew Jeffery <andrew@aj.id.au>

The AST2500 SoC family changes the runtime behaviour of the hardware
strapping register (SCU70) to write-1-set/write-1-clear, with
write-1-clear implemented on the "read-only" SoC revision register
(SCU7C). For the the AST2400, the hardware strapping is
runtime-configured with read-modify-write semantics.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20180709143524.17480-1-andrew@aj.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/aspeed_scu.h |  2 ++
 hw/misc/aspeed_scu.c         | 19 +++++++++++++++++--
 2 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSCUState {
 #define AST2500_A0_SILICON_REV   0x04000303U
 #define AST2500_A1_SILICON_REV   0x04010303U
 
+#define ASPEED_IS_AST2500(si_rev)     ((((si_rev) >> 24) & 0xff) == 0x04)
+
 extern bool is_supported_silicon_rev(uint32_t silicon_rev);
 
 #define ASPEED_SCU_PROT_KEY      0x1688A8A8
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -XXX,XX +XXX,XX @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
         s->regs[reg] = data;
         aspeed_scu_set_apb_freq(s);
         break;
-
+    case HW_STRAP1:
+        if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+            s->regs[HW_STRAP1] |= data;
+            return;
+        }
+        /* Jump to assignment below */
+        break;
+    case SILICON_REV:
+        if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
+            s->regs[HW_STRAP1] &= ~data;
+        } else {
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
+                          __func__, offset);
+        }
+        /* Avoid assignment below, we've handled everything */
+        return;
     case FREQ_CNTR_EVAL:
     case VGA_SCRATCH1 ... VGA_SCRATCH8:
     case RNG_DATA:
-    case SILICON_REV:
     case FREE_CNTR4:
     case FREE_CNTR4_EXT:
         qemu_log_mask(LOG_GUEST_ERROR,
-- 
2.17.1

In gic_deactivate_irq() the interrupt number comes from the guest
(on a write to the GICC_DIR register), so we need to sanity check
that it isn't out of range before we use it as an array index.
Handle this in a similar manner to the check we do in
gic_complete_irq() for the GICC_EOI register.

The array overrun is not disastrous because the calling code
uses (value & 0x3ff) to extract the interrupt field, so the
only out-of-range values possible are 1020..1023, which allow
overrunning only from irq_state[] into the following
irq_target[] array which the guest can already manipulate.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180712154152.32183-2-peter.maydell@linaro.org
---
 hw/intc/arm_gic.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -XXX,XX +XXX,XX @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)
 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
 {
     int cm = 1 << cpu;
-    int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
+    int group;
+
+    if (irq >= s->num_irq) {
+        /*
+         * This handles two cases:
+         * 1. If software writes the ID of a spurious interrupt [ie 1023]
+         * to the GICC_DIR, the GIC ignores that write.
+         * 2. If software writes the number of a non-existent interrupt
+         * this must be a subcase of "value written is not an active interrupt"
+         * and so this is UNPREDICTABLE. We choose to ignore it.
+         */
+        return;
+    }
+
+    group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
 
     if (!gic_eoi_split(s, cpu, attrs)) {
         /* This is UNPREDICTABLE; we choose to ignore it */
-- 
2.17.1

The GICD_ITARGETSR implementation still has some 11MPCore behaviour
that we were incorrectly using in our GICv1 and GICv2 implementations
for the case where the interrupt number is less than GIC_INTERNAL.
The desired behaviour here is:
 * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the
   CPU doing the read for irqs 29..31
 * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a
   number matching the CPU doing the read for all irqs < 32

Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this
is an 11MPCore GIC.

Reported-by: Jan Kiszka <jan.kiszka@web.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180712154152.32183-3-peter.maydell@linaro.org
---
 hw/intc/arm_gic.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
             if (irq >= s->num_irq) {
                 goto bad_reg;
             }
-            if (irq >= 29 && irq <= 31) {
+            if (irq < 29 && s->revision == REV_11MPCORE) {
+                res = 0;
+            } else if (irq < GIC_INTERNAL) {
                 res = cm;
             } else {
                 res = GIC_TARGET(irq);
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
             if (irq >= s->num_irq) {
                 goto bad_reg;
             }
-            if (irq < 29) {
+            if (irq < 29 && s->revision == REV_11MPCORE) {
                 value = 0;
             } else if (irq < GIC_INTERNAL) {
                 value = ALL_CPU_MASK;
-- 
2.17.1

From: Thomas Huth <thuth@redhat.com>

These devices are currently causing some problems when a user is trying
to hot-plug or introspect them during runtime. Since these devices can
not be instantiated by the user at all (they need to be wired up in code
instead), we should mark them with user_creatable = false anyway, then we
avoid at least the crashes with the hot-plugging. The introspection problem
will be handled by a separate patch.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1531415537-26037-1-git-send-email-thuth@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/bcm2836.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -XXX,XX +XXX,XX @@ static void bcm283x_class_init(ObjectClass *oc, void *data)
     bc->info = data;
     dc->realize = bcm2836_realize;
     dc->props = bcm2836_props;
+    /* Reason: Must be wired up in code (see raspi_init() function) */
+    dc->user_creatable = false;
 }
 
 static const TypeInfo bcm283x_type_info = {
-- 
2.17.1

From: Guenter Roeck <linux@roeck-us.net>

RX and TX interrupt bits were reversed, resulting in an endless sequence
of serial interupts in the emulated system and the following repeated
error message when booting Linux.

serial8250: too much work for irq61

This results in a boot failure most of the time.

Qemu command line used to reproduce the problem:

qemu-system-aarch64 -M raspi3 -m 1024 \
	-kernel arch/arm64/boot/Image \
	--append "rdinit=/sbin/init console=ttyS1,115200"
	-initrd rootfs.cpio \
	-dtb arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dtb \
	-nographic -monitor null -serial null -serial stdio

This is with arm64:defconfig. The root file system was generated using
buildroot.

NB that this error likely arises from an erratum in the
BCM2835 datasheet where the TX and RX bits were swapped
in the AU_MU_IER_REG description (but correct for IIR):
 https://elinux.org/BCM2835_datasheet_errata#p12

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 1529355846-25102-1-git-send-email-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: added NB about datasheet]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/bcm2835_aux.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/bcm2835_aux.c
+++ b/hw/char/bcm2835_aux.c
@@ -XXX,XX +XXX,XX @@
 #define AUX_MU_BAUD_REG 0x68
 
 /* bits in IER/IIR registers */
-#define TX_INT  0x1
-#define RX_INT  0x2
+#define RX_INT  0x1
+#define TX_INT  0x2
 
 static void bcm2835_aux_update(BCM2835AuxState *s)
 {
-- 
2.17.1

In get_page_addr_code(), we were incorrectly looking in the victim
TLB for an entry which matched the target address for reads, not
for code accesses. This meant that we could hit on a victim TLB
entry that indicated that the address was readable but not
executable, and incorrectly bypass the call to tlb_fill() which
should generate the guest MMU exception. Fix this bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180713141636.18665-2-peter.maydell@linaro.org
---
 accel/tcg/cputlb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
     mmu_idx = cpu_mmu_index(env, true);
     if (unlikely(!tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr))) {
-        if (!VICTIM_TLB_HIT(addr_read, addr)) {
+        if (!VICTIM_TLB_HIT(addr_code, addr)) {
             tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
         }
     }
-- 
2.17.1

In commit 4b1a3e1e34ad97 we added a check for whether the TLB entry
we had following a tlb_fill had the INVALID bit set.  This could
happen in some circumstances because a stale or wrong TLB entry was
pulled out of the victim cache.  However, after commit
68fea038553039e (which prevents stale entries being in the victim
cache) and the previous commit (which ensures we don't incorrectly
hit in the victim cache)) this should never be possible.

Drop the check on TLB_INVALID_MASK from the "is this a TLB_RECHECK?"
condition, and instead assert that the tlb fill procedure has given
us a valid TLB entry (or longjumped out with a guest exception).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180713141636.18665-3-peter.maydell@linaro.org
---
 accel/tcg/cputlb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
         if (!VICTIM_TLB_HIT(addr_code, addr)) {
             tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
         }
+        assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
     }
 
-    if (unlikely((env->tlb_table[mmu_idx][index].addr_code &
-                  (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) {
+    if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) {
         /*
          * This is a TLB_RECHECK access, where the MMU protection
          * covers a smaller range than a target page, and we must
-- 
2.17.1

The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216

for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:

tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000)

----------------------------------------------------------------
target-arm queue:
 * Some mostly M-profile-related code cleanups
 * avocado: Retire the boot_linux.py AArch64 TCG tests
 * hw/arm/smmuv3: Add GBPA register
 * arm/virt: don't try to spell out the accelerator
 * hw/arm: Attach PSPI module to NPCM7XX SoC
 * Some cleanup/refactoring patches aiming towards
   allowing building Arm targets without CONFIG_TCG

----------------------------------------------------------------
Alex Bennée (1):
      tests/avocado: retire the Aarch64 TCG tests from boot_linux.py

Claudio Fontana (3):
      target/arm: rename handle_semihosting to tcg_handle_semihosting
      target/arm: wrap psci call with tcg_enabled
      target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()

Cornelia Huck (1):
      arm/virt: don't try to spell out the accelerator

Fabiano Rosas (7):
      target/arm: Move PC alignment check
      target/arm: Move cpregs code out of cpu.h
      tests/avocado: Skip tests that require a missing accelerator
      tests/avocado: Tag TCG tests with accel:tcg
      target/arm: Use "max" as default cpu for the virt machine with KVM
      tests/qtest: arm-cpu-features: Match tests to required accelerators
      tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG

Hao Wu (3):
      MAINTAINERS: Add myself to maintainers and remove Havard
      hw/ssi: Add Nuvoton PSPI Module
      hw/arm: Attach PSPI module to NPCM7XX SoC

Jean-Philippe Brucker (2):
      hw/arm/smmu-common: Support 64-bit addresses
      hw/arm/smmu-common: Fix TTB1 handling

Mostafa Saleh (1):
      hw/arm/smmuv3: Add GBPA register

Philippe Mathieu-Daudé (12):
      hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
      target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
      target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
      target/arm: Constify ID_PFR1 on user emulation
      target/arm: Convert CPUARMState::eabi to boolean
      target/arm: Avoid resetting CPUARMState::eabi field
      target/arm: Restrict CPUARMState::gicv3state to sysemu
      target/arm: Restrict CPUARMState::arm_boot_info to sysemu
      target/arm: Restrict CPUARMState::nvic to sysemu
      target/arm: Store CPUARMState::nvic as NVICState*
      target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
      hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro,
similarly to automatic conversion from commit 8063396bf3
("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@
 #include "qom/object.h"
 
 #define TYPE_NVIC "armv7m_nvic"
-
-typedef struct NVICState NVICState;
-DECLARE_INSTANCE_CHECKER(NVICState, NVIC,
-                         TYPE_NVIC)
+OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC)
 
 /* Highest permitted number of exceptions (architectural limit) */
 #define NVIC_MAX_VECTORS 512
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return 0;
 }
 
-#else
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    return ARMMMUIdx_MUser;
+}
+
+#else /* !CONFIG_USER_ONLY */
 
 /*
  * What kind of stack write are we doing? This affects how exceptions
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-#endif /* !CONFIG_USER_ONLY */
-
 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
                               bool secstate, bool priv, bool negpri)
 {
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
 }
+
+#endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
are only used for system emulation in m_helper.c.
Move the definitions to avoid prototype forward declarations.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/internals.h | 14 --------
 target/arm/m_helper.c  | 74 +++++++++++++++++++++---------------------
 2 files changed, 37 insertions(+), 51 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
 
 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
 
-/*
- * Return the MMU index for a v7M CPU with all relevant information
- * manually specified.
- */
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri);
-
-/*
- * Return the MMU index for a v7M CPU in the specified security and
- * privilege state.
- */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv);
-
 /* Return the MMU index for a v7M CPU in the specified security state */
 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
 
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
 
 #else /* !CONFIG_USER_ONLY */
 
+static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+                                     bool secstate, bool priv, bool negpri)
+{
+    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
+
+    if (priv) {
+        mmu_idx |= ARM_MMU_IDX_M_PRIV;
+    }
+
+    if (negpri) {
+        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
+    }
+
+    if (secstate) {
+        mmu_idx |= ARM_MMU_IDX_M_S;
+    }
+
+    return mmu_idx;
+}
+
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+                                                       bool secstate, bool priv)
+{
+    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
+/* Return the MMU index for a v7M CPU in the specified security state */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+    bool priv = arm_v7m_is_handler_mode(env) ||
+        !(env->v7m.control[secstate] & 1);
+
+    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
 /*
  * What kind of stack write are we doing? This affects how exceptions
  * generated during the stacking are treated.
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
     return tt_resp;
 }
 
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
-                              bool secstate, bool priv, bool negpri)
-{
-    ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
-
-    if (priv) {
-        mmu_idx |= ARM_MMU_IDX_M_PRIV;
-    }
-
-    if (negpri) {
-        mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
-    }
-
-    if (secstate) {
-        mmu_idx |= ARM_MMU_IDX_M_S;
-    }
-
-    return mmu_idx;
-}
-
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
-                                                bool secstate, bool priv)
-{
-    bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
-
-    return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
-}
-
-/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
-    bool priv = arm_v7m_is_handler_mode(env) ||
-        !(env->v7m.control[secstate] & 1);
-
-    return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
-}
-
 #endif /* !CONFIG_USER_ONLY */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
     }
 }
 
+#ifndef CONFIG_USER_ONLY
 /*
  * We don't know until after realize whether there's a GICv3
  * attached, and that is what registers the gicv3 sysregs.
@@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
     return pfr1;
 }
 
-#ifndef CONFIG_USER_ONLY
 static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_NO_RAW,
               .accessfn = access_aa32_tid3,
+#ifdef CONFIG_USER_ONLY
+              .type = ARM_CP_CONST,
+              .resetvalue = cpu->isar.id_pfr1,
+#else
+              .type = ARM_CP_NO_RAW,
+              .accessfn = access_aa32_tid3,
               .readfn = id_pfr1_read,
-              .writefn = arm_cp_write_ignore },
+              .writefn = arm_cp_write_ignore
+#endif
+            },
             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/user-internals.h | 2 +-
 target/arm/cpu.h            | 2 +-
 linux-user/arm/cpu_loop.c   | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/user-internals.h
+++ b/linux-user/user-internals.h
@@ -XXX,XX +XXX,XX @@ void print_termios(void *arg);
 #ifdef TARGET_ARM
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num)
 {
-    return cpu_env->eabi == 1;
+    return cpu_env->eabi;
 }
 #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32)
 static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; }
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
 
 #if defined(CONFIG_USER_ONLY)
     /* For usermode syscall translation.  */
-    int eabi;
+    bool eabi;
 #endif
 
     struct CPUBreakpoint *cpu_breakpoint[16];
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
             break;
         case EXCP_SWI:
             {
-                env->eabi = 1;
+                env->eabi = true;
                 /* system call */
                 if (env->thumb) {
                     /* Thumb is always EABI style with syscall number in r7 */
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
                          * > 0xfffff and are handled below as out-of-range.
                          */
                         n ^= ARM_SYSCALL_BASE;
-                        env->eabi = 0;
+                        env->eabi = false;
                     }
                 }
 
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

Although the 'eabi' field is only used in user emulation where
CPU reset doesn't occur, it doesn't belong to the area to reset.
Move it after the 'end_reset_fields' for consistency.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     ARMVectorReg zarray[ARM_MAX_VQ * 16];
 #endif
 
-#if defined(CONFIG_USER_ONLY)
-    /* For usermode syscall translation.  */
-    bool eabi;
-#endif
-
     struct CPUBreakpoint *cpu_breakpoint[16];
     struct CPUWatchpoint *cpu_watchpoint[16];
 
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
+#if defined(CONFIG_USER_ONLY)
+    /* For usermode syscall translation.  */
+    bool eabi;
+#endif /* CONFIG_USER_ONLY */
 
 #ifdef TARGET_TAGGED_ADDRESSES
     /* Linux syscall tagged address support */
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

There is no point in using a void pointer to access the NVIC.
Use the real type to avoid casting it while debugging.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h      | 46 ++++++++++++++++++++++---------------------
 hw/intc/armv7m_nvic.c | 38 ++++++++++++-----------------------
 target/arm/cpu.c      |  1 +
 target/arm/m_helper.c |  2 +-
 4 files changed, 39 insertions(+), 48 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags {
 
 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
 
+typedef struct NVICState NVICState;
+
 typedef struct CPUArchState {
     /* Regs for current mode.  */
     uint32_t regs[16];
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
     } sau;
 
 #if !defined(CONFIG_USER_ONLY)
-    void *nvic;
+    NVICState *nvic;
     const struct arm_boot_info *boot_info;
     /* Store GICv3CPUState to access from this struct */
     void *gicv3state;
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
 
 /* Interface between CPU and Interrupt controller.  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(void *opaque);
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
 #else
-static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
     return true;
 }
 #endif
 /**
  * armv7m_nvic_set_pending: mark the specified exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
  * exceptions (exceptions generated in the course of trying to take
  * a different exception).
  */
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
  * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
  * generated in the course of lazy stacking of FP registers.
  */
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_pending_irq_info: return highest priority pending
  *    exception, and whether it targets Secure state
- * @opaque: the NVIC
+ * @s: the NVIC
  * @pirq: set to pending exception number
  * @ptargets_secure: set to whether pending exception targets Secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
  * to true if the current highest priority pending exception should
  * be taken to Secure state, false for NS.
  */
-void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
                                       bool *ptargets_secure);
 /**
  * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Move the current highest priority pending exception from the pending
  * state to the active state, and update v7m.exception to indicate that
  * it is the exception currently being handled.
  */
-void armv7m_nvic_acknowledge_irq(void *opaque);
+void armv7m_nvic_acknowledge_irq(NVICState *s);
 /**
  * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to complete
  * @secure: true if this exception was secure
  *
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque);
  *           0 if there is still an irq active after this one was completed
  * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
  */
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @opaque: the NVIC
+ * @s: the NVIC
  * @irq: the exception number to mark pending
  * @secure: false for non-banked exceptions or for the nonsecure
  * version of a banked exception, true for the secure version of a banked
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
  * interrupt the current execution priority. This controls whether the
  * RDY bit for it in the FPCCR is set.
  */
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
 /**
  * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @opaque: the NVIC
+ * @s: the NVIC
  *
  * Returns: the raw execution priority as defined by the v8M architecture.
  * This is the execution priority minus the effects of AIRCR.PRIS,
  * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
  * (v8M ARM ARM I_PKLD.)
  */
-int armv7m_nvic_raw_execution_priority(void *opaque);
+int armv7m_nvic_raw_execution_priority(NVICState *s);
 /**
  * armv7m_nvic_neg_prio_requested: return true if the requested execution
  * priority is negative for the specified security state.
- * @opaque: the NVIC
+ * @s: the NVIC
  * @secure: the security state to test
  * This corresponds to the pseudocode IsReqExecPriNeg().
  */
 #ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
 #else
-static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     return false;
 }
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s)
     return MIN(running, s->exception_prio);
 }
 
-bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
 {
     /* Return true if the requested execution priority is negative
      * for the specified security state, ie that security state
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
      * mean we don't allow FAULTMASK_NS to actually make the execution
      * priority negative). Compare pseudocode IsReqExcPriNeg().
      */
-    NVICState *s = opaque;
-
     if (s->cpu->env.v7m.faultmask[secure]) {
         return true;
     }
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
     return false;
 }
 
-bool armv7m_nvic_can_take_pending_exception(void *opaque)
+bool armv7m_nvic_can_take_pending_exception(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return nvic_exec_prio(s) > nvic_pending_prio(s);
 }
 
-int armv7m_nvic_raw_execution_priority(void *opaque)
+int armv7m_nvic_raw_execution_priority(NVICState *s)
 {
-    NVICState *s = opaque;
-
     return s->exception_prio;
 }
 
@@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s)
  * if @secure is true and @irq does not specify one of the fixed set
  * of architecturally banked exceptions.
  */
-static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
+static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
@@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
     }
 }
 
-void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, false);
+    do_armv7m_nvic_set_pending(s, irq, secure, false);
 }
 
-void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure)
 {
-    do_armv7m_nvic_set_pending(opaque, irq, secure, true);
+    do_armv7m_nvic_set_pending(s, irq, secure, true);
 }
 
-void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure)
 {
     /*
      * Pend an exception during lazy FP stacking. This differs
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
      * whether we should escalate depends on the saved context
      * in the FPCCR register, not on the current state of the CPU/NVIC.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     bool targets_secure;
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
 }
 
 /* Make pending IRQ active.  */
-void armv7m_nvic_acknowledge_irq(void *opaque)
+void armv7m_nvic_acknowledge_irq(NVICState *s)
 {
-    NVICState *s = (NVICState *)opaque;
     CPUARMState *env = &s->cpu->env;
     const int pending = s->vectpending;
     const int running = nvic_exec_prio(s);
@@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s)
         exc_targets_secure(s, s->vectpending);
 }
 
-void armv7m_nvic_get_pending_irq_info(void *opaque,
+void armv7m_nvic_get_pending_irq_info(NVICState *s,
                                       int *pirq, bool *ptargets_secure)
 {
-    NVICState *s = (NVICState *)opaque;
     const int pending = s->vectpending;
     bool targets_secure;
 
@@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque,
     *pirq = pending;
 }
 
-int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure)
 {
-    NVICState *s = (NVICState *)opaque;
     VecInfo *vec = NULL;
     int ret = 0;
 
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
     return ret;
 }
 
-bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure)
 {
     /*
      * Return whether an exception is "ready", i.e. it is enabled and is
@@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
      * for non-banked exceptions secure is always false; for banked exceptions
      * it indicates which of the exceptions is required.
      */
-    NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
     int running = nvic_exec_prio(s);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#include "hw/intc/armv7m_nvic.h"
 #endif
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
      * that we will need later in order to do lazy FP reg stacking.
      */
     bool is_secure = env->v7m.secure;
-    void *nvic = env->nvic;
+    NVICState *nvic = env->nvic;
     /*
      * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits
      * are banked and we want to update the bit in the bank for the
-- 
2.34.1

From: Philippe Mathieu-Daudé <philmd@linaro.org>

While dozens of files include "cpu.h", only 3 files require
these NVIC helper declarations.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230206223502.25122-12-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++
 target/arm/cpu.h              | 123 ----------------------------------
 target/arm/cpu.c              |   4 +-
 target/arm/cpu_tcg.c          |   3 +
 target/arm/m_helper.c         |   3 +
 5 files changed, 132 insertions(+), 124 deletions(-)

diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -XXX,XX +XXX,XX @@ struct NVICState {
     qemu_irq sysresetreq;
 };
 
+/* Interface between CPU and Interrupt controller.  */
+/**
+ * armv7m_nvic_set_pending: mark the specified exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Marks the specified exception as pending. Note that we will assert()
+ * if @secure is true and @irq does not specify one of the fixed set
+ * of architecturally banked exceptions.
+ */
+void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_derived: mark this derived exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for derived
+ * exceptions (exceptions generated in the course of trying to take
+ * a different exception).
+ */
+void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
+ * generated in the course of lazy stacking of FP registers.
+ */
+void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_pending_irq_info: return highest priority pending
+ *    exception, and whether it targets Secure state
+ * @s: the NVIC
+ * @pirq: set to pending exception number
+ * @ptargets_secure: set to whether pending exception targets Secure
+ *
+ * This function writes the number of the highest priority pending
+ * exception (the one which would be made active by
+ * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
+ * to true if the current highest priority pending exception should
+ * be taken to Secure state, false for NS.
+ */
+void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
+                                      bool *ptargets_secure);
+/**
+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
+ * @s: the NVIC
+ *
+ * Move the current highest priority pending exception from the pending
+ * state to the active state, and update v7m.exception to indicate that
+ * it is the exception currently being handled.
+ */
+void armv7m_nvic_acknowledge_irq(NVICState *s);
+/**
+ * armv7m_nvic_complete_irq: complete specified interrupt or exception
+ * @s: the NVIC
+ * @irq: the exception number to complete
+ * @secure: true if this exception was secure
+ *
+ * Returns: -1 if the irq was not active
+ *           1 if completing this irq brought us back to base (no active irqs)
+ *           0 if there is still an irq active after this one was completed
+ * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
+ */
+int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
+ * @s: the NVIC
+ * @irq: the exception number to mark pending
+ * @secure: false for non-banked exceptions or for the nonsecure
+ * version of a banked exception, true for the secure version of a banked
+ * exception.
+ *
+ * Return whether an exception is "ready", i.e. whether the exception is
+ * enabled and is configured at a priority which would allow it to
+ * interrupt the current execution priority. This controls whether the
+ * RDY bit for it in the FPCCR is set.
+ */
+bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
+/**
+ * armv7m_nvic_raw_execution_priority: return the raw execution priority
+ * @s: the NVIC
+ *
+ * Returns: the raw execution priority as defined by the v8M architecture.
+ * This is the execution priority minus the effects of AIRCR.PRIS,
+ * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
+ * (v8M ARM ARM I_PKLD.)
+ */
+int armv7m_nvic_raw_execution_priority(NVICState *s);
+/**
+ * armv7m_nvic_neg_prio_requested: return true if the requested execution
+ * priority is negative for the specified security state.
+ * @s: the NVIC
+ * @secure: the security state to test
+ * This corresponds to the pseudocode IsReqExecPriNeg().
+ */
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
+#else
+static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
+{
+    return false;
+}
+#endif
+#ifndef CONFIG_USER_ONLY
+bool armv7m_nvic_can_take_pending_exception(NVICState *s);
+#else
+static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
+{
+    return true;
+}
+#endif
+
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface between CPU and Interrupt controller.  */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_can_take_pending_exception(NVICState *s);
-#else
-static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s)
-{
-    return true;
-}
-#endif
-/**
- * armv7m_nvic_set_pending: mark the specified exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Marks the specified exception as pending. Note that we will assert()
- * if @secure is true and @irq does not specify one of the fixed set
- * of architecturally banked exceptions.
- */
-void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_derived: mark this derived exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for derived
- * exceptions (exceptions generated in the course of trying to take
- * a different exception).
- */
-void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
- * generated in the course of lazy stacking of FP registers.
- */
-void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_pending_irq_info: return highest priority pending
- *    exception, and whether it targets Secure state
- * @s: the NVIC
- * @pirq: set to pending exception number
- * @ptargets_secure: set to whether pending exception targets Secure
- *
- * This function writes the number of the highest priority pending
- * exception (the one which would be made active by
- * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
- * to true if the current highest priority pending exception should
- * be taken to Secure state, false for NS.
- */
-void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq,
-                                      bool *ptargets_secure);
-/**
- * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
- * @s: the NVIC
- *
- * Move the current highest priority pending exception from the pending
- * state to the active state, and update v7m.exception to indicate that
- * it is the exception currently being handled.
- */
-void armv7m_nvic_acknowledge_irq(NVICState *s);
-/**
- * armv7m_nvic_complete_irq: complete specified interrupt or exception
- * @s: the NVIC
- * @irq: the exception number to complete
- * @secure: true if this exception was secure
- *
- * Returns: -1 if the irq was not active
- *           1 if completing this irq brought us back to base (no active irqs)
- *           0 if there is still an irq active after this one was completed
- * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
- */
-int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
- * @s: the NVIC
- * @irq: the exception number to mark pending
- * @secure: false for non-banked exceptions or for the nonsecure
- * version of a banked exception, true for the secure version of a banked
- * exception.
- *
- * Return whether an exception is "ready", i.e. whether the exception is
- * enabled and is configured at a priority which would allow it to
- * interrupt the current execution priority. This controls whether the
- * RDY bit for it in the FPCCR is set.
- */
-bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure);
-/**
- * armv7m_nvic_raw_execution_priority: return the raw execution priority
- * @s: the NVIC
- *
- * Returns: the raw execution priority as defined by the v8M architecture.
- * This is the execution priority minus the effects of AIRCR.PRIS,
- * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
- * (v8M ARM ARM I_PKLD.)
- */
-int armv7m_nvic_raw_execution_priority(NVICState *s);
-/**
- * armv7m_nvic_neg_prio_requested: return true if the requested execution
- * priority is negative for the specified security state.
- * @s: the NVIC
- * @secure: the security state to test
- * This corresponds to the pseudocode IsReqExecPriNeg().
- */
-#ifndef CONFIG_USER_ONLY
-bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure);
-#else
-static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure)
-{
-    return false;
-}
-#endif
-
 /* Interface for defining coprocessor registers.
  * Registers are defined in tables of arm_cp_reginfo structs
  * which are passed to define_arm_cp_regs().
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #include "hw/boards.h"
+#ifdef CONFIG_TCG
 #include "hw/intc/armv7m_nvic.h"
-#endif
+#endif /* CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
 #include "sysemu/tcg.h"
 #include "sysemu/qtest.h"
 #include "sysemu/hw_accel.h"
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #endif
 #include "cpregs.h"
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 
 /* Share AArch32 -cpu max features with AArch64. */
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #include "semihosting/common-semi.h"
 #endif
+#if !defined(CONFIG_USER_ONLY)
+#include "hw/intc/armv7m_nvic.h"
+#endif
 
 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
                          uint32_t reg, uint32_t val)
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

The two TCG tests for GICv2 and GICv3 are very heavy weight distros
that take a long time to boot up, especially for an --enable-debug
build. The total code coverage they give is:

Overall coverage rate:
    lines......: 11.2% (59584 of 530123 lines)
    functions..: 15.0% (7436 of 49443 functions)
    branches...: 6.3% (19273 of 303933 branches)

We already get pretty close to that with the machine_aarch64_virt
tests which only does one full boot (~120s vs ~600s) of alpine. We
expand the kernel+initrd boot (~8s) to test both GICs and also add an
RNG device and a block device to generate a few IRQs and exercise the
storage layer. With that we get to a coverage of:

Overall coverage rate:
    lines......: 11.0% (58121 of 530123 lines)
    functions..: 14.9% (7343 of 49443 functions)
    branches...: 6.0% (18269 of 303933 branches)

which I feel is close enough given the massive time saving. If we want
to target any more sub-systems we can use lighter weight more directed
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux.py           | 48 ++++----------------
 tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++---
 2 files changed, 65 insertions(+), 46 deletions(-)

diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux.py
+++ b/tests/avocado/boot_linux.py
@@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self):
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
-# For Aarch64 we only boot KVM tests in CI as the TCG tests are very
-# heavyweight. There are lighter weight distros which we use in the
-# machine_aarch64_virt.py tests.
+# For Aarch64 we only boot KVM tests in CI as booting the current
+# Fedora OS in TCG tests is very heavyweight. There are lighter weight
+# distros which we use in the machine_aarch64_virt.py tests.
 class BootLinuxAarch64(LinuxTest):
     """
     :avocado: tags=arch:aarch64
     :avocado: tags=machine:virt
-    :avocado: tags=machine:gic-version=2
     """
     timeout = 720
 
-    def add_common_args(self):
-        self.vm.add_args('-bios',
-                         os.path.join(BUILD_DIR, 'pc-bios',
-                                      'edk2-aarch64-code.fd'))
-        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
-        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv2(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv2
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=2")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
-    @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab')
-    def test_fedora_cloud_tcg_gicv3(self):
-        """
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
-        :avocado: tags=device:gicv3
-        """
-        self.require_accelerator("tcg")
-        self.vm.add_args("-accel", "tcg")
-        self.vm.add_args("-cpu", "max,lpa2=off")
-        self.vm.add_args("-machine", "virt,gic-version=3")
-        self.add_common_args()
-        self.launch_and_wait(set_up_ssh_connection=False)
-
     def test_virt_kvm(self):
         """
         :avocado: tags=accel:kvm
@@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self):
         self.require_accelerator("kvm")
         self.vm.add_args("-accel", "kvm")
         self.vm.add_args("-machine", "virt,gic-version=host")
-        self.add_common_args()
+        self.vm.add_args('-bios',
+                         os.path.join(BUILD_DIR, 'pc-bios',
+                                      'edk2-aarch64-code.fd'))
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom')
         self.launch_and_wait(set_up_ssh_connection=False)
 
 
diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/machine_aarch64_virt.py
+++ b/tests/avocado/machine_aarch64_virt.py
@@ -XXX,XX +XXX,XX @@
 
 import time
 import os
+import logging
 
 from avocado_qemu import QemuSystemTest
 from avocado_qemu import wait_for_console_pattern
 from avocado_qemu import exec_command
 from avocado_qemu import BUILD_DIR
+from avocado.utils import process
+from avocado.utils.path import find_command
 
 class Aarch64VirtMachine(QemuSystemTest):
     KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
@@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self):
         self.wait_for_console_pattern('Welcome to Alpine Linux 3.16')
 
 
-    def test_aarch64_virt(self):
+    def common_aarch64_virt(self, machine):
         """
-        :avocado: tags=arch:aarch64
-        :avocado: tags=machine:virt
-        :avocado: tags=accel:tcg
-        :avocado: tags=cpu:max
+        Common code to launch basic virt machine with kernel+initrd
+        and a scratch disk.
         """
+        logger = logging.getLogger('aarch64_virt')
+
         kernel_url = ('https://fileserver.linaro.org/s/'
                       'z6B2ARM7DQT3HWN/download')
-
         kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347'
         kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
 
@@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self):
                                'console=ttyAMA0')
         self.require_accelerator("tcg")
         self.vm.add_args('-cpu', 'max,pauth-impdef=on',
+                         '-machine', machine,
                          '-accel', 'tcg',
                          '-kernel', kernel_path,
                          '-append', kernel_command_line)
+
+        # A RNG offers an easy way to generate a few IRQs
+        self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0')
+        self.vm.add_args('-object',
+                         'rng-random,id=rng0,filename=/dev/urandom')
+
+        # Also add a scratch block device
+        logger.info('creating scratch qcow2 image')
+        image_path = os.path.join(self.workdir, 'scratch.qcow2')
+        qemu_img = os.path.join(BUILD_DIR, 'qemu-img')
+        if not os.path.exists(qemu_img):
+            qemu_img = find_command('qemu-img', False)
+        if qemu_img is False:
+            self.cancel('Could not find "qemu-img", which is required to '
+                        'create the temporary qcow2 image')
+        cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path)
+        process.run(cmd)
+
+        # Add the device
+        self.vm.add_args('-blockdev',
+                         f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch")
+        self.vm.add_args('-device',
+                         'virtio-blk-device,drive=scratch')
+
         self.vm.launch()
         self.wait_for_console_pattern('Welcome to Buildroot')
         time.sleep(0.1)
         exec_command(self, 'root')
         time.sleep(0.1)
+        exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4')
+        time.sleep(0.1)
+        exec_command(self, 'md5sum /dev/vda')
+        time.sleep(0.1)
+        exec_command(self, 'cat /proc/interrupts')
+        time.sleep(0.1)
         exec_command(self, 'cat /proc/self/maps')
         time.sleep(0.1)
+
+    def test_aarch64_virt_gicv3(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic_version=3")
+
+    def test_aarch64_virt_gicv2(self):
+        """
+        :avocado: tags=arch:aarch64
+        :avocado: tags=machine:virt
+        :avocado: tags=accel:tcg
+        :avocado: tags=cpu:max
+        """
+        self.common_aarch64_virt("virt,gic-version=2")
-- 
2.34.1

From: Mostafa Saleh <smostafa@google.com>

GBPA register can be used to globally abort all
transactions.

It is described in the SMMU manual in "6.3.14 SMMU_GBPA".
ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to
be zero(Do not abort incoming transactions).

Other fields have default values of Use Incoming.

If UPDATE is not set, the write is ignored. This is the only permitted
behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure)

As this patch adds a new state to the SMMU (GBPA), it is added
in a new subsection for forward migration compatibility.
GBPA is only migrated if its value is different from the reset value.
It does this to be backward migration compatible if SW didn't write
the register.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214094009.2445653-1-smostafa@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3-internal.h |  7 +++++++
 include/hw/arm/smmuv3.h  |  1 +
 hw/arm/smmuv3.c          | 43 +++++++++++++++++++++++++++++++++++++++-
 3 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -XXX,XX +XXX,XX @@ REG32(CR0ACK,              0x24)
 REG32(CR1,                 0x28)
 REG32(CR2,                 0x2c)
 REG32(STATUSR,             0x40)
+REG32(GBPA,                0x44)
+    FIELD(GBPA, ABORT,        20, 1)
+    FIELD(GBPA, UPDATE,       31, 1)
+
+/* Use incoming. */
+#define SMMU_GBPA_RESET_VAL 0x1000
+
 REG32(IRQ_CTRL,            0x50)
     FIELD(IRQ_CTRL, GERROR_IRQEN,        0, 1)
     FIELD(IRQ_CTRL, PRI_IRQEN,           1, 1)
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -XXX,XX +XXX,XX @@ struct SMMUv3State {
     uint32_t cr[3];
     uint32_t cr0ack;
     uint32_t statusr;
+    uint32_t gbpa;
     uint32_t irq_ctrl;
     uint32_t gerror;
     uint32_t gerrorn;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s)
     s->gerror = 0;
     s->gerrorn = 0;
     s->statusr = 0;
+    s->gbpa = SMMU_GBPA_RESET_VAL;
 }
 
 static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf,
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
     qemu_mutex_lock(&s->mutex);
 
     if (!smmu_enabled(s)) {
-        status = SMMU_TRANS_DISABLE;
+        if (FIELD_EX32(s->gbpa, GBPA, ABORT)) {
+            status = SMMU_TRANS_ABORT;
+        } else {
+            status = SMMU_TRANS_DISABLE;
+        }
         goto epilogue;
     }
 
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,
     case A_GERROR_IRQ_CFG2:
         s->gerror_irq_cfg2 = data;
         return MEMTX_OK;
+    case A_GBPA:
+        /*
+         * If UPDATE is not set, the write is ignored. This is the only
+         * permitted behavior in SMMUv3.2 and later.
+         */
+        if (data & R_GBPA_UPDATE_MASK) {
+            /* Ignore update bit as write is synchronous. */
+            s->gbpa = data & ~R_GBPA_UPDATE_MASK;
+        }
+        return MEMTX_OK;
     case A_STRTAB_BASE: /* 64b */
         s->strtab_base = deposit64(s->strtab_base, 0, 32, data);
         return MEMTX_OK;
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
     case A_STATUSR:
         *data = s->statusr;
         return MEMTX_OK;
+    case A_GBPA:
+        *data = s->gbpa;
+        return MEMTX_OK;
     case A_IRQ_CTRL:
     case A_IRQ_CTRL_ACK:
         *data = s->irq_ctrl;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = {
     },
 };
 
+static bool smmuv3_gbpa_needed(void *opaque)
+{
+    SMMUv3State *s = opaque;
+
+    /* Only migrate GBPA if it has different reset value. */
+    return s->gbpa != SMMU_GBPA_RESET_VAL;
+}
+
+static const VMStateDescription vmstate_gbpa = {
+    .name = "smmuv3/gbpa",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = smmuv3_gbpa_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(gbpa, SMMUv3State),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_smmuv3 = {
     .name = "smmuv3",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = {
 
         VMSTATE_END_OF_LIST(),
     },
+    .subsections = (const VMStateDescription * []) {
+        &vmstate_gbpa,
+        NULL
+    }
 };
 
 static void smmuv3_instance_init(Object *obj)
-- 
2.34.1

From: Cornelia Huck <cohuck@redhat.com>

Just use current_accel_name() directly.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
     if (vms->secure && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Security extensions (TrustZone) to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Virtualization extensions to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
     if (vms->mte && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "MTE to the guest CPU",
-                     kvm_enabled() ? "KVM" : "HVF");
+                     current_accel_name());
         exit(1);
     }
 
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Chris Rauer <crauer@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-3-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                |   6 +-
 include/hw/ssi/npcm_pspi.h |  53 +++++++++
 hw/ssi/npcm_pspi.c         | 221 +++++++++++++++++++++++++++++++++++++
 hw/ssi/meson.build         |   2 +-
 hw/ssi/trace-events        |   5 +
 5 files changed, 283 insertions(+), 4 deletions(-)
 create mode 100644 include/hw/ssi/npcm_pspi.h
 create mode 100644 hw/ssi/npcm_pspi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com>
 M: Hao Wu <wuhaotsh@google.com>
 L: qemu-arm@nongnu.org
 S: Supported
-F: hw/*/npcm7xx*
-F: include/hw/*/npcm7xx*
-F: tests/qtest/npcm7xx*
+F: hw/*/npcm*
+F: include/hw/*/npcm*
+F: tests/qtest/npcm*
 F: pc-bios/npcm7xx_bootrom.bin
 F: roms/vbootrom
 F: docs/system/arm/nuvoton.rst
diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/ssi/npcm_pspi.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton Peripheral SPI Module
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM_PSPI_H
+#define NPCM_PSPI_H
+
+#include "hw/ssi/ssi.h"
+#include "hw/sysbus.h"
+
+/*
+ * Number of registers in our device state structure. Don't change this without
+ * incrementing the version_id in the vmstate.
+ */
+#define NPCM_PSPI_NR_REGS 3
+
+/**
+ * NPCMPSPIState - Device state for one Flash Interface Unit.
+ * @parent: System bus device.
+ * @mmio: Memory region for register access.
+ * @spi: The SPI bus mastered by this controller.
+ * @regs: Register contents.
+ * @irq: The interrupt request queue for this module.
+ *
+ * Each PSPI has a shared bank of registers, and controls up to four chip
+ * selects. Each chip select has a dedicated memory region which may be used to
+ * read and write the flash connected to that chip select as if it were memory.
+ */
+typedef struct NPCMPSPIState {
+    SysBusDevice parent;
+
+    MemoryRegion mmio;
+
+    SSIBus *spi;
+    uint16_t regs[NPCM_PSPI_NR_REGS];
+    qemu_irq irq;
+} NPCMPSPIState;
+
+#define TYPE_NPCM_PSPI "npcm-pspi"
+OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI)
+
+#endif /* NPCM_PSPI_H */
diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/ssi/npcm_pspi.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Nuvoton NPCM Peripheral SPI Module (PSPI)
+ *
+ * Copyright 2023 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/irq.h"
+#include "hw/registerfields.h"
+#include "hw/ssi/npcm_pspi.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#include "trace.h"
+
+REG16(PSPI_DATA, 0x0)
+REG16(PSPI_CTL1, 0x2)
+    FIELD(PSPI_CTL1, SPIEN, 0,  1)
+    FIELD(PSPI_CTL1, MOD,   2,  1)
+    FIELD(PSPI_CTL1, EIR,   5,  1)
+    FIELD(PSPI_CTL1, EIW,   6,  1)
+    FIELD(PSPI_CTL1, SCM,   7,  1)
+    FIELD(PSPI_CTL1, SCIDL, 8,  1)
+    FIELD(PSPI_CTL1, SCDV,  9,  7)
+REG16(PSPI_STAT, 0x4)
+    FIELD(PSPI_STAT, BSY,  0,  1)
+    FIELD(PSPI_STAT, RBF,  1,  1)
+
+static void npcm_pspi_update_irq(NPCMPSPIState *s)
+{
+    int level = 0;
+
+    /* Only fire IRQ when the module is enabled. */
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) {
+        /* Update interrupt as BSY is cleared. */
+        if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) {
+            level = 1;
+        }
+
+        /* Update interrupt as RBF is set. */
+        if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) &&
+            FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) {
+            level = 1;
+        }
+    }
+    qemu_set_irq(s->irq, level);
+}
+
+static uint16_t npcm_pspi_read_data(NPCMPSPIState *s)
+{
+    uint16_t value = s->regs[R_PSPI_DATA];
+
+    /* Clear stat bits as the value are read out. */
+    s->regs[R_PSPI_STAT] = 0;
+
+    return value;
+}
+
+static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data)
+{
+    uint16_t value = 0;
+
+    if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) {
+        value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8;
+    }
+    value |= ssi_transfer(s->spi, extract16(data, 0, 8));
+    s->regs[R_PSPI_DATA] = value;
+
+    /* Mark data as available */
+    s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK;
+}
+
+/* Control register read handler. */
+static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr,
+                                    unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value;
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        value = npcm_pspi_read_data(s);
+        break;
+
+    case A_PSPI_CTL1:
+        value = s->regs[R_PSPI_CTL1];
+        break;
+
+    case A_PSPI_STAT:
+        value = s->regs[R_PSPI_STAT];
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return 0;
+    }
+    trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value);
+    npcm_pspi_update_irq(s);
+
+    return value;
+}
+
+/* Control register write handler. */
+static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v,
+                                 unsigned int size)
+{
+    NPCMPSPIState *s = opaque;
+    uint16_t value = v;
+
+    trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value);
+
+    switch (addr) {
+    case A_PSPI_DATA:
+        npcm_pspi_write_data(s, value);
+        break;
+
+    case A_PSPI_CTL1:
+        s->regs[R_PSPI_CTL1] = value;
+        break;
+
+    case A_PSPI_STAT:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to read-only register PSPI_STAT: 0x%08"
+                      PRIx64 "\n", DEVICE(s)->canonical_path, v);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: write to invalid offset 0x%" PRIx64 "\n",
+                      DEVICE(s)->canonical_path, addr);
+        return;
+    }
+    npcm_pspi_update_irq(s);
+}
+
+static const MemoryRegionOps npcm_pspi_ctrl_ops = {
+    .read = npcm_pspi_ctrl_read,
+    .write = npcm_pspi_ctrl_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 1,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+    .impl = {
+        .min_access_size = 2,
+        .max_access_size = 2,
+        .unaligned = false,
+    },
+};
+
+static void npcm_pspi_enter_reset(Object *obj, ResetType type)
+{
+    NPCMPSPIState *s = NPCM_PSPI(obj);
+
+    trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type);
+    memset(s->regs, 0, sizeof(s->regs));
+}
+
+static void npcm_pspi_realize(DeviceState *dev, Error **errp)
+{
+    NPCMPSPIState *s = NPCM_PSPI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    Object *obj = OBJECT(dev);
+
+    s->spi = ssi_create_bus(dev, "pspi");
+    memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s,
+                          "mmio", 4 * KiB);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_npcm_pspi = {
+    .name = "npcm-pspi",
+    .version_id = 0,
+    .minimum_version_id = 0,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+
+static void npcm_pspi_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "NPCM Peripheral SPI Module";
+    dc->realize = npcm_pspi_realize;
+    dc->vmsd = &vmstate_npcm_pspi;
+    rc->phases.enter = npcm_pspi_enter_reset;
+}
+
+static const TypeInfo npcm_pspi_types[] = {
+    {
+        .name = TYPE_NPCM_PSPI,
+        .parent = TYPE_SYS_BUS_DEVICE,
+        .instance_size = sizeof(NPCMPSPIState),
+        .class_init = npcm_pspi_class_init,
+    },
+};
+DEFINE_TYPES(npcm_pspi_types);
diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/meson.build
+++ b/hw/ssi/meson.build
@@ -XXX,XX +XXX,XX @@
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c'))
 softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c'))
-softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c'))
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c'))
 softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c'))
 softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c'))
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset:
 npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
 
+# npcm_pspi.c
+npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d"
+npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16
+
 # ibex_spi_host.c
 
 ibex_spi_host_reset(const char *msg) "%s"
-- 
2.34.1

From: Hao Wu <wuhaotsh@google.com>

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>
Message-id: 20230208235433.3989937-4-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/nuvoton.rst |  2 +-
 include/hw/arm/npcm7xx.h    |  2 ++
 hw/arm/npcm7xx.c            | 25 +++++++++++++++++++++++--
 3 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/nuvoton.rst
+++ b/docs/system/arm/nuvoton.rst
@@ -XXX,XX +XXX,XX @@ Supported devices
  * SMBus controller (SMBF)
  * Ethernet controller (EMC)
  * Tachometer
+ * Peripheral SPI controller (PSPI)
 
 Missing devices
 ---------------
@@ -XXX,XX +XXX,XX @@ Missing devices
 
  * Ethernet controller (GMAC)
  * USB device (USBD)
- * Peripheral SPI controller (PSPI)
  * SD/MMC host
  * PECI interface
  * PCI and PCIe root complex and bridges
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/nvram/npcm7xx_otp.h"
 #include "hw/timer/npcm7xx_timer.h"
 #include "hw/ssi/npcm7xx_fiu.h"
+#include "hw/ssi/npcm_pspi.h"
 #include "hw/usb/hcd-ehci.h"
 #include "hw/usb/hcd-ohci.h"
 #include "target/arm/cpu.h"
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxState {
     NPCM7xxFIUState     fiu[2];
     NPCM7xxEMCState     emc[2];
     NPCM7xxSDHCIState   mmc;
+    NPCMPSPIState       pspi[2];
 };
 
 #define TYPE_NPCM7XX    "npcm7xx"
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
     NPCM7XX_EMC1RX_IRQ          = 15,
     NPCM7XX_EMC1TX_IRQ,
     NPCM7XX_MMC_IRQ             = 26,
+    NPCM7XX_PSPI2_IRQ           = 28,
+    NPCM7XX_PSPI1_IRQ           = 31,
     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
     NPCM7XX_TIMER1_IRQ,
     NPCM7XX_TIMER2_IRQ,
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = {
     0xf0826000,
 };
 
+/* Register base address for each PSPI Module */
+static const hwaddr npcm7xx_pspi_addr[] = {
+    0xf0200000,
+    0xf0201000,
+};
+
 static const struct {
     hwaddr regs_addr;
     uint32_t unconnected_pins;
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
     }
 
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
+    }
+
     object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
 }
 
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0,
             npcm7xx_irq(s, NPCM7XX_MMC_IRQ));
 
+    /* PSPI */
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi));
+    for (i = 0; i < ARRAY_SIZE(s->pspi); i++) {
+        SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]);
+        int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ;
+
+        sysbus_realize(sbd, &error_abort);
+        sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]);
+        sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+    }
+
     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
-    create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set. Ensure the IOMMU region covers all 64 bits.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 2 --
 hw/arm/smmu-common.c         | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@
 #define SMMU_PCI_DEVFN_MAX    256
 #define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
 
-#define SMMU_MAX_VA_BITS      48
-
 /*
  * Page table walk error types
  */
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
 
         memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu),
                                  s->mrtypename,
-                                 OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS);
+                                 OBJECT(s), name, UINT64_MAX);
         address_space_init(&sdev->as,
                            MEMORY_REGION(&sdev->iommu), name);
         trace_smmu_add_mr(name);
-- 
2.34.1

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Addresses targeting the second translation table (TTB1) in the SMMU have
all upper bits set (except for the top byte when TBI is enabled). Fix
the TTB1 check.

Reported-by: Ola Hugosson <ola.hugosson@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova)
         /* there is a ttbr0 region and we are in it (high bits all zero) */
         return &cfg->tt[0];
     } else if (cfg->tt[1].tsz &&
-           !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) {
+        sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) {
         /* there is a ttbr1 region and we are in it (high bits all one) */
         return &cfg->tt[1];
     } else if (!cfg->tt[0].tsz) {
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

make it clearer from the name that this is a tcg-only function.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
  * trapped to the hypervisor in KVM.
  */
 #ifdef CONFIG_TCG
-static void handle_semihosting(CPUState *cs)
+static void tcg_handle_semihosting(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
      */
 #ifdef CONFIG_TCG
     if (cs->exception_index == EXCP_SEMIHOST) {
-        handle_semihosting(cs);
+        tcg_handle_semihosting(cs);
         return;
     }
 #endif
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "sysemu/cpu-timers.h"
 #include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
 #include "qapi/qapi-commands-machine-target.h"
 #include "qapi/error.h"
 #include "qemu/guest-random.h"
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
                       env->exception.syndrome);
     }
 
-    if (arm_is_psci_call(cpu, cs->exception_index)) {
+    if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) {
         arm_handle_psci_call(cpu);
         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
         return;
-- 
2.34.1

From: Claudio Fontana <cfontana@suse.de>

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
     unsigned int cur_el = arm_current_el(env);
     int rt;
 
-    /*
-     * Note that new_el can never be 0.  If cur_el is 0, then
-     * el0_a64 is is_a64(), else el0_a64 is ignored.
-     */
-    aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    if (tcg_enabled()) {
+        /*
+         * Note that new_el can never be 0.  If cur_el is 0, then
+         * el0_a64 is is_a64(), else el0_a64 is ignored.
+         */
+        aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+    }
 
     if (cur_el < new_el) {
         /*
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/machine.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
+    /*
+     * Misaligned thumb pc is architecturally impossible. Fail the
+     * incoming migration. For TCG it would trigger the assert in
+     * thumb_tr_translate_insn().
+     */
+    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
+        return -1;
+    }
+
     hw_breakpoint_update_all(cpu);
     hw_watchpoint_update_all(cpu);
 
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
         }
     }
 
-    /*
-     * Misaligned thumb pc is architecturally impossible.
-     * We have an assert in thumb_tr_translate_insn to verify this.
-     * Fail an incoming migrate to avoid this assert.
-     */
-    if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
-        return -1;
-    }
-
     if (!kvm_enabled()) {
         pmu_op_finish(&cpu->env);
     }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have
a cpregs.h header which is more suitable for this code.

Code moved verbatim.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++
 target/arm/cpu.h    | 91 -----------------------------------------
 2 files changed, 98 insertions(+), 91 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ enum {
     ARM_CP_SME                   = 1 << 19,
 };
 
+/*
+ * Interface for defining coprocessor registers.
+ * Registers are defined in tables of arm_cp_reginfo structs
+ * which are passed to define_arm_cp_regs().
+ */
+
+/*
+ * When looking up a coprocessor register we look for it
+ * via an integer which encodes all of:
+ *  coprocessor number
+ *  Crn, Crm, opc1, opc2 fields
+ *  32 or 64 bit register (ie is it accessed via MRC/MCR
+ *    or via MRRC/MCRR?)
+ *  non-secure/secure bank (AArch32 only)
+ * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
+ * (In this case crn and opc2 should be zero.)
+ * For AArch64, there is no 32/64 bit size distinction;
+ * instead all registers have a 2 bit op0, 3 bit op1 and op2,
+ * and 4 bit CRn and CRm. The encoding patterns are chosen
+ * to be easy to convert to and from the KVM encodings, and also
+ * so that the hashtable can contain both AArch32 and AArch64
+ * registers (to allow for interprocessing where we might run
+ * 32 bit code on a 64 bit core).
+ */
+/*
+ * This bit is private to our hashtable cpreg; in KVM register
+ * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
+ * in the upper bits of the 64 bit ID.
+ */
+#define CP_REG_AA64_SHIFT 28
+#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
+
+/*
+ * To enable banking of coprocessor registers depending on ns-bit we
+ * add a bit to distinguish between secure and non-secure cpregs in the
+ * hashtable.
+ */
+#define CP_REG_NS_SHIFT 29
+#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
+
+#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
+    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
+     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
+
+#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
+    (CP_REG_AA64_MASK |                                 \
+     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
+     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
+     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
+     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
+     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
+     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+/*
+ * Convert a full 64 bit KVM register ID to the truncated 32 bit
+ * version used as a key for the coprocessor register hashtable
+ */
+static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
+{
+    uint32_t cpregid = kvmid;
+    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
+        cpregid |= CP_REG_AA64_MASK;
+    } else {
+        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
+            cpregid |= (1 << 15);
+        }
+
+        /*
+         * KVM is always non-secure so add the NS flag on AArch32 register
+         * entries.
+         */
+         cpregid |= 1 << CP_REG_NS_SHIFT;
+    }
+    return cpregid;
+}
+
+/*
+ * Convert a truncated 32 bit hashtable key into the full
+ * 64 bit KVM register ID.
+ */
+static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
+{
+    uint64_t kvmid;
+
+    if (cpregid & CP_REG_AA64_MASK) {
+        kvmid = cpregid & ~CP_REG_AA64_MASK;
+        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
+    } else {
+        kvmid = cpregid & ~(1 << 15);
+        if (cpregid & (1 << 15)) {
+            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
+        } else {
+            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
+        }
+    }
+    return kvmid;
+}
+
 /*
  * Valid values for ARMCPRegInfo state field, indicating which of
  * the AArch32 and AArch64 execution states this register is visible in.
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void);
 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
                                  uint32_t cur_el, bool secure);
 
-/* Interface for defining coprocessor registers.
- * Registers are defined in tables of arm_cp_reginfo structs
- * which are passed to define_arm_cp_regs().
- */
-
-/* When looking up a coprocessor register we look for it
- * via an integer which encodes all of:
- *  coprocessor number
- *  Crn, Crm, opc1, opc2 fields
- *  32 or 64 bit register (ie is it accessed via MRC/MCR
- *    or via MRRC/MCRR?)
- *  non-secure/secure bank (AArch32 only)
- * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
- * (In this case crn and opc2 should be zero.)
- * For AArch64, there is no 32/64 bit size distinction;
- * instead all registers have a 2 bit op0, 3 bit op1 and op2,
- * and 4 bit CRn and CRm. The encoding patterns are chosen
- * to be easy to convert to and from the KVM encodings, and also
- * so that the hashtable can contain both AArch32 and AArch64
- * registers (to allow for interprocessing where we might run
- * 32 bit code on a 64 bit core).
- */
-/* This bit is private to our hashtable cpreg; in KVM register
- * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
- * in the upper bits of the 64 bit ID.
- */
-#define CP_REG_AA64_SHIFT 28
-#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
-
-/* To enable banking of coprocessor registers depending on ns-bit we
- * add a bit to distinguish between secure and non-secure cpregs in the
- * hashtable.
- */
-#define CP_REG_NS_SHIFT 29
-#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
-
-#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2)   \
-    ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) |   \
-     ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
-
-#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
-    (CP_REG_AA64_MASK |                                 \
-     ((cp) << CP_REG_ARM_COPROC_SHIFT) |                \
-     ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) |         \
-     ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) |         \
-     ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) |         \
-     ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) |         \
-     ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
-
-/* Convert a full 64 bit KVM register ID to the truncated 32 bit
- * version used as a key for the coprocessor register hashtable
- */
-static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
-{
-    uint32_t cpregid = kvmid;
-    if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
-        cpregid |= CP_REG_AA64_MASK;
-    } else {
-        if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
-            cpregid |= (1 << 15);
-        }
-
-        /* KVM is always non-secure so add the NS flag on AArch32 register
-         * entries.
-         */
-         cpregid |= 1 << CP_REG_NS_SHIFT;
-    }
-    return cpregid;
-}
-
-/* Convert a truncated 32 bit hashtable key into the full
- * 64 bit KVM register ID.
- */
-static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
-{
-    uint64_t kvmid;
-
-    if (cpregid & CP_REG_AA64_MASK) {
-        kvmid = cpregid & ~CP_REG_AA64_MASK;
-        kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
-    } else {
-        kvmid = cpregid & ~(1 << 15);
-        if (cpregid & (1 << 15)) {
-            kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
-        } else {
-            kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
-        }
-    }
-    return kvmid;
-}
-
 /* Return the highest implemented Exception Level */
 static inline int arm_highest_el(CPUARMState *env)
 {
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.

We can now write tests without explicit calls to require_accelerator,
just the tag is enough.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/avocado_qemu/__init__.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/avocado_qemu/__init__.py
+++ b/tests/avocado/avocado_qemu/__init__.py
@@ -XXX,XX +XXX,XX @@ def setUp(self):
 
         super().setUp('qemu-system-')
 
+        accel_required = self._get_unique_tag_val('accel')
+        if accel_required:
+            self.require_accelerator(accel_required)
+
         self.machine = self.params.get('machine',
                                        default=self._get_unique_tag_val('machine'))
 
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

This allows the test to be skipped when TCG is not present in the QEMU
binary.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/avocado/boot_linux_console.py | 1 +
 tests/avocado/reverse_debugging.py  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/boot_linux_console.py
+++ b/tests/avocado/boot_linux_console.py
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self):
 
     def test_aarch64_raspi3_atf(self):
         """
+        :avocado: tags=accel:tcg
         :avocado: tags=arch:aarch64
         :avocado: tags=machine:raspi3b
         :avocado: tags=cpu:cortex-a53
diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py
index XXXXXXX..XXXXXXX 100644
--- a/tests/avocado/reverse_debugging.py
+++ b/tests/avocado/reverse_debugging.py
@@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None):
         vm.shutdown()
 
 class ReverseDebugging_X86_64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 0x10
     REG_CS = 0x12
     def get_pc(self, g):
@@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self):
         self.reverse_debugging()
 
 class ReverseDebugging_AArch64(ReverseDebugging):
+    """
+    :avocado: tags=accel:tcg
+    """
+
     REG_PC = 32
 
     # unidentified gitlab timeout problem
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.

Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->minimum_page_bits = 12;
     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+#ifdef CONFIG_TCG
     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+#else
+    mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
+#endif
     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
     mc->kvm_type = virt_kvm_type;
     assert(!mc->get_hotplug_handler);
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
 #define SVE_MAX_VQ 16
 
 #define MACHINE     "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
                     "  'arguments': { 'type': 'full', "
 #define QUERY_TAIL  "}}"
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
 {
     g_test_init(&argc, &argv, NULL);
 
-    qtest_add_data_func("/arm/query-cpu-model-expansion",
-                        NULL, test_query_cpu_model_expansion);
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/query-cpu-model-expansion",
+                            NULL, test_query_cpu_model_expansion);
+    }
+
+    if (!g_str_equal(qtest_get_arch(), "aarch64")) {
+        goto out;
+    }
 
     /*
      * For now we only run KVM specific tests with AArch64 QEMU in
      * order avoid attempting to run an AArch32 QEMU with KVM on
      * AArch64 hosts. That won't work and isn't easy to detect.
      */
-    if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
+    if (qtest_has_accel("kvm")) {
         /*
          * This tests target the 'host' CPU type, so register it only if
          * KVM is available.
          */
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                             NULL, test_query_cpu_model_expansion_kvm);
-    }
 
-    if (g_str_equal(qtest_get_arch(), "aarch64")) {
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
-                            NULL, sve_tests_sve_max_vq_8);
-        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
-                            NULL, sve_tests_sve_off);
         qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
                             NULL, sve_tests_sve_off_kvm);
     }
 
+    if (qtest_has_accel("tcg")) {
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+                            NULL, sve_tests_sve_max_vq_8);
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off);
+    }
+
+out:
     return g_test_run();
 }
-- 
2.34.1

From: Fabiano Rosas <farosas@suse.de>

These tests set -accel tcg, so restrict them to when TCG is present.

Signed-off-by: Fabiano Rosas <farosas@suse.de>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/meson.build | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
 qtests_aarch64 = \
   (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) +                            \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
-  (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
+  (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ?            \
+    ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) +                                         \
   (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
   (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) +  \
   ['arm-cpu-features',
-- 
2.34.1