[Qemu-devel] [PULL 00/11] target-arm queue
[PULL v2 00/29] target-arm queue
1
Hi; this target-arm pull request has a collection of generally
1
v2: drop pvpanic-pci patches.
2
fairly minor bugs to sneak in before 3.0 rc0 tomorrow...
3
2
4
thanks
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
5
-- PMM
6
4
7
The following changes since commit a98ff0ec2ba3538dd766b349518ee18d03942ed8:
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
8
9
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180709' into staging (2018-07-09 11:00:45 +0100)
10
6
11
are available in the Git repository at:
7
are available in the Git repository at:
12
8
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180709
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
14
10
15
for you to fetch changes up to 8fad0a65582c0a6e324580f45516461e9b6aa439:
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
16
12
17
hw/net/dp8393x: don't make prom region 'nomigrate' (2018-07-09 14:51:35 +0100)
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
18
14
19
----------------------------------------------------------------
15
----------------------------------------------------------------
20
target-arm queue:
16
target-arm queue:
21
* hw/net/dp8393x: don't make prom region 'nomigrate'
17
* Implement IMPDEF pauth algorithm
22
* boards.h: Remove doc comment reference to nonexistent function
18
* Support ARMv8.4-SEL2
23
* hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
24
* target/arm: Fix do_predset for large VL
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
25
* tcg: Restrict check_size_impl to multiples of the line size
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
26
* target/arm: Suppress Coverity warning for PRF
22
* docs: Build and install all the docs in a single manual
27
* hw/timer/cmsdk-apb-timer: fix minor corner-case bugs and
28
suppress spurious warnings when running Linux's timer driver
29
* hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
30
23
31
----------------------------------------------------------------
24
----------------------------------------------------------------
32
Eric Auger (1):
25
Gan Qixin (1):
33
hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
34
27
35
Guenter Roeck (1):
28
Peter Maydell (1):
36
hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
29
docs: Build and install all the docs in a single manual
37
38
Peter Maydell (5):
39
ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
40
hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
41
hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
42
boards.h: Remove doc comment reference to nonexistent function
43
hw/net/dp8393x: don't make prom region 'nomigrate'
44
30
45
Philippe Mathieu-Daudé (1):
31
Philippe Mathieu-Daudé (1):
46
hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
47
33
48
Richard Henderson (3):
34
Richard Henderson (7):
49
target/arm: Suppress Coverity warning for PRF
35
target/arm: Implement an IMPDEF pauth algorithm
50
tcg: Restrict check_size_impl to multiples of the line size
36
target/arm: Add cpu properties to control pauth
51
target/arm: Fix do_predset for large VL
37
target/arm: Use object_property_add_bool for "sve" property
38
target/arm: Introduce PREDDESC field definitions
39
target/arm: Update PFIRST, PNEXT for pred_desc
40
target/arm: Update ZIP, UZP, TRN for pred_desc
41
target/arm: Update REV, PUNPK for pred_desc
52
42
53
include/hw/arm/smmu-common.h | 1 +
43
Rémi Denis-Courmont (19):
54
include/hw/boards.h | 3 +--
44
target/arm: remove redundant tests
55
include/hw/ptimer.h | 9 +++++++++
45
target/arm: add arm_is_el2_enabled() helper
56
hw/arm/smmu-common.c | 2 +-
46
target/arm: use arm_is_el2_enabled() where applicable
57
hw/core/ptimer.c | 22 +++++++++++++++++++++-
47
target/arm: use arm_hcr_el2_eff() where applicable
58
hw/net/dp8393x.c | 2 +-
48
target/arm: factor MDCR_EL2 common handling
59
hw/sd/omap_mmc.c | 14 +++++++++++---
49
target/arm: Define isar_feature function to test for presence of SEL2
60
hw/timer/cmsdk-apb-timer.c | 20 ++++++++++++++++++--
50
target/arm: add 64-bit S-EL2 to EL exception table
61
target/arm/translate-sve.c | 14 ++++----------
51
target/arm: add MMU stage 1 for Secure EL2
62
tcg/tcg-op-gvec.c | 7 +++++--
52
target/arm: add ARMv8.4-SEL2 system registers
63
tests/ptimer-test.c | 25 +++++++++++++++++++------
53
target/arm: handle VMID change in secure state
64
11 files changed, 91 insertions(+), 28 deletions(-)
54
target/arm: do S1_ptw_translate() before address space lookup
55
target/arm: translate NS bit in page-walks
56
target/arm: generalize 2-stage page-walk condition
57
target/arm: secure stage 2 translation regime
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
59
target/arm: revector to run-time pick target EL
60
target/arm: Implement SCR_EL2.EEL2
61
target/arm: enable Secure EL2 in max CPU
62
target/arm: refactor vae1_tlbmask()
65
63
64
docs/conf.py | 46 ++++-
65
docs/devel/conf.py | 15 --
66
docs/index.html.in | 17 --
67
docs/interop/conf.py | 28 ---
68
docs/meson.build | 64 +++---
69
docs/specs/conf.py | 16 --
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/11] hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding
4
to a given sid. The function extracts both the PCIe bus number and
5
the devfn to return this data. Current computation of devfn is wrong
6
as it only returns the PCIe function instead of slot | function.
7
8
Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data")
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/arm/smmu-common.h | 1 +
16
hw/arm/smmu-common.c | 2 +-
17
2 files changed, 2 insertions(+), 1 deletion(-)
18
19
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/smmu-common.h
22
+++ b/include/hw/arm/smmu-common.h
23
@@ -XXX,XX +XXX,XX @@
24
25
#define SMMU_PCI_BUS_MAX 256
26
#define SMMU_PCI_DEVFN_MAX 256
27
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
28
29
#define SMMU_MAX_VA_BITS 48
30
31
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/smmu-common.c
34
+++ b/hw/arm/smmu-common.c
35
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
36
bus_n = PCI_BUS_NUM(sid);
37
smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
38
if (smmu_bus) {
39
- devfn = sid & 0x7;
40
+ devfn = SMMU_PCI_DEVFN(sid);
41
smmu = smmu_bus->pbdev[devfn];
42
if (smmu) {
43
return &smmu->iommu;
44
--
45
2.17.1
46
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/11] ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
Deleted patch
1
The CMSDK timer behaviour is that an interrupt is triggered when the
2
counter counts down from 1 to 0; however one is not triggered if the
3
counter is manually set to 0 by a guest write to the counter register.
4
Currently ptimer can't handle this; add a policy option to allow
5
a ptimer user to request this behaviour.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20180703171044.9503-2-peter.maydell@linaro.org
11
---
12
include/hw/ptimer.h | 9 +++++++++
13
hw/core/ptimer.c | 22 +++++++++++++++++++++-
14
tests/ptimer-test.c | 25 +++++++++++++++++++------
15
3 files changed, 49 insertions(+), 7 deletions(-)
16
17
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ptimer.h
20
+++ b/include/hw/ptimer.h
21
@@ -XXX,XX +XXX,XX @@
22
* not the one less. */
23
#define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
24
25
+/*
26
+ * Starting to run with a zero counter, or setting the counter to "0" via
27
+ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer
28
+ * (though it will cause a reload). Only a counter decrement to "0"
29
+ * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
30
+ * ptimer_init() will assert() that you don't set both.
31
+ */
32
+#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
33
+
34
/* ptimer.c */
35
typedef struct ptimer_state ptimer_state;
36
typedef void (*ptimer_cb)(void *opaque);
37
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/core/ptimer.c
40
+++ b/hw/core/ptimer.c
41
@@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
42
uint32_t period_frac = s->period_frac;
43
uint64_t period = s->period;
44
uint64_t delta = s->delta;
45
+ bool suppress_trigger = false;
46
47
- if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
48
+ /*
49
+ * Note that if delta_adjust is 0 then we must be here because of
50
+ * a count register write or timer start, not because of timer expiry.
51
+ * In that case the policy might require us to suppress the timer trigger
52
+ * that we would otherwise generate for a zero delta.
53
+ */
54
+ if (delta_adjust == 0 &&
55
+ (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
56
+ suppress_trigger = true;
57
+ }
58
+ if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
59
+ && !suppress_trigger) {
60
ptimer_trigger(s);
61
}
62
63
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
64
s->bh = bh;
65
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
66
s->policy_mask = policy_mask;
67
+
68
+ /*
69
+ * These two policies are incompatible -- trigger-on-decrement implies
70
+ * a timer trigger when the count becomes 0, but no-immediate-trigger
71
+ * implies a trigger when the count stops being 0.
72
+ */
73
+ assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
74
+ (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
75
return s;
76
}
77
78
diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/tests/ptimer-test.c
81
+++ b/tests/ptimer-test.c
82
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
83
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
84
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
85
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
86
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
87
88
triggered = false;
89
90
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
91
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
92
no_immediate_reload ? 0 : 10);
93
94
- if (no_immediate_trigger) {
95
+ if (no_immediate_trigger || trig_only_on_dec) {
96
g_assert_false(triggered);
97
} else {
98
g_assert_true(triggered);
99
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
100
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
101
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
102
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
103
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
104
105
triggered = false;
106
107
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
108
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
109
no_immediate_reload ? 0 : 99);
110
111
- if (no_immediate_trigger) {
112
+ if (no_immediate_trigger || trig_only_on_dec) {
113
g_assert_false(triggered);
114
} else {
115
g_assert_true(triggered);
116
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
117
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
118
no_immediate_reload ? 0 : 99);
119
120
- if (no_immediate_trigger) {
121
+ if (no_immediate_trigger || trig_only_on_dec) {
122
g_assert_false(triggered);
123
} else {
124
g_assert_true(triggered);
125
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
126
ptimer_state *ptimer = ptimer_init(bh, *policy);
127
bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER);
128
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
129
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
130
131
triggered = false;
132
133
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
134
135
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
136
137
- if (no_immediate_trigger) {
138
+ if (no_immediate_trigger || trig_only_on_dec) {
139
g_assert_false(triggered);
140
} else {
141
g_assert_true(triggered);
142
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
143
QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL);
144
ptimer_state *ptimer = ptimer_init(bh, *policy);
145
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
146
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
147
148
triggered = false;
149
150
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
151
152
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
153
154
- if (no_immediate_trigger) {
155
+ if (no_immediate_trigger || trig_only_on_dec) {
156
g_assert_false(triggered);
157
} else {
158
g_assert_true(triggered);
159
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
160
g_strlcat(policy_name, "no_counter_rounddown,", 256);
161
}
162
163
+ if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) {
164
+ g_strlcat(policy_name, "trigger_only_on_decrement,", 256);
165
+ }
166
+
167
g_test_add_data_func_full(
168
tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name),
169
g_memdup(&policy, 1), check_set_count, g_free);
170
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
171
172
static void add_all_ptimer_policies_comb_tests(void)
173
{
174
- int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN;
175
+ int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
176
int policy = PTIMER_POLICY_DEFAULT;
177
178
for (; policy < (last_policy << 1); policy++) {
179
+ if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
180
+ (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
181
+ /* Incompatible policy flag settings -- don't try to test them */
182
+ continue;
183
+ }
184
add_ptimer_tests(policy);
185
}
186
}
187
--
188
2.17.1
189
190
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/11] hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
Deleted patch
1
The CMSDK timer interrupt triggers when the counter goes from 1 to 0,
2
so we want to trigger immediately, rather than waiting for a
3
clock cycle. Drop the incorrect NO_IMMEDIATE_TRIGGER setting.
4
We also do not want to get an interrupt if the guest sets the
5
counter directly to zero, so use the new TRIGGER_ONLY_ON_DECREMENT
6
policy.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Guenter Roeck <linux@roeck-us.net>
11
Message-id: 20180703171044.9503-3-peter.maydell@linaro.org
12
---
13
hw/timer/cmsdk-apb-timer.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/cmsdk-apb-timer.c
19
+++ b/hw/timer/cmsdk-apb-timer.c
20
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
21
bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
22
s->timer = ptimer_init(bh,
23
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
24
- PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
25
+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
26
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
27
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
28
29
--
30
2.17.1
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/11] hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
The CMSDK APB timer is currently always configured as periodic timer.
4
This results in the following messages when trying to boot Linux.
5
6
Timer with delta zero, disabling
7
8
If the timer limit set with the RELOAD command is 0, the timer
9
needs to be enabled as one-shot timer.
10
11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/timer/cmsdk-apb-timer.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/cmsdk-apb-timer.c
23
+++ b/hw/timer/cmsdk-apb-timer.c
24
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
25
}
26
s->ctrl = value & 0xf;
27
if (s->ctrl & R_CTRL_EN_MASK) {
28
- ptimer_run(s->timer, 0);
29
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
30
} else {
31
ptimer_stop(s->timer);
32
}
33
--
34
2.17.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/11] hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
Deleted patch
1
If the CMSDK APB timer is set up with a zero RELOAD value
2
then it will count down to zero, fire once and then stay
3
at zero. From the point of view of the ptimer system, the
4
timer is disabled; but the enable bit in the CTRL register
5
is still set and if the guest subsequently writes to the
6
RELOAD or VALUE registers this should cause the timer to
7
start counting down again.
8
1
9
Add code to the write paths for RELOAD and VALUE so that
10
we correctly restart the timer in this situation.
11
12
Conversely, if the new RELOAD and VALUE are both zero,
13
we should stop the ptimer.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
18
Message-id: 20180703171044.9503-5-peter.maydell@linaro.org
19
---
20
hw/timer/cmsdk-apb-timer.c | 16 ++++++++++++++++
21
1 file changed, 16 insertions(+)
22
23
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/cmsdk-apb-timer.c
26
+++ b/hw/timer/cmsdk-apb-timer.c
27
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
28
break;
29
case A_RELOAD:
30
/* Writing to reload also sets the current timer value */
31
+ if (!value) {
32
+ ptimer_stop(s->timer);
33
+ }
34
ptimer_set_limit(s->timer, value, 1);
35
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
36
+ /*
37
+ * Make sure timer is running (it might have stopped if this
38
+ * was an expired one-shot timer)
39
+ */
40
+ ptimer_run(s->timer, 0);
41
+ }
42
break;
43
case A_VALUE:
44
+ if (!value && !ptimer_get_limit(s->timer)) {
45
+ ptimer_stop(s->timer);
46
+ }
47
ptimer_set_count(s->timer, value);
48
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
49
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
50
+ }
51
break;
52
case A_INTSTATUS:
53
/* Just one bit, which is W1C. */
54
--
55
2.17.1
56
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/11] target/arm: Suppress Coverity warning for PRF
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
These instructions must perform the sve_access_check, but
4
since they are implemented as NOPs there is no generated
5
code to elide when the access check fails.
6
7
Fixes: Coverity issues 1393780 & 1393779.
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
20
static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
21
{
22
/* Prefetch is a nop within QEMU. */
23
- sve_access_check(s);
24
+ (void)sve_access_check(s);
25
return true;
26
}
27
28
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
29
return false;
30
}
31
/* Prefetch is a nop within QEMU. */
32
- sve_access_check(s);
33
+ (void)sve_access_check(s);
34
return true;
35
}
36
37
--
38
2.17.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/11] tcg: Restrict check_size_impl to multiples of the line size
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Normally this is automatic in the size restrictions that are placed
4
on vector sizes coming from the implementation. However, for the
5
legitimate size tuple [oprsz=8, maxsz=32], we need to clear the final
6
24 bytes of the vector register. Without this check, do_dup selects
7
TCG_TYPE_V128 and clears only 16 bytes.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20180705191929.30773-2-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
tcg/tcg-op-gvec.c | 7 +++++--
16
1 file changed, 5 insertions(+), 2 deletions(-)
17
18
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tcg/tcg-op-gvec.c
21
+++ b/tcg/tcg-op-gvec.c
22
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
23
in units of LNSZ. This limits the expansion of inline code. */
24
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
25
{
26
- uint32_t lnct = oprsz / lnsz;
27
- return lnct >= 1 && lnct <= MAX_UNROLL;
28
+ if (oprsz % lnsz == 0) {
29
+ uint32_t lnct = oprsz / lnsz;
30
+ return lnct >= 1 && lnct <= MAX_UNROLL;
31
+ }
32
+ return false;
33
}
34
35
static void expand_clr(uint32_t dofs, uint32_t maxsz);
36
--
37
2.17.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/11] target/arm: Fix do_predset for large VL
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Use MAKE_64BIT_MASK instead of open-coding. Remove an odd
4
vector size check that is unlikely to be more profitable
5
than 3 64-bit integer stores. Correct the iteration for WORD
6
to avoid writing too much data.
7
8
Fixes RISU tests of PTRUE for VL 256.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20180705191929.30773-3-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/translate-sve.c | 10 ++--------
17
1 file changed, 2 insertions(+), 8 deletions(-)
18
19
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
24
setsz = numelem << esz;
25
lastword = word = pred_esz_masks[esz];
26
if (setsz % 64) {
27
- lastword &= ~(-1ull << (setsz % 64));
28
+ lastword &= MAKE_64BIT_MASK(0, setsz % 64);
29
}
30
}
31
32
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
33
tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
34
goto done;
35
}
36
- if (oprsz * 8 == setsz + 8) {
37
- tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
38
- tcg_gen_movi_i64(t, 0);
39
- tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
40
- goto done;
41
- }
42
}
43
44
setsz /= 8;
45
fullsz /= 8;
46
47
tcg_gen_movi_i64(t, word);
48
- for (i = 0; i < setsz; i += 8) {
49
+ for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
50
tcg_gen_st_i64(t, cpu_env, ofs + i);
51
}
52
if (lastword != word) {
53
--
54
2.17.1
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/11] hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
DeviceClass::reset models a "cold power-on" reset which can
4
also be used to powercycle a device; but there is no "hot reset"
5
(a.k.a. soft-reset) method available.
6
7
The OMAP MMC Power-Up Control bit is not designed to powercycle
8
a card, but to disable it without powering it off (pseudo-reset):
9
10
Multimedia Card (MMC/SD/SDIO) Interface [SPRU765A]
11
12
MMC_CON[11] Power-Up Control (POW)
13
This bit must be set to 1 before any valid transaction to either
14
MMC/SD or SPI memory cards.
15
When 1, the card is considered powered-up and the controller core
16
is enabled.
17
When 0, the card is considered powered-down (system dependent),
18
and the controller core logic is in pseudo-reset state. This is,
19
the MMC_STAT flags and the FIFO pointers are reset, any access to
20
MMC_DATA[DATA] has no effect, a write into the MMC.CMD register
21
is ignored, and a setting of MMC_SPI[STR] to 1 is ignored.
22
23
By splitting the 'pseudo-reset' code out of the 'power-on' reset
24
function, this patch fixes a latent bug in omap_mmc_write(MMC_CON)i
25
recently exposed by ecd219f7abb.
26
27
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Message-id: 20180706162155.8432-2-f4bug@amsat.org
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
hw/sd/omap_mmc.c | 14 +++++++++++---
33
1 file changed, 11 insertions(+), 3 deletions(-)
34
35
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/omap_mmc.c
38
+++ b/hw/sd/omap_mmc.c
39
@@ -XXX,XX +XXX,XX @@
40
/*
41
* OMAP on-chip MMC/SD host emulation.
42
*
43
+ * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
44
+ *
45
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
46
*
47
* This program is free software; you can redistribute it and/or
48
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_update(void *opaque)
49
omap_mmc_interrupts_update(s);
50
}
51
52
+static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
53
+{
54
+ host->status = 0;
55
+ host->fifo_len = 0;
56
+}
57
+
58
void omap_mmc_reset(struct omap_mmc_s *host)
59
{
60
host->last_cmd = 0;
61
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
62
host->dw = 0;
63
host->mode = 0;
64
host->enable = 0;
65
- host->status = 0;
66
host->mask = 0;
67
host->cto = 0;
68
host->dto = 0;
69
- host->fifo_len = 0;
70
host->blen = 0;
71
host->blen_counter = 0;
72
host->nblk = 0;
73
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
74
qemu_set_irq(host->coverswitch, host->cdet_state);
75
host->clkdiv = 0;
76
77
+ omap_mmc_pseudo_reset(host);
78
+
79
/* Since we're still using the legacy SD API the card is not plugged
80
* into any bus, and we must reset it manually. When omap_mmc is
81
* QOMified this must move into the QOM reset function.
82
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
83
if (s->dw != 0 && s->lines < 4)
84
printf("4-bit SD bus enabled\n");
85
if (!s->enable)
86
- omap_mmc_reset(s);
87
+ omap_mmc_pseudo_reset(s);
88
break;
89
90
case 0x10:    /* MMC_STAT */
91
--
92
2.17.1
93
94
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/11] boards.h: Remove doc comment reference to nonexistent function
Deleted patch
1
commit b08199c6fbea1 accidentally added a reference to a doc
2
comment to a nonexistent memory_region_allocate_aux_memory().
3
This was a leftover from a previous version of the patchset
4
which defined memory_region_allocate_aux_memory() for
5
"allocate RAM MemoryRegion and register it for migration"
6
and left "memory_region_init_ram()" with its original semantics
7
of "allocate RAM MR but do not register for migration". In
8
the end we decided on the approach of "memory_region_init_ram()
9
registers the MR for migration, and memory_region_init_ram_nomigrate()
10
is a new function which does not", but this comment change
11
got left in by mistake. Revert that part of the commit.
12
1
13
Reported-by: Thomas Huth <huth@tuxfamily.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20180702130605.13611-1-peter.maydell@linaro.org
16
---
17
include/hw/boards.h | 3 +--
18
1 file changed, 1 insertion(+), 2 deletions(-)
19
20
diff --git a/include/hw/boards.h b/include/hw/boards.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/boards.h
23
+++ b/include/hw/boards.h
24
@@ -XXX,XX +XXX,XX @@
25
*
26
* Smaller pieces of memory (display RAM, static RAMs, etc) don't need
27
* to be backed via the -mem-path memory backend and can simply
28
- * be created via memory_region_allocate_aux_memory() or
29
- * memory_region_init_ram().
30
+ * be created via memory_region_init_ram().
31
*/
32
void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
33
const char *name,
34
--
35
2.17.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/11] hw/net/dp8393x: don't make prom region 'nomigrate'
Deleted patch
1
Currently we use memory_region_init_rom_nomigrate() to create
2
the "dp3893x-prom" memory region, and we don't manually register
3
it with vmstate_register_ram(). This currently means that its
4
contents are migrated but as a ram block whose name is the empty
5
string; in future it may mean they are not migrated at all. Use
6
memory_region_init_ram() instead.
7
1
8
Note that this is a a cross-version migration compatibility break
9
for the MIPS "magnum" and "pica61" machines.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Aleksandar Markovic <aleksandar.markovic@wavecomp.com>
13
Message-id: 20180706174309.27110-1-peter.maydell@linaro.org
14
---
15
hw/net/dp8393x.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/net/dp8393x.c
21
+++ b/hw/net/dp8393x.c
22
@@ -XXX,XX +XXX,XX @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
23
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
24
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
25
26
- memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev),
27
+ memory_region_init_ram(&s->prom, OBJECT(dev),
28
"dp8393x-prom", SONIC_PROM_SIZE, &local_err);
29
if (local_err) {
30
error_propagate(errp, local_err);
31
--
32
2.17.1
33
34
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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