Series comparison

-[Qemu-devel] [PULL 00/11] target-arm queue
+[PULL 00/11] target-arm queue
-Hi; this target-arm pull request has a collection of generally
+target-arm queue: two bug fixes, plus the KVM/SVE patchset,
-fairly minor bugs to sneak in before 3.0 rc0 tomorrow...
+which is a new feature but one which was in my pre-softfreeze
 pullreq (it just had to be dropped due to an unexpected test failure.)
 thanks
 -- PMM
-The following changes since commit a98ff0ec2ba3538dd766b349518ee18d03942ed8:
+The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b:
-  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180709' into staging (2018-07-09 11:00:45 +0100)
+  Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +0000)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180709
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191101-1
-for you to fetch changes up to 8fad0a65582c0a6e324580f45516461e9b6aa439:
+for you to fetch changes up to d9ae7624b659362cb2bb2b04fee53bf50829ca56:
-  hw/net/dp8393x: don't make prom region 'nomigrate' (2018-07-09 14:51:35 +0100)
+  target/arm: Allow reading flags from FPSCR for M-profile (2019-11-01 08:49:10 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * hw/net/dp8393x: don't make prom region 'nomigrate'
+ * Support SVE in KVM guests
- * boards.h: Remove doc comment reference to nonexistent function
+ * Don't UNDEF on M-profile 'vmrs apsr_nzcv, fpscr'
- * hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
+ * Update hflags after boot.c modifies CPU state
  * target/arm: Fix do_predset for large VL
  * tcg: Restrict check_size_impl to multiples of the line size
  * target/arm: Suppress Coverity warning for PRF
  * hw/timer/cmsdk-apb-timer: fix minor corner-case bugs and
    suppress spurious warnings when running Linux's timer driver
  * hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
 ----------------------------------------------------------------
-Eric Auger (1):
+Andrew Jones (9):
-      hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
+      target/arm/monitor: Introduce qmp_query_cpu_model_expansion
       tests: arm: Introduce cpu feature tests
       target/arm: Allow SVE to be disabled via a CPU property
       target/arm/cpu64: max cpu: Introduce sve<N> properties
       target/arm/kvm64: Add kvm_arch_get/put_sve
       target/arm/kvm64: max cpu: Enable SVE when available
       target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
       target/arm/cpu64: max cpu: Support sve properties with KVM
       target/arm/kvm: host cpu: Add support for sve<N> properties
-Guenter Roeck (1):
+Christophe Lyon (1):
-      hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
+      target/arm: Allow reading flags from FPSCR for M-profile
-Peter Maydell (5):
+Edgar E. Iglesias (1):
-      ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
+      hw/arm/boot: Rebuild hflags when modifying CPUState at boot
       hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
       hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
       boards.h: Remove doc comment reference to nonexistent function
       hw/net/dp8393x: don't make prom region 'nomigrate'
-Philippe Mathieu-Daudé (1):
+ tests/Makefile.include         |   5 +-
-      hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
+ qapi/machine-target.json       |   6 +-
  include/qemu/bitops.h          |   1 +
  target/arm/cpu.h               |  21 ++
  target/arm/kvm_arm.h           |  39 +++
  hw/arm/boot.c                  |   1 +
  target/arm/cpu.c               |  25 +-
  target/arm/cpu64.c             | 364 +++++++++++++++++++++++++--
  target/arm/helper.c            |  10 +-
  target/arm/kvm.c               |  25 +-
  target/arm/kvm32.c             |   6 +-
  target/arm/kvm64.c             | 325 +++++++++++++++++++++---
  target/arm/monitor.c           | 158 ++++++++++++
  target/arm/translate-vfp.inc.c |   5 +-
  tests/arm-cpu-features.c       | 551 +++++++++++++++++++++++++++++++++++++++++
  docs/arm-cpu-features.rst      | 317 ++++++++++++++++++++++++
 files changed, 1795 insertions(+), 64 deletions(-)
  create mode 100644 tests/arm-cpu-features.c
  create mode 100644 docs/arm-cpu-features.rst
-Richard Henderson (3):
-      target/arm: Suppress Coverity warning for PRF
-      tcg: Restrict check_size_impl to multiples of the line size
-      target/arm: Fix do_predset for large VL
- include/hw/arm/smmu-common.h |  1 +
- include/hw/boards.h          |  3 +--
- include/hw/ptimer.h          |  9 +++++++++
- hw/arm/smmu-common.c         |  2 +-
- hw/core/ptimer.c             | 22 +++++++++++++++++++++-
- hw/net/dp8393x.c             |  2 +-
- hw/sd/omap_mmc.c             | 14 +++++++++++---
- hw/timer/cmsdk-apb-timer.c   | 20 ++++++++++++++++++--
- target/arm/translate-sve.c   | 14 ++++----------
- tcg/tcg-op-gvec.c            |  7 +++++--
- tests/ptimer-test.c          | 25 +++++++++++++++++++------
-files changed, 91 insertions(+), 28 deletions(-)

-[Qemu-devel] [PULL 11/11] hw/net/dp8393x: don't make prom region 'nomigrate'
+[PULL 01/11] target/arm/monitor: Introduce qmp_query_cpu_model_expansion
-Currently we use memory_region_init_rom_nomigrate() to create
+From: Andrew Jones <drjones@redhat.com>
-the "dp3893x-prom" memory region, and we don't manually register
-it with vmstate_register_ram(). This currently means that its
+Add support for the query-cpu-model-expansion QMP command to Arm. We
-contents are migrated but as a ram block whose name is the empty
+do this selectively, only exposing CPU properties which represent
-string; in future it may mean they are not migrated at all. Use
+optional CPU features which the user may want to enable/disable.
-memory_region_init_ram() instead.
+Additionally we restrict the list of queryable cpu models to 'max',
+'host', or the current type when KVM is in use. And, finally, we only
-Note that this is a a cross-version migration compatibility break
+implement expansion type 'full', as Arm does not yet have a "base"
-for the MIPS "magnum" and "pica61" machines.
+CPU type. More details and example queries are described in a new
+document (docs/arm-cpu-features.rst).
 Note, certainly more features may be added to the list of advertised
 features, e.g. 'vfp' and 'neon'. The only requirement is that we can
 detect invalid configurations and emit failures at QMP query time.
 For 'vfp' and 'neon' this will require some refactoring to share a
 validation function between the QMP query and the CPU realize
 functions.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
 Message-id: 20191031142734.8590-2-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Aleksandar Markovic <aleksandar.markovic@wavecomp.com>
-Message-id: 20180706174309.27110-1-peter.maydell@linaro.org
 ---
- hw/net/dp8393x.c | 2 +-
+ qapi/machine-target.json  |   6 +-
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/monitor.c      | 146 ++++++++++++++++++++++++++++++++++++++
+ docs/arm-cpu-features.rst | 137 +++++++++++++++++++++++++++++++++++
-diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
+files changed, 286 insertions(+), 3 deletions(-)
  create mode 100644 docs/arm-cpu-features.rst
 diff --git a/qapi/machine-target.json b/qapi/machine-target.json
 index XXXXXXX..XXXXXXX 100644
---- a/hw/net/dp8393x.c
+--- a/qapi/machine-target.json
-+++ b/hw/net/dp8393x.c
++++ b/qapi/machine-target.json
-@@ -XXX,XX +XXX,XX @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@
-     s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
+ ##
-     s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
+ { 'struct': 'CpuModelExpansionInfo',
+   'data': { 'model': 'CpuModelInfo' },
--    memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev),
+-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
-+    memory_region_init_ram(&s->prom, OBJECT(dev),
++  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
-                            "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
-     if (local_err) {
+ ##
-         error_propagate(errp, local_err);
+ # @query-cpu-model-expansion:
@@ -XXX,XX +XXX,XX @@
  #   query-cpu-model-expansion while using these is not advised.
  #
  # Some architectures may not support all expansion types. s390x supports
 -# "full" and "static".
 +# "full" and "static". Arm only supports "full".
  #
  # Returns: a CpuModelExpansionInfo. Returns an error if expanding CPU models is
  #          not supported, if the model cannot be expanded, if the model contains
@@ -XXX,XX +XXX,XX @@
    'data': { 'type': 'CpuModelExpansionType',
              'model': 'CpuModelInfo' },
    'returns': 'CpuModelExpansionInfo',
 -  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
 +  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
  ##
  # @CpuDefinitionInfo:
 diff --git a/target/arm/monitor.c b/target/arm/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/monitor.c
 +++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
 +#include "hw/boards.h"
  #include "kvm_arm.h"
 +#include "qapi/error.h"
 +#include "qapi/visitor.h"
 +#include "qapi/qobject-input-visitor.h"
 +#include "qapi/qapi-commands-machine-target.h"
  #include "qapi/qapi-commands-misc-target.h"
 +#include "qapi/qmp/qerror.h"
 +#include "qapi/qmp/qdict.h"
 +#include "qom/qom-qobject.h"
  static GICCapability *gic_cap_new(int version)
  {
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
      return head;
  }
 +
 +/*
 + * These are cpu model features we want to advertise. The order here
 + * matters as this is the order in which qmp_query_cpu_model_expansion
 + * will attempt to set them. If there are dependencies between features,
 + * then the order that considers those dependencies must be used.
 + */
 +static const char *cpu_model_advertised_features[] = {
 +    "aarch64", "pmu",
 +    NULL
 +};
 +
 +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
 +                                                     CpuModelInfo *model,
 +                                                     Error **errp)
 +{
 +    CpuModelExpansionInfo *expansion_info;
 +    const QDict *qdict_in = NULL;
 +    QDict *qdict_out;
 +    ObjectClass *oc;
 +    Object *obj;
 +    const char *name;
 +    int i;
 +
 +    if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {
 +        error_setg(errp, "The requested expansion type is not supported");
 +        return NULL;
 +    }
 +
 +    if (!kvm_enabled() && !strcmp(model->name, "host")) {
 +        error_setg(errp, "The CPU type '%s' requires KVM", model->name);
 +        return NULL;
 +    }
 +
 +    oc = cpu_class_by_name(TYPE_ARM_CPU, model->name);
 +    if (!oc) {
 +        error_setg(errp, "The CPU type '%s' is not a recognized ARM CPU type",
 +                   model->name);
 +        return NULL;
 +    }
 +
 +    if (kvm_enabled()) {
 +        const char *cpu_type = current_machine->cpu_type;
 +        int len = strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
 +        bool supported = false;
 +
 +        if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {
 +            /* These are kvmarm's recommended cpu types */
 +            supported = true;
 +        } else if (strlen(model->name) == len &&
 +                   !strncmp(model->name, cpu_type, len)) {
 +            /* KVM is enabled and we're using this type, so it works. */
 +            supported = true;
 +        }
 +        if (!supported) {
 +            error_setg(errp, "We cannot guarantee the CPU type '%s' works "
 +                             "with KVM on this host", model->name);
 +            return NULL;
 +        }
 +    }
 +
 +    if (model->props) {
 +        qdict_in = qobject_to(QDict, model->props);
 +        if (!qdict_in) {
 +            error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
 +            return NULL;
 +        }
 +    }
 +
 +    obj = object_new(object_class_get_name(oc));
 +
 +    if (qdict_in) {
 +        Visitor *visitor;
 +        Error *err = NULL;
 +
 +        visitor = qobject_input_visitor_new(model->props);
 +        visit_start_struct(visitor, NULL, NULL, 0, &err);
 +        if (err) {
 +            visit_free(visitor);
 +            object_unref(obj);
 +            error_propagate(errp, err);
 +            return NULL;
 +        }
 +
 +        i = 0;
 +        while ((name = cpu_model_advertised_features[i++]) != NULL) {
 +            if (qdict_get(qdict_in, name)) {
 +                object_property_set(obj, visitor, name, &err);
 +                if (err) {
 +                    break;
 +                }
 +            }
 +        }
 +
 +        if (!err) {
 +            visit_check_struct(visitor, &err);
 +        }
 +        visit_end_struct(visitor, NULL);
 +        visit_free(visitor);
 +        if (err) {
 +            object_unref(obj);
 +            error_propagate(errp, err);
 +            return NULL;
 +        }
 +    }
 +
 +    expansion_info = g_new0(CpuModelExpansionInfo, 1);
 +    expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
 +    expansion_info->model->name = g_strdup(model->name);
 +
 +    qdict_out = qdict_new();
 +
 +    i = 0;
 +    while ((name = cpu_model_advertised_features[i++]) != NULL) {
 +        ObjectProperty *prop = object_property_find(obj, name, NULL);
 +        if (prop) {
 +            Error *err = NULL;
 +            QObject *value;
 +
 +            assert(prop->get);
 +            value = object_property_get_qobject(obj, name, &err);
 +            assert(!err);
 +
 +            qdict_put_obj(qdict_out, name, value);
 +        }
 +    }
 +
 +    if (!qdict_size(qdict_out)) {
 +        qobject_unref(qdict_out);
 +    } else {
 +        expansion_info->model->props = QOBJECT(qdict_out);
 +        expansion_info->model->has_props = true;
 +    }
 +
 +    object_unref(obj);
 +
 +    return expansion_info;
 +}
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@
 +================
 +ARM CPU Features
 +================
 +
 +Examples of probing and using ARM CPU features
 +
 +Introduction
 +============
 +
 +CPU features are optional features that a CPU of supporting type may
 +choose to implement or not.  In QEMU, optional CPU features have
 +corresponding boolean CPU proprieties that, when enabled, indicate
 +that the feature is implemented, and, conversely, when disabled,
 +indicate that it is not implemented. An example of an ARM CPU feature
 +is the Performance Monitoring Unit (PMU).  CPU types such as the
 +Cortex-A15 and the Cortex-A57, which respectively implement ARM
 +architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
 +implement PMUs.  For example, if a user wants to use a Cortex-A15 without
 +a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU
 +command line, i.e. `-cpu cortex-a15,pmu=off`.
 +
 +As not all CPU types support all optional CPU features, then whether or
 +not a CPU property exists depends on the CPU type.  For example, CPUs
 +that implement the ARMv8-A architecture reference manual may optionally
 +support the AArch32 CPU feature, which may be enabled by disabling the
 +`aarch64` CPU property.  A CPU type such as the Cortex-A15, which does
 +not implement ARMv8-A, will not have the `aarch64` CPU property.
 +
 +QEMU's support may be limited for some CPU features, only partially
 +supporting the feature or only supporting the feature under certain
 +configurations.  For example, the `aarch64` CPU feature, which, when
 +disabled, enables the optional AArch32 CPU feature, is only supported
 +when using the KVM accelerator and when running on a host CPU type that
 +supports the feature.
 +
 +CPU Feature Probing
 +===================
 +
 +Determining which CPU features are available and functional for a given
 +CPU type is possible with the `query-cpu-model-expansion` QMP command.
 +Below are some examples where `scripts/qmp/qmp-shell` (see the top comment
 +block in the script for usage) is used to issue the QMP commands.
 +
 +(1) Determine which CPU features are available for the `max` CPU type
 +    (Note, we started QEMU with qemu-system-aarch64, so `max` is
 +     implementing the ARMv8-A reference manual in this case)::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
 +      { "return": {
 +        "model": { "name": "max", "props": {
 +        "pmu": true, "aarch64": true
 +      }}}}
 +
 +We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
 +We also see that the CPU features are enabled, as they are all `true`.
 +
 +(2) Let's try to disable the PMU::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
 +      { "return": {
 +        "model": { "name": "max", "props": {
 +        "pmu": false, "aarch64": true
 +      }}}}
 +
 +We see it worked, as `pmu` is now `false`.
 +
 +(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}
 +      {"error": {
 +       "class": "GenericError", "desc":
 +       "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
 +      }}
 +
 +It looks like this feature is limited to a configuration we do not
 +currently have.
 +
 +(4) Let's try probing CPU features for the Cortex-A15 CPU type::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
 +      {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
 +
 +Only the `pmu` CPU feature is available.
 +
 +A note about CPU feature dependencies
 +-------------------------------------
 +
 +It's possible for features to have dependencies on other features. I.e.
 +it may be possible to change one feature at a time without error, but
 +when attempting to change all features at once an error could occur
 +depending on the order they are processed.  It's also possible changing
 +all at once doesn't generate an error, because a feature's dependencies
 +are satisfied with other features, but the same feature cannot be changed
 +independently without error.  For these reasons callers should always
 +attempt to make their desired changes all at once in order to ensure the
 +collection is valid.
 +
 +A note about CPU models and KVM
 +-------------------------------
 +
 +Named CPU models generally do not work with KVM.  There are a few cases
 +that do work, e.g. using the named CPU model `cortex-a57` with KVM on a
 +seattle host, but mostly if KVM is enabled the `host` CPU type must be
 +used.  This means the guest is provided all the same CPU features as the
 +host CPU type has.  And, for this reason, the `host` CPU type should
 +enable all CPU features that the host has by default.  Indeed it's even
 +a bit strange to allow disabling CPU features that the host has when using
 +the `host` CPU type, but in the absence of CPU models it's the best we can
 +do if we want to launch guests without all the host's CPU features enabled.
 +
 +Enabling KVM also affects the `query-cpu-model-expansion` QMP command.  The
 +affect is not only limited to specific features, as pointed out in example
 +(3) of "CPU Feature Probing", but also to which CPU types may be expanded.
 +When KVM is enabled, only the `max`, `host`, and current CPU type may be
 +expanded.  This restriction is necessary as it's not possible to know all
 +CPU types that may work with KVM, but it does impose a small risk of users
 +experiencing unexpected errors.  For example on a seattle, as mentioned
 +above, the `cortex-a57` CPU type is also valid when KVM is enabled.
 +Therefore a user could use the `host` CPU type for the current type, but
 +then attempt to query `cortex-a57`, however that query will fail with our
 +restrictions.  This shouldn't be an issue though as management layers and
 +users have been preferring the `host` CPU type for use with KVM for quite
 +some time.  Additionally, if the KVM-enabled QEMU instance running on a
 +seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57`
 +will work.
 +
 +Using CPU Features
 +==================
 +
 +After determining which CPU features are available and supported for a
 +given CPU type, then they may be selectively enabled or disabled on the
 +QEMU command line with that CPU type::
 +
 +  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
 +
 +The example above disables the PMU for the `max` CPU type.
 +
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 10/11] boards.h: Remove doc comment reference to nonexistent function
+[PULL 02/11] tests: arm: Introduce cpu feature tests
-commit b08199c6fbea1 accidentally added a reference to a doc
+From: Andrew Jones <drjones@redhat.com>
-comment to a nonexistent memory_region_allocate_aux_memory().
-This was a leftover from a previous version of the patchset
+Now that Arm CPUs have advertised features lets add tests to ensure
-which defined memory_region_allocate_aux_memory() for
+we maintain their expected availability with and without KVM.
-"allocate RAM MemoryRegion and register it for migration"
-and left "memory_region_init_ram()" with its original semantics
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-of "allocate RAM MR but do not register for migration". In
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-the end we decided on the approach of "memory_region_init_ram()
+Message-id: 20191031142734.8590-3-drjones@redhat.com
 registers the MR for migration, and memory_region_init_ram_nomigrate()
 is a new function which does not", but this comment change
 got left in by mistake. Revert that part of the commit.
 Reported-by: Thomas Huth <huth@tuxfamily.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180702130605.13611-1-peter.maydell@linaro.org
 ---
- include/hw/boards.h | 3 +--
+ tests/Makefile.include   |   5 +-
-file changed, 1 insertion(+), 2 deletions(-)
+ tests/arm-cpu-features.c | 253 +++++++++++++++++++++++++++++++++++++++
+files changed, 257 insertions(+), 1 deletion(-)
-diff --git a/include/hw/boards.h b/include/hw/boards.h
+ create mode 100644 tests/arm-cpu-features.c
 diff --git a/tests/Makefile.include b/tests/Makefile.include
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/boards.h
+--- a/tests/Makefile.include
-+++ b/include/hw/boards.h
++++ b/tests/Makefile.include
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
  check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
  check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
 +check-qtest-arm-y += tests/arm-cpu-features$(EXESUF)
  check-qtest-arm-y += tests/microbit-test$(EXESUF)
  check-qtest-arm-y += tests/m25p80-test$(EXESUF)
  check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
  check-qtest-arm-y += tests/hexloader-test$(EXESUF)
  check-qtest-arm-$(CONFIG_PFLASH_CFI02) += tests/pflash-cfi02-test$(EXESUF)
 -check-qtest-aarch64-y = tests/numa-test$(EXESUF)
 +check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF)
 +check-qtest-aarch64-y += tests/numa-test$(EXESUF)
  check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
  check-qtest-aarch64-y += tests/migration-test$(EXESUF)
  # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional
@@ -XXX,XX +XXX,XX @@ tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)
  tests/numa-test$(EXESUF): tests/numa-test.o
  tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o
  tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)
 +tests/arm-cpu-features$(EXESUF): tests/arm-cpu-features.o
  tests/migration/stress$(EXESUF): tests/migration/stress.o
      $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/tests/arm-cpu-features.c
 @@ -XXX,XX +XXX,XX @@
-  *
++/*
-  * Smaller pieces of memory (display RAM, static RAMs, etc) don't need
++ * Arm CPU feature test cases
-  * to be backed via the -mem-path memory backend and can simply
++ *
-- * be created via memory_region_allocate_aux_memory() or
++ * Copyright (c) 2019 Red Hat Inc.
-- * memory_region_init_ram().
++ * Authors:
-+ * be created via memory_region_init_ram().
++ *  Andrew Jones <drjones@redhat.com>
-  */
++ *
- void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
++ * This work is licensed under the terms of the GNU GPL, version 2 or later.
-                                           const char *name,
++ * See the COPYING file in the top-level directory.
 + */
 +#include "qemu/osdep.h"
 +#include "libqtest.h"
 +#include "qapi/qmp/qdict.h"
 +#include "qapi/qmp/qjson.h"
 +
 +#define MACHINE     "-machine virt,gic-version=max,accel=tcg "
 +#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
 +#define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
 +                    "  'arguments': { 'type': 'full', "
 +#define QUERY_TAIL  "}}"
 +
 +static bool kvm_enabled(QTestState *qts)
 +{
 +    QDict *resp, *qdict;
 +    bool enabled;
 +
 +    resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");
 +    g_assert(qdict_haskey(resp, "return"));
 +    qdict = qdict_get_qdict(resp, "return");
 +    g_assert(qdict_haskey(qdict, "enabled"));
 +    enabled = qdict_get_bool(qdict, "enabled");
 +    qobject_unref(resp);
 +
 +    return enabled;
 +}
 +
 +static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)
 +{
 +    return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"
 +                          QUERY_TAIL, cpu_type);
 +}
 +
 +static QDict *do_query(QTestState *qts, const char *cpu_type,
 +                       const char *fmt, ...)
 +{
 +    QDict *resp;
 +
 +    if (fmt) {
 +        QDict *args;
 +        va_list ap;
 +
 +        va_start(ap, fmt);
 +        args = qdict_from_vjsonf_nofail(fmt, ap);
 +        va_end(ap);
 +
 +        resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, "
 +                                                    "'props': %p }"
 +                              QUERY_TAIL, cpu_type, args);
 +    } else {
 +        resp = do_query_no_props(qts, cpu_type);
 +    }
 +
 +    return resp;
 +}
 +
 +static const char *resp_get_error(QDict *resp)
 +{
 +    QDict *qdict;
 +
 +    g_assert(resp);
 +
 +    qdict = qdict_get_qdict(resp, "error");
 +    if (qdict) {
 +        return qdict_get_str(qdict, "desc");
 +    }
 +
 +    return NULL;
 +}
 +
 +#define assert_error(qts, cpu_type, expected_error, fmt, ...)          \
 +({                                                                     \
 +    QDict *_resp;                                                      \
 +    const char *_error;                                                \
 +                                                                       \
 +    _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);               \
 +    g_assert(_resp);                                                   \
 +    _error = resp_get_error(_resp);                                    \
 +    g_assert(_error);                                                  \
 +    g_assert(g_str_equal(_error, expected_error));                     \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +static bool resp_has_props(QDict *resp)
 +{
 +    QDict *qdict;
 +
 +    g_assert(resp);
 +
 +    if (!qdict_haskey(resp, "return")) {
 +        return false;
 +    }
 +    qdict = qdict_get_qdict(resp, "return");
 +
 +    if (!qdict_haskey(qdict, "model")) {
 +        return false;
 +    }
 +    qdict = qdict_get_qdict(qdict, "model");
 +
 +    return qdict_haskey(qdict, "props");
 +}
 +
 +static QDict *resp_get_props(QDict *resp)
 +{
 +    QDict *qdict;
 +
 +    g_assert(resp);
 +    g_assert(resp_has_props(resp));
 +
 +    qdict = qdict_get_qdict(resp, "return");
 +    qdict = qdict_get_qdict(qdict, "model");
 +    qdict = qdict_get_qdict(qdict, "props");
 +
 +    return qdict;
 +}
 +
 +#define assert_has_feature(qts, cpu_type, feature)                     \
 +({                                                                     \
 +    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
 +    g_assert(_resp);                                                   \
 +    g_assert(resp_has_props(_resp));                                   \
 +    g_assert(qdict_get(resp_get_props(_resp), feature));               \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +#define assert_has_not_feature(qts, cpu_type, feature)                 \
 +({                                                                     \
 +    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
 +    g_assert(_resp);                                                   \
 +    g_assert(!resp_has_props(_resp) ||                                 \
 +             !qdict_get(resp_get_props(_resp), feature));              \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +static void assert_type_full(QTestState *qts)
 +{
 +    const char *error;
 +    QDict *resp;
 +
 +    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
 +                            "'arguments': { 'type': 'static', "
 +                                           "'model': { 'name': 'foo' }}}");
 +    g_assert(resp);
 +    error = resp_get_error(resp);
 +    g_assert(error);
 +    g_assert(g_str_equal(error,
 +                         "The requested expansion type is not supported"));
 +    qobject_unref(resp);
 +}
 +
 +static void assert_bad_props(QTestState *qts, const char *cpu_type)
 +{
 +    const char *error;
 +    QDict *resp;
 +
 +    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
 +                            "'arguments': { 'type': 'full', "
 +                                           "'model': { 'name': %s, "
 +                                                      "'props': false }}}",
 +                     cpu_type);
 +    g_assert(resp);
 +    error = resp_get_error(resp);
 +    g_assert(error);
 +    g_assert(g_str_equal(error,
 +                         "Invalid parameter type for 'props', expected: dict"));
 +    qobject_unref(resp);
 +}
 +
 +static void test_query_cpu_model_expansion(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE "-cpu max");
 +
 +    /* Test common query-cpu-model-expansion input validation */
 +    assert_type_full(qts);
 +    assert_bad_props(qts, "max");
 +    assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "
 +                 "ARM CPU type", NULL);
 +    assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",
 +                 "{ 'not-a-prop': false }");
 +    assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
 +
 +    /* Test expected feature presence/absence for some cpu types */
 +    assert_has_feature(qts, "max", "pmu");
 +    assert_has_feature(qts, "cortex-a15", "pmu");
 +    assert_has_not_feature(qts, "cortex-a15", "aarch64");
 +
 +    if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        assert_has_feature(qts, "max", "aarch64");
 +        assert_has_feature(qts, "cortex-a57", "pmu");
 +        assert_has_feature(qts, "cortex-a57", "aarch64");
 +
 +        /* Test that features that depend on KVM generate errors without. */
 +        assert_error(qts, "max",
 +                     "'aarch64' feature cannot be disabled "
 +                     "unless KVM is enabled and 32-bit EL1 "
 +                     "is supported",
 +                     "{ 'aarch64': false }");
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +static void test_query_cpu_model_expansion_kvm(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE_KVM "-cpu max");
 +
 +    /*
 +     * These tests target the 'host' CPU type, so KVM must be enabled.
 +     */
 +    if (!kvm_enabled(qts)) {
 +        qtest_quit(qts);
 +        return;
 +    }
 +
 +    if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        assert_has_feature(qts, "host", "aarch64");
 +        assert_has_feature(qts, "host", "pmu");
 +
 +        assert_error(qts, "cortex-a15",
 +            "We cannot guarantee the CPU type 'cortex-a15' works "
 +            "with KVM on this host", NULL);
 +    } else {
 +        assert_has_not_feature(qts, "host", "aarch64");
 +        assert_has_not_feature(qts, "host", "pmu");
 +    }
 +
 +    qtest_quit(qts);
 +}
 +
 +int main(int argc, char **argv)
 +{
 +    g_test_init(&argc, &argv, NULL);
 +
 +    qtest_add_data_func("/arm/query-cpu-model-expansion",
 +                        NULL, test_query_cpu_model_expansion);
 +    qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
 +                        NULL, test_query_cpu_model_expansion_kvm);
 +
 +    return g_test_run();
 +}
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 02/11] ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
+[PULL 03/11] target/arm: Allow SVE to be disabled via a CPU property
-The CMSDK timer behaviour is that an interrupt is triggered when the
+From: Andrew Jones <drjones@redhat.com>
 counter counts down from 1 to 0; however one is not triggered if the
 counter is manually set to 0 by a guest write to the counter register.
 Currently ptimer can't handle this; add a policy option to allow
 a ptimer user to request this behaviour.
+Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via
+a CPU property") we can disable the 'max' cpu model's VFP and neon
+features, but there's no way to disable SVE. Add the 'sve=on|off'
+property to give it that flexibility. We also rename
+cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
+to follow the typical *_get/set_<property-name> pattern.
+Signed-off-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
+Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
+Message-id: 20191031142734.8590-4-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Guenter Roeck <linux@roeck-us.net>
-Message-id: 20180703171044.9503-2-peter.maydell@linaro.org
 ---
- include/hw/ptimer.h |  9 +++++++++
+ target/arm/cpu.c         |  3 ++-
- hw/core/ptimer.c    | 22 +++++++++++++++++++++-
+ target/arm/cpu64.c       | 52 ++++++++++++++++++++++++++++++++++------
- tests/ptimer-test.c | 25 +++++++++++++++++++------
+ target/arm/monitor.c     |  2 +-
-files changed, 49 insertions(+), 7 deletions(-)
+ tests/arm-cpu-features.c |  1 +
 files changed, 49 insertions(+), 9 deletions(-)
-diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/ptimer.h
+--- a/target/arm/cpu.c
-+++ b/include/hw/ptimer.h
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
-  * not the one less.  */
+         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
- #define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
+         env->cp15.cptr_el[3] |= CPTR_EZ;
+         /* with maximum vector length */
-+/*
+-        env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
-+ * Starting to run with a zero counter, or setting the counter to "0" via
++        env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
-+ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer
++                             cpu->sve_max_vq - 1 : 0;
-+ * (though it will cause a reload). Only a counter decrement to "0"
+         env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
-+ * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
+         env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
-+ * ptimer_init() will assert() that you don't set both.
+         /*
-+ */
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-+#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
+index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
  }
 -static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
 -                               void *opaque, Error **errp)
 +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
 +                                   void *opaque, Error **errp)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 -    visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
 +    uint32_t value;
 +
- /* ptimer.c */
++    /* All vector lengths are disabled when SVE is off. */
- typedef struct ptimer_state ptimer_state;
++    if (!cpu_isar_feature(aa64_sve, cpu)) {
- typedef void (*ptimer_cb)(void *opaque);
++        value = 0;
-diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
++    } else {
-index XXXXXXX..XXXXXXX 100644
++        value = cpu->sve_max_vq;
 --- a/hw/core/ptimer.c
 +++ b/hw/core/ptimer.c
@@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
      uint32_t period_frac = s->period_frac;
      uint64_t period = s->period;
      uint64_t delta = s->delta;
 +    bool suppress_trigger = false;
 -    if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
 +    /*
 +     * Note that if delta_adjust is 0 then we must be here because of
 +     * a count register write or timer start, not because of timer expiry.
 +     * In that case the policy might require us to suppress the timer trigger
 +     * that we would otherwise generate for a zero delta.
 +     */
 +    if (delta_adjust == 0 &&
 +        (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
 +        suppress_trigger = true;
 +    }
-+    if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
++    visit_type_uint32(v, name, &value, errp);
-+        && !suppress_trigger) {
+ }
-         ptimer_trigger(s);
-     }
+-static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
+-                               void *opaque, Error **errp)
-@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
++static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
-     s->bh = bh;
++                                   void *opaque, Error **errp)
-     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
+ {
-     s->policy_mask = policy_mask;
+     ARMCPU *cpu = ARM_CPU(obj);
      Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
      error_propagate(errp, err);
  }
 +static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
 +                            void *opaque, Error **errp)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +    bool value = cpu_isar_feature(aa64_sve, cpu);
 +
-+    /*
++    visit_type_bool(v, name, &value, errp);
-+     * These two policies are incompatible -- trigger-on-decrement implies
++}
-+     * a timer trigger when the count becomes 0, but no-immediate-trigger
++
-+     * implies a trigger when the count stops being 0.
++static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
-+     */
++                            void *opaque, Error **errp)
-+    assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
++{
-+             (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
++    ARMCPU *cpu = ARM_CPU(obj);
-     return s;
++    Error *err = NULL;
- }
++    bool value;
++    uint64_t t;
-diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c
++
-index XXXXXXX..XXXXXXX 100644
++    visit_type_bool(v, name, &value, &err);
---- a/tests/ptimer-test.c
++    if (err) {
-+++ b/tests/ptimer-test.c
++        error_propagate(errp, err);
-@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
++        return;
      bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
      bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
      bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 +    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
      triggered = false;
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
      g_assert_cmpuint(ptimer_get_count(ptimer), ==,
                       no_immediate_reload ? 0 : 10);
 -    if (no_immediate_trigger) {
 +    if (no_immediate_trigger || trig_only_on_dec) {
          g_assert_false(triggered);
      } else {
          g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
      bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
      bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
      bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 +    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
      triggered = false;
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
      g_assert_cmpuint(ptimer_get_count(ptimer), ==,
                       no_immediate_reload ? 0 : 99);
 -    if (no_immediate_trigger) {
 +    if (no_immediate_trigger || trig_only_on_dec) {
          g_assert_false(triggered);
      } else {
          g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
      g_assert_cmpuint(ptimer_get_count(ptimer), ==,
                       no_immediate_reload ? 0 : 99);
 -    if (no_immediate_trigger) {
 +    if (no_immediate_trigger || trig_only_on_dec) {
          g_assert_false(triggered);
      } else {
          g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
      ptimer_state *ptimer = ptimer_init(bh, *policy);
      bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER);
      bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
 +    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
      triggered = false;
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
      g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
 -    if (no_immediate_trigger) {
 +    if (no_immediate_trigger || trig_only_on_dec) {
          g_assert_false(triggered);
      } else {
          g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
      QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL);
      ptimer_state *ptimer = ptimer_init(bh, *policy);
      bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
 +    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
      triggered = false;
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
      g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
 -    if (no_immediate_trigger) {
 +    if (no_immediate_trigger || trig_only_on_dec) {
          g_assert_false(triggered);
      } else {
          g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
          g_strlcat(policy_name, "no_counter_rounddown,", 256);
      }
 +    if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) {
 +        g_strlcat(policy_name, "trigger_only_on_decrement,", 256);
 +    }
 +
-     g_test_add_data_func_full(
++    t = cpu->isar.id_aa64pfr0;
-         tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name),
++    t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
-         g_memdup(&policy, 1), check_set_count, g_free);
++    cpu->isar.id_aa64pfr0 = t;
-@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
++}
++
- static void add_all_ptimer_policies_comb_tests(void)
+ /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
- {
+  * otherwise, a CPU with as many features enabled as our emulation supports.
--    int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN;
+  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
-+    int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-     int policy = PTIMER_POLICY_DEFAULT;
+ #endif
-     for (; policy < (last_policy << 1); policy++) {
+         cpu->sve_max_vq = ARM_MAX_VQ;
-+        if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
+-        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
-+            (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
+-                            cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
-+            /* Incompatible policy flag settings -- don't try to test them */
++        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
-+            continue;
++                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-+        }
++        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
-         add_ptimer_tests(policy);
++                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
      }
  }
+diff --git a/target/arm/monitor.c b/target/arm/monitor.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/monitor.c
++++ b/target/arm/monitor.c
+@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
+  * then the order that considers those dependencies must be used.
+  */
+ static const char *cpu_model_advertised_features[] = {
+-    "aarch64", "pmu",
++    "aarch64", "pmu", "sve",
+     NULL
+ };
+diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
+index XXXXXXX..XXXXXXX 100644
+--- a/tests/arm-cpu-features.c
++++ b/tests/arm-cpu-features.c
+@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
+     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+         assert_has_feature(qts, "max", "aarch64");
++        assert_has_feature(qts, "max", "sve");
+         assert_has_feature(qts, "cortex-a57", "pmu");
+         assert_has_feature(qts, "cortex-a57", "aarch64");
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 03/11] hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
+[PULL 04/11] target/arm/cpu64: max cpu: Introduce sve<N> properties
-The CMSDK timer interrupt triggers when the counter goes from 1 to 0,
+From: Andrew Jones <drjones@redhat.com>
 so we want to trigger immediately, rather than waiting for a
 clock cycle. Drop the incorrect NO_IMMEDIATE_TRIGGER setting.
 We also do not want to get an interrupt if the guest sets the
 counter directly to zero, so use the new TRIGGER_ONLY_ON_DECREMENT
 policy.
+Introduce cpu properties to give fine control over SVE vector lengths.
+We introduce a property for each valid length up to the current
+maximum supported, which is 2048-bits. The properties are named, e.g.
+sve128, sve256, sve384, sve512, ..., where the number is the number of
+bits. See the updates to docs/arm-cpu-features.rst for a description
+of the semantics and for example uses.
+Note, as sve-max-vq is still present and we'd like to be able to
+support qmp_query_cpu_model_expansion with guests launched with e.g.
+-cpu max,sve-max-vq=8 on their command lines, then we do allow
+sve-max-vq and sve<N> properties to be provided at the same time, but
+this is not recommended, and is why sve-max-vq is not mentioned in the
+document.  If sve-max-vq is provided then it enables all lengths smaller
+than and including the max and disables all lengths larger. It also has
+the side-effect that no larger lengths may be enabled and that the max
+itself cannot be disabled. Smaller non-power-of-two lengths may,
+however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
+guest the vector lengths 128, 256, and 512 bits.
+This patch has been co-authored with Richard Henderson, who reworked
+the target/arm/cpu64.c changes in order to push all the validation and
+auto-enabling/disabling steps into the finalizer, resulting in a nice
+LOC reduction.
+Signed-off-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
+Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
+Message-id: 20191031142734.8590-5-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Guenter Roeck <linux@roeck-us.net>
-Message-id: 20180703171044.9503-3-peter.maydell@linaro.org
 ---
- hw/timer/cmsdk-apb-timer.c | 2 +-
+ include/qemu/bitops.h     |   1 +
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/cpu.h          |  19 ++++
  target/arm/cpu.c          |  19 ++++
  target/arm/cpu64.c        | 192 ++++++++++++++++++++++++++++++++++++-
  target/arm/helper.c       |  10 +-
  target/arm/monitor.c      |  12 +++
  tests/arm-cpu-features.c  | 194 ++++++++++++++++++++++++++++++++++++++
  docs/arm-cpu-features.rst | 168 +++++++++++++++++++++++++++++++--
 files changed, 606 insertions(+), 9 deletions(-)
-diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
+diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/cmsdk-apb-timer.c
+--- a/include/qemu/bitops.h
-+++ b/hw/timer/cmsdk-apb-timer.c
++++ b/include/qemu/bitops.h
-@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@
-     bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
+ #define BITS_PER_LONG           (sizeof (unsigned long) * BITS_PER_BYTE)
-     s->timer = ptimer_init(bh,
-                            PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
+ #define BIT(nr)                 (1UL << (nr))
--                           PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
++#define BIT_ULL(nr)             (1ULL << (nr))
-+                           PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
+ #define BIT_MASK(nr)            (1UL << ((nr) % BITS_PER_LONG))
-                            PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
+ #define BIT_WORD(nr)            ((nr) / BITS_PER_LONG)
-                            PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+ #define BITS_TO_LONGS(nr)       DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
  #ifdef TARGET_AARCH64
  # define ARM_MAX_VQ    16
 +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
 +uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
  #else
  # define ARM_MAX_VQ    1
 +static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
 +static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
 +{ return 0; }
  #endif
  typedef struct ARMVectorReg {
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
      /* Used to set the maximum vector length the cpu will support.  */
      uint32_t sve_max_vq;
 +
 +    /*
 +     * In sve_vq_map each set bit is a supported vector length of
 +     * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
 +     * length in quadwords.
 +     *
 +     * While processing properties during initialization, corresponding
 +     * sve_vq_init bits are set for bits in sve_vq_map that have been
 +     * set by properties.
 +     */
 +    DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
 +    DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
  };
  void arm_cpu_post_init(Object *obj);
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
      return (env->features & (1ULL << feature)) != 0;
  }
 +void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
 +
  #if !defined(CONFIG_USER_ONLY)
  /* Return true if exception levels below EL3 are in secure state,
   * or would be following an exception return to that level.
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
  #endif
  }
 +void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
 +{
 +    Error *local_err = NULL;
 +
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        arm_cpu_sve_finalize(cpu, &local_err);
 +        if (local_err != NULL) {
 +            error_propagate(errp, local_err);
 +            return;
 +        }
 +    }
 +}
 +
  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
  {
      CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          return;
      }
 +    arm_cpu_finalize_features(cpu, &local_err);
 +    if (local_err != NULL) {
 +        error_propagate(errp, local_err);
 +        return;
 +    }
 +
      if (arm_feature(env, ARM_FEATURE_AARCH64) &&
          cpu->has_vfp != cpu->has_neon) {
          /*
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
  }
 +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
 +{
 +    /*
 +     * If any vector lengths are explicitly enabled with sve<N> properties,
 +     * then all other lengths are implicitly disabled.  If sve-max-vq is
 +     * specified then it is the same as explicitly enabling all lengths
 +     * up to and including the specified maximum, which means all larger
 +     * lengths will be implicitly disabled.  If no sve<N> properties
 +     * are enabled and sve-max-vq is not specified, then all lengths not
 +     * explicitly disabled will be enabled.  Additionally, all power-of-two
 +     * vector lengths less than the maximum enabled length will be
 +     * automatically enabled and all vector lengths larger than the largest
 +     * disabled power-of-two vector length will be automatically disabled.
 +     * Errors are generated if the user provided input that interferes with
 +     * any of the above.  Finally, if SVE is not disabled, then at least one
 +     * vector length must be enabled.
 +     */
 +    DECLARE_BITMAP(tmp, ARM_MAX_VQ);
 +    uint32_t vq, max_vq = 0;
 +
 +    /*
 +     * Process explicit sve<N> properties.
 +     * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
 +     * Check first for any sve<N> enabled.
 +     */
 +    if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
 +        max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
 +
 +        if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
 +            error_setg(errp, "cannot enable sve%d", max_vq * 128);
 +            error_append_hint(errp, "sve%d is larger than the maximum vector "
 +                              "length, sve-max-vq=%d (%d bits)\n",
 +                              max_vq * 128, cpu->sve_max_vq,
 +                              cpu->sve_max_vq * 128);
 +            return;
 +        }
 +
 +        /* Propagate enabled bits down through required powers-of-two. */
 +        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 +            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
 +                set_bit(vq - 1, cpu->sve_vq_map);
 +            }
 +        }
 +    } else if (cpu->sve_max_vq == 0) {
 +        /*
 +         * No explicit bits enabled, and no implicit bits from sve-max-vq.
 +         */
 +        if (!cpu_isar_feature(aa64_sve, cpu)) {
 +            /* SVE is disabled and so are all vector lengths.  Good. */
 +            return;
 +        }
 +
 +        /* Disabling a power-of-two disables all larger lengths. */
 +        if (test_bit(0, cpu->sve_vq_init)) {
 +            error_setg(errp, "cannot disable sve128");
 +            error_append_hint(errp, "Disabling sve128 results in all vector "
 +                              "lengths being disabled.\n");
 +            error_append_hint(errp, "With SVE enabled, at least one vector "
 +                              "length must be enabled.\n");
 +            return;
 +        }
 +        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
 +            if (test_bit(vq - 1, cpu->sve_vq_init)) {
 +                break;
 +            }
 +        }
 +        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 +
 +        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
 +        max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
 +    }
 +
 +    /*
 +     * Process the sve-max-vq property.
 +     * Note that we know from the above that no bit above
 +     * sve-max-vq is currently set.
 +     */
 +    if (cpu->sve_max_vq != 0) {
 +        max_vq = cpu->sve_max_vq;
 +
 +        if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
 +            test_bit(max_vq - 1, cpu->sve_vq_init)) {
 +            error_setg(errp, "cannot disable sve%d", max_vq * 128);
 +            error_append_hint(errp, "The maximum vector length must be "
 +                              "enabled, sve-max-vq=%d (%d bits)\n",
 +                              max_vq, max_vq * 128);
 +            return;
 +        }
 +
 +        /* Set all bits not explicitly set within sve-max-vq. */
 +        bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
 +        bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
 +    }
 +
 +    /*
 +     * We should know what max-vq is now.  Also, as we're done
 +     * manipulating sve-vq-map, we ensure any bits above max-vq
 +     * are clear, just in case anybody looks.
 +     */
 +    assert(max_vq != 0);
 +    bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
 +
 +    /* Ensure all required powers-of-two are enabled. */
 +    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 +        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
 +            error_setg(errp, "cannot disable sve%d", vq * 128);
 +            error_append_hint(errp, "sve%d is required as it "
 +                              "is a power-of-two length smaller than "
 +                              "the maximum, sve%d\n",
 +                              vq * 128, max_vq * 128);
 +            return;
 +        }
 +    }
 +
 +    /*
 +     * Now that we validated all our vector lengths, the only question
 +     * left to answer is if we even want SVE at all.
 +     */
 +    if (!cpu_isar_feature(aa64_sve, cpu)) {
 +        error_setg(errp, "cannot enable sve%d", max_vq * 128);
 +        error_append_hint(errp, "SVE must be enabled to enable vector "
 +                          "lengths.\n");
 +        error_append_hint(errp, "Add sve=on to the CPU property list.\n");
 +        return;
 +    }
 +
 +    /* From now on sve_max_vq is the actual maximum supported length. */
 +    cpu->sve_max_vq = max_vq;
 +}
 +
 +uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
 +{
 +    uint32_t bitnum;
 +
 +    /*
 +     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
 +     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
 +     * function always returns the next smaller than the input.
 +     */
 +    assert(vq && vq <= ARM_MAX_VQ + 1);
 +
 +    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
 +    return bitnum == vq - 1 ? 0 : bitnum + 1;
 +}
 +
  static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
                                     void *opaque, Error **errp)
  {
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
      error_propagate(errp, err);
  }
 +static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
 +                               void *opaque, Error **errp)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +    uint32_t vq = atoi(&name[3]) / 128;
 +    bool value;
 +
 +    /* All vector lengths are disabled when SVE is off. */
 +    if (!cpu_isar_feature(aa64_sve, cpu)) {
 +        value = false;
 +    } else {
 +        value = test_bit(vq - 1, cpu->sve_vq_map);
 +    }
 +    visit_type_bool(v, name, &value, errp);
 +}
 +
 +static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
 +                               void *opaque, Error **errp)
 +{
 +    ARMCPU *cpu = ARM_CPU(obj);
 +    uint32_t vq = atoi(&name[3]) / 128;
 +    Error *err = NULL;
 +    bool value;
 +
 +    visit_type_bool(v, name, &value, &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
 +    }
 +
 +    if (value) {
 +        set_bit(vq - 1, cpu->sve_vq_map);
 +    } else {
 +        clear_bit(vq - 1, cpu->sve_vq_map);
 +    }
 +    set_bit(vq - 1, cpu->sve_vq_init);
 +}
 +
  static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
                              void *opaque, Error **errp)
  {
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
  static void aarch64_max_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 +    uint32_t vq;
      if (kvm_enabled()) {
          kvm_arm_set_cpu_features_from_host(cpu);
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          cpu->dcz_blocksize = 7; /*  512 bytes */
  #endif
 -        cpu->sve_max_vq = ARM_MAX_VQ;
          object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                              cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
          object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                              cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +
 +        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +            char name[8];
 +            sprintf(name, "sve%d", vq * 128);
 +            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 +                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 +        }
      }
  }
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
      return 0;
  }
 +static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
 +{
 +    uint32_t start_vq = (start_len & 0xf) + 1;
 +
 +    return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
 +}
 +
  /*
   * Given that SVE is enabled, return the vector length for EL.
   */
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
      if (arm_feature(env, ARM_FEATURE_EL3)) {
          zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
      }
 -    return zcr_len;
 +
 +    return sve_zcr_get_valid_len(cpu, zcr_len);
  }
  static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 diff --git a/target/arm/monitor.c b/target/arm/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/monitor.c
 +++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
      return head;
  }
 +QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
 +
  /*
   * These are cpu model features we want to advertise. The order here
   * matters as this is the order in which qmp_query_cpu_model_expansion
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
   */
  static const char *cpu_model_advertised_features[] = {
      "aarch64", "pmu", "sve",
 +    "sve128", "sve256", "sve384", "sve512",
 +    "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
 +    "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
      NULL
  };
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
          if (!err) {
              visit_check_struct(visitor, &err);
          }
 +        if (!err) {
 +            arm_cpu_finalize_features(ARM_CPU(obj), &err);
 +        }
          visit_end_struct(visitor, NULL);
          visit_free(visitor);
          if (err) {
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
              error_propagate(errp, err);
              return NULL;
          }
 +    } else {
 +        Error *err = NULL;
 +        arm_cpu_finalize_features(ARM_CPU(obj), &err);
 +        assert(err == NULL);
      }
      expansion_info = g_new0(CpuModelExpansionInfo, 1);
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/arm-cpu-features.c
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
   * See the COPYING file in the top-level directory.
   */
  #include "qemu/osdep.h"
 +#include "qemu/bitops.h"
  #include "libqtest.h"
  #include "qapi/qmp/qdict.h"
  #include "qapi/qmp/qjson.h"
 +/*
 + * We expect the SVE max-vq to be 16. Also it must be <= 64
 + * for our test code, otherwise 'vls' can't just be a uint64_t.
 + */
 +#define SVE_MAX_VQ 16
 +
  #define MACHINE     "-machine virt,gic-version=max,accel=tcg "
  #define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
  #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
@@ -XXX,XX +XXX,XX @@ static void assert_bad_props(QTestState *qts, const char *cpu_type)
      qobject_unref(resp);
  }
 +static uint64_t resp_get_sve_vls(QDict *resp)
 +{
 +    QDict *props;
 +    const QDictEntry *e;
 +    uint64_t vls = 0;
 +    int n = 0;
 +
 +    g_assert(resp);
 +    g_assert(resp_has_props(resp));
 +
 +    props = resp_get_props(resp);
 +
 +    for (e = qdict_first(props); e; e = qdict_next(props, e)) {
 +        if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) &&
 +            g_ascii_isdigit(e->key[3])) {
 +            char *endptr;
 +            int bits;
 +
 +            bits = g_ascii_strtoll(&e->key[3], &endptr, 10);
 +            if (!bits || *endptr != '\0') {
 +                continue;
 +            }
 +
 +            if (qdict_get_bool(props, e->key)) {
 +                vls |= BIT_ULL((bits / 128) - 1);
 +            }
 +            ++n;
 +        }
 +    }
 +
 +    g_assert(n == SVE_MAX_VQ);
 +
 +    return vls;
 +}
 +
 +#define assert_sve_vls(qts, cpu_type, expected_vls, fmt, ...)          \
 +({                                                                     \
 +    QDict *_resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);        \
 +    g_assert(_resp);                                                   \
 +    g_assert(resp_has_props(_resp));                                   \
 +    g_assert(resp_get_sve_vls(_resp) == expected_vls);                 \
 +    qobject_unref(_resp);                                              \
 +})
 +
 +static void sve_tests_default(QTestState *qts, const char *cpu_type)
 +{
 +    /*
 +     * With no sve-max-vq or sve<N> properties on the command line
 +     * the default is to have all vector lengths enabled. This also
 +     * tests that 'sve' is 'on' by default.
 +     */
 +    assert_sve_vls(qts, cpu_type, BIT_ULL(SVE_MAX_VQ) - 1, NULL);
 +
 +    /* With SVE off, all vector lengths should also be off. */
 +    assert_sve_vls(qts, cpu_type, 0, "{ 'sve': false }");
 +
 +    /* With SVE on, we must have at least one vector length enabled. */
 +    assert_error(qts, cpu_type, "cannot disable sve128", "{ 'sve128': false }");
 +
 +    /* Basic enable/disable tests. */
 +    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve384': true }");
 +    assert_sve_vls(qts, cpu_type, ((BIT_ULL(SVE_MAX_VQ) - 1) & ~BIT_ULL(2)),
 +                   "{ 'sve384': false }");
 +
 +    /*
 +     * ---------------------------------------------------------------------
 +     *               power-of-two(vq)   all-power-            can      can
 +     *                                  of-two(< vq)        enable   disable
 +     * ---------------------------------------------------------------------
 +     * vq < max_vq      no                MUST*              yes      yes
 +     * vq < max_vq      yes               MUST*              yes      no
 +     * ---------------------------------------------------------------------
 +     * vq == max_vq     n/a               MUST*              yes**    yes**
 +     * ---------------------------------------------------------------------
 +     * vq > max_vq      n/a               no                 no       yes
 +     * vq > max_vq      n/a               yes                yes      yes
 +     * ---------------------------------------------------------------------
 +     *
 +     * [*] "MUST" means this requirement must already be satisfied,
 +     *     otherwise 'max_vq' couldn't itself be enabled.
 +     *
 +     * [**] Not testable with the QMP interface, only with the command line.
 +     */
 +
 +    /* max_vq := 8 */
 +    assert_sve_vls(qts, cpu_type, 0x8b, "{ 'sve1024': true }");
 +
 +    /* max_vq := 8, vq < max_vq, !power-of-two(vq) */
 +    assert_sve_vls(qts, cpu_type, 0x8f,
 +                   "{ 'sve1024': true, 'sve384': true }");
 +    assert_sve_vls(qts, cpu_type, 0x8b,
 +                   "{ 'sve1024': true, 'sve384': false }");
 +
 +    /* max_vq := 8, vq < max_vq, power-of-two(vq) */
 +    assert_sve_vls(qts, cpu_type, 0x8b,
 +                   "{ 'sve1024': true, 'sve256': true }");
 +    assert_error(qts, cpu_type, "cannot disable sve256",
 +                 "{ 'sve1024': true, 'sve256': false }");
 +
 +    /* max_vq := 3, vq > max_vq, !all-power-of-two(< vq) */
 +    assert_error(qts, cpu_type, "cannot disable sve512",
 +                 "{ 'sve384': true, 'sve512': false, 'sve640': true }");
 +
 +    /*
 +     * We can disable power-of-two vector lengths when all larger lengths
 +     * are also disabled. We only need to disable the power-of-two length,
 +     * as all non-enabled larger lengths will then be auto-disabled.
 +     */
 +    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve512': false }");
 +
 +    /* max_vq := 3, vq > max_vq, all-power-of-two(< vq) */
 +    assert_sve_vls(qts, cpu_type, 0x1f,
 +                   "{ 'sve384': true, 'sve512': true, 'sve640': true }");
 +    assert_sve_vls(qts, cpu_type, 0xf,
 +                   "{ 'sve384': true, 'sve512': true, 'sve640': false }");
 +}
 +
 +static void sve_tests_sve_max_vq_8(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE "-cpu max,sve-max-vq=8");
 +
 +    assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL);
 +
 +    /*
 +     * Disabling the max-vq set by sve-max-vq is not allowed, but
 +     * of course enabling it is OK.
 +     */
 +    assert_error(qts, "max", "cannot disable sve1024", "{ 'sve1024': false }");
 +    assert_sve_vls(qts, "max", 0xff, "{ 'sve1024': true }");
 +
 +    /*
 +     * Enabling anything larger than max-vq set by sve-max-vq is not
 +     * allowed, but of course disabling everything larger is OK.
 +     */
 +    assert_error(qts, "max", "cannot enable sve1152", "{ 'sve1152': true }");
 +    assert_sve_vls(qts, "max", 0xff, "{ 'sve1152': false }");
 +
 +    /*
 +     * We can enable/disable non power-of-two lengths smaller than the
 +     * max-vq set by sve-max-vq, but, while we can enable power-of-two
 +     * lengths, we can't disable them.
 +     */
 +    assert_sve_vls(qts, "max", 0xff, "{ 'sve384': true }");
 +    assert_sve_vls(qts, "max", 0xfb, "{ 'sve384': false }");
 +    assert_sve_vls(qts, "max", 0xff, "{ 'sve256': true }");
 +    assert_error(qts, "max", "cannot disable sve256", "{ 'sve256': false }");
 +
 +    qtest_quit(qts);
 +}
 +
 +static void sve_tests_sve_off(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE "-cpu max,sve=off");
 +
 +    /* SVE is off, so the map should be empty. */
 +    assert_sve_vls(qts, "max", 0, NULL);
 +
 +    /* The map stays empty even if we turn lengths off. */
 +    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
 +
 +    /* It's an error to enable lengths when SVE is off. */
 +    assert_error(qts, "max", "cannot enable sve128", "{ 'sve128': true }");
 +
 +    /* With SVE re-enabled we should get all vector lengths enabled. */
 +    assert_sve_vls(qts, "max", BIT_ULL(SVE_MAX_VQ) - 1, "{ 'sve': true }");
 +
 +    /* Or enable SVE with just specific vector lengths. */
 +    assert_sve_vls(qts, "max", 0x3,
 +                   "{ 'sve': true, 'sve128': true, 'sve256': true }");
 +
 +    qtest_quit(qts);
 +}
 +
  static void test_query_cpu_model_expansion(const void *data)
  {
      QTestState *qts;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
          assert_has_feature(qts, "max", "aarch64");
          assert_has_feature(qts, "max", "sve");
 +        assert_has_feature(qts, "max", "sve128");
          assert_has_feature(qts, "cortex-a57", "pmu");
          assert_has_feature(qts, "cortex-a57", "aarch64");
 +        sve_tests_default(qts, "max");
 +
          /* Test that features that depend on KVM generate errors without. */
          assert_error(qts, "max",
                       "'aarch64' feature cannot be disabled "
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
      qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                          NULL, test_query_cpu_model_expansion_kvm);
 +    if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
 +                            NULL, sve_tests_sve_max_vq_8);
 +        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
 +                            NULL, sve_tests_sve_off);
 +    }
 +
      return g_test_run();
  }
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/arm-cpu-features.rst
 +++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ block in the script for usage) is used to issue the QMP commands.
        (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
        { "return": {
          "model": { "name": "max", "props": {
 -        "pmu": true, "aarch64": true
 +        "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
 +        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
 +        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
 +        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
 +        "sve896": true, "sve1280": true, "sve2048": true
        }}}}
 -We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
 -We also see that the CPU features are enabled, as they are all `true`.
 +We see that the `max` CPU type has the `pmu`, `aarch64`, `sve`, and many
 +`sve<N>` CPU features.  We also see that all the CPU features are
 +enabled, as they are all `true`.  (The `sve<N>` CPU features are all
 +optional SVE vector lengths (see "SVE CPU Properties").  While with TCG
 +all SVE vector lengths can be supported, when KVM is in use it's more
 +likely that only a few lengths will be supported, if SVE is supported at
 +all.)
  (2) Let's try to disable the PMU::
        (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
        { "return": {
          "model": { "name": "max", "props": {
 -        "pmu": false, "aarch64": true
 +        "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
 +        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
 +        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
 +        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
 +        "sve896": true, "sve1280": true, "sve2048": true
        }}}}
  We see it worked, as `pmu` is now `false`.
@@ -XXX,XX +XXX,XX @@ We see it worked, as `pmu` is now `false`.
  It looks like this feature is limited to a configuration we do not
  currently have.
 -(4) Let's try probing CPU features for the Cortex-A15 CPU type::
 +(4) Let's disable `sve` and see what happens to all the optional SVE
 +    vector lengths::
 +
 +      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}}
 +      { "return": {
 +        "model": { "name": "max", "props": {
 +        "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
 +        "sve128": false, "aarch64": true, "sve1024": false, "sve": false,
 +        "sve640": false, "sve768": false, "sve1408": false, "sve256": false,
 +        "sve1152": false, "sve512": false, "sve384": false, "sve1536": false,
 +        "sve896": false, "sve1280": false, "sve2048": false
 +      }}}}
 +
 +As expected they are now all `false`.
 +
 +(5) Let's try probing CPU features for the Cortex-A15 CPU type::
        (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
        {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
@@ -XXX,XX +XXX,XX @@ After determining which CPU features are available and supported for a
  given CPU type, then they may be selectively enabled or disabled on the
  QEMU command line with that CPU type::
 -  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
 +  $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
 -The example above disables the PMU for the `max` CPU type.
 +The example above disables the PMU and enables the first two SVE vector
 +lengths for the `max` CPU type.  Note, the `sve=on` isn't actually
 +necessary, because, as we observed above with our probe of the `max` CPU
 +type, `sve` is already on by default.  Also, based on our probe of
 +defaults, it would seem we need to disable many SVE vector lengths, rather
 +than only enabling the two we want.  This isn't the case, because, as
 +disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
 +properties have special semantics (see "SVE CPU Property Parsing
 +Semantics").
 +
 +SVE CPU Properties
 +==================
 +
 +There are two types of SVE CPU properties: `sve` and `sve<N>`.  The first
 +is used to enable or disable the entire SVE feature, just as the `pmu`
 +CPU property completely enables or disables the PMU.  The second type
 +is used to enable or disable specific vector lengths, where `N` is the
 +number of bits of the length.  The `sve<N>` CPU properties have special
 +dependencies and constraints, see "SVE CPU Property Dependencies and
 +Constraints" below.  Additionally, as we want all supported vector lengths
 +to be enabled by default, then, in order to avoid overly verbose command
 +lines (command lines full of `sve<N>=off`, for all `N` not wanted), we
 +provide the parsing semantics listed in "SVE CPU Property Parsing
 +Semantics".
 +
 +SVE CPU Property Dependencies and Constraints
 +---------------------------------------------
 +
 +  1) At least one vector length must be enabled when `sve` is enabled.
 +
 +  2) If a vector length `N` is enabled, then all power-of-two vector
 +     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
 +     is enabled, then the 128-bit and 256-bit vector lengths must also
 +     be enabled.
 +
 +SVE CPU Property Parsing Semantics
 +----------------------------------
 +
 +  1) If SVE is disabled (`sve=off`), then which SVE vector lengths
 +     are enabled or disabled is irrelevant to the guest, as the entire
 +     SVE feature is disabled and that disables all vector lengths for
 +     the guest.  However QEMU will still track any `sve<N>` CPU
 +     properties provided by the user.  If later an `sve=on` is provided,
 +     then the guest will get only the enabled lengths.  If no `sve=on`
 +     is provided and there are explicitly enabled vector lengths, then
 +     an error is generated.
 +
 +  2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
 +     provided, then all supported vector lengths are enabled, including
 +     the non-power-of-two lengths.
 +
 +  3) If SVE is enabled, then an error is generated when attempting to
 +     disable the last enabled vector length (see constraint (1) of "SVE
 +     CPU Property Dependencies and Constraints").
 +
 +  4) If one or more vector lengths have been explicitly enabled and at
 +     at least one of the dependency lengths of the maximum enabled length
 +     has been explicitly disabled, then an error is generated (see
 +     constraint (2) of "SVE CPU Property Dependencies and Constraints").
 +
 +  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
 +     CPU properties are set `on`, then the specified vector lengths are
 +     disabled but the default for any unspecified lengths remains enabled.
 +     Disabling a power-of-two vector length also disables all vector
 +     lengths larger than the power-of-two length (see constraint (2) of
 +     "SVE CPU Property Dependencies and Constraints").
 +
 +  6) If one or more `sve<N>` CPU properties are set to `on`, then they
 +     are enabled and all unspecified lengths default to disabled, except
 +     for the required lengths per constraint (2) of "SVE CPU Property
 +     Dependencies and Constraints", which will even be auto-enabled if
 +     they were not explicitly enabled.
 +
 +  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
 +     explicitly disabled (i.e. avoiding the error specified in (3) of
 +     "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
 +     provided an error will be generated.  To avoid this error, one must
 +     enable at least one vector length prior to enabling SVE.
 +
 +SVE CPU Property Examples
 +-------------------------
 +
 +  1) Disable SVE::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve=off
 +
 +  2) Implicitly enable all vector lengths for the `max` CPU type::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max
 +
 +  3) Only enable the 128-bit vector length::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve128=on
 +
 +  4) Disable the 512-bit vector length and all larger vector lengths,
 +     since 512 is a power-of-two.  This results in all the smaller,
 +     uninitialized lengths (128, 256, and 384) defaulting to enabled::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve512=off
 +
 +  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
 +
 +  6) The same as (5), but since the 128-bit and 256-bit vector
 +     lengths are required for the 512-bit vector length to be enabled,
 +     then allow them to be auto-enabled::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve512=on
 +
 +  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
 +
 +  8) Force errors regarding the last vector length::
 +
 +     $ qemu-system-aarch64 -M virt -cpu max,sve128=off
 +     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
 +
 +SVE CPU Property Recommendations
 +--------------------------------
 +
 +The examples in "SVE CPU Property Examples" exhibit many ways to select
 +vector lengths which developers may find useful in order to avoid overly
 +verbose command lines.  However, the recommended way to select vector
 +lengths is to explicitly enable each desired length.  Therefore only
 +example's (1), (3), and (5) exhibit recommended uses of the properties.
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 08/11] target/arm: Fix do_predset for large VL
+[PULL 05/11] target/arm/kvm64: Add kvm_arch_get/put_sve
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-Use MAKE_64BIT_MASK instead of open-coding.  Remove an odd
+These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
-vector size check that is unlikely to be more profitable
+swabbing is different than it is for fpsmid because the vector format
-than 3 64-bit integer stores.  Correct the iteration for WORD
+is a little-endian stream of words.
-to avoid writing too much data.
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-Fixes RISU tests of PTRUE for VL 256.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20191031142734.8590-6-drjones@redhat.com
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20180705191929.30773-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-sve.c | 10 ++--------
+ target/arm/kvm64.c | 185 ++++++++++++++++++++++++++++++++++++++-------
-file changed, 2 insertions(+), 8 deletions(-)
+file changed, 156 insertions(+), 29 deletions(-)
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-sve.c
+--- a/target/arm/kvm64.c
-+++ b/target/arm/translate-sve.c
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_destroy_vcpu(CPUState *cs)
-         setsz = numelem << esz;
+ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
-         lastword = word = pred_esz_masks[esz];
+ {
-         if (setsz % 64) {
+     /* Return true if the regidx is a register we should synchronize
--            lastword &= ~(-1ull << (setsz % 64));
+-     * via the cpreg_tuples array (ie is not a core reg we sync by
-+            lastword &= MAKE_64BIT_MASK(0, setsz % 64);
+-     * hand in kvm_arch_get/put_registers())
 +     * via the cpreg_tuples array (ie is not a core or sve reg that
 +     * we sync by hand in kvm_arch_get/put_registers())
       */
      switch (regidx & KVM_REG_ARM_COPROC_MASK) {
      case KVM_REG_ARM_CORE:
 +    case KVM_REG_ARM64_SVE:
          return false;
      default:
          return true;
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
  static int kvm_arch_put_fpsimd(CPUState *cs)
  {
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 +    CPUARMState *env = &ARM_CPU(cs)->env;
      struct kvm_one_reg reg;
 -    uint32_t fpr;
      int i, ret;
      for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_fpsimd(CPUState *cs)
          }
      }
-@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
+-    reg.addr = (uintptr_t)(&fpr);
-             tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
+-    fpr = vfp_get_fpsr(env);
-             goto done;
+-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 -    if (ret) {
 -        return ret;
 +    return 0;
 +}
 +
 +/*
 + * SVE registers are encoded in KVM's memory in an endianness-invariant format.
 + * The byte at offset i from the start of the in-memory representation contains
 + * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
 + * lowest offsets are stored in the lowest memory addresses, then that nearly
 + * matches QEMU's representation, which is to use an array of host-endian
 + * uint64_t's, where the lower offsets are at the lower indices. To complete
 + * the translation we just need to byte swap the uint64_t's on big-endian hosts.
 + */
 +static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
 +{
 +#ifdef HOST_WORDS_BIGENDIAN
 +    int i;
 +
 +    for (i = 0; i < nr; ++i) {
 +        dst[i] = bswap64(src[i]);
      }
 -    reg.addr = (uintptr_t)(&fpr);
 -    fpr = vfp_get_fpcr(env);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +    return dst;
 +#else
 +    return src;
 +#endif
 +}
 +
 +/*
 + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
 + * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
 + * code the slice index to zero for now as it's unlikely we'll need more than
 + * one slice for quite some time.
 + */
 +static int kvm_arch_put_sve(CPUState *cs)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    uint64_t tmp[ARM_MAX_VQ * 2];
 +    uint64_t *r;
 +    struct kvm_one_reg reg;
 +    int n, ret;
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
 +        r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +    }
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
 +        r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
 +                        DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +    }
 +
 +    r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
 +                    DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 +    reg.addr = (uintptr_t)r;
 +    reg.id = KVM_REG_ARM64_SVE_FFR(0);
      ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
      if (ret) {
          return ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
  {
      struct kvm_one_reg reg;
      uint64_t val;
 +    uint32_t fpr;
      int i, ret;
      unsigned int el;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
          }
--        if (oprsz * 8 == setsz + 8) {
+     }
--            tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
--            tcg_gen_movi_i64(t, 0);
+-    ret = kvm_arch_put_fpsimd(cs);
--            tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
++    if (cpu_isar_feature(aa64_sve, cpu)) {
--            goto done;
++        ret = kvm_arch_put_sve(cs);
--        }
++    } else {
-     }
++        ret = kvm_arch_put_fpsimd(cs);
++    }
-     setsz /= 8;
++    if (ret) {
-     fullsz /= 8;
++        return ret;
++    }
-     tcg_gen_movi_i64(t, word);
++
--    for (i = 0; i < setsz; i += 8) {
++    reg.addr = (uintptr_t)(&fpr);
-+    for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
++    fpr = vfp_get_fpsr(env);
-         tcg_gen_st_i64(t, cpu_env, ofs + i);
++    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-     }
++    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
-     if (lastword != word) {
++    if (ret) {
 +        return ret;
 +    }
 +
 +    reg.addr = (uintptr_t)(&fpr);
 +    fpr = vfp_get_fpcr(env);
 +    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
      if (ret) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
  static int kvm_arch_get_fpsimd(CPUState *cs)
  {
 -    ARMCPU *cpu = ARM_CPU(cs);
 -    CPUARMState *env = &cpu->env;
 +    CPUARMState *env = &ARM_CPU(cs)->env;
      struct kvm_one_reg reg;
 -    uint32_t fpr;
      int i, ret;
      for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_fpsimd(CPUState *cs)
          }
      }
 -    reg.addr = (uintptr_t)(&fpr);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 -    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 -    if (ret) {
 -        return ret;
 -    }
 -    vfp_set_fpsr(env, fpr);
 +    return 0;
 +}
 -    reg.addr = (uintptr_t)(&fpr);
 -    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +/*
 + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
 + * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
 + * code the slice index to zero for now as it's unlikely we'll need more than
 + * one slice for quite some time.
 + */
 +static int kvm_arch_get_sve(CPUState *cs)
 +{
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    CPUARMState *env = &cpu->env;
 +    struct kvm_one_reg reg;
 +    uint64_t *r;
 +    int n, ret;
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
 +        r = &env->vfp.zregs[n].d[0];
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +        sve_bswap64(r, r, cpu->sve_max_vq * 2);
 +    }
 +
 +    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
 +        r = &env->vfp.pregs[n].p[0];
 +        reg.addr = (uintptr_t)r;
 +        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
 +        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +        if (ret) {
 +            return ret;
 +        }
 +        sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 +    }
 +
 +    r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
 +    reg.addr = (uintptr_t)r;
 +    reg.id = KVM_REG_ARM64_SVE_FFR(0);
      ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
      if (ret) {
          return ret;
      }
 -    vfp_set_fpcr(env, fpr);
 +    sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
      struct kvm_one_reg reg;
      uint64_t val;
      unsigned int el;
 +    uint32_t fpr;
      int i, ret;
      ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
          env->spsr = env->banked_spsr[i];
      }
 -    ret = kvm_arch_get_fpsimd(cs);
 +    if (cpu_isar_feature(aa64_sve, cpu)) {
 +        ret = kvm_arch_get_sve(cs);
 +    } else {
 +        ret = kvm_arch_get_fpsimd(cs);
 +    }
      if (ret) {
          return ret;
      }
 +    reg.addr = (uintptr_t)(&fpr);
 +    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
 +    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    if (ret) {
 +        return ret;
 +    }
 +    vfp_set_fpsr(env, fpr);
 +
 +    reg.addr = (uintptr_t)(&fpr);
 +    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
 +    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
 +    if (ret) {
 +        return ret;
 +    }
 +    vfp_set_fpcr(env, fpr);
 +
      ret = kvm_get_vcpu_events(cpu);
      if (ret) {
          return ret;
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 05/11] hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
+[PULL 06/11] target/arm/kvm64: max cpu: Enable SVE when available
-If the CMSDK APB timer is set up with a zero RELOAD value
+From: Andrew Jones <drjones@redhat.com>
-then it will count down to zero, fire once and then stay
-at zero. From the point of view of the ptimer system, the
+Enable SVE in the KVM guest when the 'max' cpu type is configured
-timer is disabled; but the enable bit in the CTRL register
+and KVM supports it. KVM SVE requires use of the new finalize
-is still set and if the guest subsequently writes to the
+vcpu ioctl, so we add that now too. For starters SVE can only be
-RELOAD or VALUE registers this should cause the timer to
+turned on or off, getting all vector lengths the host CPU supports
-start counting down again.
+when on. We'll add the other SVE CPU properties in later patches.
-Add code to the write paths for RELOAD and VALUE so that
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-we correctly restart the timer in this situation.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Conversely, if the new RELOAD and VALUE are both zero,
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-we should stop the ptimer.
+Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
+Message-id: 20191031142734.8590-7-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Guenter Roeck <linux@roeck-us.net>
-Message-id: 20180703171044.9503-5-peter.maydell@linaro.org
 ---
- hw/timer/cmsdk-apb-timer.c | 16 ++++++++++++++++
+ target/arm/kvm_arm.h     | 27 +++++++++++++++++++++++++++
-file changed, 16 insertions(+)
+ target/arm/cpu64.c       | 17 ++++++++++++++---
+ target/arm/kvm.c         |  5 +++++
-diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
+ target/arm/kvm64.c       | 20 +++++++++++++++++++-
-index XXXXXXX..XXXXXXX 100644
+ tests/arm-cpu-features.c |  4 ++++
---- a/hw/timer/cmsdk-apb-timer.c
+files changed, 69 insertions(+), 4 deletions(-)
-+++ b/hw/timer/cmsdk-apb-timer.c
-@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
-         break;
+index XXXXXXX..XXXXXXX 100644
-     case A_RELOAD:
+--- a/target/arm/kvm_arm.h
-         /* Writing to reload also sets the current timer value */
++++ b/target/arm/kvm_arm.h
-+        if (!value) {
+@@ -XXX,XX +XXX,XX @@
-+            ptimer_stop(s->timer);
+  */
  int kvm_arm_vcpu_init(CPUState *cs);
 +/**
 + * kvm_arm_vcpu_finalize
 + * @cs: CPUState
 + * @feature: int
 + *
 + * Finalizes the configuration of the specified VCPU feature by
 + * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
 + * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of
 + * KVM's API documentation.
 + *
 + * Returns: 0 if success else < 0 error code
 + */
 +int kvm_arm_vcpu_finalize(CPUState *cs, int feature);
 +
  /**
   * kvm_arm_register_device:
   * @mr: memory region for this device
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
   */
  bool kvm_arm_pmu_supported(CPUState *cs);
 +/**
 + * bool kvm_arm_sve_supported:
 + * @cs: CPUState
 + *
 + * Returns true if the KVM VCPU can enable SVE and false otherwise.
 + */
 +bool kvm_arm_sve_supported(CPUState *cs);
 +
  /**
   * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
   * IPA address space supported by KVM
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_pmu_supported(CPUState *cs)
      return false;
  }
 +static inline bool kvm_arm_sve_supported(CPUState *cs)
 +{
 +    return false;
 +}
 +
  static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
  {
      return -ENOENT;
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
          return;
      }
 +    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
 +        error_setg(errp, "'sve' feature not supported by KVM on this host");
 +        return;
 +    }
 +
      t = cpu->isar.id_aa64pfr0;
      t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
      cpu->isar.id_aa64pfr0 = t;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
      uint32_t vq;
 +    uint64_t t;
      if (kvm_enabled()) {
          kvm_arm_set_cpu_features_from_host(cpu);
 +        if (kvm_arm_sve_supported(CPU(cpu))) {
 +            t = cpu->isar.id_aa64pfr0;
 +            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 +            cpu->isar.id_aa64pfr0 = t;
 +        }
-         ptimer_set_limit(s->timer, value, 1);
+     } else {
-+        if (value && (s->ctrl & R_CTRL_EN_MASK)) {
+-        uint64_t t;
-+            /*
+         uint32_t u;
-+             * Make sure timer is running (it might have stopped if this
+         aarch64_a57_initfn(obj);
-+             * was an expired one-shot timer)
-+             */
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-+            ptimer_run(s->timer, 0);
          object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                              cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 -        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 -                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
          for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
              char name[8];
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
                                  cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
          }
      }
 +
 +    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 +                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
  }
  struct ARMCPUInfo {
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs)
      return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
  }
 +int kvm_arm_vcpu_finalize(CPUState *cs, int feature)
 +{
 +    return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature);
 +}
 +
  void kvm_arm_init_serror_injection(CPUState *cs)
  {
      cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cpu)
      return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
  }
 +bool kvm_arm_sve_supported(CPUState *cpu)
 +{
 +    KVMState *s = KVM_STATE(current_machine->accelerator);
 +
 +    return kvm_check_extension(s, KVM_CAP_ARM_SVE);
 +}
 +
  #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
  int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
      }
      if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
 -            cpu->has_pmu = false;
 +        cpu->has_pmu = false;
      }
      if (cpu->has_pmu) {
          cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
      } else {
          unset_feature(&env->features, ARM_FEATURE_PMU);
      }
 +    if (cpu_isar_feature(aa64_sve, cpu)) {
 +        assert(kvm_arm_sve_supported(cs));
 +        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
 +    }
      /* Do KVM_ARM_VCPU_INIT ioctl */
      ret = kvm_arm_vcpu_init(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
          return ret;
      }
 +    if (cpu_isar_feature(aa64_sve, cpu)) {
 +        ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
 +        if (ret) {
 +            return ret;
 +        }
-         break;
++    }
-     case A_VALUE:
++
-+        if (!value && !ptimer_get_limit(s->timer)) {
+     /*
-+            ptimer_stop(s->timer);
+      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
-+        }
+      * Currently KVM has its own idea about MPIDR assignment, so we
-         ptimer_set_count(s->timer, value);
+diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
-+        if (value && (s->ctrl & R_CTRL_EN_MASK)) {
+index XXXXXXX..XXXXXXX 100644
-+            ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
+--- a/tests/arm-cpu-features.c
-+        }
++++ b/tests/arm-cpu-features.c
-         break;
+@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
-     case A_INTSTATUS:
+         assert_has_feature(qts, "host", "aarch64");
-         /* Just one bit, which is W1C. */
+         assert_has_feature(qts, "host", "pmu");
 +        assert_has_feature(qts, "max", "sve");
 +
          assert_error(qts, "cortex-a15",
              "We cannot guarantee the CPU type 'cortex-a15' works "
              "with KVM on this host", NULL);
      } else {
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
 +
 +        assert_has_not_feature(qts, "max", "sve");
      }
      qtest_quit(qts);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 04/11] hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
+[PULL 07/11] target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
-From: Guenter Roeck <linux@roeck-us.net>
+From: Andrew Jones <drjones@redhat.com>
-The CMSDK APB timer is currently always configured as periodic timer.
+kvm_arm_create_scratch_host_vcpu() takes a struct kvm_vcpu_init
-This results in the following messages when trying to boot Linux.
+parameter. Rather than just using it as an output parameter to
 pass back the preferred target, use it also as an input parameter,
 allowing a caller to pass a selected target if they wish and to
 also pass cpu features. If the caller doesn't want to select a
 target they can pass -1 for the target which indicates they want
 to use the preferred target and have it passed back like before.
-Timer with delta zero, disabling
+Signed-off-by: Andrew Jones <drjones@redhat.com>
 If the timer limit set with the RELOAD command is 0, the timer
 needs to be enabled as one-shot timer.
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Tested-by: Guenter Roeck <linux@roeck-us.net>
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
 Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
 Message-id: 20191031142734.8590-8-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/timer/cmsdk-apb-timer.c | 2 +-
+ target/arm/kvm.c   | 20 +++++++++++++++-----
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/kvm32.c |  6 +++++-
  target/arm/kvm64.c |  6 +++++-
 files changed, 25 insertions(+), 7 deletions(-)
-diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/timer/cmsdk-apb-timer.c
+--- a/target/arm/kvm.c
-+++ b/hw/timer/cmsdk-apb-timer.c
++++ b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
                                        int *fdarray,
                                        struct kvm_vcpu_init *init)
  {
 -    int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
 +    int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1;
      kvmfd = qemu_open("/dev/kvm", O_RDWR);
      if (kvmfd < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
          goto finish;
      }
 -    ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
 +    if (init->target == -1) {
 +        struct kvm_vcpu_init preferred;
 +
 +        ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred);
 +        if (!ret) {
 +            init->target = preferred.target;
 +        }
 +    }
      if (ret >= 0) {
          ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
          if (ret < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
           * creating one kind of guest CPU which is its preferred
           * CPU type.
           */
 +        struct kvm_vcpu_init try;
 +
          while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
 -            init->target = *cpus_to_try++;
 -            memset(init->features, 0, sizeof(init->features));
 -            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
 +            try.target = *cpus_to_try++;
 +            memcpy(try.features, init->features, sizeof(init->features));
 +            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try);
              if (ret >= 0) {
                  break;
              }
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
          if (ret < 0) {
              goto err;
          }
-         s->ctrl = value & 0xf;
++        init->target = try.target;
-         if (s->ctrl & R_CTRL_EN_MASK) {
+     } else {
--            ptimer_run(s->timer, 0);
+         /* Treat a NULL cpus_to_try argument the same as an empty
-+            ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
+          * list, which means we will fail the call since this must
-         } else {
+diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
-             ptimer_stop(s->timer);
+index XXXXXXX..XXXXXXX 100644
-         }
+--- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          QEMU_KVM_ARM_TARGET_CORTEX_A15,
          QEMU_KVM_ARM_TARGET_NONE
      };
 -    struct kvm_vcpu_init init;
 +    /*
 +     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
 +     * to use the preferred target
 +     */
 +    struct kvm_vcpu_init init = { .target = -1, };
      if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
          return false;
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          KVM_ARM_TARGET_CORTEX_A57,
          QEMU_KVM_ARM_TARGET_NONE
      };
 -    struct kvm_vcpu_init init;
 +    /*
 +     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
 +     * to use the preferred target
 +     */
 +    struct kvm_vcpu_init init = { .target = -1, };
      if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
          return false;
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 09/11] hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
+[PULL 08/11] target/arm/cpu64: max cpu: Support sve properties with KVM
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Andrew Jones <drjones@redhat.com>
-DeviceClass::reset models a "cold power-on" reset which can
+Extend the SVE vq map initialization and validation with KVM's
-also be used to powercycle a device; but there is no "hot reset"
+supported vector lengths when KVM is enabled. In order to determine
-(a.k.a. soft-reset) method available.
+and select supported lengths we add two new KVM functions for getting
 and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.
-The OMAP MMC Power-Up Control bit is not designed to powercycle
+This patch has been co-authored with Richard Henderson, who reworked
-a card, but to disable it without powering it off (pseudo-reset):
+the target/arm/cpu64.c changes in order to push all the validation and
 auto-enabling/disabling steps into the finalizer, resulting in a nice
 LOC reduction.
-  Multimedia Card (MMC/SD/SDIO) Interface [SPRU765A]
+Signed-off-by: Andrew Jones <drjones@redhat.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-  MMC_CON[11] Power-Up Control (POW)
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-  This bit must be set to 1 before any valid transaction to either
+Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
-  MMC/SD or SPI memory cards.
+Message-id: 20191031142734.8590-9-drjones@redhat.com
   When 1, the card is considered powered-up and the controller core
   is enabled.
   When 0, the card is considered powered-down (system dependent),
   and the controller core logic is in pseudo-reset state. This is,
   the MMC_STAT flags and the FIFO pointers are reset, any access to
   MMC_DATA[DATA] has no effect, a write into the MMC.CMD register
   is ignored, and a setting of MMC_SPI[STR] to 1 is ignored.
 By splitting the 'pseudo-reset' code out of the 'power-on' reset
 function, this patch fixes a latent bug in omap_mmc_write(MMC_CON)i
 recently exposed by ecd219f7abb.
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180706162155.8432-2-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/sd/omap_mmc.c | 14 +++++++++++---
+ target/arm/kvm_arm.h      |  12 +++
-file changed, 11 insertions(+), 3 deletions(-)
+ target/arm/cpu64.c        | 176 ++++++++++++++++++++++++++++----------
  target/arm/kvm64.c        | 100 +++++++++++++++++++++-
  tests/arm-cpu-features.c  | 104 +++++++++++++++++++++-
  docs/arm-cpu-features.rst |  45 +++++++---
 files changed, 379 insertions(+), 58 deletions(-)
-diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/omap_mmc.c
+--- a/target/arm/kvm_arm.h
-+++ b/hw/sd/omap_mmc.c
++++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
- /*
+  */
-  * OMAP on-chip MMC/SD host emulation.
+ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
-  *
-+ * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
++/**
 + * kvm_arm_sve_get_vls:
 + * @cs: CPUState
 + * @map: bitmap to fill in
 + *
-  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
++ * Get all the SVE vector lengths supported by the KVM host, setting
-  *
++ * the bits corresponding to their length in quadwords minus one
-  * This program is free software; you can redistribute it and/or
++ * (vq - 1) in @map up to ARM_MAX_VQ.
-@@ -XXX,XX +XXX,XX @@ static void omap_mmc_update(void *opaque)
++ */
-     omap_mmc_interrupts_update(s);
++void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
 +
  /**
   * kvm_arm_set_cpu_features_from_host:
   * @cpu: ARMCPU to set the features for
@@ -XXX,XX +XXX,XX @@ static inline int kvm_arm_vgic_probe(void)
  static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
  static inline void kvm_arm_pmu_init(CPUState *cs) {}
 +static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
  #endif
  static inline const char *gic_class_name(void)
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
       * any of the above.  Finally, if SVE is not disabled, then at least one
       * vector length must be enabled.
       */
 +    DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
      DECLARE_BITMAP(tmp, ARM_MAX_VQ);
      uint32_t vq, max_vq = 0;
 +    /* Collect the set of vector lengths supported by KVM. */
 +    bitmap_zero(kvm_supported, ARM_MAX_VQ);
 +    if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
 +        kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
 +    } else if (kvm_enabled()) {
 +        assert(!cpu_isar_feature(aa64_sve, cpu));
 +    }
 +
      /*
       * Process explicit sve<N> properties.
       * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
              return;
          }
 -        /* Propagate enabled bits down through required powers-of-two. */
 -        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 -            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
 -                set_bit(vq - 1, cpu->sve_vq_map);
 +        if (kvm_enabled()) {
 +            /*
 +             * For KVM we have to automatically enable all supported unitialized
 +             * lengths, even when the smaller lengths are not all powers-of-two.
 +             */
 +            bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
 +            bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
 +        } else {
 +            /* Propagate enabled bits down through required powers-of-two. */
 +            for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 +                if (!test_bit(vq - 1, cpu->sve_vq_init)) {
 +                    set_bit(vq - 1, cpu->sve_vq_map);
 +                }
              }
          }
      } else if (cpu->sve_max_vq == 0) {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
              return;
          }
 -        /* Disabling a power-of-two disables all larger lengths. */
 -        if (test_bit(0, cpu->sve_vq_init)) {
 -            error_setg(errp, "cannot disable sve128");
 -            error_append_hint(errp, "Disabling sve128 results in all vector "
 -                              "lengths being disabled.\n");
 -            error_append_hint(errp, "With SVE enabled, at least one vector "
 -                              "length must be enabled.\n");
 -            return;
 -        }
 -        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
 -            if (test_bit(vq - 1, cpu->sve_vq_init)) {
 -                break;
 +        if (kvm_enabled()) {
 +            /* Disabling a supported length disables all larger lengths. */
 +            for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +                if (test_bit(vq - 1, cpu->sve_vq_init) &&
 +                    test_bit(vq - 1, kvm_supported)) {
 +                    break;
 +                }
              }
 +            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 +            bitmap_andnot(cpu->sve_vq_map, kvm_supported,
 +                          cpu->sve_vq_init, max_vq);
 +            if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
 +                error_setg(errp, "cannot disable sve%d", vq * 128);
 +                error_append_hint(errp, "Disabling sve%d results in all "
 +                                  "vector lengths being disabled.\n",
 +                                  vq * 128);
 +                error_append_hint(errp, "With SVE enabled, at least one "
 +                                  "vector length must be enabled.\n");
 +                return;
 +            }
 +        } else {
 +            /* Disabling a power-of-two disables all larger lengths. */
 +            if (test_bit(0, cpu->sve_vq_init)) {
 +                error_setg(errp, "cannot disable sve128");
 +                error_append_hint(errp, "Disabling sve128 results in all "
 +                                  "vector lengths being disabled.\n");
 +                error_append_hint(errp, "With SVE enabled, at least one "
 +                                  "vector length must be enabled.\n");
 +                return;
 +            }
 +            for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
 +                if (test_bit(vq - 1, cpu->sve_vq_init)) {
 +                    break;
 +                }
 +            }
 +            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 +            bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
          }
 -        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 -        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
          max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
      }
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
      assert(max_vq != 0);
      bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
 -    /* Ensure all required powers-of-two are enabled. */
 -    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 -        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
 -            error_setg(errp, "cannot disable sve%d", vq * 128);
 -            error_append_hint(errp, "sve%d is required as it "
 -                              "is a power-of-two length smaller than "
 -                              "the maximum, sve%d\n",
 -                              vq * 128, max_vq * 128);
 +    if (kvm_enabled()) {
 +        /* Ensure the set of lengths matches what KVM supports. */
 +        bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
 +        if (!bitmap_empty(tmp, max_vq)) {
 +            vq = find_last_bit(tmp, max_vq) + 1;
 +            if (test_bit(vq - 1, cpu->sve_vq_map)) {
 +                if (cpu->sve_max_vq) {
 +                    error_setg(errp, "cannot set sve-max-vq=%d",
 +                               cpu->sve_max_vq);
 +                    error_append_hint(errp, "This KVM host does not support "
 +                                      "the vector length %d-bits.\n",
 +                                      vq * 128);
 +                    error_append_hint(errp, "It may not be possible to use "
 +                                      "sve-max-vq with this KVM host. Try "
 +                                      "using only sve<N> properties.\n");
 +                } else {
 +                    error_setg(errp, "cannot enable sve%d", vq * 128);
 +                    error_append_hint(errp, "This KVM host does not support "
 +                                      "the vector length %d-bits.\n",
 +                                      vq * 128);
 +                }
 +            } else {
 +                error_setg(errp, "cannot disable sve%d", vq * 128);
 +                error_append_hint(errp, "The KVM host requires all "
 +                                  "supported vector lengths smaller "
 +                                  "than %d bits to also be enabled.\n",
 +                                  max_vq * 128);
 +            }
              return;
          }
 +    } else {
 +        /* Ensure all required powers-of-two are enabled. */
 +        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
 +            if (!test_bit(vq - 1, cpu->sve_vq_map)) {
 +                error_setg(errp, "cannot disable sve%d", vq * 128);
 +                error_append_hint(errp, "sve%d is required as it "
 +                                  "is a power-of-two length smaller than "
 +                                  "the maximum, sve%d\n",
 +                                  vq * 128, max_vq * 128);
 +                return;
 +            }
 +        }
      }
      /*
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
  {
      ARMCPU *cpu = ARM_CPU(obj);
      Error *err = NULL;
 +    uint32_t max_vq;
 -    visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
 -
 -    if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
 -        error_setg(&err, "unsupported SVE vector length");
 -        error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
 -                          ARM_MAX_VQ);
 +    visit_type_uint32(v, name, &max_vq, &err);
 +    if (err) {
 +        error_propagate(errp, err);
 +        return;
      }
 -    error_propagate(errp, err);
 +
 +    if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
 +        error_setg(errp, "cannot set sve-max-vq");
 +        error_append_hint(errp, "SVE not supported by KVM on this host\n");
 +        return;
 +    }
 +
 +    if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
 +        error_setg(errp, "unsupported SVE vector length");
 +        error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
 +                          ARM_MAX_VQ);
 +        return;
 +    }
 +
 +    cpu->sve_max_vq = max_vq;
  }
-+static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
+ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
          return;
      }
 +    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
 +        error_setg(errp, "cannot enable %s", name);
 +        error_append_hint(errp, "SVE not supported by KVM on this host\n");
 +        return;
 +    }
 +
      if (value) {
          set_bit(vq - 1, cpu->sve_vq_map);
      } else {
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
          cpu->dcz_blocksize = 7; /*  512 bytes */
  #endif
 -
 -        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
 -                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 -
 -        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 -            char name[8];
 -            sprintf(name, "sve%d", vq * 128);
 -            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 -                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 -        }
      }
      object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                          cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +    object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
 +                        cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 +
 +    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +        char name[8];
 +        sprintf(name, "sve%d", vq * 128);
 +        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 +                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 +    }
  }
  struct ARMCPUInfo {
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(CPUState *cpu)
      return kvm_check_extension(s, KVM_CAP_ARM_SVE);
  }
 +QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
 +
 +void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
 +{
-+    host->status = 0;
++    /* Only call this function if kvm_arm_sve_supported() returns true. */
-+    host->fifo_len = 0;
++    static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
 +    static bool probed;
 +    uint32_t vq = 0;
 +    int i, j;
 +
 +    bitmap_clear(map, 0, ARM_MAX_VQ);
 +
 +    /*
 +     * KVM ensures all host CPUs support the same set of vector lengths.
 +     * So we only need to create the scratch VCPUs once and then cache
 +     * the results.
 +     */
 +    if (!probed) {
 +        struct kvm_vcpu_init init = {
 +            .target = -1,
 +            .features[0] = (1 << KVM_ARM_VCPU_SVE),
 +        };
 +        struct kvm_one_reg reg = {
 +            .id = KVM_REG_ARM64_SVE_VLS,
 +            .addr = (uint64_t)&vls[0],
 +        };
 +        int fdarray[3], ret;
 +
 +        probed = true;
 +
 +        if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
 +            error_report("failed to create scratch VCPU with SVE enabled");
 +            abort();
 +        }
 +        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &reg);
 +        kvm_arm_destroy_scratch_host_vcpu(fdarray);
 +        if (ret) {
 +            error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
 +                         strerror(errno));
 +            abort();
 +        }
 +
 +        for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {
 +            if (vls[i]) {
 +                vq = 64 - clz64(vls[i]) + i * 64;
 +                break;
 +            }
 +        }
 +        if (vq > ARM_MAX_VQ) {
 +            warn_report("KVM supports vector lengths larger than "
 +                        "QEMU can enable");
 +        }
 +    }
 +
 +    for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) {
 +        if (!vls[i]) {
 +            continue;
 +        }
 +        for (j = 1; j <= 64; ++j) {
 +            vq = j + i * 64;
 +            if (vq > ARM_MAX_VQ) {
 +                return;
 +            }
 +            if (vls[i] & (1UL << (j - 1))) {
 +                set_bit(vq - 1, map);
 +            }
 +        }
 +    }
 +}
 +
- void omap_mmc_reset(struct omap_mmc_s *host)
++static int kvm_arm_sve_set_vls(CPUState *cs)
 +{
 +    uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0};
 +    struct kvm_one_reg reg = {
 +        .id = KVM_REG_ARM64_SVE_VLS,
 +        .addr = (uint64_t)&vls[0],
 +    };
 +    ARMCPU *cpu = ARM_CPU(cs);
 +    uint32_t vq;
 +    int i, j;
 +
 +    assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
 +
 +    for (vq = 1; vq <= cpu->sve_max_vq; ++vq) {
 +        if (test_bit(vq - 1, cpu->sve_vq_map)) {
 +            i = (vq - 1) / 64;
 +            j = (vq - 1) % 64;
 +            vls[i] |= 1UL << j;
 +        }
 +    }
 +
 +    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
 +}
 +
  #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
  int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
          !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
 -        fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 +        error_report("KVM is not supported for this guest CPU type");
          return -EINVAL;
      }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      }
      if (cpu_isar_feature(aa64_sve, cpu)) {
 +        ret = kvm_arm_sve_set_vls(cs);
 +        if (ret) {
 +            return ret;
 +        }
          ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
          if (ret) {
              return ret;
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/arm-cpu-features.c
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static QDict *resp_get_props(QDict *resp)
      return qdict;
  }
 +static bool resp_get_feature(QDict *resp, const char *feature)
 +{
 +    QDict *props;
 +
 +    g_assert(resp);
 +    g_assert(resp_has_props(resp));
 +    props = resp_get_props(resp);
 +    g_assert(qdict_get(props, feature));
 +    return qdict_get_bool(props, feature);
 +}
 +
  #define assert_has_feature(qts, cpu_type, feature)                     \
  ({                                                                     \
      QDict *_resp = do_query_no_props(qts, cpu_type);                   \
@@ -XXX,XX +XXX,XX @@ static void sve_tests_sve_off(const void *data)
      qtest_quit(qts);
  }
 +static void sve_tests_sve_off_kvm(const void *data)
 +{
 +    QTestState *qts;
 +
 +    qts = qtest_init(MACHINE_KVM "-cpu max,sve=off");
 +
 +    /*
 +     * We don't know if this host supports SVE so we don't
 +     * attempt to test enabling anything. We only test that
 +     * everything is disabled (as it should be with sve=off)
 +     * and that using sve<N>=off to explicitly disable vector
 +     * lengths is OK too.
 +     */
 +    assert_sve_vls(qts, "max", 0, NULL);
 +    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
 +
 +    qtest_quit(qts);
 +}
 +
  static void test_query_cpu_model_expansion(const void *data)
  {
-     host->last_cmd = 0;
+     QTestState *qts;
-@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
+@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
-     host->dw = 0;
+     }
-     host->mode = 0;
-     host->enable = 0;
+     if (g_str_equal(qtest_get_arch(), "aarch64")) {
--    host->status = 0;
++        bool kvm_supports_sve;
-     host->mask = 0;
++        char max_name[8], name[8];
-     host->cto = 0;
++        uint32_t max_vq, vq;
-     host->dto = 0;
++        uint64_t vls;
--    host->fifo_len = 0;
++        QDict *resp;
-     host->blen = 0;
++        char *error;
-     host->blen_counter = 0;
++
-     host->nblk = 0;
+         assert_has_feature(qts, "host", "aarch64");
-@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
+         assert_has_feature(qts, "host", "pmu");
-     qemu_set_irq(host->coverswitch, host->cdet_state);
-     host->clkdiv = 0;
+-        assert_has_feature(qts, "max", "sve");
+-
-+    omap_mmc_pseudo_reset(host);
+         assert_error(qts, "cortex-a15",
-+
+             "We cannot guarantee the CPU type 'cortex-a15' works "
-     /* Since we're still using the legacy SD API the card is not plugged
+             "with KVM on this host", NULL);
-      * into any bus, and we must reset it manually. When omap_mmc is
++
-      * QOMified this must move into the QOM reset function.
++        assert_has_feature(qts, "max", "sve");
-@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
++        resp = do_query_no_props(qts, "max");
-         if (s->dw != 0 && s->lines < 4)
++        kvm_supports_sve = resp_get_feature(resp, "sve");
-             printf("4-bit SD bus enabled\n");
++        vls = resp_get_sve_vls(resp);
-         if (!s->enable)
++        qobject_unref(resp);
--            omap_mmc_reset(s);
++
-+            omap_mmc_pseudo_reset(s);
++        if (kvm_supports_sve) {
-         break;
++            g_assert(vls != 0);
++            max_vq = 64 - __builtin_clzll(vls);
-     case 0x10:    /* MMC_STAT */
++            sprintf(max_name, "sve%d", max_vq * 128);
 +
 +            /* Enabling a supported length is of course fine. */
 +            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
 +
 +            /* Get the next supported length smaller than max-vq. */
 +            vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
 +            if (vq) {
 +                /*
 +                 * We have at least one length smaller than max-vq,
 +                 * so we can disable max-vq.
 +                 */
 +                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
 +                               "{ %s: false }", max_name);
 +
 +                /*
 +                 * Smaller, supported vector lengths cannot be disabled
 +                 * unless all larger, supported vector lengths are also
 +                 * disabled.
 +                 */
 +                sprintf(name, "sve%d", vq * 128);
 +                error = g_strdup_printf("cannot disable %s", name);
 +                assert_error(qts, "max", error,
 +                             "{ %s: true, %s: false }",
 +                             max_name, name);
 +                g_free(error);
 +            }
 +
 +            /*
 +             * The smallest, supported vector length is required, because
 +             * we need at least one vector length enabled.
 +             */
 +            vq = __builtin_ffsll(vls);
 +            sprintf(name, "sve%d", vq * 128);
 +            error = g_strdup_printf("cannot disable %s", name);
 +            assert_error(qts, "max", error, "{ %s: false }", name);
 +            g_free(error);
 +
 +            /* Get an unsupported length. */
 +            for (vq = 1; vq <= max_vq; ++vq) {
 +                if (!(vls & BIT_ULL(vq - 1))) {
 +                    break;
 +                }
 +            }
 +            if (vq <= SVE_MAX_VQ) {
 +                sprintf(name, "sve%d", vq * 128);
 +                error = g_strdup_printf("cannot enable %s", name);
 +                assert_error(qts, "max", error, "{ %s: true }", name);
 +                g_free(error);
 +            }
 +        } else {
 +            g_assert(vls == 0);
 +        }
      } else {
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
                              NULL, sve_tests_sve_max_vq_8);
          qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
                              NULL, sve_tests_sve_off);
 +        qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
 +                            NULL, sve_tests_sve_off_kvm);
      }
      return g_test_run();
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/arm-cpu-features.rst
 +++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Dependencies and Constraints
 ) At least one vector length must be enabled when `sve` is enabled.
 -  2) If a vector length `N` is enabled, then all power-of-two vector
 -     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
 -     is enabled, then the 128-bit and 256-bit vector lengths must also
 -     be enabled.
 +  2) If a vector length `N` is enabled, then, when KVM is enabled, all
 +     smaller, host supported vector lengths must also be enabled.  If
 +     KVM is not enabled, then only all the smaller, power-of-two vector
 +     lengths must be enabled.  E.g. with KVM if the host supports all
 +     vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512`
 +     is enabled, the 128-bit vector length, 256-bit vector length, and
 +     384-bit vector length must also be enabled. Without KVM, the 384-bit
 +     vector length would not be required.
 +
 +  3) If KVM is enabled then only vector lengths that the host CPU type
 +     support may be enabled.  If SVE is not supported by the host, then
 +     no `sve*` properties may be enabled.
  SVE CPU Property Parsing Semantics
  ----------------------------------
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
       an error is generated.
 ) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
 -     provided, then all supported vector lengths are enabled, including
 -     the non-power-of-two lengths.
 +     provided, then all supported vector lengths are enabled, which when
 +     KVM is not in use means including the non-power-of-two lengths, and,
 +     when KVM is in use, it means all vector lengths supported by the host
 +     processor.
 ) If SVE is enabled, then an error is generated when attempting to
       disable the last enabled vector length (see constraint (1) of "SVE
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
       has been explicitly disabled, then an error is generated (see
       constraint (2) of "SVE CPU Property Dependencies and Constraints").
 -  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
 +  5) When KVM is enabled, if the host does not support SVE, then an error
 +     is generated when attempting to enable any `sve*` properties (see
 +     constraint (3) of "SVE CPU Property Dependencies and Constraints").
 +
 +  6) When KVM is enabled, if the host does support SVE, then an error is
 +     generated when attempting to enable any vector lengths not supported
 +     by the host (see constraint (3) of "SVE CPU Property Dependencies and
 +     Constraints").
 +
 +  7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
       CPU properties are set `on`, then the specified vector lengths are
       disabled but the default for any unspecified lengths remains enabled.
 -     Disabling a power-of-two vector length also disables all vector
 -     lengths larger than the power-of-two length (see constraint (2) of
 -     "SVE CPU Property Dependencies and Constraints").
 +     When KVM is not enabled, disabling a power-of-two vector length also
 +     disables all vector lengths larger than the power-of-two length.
 +     When KVM is enabled, then disabling any supported vector length also
 +     disables all larger vector lengths (see constraint (2) of "SVE CPU
 +     Property Dependencies and Constraints").
 -  6) If one or more `sve<N>` CPU properties are set to `on`, then they
 +  8) If one or more `sve<N>` CPU properties are set to `on`, then they
       are enabled and all unspecified lengths default to disabled, except
       for the required lengths per constraint (2) of "SVE CPU Property
       Dependencies and Constraints", which will even be auto-enabled if
       they were not explicitly enabled.
 -  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
 +  9) If SVE was disabled (`sve=off`), allowing all vector lengths to be
       explicitly disabled (i.e. avoiding the error specified in (3) of
       "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
       provided an error will be generated.  To avoid this error, one must
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 06/11] target/arm: Suppress Coverity warning for PRF
+[PULL 09/11] target/arm/kvm: host cpu: Add support for sve<N> properties
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-These instructions must perform the sve_access_check, but
+Allow cpu 'host' to enable SVE when it's available, unless the
-since they are implemented as NOPs there is no generated
+user chooses to disable it with the added 'sve=off' cpu property.
-code to elide when the access check fails.
+Also give the user the ability to select vector lengths with the
+sve<N> properties. We don't adopt 'max' cpu's other sve property,
-Fixes: Coverity issues 1393780 & 1393779.
+sve-max-vq, because that property is difficult to use with KVM.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+That property assumes all vector lengths in the range from 1 up
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+to and including the specified maximum length are supported, but
 there may be optional lengths not supported by the host in that
 range. With KVM one must be more specific when enabling vector
 lengths.
 Signed-off-by: Andrew Jones <drjones@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
 Message-id: 20191031142734.8590-10-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-sve.c | 4 ++--
+ target/arm/cpu.h          |  2 ++
-file changed, 2 insertions(+), 2 deletions(-)
+ target/arm/cpu.c          |  3 +++
+ target/arm/cpu64.c        | 33 +++++++++++++++++----------------
-diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
+ target/arm/kvm64.c        | 14 +++++++++++++-
-index XXXXXXX..XXXXXXX 100644
+ tests/arm-cpu-features.c  | 17 ++++++++---------
---- a/target/arm/translate-sve.c
+ docs/arm-cpu-features.rst | 19 ++++++++++++-------
-+++ b/target/arm/translate-sve.c
+files changed, 55 insertions(+), 33 deletions(-)
-@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
- static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
  void aarch64_sve_change_el(CPUARMState *env, int old_el,
                             int new_el, bool el0_a64);
 +void aarch64_add_sve_properties(Object *obj);
  #else
  static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
  static inline void aarch64_sve_change_el(CPUARMState *env, int o,
                                           int n, bool a)
  { }
 +static inline void aarch64_add_sve_properties(Object *obj) { }
  #endif
  #if !defined(CONFIG_TCG)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
      ARMCPU *cpu = ARM_CPU(obj);
      kvm_arm_set_cpu_features_from_host(cpu);
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        aarch64_add_sve_properties(obj);
 +    }
      arm_cpu_post_init(obj);
  }
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
      cpu->isar.id_aa64pfr0 = t;
  }
 +void aarch64_add_sve_properties(Object *obj)
 +{
 +    uint32_t vq;
 +
 +    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 +                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +
 +    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 +        char name[8];
 +        sprintf(name, "sve%d", vq * 128);
 +        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 +                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 +    }
 +}
 +
  /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
   * otherwise, a CPU with as many features enabled as our emulation supports.
   * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
  static void aarch64_max_initfn(Object *obj)
  {
-     /* Prefetch is a nop within QEMU.  */
+     ARMCPU *cpu = ARM_CPU(obj);
--    sve_access_check(s);
+-    uint32_t vq;
-+    (void)sve_access_check(s);
+-    uint64_t t;
-     return true;
      if (kvm_enabled()) {
          kvm_arm_set_cpu_features_from_host(cpu);
 -        if (kvm_arm_sve_supported(CPU(cpu))) {
 -            t = cpu->isar.id_aa64pfr0;
 -            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 -            cpu->isar.id_aa64pfr0 = t;
 -        }
      } else {
 +        uint64_t t;
          uint32_t u;
          aarch64_a57_initfn(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
  #endif
      }
 -    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
 -                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
 +    aarch64_add_sve_properties(obj);
      object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                          cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
 -
 -    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
 -        char name[8];
 -        sprintf(name, "sve%d", vq * 128);
 -        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
 -                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
 -    }
  }
-@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
+ struct ARMCPUInfo {
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
       * and then query that CPU for the relevant ID registers.
       */
      int fdarray[3];
 +    bool sve_supported;
      uint64_t features = 0;
 +    uint64_t t;
      int err;
      /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                                ARM64_SYS_REG(3, 0, 0, 3, 2));
      }
 +    sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
 +
      kvm_arm_destroy_scratch_host_vcpu(fdarray);
      if (err < 0) {
          return false;
      }
-     /* Prefetch is a nop within QEMU.  */
--    sve_access_check(s);
+-   /* We can assume any KVM supporting CPU is at least a v8
-+    (void)sve_access_check(s);
++    /* Add feature bits that can't appear until after VCPU init. */
-     return true;
++    if (sve_supported) {
- }
++        t = ahcf->isar.id_aa64pfr0;
 +        t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
 +        ahcf->isar.id_aa64pfr0 = t;
 +    }
 +
 +    /*
 +     * We can assume any KVM supporting CPU is at least a v8
       * with VFPv4+Neon; this in turn implies most of the other
       * feature bits.
       */
 diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/arm-cpu-features.c
 +++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              "We cannot guarantee the CPU type 'cortex-a15' works "
              "with KVM on this host", NULL);
 -        assert_has_feature(qts, "max", "sve");
 -        resp = do_query_no_props(qts, "max");
 +        assert_has_feature(qts, "host", "sve");
 +        resp = do_query_no_props(qts, "host");
          kvm_supports_sve = resp_get_feature(resp, "sve");
          vls = resp_get_sve_vls(resp);
          qobject_unref(resp);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              sprintf(max_name, "sve%d", max_vq * 128);
              /* Enabling a supported length is of course fine. */
 -            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
 +            assert_sve_vls(qts, "host", vls, "{ %s: true }", max_name);
              /* Get the next supported length smaller than max-vq. */
              vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                   * We have at least one length smaller than max-vq,
                   * so we can disable max-vq.
                   */
 -                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
 +                assert_sve_vls(qts, "host", (vls & ~BIT_ULL(max_vq - 1)),
                                 "{ %s: false }", max_name);
                  /*
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                   */
                  sprintf(name, "sve%d", vq * 128);
                  error = g_strdup_printf("cannot disable %s", name);
 -                assert_error(qts, "max", error,
 +                assert_error(qts, "host", error,
                               "{ %s: true, %s: false }",
                               max_name, name);
                  g_free(error);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              vq = __builtin_ffsll(vls);
              sprintf(name, "sve%d", vq * 128);
              error = g_strdup_printf("cannot disable %s", name);
 -            assert_error(qts, "max", error, "{ %s: false }", name);
 +            assert_error(qts, "host", error, "{ %s: false }", name);
              g_free(error);
              /* Get an unsupported length. */
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
              if (vq <= SVE_MAX_VQ) {
                  sprintf(name, "sve%d", vq * 128);
                  error = g_strdup_printf("cannot enable %s", name);
 -                assert_error(qts, "max", error, "{ %s: true }", name);
 +                assert_error(qts, "host", error, "{ %s: true }", name);
                  g_free(error);
              }
          } else {
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
      } else {
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
 -
 -        assert_has_not_feature(qts, "max", "sve");
 +        assert_has_not_feature(qts, "host", "sve");
      }
      qtest_quit(qts);
 diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
 --- a/docs/arm-cpu-features.rst
 +++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Examples
       $ qemu-system-aarch64 -M virt -cpu max
 -  3) Only enable the 128-bit vector length::
 +  3) When KVM is enabled, implicitly enable all host CPU supported vector
 +     lengths with the `host` CPU type::
 +
 +     $ qemu-system-aarch64 -M virt,accel=kvm -cpu host
 +
 +  4) Only enable the 128-bit vector length::
       $ qemu-system-aarch64 -M virt -cpu max,sve128=on
 -  4) Disable the 512-bit vector length and all larger vector lengths,
 +  5) Disable the 512-bit vector length and all larger vector lengths,
       since 512 is a power-of-two.  This results in all the smaller,
       uninitialized lengths (128, 256, and 384) defaulting to enabled::
       $ qemu-system-aarch64 -M virt -cpu max,sve512=off
 -  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
 +  6) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
       $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
 -  6) The same as (5), but since the 128-bit and 256-bit vector
 +  7) The same as (6), but since the 128-bit and 256-bit vector
       lengths are required for the 512-bit vector length to be enabled,
       then allow them to be auto-enabled::
       $ qemu-system-aarch64 -M virt -cpu max,sve512=on
 -  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
 +  8) Do the same as (7), but by first disabling SVE and then re-enabling it::
       $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
 -  8) Force errors regarding the last vector length::
 +  9) Force errors regarding the last vector length::
       $ qemu-system-aarch64 -M virt -cpu max,sve128=off
       $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
@@ -XXX,XX +XXX,XX @@ The examples in "SVE CPU Property Examples" exhibit many ways to select
  vector lengths which developers may find useful in order to avoid overly
  verbose command lines.  However, the recommended way to select vector
  lengths is to explicitly enable each desired length.  Therefore only
 -example's (1), (3), and (5) exhibit recommended uses of the properties.
 +example's (1), (4), and (6) exhibit recommended uses of the properties.
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 07/11] tcg: Restrict check_size_impl to multiples of the line size
+[PULL 10/11] hw/arm/boot: Rebuild hflags when modifying CPUState at boot
-From: Richard Henderson <richard.henderson@linaro.org>
+From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Normally this is automatic in the size restrictions that are placed
+Rebuild hflags when modifying CPUState at boot.
 on vector sizes coming from the implementation.  However, for the
 legitimate size tuple [oprsz=8, maxsz=32], we need to clear the final
 bytes of the vector register.  Without this check, do_dup selects
 TCG_TYPE_V128 and clears only 16 bytes.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Fixes: e979972a6a
 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20180705191929.30773-2-richard.henderson@linaro.org
+Message-id: 20191031040830.18800-2-edgar.iglesias@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tcg/tcg-op-gvec.c | 7 +++++--
+ hw/arm/boot.c | 1 +
-file changed, 5 insertions(+), 2 deletions(-)
+file changed, 1 insertion(+)
-diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
+diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg-op-gvec.c
+--- a/hw/arm/boot.c
-+++ b/tcg/tcg-op-gvec.c
++++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
-    in units of LNSZ.  This limits the expansion of inline code.  */
+                 info->secondary_cpu_reset_hook(cpu, info);
- static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
+             }
- {
+         }
--    uint32_t lnct = oprsz / lnsz;
++        arm_rebuild_hflags(env);
--    return lnct >= 1 && lnct <= MAX_UNROLL;
+     }
 +    if (oprsz % lnsz == 0) {
 +        uint32_t lnct = oprsz / lnsz;
 +        return lnct >= 1 && lnct <= MAX_UNROLL;
 +    }
 +    return false;
  }
- static void expand_clr(uint32_t dofs, uint32_t maxsz);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 01/11] hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
+[PULL 11/11] target/arm: Allow reading flags from FPSCR for M-profile
-From: Eric Auger <eric.auger@redhat.com>
+From: Christophe Lyon <christophe.lyon@linaro.org>
-smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding
+rt==15 is a special case when reading the flags: it means the
-to a given sid. The function extracts both the PCIe bus number and
+destination is APSR. This patch avoids rejecting
-the devfn to return this data. Current computation of devfn is wrong
+vmrs apsr_nzcv, fpscr
-as it only returns the PCIe function instead of slot | function.
+as illegal instruction.
-Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data")
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
-Signed-off-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20191025095711.10853-1-christophe.lyon@linaro.org
-Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com
+[PMM: updated the comment]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/smmu-common.h | 1 +
+ target/arm/translate-vfp.inc.c | 5 +++--
- hw/arm/smmu-common.c         | 2 +-
+file changed, 3 insertions(+), 2 deletions(-)
 files changed, 2 insertions(+), 1 deletion(-)
-diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/smmu-common.h
+--- a/target/arm/translate-vfp.inc.c
-+++ b/include/hw/arm/smmu-common.h
++++ b/target/arm/translate-vfp.inc.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
+     if (arm_dc_feature(s, ARM_FEATURE_M)) {
- #define SMMU_PCI_BUS_MAX      256
+         /*
- #define SMMU_PCI_DEVFN_MAX    256
+          * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
-+#define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
+-         * Writes to R15 are UNPREDICTABLE; we choose to undef.
++         * Accesses to R15 are UNPREDICTABLE; we choose to undef.
- #define SMMU_MAX_VA_BITS      48
++         * (FPSCR -> r15 is a special case which writes to the PSR flags.)
+          */
-diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+-        if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
-index XXXXXXX..XXXXXXX 100644
++        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
---- a/hw/arm/smmu-common.c
+             return false;
-+++ b/hw/arm/smmu-common.c
+         }
-@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
+     }
      bus_n = PCI_BUS_NUM(sid);
      smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
      if (smmu_bus) {
 -        devfn = sid & 0x7;
 +        devfn = SMMU_PCI_DEVFN(sid);
          smmu = smmu_bus->pbdev[devfn];
          if (smmu) {
              return &smmu->iommu;
 --
-.17.1
+.20.1

Hi; this target-arm pull request has a collection of generally
fairly minor bugs to sneak in before 3.0 rc0 tomorrow...

thanks
-- PMM

The following changes since commit a98ff0ec2ba3538dd766b349518ee18d03942ed8:

Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180709' into staging (2018-07-09 11:00:45 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180709

for you to fetch changes up to 8fad0a65582c0a6e324580f45516461e9b6aa439:

hw/net/dp8393x: don't make prom region 'nomigrate' (2018-07-09 14:51:35 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/net/dp8393x: don't make prom region 'nomigrate'
 * boards.h: Remove doc comment reference to nonexistent function
 * hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
 * target/arm: Fix do_predset for large VL
 * tcg: Restrict check_size_impl to multiples of the line size
 * target/arm: Suppress Coverity warning for PRF
 * hw/timer/cmsdk-apb-timer: fix minor corner-case bugs and
   suppress spurious warnings when running Linux's timer driver
 * hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr

----------------------------------------------------------------
Eric Auger (1):
      hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr

Guenter Roeck (1):
      hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode

Peter Maydell (5):
      ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
      hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
      hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
      boards.h: Remove doc comment reference to nonexistent function
      hw/net/dp8393x: don't make prom region 'nomigrate'

Philippe Mathieu-Daudé (1):
      hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'

Richard Henderson (3):
      target/arm: Suppress Coverity warning for PRF
      tcg: Restrict check_size_impl to multiples of the line size
      target/arm: Fix do_predset for large VL

From: Eric Auger <eric.auger@redhat.com>

smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding
to a given sid. The function extracts both the PCIe bus number and
the devfn to return this data. Current computation of devfn is wrong
as it only returns the PCIe function instead of slot | function.

Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data")

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 1 +
 hw/arm/smmu-common.c         | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@
 
 #define SMMU_PCI_BUS_MAX      256
 #define SMMU_PCI_DEVFN_MAX    256
+#define SMMU_PCI_DEVFN(sid)   (sid & 0xFF)
 
 #define SMMU_MAX_VA_BITS      48
 
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
     bus_n = PCI_BUS_NUM(sid);
     smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
     if (smmu_bus) {
-        devfn = sid & 0x7;
+        devfn = SMMU_PCI_DEVFN(sid);
         smmu = smmu_bus->pbdev[devfn];
         if (smmu) {
             return &smmu->iommu;
-- 
2.17.1

The CMSDK timer behaviour is that an interrupt is triggered when the
counter counts down from 1 to 0; however one is not triggered if the
counter is manually set to 0 by a guest write to the counter register.
Currently ptimer can't handle this; add a policy option to allow
a ptimer user to request this behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20180703171044.9503-2-peter.maydell@linaro.org
---
 include/hw/ptimer.h |  9 +++++++++
 hw/core/ptimer.c    | 22 +++++++++++++++++++++-
 tests/ptimer-test.c | 25 +++++++++++++++++++------
 3 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -XXX,XX +XXX,XX @@
  * not the one less.  */
 #define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
 
+/*
+ * Starting to run with a zero counter, or setting the counter to "0" via
+ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer
+ * (though it will cause a reload). Only a counter decrement to "0"
+ * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
+ * ptimer_init() will assert() that you don't set both.
+ */
+#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
+
 /* ptimer.c */
 typedef struct ptimer_state ptimer_state;
 typedef void (*ptimer_cb)(void *opaque);
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/ptimer.c
+++ b/hw/core/ptimer.c
@@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
     uint32_t period_frac = s->period_frac;
     uint64_t period = s->period;
     uint64_t delta = s->delta;
+    bool suppress_trigger = false;
 
-    if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
+    /*
+     * Note that if delta_adjust is 0 then we must be here because of
+     * a count register write or timer start, not because of timer expiry.
+     * In that case the policy might require us to suppress the timer trigger
+     * that we would otherwise generate for a zero delta.
+     */
+    if (delta_adjust == 0 &&
+        (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
+        suppress_trigger = true;
+    }
+    if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
+        && !suppress_trigger) {
         ptimer_trigger(s);
     }
 
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
     s->bh = bh;
     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
     s->policy_mask = policy_mask;
+
+    /*
+     * These two policies are incompatible -- trigger-on-decrement implies
+     * a timer trigger when the count becomes 0, but no-immediate-trigger
+     * implies a trigger when the count stops being 0.
+     */
+    assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
+             (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
     return s;
 }
 
diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/ptimer-test.c
+++ b/tests/ptimer-test.c
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
     bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
     bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
     bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
 
     triggered = false;
 
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
     g_assert_cmpuint(ptimer_get_count(ptimer), ==,
                      no_immediate_reload ? 0 : 10);
 
-    if (no_immediate_trigger) {
+    if (no_immediate_trigger || trig_only_on_dec) {
         g_assert_false(triggered);
     } else {
         g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
     bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
     bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
     bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
+    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
 
     triggered = false;
 
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
     g_assert_cmpuint(ptimer_get_count(ptimer), ==,
                      no_immediate_reload ? 0 : 99);
 
-    if (no_immediate_trigger) {
+    if (no_immediate_trigger || trig_only_on_dec) {
         g_assert_false(triggered);
     } else {
         g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
     g_assert_cmpuint(ptimer_get_count(ptimer), ==,
                      no_immediate_reload ? 0 : 99);
 
-    if (no_immediate_trigger) {
+    if (no_immediate_trigger || trig_only_on_dec) {
         g_assert_false(triggered);
     } else {
         g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
     ptimer_state *ptimer = ptimer_init(bh, *policy);
     bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER);
     bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
+    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
 
     triggered = false;
 
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
 
     g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
 
-    if (no_immediate_trigger) {
+    if (no_immediate_trigger || trig_only_on_dec) {
         g_assert_false(triggered);
     } else {
         g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
     QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL);
     ptimer_state *ptimer = ptimer_init(bh, *policy);
     bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
+    bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
 
     triggered = false;
 
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
 
     g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
 
-    if (no_immediate_trigger) {
+    if (no_immediate_trigger || trig_only_on_dec) {
         g_assert_false(triggered);
     } else {
         g_assert_true(triggered);
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
         g_strlcat(policy_name, "no_counter_rounddown,", 256);
     }
 
+    if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) {
+        g_strlcat(policy_name, "trigger_only_on_decrement,", 256);
+    }
+
     g_test_add_data_func_full(
         tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name),
         g_memdup(&policy, 1), check_set_count, g_free);
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
 
 static void add_all_ptimer_policies_comb_tests(void)
 {
-    int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN;
+    int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
     int policy = PTIMER_POLICY_DEFAULT;
 
     for (; policy < (last_policy << 1); policy++) {
+        if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
+            (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
+            /* Incompatible policy flag settings -- don't try to test them */
+            continue;
+        }
         add_ptimer_tests(policy);
     }
 }
-- 
2.17.1

The CMSDK timer interrupt triggers when the counter goes from 1 to 0,
so we want to trigger immediately, rather than waiting for a
clock cycle. Drop the incorrect NO_IMMEDIATE_TRIGGER setting.
We also do not want to get an interrupt if the guest sets the
counter directly to zero, so use the new TRIGGER_ONLY_ON_DECREMENT
policy.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20180703171044.9503-3-peter.maydell@linaro.org
---
 hw/timer/cmsdk-apb-timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
     bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
     s->timer = ptimer_init(bh,
                            PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
-                           PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
+                           PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
                            PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
                            PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 
-- 
2.17.1

From: Guenter Roeck <linux@roeck-us.net>

The CMSDK APB timer is currently always configured as periodic timer.
This results in the following messages when trying to boot Linux.

Timer with delta zero, disabling

If the timer limit set with the RELOAD command is 0, the timer
needs to be enabled as one-shot timer.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/timer/cmsdk-apb-timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

If the CMSDK APB timer is set up with a zero RELOAD value
then it will count down to zero, fire once and then stay
at zero. From the point of view of the ptimer system, the
timer is disabled; but the enable bit in the CTRL register
is still set and if the guest subsequently writes to the
RELOAD or VALUE registers this should cause the timer to
start counting down again.

Add code to the write paths for RELOAD and VALUE so that
we correctly restart the timer in this situation.

Conversely, if the new RELOAD and VALUE are both zero,
we should stop the ptimer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20180703171044.9503-5-peter.maydell@linaro.org
---
 hw/timer/cmsdk-apb-timer.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
         break;
     case A_RELOAD:
         /* Writing to reload also sets the current timer value */
+        if (!value) {
+            ptimer_stop(s->timer);
+        }
         ptimer_set_limit(s->timer, value, 1);
+        if (value && (s->ctrl & R_CTRL_EN_MASK)) {
+            /*
+             * Make sure timer is running (it might have stopped if this
+             * was an expired one-shot timer)
+             */
+            ptimer_run(s->timer, 0);
+        }
         break;
     case A_VALUE:
+        if (!value && !ptimer_get_limit(s->timer)) {
+            ptimer_stop(s->timer);
+        }
         ptimer_set_count(s->timer, value);
+        if (value && (s->ctrl & R_CTRL_EN_MASK)) {
+            ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
+        }
         break;
     case A_INTSTATUS:
         /* Just one bit, which is W1C. */
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

These instructions must perform the sve_access_check, but
since they are implemented as NOPs there is no generated
code to elide when the access check fails.

Fixes: Coverity issues 1393780 & 1393779.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-sve.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
 static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
 {
     /* Prefetch is a nop within QEMU.  */
-    sve_access_check(s);
+    (void)sve_access_check(s);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
         return false;
     }
     /* Prefetch is a nop within QEMU.  */
-    sve_access_check(s);
+    (void)sve_access_check(s);
     return true;
 }
 
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Normally this is automatic in the size restrictions that are placed
on vector sizes coming from the implementation.  However, for the
legitimate size tuple [oprsz=8, maxsz=32], we need to clear the final
24 bytes of the vector register.  Without this check, do_dup selects
TCG_TYPE_V128 and clears only 16 bytes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180705191929.30773-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tcg/tcg-op-gvec.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
    in units of LNSZ.  This limits the expansion of inline code.  */
 static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
 {
-    uint32_t lnct = oprsz / lnsz;
-    return lnct >= 1 && lnct <= MAX_UNROLL;
+    if (oprsz % lnsz == 0) {
+        uint32_t lnct = oprsz / lnsz;
+        return lnct >= 1 && lnct <= MAX_UNROLL;
+    }
+    return false;
 }
 
 static void expand_clr(uint32_t dofs, uint32_t maxsz);
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Use MAKE_64BIT_MASK instead of open-coding.  Remove an odd
vector size check that is unlikely to be more profitable
than 3 64-bit integer stores.  Correct the iteration for WORD
to avoid writing too much data.

Fixes RISU tests of PTRUE for VL 256.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180705191929.30773-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-sve.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
         setsz = numelem << esz;
         lastword = word = pred_esz_masks[esz];
         if (setsz % 64) {
-            lastword &= ~(-1ull << (setsz % 64));
+            lastword &= MAKE_64BIT_MASK(0, setsz % 64);
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
             tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
             goto done;
         }
-        if (oprsz * 8 == setsz + 8) {
-            tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
-            tcg_gen_movi_i64(t, 0);
-            tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
-            goto done;
-        }
     }
 
     setsz /= 8;
     fullsz /= 8;
 
     tcg_gen_movi_i64(t, word);
-    for (i = 0; i < setsz; i += 8) {
+    for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
         tcg_gen_st_i64(t, cpu_env, ofs + i);
     }
     if (lastword != word) {
-- 
2.17.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

DeviceClass::reset models a "cold power-on" reset which can
also be used to powercycle a device; but there is no "hot reset"
(a.k.a. soft-reset) method available.

The OMAP MMC Power-Up Control bit is not designed to powercycle
a card, but to disable it without powering it off (pseudo-reset):

Multimedia Card (MMC/SD/SDIO) Interface [SPRU765A]

MMC_CON[11] Power-Up Control (POW)
  This bit must be set to 1 before any valid transaction to either
  MMC/SD or SPI memory cards.
  When 1, the card is considered powered-up and the controller core
  is enabled.
  When 0, the card is considered powered-down (system dependent),
  and the controller core logic is in pseudo-reset state. This is,
  the MMC_STAT flags and the FIFO pointers are reset, any access to
  MMC_DATA[DATA] has no effect, a write into the MMC.CMD register
  is ignored, and a setting of MMC_SPI[STR] to 1 is ignored.

By splitting the 'pseudo-reset' code out of the 'power-on' reset
function, this patch fixes a latent bug in omap_mmc_write(MMC_CON)i
recently exposed by ecd219f7abb.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180706162155.8432-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/sd/omap_mmc.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/omap_mmc.c
+++ b/hw/sd/omap_mmc.c
@@ -XXX,XX +XXX,XX @@
 /*
  * OMAP on-chip MMC/SD host emulation.
  *
+ * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
+ *
  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
  *
  * This program is free software; you can redistribute it and/or
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_update(void *opaque)
     omap_mmc_interrupts_update(s);
 }
 
+static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
+{
+    host->status = 0;
+    host->fifo_len = 0;
+}
+
 void omap_mmc_reset(struct omap_mmc_s *host)
 {
     host->last_cmd = 0;
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
     host->dw = 0;
     host->mode = 0;
     host->enable = 0;
-    host->status = 0;
     host->mask = 0;
     host->cto = 0;
     host->dto = 0;
-    host->fifo_len = 0;
     host->blen = 0;
     host->blen_counter = 0;
     host->nblk = 0;
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
     qemu_set_irq(host->coverswitch, host->cdet_state);
     host->clkdiv = 0;
 
+    omap_mmc_pseudo_reset(host);
+
     /* Since we're still using the legacy SD API the card is not plugged
      * into any bus, and we must reset it manually. When omap_mmc is
      * QOMified this must move into the QOM reset function.
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
         if (s->dw != 0 && s->lines < 4)
             printf("4-bit SD bus enabled\n");
         if (!s->enable)
-            omap_mmc_reset(s);
+            omap_mmc_pseudo_reset(s);
         break;
 
     case 0x10:	/* MMC_STAT */
-- 
2.17.1

commit b08199c6fbea1 accidentally added a reference to a doc
comment to a nonexistent memory_region_allocate_aux_memory().
This was a leftover from a previous version of the patchset
which defined memory_region_allocate_aux_memory() for
"allocate RAM MemoryRegion and register it for migration"
and left "memory_region_init_ram()" with its original semantics
of "allocate RAM MR but do not register for migration". In
the end we decided on the approach of "memory_region_init_ram()
registers the MR for migration, and memory_region_init_ram_nomigrate()
is a new function which does not", but this comment change
got left in by mistake. Revert that part of the commit.

Reported-by: Thomas Huth <huth@tuxfamily.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180702130605.13611-1-peter.maydell@linaro.org
---
 include/hw/boards.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/hw/boards.h b/include/hw/boards.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -XXX,XX +XXX,XX @@
  *
  * Smaller pieces of memory (display RAM, static RAMs, etc) don't need
  * to be backed via the -mem-path memory backend and can simply
- * be created via memory_region_allocate_aux_memory() or
- * memory_region_init_ram().
+ * be created via memory_region_init_ram().
  */
 void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
                                           const char *name,
-- 
2.17.1

Currently we use memory_region_init_rom_nomigrate() to create
the "dp3893x-prom" memory region, and we don't manually register
it with vmstate_register_ram(). This currently means that its
contents are migrated but as a ram block whose name is the empty
string; in future it may mean they are not migrated at all. Use
memory_region_init_ram() instead.

Note that this is a a cross-version migration compatibility break
for the MIPS "magnum" and "pica61" machines.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.markovic@wavecomp.com>
Message-id: 20180706174309.27110-1-peter.maydell@linaro.org
---
 hw/net/dp8393x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/dp8393x.c
+++ b/hw/net/dp8393x.c
@@ -XXX,XX +XXX,XX @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
     s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
     s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
 
-    memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev),
+    memory_region_init_ram(&s->prom, OBJECT(dev),
                            "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
     if (local_err) {
         error_propagate(errp, local_err);
-- 
2.17.1

target-arm queue: two bug fixes, plus the KVM/SVE patchset,
which is a new feature but one which was in my pre-softfreeze
pullreq (it just had to be dropped due to an unexpected test failure.)

thanks
-- PMM

The following changes since commit b7c9a7f353c0e260519bf735ff0d4aa01e72784b:

Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging (2019-10-31 15:57:30 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191101-1

for you to fetch changes up to d9ae7624b659362cb2bb2b04fee53bf50829ca56:

target/arm: Allow reading flags from FPSCR for M-profile (2019-11-01 08:49:10 +0000)

----------------------------------------------------------------
target-arm queue:
 * Support SVE in KVM guests
 * Don't UNDEF on M-profile 'vmrs apsr_nzcv, fpscr'
 * Update hflags after boot.c modifies CPU state

----------------------------------------------------------------
Andrew Jones (9):
      target/arm/monitor: Introduce qmp_query_cpu_model_expansion
      tests: arm: Introduce cpu feature tests
      target/arm: Allow SVE to be disabled via a CPU property
      target/arm/cpu64: max cpu: Introduce sve<N> properties
      target/arm/kvm64: Add kvm_arch_get/put_sve
      target/arm/kvm64: max cpu: Enable SVE when available
      target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features
      target/arm/cpu64: max cpu: Support sve properties with KVM
      target/arm/kvm: host cpu: Add support for sve<N> properties

Christophe Lyon (1):
      target/arm: Allow reading flags from FPSCR for M-profile

Edgar E. Iglesias (1):
      hw/arm/boot: Rebuild hflags when modifying CPUState at boot

From: Andrew Jones <drjones@redhat.com>

Add support for the query-cpu-model-expansion QMP command to Arm. We
do this selectively, only exposing CPU properties which represent
optional CPU features which the user may want to enable/disable.
Additionally we restrict the list of queryable cpu models to 'max',
'host', or the current type when KVM is in use. And, finally, we only
implement expansion type 'full', as Arm does not yet have a "base"
CPU type. More details and example queries are described in a new
document (docs/arm-cpu-features.rst).

Note, certainly more features may be added to the list of advertised
features, e.g. 'vfp' and 'neon'. The only requirement is that we can
detect invalid configurations and emit failures at QMP query time.
For 'vfp' and 'neon' this will require some refactoring to share a
validation function between the QMP query and the CPU realize
functions.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 qapi/machine-target.json  |   6 +-
 target/arm/monitor.c      | 146 ++++++++++++++++++++++++++++++++++++++
 docs/arm-cpu-features.rst | 137 +++++++++++++++++++++++++++++++++++
 3 files changed, 286 insertions(+), 3 deletions(-)
 create mode 100644 docs/arm-cpu-features.rst

diff --git a/qapi/machine-target.json b/qapi/machine-target.json
index XXXXXXX..XXXXXXX 100644
--- a/qapi/machine-target.json
+++ b/qapi/machine-target.json
@@ -XXX,XX +XXX,XX @@
 ##
 { 'struct': 'CpuModelExpansionInfo',
   'data': { 'model': 'CpuModelInfo' },
-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
+  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
 
 ##
 # @query-cpu-model-expansion:
@@ -XXX,XX +XXX,XX @@
 #   query-cpu-model-expansion while using these is not advised.
 #
 # Some architectures may not support all expansion types. s390x supports
-# "full" and "static".
+# "full" and "static". Arm only supports "full".
 #
 # Returns: a CpuModelExpansionInfo. Returns an error if expanding CPU models is
 #          not supported, if the model cannot be expanded, if the model contains
@@ -XXX,XX +XXX,XX @@
   'data': { 'type': 'CpuModelExpansionType',
             'model': 'CpuModelInfo' },
   'returns': 'CpuModelExpansionInfo',
-  'if': 'defined(TARGET_S390X) || defined(TARGET_I386)' }
+  'if': 'defined(TARGET_S390X) || defined(TARGET_I386) || defined(TARGET_ARM)' }
 
 ##
 # @CpuDefinitionInfo:
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "hw/boards.h"
 #include "kvm_arm.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "qapi/qobject-input-visitor.h"
+#include "qapi/qapi-commands-machine-target.h"
 #include "qapi/qapi-commands-misc-target.h"
+#include "qapi/qmp/qerror.h"
+#include "qapi/qmp/qdict.h"
+#include "qom/qom-qobject.h"
 
 static GICCapability *gic_cap_new(int version)
 {
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
 
     return head;
 }
+
+/*
+ * These are cpu model features we want to advertise. The order here
+ * matters as this is the order in which qmp_query_cpu_model_expansion
+ * will attempt to set them. If there are dependencies between features,
+ * then the order that considers those dependencies must be used.
+ */
+static const char *cpu_model_advertised_features[] = {
+    "aarch64", "pmu",
+    NULL
+};
+
+CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
+                                                     CpuModelInfo *model,
+                                                     Error **errp)
+{
+    CpuModelExpansionInfo *expansion_info;
+    const QDict *qdict_in = NULL;
+    QDict *qdict_out;
+    ObjectClass *oc;
+    Object *obj;
+    const char *name;
+    int i;
+
+    if (type != CPU_MODEL_EXPANSION_TYPE_FULL) {
+        error_setg(errp, "The requested expansion type is not supported");
+        return NULL;
+    }
+
+    if (!kvm_enabled() && !strcmp(model->name, "host")) {
+        error_setg(errp, "The CPU type '%s' requires KVM", model->name);
+        return NULL;
+    }
+
+    oc = cpu_class_by_name(TYPE_ARM_CPU, model->name);
+    if (!oc) {
+        error_setg(errp, "The CPU type '%s' is not a recognized ARM CPU type",
+                   model->name);
+        return NULL;
+    }
+
+    if (kvm_enabled()) {
+        const char *cpu_type = current_machine->cpu_type;
+        int len = strlen(cpu_type) - strlen(ARM_CPU_TYPE_SUFFIX);
+        bool supported = false;
+
+        if (!strcmp(model->name, "host") || !strcmp(model->name, "max")) {
+            /* These are kvmarm's recommended cpu types */
+            supported = true;
+        } else if (strlen(model->name) == len &&
+                   !strncmp(model->name, cpu_type, len)) {
+            /* KVM is enabled and we're using this type, so it works. */
+            supported = true;
+        }
+        if (!supported) {
+            error_setg(errp, "We cannot guarantee the CPU type '%s' works "
+                             "with KVM on this host", model->name);
+            return NULL;
+        }
+    }
+
+    if (model->props) {
+        qdict_in = qobject_to(QDict, model->props);
+        if (!qdict_in) {
+            error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict");
+            return NULL;
+        }
+    }
+
+    obj = object_new(object_class_get_name(oc));
+
+    if (qdict_in) {
+        Visitor *visitor;
+        Error *err = NULL;
+
+        visitor = qobject_input_visitor_new(model->props);
+        visit_start_struct(visitor, NULL, NULL, 0, &err);
+        if (err) {
+            visit_free(visitor);
+            object_unref(obj);
+            error_propagate(errp, err);
+            return NULL;
+        }
+
+        i = 0;
+        while ((name = cpu_model_advertised_features[i++]) != NULL) {
+            if (qdict_get(qdict_in, name)) {
+                object_property_set(obj, visitor, name, &err);
+                if (err) {
+                    break;
+                }
+            }
+        }
+
+        if (!err) {
+            visit_check_struct(visitor, &err);
+        }
+        visit_end_struct(visitor, NULL);
+        visit_free(visitor);
+        if (err) {
+            object_unref(obj);
+            error_propagate(errp, err);
+            return NULL;
+        }
+    }
+
+    expansion_info = g_new0(CpuModelExpansionInfo, 1);
+    expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
+    expansion_info->model->name = g_strdup(model->name);
+
+    qdict_out = qdict_new();
+
+    i = 0;
+    while ((name = cpu_model_advertised_features[i++]) != NULL) {
+        ObjectProperty *prop = object_property_find(obj, name, NULL);
+        if (prop) {
+            Error *err = NULL;
+            QObject *value;
+
+            assert(prop->get);
+            value = object_property_get_qobject(obj, name, &err);
+            assert(!err);
+
+            qdict_put_obj(qdict_out, name, value);
+        }
+    }
+
+    if (!qdict_size(qdict_out)) {
+        qobject_unref(qdict_out);
+    } else {
+        expansion_info->model->props = QOBJECT(qdict_out);
+        expansion_info->model->has_props = true;
+    }
+
+    object_unref(obj);
+
+    return expansion_info;
+}
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@
+================
+ARM CPU Features
+================
+
+Examples of probing and using ARM CPU features
+
+Introduction
+============
+
+CPU features are optional features that a CPU of supporting type may
+choose to implement or not.  In QEMU, optional CPU features have
+corresponding boolean CPU proprieties that, when enabled, indicate
+that the feature is implemented, and, conversely, when disabled,
+indicate that it is not implemented. An example of an ARM CPU feature
+is the Performance Monitoring Unit (PMU).  CPU types such as the
+Cortex-A15 and the Cortex-A57, which respectively implement ARM
+architecture reference manuals ARMv7-A and ARMv8-A, may both optionally
+implement PMUs.  For example, if a user wants to use a Cortex-A15 without
+a PMU, then the `-cpu` parameter should contain `pmu=off` on the QEMU
+command line, i.e. `-cpu cortex-a15,pmu=off`.
+
+As not all CPU types support all optional CPU features, then whether or
+not a CPU property exists depends on the CPU type.  For example, CPUs
+that implement the ARMv8-A architecture reference manual may optionally
+support the AArch32 CPU feature, which may be enabled by disabling the
+`aarch64` CPU property.  A CPU type such as the Cortex-A15, which does
+not implement ARMv8-A, will not have the `aarch64` CPU property.
+
+QEMU's support may be limited for some CPU features, only partially
+supporting the feature or only supporting the feature under certain
+configurations.  For example, the `aarch64` CPU feature, which, when
+disabled, enables the optional AArch32 CPU feature, is only supported
+when using the KVM accelerator and when running on a host CPU type that
+supports the feature.
+
+CPU Feature Probing
+===================
+
+Determining which CPU features are available and functional for a given
+CPU type is possible with the `query-cpu-model-expansion` QMP command.
+Below are some examples where `scripts/qmp/qmp-shell` (see the top comment
+block in the script for usage) is used to issue the QMP commands.
+
+(1) Determine which CPU features are available for the `max` CPU type
+    (Note, we started QEMU with qemu-system-aarch64, so `max` is
+     implementing the ARMv8-A reference manual in this case)::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
+      { "return": {
+        "model": { "name": "max", "props": {
+        "pmu": true, "aarch64": true
+      }}}}
+
+We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
+We also see that the CPU features are enabled, as they are all `true`.
+
+(2) Let's try to disable the PMU::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
+      { "return": {
+        "model": { "name": "max", "props": {
+        "pmu": false, "aarch64": true
+      }}}}
+
+We see it worked, as `pmu` is now `false`.
+
+(3) Let's try to disable `aarch64`, which enables the AArch32 CPU feature::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"aarch64":false}}
+      {"error": {
+       "class": "GenericError", "desc":
+       "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
+      }}
+
+It looks like this feature is limited to a configuration we do not
+currently have.
+
+(4) Let's try probing CPU features for the Cortex-A15 CPU type::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
+      {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
+
+Only the `pmu` CPU feature is available.
+
+A note about CPU feature dependencies
+-------------------------------------
+
+It's possible for features to have dependencies on other features. I.e.
+it may be possible to change one feature at a time without error, but
+when attempting to change all features at once an error could occur
+depending on the order they are processed.  It's also possible changing
+all at once doesn't generate an error, because a feature's dependencies
+are satisfied with other features, but the same feature cannot be changed
+independently without error.  For these reasons callers should always
+attempt to make their desired changes all at once in order to ensure the
+collection is valid.
+
+A note about CPU models and KVM
+-------------------------------
+
+Named CPU models generally do not work with KVM.  There are a few cases
+that do work, e.g. using the named CPU model `cortex-a57` with KVM on a
+seattle host, but mostly if KVM is enabled the `host` CPU type must be
+used.  This means the guest is provided all the same CPU features as the
+host CPU type has.  And, for this reason, the `host` CPU type should
+enable all CPU features that the host has by default.  Indeed it's even
+a bit strange to allow disabling CPU features that the host has when using
+the `host` CPU type, but in the absence of CPU models it's the best we can
+do if we want to launch guests without all the host's CPU features enabled.
+
+Enabling KVM also affects the `query-cpu-model-expansion` QMP command.  The
+affect is not only limited to specific features, as pointed out in example
+(3) of "CPU Feature Probing", but also to which CPU types may be expanded.
+When KVM is enabled, only the `max`, `host`, and current CPU type may be
+expanded.  This restriction is necessary as it's not possible to know all
+CPU types that may work with KVM, but it does impose a small risk of users
+experiencing unexpected errors.  For example on a seattle, as mentioned
+above, the `cortex-a57` CPU type is also valid when KVM is enabled.
+Therefore a user could use the `host` CPU type for the current type, but
+then attempt to query `cortex-a57`, however that query will fail with our
+restrictions.  This shouldn't be an issue though as management layers and
+users have been preferring the `host` CPU type for use with KVM for quite
+some time.  Additionally, if the KVM-enabled QEMU instance running on a
+seattle host is using the `cortex-a57` CPU type, then querying `cortex-a57`
+will work.
+
+Using CPU Features
+==================
+
+After determining which CPU features are available and supported for a
+given CPU type, then they may be selectively enabled or disabled on the
+QEMU command line with that CPU type::
+
+  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
+
+The example above disables the PMU for the `max` CPU type.
+
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Now that Arm CPUs have advertised features lets add tests to ensure
we maintain their expected availability with and without KVM.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20191031142734.8590-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/Makefile.include   |   5 +-
 tests/arm-cpu-features.c | 253 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 257 insertions(+), 1 deletion(-)
 create mode 100644 tests/arm-cpu-features.c

diff --git a/tests/Makefile.include b/tests/Makefile.include
index XXXXXXX..XXXXXXX 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
 check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
 check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
 
+check-qtest-arm-y += tests/arm-cpu-features$(EXESUF)
 check-qtest-arm-y += tests/microbit-test$(EXESUF)
 check-qtest-arm-y += tests/m25p80-test$(EXESUF)
 check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
 check-qtest-arm-y += tests/hexloader-test$(EXESUF)
 check-qtest-arm-$(CONFIG_PFLASH_CFI02) += tests/pflash-cfi02-test$(EXESUF)
 
-check-qtest-aarch64-y = tests/numa-test$(EXESUF)
+check-qtest-aarch64-y += tests/arm-cpu-features$(EXESUF)
+check-qtest-aarch64-y += tests/numa-test$(EXESUF)
 check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
 check-qtest-aarch64-y += tests/migration-test$(EXESUF)
 # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make test unconditional
@@ -XXX,XX +XXX,XX @@ tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)
 tests/numa-test$(EXESUF): tests/numa-test.o
 tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o
 tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)
+tests/arm-cpu-features$(EXESUF): tests/arm-cpu-features.o
 
 tests/migration/stress$(EXESUF): tests/migration/stress.o
 	$(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Arm CPU feature test cases
+ *
+ * Copyright (c) 2019 Red Hat Inc.
+ * Authors:
+ *  Andrew Jones <drjones@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qjson.h"
+
+#define MACHINE     "-machine virt,gic-version=max,accel=tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
+#define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
+                    "  'arguments': { 'type': 'full', "
+#define QUERY_TAIL  "}}"
+
+static bool kvm_enabled(QTestState *qts)
+{
+    QDict *resp, *qdict;
+    bool enabled;
+
+    resp = qtest_qmp(qts, "{ 'execute': 'query-kvm' }");
+    g_assert(qdict_haskey(resp, "return"));
+    qdict = qdict_get_qdict(resp, "return");
+    g_assert(qdict_haskey(qdict, "enabled"));
+    enabled = qdict_get_bool(qdict, "enabled");
+    qobject_unref(resp);
+
+    return enabled;
+}
+
+static QDict *do_query_no_props(QTestState *qts, const char *cpu_type)
+{
+    return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }"
+                          QUERY_TAIL, cpu_type);
+}
+
+static QDict *do_query(QTestState *qts, const char *cpu_type,
+                       const char *fmt, ...)
+{
+    QDict *resp;
+
+    if (fmt) {
+        QDict *args;
+        va_list ap;
+
+        va_start(ap, fmt);
+        args = qdict_from_vjsonf_nofail(fmt, ap);
+        va_end(ap);
+
+        resp = qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s, "
+                                                    "'props': %p }"
+                              QUERY_TAIL, cpu_type, args);
+    } else {
+        resp = do_query_no_props(qts, cpu_type);
+    }
+
+    return resp;
+}
+
+static const char *resp_get_error(QDict *resp)
+{
+    QDict *qdict;
+
+    g_assert(resp);
+
+    qdict = qdict_get_qdict(resp, "error");
+    if (qdict) {
+        return qdict_get_str(qdict, "desc");
+    }
+
+    return NULL;
+}
+
+#define assert_error(qts, cpu_type, expected_error, fmt, ...)          \
+({                                                                     \
+    QDict *_resp;                                                      \
+    const char *_error;                                                \
+                                                                       \
+    _resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);               \
+    g_assert(_resp);                                                   \
+    _error = resp_get_error(_resp);                                    \
+    g_assert(_error);                                                  \
+    g_assert(g_str_equal(_error, expected_error));                     \
+    qobject_unref(_resp);                                              \
+})
+
+static bool resp_has_props(QDict *resp)
+{
+    QDict *qdict;
+
+    g_assert(resp);
+
+    if (!qdict_haskey(resp, "return")) {
+        return false;
+    }
+    qdict = qdict_get_qdict(resp, "return");
+
+    if (!qdict_haskey(qdict, "model")) {
+        return false;
+    }
+    qdict = qdict_get_qdict(qdict, "model");
+
+    return qdict_haskey(qdict, "props");
+}
+
+static QDict *resp_get_props(QDict *resp)
+{
+    QDict *qdict;
+
+    g_assert(resp);
+    g_assert(resp_has_props(resp));
+
+    qdict = qdict_get_qdict(resp, "return");
+    qdict = qdict_get_qdict(qdict, "model");
+    qdict = qdict_get_qdict(qdict, "props");
+
+    return qdict;
+}
+
+#define assert_has_feature(qts, cpu_type, feature)                     \
+({                                                                     \
+    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
+    g_assert(_resp);                                                   \
+    g_assert(resp_has_props(_resp));                                   \
+    g_assert(qdict_get(resp_get_props(_resp), feature));               \
+    qobject_unref(_resp);                                              \
+})
+
+#define assert_has_not_feature(qts, cpu_type, feature)                 \
+({                                                                     \
+    QDict *_resp = do_query_no_props(qts, cpu_type);                   \
+    g_assert(_resp);                                                   \
+    g_assert(!resp_has_props(_resp) ||                                 \
+             !qdict_get(resp_get_props(_resp), feature));              \
+    qobject_unref(_resp);                                              \
+})
+
+static void assert_type_full(QTestState *qts)
+{
+    const char *error;
+    QDict *resp;
+
+    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
+                            "'arguments': { 'type': 'static', "
+                                           "'model': { 'name': 'foo' }}}");
+    g_assert(resp);
+    error = resp_get_error(resp);
+    g_assert(error);
+    g_assert(g_str_equal(error,
+                         "The requested expansion type is not supported"));
+    qobject_unref(resp);
+}
+
+static void assert_bad_props(QTestState *qts, const char *cpu_type)
+{
+    const char *error;
+    QDict *resp;
+
+    resp = qtest_qmp(qts, "{ 'execute': 'query-cpu-model-expansion', "
+                            "'arguments': { 'type': 'full', "
+                                           "'model': { 'name': %s, "
+                                                      "'props': false }}}",
+                     cpu_type);
+    g_assert(resp);
+    error = resp_get_error(resp);
+    g_assert(error);
+    g_assert(g_str_equal(error,
+                         "Invalid parameter type for 'props', expected: dict"));
+    qobject_unref(resp);
+}
+
+static void test_query_cpu_model_expansion(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE "-cpu max");
+
+    /* Test common query-cpu-model-expansion input validation */
+    assert_type_full(qts);
+    assert_bad_props(qts, "max");
+    assert_error(qts, "foo", "The CPU type 'foo' is not a recognized "
+                 "ARM CPU type", NULL);
+    assert_error(qts, "max", "Parameter 'not-a-prop' is unexpected",
+                 "{ 'not-a-prop': false }");
+    assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL);
+
+    /* Test expected feature presence/absence for some cpu types */
+    assert_has_feature(qts, "max", "pmu");
+    assert_has_feature(qts, "cortex-a15", "pmu");
+    assert_has_not_feature(qts, "cortex-a15", "aarch64");
+
+    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        assert_has_feature(qts, "max", "aarch64");
+        assert_has_feature(qts, "cortex-a57", "pmu");
+        assert_has_feature(qts, "cortex-a57", "aarch64");
+
+        /* Test that features that depend on KVM generate errors without. */
+        assert_error(qts, "max",
+                     "'aarch64' feature cannot be disabled "
+                     "unless KVM is enabled and 32-bit EL1 "
+                     "is supported",
+                     "{ 'aarch64': false }");
+    }
+
+    qtest_quit(qts);
+}
+
+static void test_query_cpu_model_expansion_kvm(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE_KVM "-cpu max");
+
+    /*
+     * These tests target the 'host' CPU type, so KVM must be enabled.
+     */
+    if (!kvm_enabled(qts)) {
+        qtest_quit(qts);
+        return;
+    }
+
+    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        assert_has_feature(qts, "host", "aarch64");
+        assert_has_feature(qts, "host", "pmu");
+
+        assert_error(qts, "cortex-a15",
+            "We cannot guarantee the CPU type 'cortex-a15' works "
+            "with KVM on this host", NULL);
+    } else {
+        assert_has_not_feature(qts, "host", "aarch64");
+        assert_has_not_feature(qts, "host", "pmu");
+    }
+
+    qtest_quit(qts);
+}
+
+int main(int argc, char **argv)
+{
+    g_test_init(&argc, &argv, NULL);
+
+    qtest_add_data_func("/arm/query-cpu-model-expansion",
+                        NULL, test_query_cpu_model_expansion);
+    qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
+                        NULL, test_query_cpu_model_expansion_kvm);
+
+    return g_test_run();
+}
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Since 97a28b0eeac14 ("target/arm: Allow VFP and Neon to be disabled via
a CPU property") we can disable the 'max' cpu model's VFP and neon
features, but there's no way to disable SVE. Add the 'sve=on|off'
property to give it that flexibility. We also rename
cpu_max_get/set_sve_vq to cpu_max_get/set_sve_max_vq in order for them
to follow the typical *_get/set_<property-name> pattern.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c         |  3 ++-
 target/arm/cpu64.c       | 52 ++++++++++++++++++++++++++++++++++------
 target/arm/monitor.c     |  2 +-
 tests/arm-cpu-features.c |  1 +
 4 files changed, 49 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
         env->cp15.cptr_el[3] |= CPTR_EZ;
         /* with maximum vector length */
-        env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
+        env->vfp.zcr_el[1] = cpu_isar_feature(aa64_sve, cpu) ?
+                             cpu->sve_max_vq - 1 : 0;
         env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
         env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
         /*
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 }
 
-static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
-                               void *opaque, Error **errp)
+static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
+    uint32_t value;
+
+    /* All vector lengths are disabled when SVE is off. */
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        value = 0;
+    } else {
+        value = cpu->sve_max_vq;
+    }
+    visit_type_uint32(v, name, &value, errp);
 }
 
-static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
-                               void *opaque, Error **errp)
+static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
+                                   void *opaque, Error **errp)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
     error_propagate(errp, err);
 }
 
+static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    bool value = cpu_isar_feature(aa64_sve, cpu);
+
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
+                            void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    Error *err = NULL;
+    bool value;
+    uint64_t t;
+
+    visit_type_bool(v, name, &value, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    t = cpu->isar.id_aa64pfr0;
+    t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
+    cpu->isar.id_aa64pfr0 = t;
+}
+
 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
  * otherwise, a CPU with as many features enabled as our emulation supports.
  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 #endif
 
         cpu->sve_max_vq = ARM_MAX_VQ;
-        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
-                            cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
+        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
+        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
     }
 }
 
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
  * then the order that considers those dependencies must be used.
  */
 static const char *cpu_model_advertised_features[] = {
-    "aarch64", "pmu",
+    "aarch64", "pmu", "sve",
     NULL
 };
 
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         assert_has_feature(qts, "max", "aarch64");
+        assert_has_feature(qts, "max", "sve");
         assert_has_feature(qts, "cortex-a57", "pmu");
         assert_has_feature(qts, "cortex-a57", "aarch64");
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Introduce cpu properties to give fine control over SVE vector lengths.
We introduce a property for each valid length up to the current
maximum supported, which is 2048-bits. The properties are named, e.g.
sve128, sve256, sve384, sve512, ..., where the number is the number of
bits. See the updates to docs/arm-cpu-features.rst for a description
of the semantics and for example uses.

Note, as sve-max-vq is still present and we'd like to be able to
support qmp_query_cpu_model_expansion with guests launched with e.g.
-cpu max,sve-max-vq=8 on their command lines, then we do allow
sve-max-vq and sve<N> properties to be provided at the same time, but
this is not recommended, and is why sve-max-vq is not mentioned in the
document.  If sve-max-vq is provided then it enables all lengths smaller
than and including the max and disables all lengths larger. It also has
the side-effect that no larger lengths may be enabled and that the max
itself cannot be disabled. Smaller non-power-of-two lengths may,
however, be disabled, e.g. -cpu max,sve-max-vq=4,sve384=off provides a
guest the vector lengths 128, 256, and 512 bits.

This patch has been co-authored with Richard Henderson, who reworked
the target/arm/cpu64.c changes in order to push all the validation and
auto-enabling/disabling steps into the finalizer, resulting in a nice
LOC reduction.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/qemu/bitops.h     |   1 +
 target/arm/cpu.h          |  19 ++++
 target/arm/cpu.c          |  19 ++++
 target/arm/cpu64.c        | 192 ++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c       |  10 +-
 target/arm/monitor.c      |  12 +++
 tests/arm-cpu-features.c  | 194 ++++++++++++++++++++++++++++++++++++++
 docs/arm-cpu-features.rst | 168 +++++++++++++++++++++++++++++++--
 8 files changed, 606 insertions(+), 9 deletions(-)

diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index XXXXXXX..XXXXXXX 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -XXX,XX +XXX,XX @@
 #define BITS_PER_LONG           (sizeof (unsigned long) * BITS_PER_BYTE)
 
 #define BIT(nr)                 (1UL << (nr))
+#define BIT_ULL(nr)             (1ULL << (nr))
 #define BIT_MASK(nr)            (1UL << ((nr) % BITS_PER_LONG))
 #define BIT_WORD(nr)            ((nr) / BITS_PER_LONG)
 #define BITS_TO_LONGS(nr)       DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
 
 #ifdef TARGET_AARCH64
 # define ARM_MAX_VQ    16
+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
 #else
 # define ARM_MAX_VQ    1
+static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
+static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
+{ return 0; }
 #endif
 
 typedef struct ARMVectorReg {
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
 
     /* Used to set the maximum vector length the cpu will support.  */
     uint32_t sve_max_vq;
+
+    /*
+     * In sve_vq_map each set bit is a supported vector length of
+     * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
+     * length in quadwords.
+     *
+     * While processing properties during initialization, corresponding
+     * sve_vq_init bits are set for bits in sve_vq_map that have been
+     * set by properties.
+     */
+    DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
+    DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
 };
 
 void arm_cpu_post_init(Object *obj);
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
     return (env->features & (1ULL << feature)) != 0;
 }
 
+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
+
 #if !defined(CONFIG_USER_ONLY)
 /* Return true if exception levels below EL3 are in secure state,
  * or would be following an exception return to that level.
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_finalizefn(Object *obj)
 #endif
 }
 
+void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
+{
+    Error *local_err = NULL;
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        arm_cpu_sve_finalize(cpu, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
+    }
+}
+
 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 {
     CPUState *cs = CPU(dev);
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
+    arm_cpu_finalize_features(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
     if (arm_feature(env, ARM_FEATURE_AARCH64) &&
         cpu->has_vfp != cpu->has_neon) {
         /*
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
 }
 
+void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+{
+    /*
+     * If any vector lengths are explicitly enabled with sve<N> properties,
+     * then all other lengths are implicitly disabled.  If sve-max-vq is
+     * specified then it is the same as explicitly enabling all lengths
+     * up to and including the specified maximum, which means all larger
+     * lengths will be implicitly disabled.  If no sve<N> properties
+     * are enabled and sve-max-vq is not specified, then all lengths not
+     * explicitly disabled will be enabled.  Additionally, all power-of-two
+     * vector lengths less than the maximum enabled length will be
+     * automatically enabled and all vector lengths larger than the largest
+     * disabled power-of-two vector length will be automatically disabled.
+     * Errors are generated if the user provided input that interferes with
+     * any of the above.  Finally, if SVE is not disabled, then at least one
+     * vector length must be enabled.
+     */
+    DECLARE_BITMAP(tmp, ARM_MAX_VQ);
+    uint32_t vq, max_vq = 0;
+
+    /*
+     * Process explicit sve<N> properties.
+     * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
+     * Check first for any sve<N> enabled.
+     */
+    if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) {
+        max_vq = find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1;
+
+        if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
+            error_setg(errp, "cannot enable sve%d", max_vq * 128);
+            error_append_hint(errp, "sve%d is larger than the maximum vector "
+                              "length, sve-max-vq=%d (%d bits)\n",
+                              max_vq * 128, cpu->sve_max_vq,
+                              cpu->sve_max_vq * 128);
+            return;
+        }
+
+        /* Propagate enabled bits down through required powers-of-two. */
+        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
+                set_bit(vq - 1, cpu->sve_vq_map);
+            }
+        }
+    } else if (cpu->sve_max_vq == 0) {
+        /*
+         * No explicit bits enabled, and no implicit bits from sve-max-vq.
+         */
+        if (!cpu_isar_feature(aa64_sve, cpu)) {
+            /* SVE is disabled and so are all vector lengths.  Good. */
+            return;
+        }
+
+        /* Disabling a power-of-two disables all larger lengths. */
+        if (test_bit(0, cpu->sve_vq_init)) {
+            error_setg(errp, "cannot disable sve128");
+            error_append_hint(errp, "Disabling sve128 results in all vector "
+                              "lengths being disabled.\n");
+            error_append_hint(errp, "With SVE enabled, at least one vector "
+                              "length must be enabled.\n");
+            return;
+        }
+        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
+            if (test_bit(vq - 1, cpu->sve_vq_init)) {
+                break;
+            }
+        }
+        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
+
+        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
+        max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
+    }
+
+    /*
+     * Process the sve-max-vq property.
+     * Note that we know from the above that no bit above
+     * sve-max-vq is currently set.
+     */
+    if (cpu->sve_max_vq != 0) {
+        max_vq = cpu->sve_max_vq;
+
+        if (!test_bit(max_vq - 1, cpu->sve_vq_map) &&
+            test_bit(max_vq - 1, cpu->sve_vq_init)) {
+            error_setg(errp, "cannot disable sve%d", max_vq * 128);
+            error_append_hint(errp, "The maximum vector length must be "
+                              "enabled, sve-max-vq=%d (%d bits)\n",
+                              max_vq, max_vq * 128);
+            return;
+        }
+
+        /* Set all bits not explicitly set within sve-max-vq. */
+        bitmap_complement(tmp, cpu->sve_vq_init, max_vq);
+        bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
+    }
+
+    /*
+     * We should know what max-vq is now.  Also, as we're done
+     * manipulating sve-vq-map, we ensure any bits above max-vq
+     * are clear, just in case anybody looks.
+     */
+    assert(max_vq != 0);
+    bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
+
+    /* Ensure all required powers-of-two are enabled. */
+    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
+            error_setg(errp, "cannot disable sve%d", vq * 128);
+            error_append_hint(errp, "sve%d is required as it "
+                              "is a power-of-two length smaller than "
+                              "the maximum, sve%d\n",
+                              vq * 128, max_vq * 128);
+            return;
+        }
+    }
+
+    /*
+     * Now that we validated all our vector lengths, the only question
+     * left to answer is if we even want SVE at all.
+     */
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        error_setg(errp, "cannot enable sve%d", max_vq * 128);
+        error_append_hint(errp, "SVE must be enabled to enable vector "
+                          "lengths.\n");
+        error_append_hint(errp, "Add sve=on to the CPU property list.\n");
+        return;
+    }
+
+    /* From now on sve_max_vq is the actual maximum supported length. */
+    cpu->sve_max_vq = max_vq;
+}
+
+uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
+{
+    uint32_t bitnum;
+
+    /*
+     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
+     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
+     * function always returns the next smaller than the input.
+     */
+    assert(vq && vq <= ARM_MAX_VQ + 1);
+
+    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
+    return bitnum == vq - 1 ? 0 : bitnum + 1;
+}
+
 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
                                    void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
     error_propagate(errp, err);
 }
 
+static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t vq = atoi(&name[3]) / 128;
+    bool value;
+
+    /* All vector lengths are disabled when SVE is off. */
+    if (!cpu_isar_feature(aa64_sve, cpu)) {
+        value = false;
+    } else {
+        value = test_bit(vq - 1, cpu->sve_vq_map);
+    }
+    visit_type_bool(v, name, &value, errp);
+}
+
+static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t vq = atoi(&name[3]) / 128;
+    Error *err = NULL;
+    bool value;
+
+    visit_type_bool(v, name, &value, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
+    }
+
+    if (value) {
+        set_bit(vq - 1, cpu->sve_vq_map);
+    } else {
+        clear_bit(vq - 1, cpu->sve_vq_map);
+    }
+    set_bit(vq - 1, cpu->sve_vq_init);
+}
+
 static void cpu_arm_get_sve(Object *obj, Visitor *v, const char *name,
                             void *opaque, Error **errp)
 {
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
 static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
+    uint32_t vq;
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
 
-        cpu->sve_max_vq = ARM_MAX_VQ;
         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                             cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
         object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                             cpu_arm_set_sve, NULL, NULL, &error_fatal);
+
+        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+            char name[8];
+            sprintf(name, "sve%d", vq * 128);
+            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
+                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+        }
     }
 }
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
     return 0;
 }
 
+static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+{
+    uint32_t start_vq = (start_len & 0xf) + 1;
+
+    return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
+}
+
 /*
  * Given that SVE is enabled, return the vector length for EL.
  */
@@ -XXX,XX +XXX,XX @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el)
     if (arm_feature(env, ARM_FEATURE_EL3)) {
         zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
     }
-    return zcr_len;
+
+    return sve_zcr_get_valid_len(cpu, zcr_len);
 }
 
 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
     return head;
 }
 
+QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
+
 /*
  * These are cpu model features we want to advertise. The order here
  * matters as this is the order in which qmp_query_cpu_model_expansion
@@ -XXX,XX +XXX,XX @@ GICCapabilityList *qmp_query_gic_capabilities(Error **errp)
  */
 static const char *cpu_model_advertised_features[] = {
     "aarch64", "pmu", "sve",
+    "sve128", "sve256", "sve384", "sve512",
+    "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
+    "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
     NULL
 };
 
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
         if (!err) {
             visit_check_struct(visitor, &err);
         }
+        if (!err) {
+            arm_cpu_finalize_features(ARM_CPU(obj), &err);
+        }
         visit_end_struct(visitor, NULL);
         visit_free(visitor);
         if (err) {
@@ -XXX,XX +XXX,XX @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
             error_propagate(errp, err);
             return NULL;
         }
+    } else {
+        Error *err = NULL;
+        arm_cpu_finalize_features(ARM_CPU(obj), &err);
+        assert(err == NULL);
     }
 
     expansion_info = g_new0(CpuModelExpansionInfo, 1);
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@
  * See the COPYING file in the top-level directory.
  */
 #include "qemu/osdep.h"
+#include "qemu/bitops.h"
 #include "libqtest.h"
 #include "qapi/qmp/qdict.h"
 #include "qapi/qmp/qjson.h"
 
+/*
+ * We expect the SVE max-vq to be 16. Also it must be <= 64
+ * for our test code, otherwise 'vls' can't just be a uint64_t.
+ */
+#define SVE_MAX_VQ 16
+
 #define MACHINE     "-machine virt,gic-version=max,accel=tcg "
 #define MACHINE_KVM "-machine virt,gic-version=max,accel=kvm:tcg "
 #define QUERY_HEAD  "{ 'execute': 'query-cpu-model-expansion', " \
@@ -XXX,XX +XXX,XX @@ static void assert_bad_props(QTestState *qts, const char *cpu_type)
     qobject_unref(resp);
 }
 
+static uint64_t resp_get_sve_vls(QDict *resp)
+{
+    QDict *props;
+    const QDictEntry *e;
+    uint64_t vls = 0;
+    int n = 0;
+
+    g_assert(resp);
+    g_assert(resp_has_props(resp));
+
+    props = resp_get_props(resp);
+
+    for (e = qdict_first(props); e; e = qdict_next(props, e)) {
+        if (strlen(e->key) > 3 && !strncmp(e->key, "sve", 3) &&
+            g_ascii_isdigit(e->key[3])) {
+            char *endptr;
+            int bits;
+
+            bits = g_ascii_strtoll(&e->key[3], &endptr, 10);
+            if (!bits || *endptr != '\0') {
+                continue;
+            }
+
+            if (qdict_get_bool(props, e->key)) {
+                vls |= BIT_ULL((bits / 128) - 1);
+            }
+            ++n;
+        }
+    }
+
+    g_assert(n == SVE_MAX_VQ);
+
+    return vls;
+}
+
+#define assert_sve_vls(qts, cpu_type, expected_vls, fmt, ...)          \
+({                                                                     \
+    QDict *_resp = do_query(qts, cpu_type, fmt, ##__VA_ARGS__);        \
+    g_assert(_resp);                                                   \
+    g_assert(resp_has_props(_resp));                                   \
+    g_assert(resp_get_sve_vls(_resp) == expected_vls);                 \
+    qobject_unref(_resp);                                              \
+})
+
+static void sve_tests_default(QTestState *qts, const char *cpu_type)
+{
+    /*
+     * With no sve-max-vq or sve<N> properties on the command line
+     * the default is to have all vector lengths enabled. This also
+     * tests that 'sve' is 'on' by default.
+     */
+    assert_sve_vls(qts, cpu_type, BIT_ULL(SVE_MAX_VQ) - 1, NULL);
+
+    /* With SVE off, all vector lengths should also be off. */
+    assert_sve_vls(qts, cpu_type, 0, "{ 'sve': false }");
+
+    /* With SVE on, we must have at least one vector length enabled. */
+    assert_error(qts, cpu_type, "cannot disable sve128", "{ 'sve128': false }");
+
+    /* Basic enable/disable tests. */
+    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve384': true }");
+    assert_sve_vls(qts, cpu_type, ((BIT_ULL(SVE_MAX_VQ) - 1) & ~BIT_ULL(2)),
+                   "{ 'sve384': false }");
+
+    /*
+     * ---------------------------------------------------------------------
+     *               power-of-two(vq)   all-power-            can      can
+     *                                  of-two(< vq)        enable   disable
+     * ---------------------------------------------------------------------
+     * vq < max_vq      no                MUST*              yes      yes
+     * vq < max_vq      yes               MUST*              yes      no
+     * ---------------------------------------------------------------------
+     * vq == max_vq     n/a               MUST*              yes**    yes**
+     * ---------------------------------------------------------------------
+     * vq > max_vq      n/a               no                 no       yes
+     * vq > max_vq      n/a               yes                yes      yes
+     * ---------------------------------------------------------------------
+     *
+     * [*] "MUST" means this requirement must already be satisfied,
+     *     otherwise 'max_vq' couldn't itself be enabled.
+     *
+     * [**] Not testable with the QMP interface, only with the command line.
+     */
+
+    /* max_vq := 8 */
+    assert_sve_vls(qts, cpu_type, 0x8b, "{ 'sve1024': true }");
+
+    /* max_vq := 8, vq < max_vq, !power-of-two(vq) */
+    assert_sve_vls(qts, cpu_type, 0x8f,
+                   "{ 'sve1024': true, 'sve384': true }");
+    assert_sve_vls(qts, cpu_type, 0x8b,
+                   "{ 'sve1024': true, 'sve384': false }");
+
+    /* max_vq := 8, vq < max_vq, power-of-two(vq) */
+    assert_sve_vls(qts, cpu_type, 0x8b,
+                   "{ 'sve1024': true, 'sve256': true }");
+    assert_error(qts, cpu_type, "cannot disable sve256",
+                 "{ 'sve1024': true, 'sve256': false }");
+
+    /* max_vq := 3, vq > max_vq, !all-power-of-two(< vq) */
+    assert_error(qts, cpu_type, "cannot disable sve512",
+                 "{ 'sve384': true, 'sve512': false, 'sve640': true }");
+
+    /*
+     * We can disable power-of-two vector lengths when all larger lengths
+     * are also disabled. We only need to disable the power-of-two length,
+     * as all non-enabled larger lengths will then be auto-disabled.
+     */
+    assert_sve_vls(qts, cpu_type, 0x7, "{ 'sve512': false }");
+
+    /* max_vq := 3, vq > max_vq, all-power-of-two(< vq) */
+    assert_sve_vls(qts, cpu_type, 0x1f,
+                   "{ 'sve384': true, 'sve512': true, 'sve640': true }");
+    assert_sve_vls(qts, cpu_type, 0xf,
+                   "{ 'sve384': true, 'sve512': true, 'sve640': false }");
+}
+
+static void sve_tests_sve_max_vq_8(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE "-cpu max,sve-max-vq=8");
+
+    assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL);
+
+    /*
+     * Disabling the max-vq set by sve-max-vq is not allowed, but
+     * of course enabling it is OK.
+     */
+    assert_error(qts, "max", "cannot disable sve1024", "{ 'sve1024': false }");
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve1024': true }");
+
+    /*
+     * Enabling anything larger than max-vq set by sve-max-vq is not
+     * allowed, but of course disabling everything larger is OK.
+     */
+    assert_error(qts, "max", "cannot enable sve1152", "{ 'sve1152': true }");
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve1152': false }");
+
+    /*
+     * We can enable/disable non power-of-two lengths smaller than the
+     * max-vq set by sve-max-vq, but, while we can enable power-of-two
+     * lengths, we can't disable them.
+     */
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve384': true }");
+    assert_sve_vls(qts, "max", 0xfb, "{ 'sve384': false }");
+    assert_sve_vls(qts, "max", 0xff, "{ 'sve256': true }");
+    assert_error(qts, "max", "cannot disable sve256", "{ 'sve256': false }");
+
+    qtest_quit(qts);
+}
+
+static void sve_tests_sve_off(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE "-cpu max,sve=off");
+
+    /* SVE is off, so the map should be empty. */
+    assert_sve_vls(qts, "max", 0, NULL);
+
+    /* The map stays empty even if we turn lengths off. */
+    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
+
+    /* It's an error to enable lengths when SVE is off. */
+    assert_error(qts, "max", "cannot enable sve128", "{ 'sve128': true }");
+
+    /* With SVE re-enabled we should get all vector lengths enabled. */
+    assert_sve_vls(qts, "max", BIT_ULL(SVE_MAX_VQ) - 1, "{ 'sve': true }");
+
+    /* Or enable SVE with just specific vector lengths. */
+    assert_sve_vls(qts, "max", 0x3,
+                   "{ 'sve': true, 'sve128': true, 'sve256': true }");
+
+    qtest_quit(qts);
+}
+
 static void test_query_cpu_model_expansion(const void *data)
 {
     QTestState *qts;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         assert_has_feature(qts, "max", "aarch64");
         assert_has_feature(qts, "max", "sve");
+        assert_has_feature(qts, "max", "sve128");
         assert_has_feature(qts, "cortex-a57", "pmu");
         assert_has_feature(qts, "cortex-a57", "aarch64");
 
+        sve_tests_default(qts, "max");
+
         /* Test that features that depend on KVM generate errors without. */
         assert_error(qts, "max",
                      "'aarch64' feature cannot be disabled "
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
     qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
                         NULL, test_query_cpu_model_expansion_kvm);
 
+    if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
+                            NULL, sve_tests_sve_max_vq_8);
+        qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off);
+    }
+
     return g_test_run();
 }
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ block in the script for usage) is used to issue the QMP commands.
       (QEMU) query-cpu-model-expansion type=full model={"name":"max"}
       { "return": {
         "model": { "name": "max", "props": {
-        "pmu": true, "aarch64": true
+        "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
+        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
+        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
+        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
+        "sve896": true, "sve1280": true, "sve2048": true
       }}}}
 
-We see that the `max` CPU type has the `pmu` and `aarch64` CPU features.
-We also see that the CPU features are enabled, as they are all `true`.
+We see that the `max` CPU type has the `pmu`, `aarch64`, `sve`, and many
+`sve<N>` CPU features.  We also see that all the CPU features are
+enabled, as they are all `true`.  (The `sve<N>` CPU features are all
+optional SVE vector lengths (see "SVE CPU Properties").  While with TCG
+all SVE vector lengths can be supported, when KVM is in use it's more
+likely that only a few lengths will be supported, if SVE is supported at
+all.)
 
 (2) Let's try to disable the PMU::
 
       (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
       { "return": {
         "model": { "name": "max", "props": {
-        "pmu": false, "aarch64": true
+        "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
+        "sve128": true, "aarch64": true, "sve1024": true, "sve": true,
+        "sve640": true, "sve768": true, "sve1408": true, "sve256": true,
+        "sve1152": true, "sve512": true, "sve384": true, "sve1536": true,
+        "sve896": true, "sve1280": true, "sve2048": true
       }}}}
 
 We see it worked, as `pmu` is now `false`.
@@ -XXX,XX +XXX,XX @@ We see it worked, as `pmu` is now `false`.
 It looks like this feature is limited to a configuration we do not
 currently have.
 
-(4) Let's try probing CPU features for the Cortex-A15 CPU type::
+(4) Let's disable `sve` and see what happens to all the optional SVE
+    vector lengths::
+
+      (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"sve":false}}
+      { "return": {
+        "model": { "name": "max", "props": {
+        "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
+        "sve128": false, "aarch64": true, "sve1024": false, "sve": false,
+        "sve640": false, "sve768": false, "sve1408": false, "sve256": false,
+        "sve1152": false, "sve512": false, "sve384": false, "sve1536": false,
+        "sve896": false, "sve1280": false, "sve2048": false
+      }}}}
+
+As expected they are now all `false`.
+
+(5) Let's try probing CPU features for the Cortex-A15 CPU type::
 
       (QEMU) query-cpu-model-expansion type=full model={"name":"cortex-a15"}
       {"return": {"model": {"name": "cortex-a15", "props": {"pmu": true}}}}
@@ -XXX,XX +XXX,XX @@ After determining which CPU features are available and supported for a
 given CPU type, then they may be selectively enabled or disabled on the
 QEMU command line with that CPU type::
 
-  $ qemu-system-aarch64 -M virt -cpu max,pmu=off
+  $ qemu-system-aarch64 -M virt -cpu max,pmu=off,sve=on,sve128=on,sve256=on
 
-The example above disables the PMU for the `max` CPU type.
+The example above disables the PMU and enables the first two SVE vector
+lengths for the `max` CPU type.  Note, the `sve=on` isn't actually
+necessary, because, as we observed above with our probe of the `max` CPU
+type, `sve` is already on by default.  Also, based on our probe of
+defaults, it would seem we need to disable many SVE vector lengths, rather
+than only enabling the two we want.  This isn't the case, because, as
+disabling many SVE vector lengths would be quite verbose, the `sve<N>` CPU
+properties have special semantics (see "SVE CPU Property Parsing
+Semantics").
+
+SVE CPU Properties
+==================
+
+There are two types of SVE CPU properties: `sve` and `sve<N>`.  The first
+is used to enable or disable the entire SVE feature, just as the `pmu`
+CPU property completely enables or disables the PMU.  The second type
+is used to enable or disable specific vector lengths, where `N` is the
+number of bits of the length.  The `sve<N>` CPU properties have special
+dependencies and constraints, see "SVE CPU Property Dependencies and
+Constraints" below.  Additionally, as we want all supported vector lengths
+to be enabled by default, then, in order to avoid overly verbose command
+lines (command lines full of `sve<N>=off`, for all `N` not wanted), we
+provide the parsing semantics listed in "SVE CPU Property Parsing
+Semantics".
+
+SVE CPU Property Dependencies and Constraints
+---------------------------------------------
+
+  1) At least one vector length must be enabled when `sve` is enabled.
+
+  2) If a vector length `N` is enabled, then all power-of-two vector
+     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
+     is enabled, then the 128-bit and 256-bit vector lengths must also
+     be enabled.
+
+SVE CPU Property Parsing Semantics
+----------------------------------
+
+  1) If SVE is disabled (`sve=off`), then which SVE vector lengths
+     are enabled or disabled is irrelevant to the guest, as the entire
+     SVE feature is disabled and that disables all vector lengths for
+     the guest.  However QEMU will still track any `sve<N>` CPU
+     properties provided by the user.  If later an `sve=on` is provided,
+     then the guest will get only the enabled lengths.  If no `sve=on`
+     is provided and there are explicitly enabled vector lengths, then
+     an error is generated.
+
+  2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
+     provided, then all supported vector lengths are enabled, including
+     the non-power-of-two lengths.
+
+  3) If SVE is enabled, then an error is generated when attempting to
+     disable the last enabled vector length (see constraint (1) of "SVE
+     CPU Property Dependencies and Constraints").
+
+  4) If one or more vector lengths have been explicitly enabled and at
+     at least one of the dependency lengths of the maximum enabled length
+     has been explicitly disabled, then an error is generated (see
+     constraint (2) of "SVE CPU Property Dependencies and Constraints").
+
+  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
+     CPU properties are set `on`, then the specified vector lengths are
+     disabled but the default for any unspecified lengths remains enabled.
+     Disabling a power-of-two vector length also disables all vector
+     lengths larger than the power-of-two length (see constraint (2) of
+     "SVE CPU Property Dependencies and Constraints").
+
+  6) If one or more `sve<N>` CPU properties are set to `on`, then they
+     are enabled and all unspecified lengths default to disabled, except
+     for the required lengths per constraint (2) of "SVE CPU Property
+     Dependencies and Constraints", which will even be auto-enabled if
+     they were not explicitly enabled.
+
+  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
+     explicitly disabled (i.e. avoiding the error specified in (3) of
+     "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
+     provided an error will be generated.  To avoid this error, one must
+     enable at least one vector length prior to enabling SVE.
+
+SVE CPU Property Examples
+-------------------------
+
+  1) Disable SVE::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve=off
+
+  2) Implicitly enable all vector lengths for the `max` CPU type::
+
+     $ qemu-system-aarch64 -M virt -cpu max
+
+  3) Only enable the 128-bit vector length::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve128=on
+
+  4) Disable the 512-bit vector length and all larger vector lengths,
+     since 512 is a power-of-two.  This results in all the smaller,
+     uninitialized lengths (128, 256, and 384) defaulting to enabled::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve512=off
+
+  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
+
+  6) The same as (5), but since the 128-bit and 256-bit vector
+     lengths are required for the 512-bit vector length to be enabled,
+     then allow them to be auto-enabled::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve512=on
+
+  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
+
+  8) Force errors regarding the last vector length::
+
+     $ qemu-system-aarch64 -M virt -cpu max,sve128=off
+     $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
+
+SVE CPU Property Recommendations
+--------------------------------
+
+The examples in "SVE CPU Property Examples" exhibit many ways to select
+vector lengths which developers may find useful in order to avoid overly
+verbose command lines.  However, the recommended way to select vector
+lengths is to explicitly enable each desired length.  Therefore only
+example's (1), (3), and (5) exhibit recommended uses of the properties.
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

These are the SVE equivalents to kvm_arch_get/put_fpsimd. Note, the
swabbing is different than it is for fpsmid because the vector format
is a little-endian stream of words.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-6-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm64.c | 185 ++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 156 insertions(+), 29 deletions(-)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_destroy_vcpu(CPUState *cs)
 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 {
     /* Return true if the regidx is a register we should synchronize
-     * via the cpreg_tuples array (ie is not a core reg we sync by
-     * hand in kvm_arch_get/put_registers())
+     * via the cpreg_tuples array (ie is not a core or sve reg that
+     * we sync by hand in kvm_arch_get/put_registers())
      */
     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
     case KVM_REG_ARM_CORE:
+    case KVM_REG_ARM64_SVE:
         return false;
     default:
         return true;
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
 
 static int kvm_arch_put_fpsimd(CPUState *cs)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
+    CPUARMState *env = &ARM_CPU(cs)->env;
     struct kvm_one_reg reg;
-    uint32_t fpr;
     int i, ret;
 
     for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_put_fpsimd(CPUState *cs)
         }
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    fpr = vfp_get_fpsr(env);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
-    if (ret) {
-        return ret;
+    return 0;
+}
+
+/*
+ * SVE registers are encoded in KVM's memory in an endianness-invariant format.
+ * The byte at offset i from the start of the in-memory representation contains
+ * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
+ * lowest offsets are stored in the lowest memory addresses, then that nearly
+ * matches QEMU's representation, which is to use an array of host-endian
+ * uint64_t's, where the lower offsets are at the lower indices. To complete
+ * the translation we just need to byte swap the uint64_t's on big-endian hosts.
+ */
+static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
+{
+#ifdef HOST_WORDS_BIGENDIAN
+    int i;
+
+    for (i = 0; i < nr; ++i) {
+        dst[i] = bswap64(src[i]);
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    fpr = vfp_get_fpcr(env);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+    return dst;
+#else
+    return src;
+#endif
+}
+
+/*
+ * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
+ * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
+ * code the slice index to zero for now as it's unlikely we'll need more than
+ * one slice for quite some time.
+ */
+static int kvm_arch_put_sve(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    uint64_t tmp[ARM_MAX_VQ * 2];
+    uint64_t *r;
+    struct kvm_one_reg reg;
+    int n, ret;
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
+        r = sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * 2);
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
+        r = sve_bswap64(tmp, r = &env->vfp.pregs[n].p[0],
+                        DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+    }
+
+    r = sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0],
+                    DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
+    reg.addr = (uintptr_t)r;
+    reg.id = KVM_REG_ARM64_SVE_FFR(0);
     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
     if (ret) {
         return ret;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
 {
     struct kvm_one_reg reg;
     uint64_t val;
+    uint32_t fpr;
     int i, ret;
     unsigned int el;
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         }
     }
 
-    ret = kvm_arch_put_fpsimd(cs);
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arch_put_sve(cs);
+    } else {
+        ret = kvm_arch_put_fpsimd(cs);
+    }
+    if (ret) {
+        return ret;
+    }
+
+    reg.addr = (uintptr_t)(&fpr);
+    fpr = vfp_get_fpsr(env);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+    if (ret) {
+        return ret;
+    }
+
+    reg.addr = (uintptr_t)(&fpr);
+    fpr = vfp_get_fpcr(env);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+    ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
     if (ret) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
 
 static int kvm_arch_get_fpsimd(CPUState *cs)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
+    CPUARMState *env = &ARM_CPU(cs)->env;
     struct kvm_one_reg reg;
-    uint32_t fpr;
     int i, ret;
 
     for (i = 0; i < 32; i++) {
@@ -XXX,XX +XXX,XX @@ static int kvm_arch_get_fpsimd(CPUState *cs)
         }
     }
 
-    reg.addr = (uintptr_t)(&fpr);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
-    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
-    if (ret) {
-        return ret;
-    }
-    vfp_set_fpsr(env, fpr);
+    return 0;
+}
 
-    reg.addr = (uintptr_t)(&fpr);
-    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+/*
+ * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
+ * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
+ * code the slice index to zero for now as it's unlikely we'll need more than
+ * one slice for quite some time.
+ */
+static int kvm_arch_get_sve(CPUState *cs)
+{
+    ARMCPU *cpu = ARM_CPU(cs);
+    CPUARMState *env = &cpu->env;
+    struct kvm_one_reg reg;
+    uint64_t *r;
+    int n, ret;
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) {
+        r = &env->vfp.zregs[n].d[0];
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_ZREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+        sve_bswap64(r, r, cpu->sve_max_vq * 2);
+    }
+
+    for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) {
+        r = &env->vfp.pregs[n].p[0];
+        reg.addr = (uintptr_t)r;
+        reg.id = KVM_REG_ARM64_SVE_PREG(n, 0);
+        ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+        if (ret) {
+            return ret;
+        }
+        sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
+    }
+
+    r = &env->vfp.pregs[FFR_PRED_NUM].p[0];
+    reg.addr = (uintptr_t)r;
+    reg.id = KVM_REG_ARM64_SVE_FFR(0);
     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
     if (ret) {
         return ret;
     }
-    vfp_set_fpcr(env, fpr);
+    sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8));
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
     struct kvm_one_reg reg;
     uint64_t val;
     unsigned int el;
+    uint32_t fpr;
     int i, ret;
 
     ARMCPU *cpu = ARM_CPU(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
         env->spsr = env->banked_spsr[i];
     }
 
-    ret = kvm_arch_get_fpsimd(cs);
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arch_get_sve(cs);
+    } else {
+        ret = kvm_arch_get_fpsimd(cs);
+    }
     if (ret) {
         return ret;
     }
 
+    reg.addr = (uintptr_t)(&fpr);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret) {
+        return ret;
+    }
+    vfp_set_fpsr(env, fpr);
+
+    reg.addr = (uintptr_t)(&fpr);
+    reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
+    ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
+    if (ret) {
+        return ret;
+    }
+    vfp_set_fpcr(env, fpr);
+
     ret = kvm_get_vcpu_events(cpu);
     if (ret) {
         return ret;
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Enable SVE in the KVM guest when the 'max' cpu type is configured
and KVM supports it. KVM SVE requires use of the new finalize
vcpu ioctl, so we add that now too. For starters SVE can only be
turned on or off, getting all vector lengths the host CPU supports
when on. We'll add the other SVE CPU properties in later patches.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Reviewed-by: Beata Michalska <beata.michalska@linaro.org>
Message-id: 20191031142734.8590-7-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h     | 27 +++++++++++++++++++++++++++
 target/arm/cpu64.c       | 17 ++++++++++++++---
 target/arm/kvm.c         |  5 +++++
 target/arm/kvm64.c       | 20 +++++++++++++++++++-
 tests/arm-cpu-features.c |  4 ++++
 5 files changed, 69 insertions(+), 4 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@
  */
 int kvm_arm_vcpu_init(CPUState *cs);
 
+/**
+ * kvm_arm_vcpu_finalize
+ * @cs: CPUState
+ * @feature: int
+ *
+ * Finalizes the configuration of the specified VCPU feature by
+ * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring
+ * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of
+ * KVM's API documentation.
+ *
+ * Returns: 0 if success else < 0 error code
+ */
+int kvm_arm_vcpu_finalize(CPUState *cs, int feature);
+
 /**
  * kvm_arm_register_device:
  * @mr: memory region for this device
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cs);
  */
 bool kvm_arm_pmu_supported(CPUState *cs);
 
+/**
+ * bool kvm_arm_sve_supported:
+ * @cs: CPUState
+ *
+ * Returns true if the KVM VCPU can enable SVE and false otherwise.
+ */
+bool kvm_arm_sve_supported(CPUState *cs);
+
 /**
  * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
  * IPA address space supported by KVM
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_pmu_supported(CPUState *cs)
     return false;
 }
 
+static inline bool kvm_arm_sve_supported(CPUState *cs)
+{
+    return false;
+}
+
 static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
 {
     return -ENOENT;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
         return;
     }
 
+    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+        error_setg(errp, "'sve' feature not supported by KVM on this host");
+        return;
+    }
+
     t = cpu->isar.id_aa64pfr0;
     t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
     cpu->isar.id_aa64pfr0 = t;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
     uint32_t vq;
+    uint64_t t;
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
+        if (kvm_arm_sve_supported(CPU(cpu))) {
+            t = cpu->isar.id_aa64pfr0;
+            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+            cpu->isar.id_aa64pfr0 = t;
+        }
     } else {
-        uint64_t t;
         uint32_t u;
         aarch64_a57_initfn(obj);
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 
         object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                             cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-        object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
-                            cpu_arm_set_sve, NULL, NULL, &error_fatal);
 
         for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
             char name[8];
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
                                 cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
         }
     }
+
+    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
 }
 
 struct ARMCPUInfo {
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vcpu_init(CPUState *cs)
     return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
 }
 
+int kvm_arm_vcpu_finalize(CPUState *cs, int feature)
+{
+    return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature);
+}
+
 void kvm_arm_init_serror_injection(CPUState *cs)
 {
     cap_has_inject_serror_esr = kvm_check_extension(cs->kvm_state,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_aarch32_supported(CPUState *cpu)
     return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
 }
 
+bool kvm_arm_sve_supported(CPUState *cpu)
+{
+    KVMState *s = KVM_STATE(current_machine->accelerator);
+
+    return kvm_check_extension(s, KVM_CAP_ARM_SVE);
+}
+
 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
 
 int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
     }
     if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
-            cpu->has_pmu = false;
+        cpu->has_pmu = false;
     }
     if (cpu->has_pmu) {
         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
     } else {
         unset_feature(&env->features, ARM_FEATURE_PMU);
     }
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        assert(kvm_arm_sve_supported(cs));
+        cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE;
+    }
 
     /* Do KVM_ARM_VCPU_INIT ioctl */
     ret = kvm_arm_vcpu_init(cs);
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
         return ret;
     }
 
+    if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
+        if (ret) {
+            return ret;
+        }
+    }
+
     /*
      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
      * Currently KVM has its own idea about MPIDR assignment, so we
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         assert_has_feature(qts, "host", "aarch64");
         assert_has_feature(qts, "host", "pmu");
 
+        assert_has_feature(qts, "max", "sve");
+
         assert_error(qts, "cortex-a15",
             "We cannot guarantee the CPU type 'cortex-a15' works "
             "with KVM on this host", NULL);
     } else {
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
+
+        assert_has_not_feature(qts, "max", "sve");
     }
 
     qtest_quit(qts);
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

kvm_arm_create_scratch_host_vcpu() takes a struct kvm_vcpu_init
parameter. Rather than just using it as an output parameter to
pass back the preferred target, use it also as an input parameter,
allowing a caller to pass a selected target if they wish and to
also pass cpu features. If the caller doesn't want to select a
target they can pass -1 for the target which indicates they want
to use the preferred target and have it passed back like before.

diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
                                       int *fdarray,
                                       struct kvm_vcpu_init *init)
 {
-    int ret, kvmfd = -1, vmfd = -1, cpufd = -1;
+    int ret = 0, kvmfd = -1, vmfd = -1, cpufd = -1;
 
     kvmfd = qemu_open("/dev/kvm", O_RDWR);
     if (kvmfd < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
         goto finish;
     }
 
-    ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, init);
+    if (init->target == -1) {
+        struct kvm_vcpu_init preferred;
+
+        ret = ioctl(vmfd, KVM_ARM_PREFERRED_TARGET, &preferred);
+        if (!ret) {
+            init->target = preferred.target;
+        }
+    }
     if (ret >= 0) {
         ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
         if (ret < 0) {
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
          * creating one kind of guest CPU which is its preferred
          * CPU type.
          */
+        struct kvm_vcpu_init try;
+
         while (*cpus_to_try != QEMU_KVM_ARM_TARGET_NONE) {
-            init->target = *cpus_to_try++;
-            memset(init->features, 0, sizeof(init->features));
-            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, init);
+            try.target = *cpus_to_try++;
+            memcpy(try.features, init->features, sizeof(init->features));
+            ret = ioctl(cpufd, KVM_ARM_VCPU_INIT, &try);
             if (ret >= 0) {
                 break;
             }
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
         if (ret < 0) {
             goto err;
         }
+        init->target = try.target;
     } else {
         /* Treat a NULL cpus_to_try argument the same as an empty
          * list, which means we will fail the call since this must
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         QEMU_KVM_ARM_TARGET_CORTEX_A15,
         QEMU_KVM_ARM_TARGET_NONE
     };
-    struct kvm_vcpu_init init;
+    /*
+     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
+     * to use the preferred target
+     */
+    struct kvm_vcpu_init init = { .target = -1, };
 
     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
         return false;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         KVM_ARM_TARGET_CORTEX_A57,
         QEMU_KVM_ARM_TARGET_NONE
     };
-    struct kvm_vcpu_init init;
+    /*
+     * target = -1 informs kvm_arm_create_scratch_host_vcpu()
+     * to use the preferred target
+     */
+    struct kvm_vcpu_init init = { .target = -1, };
 
     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
         return false;
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Extend the SVE vq map initialization and validation with KVM's
supported vector lengths when KVM is enabled. In order to determine
and select supported lengths we add two new KVM functions for getting
and setting the KVM_REG_ARM64_SVE_VLS pseudo-register.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-9-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h      |  12 +++
 target/arm/cpu64.c        | 176 ++++++++++++++++++++++++++++----------
 target/arm/kvm64.c        | 100 +++++++++++++++++++++-
 tests/arm-cpu-features.c  | 104 +++++++++++++++++++++-
 docs/arm-cpu-features.rst |  45 +++++++---
 5 files changed, 379 insertions(+), 58 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ typedef struct ARMHostCPUFeatures {
  */
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
 
+/**
+ * kvm_arm_sve_get_vls:
+ * @cs: CPUState
+ * @map: bitmap to fill in
+ *
+ * Get all the SVE vector lengths supported by the KVM host, setting
+ * the bits corresponding to their length in quadwords minus one
+ * (vq - 1) in @map up to ARM_MAX_VQ.
+ */
+void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map);
+
 /**
  * kvm_arm_set_cpu_features_from_host:
  * @cpu: ARMCPU to set the features for
@@ -XXX,XX +XXX,XX @@ static inline int kvm_arm_vgic_probe(void)
 static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
 static inline void kvm_arm_pmu_init(CPUState *cs) {}
 
+static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
 #endif
 
 static inline const char *gic_class_name(void)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
      * any of the above.  Finally, if SVE is not disabled, then at least one
      * vector length must be enabled.
      */
+    DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ);
     DECLARE_BITMAP(tmp, ARM_MAX_VQ);
     uint32_t vq, max_vq = 0;
 
+    /* Collect the set of vector lengths supported by KVM. */
+    bitmap_zero(kvm_supported, ARM_MAX_VQ);
+    if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) {
+        kvm_arm_sve_get_vls(CPU(cpu), kvm_supported);
+    } else if (kvm_enabled()) {
+        assert(!cpu_isar_feature(aa64_sve, cpu));
+    }
+
     /*
      * Process explicit sve<N> properties.
      * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
             return;
         }
 
-        /* Propagate enabled bits down through required powers-of-two. */
-        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
-            if (!test_bit(vq - 1, cpu->sve_vq_init)) {
-                set_bit(vq - 1, cpu->sve_vq_map);
+        if (kvm_enabled()) {
+            /*
+             * For KVM we have to automatically enable all supported unitialized
+             * lengths, even when the smaller lengths are not all powers-of-two.
+             */
+            bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq);
+            bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq);
+        } else {
+            /* Propagate enabled bits down through required powers-of-two. */
+            for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+                if (!test_bit(vq - 1, cpu->sve_vq_init)) {
+                    set_bit(vq - 1, cpu->sve_vq_map);
+                }
             }
         }
     } else if (cpu->sve_max_vq == 0) {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
             return;
         }
 
-        /* Disabling a power-of-two disables all larger lengths. */
-        if (test_bit(0, cpu->sve_vq_init)) {
-            error_setg(errp, "cannot disable sve128");
-            error_append_hint(errp, "Disabling sve128 results in all vector "
-                              "lengths being disabled.\n");
-            error_append_hint(errp, "With SVE enabled, at least one vector "
-                              "length must be enabled.\n");
-            return;
-        }
-        for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
-            if (test_bit(vq - 1, cpu->sve_vq_init)) {
-                break;
+        if (kvm_enabled()) {
+            /* Disabling a supported length disables all larger lengths. */
+            for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+                if (test_bit(vq - 1, cpu->sve_vq_init) &&
+                    test_bit(vq - 1, kvm_supported)) {
+                    break;
+                }
             }
+            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
+            bitmap_andnot(cpu->sve_vq_map, kvm_supported,
+                          cpu->sve_vq_init, max_vq);
+            if (max_vq == 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) {
+                error_setg(errp, "cannot disable sve%d", vq * 128);
+                error_append_hint(errp, "Disabling sve%d results in all "
+                                  "vector lengths being disabled.\n",
+                                  vq * 128);
+                error_append_hint(errp, "With SVE enabled, at least one "
+                                  "vector length must be enabled.\n");
+                return;
+            }
+        } else {
+            /* Disabling a power-of-two disables all larger lengths. */
+            if (test_bit(0, cpu->sve_vq_init)) {
+                error_setg(errp, "cannot disable sve128");
+                error_append_hint(errp, "Disabling sve128 results in all "
+                                  "vector lengths being disabled.\n");
+                error_append_hint(errp, "With SVE enabled, at least one "
+                                  "vector length must be enabled.\n");
+                return;
+            }
+            for (vq = 2; vq <= ARM_MAX_VQ; vq <<= 1) {
+                if (test_bit(vq - 1, cpu->sve_vq_init)) {
+                    break;
+                }
+            }
+            max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
+            bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
         }
-        max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
 
-        bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq);
         max_vq = find_last_bit(cpu->sve_vq_map, max_vq) + 1;
     }
 
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
     assert(max_vq != 0);
     bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq);
 
-    /* Ensure all required powers-of-two are enabled. */
-    for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
-        if (!test_bit(vq - 1, cpu->sve_vq_map)) {
-            error_setg(errp, "cannot disable sve%d", vq * 128);
-            error_append_hint(errp, "sve%d is required as it "
-                              "is a power-of-two length smaller than "
-                              "the maximum, sve%d\n",
-                              vq * 128, max_vq * 128);
+    if (kvm_enabled()) {
+        /* Ensure the set of lengths matches what KVM supports. */
+        bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq);
+        if (!bitmap_empty(tmp, max_vq)) {
+            vq = find_last_bit(tmp, max_vq) + 1;
+            if (test_bit(vq - 1, cpu->sve_vq_map)) {
+                if (cpu->sve_max_vq) {
+                    error_setg(errp, "cannot set sve-max-vq=%d",
+                               cpu->sve_max_vq);
+                    error_append_hint(errp, "This KVM host does not support "
+                                      "the vector length %d-bits.\n",
+                                      vq * 128);
+                    error_append_hint(errp, "It may not be possible to use "
+                                      "sve-max-vq with this KVM host. Try "
+                                      "using only sve<N> properties.\n");
+                } else {
+                    error_setg(errp, "cannot enable sve%d", vq * 128);
+                    error_append_hint(errp, "This KVM host does not support "
+                                      "the vector length %d-bits.\n",
+                                      vq * 128);
+                }
+            } else {
+                error_setg(errp, "cannot disable sve%d", vq * 128);
+                error_append_hint(errp, "The KVM host requires all "
+                                  "supported vector lengths smaller "
+                                  "than %d bits to also be enabled.\n",
+                                  max_vq * 128);
+            }
             return;
         }
+    } else {
+        /* Ensure all required powers-of-two are enabled. */
+        for (vq = pow2floor(max_vq); vq >= 1; vq >>= 1) {
+            if (!test_bit(vq - 1, cpu->sve_vq_map)) {
+                error_setg(errp, "cannot disable sve%d", vq * 128);
+                error_append_hint(errp, "sve%d is required as it "
+                                  "is a power-of-two length smaller than "
+                                  "the maximum, sve%d\n",
+                                  vq * 128, max_vq * 128);
+                return;
+            }
+        }
     }
 
     /*
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
 {
     ARMCPU *cpu = ARM_CPU(obj);
     Error *err = NULL;
+    uint32_t max_vq;
 
-    visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
-
-    if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
-        error_setg(&err, "unsupported SVE vector length");
-        error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
-                          ARM_MAX_VQ);
+    visit_type_uint32(v, name, &max_vq, &err);
+    if (err) {
+        error_propagate(errp, err);
+        return;
     }
-    error_propagate(errp, err);
+
+    if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+        error_setg(errp, "cannot set sve-max-vq");
+        error_append_hint(errp, "SVE not supported by KVM on this host\n");
+        return;
+    }
+
+    if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
+        error_setg(errp, "unsupported SVE vector length");
+        error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
+                          ARM_MAX_VQ);
+        return;
+    }
+
+    cpu->sve_max_vq = max_vq;
 }
 
 static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
         return;
     }
 
+    if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) {
+        error_setg(errp, "cannot enable %s", name);
+        error_append_hint(errp, "SVE not supported by KVM on this host\n");
+        return;
+    }
+
     if (value) {
         set_bit(vq - 1, cpu->sve_vq_map);
     } else {
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
         cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
-
-        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
-                            cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-
-        for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
-            char name[8];
-            sprintf(name, "sve%d", vq * 128);
-            object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
-                                cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
-        }
     }
 
     object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
                         cpu_arm_set_sve, NULL, NULL, &error_fatal);
+    object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+                        cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
+
+    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+        char name[8];
+        sprintf(name, "sve%d", vq * 128);
+        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
+                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+    }
 }
 
 struct ARMCPUInfo {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(CPUState *cpu)
     return kvm_check_extension(s, KVM_CAP_ARM_SVE);
 }
 
+QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
+
+void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
+{
+    /* Only call this function if kvm_arm_sve_supported() returns true. */
+    static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];
+    static bool probed;
+    uint32_t vq = 0;
+    int i, j;
+
+    bitmap_clear(map, 0, ARM_MAX_VQ);
+
+    /*
+     * KVM ensures all host CPUs support the same set of vector lengths.
+     * So we only need to create the scratch VCPUs once and then cache
+     * the results.
+     */
+    if (!probed) {
+        struct kvm_vcpu_init init = {
+            .target = -1,
+            .features[0] = (1 << KVM_ARM_VCPU_SVE),
+        };
+        struct kvm_one_reg reg = {
+            .id = KVM_REG_ARM64_SVE_VLS,
+            .addr = (uint64_t)&vls[0],
+        };
+        int fdarray[3], ret;
+
+        probed = true;
+
+        if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) {
+            error_report("failed to create scratch VCPU with SVE enabled");
+            abort();
+        }
+        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &reg);
+        kvm_arm_destroy_scratch_host_vcpu(fdarray);
+        if (ret) {
+            error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s",
+                         strerror(errno));
+            abort();
+        }
+
+        for (i = KVM_ARM64_SVE_VLS_WORDS - 1; i >= 0; --i) {
+            if (vls[i]) {
+                vq = 64 - clz64(vls[i]) + i * 64;
+                break;
+            }
+        }
+        if (vq > ARM_MAX_VQ) {
+            warn_report("KVM supports vector lengths larger than "
+                        "QEMU can enable");
+        }
+    }
+
+    for (i = 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) {
+        if (!vls[i]) {
+            continue;
+        }
+        for (j = 1; j <= 64; ++j) {
+            vq = j + i * 64;
+            if (vq > ARM_MAX_VQ) {
+                return;
+            }
+            if (vls[i] & (1UL << (j - 1))) {
+                set_bit(vq - 1, map);
+            }
+        }
+    }
+}
+
+static int kvm_arm_sve_set_vls(CPUState *cs)
+{
+    uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] = {0};
+    struct kvm_one_reg reg = {
+        .id = KVM_REG_ARM64_SVE_VLS,
+        .addr = (uint64_t)&vls[0],
+    };
+    ARMCPU *cpu = ARM_CPU(cs);
+    uint32_t vq;
+    int i, j;
+
+    assert(cpu->sve_max_vq <= KVM_ARM64_SVE_VQ_MAX);
+
+    for (vq = 1; vq <= cpu->sve_max_vq; ++vq) {
+        if (test_bit(vq - 1, cpu->sve_vq_map)) {
+            i = (vq - 1) / 64;
+            j = (vq - 1) % 64;
+            vls[i] |= 1UL << j;
+        }
+    }
+
+    return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
+}
+
 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
 
 int kvm_arch_init_vcpu(CPUState *cs)
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
 
     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
         !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
-        fprintf(stderr, "KVM is not supported for this guest CPU type\n");
+        error_report("KVM is not supported for this guest CPU type");
         return -EINVAL;
     }
 
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     }
 
     if (cpu_isar_feature(aa64_sve, cpu)) {
+        ret = kvm_arm_sve_set_vls(cs);
+        if (ret) {
+            return ret;
+        }
         ret = kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE);
         if (ret) {
             return ret;
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static QDict *resp_get_props(QDict *resp)
     return qdict;
 }
 
+static bool resp_get_feature(QDict *resp, const char *feature)
+{
+    QDict *props;
+
+    g_assert(resp);
+    g_assert(resp_has_props(resp));
+    props = resp_get_props(resp);
+    g_assert(qdict_get(props, feature));
+    return qdict_get_bool(props, feature);
+}
+
 #define assert_has_feature(qts, cpu_type, feature)                     \
 ({                                                                     \
     QDict *_resp = do_query_no_props(qts, cpu_type);                   \
@@ -XXX,XX +XXX,XX @@ static void sve_tests_sve_off(const void *data)
     qtest_quit(qts);
 }
 
+static void sve_tests_sve_off_kvm(const void *data)
+{
+    QTestState *qts;
+
+    qts = qtest_init(MACHINE_KVM "-cpu max,sve=off");
+
+    /*
+     * We don't know if this host supports SVE so we don't
+     * attempt to test enabling anything. We only test that
+     * everything is disabled (as it should be with sve=off)
+     * and that using sve<N>=off to explicitly disable vector
+     * lengths is OK too.
+     */
+    assert_sve_vls(qts, "max", 0, NULL);
+    assert_sve_vls(qts, "max", 0, "{ 'sve128': false }");
+
+    qtest_quit(qts);
+}
+
 static void test_query_cpu_model_expansion(const void *data)
 {
     QTestState *qts;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
     }
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        bool kvm_supports_sve;
+        char max_name[8], name[8];
+        uint32_t max_vq, vq;
+        uint64_t vls;
+        QDict *resp;
+        char *error;
+
         assert_has_feature(qts, "host", "aarch64");
         assert_has_feature(qts, "host", "pmu");
 
-        assert_has_feature(qts, "max", "sve");
-
         assert_error(qts, "cortex-a15",
             "We cannot guarantee the CPU type 'cortex-a15' works "
             "with KVM on this host", NULL);
+
+        assert_has_feature(qts, "max", "sve");
+        resp = do_query_no_props(qts, "max");
+        kvm_supports_sve = resp_get_feature(resp, "sve");
+        vls = resp_get_sve_vls(resp);
+        qobject_unref(resp);
+
+        if (kvm_supports_sve) {
+            g_assert(vls != 0);
+            max_vq = 64 - __builtin_clzll(vls);
+            sprintf(max_name, "sve%d", max_vq * 128);
+
+            /* Enabling a supported length is of course fine. */
+            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
+
+            /* Get the next supported length smaller than max-vq. */
+            vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
+            if (vq) {
+                /*
+                 * We have at least one length smaller than max-vq,
+                 * so we can disable max-vq.
+                 */
+                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
+                               "{ %s: false }", max_name);
+
+                /*
+                 * Smaller, supported vector lengths cannot be disabled
+                 * unless all larger, supported vector lengths are also
+                 * disabled.
+                 */
+                sprintf(name, "sve%d", vq * 128);
+                error = g_strdup_printf("cannot disable %s", name);
+                assert_error(qts, "max", error,
+                             "{ %s: true, %s: false }",
+                             max_name, name);
+                g_free(error);
+            }
+
+            /*
+             * The smallest, supported vector length is required, because
+             * we need at least one vector length enabled.
+             */
+            vq = __builtin_ffsll(vls);
+            sprintf(name, "sve%d", vq * 128);
+            error = g_strdup_printf("cannot disable %s", name);
+            assert_error(qts, "max", error, "{ %s: false }", name);
+            g_free(error);
+
+            /* Get an unsupported length. */
+            for (vq = 1; vq <= max_vq; ++vq) {
+                if (!(vls & BIT_ULL(vq - 1))) {
+                    break;
+                }
+            }
+            if (vq <= SVE_MAX_VQ) {
+                sprintf(name, "sve%d", vq * 128);
+                error = g_strdup_printf("cannot enable %s", name);
+                assert_error(qts, "max", error, "{ %s: true }", name);
+                g_free(error);
+            }
+        } else {
+            g_assert(vls == 0);
+        }
     } else {
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv)
                             NULL, sve_tests_sve_max_vq_8);
         qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
                             NULL, sve_tests_sve_off);
+        qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+                            NULL, sve_tests_sve_off_kvm);
     }
 
     return g_test_run();
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Dependencies and Constraints
 
   1) At least one vector length must be enabled when `sve` is enabled.
 
-  2) If a vector length `N` is enabled, then all power-of-two vector
-     lengths smaller than `N` must also be enabled.  E.g. if `sve512`
-     is enabled, then the 128-bit and 256-bit vector lengths must also
-     be enabled.
+  2) If a vector length `N` is enabled, then, when KVM is enabled, all
+     smaller, host supported vector lengths must also be enabled.  If
+     KVM is not enabled, then only all the smaller, power-of-two vector
+     lengths must be enabled.  E.g. with KVM if the host supports all
+     vector lengths up to 512-bits (128, 256, 384, 512), then if `sve512`
+     is enabled, the 128-bit vector length, 256-bit vector length, and
+     384-bit vector length must also be enabled. Without KVM, the 384-bit
+     vector length would not be required.
+
+  3) If KVM is enabled then only vector lengths that the host CPU type
+     support may be enabled.  If SVE is not supported by the host, then
+     no `sve*` properties may be enabled.
 
 SVE CPU Property Parsing Semantics
 ----------------------------------
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
      an error is generated.
 
   2) If SVE is enabled (`sve=on`), but no `sve<N>` CPU properties are
-     provided, then all supported vector lengths are enabled, including
-     the non-power-of-two lengths.
+     provided, then all supported vector lengths are enabled, which when
+     KVM is not in use means including the non-power-of-two lengths, and,
+     when KVM is in use, it means all vector lengths supported by the host
+     processor.
 
   3) If SVE is enabled, then an error is generated when attempting to
      disable the last enabled vector length (see constraint (1) of "SVE
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Parsing Semantics
      has been explicitly disabled, then an error is generated (see
      constraint (2) of "SVE CPU Property Dependencies and Constraints").
 
-  5) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
+  5) When KVM is enabled, if the host does not support SVE, then an error
+     is generated when attempting to enable any `sve*` properties (see
+     constraint (3) of "SVE CPU Property Dependencies and Constraints").
+
+  6) When KVM is enabled, if the host does support SVE, then an error is
+     generated when attempting to enable any vector lengths not supported
+     by the host (see constraint (3) of "SVE CPU Property Dependencies and
+     Constraints").
+
+  7) If one or more `sve<N>` CPU properties are set `off`, but no `sve<N>`,
      CPU properties are set `on`, then the specified vector lengths are
      disabled but the default for any unspecified lengths remains enabled.
-     Disabling a power-of-two vector length also disables all vector
-     lengths larger than the power-of-two length (see constraint (2) of
-     "SVE CPU Property Dependencies and Constraints").
+     When KVM is not enabled, disabling a power-of-two vector length also
+     disables all vector lengths larger than the power-of-two length.
+     When KVM is enabled, then disabling any supported vector length also
+     disables all larger vector lengths (see constraint (2) of "SVE CPU
+     Property Dependencies and Constraints").
 
-  6) If one or more `sve<N>` CPU properties are set to `on`, then they
+  8) If one or more `sve<N>` CPU properties are set to `on`, then they
      are enabled and all unspecified lengths default to disabled, except
      for the required lengths per constraint (2) of "SVE CPU Property
      Dependencies and Constraints", which will even be auto-enabled if
      they were not explicitly enabled.
 
-  7) If SVE was disabled (`sve=off`), allowing all vector lengths to be
+  9) If SVE was disabled (`sve=off`), allowing all vector lengths to be
      explicitly disabled (i.e. avoiding the error specified in (3) of
      "SVE CPU Property Parsing Semantics"), then if later an `sve=on` is
      provided an error will be generated.  To avoid this error, one must
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Allow cpu 'host' to enable SVE when it's available, unless the
user chooses to disable it with the added 'sve=off' cpu property.
Also give the user the ability to select vector lengths with the
sve<N> properties. We don't adopt 'max' cpu's other sve property,
sve-max-vq, because that property is difficult to use with KVM.
That property assumes all vector lengths in the range from 1 up
to and including the specified maximum length are supported, but
there may be optional lengths not supported by the host in that
range. With KVM one must be more specific when enabling vector
lengths.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Message-id: 20191031142734.8590-10-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h          |  2 ++
 target/arm/cpu.c          |  3 +++
 target/arm/cpu64.c        | 33 +++++++++++++++++----------------
 target/arm/kvm64.c        | 14 +++++++++++++-
 tests/arm-cpu-features.c  | 17 ++++++++---------
 docs/arm-cpu-features.rst | 19 ++++++++++++-------
 6 files changed, 55 insertions(+), 33 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
 void aarch64_sve_change_el(CPUARMState *env, int old_el,
                            int new_el, bool el0_a64);
+void aarch64_add_sve_properties(Object *obj);
 #else
 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
                                          int n, bool a)
 { }
+static inline void aarch64_add_sve_properties(Object *obj) { }
 #endif
 
 #if !defined(CONFIG_TCG)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_host_initfn(Object *obj)
     ARMCPU *cpu = ARM_CPU(obj);
 
     kvm_arm_set_cpu_features_from_host(cpu);
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        aarch64_add_sve_properties(obj);
+    }
     arm_cpu_post_init(obj);
 }
 
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
     cpu->isar.id_aa64pfr0 = t;
 }
 
+void aarch64_add_sve_properties(Object *obj)
+{
+    uint32_t vq;
+
+    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
+                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
+
+    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
+        char name[8];
+        sprintf(name, "sve%d", vq * 128);
+        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
+                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
+    }
+}
+
 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
  * otherwise, a CPU with as many features enabled as our emulation supports.
  * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
@@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name,
 static void aarch64_max_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
-    uint32_t vq;
-    uint64_t t;
 
     if (kvm_enabled()) {
         kvm_arm_set_cpu_features_from_host(cpu);
-        if (kvm_arm_sve_supported(CPU(cpu))) {
-            t = cpu->isar.id_aa64pfr0;
-            t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
-            cpu->isar.id_aa64pfr0 = t;
-        }
     } else {
+        uint64_t t;
         uint32_t u;
         aarch64_a57_initfn(obj);
 
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
 #endif
     }
 
-    object_property_add(obj, "sve", "bool", cpu_arm_get_sve,
-                        cpu_arm_set_sve, NULL, NULL, &error_fatal);
+    aarch64_add_sve_properties(obj);
     object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                         cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal);
-
-    for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
-        char name[8];
-        sprintf(name, "sve%d", vq * 128);
-        object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
-                            cpu_arm_set_sve_vq, NULL, NULL, &error_fatal);
-    }
 }
 
 struct ARMCPUInfo {
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      * and then query that CPU for the relevant ID registers.
      */
     int fdarray[3];
+    bool sve_supported;
     uint64_t features = 0;
+    uint64_t t;
     int err;
 
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                               ARM64_SYS_REG(3, 0, 0, 3, 2));
     }
 
+    sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0;
+
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
     if (err < 0) {
         return false;
     }
 
-   /* We can assume any KVM supporting CPU is at least a v8
+    /* Add feature bits that can't appear until after VCPU init. */
+    if (sve_supported) {
+        t = ahcf->isar.id_aa64pfr0;
+        t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+        ahcf->isar.id_aa64pfr0 = t;
+    }
+
+    /*
+     * We can assume any KVM supporting CPU is at least a v8
      * with VFPv4+Neon; this in turn implies most of the other
      * feature bits.
      */
diff --git a/tests/arm-cpu-features.c b/tests/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/arm-cpu-features.c
+++ b/tests/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             "We cannot guarantee the CPU type 'cortex-a15' works "
             "with KVM on this host", NULL);
 
-        assert_has_feature(qts, "max", "sve");
-        resp = do_query_no_props(qts, "max");
+        assert_has_feature(qts, "host", "sve");
+        resp = do_query_no_props(qts, "host");
         kvm_supports_sve = resp_get_feature(resp, "sve");
         vls = resp_get_sve_vls(resp);
         qobject_unref(resp);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             sprintf(max_name, "sve%d", max_vq * 128);
 
             /* Enabling a supported length is of course fine. */
-            assert_sve_vls(qts, "max", vls, "{ %s: true }", max_name);
+            assert_sve_vls(qts, "host", vls, "{ %s: true }", max_name);
 
             /* Get the next supported length smaller than max-vq. */
             vq = 64 - __builtin_clzll(vls & ~BIT_ULL(max_vq - 1));
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                  * We have at least one length smaller than max-vq,
                  * so we can disable max-vq.
                  */
-                assert_sve_vls(qts, "max", (vls & ~BIT_ULL(max_vq - 1)),
+                assert_sve_vls(qts, "host", (vls & ~BIT_ULL(max_vq - 1)),
                                "{ %s: false }", max_name);
 
                 /*
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
                  */
                 sprintf(name, "sve%d", vq * 128);
                 error = g_strdup_printf("cannot disable %s", name);
-                assert_error(qts, "max", error,
+                assert_error(qts, "host", error,
                              "{ %s: true, %s: false }",
                              max_name, name);
                 g_free(error);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             vq = __builtin_ffsll(vls);
             sprintf(name, "sve%d", vq * 128);
             error = g_strdup_printf("cannot disable %s", name);
-            assert_error(qts, "max", error, "{ %s: false }", name);
+            assert_error(qts, "host", error, "{ %s: false }", name);
             g_free(error);
 
             /* Get an unsupported length. */
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
             if (vq <= SVE_MAX_VQ) {
                 sprintf(name, "sve%d", vq * 128);
                 error = g_strdup_printf("cannot enable %s", name);
-                assert_error(qts, "max", error, "{ %s: true }", name);
+                assert_error(qts, "host", error, "{ %s: true }", name);
                 g_free(error);
             }
         } else {
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
     } else {
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
-
-        assert_has_not_feature(qts, "max", "sve");
+        assert_has_not_feature(qts, "host", "sve");
     }
 
     qtest_quit(qts);
diff --git a/docs/arm-cpu-features.rst b/docs/arm-cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/arm-cpu-features.rst
+++ b/docs/arm-cpu-features.rst
@@ -XXX,XX +XXX,XX @@ SVE CPU Property Examples
 
      $ qemu-system-aarch64 -M virt -cpu max
 
-  3) Only enable the 128-bit vector length::
+  3) When KVM is enabled, implicitly enable all host CPU supported vector
+     lengths with the `host` CPU type::
+
+     $ qemu-system-aarch64 -M virt,accel=kvm -cpu host
+
+  4) Only enable the 128-bit vector length::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve128=on
 
-  4) Disable the 512-bit vector length and all larger vector lengths,
+  5) Disable the 512-bit vector length and all larger vector lengths,
      since 512 is a power-of-two.  This results in all the smaller,
      uninitialized lengths (128, 256, and 384) defaulting to enabled::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve512=off
 
-  5) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
+  6) Enable the 128-bit, 256-bit, and 512-bit vector lengths::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve128=on,sve256=on,sve512=on
 
-  6) The same as (5), but since the 128-bit and 256-bit vector
+  7) The same as (6), but since the 128-bit and 256-bit vector
      lengths are required for the 512-bit vector length to be enabled,
      then allow them to be auto-enabled::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve512=on
 
-  7) Do the same as (6), but by first disabling SVE and then re-enabling it::
+  8) Do the same as (7), but by first disabling SVE and then re-enabling it::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve512=on,sve=on
 
-  8) Force errors regarding the last vector length::
+  9) Force errors regarding the last vector length::
 
      $ qemu-system-aarch64 -M virt -cpu max,sve128=off
      $ qemu-system-aarch64 -M virt -cpu max,sve=off,sve128=off,sve=on
@@ -XXX,XX +XXX,XX @@ The examples in "SVE CPU Property Examples" exhibit many ways to select
 vector lengths which developers may find useful in order to avoid overly
 verbose command lines.  However, the recommended way to select vector
 lengths is to explicitly enable each desired length.  Therefore only
-example's (1), (3), and (5) exhibit recommended uses of the properties.
+example's (1), (4), and (6) exhibit recommended uses of the properties.
 
-- 
2.20.1

From: Christophe Lyon <christophe.lyon@linaro.org>

rt==15 is a special case when reading the flags: it means the
destination is APSR. This patch avoids rejecting
vmrs apsr_nzcv, fpscr
as illegal instruction.

Cc: qemu-stable@nongnu.org
Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
Message-id: 20191025095711.10853-1-christophe.lyon@linaro.org
[PMM: updated the comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-vfp.inc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
     if (arm_dc_feature(s, ARM_FEATURE_M)) {
         /*
          * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
-         * Writes to R15 are UNPREDICTABLE; we choose to undef.
+         * Accesses to R15 are UNPREDICTABLE; we choose to undef.
+         * (FPSCR -> r15 is a special case which writes to the PSR flags.)
          */
-        if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
+        if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
             return false;
         }
     }
-- 
2.20.1