[Qemu-devel] [PULL 00/11] target-arm queue
[Qemu-devel] [PULL v2 00/23] target-arm queue
1
Hi; this target-arm pull request has a collection of generally
1
v2: dropped patches that add the microbit nRF51 non-volatile memories
2
fairly minor bugs to sneak in before 3.0 rc0 tomorrow...
2
and the test case for them.
3
3
4
thanks
4
thanks
5
-- PMM
5
-- PMM
6
6
7
The following changes since commit a98ff0ec2ba3538dd766b349518ee18d03942ed8:
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7
9
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180709' into staging (2018-07-09 11:00:45 +0100)
8
The following changes since commit 3a183e330dbd7dbcac3841737ac874979552cca2:
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10
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging (2019-01-28 16:26:47 +0000)
10
11
11
are available in the Git repository at:
12
are available in the Git repository at:
12
13
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180709
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190129
14
15
15
for you to fetch changes up to 8fad0a65582c0a6e324580f45516461e9b6aa439:
16
for you to fetch changes up to 46f5abc0a2566ac3dc954eeb62fd625f0eaca120:
16
17
17
hw/net/dp8393x: don't make prom region 'nomigrate' (2018-07-09 14:51:35 +0100)
18
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index (2019-01-29 11:46:06 +0000)
18
19
19
----------------------------------------------------------------
20
----------------------------------------------------------------
20
target-arm queue:
21
target-arm queue:
21
* hw/net/dp8393x: don't make prom region 'nomigrate'
22
* Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4)
22
* boards.h: Remove doc comment reference to nonexistent function
23
* v8m: Ensure IDAU is respected if SAU is disabled
23
* hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
24
* gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
24
* target/arm: Fix do_predset for large VL
25
* exec.c: Use correct attrs in cpu_memory_rw_debug()
25
* tcg: Restrict check_size_impl to multiples of the line size
26
* accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
26
* target/arm: Suppress Coverity warning for PRF
27
* target/arm: Don't clear supported PMU events when initializing PMCEID1
27
* hw/timer/cmsdk-apb-timer: fix minor corner-case bugs and
28
* memory: add memory_region_flush_rom_device()
28
suppress spurious warnings when running Linux's timer driver
29
* microbit: Add stub NRF51 TWI magnetometer/accelerometer detection
29
* hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
30
* tests/microbit-test: extend testing of microbit devices
31
* checkpatch: Don't emit spurious warnings about block comments
32
* aspeed/smc: misc bug fixes
33
* xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
34
* xlnx-zynqmp: Realize cluster after putting RPUs in it
35
* accel/tcg: Add cluster number to TCG TB hash so differently configured
36
CPUs don't pick up cached TBs for the wrong kind of CPU
30
37
31
----------------------------------------------------------------
38
----------------------------------------------------------------
32
Eric Auger (1):
39
Aaron Lindsay OS (1):
33
hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
40
target/arm: Don't clear supported PMU events when initializing PMCEID1
34
41
35
Guenter Roeck (1):
42
Cédric Le Goater (4):
36
hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
43
aspeed/smc: fix default read value
44
aspeed/smc: define registers for all possible CS
45
aspeed/smc: Add dummy data register
46
aspeed/smc: snoop SPI transfers to fake dummy cycles
37
47
38
Peter Maydell (5):
48
Julia Suvorova (3):
39
ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
49
tests/libqtest: Introduce qtest_init_with_serial()
40
hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
50
tests/microbit-test: Make test independent of global_qtest
41
hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
51
tests/microbit-test: Check nRF51 UART functionality
42
boards.h: Remove doc comment reference to nonexistent function
43
hw/net/dp8393x: don't make prom region 'nomigrate'
44
52
45
Philippe Mathieu-Daudé (1):
53
Luc Michel (1):
46
hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
54
gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0
47
55
48
Richard Henderson (3):
56
Peter Maydell (8):
49
target/arm: Suppress Coverity warning for PRF
57
exec.c: Use correct attrs in cpu_memory_rw_debug()
50
tcg: Restrict check_size_impl to multiples of the line size
58
accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write
51
target/arm: Fix do_predset for large VL
59
checkpatch: Don't emit spurious warnings about block comments
60
xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs
61
hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it
62
qom/cpu: Add cluster_index to CPUState
63
accel/tcg: Add cluster number to TCG TB hash
64
gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index
52
65
53
include/hw/arm/smmu-common.h | 1 +
66
Richard Henderson (1):
54
include/hw/boards.h | 3 +--
67
target/arm: Fix validation of 32-bit address spaces for aa32
55
include/hw/ptimer.h | 9 +++++++++
56
hw/arm/smmu-common.c | 2 +-
57
hw/core/ptimer.c | 22 +++++++++++++++++++++-
58
hw/net/dp8393x.c | 2 +-
59
hw/sd/omap_mmc.c | 14 +++++++++++---
60
hw/timer/cmsdk-apb-timer.c | 20 ++++++++++++++++++--
61
target/arm/translate-sve.c | 14 ++++----------
62
tcg/tcg-op-gvec.c | 7 +++++--
63
tests/ptimer-test.c | 25 +++++++++++++++++++------
64
11 files changed, 91 insertions(+), 28 deletions(-)
65
68
69
Stefan Hajnoczi (3):
70
tests/microbit-test: add TWI stub device test
71
MAINTAINERS: update microbit ARM board files
72
memory: add memory_region_flush_rom_device()
73
74
Steffen Görtz (1):
75
arm: Stub out NRF51 TWI magnetometer/accelerometer detection
76
77
Thomas Roth (1):
78
target/arm: v8m: Ensure IDAU is respected if SAU is disabled
79
80
hw/i2c/Makefile.objs | 1 +
81
include/exec/exec-all.h | 4 +-
82
include/exec/memory.h | 18 +++
83
include/hw/arm/nrf51.h | 2 +
84
include/hw/arm/nrf51_soc.h | 1 +
85
include/hw/cpu/cluster.h | 24 +++
86
include/hw/i2c/microbit_i2c.h | 42 +++++
87
include/hw/ssi/aspeed_smc.h | 3 +
88
include/qom/cpu.h | 7 +
89
target/arm/cpu.h | 11 +-
90
tests/libqtest.h | 11 ++
91
accel/tcg/cpu-exec.c | 3 +
92
accel/tcg/translate-all.c | 3 +
93
accel/tcg/user-exec.c | 66 ++++++--
94
exec.c | 19 ++-
95
gdbstub.c | 120 ++++++---------
96
hw/arm/microbit.c | 16 ++
97
hw/arm/xlnx-zynqmp.c | 9 +-
98
hw/cpu/cluster.c | 46 ++++++
99
hw/i2c/microbit_i2c.c | 127 +++++++++++++++
100
hw/ssi/aspeed_smc.c | 128 ++++++++++++++-
101
qom/cpu.c | 1 +
102
target/arm/cpu.c | 3 +-
103
target/arm/helper.c | 67 ++++----
104
tests/libqtest.c | 25 +++
105
tests/microbit-test.c | 350 +++++++++++++++++++++++++++++-------------
106
MAINTAINERS | 8 +-
107
scripts/checkpatch.pl | 2 +-
108
28 files changed, 874 insertions(+), 243 deletions(-)
109
create mode 100644 include/hw/i2c/microbit_i2c.h
110
create mode 100644 hw/i2c/microbit_i2c.c
111
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/11] hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding
4
to a given sid. The function extracts both the PCIe bus number and
5
the devfn to return this data. Current computation of devfn is wrong
6
as it only returns the PCIe function instead of slot | function.
7
8
Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data")
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/arm/smmu-common.h | 1 +
16
hw/arm/smmu-common.c | 2 +-
17
2 files changed, 2 insertions(+), 1 deletion(-)
18
19
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/smmu-common.h
22
+++ b/include/hw/arm/smmu-common.h
23
@@ -XXX,XX +XXX,XX @@
24
25
#define SMMU_PCI_BUS_MAX 256
26
#define SMMU_PCI_DEVFN_MAX 256
27
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
28
29
#define SMMU_MAX_VA_BITS 48
30
31
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/smmu-common.c
34
+++ b/hw/arm/smmu-common.c
35
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
36
bus_n = PCI_BUS_NUM(sid);
37
smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
38
if (smmu_bus) {
39
- devfn = sid & 0x7;
40
+ devfn = SMMU_PCI_DEVFN(sid);
41
smmu = smmu_bus->pbdev[devfn];
42
if (smmu) {
43
return &smmu->iommu;
44
--
45
2.17.1
46
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/11] ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
Deleted patch
1
The CMSDK timer behaviour is that an interrupt is triggered when the
2
counter counts down from 1 to 0; however one is not triggered if the
3
counter is manually set to 0 by a guest write to the counter register.
4
Currently ptimer can't handle this; add a policy option to allow
5
a ptimer user to request this behaviour.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20180703171044.9503-2-peter.maydell@linaro.org
11
---
12
include/hw/ptimer.h | 9 +++++++++
13
hw/core/ptimer.c | 22 +++++++++++++++++++++-
14
tests/ptimer-test.c | 25 +++++++++++++++++++------
15
3 files changed, 49 insertions(+), 7 deletions(-)
16
17
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ptimer.h
20
+++ b/include/hw/ptimer.h
21
@@ -XXX,XX +XXX,XX @@
22
* not the one less. */
23
#define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
24
25
+/*
26
+ * Starting to run with a zero counter, or setting the counter to "0" via
27
+ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer
28
+ * (though it will cause a reload). Only a counter decrement to "0"
29
+ * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
30
+ * ptimer_init() will assert() that you don't set both.
31
+ */
32
+#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
33
+
34
/* ptimer.c */
35
typedef struct ptimer_state ptimer_state;
36
typedef void (*ptimer_cb)(void *opaque);
37
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/core/ptimer.c
40
+++ b/hw/core/ptimer.c
41
@@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
42
uint32_t period_frac = s->period_frac;
43
uint64_t period = s->period;
44
uint64_t delta = s->delta;
45
+ bool suppress_trigger = false;
46
47
- if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
48
+ /*
49
+ * Note that if delta_adjust is 0 then we must be here because of
50
+ * a count register write or timer start, not because of timer expiry.
51
+ * In that case the policy might require us to suppress the timer trigger
52
+ * that we would otherwise generate for a zero delta.
53
+ */
54
+ if (delta_adjust == 0 &&
55
+ (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
56
+ suppress_trigger = true;
57
+ }
58
+ if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
59
+ && !suppress_trigger) {
60
ptimer_trigger(s);
61
}
62
63
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
64
s->bh = bh;
65
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
66
s->policy_mask = policy_mask;
67
+
68
+ /*
69
+ * These two policies are incompatible -- trigger-on-decrement implies
70
+ * a timer trigger when the count becomes 0, but no-immediate-trigger
71
+ * implies a trigger when the count stops being 0.
72
+ */
73
+ assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
74
+ (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
75
return s;
76
}
77
78
diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/tests/ptimer-test.c
81
+++ b/tests/ptimer-test.c
82
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
83
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
84
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
85
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
86
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
87
88
triggered = false;
89
90
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
91
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
92
no_immediate_reload ? 0 : 10);
93
94
- if (no_immediate_trigger) {
95
+ if (no_immediate_trigger || trig_only_on_dec) {
96
g_assert_false(triggered);
97
} else {
98
g_assert_true(triggered);
99
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
100
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
101
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
102
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
103
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
104
105
triggered = false;
106
107
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
108
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
109
no_immediate_reload ? 0 : 99);
110
111
- if (no_immediate_trigger) {
112
+ if (no_immediate_trigger || trig_only_on_dec) {
113
g_assert_false(triggered);
114
} else {
115
g_assert_true(triggered);
116
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
117
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
118
no_immediate_reload ? 0 : 99);
119
120
- if (no_immediate_trigger) {
121
+ if (no_immediate_trigger || trig_only_on_dec) {
122
g_assert_false(triggered);
123
} else {
124
g_assert_true(triggered);
125
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
126
ptimer_state *ptimer = ptimer_init(bh, *policy);
127
bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER);
128
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
129
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
130
131
triggered = false;
132
133
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
134
135
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
136
137
- if (no_immediate_trigger) {
138
+ if (no_immediate_trigger || trig_only_on_dec) {
139
g_assert_false(triggered);
140
} else {
141
g_assert_true(triggered);
142
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
143
QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL);
144
ptimer_state *ptimer = ptimer_init(bh, *policy);
145
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
146
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
147
148
triggered = false;
149
150
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
151
152
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
153
154
- if (no_immediate_trigger) {
155
+ if (no_immediate_trigger || trig_only_on_dec) {
156
g_assert_false(triggered);
157
} else {
158
g_assert_true(triggered);
159
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
160
g_strlcat(policy_name, "no_counter_rounddown,", 256);
161
}
162
163
+ if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) {
164
+ g_strlcat(policy_name, "trigger_only_on_decrement,", 256);
165
+ }
166
+
167
g_test_add_data_func_full(
168
tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name),
169
g_memdup(&policy, 1), check_set_count, g_free);
170
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
171
172
static void add_all_ptimer_policies_comb_tests(void)
173
{
174
- int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN;
175
+ int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
176
int policy = PTIMER_POLICY_DEFAULT;
177
178
for (; policy < (last_policy << 1); policy++) {
179
+ if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
180
+ (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
181
+ /* Incompatible policy flag settings -- don't try to test them */
182
+ continue;
183
+ }
184
add_ptimer_tests(policy);
185
}
186
}
187
--
188
2.17.1
189
190
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/11] hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
Deleted patch
1
The CMSDK timer interrupt triggers when the counter goes from 1 to 0,
2
so we want to trigger immediately, rather than waiting for a
3
clock cycle. Drop the incorrect NO_IMMEDIATE_TRIGGER setting.
4
We also do not want to get an interrupt if the guest sets the
5
counter directly to zero, so use the new TRIGGER_ONLY_ON_DECREMENT
6
policy.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Tested-by: Guenter Roeck <linux@roeck-us.net>
11
Message-id: 20180703171044.9503-3-peter.maydell@linaro.org
12
---
13
hw/timer/cmsdk-apb-timer.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/cmsdk-apb-timer.c
19
+++ b/hw/timer/cmsdk-apb-timer.c
20
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
21
bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
22
s->timer = ptimer_init(bh,
23
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
24
- PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
25
+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
26
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
27
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
28
29
--
30
2.17.1
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/11] hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
Deleted patch
1
From: Guenter Roeck <linux@roeck-us.net>
2
1
3
The CMSDK APB timer is currently always configured as periodic timer.
4
This results in the following messages when trying to boot Linux.
5
6
Timer with delta zero, disabling
7
8
If the timer limit set with the RELOAD command is 0, the timer
9
needs to be enabled as one-shot timer.
10
11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/timer/cmsdk-apb-timer.c | 2 +-
18
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/cmsdk-apb-timer.c
23
+++ b/hw/timer/cmsdk-apb-timer.c
24
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
25
}
26
s->ctrl = value & 0xf;
27
if (s->ctrl & R_CTRL_EN_MASK) {
28
- ptimer_run(s->timer, 0);
29
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
30
} else {
31
ptimer_stop(s->timer);
32
}
33
--
34
2.17.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/11] hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
Deleted patch
1
If the CMSDK APB timer is set up with a zero RELOAD value
2
then it will count down to zero, fire once and then stay
3
at zero. From the point of view of the ptimer system, the
4
timer is disabled; but the enable bit in the CTRL register
5
is still set and if the guest subsequently writes to the
6
RELOAD or VALUE registers this should cause the timer to
7
start counting down again.
8
1
9
Add code to the write paths for RELOAD and VALUE so that
10
we correctly restart the timer in this situation.
11
12
Conversely, if the new RELOAD and VALUE are both zero,
13
we should stop the ptimer.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
18
Message-id: 20180703171044.9503-5-peter.maydell@linaro.org
19
---
20
hw/timer/cmsdk-apb-timer.c | 16 ++++++++++++++++
21
1 file changed, 16 insertions(+)
22
23
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/cmsdk-apb-timer.c
26
+++ b/hw/timer/cmsdk-apb-timer.c
27
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
28
break;
29
case A_RELOAD:
30
/* Writing to reload also sets the current timer value */
31
+ if (!value) {
32
+ ptimer_stop(s->timer);
33
+ }
34
ptimer_set_limit(s->timer, value, 1);
35
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
36
+ /*
37
+ * Make sure timer is running (it might have stopped if this
38
+ * was an expired one-shot timer)
39
+ */
40
+ ptimer_run(s->timer, 0);
41
+ }
42
break;
43
case A_VALUE:
44
+ if (!value && !ptimer_get_limit(s->timer)) {
45
+ ptimer_stop(s->timer);
46
+ }
47
ptimer_set_count(s->timer, value);
48
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
49
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
50
+ }
51
break;
52
case A_INTSTATUS:
53
/* Just one bit, which is W1C. */
54
--
55
2.17.1
56
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/11] target/arm: Suppress Coverity warning for PRF
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
These instructions must perform the sve_access_check, but
4
since they are implemented as NOPs there is no generated
5
code to elide when the access check fails.
6
7
Fixes: Coverity issues 1393780 & 1393779.
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
20
static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
21
{
22
/* Prefetch is a nop within QEMU. */
23
- sve_access_check(s);
24
+ (void)sve_access_check(s);
25
return true;
26
}
27
28
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
29
return false;
30
}
31
/* Prefetch is a nop within QEMU. */
32
- sve_access_check(s);
33
+ (void)sve_access_check(s);
34
return true;
35
}
36
37
--
38
2.17.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/11] tcg: Restrict check_size_impl to multiples of the line size
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Normally this is automatic in the size restrictions that are placed
4
on vector sizes coming from the implementation. However, for the
5
legitimate size tuple [oprsz=8, maxsz=32], we need to clear the final
6
24 bytes of the vector register. Without this check, do_dup selects
7
TCG_TYPE_V128 and clears only 16 bytes.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20180705191929.30773-2-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
tcg/tcg-op-gvec.c | 7 +++++--
16
1 file changed, 5 insertions(+), 2 deletions(-)
17
18
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/tcg/tcg-op-gvec.c
21
+++ b/tcg/tcg-op-gvec.c
22
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
23
in units of LNSZ. This limits the expansion of inline code. */
24
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
25
{
26
- uint32_t lnct = oprsz / lnsz;
27
- return lnct >= 1 && lnct <= MAX_UNROLL;
28
+ if (oprsz % lnsz == 0) {
29
+ uint32_t lnct = oprsz / lnsz;
30
+ return lnct >= 1 && lnct <= MAX_UNROLL;
31
+ }
32
+ return false;
33
}
34
35
static void expand_clr(uint32_t dofs, uint32_t maxsz);
36
--
37
2.17.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/11] target/arm: Fix do_predset for large VL
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
Use MAKE_64BIT_MASK instead of open-coding. Remove an odd
4
vector size check that is unlikely to be more profitable
5
than 3 64-bit integer stores. Correct the iteration for WORD
6
to avoid writing too much data.
7
8
Fixes RISU tests of PTRUE for VL 256.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20180705191929.30773-3-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/translate-sve.c | 10 ++--------
17
1 file changed, 2 insertions(+), 8 deletions(-)
18
19
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
24
setsz = numelem << esz;
25
lastword = word = pred_esz_masks[esz];
26
if (setsz % 64) {
27
- lastword &= ~(-1ull << (setsz % 64));
28
+ lastword &= MAKE_64BIT_MASK(0, setsz % 64);
29
}
30
}
31
32
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
33
tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
34
goto done;
35
}
36
- if (oprsz * 8 == setsz + 8) {
37
- tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
38
- tcg_gen_movi_i64(t, 0);
39
- tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
40
- goto done;
41
- }
42
}
43
44
setsz /= 8;
45
fullsz /= 8;
46
47
tcg_gen_movi_i64(t, word);
48
- for (i = 0; i < setsz; i += 8) {
49
+ for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
50
tcg_gen_st_i64(t, cpu_env, ofs + i);
51
}
52
if (lastword != word) {
53
--
54
2.17.1
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/11] hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
DeviceClass::reset models a "cold power-on" reset which can
4
also be used to powercycle a device; but there is no "hot reset"
5
(a.k.a. soft-reset) method available.
6
7
The OMAP MMC Power-Up Control bit is not designed to powercycle
8
a card, but to disable it without powering it off (pseudo-reset):
9
10
Multimedia Card (MMC/SD/SDIO) Interface [SPRU765A]
11
12
MMC_CON[11] Power-Up Control (POW)
13
This bit must be set to 1 before any valid transaction to either
14
MMC/SD or SPI memory cards.
15
When 1, the card is considered powered-up and the controller core
16
is enabled.
17
When 0, the card is considered powered-down (system dependent),
18
and the controller core logic is in pseudo-reset state. This is,
19
the MMC_STAT flags and the FIFO pointers are reset, any access to
20
MMC_DATA[DATA] has no effect, a write into the MMC.CMD register
21
is ignored, and a setting of MMC_SPI[STR] to 1 is ignored.
22
23
By splitting the 'pseudo-reset' code out of the 'power-on' reset
24
function, this patch fixes a latent bug in omap_mmc_write(MMC_CON)i
25
recently exposed by ecd219f7abb.
26
27
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Message-id: 20180706162155.8432-2-f4bug@amsat.org
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
32
hw/sd/omap_mmc.c | 14 +++++++++++---
33
1 file changed, 11 insertions(+), 3 deletions(-)
34
35
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/omap_mmc.c
38
+++ b/hw/sd/omap_mmc.c
39
@@ -XXX,XX +XXX,XX @@
40
/*
41
* OMAP on-chip MMC/SD host emulation.
42
*
43
+ * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
44
+ *
45
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
46
*
47
* This program is free software; you can redistribute it and/or
48
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_update(void *opaque)
49
omap_mmc_interrupts_update(s);
50
}
51
52
+static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
53
+{
54
+ host->status = 0;
55
+ host->fifo_len = 0;
56
+}
57
+
58
void omap_mmc_reset(struct omap_mmc_s *host)
59
{
60
host->last_cmd = 0;
61
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
62
host->dw = 0;
63
host->mode = 0;
64
host->enable = 0;
65
- host->status = 0;
66
host->mask = 0;
67
host->cto = 0;
68
host->dto = 0;
69
- host->fifo_len = 0;
70
host->blen = 0;
71
host->blen_counter = 0;
72
host->nblk = 0;
73
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
74
qemu_set_irq(host->coverswitch, host->cdet_state);
75
host->clkdiv = 0;
76
77
+ omap_mmc_pseudo_reset(host);
78
+
79
/* Since we're still using the legacy SD API the card is not plugged
80
* into any bus, and we must reset it manually. When omap_mmc is
81
* QOMified this must move into the QOM reset function.
82
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
83
if (s->dw != 0 && s->lines < 4)
84
printf("4-bit SD bus enabled\n");
85
if (!s->enable)
86
- omap_mmc_reset(s);
87
+ omap_mmc_pseudo_reset(s);
88
break;
89
90
case 0x10:    /* MMC_STAT */
91
--
92
2.17.1
93
94
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/11] boards.h: Remove doc comment reference to nonexistent function
Deleted patch
1
commit b08199c6fbea1 accidentally added a reference to a doc
2
comment to a nonexistent memory_region_allocate_aux_memory().
3
This was a leftover from a previous version of the patchset
4
which defined memory_region_allocate_aux_memory() for
5
"allocate RAM MemoryRegion and register it for migration"
6
and left "memory_region_init_ram()" with its original semantics
7
of "allocate RAM MR but do not register for migration". In
8
the end we decided on the approach of "memory_region_init_ram()
9
registers the MR for migration, and memory_region_init_ram_nomigrate()
10
is a new function which does not", but this comment change
11
got left in by mistake. Revert that part of the commit.
12
1
13
Reported-by: Thomas Huth <huth@tuxfamily.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20180702130605.13611-1-peter.maydell@linaro.org
16
---
17
include/hw/boards.h | 3 +--
18
1 file changed, 1 insertion(+), 2 deletions(-)
19
20
diff --git a/include/hw/boards.h b/include/hw/boards.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/boards.h
23
+++ b/include/hw/boards.h
24
@@ -XXX,XX +XXX,XX @@
25
*
26
* Smaller pieces of memory (display RAM, static RAMs, etc) don't need
27
* to be backed via the -mem-path memory backend and can simply
28
- * be created via memory_region_allocate_aux_memory() or
29
- * memory_region_init_ram().
30
+ * be created via memory_region_init_ram().
31
*/
32
void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
33
const char *name,
34
--
35
2.17.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/11] hw/net/dp8393x: don't make prom region 'nomigrate'
Deleted patch
1
Currently we use memory_region_init_rom_nomigrate() to create
2
the "dp3893x-prom" memory region, and we don't manually register
3
it with vmstate_register_ram(). This currently means that its
4
contents are migrated but as a ram block whose name is the empty
5
string; in future it may mean they are not migrated at all. Use
6
memory_region_init_ram() instead.
7
1
8
Note that this is a a cross-version migration compatibility break
9
for the MIPS "magnum" and "pica61" machines.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Aleksandar Markovic <aleksandar.markovic@wavecomp.com>
13
Message-id: 20180706174309.27110-1-peter.maydell@linaro.org
14
---
15
hw/net/dp8393x.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
17
18
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/net/dp8393x.c
21
+++ b/hw/net/dp8393x.c
22
@@ -XXX,XX +XXX,XX @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
23
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
24
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
25
26
- memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev),
27
+ memory_region_init_ram(&s->prom, OBJECT(dev),
28
"dp8393x-prom", SONIC_PROM_SIZE, &local_err);
29
if (local_err) {
30
error_propagate(errp, local_err);
31
--
32
2.17.1
33
34
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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