1
Hi; this target-arm pull request has a collection of generally
1
target-arm queue of various easier things that had piled
2
fairly minor bugs to sneak in before 3.0 rc0 tomorrow...
2
up while I was on holiday.
3
3
4
thanks
4
thanks
5
-- PMM
5
-- PMM
6
6
7
The following changes since commit a98ff0ec2ba3538dd766b349518ee18d03942ed8:
7
The following changes since commit 506e4a00de01e0b29fa83db5cbbc3d154253b4ea:
8
8
9
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180709' into staging (2018-07-09 11:00:45 +0100)
9
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180925' into staging (2018-09-25 13:30:45 +0100)
10
10
11
are available in the Git repository at:
11
are available in the Git repository at:
12
12
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180709
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180925
14
14
15
for you to fetch changes up to 8fad0a65582c0a6e324580f45516461e9b6aa439:
15
for you to fetch changes up to 4a87106b160a3e72152443065fb92f8a1313c23d:
16
16
17
hw/net/dp8393x: don't make prom region 'nomigrate' (2018-07-09 14:51:35 +0100)
17
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode (2018-09-25 14:14:07 +0100)
18
18
19
----------------------------------------------------------------
19
----------------------------------------------------------------
20
target-arm queue:
20
target-arm queue:
21
* hw/net/dp8393x: don't make prom region 'nomigrate'
21
* target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
22
* boards.h: Remove doc comment reference to nonexistent function
22
* hw/arm/exynos4210: fix Exynos4210 UART support
23
* hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
23
* hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
24
* target/arm: Fix do_predset for large VL
24
* arm: Add BBC micro:bit machine
25
* tcg: Restrict check_size_impl to multiples of the line size
25
* aspeed/i2c: Fix interrupt handling bugs
26
* target/arm: Suppress Coverity warning for PRF
26
* hw/arm/smmu-common: Fix the name of the iommu memory regions
27
* hw/timer/cmsdk-apb-timer: fix minor corner-case bugs and
27
* hw/arm/smmuv3: fix eventq recording and IRQ triggerring
28
suppress spurious warnings when running Linux's timer driver
28
* hw/intc/arm_gic: Document QEMU interface
29
* hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
29
* hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
30
* hw/net/pcnet-pci: Convert away from old_mmio accessors
31
* hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
32
* aspeed/timer: fix compile breakage with clang 3.4.2
33
* hw/arm/aspeed: change the FMC flash model of the AST2500 evb
34
* hw/arm/aspeed: Minor code cleanups
35
* target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
30
36
31
----------------------------------------------------------------
37
----------------------------------------------------------------
32
Eric Auger (1):
38
Bartlomiej Zolnierkiewicz (1):
33
hw/arm/smmu-common: Fix devfn computation in smmu_iommu_mr
39
hw/arm/exynos4210: fix Exynos4210 UART support
34
40
35
Guenter Roeck (1):
41
Cédric Le Goater (5):
36
hw/timer/cmsdk-apb-timer: Correctly identify and set one-shot mode
42
aspeed/i2c: interrupts should be cleared by software only
43
aspeed/timer: fix compile breakage with clang 3.4.2
44
hw/arm/aspeed: change the FMC flash model of the AST2500 evb
45
hw/arm/aspeed: Add an Aspeed machine class
46
aspeed/smc: fix some alignment issues
37
47
38
Peter Maydell (5):
48
Eric Auger (2):
39
ptimer: Add TRIGGER_ONLY_ON_DECREMENT policy option
49
hw/arm/smmu-common: Fix the name of the iommu memory regions
40
hw/timer/cmsdk-apb-timer: Correct ptimer policy settings
50
hw/arm/smmuv3: fix eventq recording and IRQ triggerring
41
hw/timer/cmsdk-apb-timer: run or stop timer on writes to RELOAD and VALUE
42
boards.h: Remove doc comment reference to nonexistent function
43
hw/net/dp8393x: don't make prom region 'nomigrate'
44
51
45
Philippe Mathieu-Daudé (1):
52
Guenter Roeck (2):
46
hw/sd/omap_mmc: Split 'pseudo-reset' from 'power-on-reset'
53
aspeed/i2c: Handle receive command in separate function
54
aspeed/i2c: Fix receive done interrupt handling
47
55
48
Richard Henderson (3):
56
Joel Stanley (3):
49
target/arm: Suppress Coverity warning for PRF
57
MAINTAINERS: Add NRF51 entry
50
tcg: Restrict check_size_impl to multiples of the line size
58
arm: Add Nordic Semiconductor nRF51 SoC
51
target/arm: Fix do_predset for large VL
59
arm: Add BBC micro:bit machine
52
60
53
include/hw/arm/smmu-common.h | 1 +
61
Peter Maydell (6):
54
include/hw/boards.h | 3 +--
62
hw/intc/arm_gic: Document QEMU interface
55
include/hw/ptimer.h | 9 +++++++++
63
hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
56
hw/arm/smmu-common.c | 2 +-
64
hw/net/pcnet-pci: Convert away from old_mmio accessors
57
hw/core/ptimer.c | 22 +++++++++++++++++++++-
65
hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
58
hw/net/dp8393x.c | 2 +-
66
hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
59
hw/sd/omap_mmc.c | 14 +++++++++++---
67
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
60
hw/timer/cmsdk-apb-timer.c | 20 ++++++++++++++++++--
61
target/arm/translate-sve.c | 14 ++++----------
62
tcg/tcg-op-gvec.c | 7 +++++--
63
tests/ptimer-test.c | 25 +++++++++++++++++++------
64
11 files changed, 91 insertions(+), 28 deletions(-)
65
68
69
Richard Henderson (1):
70
target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
71
72
Shannon Zhao (1):
73
hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
74
75
hw/arm/Makefile.objs | 1 +
76
hw/arm/smmuv3-internal.h | 26 ++---
77
hw/intc/gic_internal.h | 2 -
78
include/hw/arm/aspeed.h | 46 +++++++++
79
include/hw/arm/nrf51_soc.h | 41 ++++++++
80
include/hw/intc/arm_gic.h | 43 ++++++++
81
include/hw/timer/aspeed_timer.h | 3 +-
82
hw/arm/aspeed.c | 212 +++++++++++++---------------------------
83
hw/arm/exynos4210.c | 8 +-
84
hw/arm/microbit.c | 67 +++++++++++++
85
hw/arm/nrf51_soc.c | 133 +++++++++++++++++++++++++
86
hw/arm/smmu-common.c | 6 +-
87
hw/arm/smmuv3.c | 2 +-
88
hw/arm/virt-acpi-build.c | 10 +-
89
hw/i2c/aspeed_i2c.c | 63 ++++++++----
90
hw/intc/arm_gic.c | 31 +++---
91
hw/intc/arm_gic_common.c | 1 -
92
hw/net/pcnet-pci.c | 98 ++-----------------
93
hw/ssi/aspeed_smc.c | 8 +-
94
hw/timer/aspeed_timer.c | 1 -
95
hw/timer/cmsdk-apb-dualtimer.c | 2 +
96
target/arm/cpu.c | 14 ++-
97
target/arm/helper.c | 45 +++++----
98
MAINTAINERS | 8 ++
99
default-configs/arm-softmmu.mak | 1 +
100
hw/net/trace-events | 6 --
101
26 files changed, 542 insertions(+), 336 deletions(-)
102
create mode 100644 include/hw/arm/aspeed.h
103
create mode 100644 include/hw/arm/nrf51_soc.h
104
create mode 100644 hw/arm/microbit.c
105
create mode 100644 hw/arm/nrf51_soc.c
106
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
These instructions must perform the sve_access_check, but
3
Not only are the sve-related tb_flags fields unused when SVE is
4
since they are implemented as NOPs there is no generated
4
disabled, but not all of the cpu registers are initialized properly
5
code to elide when the access check fails.
5
for computing same. This can corrupt other fields by ORing in -1,
6
which might result in QEMU crashing.
6
7
7
Fixes: Coverity issues 1393780 & 1393779.
8
This bug was not present in 3.0, but this patch is cc'd to
9
stable because adf92eab90e3f5f34c285 where the bug was
10
introduced was marked for stable.
11
12
Fixes: adf92eab90e3f5f34c285
13
Cc: qemu-stable@nongnu.org (3.0.1)
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
17
---
12
target/arm/translate-sve.c | 4 ++--
18
target/arm/helper.c | 45 ++++++++++++++++++++++++---------------------
13
1 file changed, 2 insertions(+), 2 deletions(-)
19
1 file changed, 24 insertions(+), 21 deletions(-)
14
20
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
23
--- a/target/arm/helper.c
18
+++ b/target/arm/translate-sve.c
24
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
25
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
20
static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
26
uint32_t flags;
21
{
27
22
/* Prefetch is a nop within QEMU. */
28
if (is_a64(env)) {
23
- sve_access_check(s);
29
- int sve_el = sve_exception_el(env);
24
+ (void)sve_access_check(s);
30
- uint32_t zcr_len;
25
return true;
31
-
26
}
32
*pc = env->pc;
27
33
flags = ARM_TBFLAG_AARCH64_STATE_MASK;
28
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
34
/* Get control bits for tagged addresses */
29
return false;
35
flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
30
}
36
flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
31
/* Prefetch is a nop within QEMU. */
37
- flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT;
32
- sve_access_check(s);
38
33
+ (void)sve_access_check(s);
39
- /* If SVE is disabled, but FP is enabled,
34
return true;
40
- then the effective len is 0. */
35
}
41
- if (sve_el != 0 && fp_el == 0) {
36
42
- zcr_len = 0;
43
- } else {
44
- int current_el = arm_current_el(env);
45
- ARMCPU *cpu = arm_env_get_cpu(env);
46
+ if (arm_feature(env, ARM_FEATURE_SVE)) {
47
+ int sve_el = sve_exception_el(env);
48
+ uint32_t zcr_len;
49
50
- zcr_len = cpu->sve_max_vq - 1;
51
- if (current_el <= 1) {
52
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
53
- }
54
- if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
55
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
56
- }
57
- if (current_el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
58
- zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
59
+ /* If SVE is disabled, but FP is enabled,
60
+ * then the effective len is 0.
61
+ */
62
+ if (sve_el != 0 && fp_el == 0) {
63
+ zcr_len = 0;
64
+ } else {
65
+ int current_el = arm_current_el(env);
66
+ ARMCPU *cpu = arm_env_get_cpu(env);
67
+
68
+ zcr_len = cpu->sve_max_vq - 1;
69
+ if (current_el <= 1) {
70
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
71
+ }
72
+ if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
73
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
74
+ }
75
+ if (current_el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
76
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]);
77
+ }
78
}
79
+ flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT;
80
+ flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT;
81
}
82
- flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT;
83
} else {
84
*pc = env->regs[15];
85
flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
37
--
86
--
38
2.17.1
87
2.19.0
39
88
40
89
diff view generated by jsdifflib
New patch
1
From: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
1
2
3
commit 97274d0c05d4 ("hw/char/exynos4210_uart.c: Remove unneeded
4
handling of NULL chardev") broke Exynos4210 support as it removed
5
NULL 'Chardev *chr' handling from exynos4210_uart_create() and
6
currently exynos4210_init() always passes NULL as 'Chardev *chr'
7
argument to exynos4210_uart_create() calls. Fix it by adding
8
missing serial_hd() calls to exynos4210_init().
9
10
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
11
Reviewed-by: Thomas Huth <thuth@redhat.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 9310418.Wg32kryeWE@amdc3058
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/exynos4210.c | 8 ++++----
17
1 file changed, 4 insertions(+), 4 deletions(-)
18
19
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/exynos4210.c
22
+++ b/hw/arm/exynos4210.c
23
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
24
25
/*** UARTs ***/
26
exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR,
27
- EXYNOS4210_UART0_FIFO_SIZE, 0, NULL,
28
+ EXYNOS4210_UART0_FIFO_SIZE, 0, serial_hd(0),
29
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]);
30
31
exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR,
32
- EXYNOS4210_UART1_FIFO_SIZE, 1, NULL,
33
+ EXYNOS4210_UART1_FIFO_SIZE, 1, serial_hd(1),
34
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]);
35
36
exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR,
37
- EXYNOS4210_UART2_FIFO_SIZE, 2, NULL,
38
+ EXYNOS4210_UART2_FIFO_SIZE, 2, serial_hd(2),
39
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]);
40
41
exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR,
42
- EXYNOS4210_UART3_FIFO_SIZE, 3, NULL,
43
+ EXYNOS4210_UART3_FIFO_SIZE, 3, serial_hd(3),
44
s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]);
45
46
/*** SD/MMC host controllers ***/
47
--
48
2.19.0
49
50
diff view generated by jsdifflib
New patch
1
From: Shannon Zhao <shannon.zhaosl@gmail.com>
1
2
3
Like commit 16b4226(hw/acpi-build: Add a check for memory-less NUMA node
4
), it also needs to check memory length for NUMA nodes on ARM.
5
6
Signed-off-by: Shannon Zhao <shannon.zhaosl@gmail.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20180911112643.19296-1-shenglong.zsl@alibaba-inc.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/virt-acpi-build.c | 10 ++++++----
12
1 file changed, 6 insertions(+), 4 deletions(-)
13
14
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt-acpi-build.c
17
+++ b/hw/arm/virt-acpi-build.c
18
@@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
19
20
mem_base = vms->memmap[VIRT_MEM].base;
21
for (i = 0; i < nb_numa_nodes; ++i) {
22
- numamem = acpi_data_push(table_data, sizeof(*numamem));
23
- build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
24
- MEM_AFFINITY_ENABLED);
25
- mem_base += numa_info[i].node_mem;
26
+ if (numa_info[i].node_mem > 0) {
27
+ numamem = acpi_data_push(table_data, sizeof(*numamem));
28
+ build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
29
+ MEM_AFFINITY_ENABLED);
30
+ mem_base += numa_info[i].node_mem;
31
+ }
32
}
33
34
build_header(linker, table_data, (void *)(table_data->data + srat_start),
35
--
36
2.19.0
37
38
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
This contains the NRF51, and the machine that uses it, the BBC
4
micro:bit.
5
6
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
9
Message-id: 20180831220920.27113-2-joel@jms.id.au
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
MAINTAINERS | 8 ++++++++
13
1 file changed, 8 insertions(+)
14
15
diff --git a/MAINTAINERS b/MAINTAINERS
16
index XXXXXXX..XXXXXXX 100644
17
--- a/MAINTAINERS
18
+++ b/MAINTAINERS
19
@@ -XXX,XX +XXX,XX @@ F: include/hw/*/*aspeed*
20
F: hw/net/ftgmac100.c
21
F: include/hw/net/ftgmac100.h
22
23
+NRF51
24
+M: Joel Stanley <joel@jms.id.au>
25
+L: qemu-arm@nongnu.org
26
+S: Maintained
27
+F: hw/arm/nrf51_soc.c
28
+F: hw/arm/microbit.c
29
+F: include/hw/arm/nrf51_soc.h
30
+
31
CRIS Machines
32
-------------
33
Axis Dev88
34
--
35
2.19.0
36
37
diff view generated by jsdifflib
New patch
1
1
From: Joel Stanley <joel@jms.id.au>
2
3
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module,
4
plus other common ARM SoC peripherals.
5
6
http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
7
8
This defines a basic model of the CPU and memory, with no peripherals
9
implemented at this stage.
10
11
Signed-off-by: Joel Stanley <joel@jms.id.au>
12
Message-id: 20180831220920.27113-3-joel@jms.id.au
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
[PMM: wrapped a few long lines]
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/Makefile.objs | 1 +
18
include/hw/arm/nrf51_soc.h | 41 ++++++++++
19
hw/arm/nrf51_soc.c | 133 ++++++++++++++++++++++++++++++++
20
default-configs/arm-softmmu.mak | 1 +
21
4 files changed, 176 insertions(+)
22
create mode 100644 include/hw/arm/nrf51_soc.h
23
create mode 100644 hw/arm/nrf51_soc.c
24
25
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/Makefile.objs
28
+++ b/hw/arm/Makefile.objs
29
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT) += iotkit.o
30
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
31
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
32
obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o
33
+obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o
34
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
35
new file mode 100644
36
index XXXXXXX..XXXXXXX
37
--- /dev/null
38
+++ b/include/hw/arm/nrf51_soc.h
39
@@ -XXX,XX +XXX,XX @@
40
+/*
41
+ * Nordic Semiconductor nRF51 SoC
42
+ *
43
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
44
+ *
45
+ * This code is licensed under the GPL version 2 or later. See
46
+ * the COPYING file in the top-level directory.
47
+ */
48
+
49
+#ifndef NRF51_SOC_H
50
+#define NRF51_SOC_H
51
+
52
+#include "hw/sysbus.h"
53
+#include "hw/arm/armv7m.h"
54
+
55
+#define TYPE_NRF51_SOC "nrf51-soc"
56
+#define NRF51_SOC(obj) \
57
+ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
58
+
59
+typedef struct NRF51State {
60
+ /*< private >*/
61
+ SysBusDevice parent_obj;
62
+
63
+ /*< public >*/
64
+ ARMv7MState cpu;
65
+
66
+ MemoryRegion iomem;
67
+ MemoryRegion sram;
68
+ MemoryRegion flash;
69
+
70
+ uint32_t sram_size;
71
+ uint32_t flash_size;
72
+
73
+ MemoryRegion *board_memory;
74
+
75
+ MemoryRegion container;
76
+
77
+} NRF51State;
78
+
79
+#endif
80
+
81
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
82
new file mode 100644
83
index XXXXXXX..XXXXXXX
84
--- /dev/null
85
+++ b/hw/arm/nrf51_soc.c
86
@@ -XXX,XX +XXX,XX @@
87
+/*
88
+ * Nordic Semiconductor nRF51 SoC
89
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
90
+ *
91
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
92
+ *
93
+ * This code is licensed under the GPL version 2 or later. See
94
+ * the COPYING file in the top-level directory.
95
+ */
96
+
97
+#include "qemu/osdep.h"
98
+#include "qapi/error.h"
99
+#include "qemu-common.h"
100
+#include "hw/arm/arm.h"
101
+#include "hw/sysbus.h"
102
+#include "hw/boards.h"
103
+#include "hw/devices.h"
104
+#include "hw/misc/unimp.h"
105
+#include "exec/address-spaces.h"
106
+#include "sysemu/sysemu.h"
107
+#include "qemu/log.h"
108
+#include "cpu.h"
109
+
110
+#include "hw/arm/nrf51_soc.h"
111
+
112
+#define IOMEM_BASE 0x40000000
113
+#define IOMEM_SIZE 0x20000000
114
+
115
+#define FICR_BASE 0x10000000
116
+#define FICR_SIZE 0x000000fc
117
+
118
+#define FLASH_BASE 0x00000000
119
+#define SRAM_BASE 0x20000000
120
+
121
+#define PRIVATE_BASE 0xF0000000
122
+#define PRIVATE_SIZE 0x10000000
123
+
124
+/*
125
+ * The size and base is for the NRF51822 part. If other parts
126
+ * are supported in the future, add a sub-class of NRF51SoC for
127
+ * the specific variants
128
+ */
129
+#define NRF51822_FLASH_SIZE (256 * 1024)
130
+#define NRF51822_SRAM_SIZE (16 * 1024)
131
+
132
+static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
133
+{
134
+ NRF51State *s = NRF51_SOC(dev_soc);
135
+ Error *err = NULL;
136
+
137
+ if (!s->board_memory) {
138
+ error_setg(errp, "memory property was not set");
139
+ return;
140
+ }
141
+
142
+ object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
143
+ &err);
144
+ if (err) {
145
+ error_propagate(errp, err);
146
+ return;
147
+ }
148
+ object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
149
+ if (err) {
150
+ error_propagate(errp, err);
151
+ return;
152
+ }
153
+
154
+ memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
155
+
156
+ memory_region_init_rom(&s->flash, OBJECT(s), "nrf51.flash", s->flash_size,
157
+ &err);
158
+ if (err) {
159
+ error_propagate(errp, err);
160
+ return;
161
+ }
162
+ memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash);
163
+
164
+ memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &err);
165
+ if (err) {
166
+ error_propagate(errp, err);
167
+ return;
168
+ }
169
+ memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram);
170
+
171
+ create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE);
172
+ create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE);
173
+ create_unimplemented_device("nrf51_soc.private",
174
+ PRIVATE_BASE, PRIVATE_SIZE);
175
+}
176
+
177
+static void nrf51_soc_init(Object *obj)
178
+{
179
+ NRF51State *s = NRF51_SOC(obj);
180
+
181
+ memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
182
+
183
+ sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
184
+ TYPE_ARMV7M);
185
+ qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
186
+ ARM_CPU_TYPE_NAME("cortex-m0"));
187
+ qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
188
+}
189
+
190
+static Property nrf51_soc_properties[] = {
191
+ DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
192
+ MemoryRegion *),
193
+ DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
194
+ DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
195
+ NRF51822_FLASH_SIZE),
196
+ DEFINE_PROP_END_OF_LIST(),
197
+};
198
+
199
+static void nrf51_soc_class_init(ObjectClass *klass, void *data)
200
+{
201
+ DeviceClass *dc = DEVICE_CLASS(klass);
202
+
203
+ dc->realize = nrf51_soc_realize;
204
+ dc->props = nrf51_soc_properties;
205
+}
206
+
207
+static const TypeInfo nrf51_soc_info = {
208
+ .name = TYPE_NRF51_SOC,
209
+ .parent = TYPE_SYS_BUS_DEVICE,
210
+ .instance_size = sizeof(NRF51State),
211
+ .instance_init = nrf51_soc_init,
212
+ .class_init = nrf51_soc_class_init,
213
+};
214
+
215
+static void nrf51_soc_types(void)
216
+{
217
+ type_register_static(&nrf51_soc_info);
218
+}
219
+type_init(nrf51_soc_types)
220
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
221
index XXXXXXX..XXXXXXX 100644
222
--- a/default-configs/arm-softmmu.mak
223
+++ b/default-configs/arm-softmmu.mak
224
@@ -XXX,XX +XXX,XX @@ CONFIG_STM32F2XX_SYSCFG=y
225
CONFIG_STM32F2XX_ADC=y
226
CONFIG_STM32F2XX_SPI=y
227
CONFIG_STM32F205_SOC=y
228
+CONFIG_NRF51_SOC=y
229
230
CONFIG_CMSDK_APB_TIMER=y
231
CONFIG_CMSDK_APB_DUALTIMER=y
232
--
233
2.19.0
234
235
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
This adds the base for a machine model of the BBC micro:bit:
4
5
https://en.wikipedia.org/wiki/Micro_Bit
6
7
This is a system with a nRF51 SoC containing the main processor, with
8
various peripherals on board.
9
10
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
11
Signed-off-by: Joel Stanley <joel@jms.id.au>
12
Message-id: 20180831220920.27113-4-joel@jms.id.au
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/Makefile.objs | 2 +-
17
hw/arm/microbit.c | 67 ++++++++++++++++++++++++++++++++++++++++++++
18
2 files changed, 68 insertions(+), 1 deletion(-)
19
create mode 100644 hw/arm/microbit.c
20
21
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/Makefile.objs
24
+++ b/hw/arm/Makefile.objs
25
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT) += iotkit.o
26
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
27
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
28
obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o
29
-obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o
30
+obj-$(CONFIG_NRF51_SOC) += nrf51_soc.o microbit.o
31
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
32
new file mode 100644
33
index XXXXXXX..XXXXXXX
34
--- /dev/null
35
+++ b/hw/arm/microbit.c
36
@@ -XXX,XX +XXX,XX @@
37
+/*
38
+ * BBC micro:bit machine
39
+ * http://tech.microbit.org/hardware/
40
+ *
41
+ * Copyright 2018 Joel Stanley <joel@jms.id.au>
42
+ *
43
+ * This code is licensed under the GPL version 2 or later. See
44
+ * the COPYING file in the top-level directory.
45
+ */
46
+
47
+#include "qemu/osdep.h"
48
+#include "qapi/error.h"
49
+#include "hw/boards.h"
50
+#include "hw/arm/arm.h"
51
+#include "exec/address-spaces.h"
52
+
53
+#include "hw/arm/nrf51_soc.h"
54
+
55
+typedef struct {
56
+ MachineState parent;
57
+
58
+ NRF51State nrf51;
59
+} MicrobitMachineState;
60
+
61
+#define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit")
62
+
63
+#define MICROBIT_MACHINE(obj) \
64
+ OBJECT_CHECK(MicrobitMachineState, obj, TYPE_MICROBIT_MACHINE)
65
+
66
+static void microbit_init(MachineState *machine)
67
+{
68
+ MicrobitMachineState *s = MICROBIT_MACHINE(machine);
69
+ MemoryRegion *system_memory = get_system_memory();
70
+ Object *soc = OBJECT(&s->nrf51);
71
+
72
+ sysbus_init_child_obj(OBJECT(machine), "nrf51", soc, sizeof(s->nrf51),
73
+ TYPE_NRF51_SOC);
74
+ object_property_set_link(soc, OBJECT(system_memory), "memory",
75
+ &error_fatal);
76
+ object_property_set_bool(soc, true, "realized", &error_fatal);
77
+
78
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
79
+ NRF51_SOC(soc)->flash_size);
80
+}
81
+
82
+static void microbit_machine_class_init(ObjectClass *oc, void *data)
83
+{
84
+ MachineClass *mc = MACHINE_CLASS(oc);
85
+
86
+ mc->desc = "BBC micro:bit";
87
+ mc->init = microbit_init;
88
+ mc->max_cpus = 1;
89
+}
90
+
91
+static const TypeInfo microbit_info = {
92
+ .name = TYPE_MICROBIT_MACHINE,
93
+ .parent = TYPE_MACHINE,
94
+ .instance_size = sizeof(MicrobitMachineState),
95
+ .class_init = microbit_machine_class_init,
96
+};
97
+
98
+static void microbit_machine_init(void)
99
+{
100
+ type_register_static(&microbit_info);
101
+}
102
+
103
+type_init(microbit_machine_init);
104
--
105
2.19.0
106
107
diff view generated by jsdifflib
New patch
1
From: Cédric Le Goater <clg@kaod.org>
1
2
3
aspeed i2c interrupts should be cleared by software only, and the bus
4
interrupt should be lowered when all interrupts have been cleared.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 20180914063506.20815-2-clg@kaod.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
[PMM: drop TODO comment describing an issue which is
10
fixed later in the patch series, and clean up commit message]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/i2c/aspeed_i2c.c | 16 ++++++++++++----
14
1 file changed, 12 insertions(+), 4 deletions(-)
15
16
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/i2c/aspeed_i2c.c
19
+++ b/hw/i2c/aspeed_i2c.c
20
@@ -XXX,XX +XXX,XX @@
21
#define I2CD_AC_TIMING_REG2 0x08 /* Clock and AC Timing Control #1 */
22
#define I2CD_INTR_CTRL_REG 0x0c /* I2CD Interrupt Control */
23
#define I2CD_INTR_STS_REG 0x10 /* I2CD Interrupt Status */
24
+
25
+#define I2CD_INTR_SLAVE_ADDR_MATCH (0x1 << 31) /* 0: addr1 1: addr2 */
26
+#define I2CD_INTR_SLAVE_ADDR_RX_PENDING (0x1 << 30)
27
+/* bits[19-16] Reserved */
28
+
29
+/* All bits below are cleared by writing 1 */
30
+#define I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15)
31
#define I2CD_INTR_SDA_DL_TIMEOUT (0x1 << 14)
32
#define I2CD_INTR_BUS_RECOVER_DONE (0x1 << 13)
33
#define I2CD_INTR_SMBUS_ALERT (0x1 << 12) /* Bus [0-3] only */
34
@@ -XXX,XX +XXX,XX @@
35
#define I2CD_INTR_SMBUS_DEV_ALERT_ADDR (0x1 << 10) /* Removed */
36
#define I2CD_INTR_SMBUS_DEF_ADDR (0x1 << 9) /* Removed */
37
#define I2CD_INTR_GCALL_ADDR (0x1 << 8) /* Removed */
38
-#define I2CD_INTR_SLAVE_MATCH (0x1 << 7) /* use RX_DONE */
39
+#define I2CD_INTR_SLAVE_ADDR_RX_MATCH (0x1 << 7) /* use RX_DONE */
40
#define I2CD_INTR_SCL_TIMEOUT (0x1 << 6)
41
#define I2CD_INTR_ABNORMAL (0x1 << 5)
42
#define I2CD_INTR_NORMAL_STOP (0x1 << 4)
43
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
44
{
45
bus->cmd &= ~0xFFFF;
46
bus->cmd |= value & 0xFFFF;
47
- bus->intr_status = 0;
48
49
if (bus->cmd & I2CD_M_START_CMD) {
50
uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
51
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
52
break;
53
case I2CD_INTR_STS_REG:
54
bus->intr_status &= ~(value & 0x7FFF);
55
- bus->controller->intr_status &= ~(1 << bus->id);
56
- qemu_irq_lower(bus->controller->irq);
57
+ if (!bus->intr_status) {
58
+ bus->controller->intr_status &= ~(1 << bus->id);
59
+ qemu_irq_lower(bus->controller->irq);
60
+ }
61
break;
62
case I2CD_DEV_ADDR_REG:
63
qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
64
--
65
2.19.0
66
67
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Guenter Roeck <linux@roeck-us.net>
2
2
3
DeviceClass::reset models a "cold power-on" reset which can
3
Receive command handling may have to be deferred if a previous receive
4
also be used to powercycle a device; but there is no "hot reset"
4
done interrupt was not yet acknowledged. Move receive command handling
5
(a.k.a. soft-reset) method available.
5
into a separate function to prepare for the necessary changes.
6
6
7
The OMAP MMC Power-Up Control bit is not designed to powercycle
7
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
8
a card, but to disable it without powering it off (pseudo-reset):
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
9
9
Message-id: 20180914063506.20815-3-clg@kaod.org
10
Multimedia Card (MMC/SD/SDIO) Interface [SPRU765A]
11
12
MMC_CON[11] Power-Up Control (POW)
13
This bit must be set to 1 before any valid transaction to either
14
MMC/SD or SPI memory cards.
15
When 1, the card is considered powered-up and the controller core
16
is enabled.
17
When 0, the card is considered powered-down (system dependent),
18
and the controller core logic is in pseudo-reset state. This is,
19
the MMC_STAT flags and the FIFO pointers are reset, any access to
20
MMC_DATA[DATA] has no effect, a write into the MMC.CMD register
21
is ignored, and a setting of MMC_SPI[STR] to 1 is ignored.
22
23
By splitting the 'pseudo-reset' code out of the 'power-on' reset
24
function, this patch fixes a latent bug in omap_mmc_write(MMC_CON)i
25
recently exposed by ecd219f7abb.
26
27
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
28
Message-id: 20180706162155.8432-2-f4bug@amsat.org
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
---
12
---
32
hw/sd/omap_mmc.c | 14 +++++++++++---
13
hw/i2c/aspeed_i2c.c | 37 +++++++++++++++++++++----------------
33
1 file changed, 11 insertions(+), 3 deletions(-)
14
1 file changed, 21 insertions(+), 16 deletions(-)
34
15
35
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
16
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
36
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/omap_mmc.c
18
--- a/hw/i2c/aspeed_i2c.c
38
+++ b/hw/sd/omap_mmc.c
19
+++ b/hw/i2c/aspeed_i2c.c
39
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
40
/*
21
return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
41
* OMAP on-chip MMC/SD host emulation.
42
*
43
+ * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A)
44
+ *
45
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
46
*
47
* This program is free software; you can redistribute it and/or
48
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_update(void *opaque)
49
omap_mmc_interrupts_update(s);
50
}
22
}
51
23
52
+static void omap_mmc_pseudo_reset(struct omap_mmc_s *host)
24
+static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
53
+{
25
+{
54
+ host->status = 0;
26
+ int ret;
55
+ host->fifo_len = 0;
27
+
28
+ aspeed_i2c_set_state(bus, I2CD_MRXD);
29
+ ret = i2c_recv(bus->bus);
30
+ if (ret < 0) {
31
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
32
+ ret = 0xff;
33
+ } else {
34
+ bus->intr_status |= I2CD_INTR_RX_DONE;
35
+ }
36
+ bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
37
+ if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
38
+ i2c_nack(bus->bus);
39
+ }
40
+ bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
41
+ aspeed_i2c_set_state(bus, I2CD_MACTIVE);
56
+}
42
+}
57
+
43
+
58
void omap_mmc_reset(struct omap_mmc_s *host)
44
/*
59
{
45
* The state machine needs some refinement. It is only used to track
60
host->last_cmd = 0;
46
* invalid STOP commands for the moment.
61
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
47
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
62
host->dw = 0;
48
}
63
host->mode = 0;
49
64
host->enable = 0;
50
if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
65
- host->status = 0;
51
- int ret;
66
host->mask = 0;
52
-
67
host->cto = 0;
53
- aspeed_i2c_set_state(bus, I2CD_MRXD);
68
host->dto = 0;
54
- ret = i2c_recv(bus->bus);
69
- host->fifo_len = 0;
55
- if (ret < 0) {
70
host->blen = 0;
56
- qemu_log_mask(LOG_GUEST_ERROR, "%s: read failed\n", __func__);
71
host->blen_counter = 0;
57
- ret = 0xff;
72
host->nblk = 0;
58
- } else {
73
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
59
- bus->intr_status |= I2CD_INTR_RX_DONE;
74
qemu_set_irq(host->coverswitch, host->cdet_state);
60
- }
75
host->clkdiv = 0;
61
- bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
76
62
- if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
77
+ omap_mmc_pseudo_reset(host);
63
- i2c_nack(bus->bus);
78
+
64
- }
79
/* Since we're still using the legacy SD API the card is not plugged
65
- bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
80
* into any bus, and we must reset it manually. When omap_mmc is
66
- aspeed_i2c_set_state(bus, I2CD_MACTIVE);
81
* QOMified this must move into the QOM reset function.
67
+ aspeed_i2c_handle_rx_cmd(bus);
82
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
68
}
83
if (s->dw != 0 && s->lines < 4)
69
84
printf("4-bit SD bus enabled\n");
70
if (bus->cmd & I2CD_M_STOP_CMD) {
85
if (!s->enable)
86
- omap_mmc_reset(s);
87
+ omap_mmc_pseudo_reset(s);
88
break;
89
90
case 0x10:    /* MMC_STAT */
91
--
71
--
92
2.17.1
72
2.19.0
93
73
94
74
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Guenter Roeck <linux@roeck-us.net>
2
2
3
The CMSDK APB timer is currently always configured as periodic timer.
3
The AST2500 datasheet says:
4
This results in the following messages when trying to boot Linux.
5
4
6
Timer with delta zero, disabling
5
I2CD10 Interrupt Status Register
6
bit 2 Receive Done Interrupt status
7
S/W needs to clear this status bit to allow next data receiving
7
8
8
If the timer limit set with the RELOAD command is 0, the timer
9
The Rx interrupt done interrupt status bit needs to be cleared
9
needs to be enabled as one-shot timer.
10
explicitly before the next byte can be received, and must therefore
11
not be auto-cleared. Also, receiving the next byte must be delayed
12
until the bit has been cleared.
10
13
11
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
14
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180914063506.20815-4-clg@kaod.org
14
Tested-by: Guenter Roeck <linux@roeck-us.net>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
18
---
17
hw/timer/cmsdk-apb-timer.c | 2 +-
19
hw/i2c/aspeed_i2c.c | 10 +++++++++-
18
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 9 insertions(+), 1 deletion(-)
19
21
20
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
22
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
21
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/timer/cmsdk-apb-timer.c
24
--- a/hw/i2c/aspeed_i2c.c
23
+++ b/hw/timer/cmsdk-apb-timer.c
25
+++ b/hw/i2c/aspeed_i2c.c
24
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
26
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
27
aspeed_i2c_set_state(bus, I2CD_MACTIVE);
28
}
29
30
- if (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) {
31
+ if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) &&
32
+ !(bus->intr_status & I2CD_INTR_RX_DONE)) {
33
aspeed_i2c_handle_rx_cmd(bus);
34
}
35
36
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
37
uint64_t value, unsigned size)
38
{
39
AspeedI2CBus *bus = opaque;
40
+ bool handle_rx;
41
42
switch (offset) {
43
case I2CD_FUN_CTRL_REG:
44
@@ -XXX,XX +XXX,XX @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
45
bus->intr_ctrl = value & 0x7FFF;
46
break;
47
case I2CD_INTR_STS_REG:
48
+ handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) &&
49
+ (value & I2CD_INTR_RX_DONE);
50
bus->intr_status &= ~(value & 0x7FFF);
51
if (!bus->intr_status) {
52
bus->controller->intr_status &= ~(1 << bus->id);
53
qemu_irq_lower(bus->controller->irq);
25
}
54
}
26
s->ctrl = value & 0xf;
55
+ if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) {
27
if (s->ctrl & R_CTRL_EN_MASK) {
56
+ aspeed_i2c_handle_rx_cmd(bus);
28
- ptimer_run(s->timer, 0);
57
+ aspeed_i2c_bus_raise_interrupt(bus);
29
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
58
+ }
30
} else {
59
break;
31
ptimer_stop(s->timer);
60
case I2CD_DEV_ADDR_REG:
32
}
61
qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
33
--
62
--
34
2.17.1
63
2.19.0
35
64
36
65
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Eric Auger <eric.auger@redhat.com>
2
2
3
smmu_iommu_mr() aims at returning the IOMMUMemoryRegion corresponding
3
At the point smmu_find_add_as() gets called, the bus number might
4
to a given sid. The function extracts both the PCIe bus number and
4
not be computed. Let's change the name of IOMMU memory region and
5
the devfn to return this data. Current computation of devfn is wrong
5
just use the devfn and an incrementing index.
6
as it only returns the PCIe function instead of slot | function.
7
6
8
Fixes 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data")
7
The name only is used for debug.
9
8
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1530775623-32399-1-git-send-email-eric.auger@redhat.com
10
Message-id: 20180921070138.10114-2-eric.auger@redhat.com
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
13
---
15
include/hw/arm/smmu-common.h | 1 +
14
hw/arm/smmu-common.c | 6 +++---
16
hw/arm/smmu-common.c | 2 +-
15
1 file changed, 3 insertions(+), 3 deletions(-)
17
2 files changed, 2 insertions(+), 1 deletion(-)
18
16
19
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/smmu-common.h
22
+++ b/include/hw/arm/smmu-common.h
23
@@ -XXX,XX +XXX,XX @@
24
25
#define SMMU_PCI_BUS_MAX 256
26
#define SMMU_PCI_DEVFN_MAX 256
27
+#define SMMU_PCI_DEVFN(sid) (sid & 0xFF)
28
29
#define SMMU_MAX_VA_BITS 48
30
31
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
17
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
32
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/smmu-common.c
19
--- a/hw/arm/smmu-common.c
34
+++ b/hw/arm/smmu-common.c
20
+++ b/hw/arm/smmu-common.c
35
@@ -XXX,XX +XXX,XX @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
21
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
36
bus_n = PCI_BUS_NUM(sid);
22
SMMUState *s = opaque;
37
smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
23
SMMUPciBus *sbus = g_hash_table_lookup(s->smmu_pcibus_by_busptr, bus);
38
if (smmu_bus) {
24
SMMUDevice *sdev;
39
- devfn = sid & 0x7;
25
+ static uint index;
40
+ devfn = SMMU_PCI_DEVFN(sid);
26
41
smmu = smmu_bus->pbdev[devfn];
27
if (!sbus) {
42
if (smmu) {
28
sbus = g_malloc0(sizeof(SMMUPciBus) +
43
return &smmu->iommu;
29
@@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn)
30
31
sdev = sbus->pbdev[devfn];
32
if (!sdev) {
33
- char *name = g_strdup_printf("%s-%d-%d",
34
- s->mrtypename,
35
- pci_bus_num(bus), devfn);
36
+ char *name = g_strdup_printf("%s-%d-%d", s->mrtypename, devfn, index++);
37
+
38
sdev = sbus->pbdev[devfn] = g_new0(SMMUDevice, 1);
39
40
sdev->smmu = s;
44
--
41
--
45
2.17.1
42
2.19.0
46
43
47
44
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Eric Auger <eric.auger@redhat.com>
2
2
3
Use MAKE_64BIT_MASK instead of open-coding. Remove an odd
3
The event queue management is broken today. Event records
4
vector size check that is unlikely to be more profitable
4
are not properly written as EVT_SET_* macro was not updating
5
than 3 64-bit integer stores. Correct the iteration for WORD
5
the actual event record. Also the event queue interrupt
6
to avoid writing too much data.
6
is not correctly triggered.
7
7
8
Fixes RISU tests of PTRUE for VL 256.
8
Fixes: bb981004eaf4 ("hw/arm/smmuv3: Event queue recording helper")
9
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180921070138.10114-3-eric.auger@redhat.com
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
Message-id: 20180705191929.30773-3-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
13
---
16
target/arm/translate-sve.c | 10 ++--------
14
hw/arm/smmuv3-internal.h | 26 +++++++++++++-------------
17
1 file changed, 2 insertions(+), 8 deletions(-)
15
hw/arm/smmuv3.c | 2 +-
16
2 files changed, 14 insertions(+), 14 deletions(-)
18
17
19
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
20
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-sve.c
20
--- a/hw/arm/smmuv3-internal.h
22
+++ b/target/arm/translate-sve.c
21
+++ b/hw/arm/smmuv3-internal.h
23
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
22
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo {
24
setsz = numelem << esz;
23
25
lastword = word = pred_esz_masks[esz];
24
#define EVT_Q_OVERFLOW (1 << 31)
26
if (setsz % 64) {
25
27
- lastword &= ~(-1ull << (setsz % 64));
26
-#define EVT_SET_TYPE(x, v) deposit32((x)->word[0], 0 , 8 , v)
28
+ lastword &= MAKE_64BIT_MASK(0, setsz % 64);
27
-#define EVT_SET_SSV(x, v) deposit32((x)->word[0], 11, 1 , v)
29
}
28
-#define EVT_SET_SSID(x, v) deposit32((x)->word[0], 12, 20, v)
29
-#define EVT_SET_SID(x, v) ((x)->word[1] = v)
30
-#define EVT_SET_STAG(x, v) deposit32((x)->word[2], 0 , 16, v)
31
-#define EVT_SET_STALL(x, v) deposit32((x)->word[2], 31, 1 , v)
32
-#define EVT_SET_PNU(x, v) deposit32((x)->word[3], 1 , 1 , v)
33
-#define EVT_SET_IND(x, v) deposit32((x)->word[3], 2 , 1 , v)
34
-#define EVT_SET_RNW(x, v) deposit32((x)->word[3], 3 , 1 , v)
35
-#define EVT_SET_S2(x, v) deposit32((x)->word[3], 7 , 1 , v)
36
-#define EVT_SET_CLASS(x, v) deposit32((x)->word[3], 8 , 2 , v)
37
+#define EVT_SET_TYPE(x, v) ((x)->word[0] = deposit32((x)->word[0], 0 , 8 , v))
38
+#define EVT_SET_SSV(x, v) ((x)->word[0] = deposit32((x)->word[0], 11, 1 , v))
39
+#define EVT_SET_SSID(x, v) ((x)->word[0] = deposit32((x)->word[0], 12, 20, v))
40
+#define EVT_SET_SID(x, v) ((x)->word[1] = v)
41
+#define EVT_SET_STAG(x, v) ((x)->word[2] = deposit32((x)->word[2], 0 , 16, v))
42
+#define EVT_SET_STALL(x, v) ((x)->word[2] = deposit32((x)->word[2], 31, 1 , v))
43
+#define EVT_SET_PNU(x, v) ((x)->word[3] = deposit32((x)->word[3], 1 , 1 , v))
44
+#define EVT_SET_IND(x, v) ((x)->word[3] = deposit32((x)->word[3], 2 , 1 , v))
45
+#define EVT_SET_RNW(x, v) ((x)->word[3] = deposit32((x)->word[3], 3 , 1 , v))
46
+#define EVT_SET_S2(x, v) ((x)->word[3] = deposit32((x)->word[3], 7 , 1 , v))
47
+#define EVT_SET_CLASS(x, v) ((x)->word[3] = deposit32((x)->word[3], 8 , 2 , v))
48
#define EVT_SET_ADDR(x, addr) \
49
do { \
50
(x)->word[5] = (uint32_t)(addr >> 32); \
51
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUEventInfo {
52
} while (0)
53
#define EVT_SET_ADDR2(x, addr) \
54
do { \
55
- deposit32((x)->word[7], 3, 29, addr >> 16); \
56
- deposit32((x)->word[7], 0, 16, addr & 0xffff);\
57
+ (x)->word[7] = deposit32((x)->word[7], 3, 29, addr >> 16); \
58
+ (x)->word[7] = deposit32((x)->word[7], 0, 16, addr & 0xffff);\
59
} while (0)
60
61
void smmuv3_record_event(SMMUv3State *s, SMMUEventInfo *event);
62
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/arm/smmuv3.c
65
+++ b/hw/arm/smmuv3.c
66
@@ -XXX,XX +XXX,XX @@ static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt)
67
return r;
30
}
68
}
31
69
32
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
70
- if (smmuv3_q_empty(q)) {
33
tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
71
+ if (!smmuv3_q_empty(q)) {
34
goto done;
72
smmuv3_trigger_irq(s, SMMU_IRQ_EVTQ, 0);
35
}
36
- if (oprsz * 8 == setsz + 8) {
37
- tcg_gen_gvec_dup64i(ofs, oprsz, maxsz, word);
38
- tcg_gen_movi_i64(t, 0);
39
- tcg_gen_st_i64(t, cpu_env, ofs + oprsz - 8);
40
- goto done;
41
- }
42
}
73
}
43
74
return MEMTX_OK;
44
setsz /= 8;
45
fullsz /= 8;
46
47
tcg_gen_movi_i64(t, word);
48
- for (i = 0; i < setsz; i += 8) {
49
+ for (i = 0; i < QEMU_ALIGN_DOWN(setsz, 8); i += 8) {
50
tcg_gen_st_i64(t, cpu_env, ofs + i);
51
}
52
if (lastword != word) {
53
--
75
--
54
2.17.1
76
2.19.0
55
77
56
78
diff view generated by jsdifflib
1
The CMSDK timer interrupt triggers when the counter goes from 1 to 0,
1
The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
2
so we want to trigger immediately, rather than waiting for a
2
etc) is now quite complicated with the addition of the
3
clock cycle. Drop the incorrect NO_IMMEDIATE_TRIGGER setting.
3
virtualization extensions. Add a comment in the header
4
We also do not want to get an interrupt if the guest sets the
4
file which documents it.
5
counter directly to zero, so use the new TRIGGER_ONLY_ON_DECREMENT
6
policy.
7
5
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20180823103818.31189-1-peter.maydell@linaro.org
11
Message-id: 20180703171044.9503-3-peter.maydell@linaro.org
12
---
9
---
13
hw/timer/cmsdk-apb-timer.c | 2 +-
10
include/hw/intc/arm_gic.h | 43 +++++++++++++++++++++++++++++++++++++++
14
1 file changed, 1 insertion(+), 1 deletion(-)
11
1 file changed, 43 insertions(+)
15
12
16
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
13
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/timer/cmsdk-apb-timer.c
15
--- a/include/hw/intc/arm_gic.h
19
+++ b/hw/timer/cmsdk-apb-timer.c
16
+++ b/include/hw/intc/arm_gic.h
20
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
17
@@ -XXX,XX +XXX,XX @@
21
bh = qemu_bh_new(cmsdk_apb_timer_tick, s);
18
* with this program; if not, see <http://www.gnu.org/licenses/>.
22
s->timer = ptimer_init(bh,
19
*/
23
PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
20
24
- PTIMER_POLICY_NO_IMMEDIATE_TRIGGER |
21
+/*
25
+ PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
22
+ * QEMU interface:
26
PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
23
+ * + QOM property "num-cpu": number of CPUs to support
27
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
24
+ * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
25
+ * + QOM property "revision": GIC version (1 or 2), or 0 for the 11MPCore GIC
26
+ * + QOM property "has-security-extensions": set true if the GIC should
27
+ * implement the security extensions
28
+ * + QOM property "has-virtualization-extensions": set true if the GIC should
29
+ * implement the virtualization extensions
30
+ * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
31
+ * [0..P-1] SPIs
32
+ * [P..P+31] PPIs for CPU 0
33
+ * [P+32..P+63] PPIs for CPU 1
34
+ * ...
35
+ * + sysbus IRQs: (in order; number will vary depending on number of cores)
36
+ * - IRQ for CPU 0
37
+ * - IRQ for CPU 1
38
+ * ...
39
+ * - FIQ for CPU 0
40
+ * - FIQ for CPU 1
41
+ * ...
42
+ * - VIRQ for CPU 0 (exists even if virt extensions not present)
43
+ * - VIRQ for CPU 1 (exists even if virt extensions not present)
44
+ * ...
45
+ * - VFIQ for CPU 0 (exists even if virt extensions not present)
46
+ * - VFIQ for CPU 1 (exists even if virt extensions not present)
47
+ * ...
48
+ * - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
49
+ * - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
50
+ * + sysbus MMIO regions: (in order; numbers will vary depending on
51
+ * whether virtualization extensions are present and on number of cores)
52
+ * - distributor registers (GICD*)
53
+ * - CPU interface for the accessing core (GICC*)
54
+ * - virtual interface control registers (GICH*) (only if virt extns present)
55
+ * - virtual CPU interface for the accessing core (GICV*) (only if virt)
56
+ * - CPU 0 CPU interface registers
57
+ * - CPU 1 CPU interface registers
58
+ * ...
59
+ * - CPU 0 virtual interface control registers (only if virt extns present)
60
+ * - CPU 1 virtual interface control registers (only if virt extns present)
61
+ * ...
62
+ */
63
+
64
#ifndef HW_ARM_GIC_H
65
#define HW_ARM_GIC_H
28
66
29
--
67
--
30
2.17.1
68
2.19.0
31
69
32
70
diff view generated by jsdifflib
1
If the CMSDK APB timer is set up with a zero RELOAD value
1
The GIC_BASE_IRQ macro is a leftover from when we shared code
2
then it will count down to zero, fire once and then stay
2
between the GICv2 and the v7M NVIC. Since the NVIC is now
3
at zero. From the point of view of the ptimer system, the
3
split off, GIC_BASE_IRQ is always 0, and we can just delete it.
4
timer is disabled; but the enable bit in the CTRL register
5
is still set and if the guest subsequently writes to the
6
RELOAD or VALUE registers this should cause the timer to
7
start counting down again.
8
9
Add code to the write paths for RELOAD and VALUE so that
10
we correctly restart the timer in this situation.
11
12
Conversely, if the new RELOAD and VALUE are both zero,
13
we should stop the ptimer.
14
4
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
18
Message-id: 20180703171044.9503-5-peter.maydell@linaro.org
8
Message-id: 20180824161819.11085-1-peter.maydell@linaro.org
19
---
9
---
20
hw/timer/cmsdk-apb-timer.c | 16 ++++++++++++++++
10
hw/intc/gic_internal.h | 2 --
21
1 file changed, 16 insertions(+)
11
hw/intc/arm_gic.c | 31 ++++++++++++++-----------------
12
hw/intc/arm_gic_common.c | 1 -
13
3 files changed, 14 insertions(+), 20 deletions(-)
22
14
23
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
15
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/timer/cmsdk-apb-timer.c
17
--- a/hw/intc/gic_internal.h
26
+++ b/hw/timer/cmsdk-apb-timer.c
18
+++ b/hw/intc/gic_internal.h
27
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
19
@@ -XXX,XX +XXX,XX @@
28
break;
20
29
case A_RELOAD:
21
#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
30
/* Writing to reload also sets the current timer value */
22
31
+ if (!value) {
23
-#define GIC_BASE_IRQ 0
32
+ ptimer_stop(s->timer);
24
-
33
+ }
25
#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
34
ptimer_set_limit(s->timer, value, 1);
26
#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))
35
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
27
#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
36
+ /*
28
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
37
+ * Make sure timer is running (it might have stopped if this
29
index XXXXXXX..XXXXXXX 100644
38
+ * was an expired one-shot timer)
30
--- a/hw/intc/arm_gic.c
39
+ */
31
+++ b/hw/intc/arm_gic.c
40
+ ptimer_run(s->timer, 0);
32
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
41
+ }
33
res = 0;
42
break;
34
if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
43
case A_VALUE:
35
/* Every byte offset holds 8 group status bits */
44
+ if (!value && !ptimer_get_limit(s->timer)) {
36
- irq = (offset - 0x080) * 8 + GIC_BASE_IRQ;
45
+ ptimer_stop(s->timer);
37
+ irq = (offset - 0x080) * 8;
46
+ }
38
if (irq >= s->num_irq) {
47
ptimer_set_count(s->timer, value);
39
goto bad_reg;
48
+ if (value && (s->ctrl & R_CTRL_EN_MASK)) {
40
}
49
+ ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0);
41
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
50
+ }
42
irq = (offset - 0x100) * 8;
51
break;
43
else
52
case A_INTSTATUS:
44
irq = (offset - 0x180) * 8;
53
/* Just one bit, which is W1C. */
45
- irq += GIC_BASE_IRQ;
46
if (irq >= s->num_irq)
47
goto bad_reg;
48
res = 0;
49
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
50
irq = (offset - 0x200) * 8;
51
else
52
irq = (offset - 0x280) * 8;
53
- irq += GIC_BASE_IRQ;
54
if (irq >= s->num_irq)
55
goto bad_reg;
56
res = 0;
57
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
58
goto bad_reg;
59
}
60
61
- irq += GIC_BASE_IRQ;
62
if (irq >= s->num_irq)
63
goto bad_reg;
64
res = 0;
65
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
66
}
67
} else if (offset < 0x800) {
68
/* Interrupt Priority. */
69
- irq = (offset - 0x400) + GIC_BASE_IRQ;
70
+ irq = (offset - 0x400);
71
if (irq >= s->num_irq)
72
goto bad_reg;
73
res = gic_dist_get_priority(s, cpu, irq, attrs);
74
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
75
/* For uniprocessor GICs these RAZ/WI */
76
res = 0;
77
} else {
78
- irq = (offset - 0x800) + GIC_BASE_IRQ;
79
+ irq = (offset - 0x800);
80
if (irq >= s->num_irq) {
81
goto bad_reg;
82
}
83
@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
84
}
85
} else if (offset < 0xf00) {
86
/* Interrupt Configuration. */
87
- irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
88
+ irq = (offset - 0xc00) * 4;
89
if (irq >= s->num_irq)
90
goto bad_reg;
91
res = 0;
92
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
93
*/
94
if (!(s->security_extn && !attrs.secure) && gic_has_groups(s)) {
95
/* Every byte offset holds 8 group status bits */
96
- irq = (offset - 0x80) * 8 + GIC_BASE_IRQ;
97
+ irq = (offset - 0x80) * 8;
98
if (irq >= s->num_irq) {
99
goto bad_reg;
100
}
101
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
102
}
103
} else if (offset < 0x180) {
104
/* Interrupt Set Enable. */
105
- irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
106
+ irq = (offset - 0x100) * 8;
107
if (irq >= s->num_irq)
108
goto bad_reg;
109
if (irq < GIC_NR_SGIS) {
110
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
111
}
112
} else if (offset < 0x200) {
113
/* Interrupt Clear Enable. */
114
- irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
115
+ irq = (offset - 0x180) * 8;
116
if (irq >= s->num_irq)
117
goto bad_reg;
118
if (irq < GIC_NR_SGIS) {
119
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
120
}
121
} else if (offset < 0x280) {
122
/* Interrupt Set Pending. */
123
- irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
124
+ irq = (offset - 0x200) * 8;
125
if (irq >= s->num_irq)
126
goto bad_reg;
127
if (irq < GIC_NR_SGIS) {
128
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
129
}
130
} else if (offset < 0x300) {
131
/* Interrupt Clear Pending. */
132
- irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
133
+ irq = (offset - 0x280) * 8;
134
if (irq >= s->num_irq)
135
goto bad_reg;
136
if (irq < GIC_NR_SGIS) {
137
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
138
goto bad_reg;
139
}
140
141
- irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
142
+ irq = (offset - 0x300) * 8;
143
if (irq >= s->num_irq) {
144
goto bad_reg;
145
}
146
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
147
goto bad_reg;
148
}
149
150
- irq = (offset - 0x380) * 8 + GIC_BASE_IRQ;
151
+ irq = (offset - 0x380) * 8;
152
if (irq >= s->num_irq) {
153
goto bad_reg;
154
}
155
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
156
}
157
} else if (offset < 0x800) {
158
/* Interrupt Priority. */
159
- irq = (offset - 0x400) + GIC_BASE_IRQ;
160
+ irq = (offset - 0x400);
161
if (irq >= s->num_irq)
162
goto bad_reg;
163
gic_dist_set_priority(s, cpu, irq, value, attrs);
164
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
165
* annoying exception of the 11MPCore's GIC.
166
*/
167
if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
168
- irq = (offset - 0x800) + GIC_BASE_IRQ;
169
+ irq = (offset - 0x800);
170
if (irq >= s->num_irq) {
171
goto bad_reg;
172
}
173
@@ -XXX,XX +XXX,XX @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
174
}
175
} else if (offset < 0xf00) {
176
/* Interrupt Configuration. */
177
- irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
178
+ irq = (offset - 0xc00) * 4;
179
if (irq >= s->num_irq)
180
goto bad_reg;
181
if (irq < GIC_NR_SGIS)
182
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
183
index XXXXXXX..XXXXXXX 100644
184
--- a/hw/intc/arm_gic_common.c
185
+++ b/hw/intc/arm_gic_common.c
186
@@ -XXX,XX +XXX,XX @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
187
s->num_cpu, GIC_NCPU);
188
return;
189
}
190
- s->num_irq += GIC_BASE_IRQ;
191
if (s->num_irq > GIC_MAXIRQ) {
192
error_setg(errp,
193
"requested %u interrupt lines exceeds GIC maximum %d",
54
--
194
--
55
2.17.1
195
2.19.0
56
196
57
197
diff view generated by jsdifflib
New patch
1
1
Convert the pcnet-pci device away from using the old_mmio
2
MemoryRegionOps accessor functions.
3
4
This commit is a no-behaviour-change API conversion.
5
(Since PCNET_PNPMMIO_SIZE is 0x20, the old "addr & 0x10"
6
check and the new "addr < 0x10" check are exact opposites;
7
the new code is phrased to be parallel with the
8
pcnet_io_read/write functions.)
9
10
I have left a TODO comment marker because the similarity
11
between the MMIO and IO accessor behaviour is suspicious
12
and they could be combined, but this will be left to a
13
different patch.
14
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/net/pcnet-pci.c | 133 ++++++++++++++++++--------------------------
19
hw/net/trace-events | 8 +--
20
2 files changed, 57 insertions(+), 84 deletions(-)
21
22
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/hw/net/pcnet-pci.c
25
+++ b/hw/net/pcnet-pci.c
26
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pcnet_io_ops = {
27
.endianness = DEVICE_LITTLE_ENDIAN,
28
};
29
30
-static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
31
+/*
32
+ * TODO: should MMIO accesses to the addresses corresponding to the
33
+ * APROM also honour the BCR_DWIO() setting? If so, then these functions
34
+ * and pcnet_ioport_write/pcnet_ioport_read could be merged.
35
+ * If not, then should pcnet_ioport_{read,write}{w,l} really check
36
+ * BCR_DWIO() for MMIO writes ?
37
+ */
38
+static void pcnet_mmio_write(void *opaque, hwaddr addr, uint64_t value,
39
+ unsigned size)
40
{
41
PCNetState *d = opaque;
42
43
- trace_pcnet_mmio_writeb(opaque, addr, val);
44
- if (!(addr & 0x10))
45
- pcnet_aprom_writeb(d, addr & 0x0f, val);
46
-}
47
+ trace_pcnet_mmio_write(opaque, addr, size, val);
48
49
-static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
50
-{
51
- PCNetState *d = opaque;
52
- uint32_t val = -1;
53
-
54
- if (!(addr & 0x10))
55
- val = pcnet_aprom_readb(d, addr & 0x0f);
56
- trace_pcnet_mmio_readb(opaque, addr, val);
57
- return val;
58
-}
59
-
60
-static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
61
-{
62
- PCNetState *d = opaque;
63
-
64
- trace_pcnet_mmio_writew(opaque, addr, val);
65
- if (addr & 0x10)
66
- pcnet_ioport_writew(d, addr & 0x0f, val);
67
- else {
68
- addr &= 0x0f;
69
- pcnet_aprom_writeb(d, addr, val & 0xff);
70
- pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
71
+ if (addr < 0x10) {
72
+ if (size == 1) {
73
+ pcnet_aprom_writeb(d, addr, data);
74
+ } else if ((addr & 1) == 0 && size == 2) {
75
+ pcnet_aprom_writeb(d, addr, data & 0xff);
76
+ pcnet_aprom_writeb(d, addr + 1, data >> 8);
77
+ } else if ((addr & 3) == 0 && size == 4) {
78
+ pcnet_aprom_writeb(d, addr, data & 0xff);
79
+ pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
80
+ pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
81
+ pcnet_aprom_writeb(d, addr + 3, data >> 24);
82
+ }
83
+ } else {
84
+ if (size == 2) {
85
+ pcnet_ioport_writew(d, addr, data);
86
+ } else if (size == 4) {
87
+ pcnet_ioport_writel(d, addr, data);
88
+ }
89
}
90
}
91
92
-static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
93
-{
94
- PCNetState *d = opaque;
95
- uint32_t val = -1;
96
-
97
- if (addr & 0x10)
98
- val = pcnet_ioport_readw(d, addr & 0x0f);
99
- else {
100
- addr &= 0x0f;
101
- val = pcnet_aprom_readb(d, addr+1);
102
- val <<= 8;
103
- val |= pcnet_aprom_readb(d, addr);
104
- }
105
- trace_pcnet_mmio_readw(opaque, addr, val);
106
- return val;
107
-}
108
-
109
-static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
110
+static uint64_t pcnet_mmio_read(void *opque, hwaddr addr, unsigned size)
111
{
112
PCNetState *d = opaque;
113
114
- trace_pcnet_mmio_writel(opaque, addr, val);
115
- if (addr & 0x10)
116
- pcnet_ioport_writel(d, addr & 0x0f, val);
117
- else {
118
- addr &= 0x0f;
119
- pcnet_aprom_writeb(d, addr, val & 0xff);
120
- pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
121
- pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
122
- pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
123
- }
124
-}
125
+ trace_pcnet_ioport_read(opaque, addr, size);
126
127
-static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
128
-{
129
- PCNetState *d = opaque;
130
- uint32_t val;
131
-
132
- if (addr & 0x10)
133
- val = pcnet_ioport_readl(d, addr & 0x0f);
134
- else {
135
- addr &= 0x0f;
136
- val = pcnet_aprom_readb(d, addr+3);
137
- val <<= 8;
138
- val |= pcnet_aprom_readb(d, addr+2);
139
- val <<= 8;
140
- val |= pcnet_aprom_readb(d, addr+1);
141
- val <<= 8;
142
- val |= pcnet_aprom_readb(d, addr);
143
+ if (addr < 0x10) {
144
+ if (size == 1) {
145
+ return pcnet_aprom_readb(d, addr);
146
+ } else if ((addr & 1) == 0 && size == 2) {
147
+ return pcnet_aprom_readb(d, addr) |
148
+ (pcnet_aprom_readb(d, addr + 1) << 8);
149
+ } else if ((addr & 3) == 0 && size == 4) {
150
+ return pcnet_aprom_readb(d, addr) |
151
+ (pcnet_aprom_readb(d, addr + 1) << 8) |
152
+ (pcnet_aprom_readb(d, addr + 2) << 16) |
153
+ (pcnet_aprom_readb(d, addr + 3) << 24);
154
+ }
155
+ } else {
156
+ if (size == 2) {
157
+ return pcnet_ioport_readw(d, addr);
158
+ } else if (size == 4) {
159
+ return pcnet_ioport_readl(d, addr);
160
+ }
161
}
162
- trace_pcnet_mmio_readl(opaque, addr, val);
163
- return val;
164
+ return ((uint64_t)1 << (size * 8)) - 1;
165
}
166
167
static const VMStateDescription vmstate_pci_pcnet = {
168
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pci_pcnet = {
169
/* PCI interface */
170
171
static const MemoryRegionOps pcnet_mmio_ops = {
172
- .old_mmio = {
173
- .read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
174
- .write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
175
- },
176
+ .read = pcnet_mmio_read,
177
+ .write = pcnet_mmio_write,
178
+ .valid.min_access_size = 1,
179
+ .valid.max_access_size = 4,
180
+ .impl.min_access_size = 1,
181
+ .impl.max_access_size = 4,
182
.endianness = DEVICE_LITTLE_ENDIAN,
183
};
184
185
diff --git a/hw/net/trace-events b/hw/net/trace-events
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/net/trace-events
188
+++ b/hw/net/trace-events
189
@@ -XXX,XX +XXX,XX @@ pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x
190
pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x"
191
pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
192
pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d"
193
-pcnet_mmio_writeb(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
194
-pcnet_mmio_writew(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
195
-pcnet_mmio_writel(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
196
-pcnet_mmio_readb(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
197
-pcnet_mmio_readw(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
198
-pcnet_mmio_readl(void *opaque, uint64_t addr, uint32_t val) "opaque=%p addr=0x%"PRIx64" val=0x%x"
199
+pcnet_mmio_write(void *opaque, uint64_t addr, uint32_t val, unsigned size) "opaque=%p addr=0x%"PRIx64" val=0x%x size=%d"
200
+pcnet_mmio_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
201
202
# hw/net/net_rx_pkt.c
203
net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu"
204
--
205
2.19.0
206
207
diff view generated by jsdifflib
New patch
1
The only difference between our implementation of the pcnet ioport
2
accessors and the mmio accessors is that the former check BCR_DWIO to
3
see what access widths are permitted for addresses in the aprom range
4
(0x0..0xf). In fact our failure to do this in the mmio accessors
5
is a bug (one which was fixed for the ioport accessors in
6
commit 7ba79741970 in 2011).
1
7
8
The data sheet for the Am79C970A does not describe the DWIO
9
bit as only applying for I/O space mapped I/O resources and
10
not memory mapped I/O resources, and our MMIO accessors already
11
honour DWIO for accesses in the 0x10..0x1f range (since the
12
pcnet_ioport_{read,write}{w,l} functions check it).
13
14
The data sheet for the later but compatible Am79C976 is clearer:
15
it states specifically "DWIO mode applies to both I/O- and
16
memory-mapped acceses." This seems to be reasonable evidence
17
in favour of interpretating the Am79C970A spec as being the same.
18
19
(NB: Linux's pcnet driver only supports I/O accesses, so the
20
MMIO access part of this device is probably untested anyway.)
21
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
hw/net/pcnet-pci.c | 67 ++-------------------------------------------
26
hw/net/trace-events | 2 --
27
2 files changed, 2 insertions(+), 67 deletions(-)
28
29
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/net/pcnet-pci.c
32
+++ b/hw/net/pcnet-pci.c
33
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pcnet_io_ops = {
34
.endianness = DEVICE_LITTLE_ENDIAN,
35
};
36
37
-/*
38
- * TODO: should MMIO accesses to the addresses corresponding to the
39
- * APROM also honour the BCR_DWIO() setting? If so, then these functions
40
- * and pcnet_ioport_write/pcnet_ioport_read could be merged.
41
- * If not, then should pcnet_ioport_{read,write}{w,l} really check
42
- * BCR_DWIO() for MMIO writes ?
43
- */
44
-static void pcnet_mmio_write(void *opaque, hwaddr addr, uint64_t value,
45
- unsigned size)
46
-{
47
- PCNetState *d = opaque;
48
-
49
- trace_pcnet_mmio_write(opaque, addr, size, val);
50
-
51
- if (addr < 0x10) {
52
- if (size == 1) {
53
- pcnet_aprom_writeb(d, addr, data);
54
- } else if ((addr & 1) == 0 && size == 2) {
55
- pcnet_aprom_writeb(d, addr, data & 0xff);
56
- pcnet_aprom_writeb(d, addr + 1, data >> 8);
57
- } else if ((addr & 3) == 0 && size == 4) {
58
- pcnet_aprom_writeb(d, addr, data & 0xff);
59
- pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
60
- pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
61
- pcnet_aprom_writeb(d, addr + 3, data >> 24);
62
- }
63
- } else {
64
- if (size == 2) {
65
- pcnet_ioport_writew(d, addr, data);
66
- } else if (size == 4) {
67
- pcnet_ioport_writel(d, addr, data);
68
- }
69
- }
70
-}
71
-
72
-static uint64_t pcnet_mmio_read(void *opque, hwaddr addr, unsigned size)
73
-{
74
- PCNetState *d = opaque;
75
-
76
- trace_pcnet_ioport_read(opaque, addr, size);
77
-
78
- if (addr < 0x10) {
79
- if (size == 1) {
80
- return pcnet_aprom_readb(d, addr);
81
- } else if ((addr & 1) == 0 && size == 2) {
82
- return pcnet_aprom_readb(d, addr) |
83
- (pcnet_aprom_readb(d, addr + 1) << 8);
84
- } else if ((addr & 3) == 0 && size == 4) {
85
- return pcnet_aprom_readb(d, addr) |
86
- (pcnet_aprom_readb(d, addr + 1) << 8) |
87
- (pcnet_aprom_readb(d, addr + 2) << 16) |
88
- (pcnet_aprom_readb(d, addr + 3) << 24);
89
- }
90
- } else {
91
- if (size == 2) {
92
- return pcnet_ioport_readw(d, addr);
93
- } else if (size == 4) {
94
- return pcnet_ioport_readl(d, addr);
95
- }
96
- }
97
- return ((uint64_t)1 << (size * 8)) - 1;
98
-}
99
-
100
static const VMStateDescription vmstate_pci_pcnet = {
101
.name = "pcnet",
102
.version_id = 3,
103
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pci_pcnet = {
104
/* PCI interface */
105
106
static const MemoryRegionOps pcnet_mmio_ops = {
107
- .read = pcnet_mmio_read,
108
- .write = pcnet_mmio_write,
109
+ .read = pcnet_ioport_read,
110
+ .write = pcnet_ioport_write,
111
.valid.min_access_size = 1,
112
.valid.max_access_size = 4,
113
.impl.min_access_size = 1,
114
diff --git a/hw/net/trace-events b/hw/net/trace-events
115
index XXXXXXX..XXXXXXX 100644
116
--- a/hw/net/trace-events
117
+++ b/hw/net/trace-events
118
@@ -XXX,XX +XXX,XX @@ pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x
119
pcnet_aprom_readb(void *opaque, uint32_t addr, uint32_t val) "opaque=%p addr=0x%08x val=0x%02x"
120
pcnet_ioport_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
121
pcnet_ioport_write(void *opaque, uint64_t addr, uint64_t data, unsigned size) "opaque=%p addr=0x%"PRIx64" data=0x%"PRIx64" size=%d"
122
-pcnet_mmio_write(void *opaque, uint64_t addr, uint32_t val, unsigned size) "opaque=%p addr=0x%"PRIx64" val=0x%x size=%d"
123
-pcnet_mmio_read(void *opaque, uint64_t addr, unsigned size) "opaque=%p addr=0x%"PRIx64" size=%d"
124
125
# hw/net/net_rx_pkt.c
126
net_rx_pkt_parsed(bool ip4, bool ip6, bool udp, bool tcp, size_t l3o, size_t l4o, size_t l5o) "RX packet parsed: ip4: %d, ip6: %d, udp: %d, tcp: %d, l3 offset: %zu, l4 offset: %zu, l5 offset: %zu"
127
--
128
2.19.0
129
130
diff view generated by jsdifflib
New patch
1
Add 'break' statements missing from a switch in the APB dual-timer
2
write function. Spotted by Coverity as CID 1395626 and 1395633.
1
3
4
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180924123122.14549-1-peter.maydell@linaro.org
8
---
9
hw/timer/cmsdk-apb-dualtimer.c | 2 ++
10
1 file changed, 2 insertions(+)
11
12
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/timer/cmsdk-apb-dualtimer.c
15
+++ b/hw/timer/cmsdk-apb-dualtimer.c
16
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwaddr offset,
17
case A_TIMERITCR:
18
s->timeritcr = value & R_TIMERITCR_VALID_MASK;
19
cmsdk_apb_dualtimer_update(s);
20
+ break;
21
case A_TIMERITOP:
22
s->timeritop = value & R_TIMERITOP_VALID_MASK;
23
cmsdk_apb_dualtimer_update(s);
24
+ break;
25
default:
26
bad_offset:
27
qemu_log_mask(LOG_GUEST_ERROR,
28
--
29
2.19.0
30
31
diff view generated by jsdifflib
1
commit b08199c6fbea1 accidentally added a reference to a doc
1
From: Cédric Le Goater <clg@kaod.org>
2
comment to a nonexistent memory_region_allocate_aux_memory().
3
This was a leftover from a previous version of the patchset
4
which defined memory_region_allocate_aux_memory() for
5
"allocate RAM MemoryRegion and register it for migration"
6
and left "memory_region_init_ram()" with its original semantics
7
of "allocate RAM MR but do not register for migration". In
8
the end we decided on the approach of "memory_region_init_ram()
9
registers the MR for migration, and memory_region_init_ram_nomigrate()
10
is a new function which does not", but this comment change
11
got left in by mistake. Revert that part of the commit.
12
2
13
Reported-by: Thomas Huth <huth@tuxfamily.org>
3
In file included from /home/thuth/devel/qemu/hw/timer/aspeed_timer.c:16:
4
/home/thuth/devel/qemu/include/hw/misc/aspeed_scu.h:37:3: error:
5
redefinition of typedef 'AspeedSCUState' is a C11 feature
6
[-Werror,-Wtypedef-redefinition]
7
} AspeedSCUState;
8
^
9
/home/thuth/devel/qemu/include/hw/timer/aspeed_timer.h:27:31: note:
10
previous definition is here
11
typedef struct AspeedSCUState AspeedSCUState;
12
13
Reported-by: Thomas Huth <thuth@redhat.com>
14
Signed-off-by: Cédric Le Goater <clg@kaod.org>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20180921161939.822-2-clg@kaod.org
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20180702130605.13611-1-peter.maydell@linaro.org
16
---
19
---
17
include/hw/boards.h | 3 +--
20
include/hw/timer/aspeed_timer.h | 3 +--
18
1 file changed, 1 insertion(+), 2 deletions(-)
21
hw/timer/aspeed_timer.c | 1 -
22
2 files changed, 1 insertion(+), 3 deletions(-)
19
23
20
diff --git a/include/hw/boards.h b/include/hw/boards.h
24
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
21
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/boards.h
26
--- a/include/hw/timer/aspeed_timer.h
23
+++ b/include/hw/boards.h
27
+++ b/include/hw/timer/aspeed_timer.h
24
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
25
*
29
#define ASPEED_TIMER_H
26
* Smaller pieces of memory (display RAM, static RAMs, etc) don't need
30
27
* to be backed via the -mem-path memory backend and can simply
31
#include "qemu/timer.h"
28
- * be created via memory_region_allocate_aux_memory() or
32
-
29
- * memory_region_init_ram().
33
-typedef struct AspeedSCUState AspeedSCUState;
30
+ * be created via memory_region_init_ram().
34
+#include "hw/misc/aspeed_scu.h"
31
*/
35
32
void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner,
36
#define ASPEED_TIMER(obj) \
33
const char *name,
37
OBJECT_CHECK(AspeedTimerCtrlState, (obj), TYPE_ASPEED_TIMER);
38
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/timer/aspeed_timer.c
41
+++ b/hw/timer/aspeed_timer.c
42
@@ -XXX,XX +XXX,XX @@
43
#include "qapi/error.h"
44
#include "hw/sysbus.h"
45
#include "hw/timer/aspeed_timer.h"
46
-#include "hw/misc/aspeed_scu.h"
47
#include "qemu-common.h"
48
#include "qemu/bitops.h"
49
#include "qemu/timer.h"
34
--
50
--
35
2.17.1
51
2.19.0
36
52
37
53
diff view generated by jsdifflib
1
Currently we use memory_region_init_rom_nomigrate() to create
1
From: Cédric Le Goater <clg@kaod.org>
2
the "dp3893x-prom" memory region, and we don't manually register
3
it with vmstate_register_ram(). This currently means that its
4
contents are migrated but as a ram block whose name is the empty
5
string; in future it may mean they are not migrated at all. Use
6
memory_region_init_ram() instead.
7
2
8
Note that this is a a cross-version migration compatibility break
3
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit
9
for the MIPS "magnum" and "pica61" machines.
4
to make the chip operate in 4 Byte address mode at power up. This
5
should be an interesting feature to model as it will exercise a bit
6
more the SMC controllers and MMIO execution at boot time.
10
7
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
9
Message-id: 20180921161939.822-3-clg@kaod.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Aleksandar Markovic <aleksandar.markovic@wavecomp.com>
13
Message-id: 20180706174309.27110-1-peter.maydell@linaro.org
14
---
12
---
15
hw/net/dp8393x.c | 2 +-
13
hw/arm/aspeed.c | 2 +-
16
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
17
15
18
diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c
16
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/net/dp8393x.c
18
--- a/hw/arm/aspeed.c
21
+++ b/hw/net/dp8393x.c
19
+++ b/hw/arm/aspeed.c
22
@@ -XXX,XX +XXX,XX @@ static void dp8393x_realize(DeviceState *dev, Error **errp)
20
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
23
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
21
[AST2500_EVB] = {
24
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
22
.soc_name = "ast2500-a1",
25
23
.hw_strap1 = AST2500_EVB_HW_STRAP1,
26
- memory_region_init_ram_nomigrate(&s->prom, OBJECT(dev),
24
- .fmc_model = "n25q256a",
27
+ memory_region_init_ram(&s->prom, OBJECT(dev),
25
+ .fmc_model = "w25q256",
28
"dp8393x-prom", SONIC_PROM_SIZE, &local_err);
26
.spi_model = "mx25l25635e",
29
if (local_err) {
27
.num_cs = 1,
30
error_propagate(errp, local_err);
28
.i2c_init = ast2500_evb_i2c_init,
31
--
29
--
32
2.17.1
30
2.19.0
33
31
34
32
diff view generated by jsdifflib
New patch
1
1
From: Cédric Le Goater <clg@kaod.org>
2
3
The code looks better, it removes duplicated lines and it will ease
4
the introduction of common properties for the Aspeed machines.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20180921161939.822-4-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/aspeed.h | 46 +++++++++
12
hw/arm/aspeed.c | 212 +++++++++++++---------------------------
13
2 files changed, 116 insertions(+), 142 deletions(-)
14
create mode 100644 include/hw/arm/aspeed.h
15
16
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
17
new file mode 100644
18
index XXXXXXX..XXXXXXX
19
--- /dev/null
20
+++ b/include/hw/arm/aspeed.h
21
@@ -XXX,XX +XXX,XX @@
22
+/*
23
+ * Aspeed Machines
24
+ *
25
+ * Copyright 2018 IBM Corp.
26
+ *
27
+ * This code is licensed under the GPL version 2 or later. See
28
+ * the COPYING file in the top-level directory.
29
+ */
30
+#ifndef ARM_ASPEED_H
31
+#define ARM_ASPEED_H
32
+
33
+#include "hw/boards.h"
34
+
35
+typedef struct AspeedBoardState AspeedBoardState;
36
+
37
+typedef struct AspeedBoardConfig {
38
+ const char *name;
39
+ const char *desc;
40
+ const char *soc_name;
41
+ uint32_t hw_strap1;
42
+ const char *fmc_model;
43
+ const char *spi_model;
44
+ uint32_t num_cs;
45
+ void (*i2c_init)(AspeedBoardState *bmc);
46
+} AspeedBoardConfig;
47
+
48
+#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
49
+#define ASPEED_MACHINE(obj) \
50
+ OBJECT_CHECK(AspeedMachine, (obj), TYPE_ASPEED_MACHINE)
51
+
52
+typedef struct AspeedMachine {
53
+ MachineState parent_obj;
54
+} AspeedMachine;
55
+
56
+#define ASPEED_MACHINE_CLASS(klass) \
57
+ OBJECT_CLASS_CHECK(AspeedMachineClass, (klass), TYPE_ASPEED_MACHINE)
58
+#define ASPEED_MACHINE_GET_CLASS(obj) \
59
+ OBJECT_GET_CLASS(AspeedMachineClass, (obj), TYPE_ASPEED_MACHINE)
60
+
61
+typedef struct AspeedMachineClass {
62
+ MachineClass parent_obj;
63
+ const AspeedBoardConfig *board;
64
+} AspeedMachineClass;
65
+
66
+
67
+#endif
68
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/hw/arm/aspeed.c
71
+++ b/hw/arm/aspeed.c
72
@@ -XXX,XX +XXX,XX @@
73
#include "cpu.h"
74
#include "exec/address-spaces.h"
75
#include "hw/arm/arm.h"
76
+#include "hw/arm/aspeed.h"
77
#include "hw/arm/aspeed_soc.h"
78
#include "hw/boards.h"
79
#include "hw/i2c/smbus.h"
80
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardState {
81
MemoryRegion max_ram;
82
} AspeedBoardState;
83
84
-typedef struct AspeedBoardConfig {
85
- const char *soc_name;
86
- uint32_t hw_strap1;
87
- const char *fmc_model;
88
- const char *spi_model;
89
- uint32_t num_cs;
90
- void (*i2c_init)(AspeedBoardState *bmc);
91
-} AspeedBoardConfig;
92
-
93
-enum {
94
- PALMETTO_BMC,
95
- AST2500_EVB,
96
- ROMULUS_BMC,
97
- WITHERSPOON_BMC,
98
-};
99
-
100
/* Palmetto hardware value: 0x120CE416 */
101
#define PALMETTO_BMC_HW_STRAP1 ( \
102
SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
103
@@ -XXX,XX +XXX,XX @@ enum {
104
/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
105
#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
106
107
-static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
108
-static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
109
-static void romulus_bmc_i2c_init(AspeedBoardState *bmc);
110
-static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc);
111
-
112
-static const AspeedBoardConfig aspeed_boards[] = {
113
- [PALMETTO_BMC] = {
114
- .soc_name = "ast2400-a1",
115
- .hw_strap1 = PALMETTO_BMC_HW_STRAP1,
116
- .fmc_model = "n25q256a",
117
- .spi_model = "mx25l25635e",
118
- .num_cs = 1,
119
- .i2c_init = palmetto_bmc_i2c_init,
120
- },
121
- [AST2500_EVB] = {
122
- .soc_name = "ast2500-a1",
123
- .hw_strap1 = AST2500_EVB_HW_STRAP1,
124
- .fmc_model = "w25q256",
125
- .spi_model = "mx25l25635e",
126
- .num_cs = 1,
127
- .i2c_init = ast2500_evb_i2c_init,
128
- },
129
- [ROMULUS_BMC] = {
130
- .soc_name = "ast2500-a1",
131
- .hw_strap1 = ROMULUS_BMC_HW_STRAP1,
132
- .fmc_model = "n25q256a",
133
- .spi_model = "mx66l1g45g",
134
- .num_cs = 2,
135
- .i2c_init = romulus_bmc_i2c_init,
136
- },
137
- [WITHERSPOON_BMC] = {
138
- .soc_name = "ast2500-a1",
139
- .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
140
- .fmc_model = "mx25l25635e",
141
- .spi_model = "mx66l1g45g",
142
- .num_cs = 2,
143
- .i2c_init = witherspoon_bmc_i2c_init,
144
- },
145
-};
146
-
147
/*
148
* The max ram region is for firmwares that scan the address space
149
* with load/store to guess how much RAM the SoC has.
150
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
151
object_property_set_int(OBJECT(dev), 110000, "temperature3", &error_abort);
152
}
153
154
-static void palmetto_bmc_init(MachineState *machine)
155
-{
156
- aspeed_board_init(machine, &aspeed_boards[PALMETTO_BMC]);
157
-}
158
-
159
-static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
160
-{
161
- MachineClass *mc = MACHINE_CLASS(oc);
162
-
163
- mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
164
- mc->init = palmetto_bmc_init;
165
- mc->max_cpus = 1;
166
- mc->no_sdcard = 1;
167
- mc->no_floppy = 1;
168
- mc->no_cdrom = 1;
169
- mc->no_parallel = 1;
170
-}
171
-
172
-static const TypeInfo palmetto_bmc_type = {
173
- .name = MACHINE_TYPE_NAME("palmetto-bmc"),
174
- .parent = TYPE_MACHINE,
175
- .class_init = palmetto_bmc_class_init,
176
-};
177
-
178
static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
179
{
180
AspeedSoCState *soc = &bmc->soc;
181
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
182
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
183
}
184
185
-static void ast2500_evb_init(MachineState *machine)
186
-{
187
- aspeed_board_init(machine, &aspeed_boards[AST2500_EVB]);
188
-}
189
-
190
-static void ast2500_evb_class_init(ObjectClass *oc, void *data)
191
-{
192
- MachineClass *mc = MACHINE_CLASS(oc);
193
-
194
- mc->desc = "Aspeed AST2500 EVB (ARM1176)";
195
- mc->init = ast2500_evb_init;
196
- mc->max_cpus = 1;
197
- mc->no_sdcard = 1;
198
- mc->no_floppy = 1;
199
- mc->no_cdrom = 1;
200
- mc->no_parallel = 1;
201
-}
202
-
203
-static const TypeInfo ast2500_evb_type = {
204
- .name = MACHINE_TYPE_NAME("ast2500-evb"),
205
- .parent = TYPE_MACHINE,
206
- .class_init = ast2500_evb_class_init,
207
-};
208
-
209
static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
210
{
211
AspeedSoCState *soc = &bmc->soc;
212
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
213
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
214
}
215
216
-static void romulus_bmc_init(MachineState *machine)
217
-{
218
- aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]);
219
-}
220
-
221
-static void romulus_bmc_class_init(ObjectClass *oc, void *data)
222
-{
223
- MachineClass *mc = MACHINE_CLASS(oc);
224
-
225
- mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
226
- mc->init = romulus_bmc_init;
227
- mc->max_cpus = 1;
228
- mc->no_sdcard = 1;
229
- mc->no_floppy = 1;
230
- mc->no_cdrom = 1;
231
- mc->no_parallel = 1;
232
-}
233
-
234
-static const TypeInfo romulus_bmc_type = {
235
- .name = MACHINE_TYPE_NAME("romulus-bmc"),
236
- .parent = TYPE_MACHINE,
237
- .class_init = romulus_bmc_class_init,
238
-};
239
-
240
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
241
{
242
AspeedSoCState *soc = &bmc->soc;
243
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
244
0x60);
245
}
246
247
-static void witherspoon_bmc_init(MachineState *machine)
248
+static void aspeed_machine_init(MachineState *machine)
249
{
250
- aspeed_board_init(machine, &aspeed_boards[WITHERSPOON_BMC]);
251
+ AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
252
+
253
+ aspeed_board_init(machine, amc->board);
254
}
255
256
-static void witherspoon_bmc_class_init(ObjectClass *oc, void *data)
257
+static void aspeed_machine_class_init(ObjectClass *oc, void *data)
258
{
259
MachineClass *mc = MACHINE_CLASS(oc);
260
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
261
+ const AspeedBoardConfig *board = data;
262
263
- mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
264
- mc->init = witherspoon_bmc_init;
265
+ mc->desc = board->desc;
266
+ mc->init = aspeed_machine_init;
267
mc->max_cpus = 1;
268
mc->no_sdcard = 1;
269
mc->no_floppy = 1;
270
mc->no_cdrom = 1;
271
mc->no_parallel = 1;
272
+ amc->board = board;
273
}
274
275
-static const TypeInfo witherspoon_bmc_type = {
276
- .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
277
+static const TypeInfo aspeed_machine_type = {
278
+ .name = TYPE_ASPEED_MACHINE,
279
.parent = TYPE_MACHINE,
280
- .class_init = witherspoon_bmc_class_init,
281
+ .instance_size = sizeof(AspeedMachine),
282
+ .class_size = sizeof(AspeedMachineClass),
283
+ .abstract = true,
284
};
285
286
-static void aspeed_machine_init(void)
287
+static const AspeedBoardConfig aspeed_boards[] = {
288
+ {
289
+ .name = MACHINE_TYPE_NAME("palmetto-bmc"),
290
+ .desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)",
291
+ .soc_name = "ast2400-a1",
292
+ .hw_strap1 = PALMETTO_BMC_HW_STRAP1,
293
+ .fmc_model = "n25q256a",
294
+ .spi_model = "mx25l25635e",
295
+ .num_cs = 1,
296
+ .i2c_init = palmetto_bmc_i2c_init,
297
+ }, {
298
+ .name = MACHINE_TYPE_NAME("ast2500-evb"),
299
+ .desc = "Aspeed AST2500 EVB (ARM1176)",
300
+ .soc_name = "ast2500-a1",
301
+ .hw_strap1 = AST2500_EVB_HW_STRAP1,
302
+ .fmc_model = "w25q256",
303
+ .spi_model = "mx25l25635e",
304
+ .num_cs = 1,
305
+ .i2c_init = ast2500_evb_i2c_init,
306
+ }, {
307
+ .name = MACHINE_TYPE_NAME("romulus-bmc"),
308
+ .desc = "OpenPOWER Romulus BMC (ARM1176)",
309
+ .soc_name = "ast2500-a1",
310
+ .hw_strap1 = ROMULUS_BMC_HW_STRAP1,
311
+ .fmc_model = "n25q256a",
312
+ .spi_model = "mx66l1g45g",
313
+ .num_cs = 2,
314
+ .i2c_init = romulus_bmc_i2c_init,
315
+ }, {
316
+ .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
317
+ .desc = "OpenPOWER Witherspoon BMC (ARM1176)",
318
+ .soc_name = "ast2500-a1",
319
+ .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
320
+ .fmc_model = "mx25l25635e",
321
+ .spi_model = "mx66l1g45g",
322
+ .num_cs = 2,
323
+ .i2c_init = witherspoon_bmc_i2c_init,
324
+ },
325
+};
326
+
327
+static void aspeed_machine_types(void)
328
{
329
- type_register_static(&palmetto_bmc_type);
330
- type_register_static(&ast2500_evb_type);
331
- type_register_static(&romulus_bmc_type);
332
- type_register_static(&witherspoon_bmc_type);
333
+ int i;
334
+
335
+ type_register_static(&aspeed_machine_type);
336
+ for (i = 0; i < ARRAY_SIZE(aspeed_boards); ++i) {
337
+ TypeInfo ti = {
338
+ .name = aspeed_boards[i].name,
339
+ .parent = TYPE_ASPEED_MACHINE,
340
+ .class_init = aspeed_machine_class_init,
341
+ .class_data = (void *)&aspeed_boards[i],
342
+ };
343
+ type_register(&ti);
344
+ }
345
}
346
347
-type_init(aspeed_machine_init)
348
+type_init(aspeed_machine_types)
349
--
350
2.19.0
351
352
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Cédric Le Goater <clg@kaod.org>
2
2
3
Normally this is automatic in the size restrictions that are placed
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4
on vector sizes coming from the implementation. However, for the
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
legitimate size tuple [oprsz=8, maxsz=32], we need to clear the final
5
Message-id: 20180921161939.822-6-clg@kaod.org
6
24 bytes of the vector register. Without this check, do_dup selects
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
TCG_TYPE_V128 and clears only 16 bytes.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20180705191929.30773-2-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
8
---
15
tcg/tcg-op-gvec.c | 7 +++++--
9
hw/ssi/aspeed_smc.c | 8 ++++----
16
1 file changed, 5 insertions(+), 2 deletions(-)
10
1 file changed, 4 insertions(+), 4 deletions(-)
17
11
18
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
12
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
19
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
20
--- a/tcg/tcg-op-gvec.c
14
--- a/hw/ssi/aspeed_smc.c
21
+++ b/tcg/tcg-op-gvec.c
15
+++ b/hw/ssi/aspeed_smc.c
22
@@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
16
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
23
in units of LNSZ. This limits the expansion of inline code. */
17
static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
24
static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
18
uint64_t data, unsigned size)
25
{
19
{
26
- uint32_t lnct = oprsz / lnsz;
20
- qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
27
- return lnct >= 1 && lnct <= MAX_UNROLL;
21
- PRIx64 "\n", __func__, addr, size, data);
28
+ if (oprsz % lnsz == 0) {
22
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%"
29
+ uint32_t lnct = oprsz / lnsz;
23
+ PRIx64 "\n", __func__, addr, size, data);
30
+ return lnct >= 1 && lnct <= MAX_UNROLL;
31
+ }
32
+ return false;
33
}
24
}
34
25
35
static void expand_clr(uint32_t dofs, uint32_t maxsz);
26
static const MemoryRegionOps aspeed_smc_flash_default_ops = {
27
@@ -XXX,XX +XXX,XX @@ static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
28
*/
29
if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
30
for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
31
- ssi_transfer(fl->controller->spi, 0xFF);
32
+ ssi_transfer(fl->controller->spi, 0xFF);
33
}
34
}
35
}
36
@@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
37
}
38
39
static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
40
- unsigned size)
41
+ unsigned size)
42
{
43
AspeedSMCFlash *fl = opaque;
44
AspeedSMCState *s = fl->controller;
36
--
45
--
37
2.17.1
46
2.19.0
38
47
39
48
diff view generated by jsdifflib
1
The CMSDK timer behaviour is that an interrupt is triggered when the
1
The ARMv8 architecture defines that an AArch32 CPU starts
2
counter counts down from 1 to 0; however one is not triggered if the
2
in SVC mode, unless EL2 is the highest available EL, in
3
counter is manually set to 0 by a guest write to the counter register.
3
which case it starts in Hyp mode. (In ARMv7 a CPU with EL2
4
Currently ptimer can't handle this; add a policy option to allow
4
but not EL3 was not a valid configuration, but we don't
5
a ptimer user to request this behaviour.
5
specifically reject this if the user asks for one.)
6
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20180823135047.16525-1-peter.maydell@linaro.org
10
Message-id: 20180703171044.9503-2-peter.maydell@linaro.org
11
---
10
---
12
include/hw/ptimer.h | 9 +++++++++
11
target/arm/cpu.c | 14 ++++++++++++--
13
hw/core/ptimer.c | 22 +++++++++++++++++++++-
12
1 file changed, 12 insertions(+), 2 deletions(-)
14
tests/ptimer-test.c | 25 +++++++++++++++++++------
15
3 files changed, 49 insertions(+), 7 deletions(-)
16
13
17
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ptimer.h
16
--- a/target/arm/cpu.c
20
+++ b/include/hw/ptimer.h
17
+++ b/target/arm/cpu.c
21
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
22
* not the one less. */
19
env->cp15.c15_cpar = 1;
23
#define PTIMER_POLICY_NO_COUNTER_ROUND_DOWN (1 << 4)
24
25
+/*
26
+ * Starting to run with a zero counter, or setting the counter to "0" via
27
+ * ptimer_set_count() or ptimer_set_limit() will not trigger the timer
28
+ * (though it will cause a reload). Only a counter decrement to "0"
29
+ * will cause a trigger. Not compatible with NO_IMMEDIATE_TRIGGER;
30
+ * ptimer_init() will assert() that you don't set both.
31
+ */
32
+#define PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT (1 << 5)
33
+
34
/* ptimer.c */
35
typedef struct ptimer_state ptimer_state;
36
typedef void (*ptimer_cb)(void *opaque);
37
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/hw/core/ptimer.c
40
+++ b/hw/core/ptimer.c
41
@@ -XXX,XX +XXX,XX @@ static void ptimer_reload(ptimer_state *s, int delta_adjust)
42
uint32_t period_frac = s->period_frac;
43
uint64_t period = s->period;
44
uint64_t delta = s->delta;
45
+ bool suppress_trigger = false;
46
47
- if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
48
+ /*
49
+ * Note that if delta_adjust is 0 then we must be here because of
50
+ * a count register write or timer start, not because of timer expiry.
51
+ * In that case the policy might require us to suppress the timer trigger
52
+ * that we would otherwise generate for a zero delta.
53
+ */
54
+ if (delta_adjust == 0 &&
55
+ (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
56
+ suppress_trigger = true;
57
+ }
58
+ if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
59
+ && !suppress_trigger) {
60
ptimer_trigger(s);
61
}
20
}
62
21
#else
63
@@ -XXX,XX +XXX,XX @@ ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
22
- /* SVC mode with interrupts disabled. */
64
s->bh = bh;
23
- env->uncached_cpsr = ARM_CPU_MODE_SVC;
65
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
66
s->policy_mask = policy_mask;
67
+
24
+
68
+ /*
25
+ /*
69
+ * These two policies are incompatible -- trigger-on-decrement implies
26
+ * If the highest available EL is EL2, AArch32 will start in Hyp
70
+ * a timer trigger when the count becomes 0, but no-immediate-trigger
27
+ * mode; otherwise it starts in SVC. Note that if we start in
71
+ * implies a trigger when the count stops being 0.
28
+ * AArch64 then these values in the uncached_cpsr will be ignored.
72
+ */
29
+ */
73
+ assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
30
+ if (arm_feature(env, ARM_FEATURE_EL2) &&
74
+ (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
31
+ !arm_feature(env, ARM_FEATURE_EL3)) {
75
return s;
32
+ env->uncached_cpsr = ARM_CPU_MODE_HYP;
76
}
33
+ } else {
77
34
+ env->uncached_cpsr = ARM_CPU_MODE_SVC;
78
diff --git a/tests/ptimer-test.c b/tests/ptimer-test.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/tests/ptimer-test.c
81
+++ b/tests/ptimer-test.c
82
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
83
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
84
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
85
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
86
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
87
88
triggered = false;
89
90
@@ -XXX,XX +XXX,XX @@ static void check_periodic(gconstpointer arg)
91
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
92
no_immediate_reload ? 0 : 10);
93
94
- if (no_immediate_trigger) {
95
+ if (no_immediate_trigger || trig_only_on_dec) {
96
g_assert_false(triggered);
97
} else {
98
g_assert_true(triggered);
99
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
100
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
101
bool no_immediate_reload = (*policy & PTIMER_POLICY_NO_IMMEDIATE_RELOAD);
102
bool no_round_down = (*policy & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
103
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
104
105
triggered = false;
106
107
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
108
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
109
no_immediate_reload ? 0 : 99);
110
111
- if (no_immediate_trigger) {
112
+ if (no_immediate_trigger || trig_only_on_dec) {
113
g_assert_false(triggered);
114
} else {
115
g_assert_true(triggered);
116
@@ -XXX,XX +XXX,XX @@ static void check_run_with_delta_0(gconstpointer arg)
117
g_assert_cmpuint(ptimer_get_count(ptimer), ==,
118
no_immediate_reload ? 0 : 99);
119
120
- if (no_immediate_trigger) {
121
+ if (no_immediate_trigger || trig_only_on_dec) {
122
g_assert_false(triggered);
123
} else {
124
g_assert_true(triggered);
125
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
126
ptimer_state *ptimer = ptimer_init(bh, *policy);
127
bool continuous_trigger = (*policy & PTIMER_POLICY_CONTINUOUS_TRIGGER);
128
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
129
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
130
131
triggered = false;
132
133
@@ -XXX,XX +XXX,XX @@ static void check_periodic_with_load_0(gconstpointer arg)
134
135
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
136
137
- if (no_immediate_trigger) {
138
+ if (no_immediate_trigger || trig_only_on_dec) {
139
g_assert_false(triggered);
140
} else {
141
g_assert_true(triggered);
142
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
143
QEMUBH *bh = qemu_bh_new(ptimer_trigger, NULL);
144
ptimer_state *ptimer = ptimer_init(bh, *policy);
145
bool no_immediate_trigger = (*policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER);
146
+ bool trig_only_on_dec = (*policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT);
147
148
triggered = false;
149
150
@@ -XXX,XX +XXX,XX @@ static void check_oneshot_with_load_0(gconstpointer arg)
151
152
g_assert_cmpuint(ptimer_get_count(ptimer), ==, 0);
153
154
- if (no_immediate_trigger) {
155
+ if (no_immediate_trigger || trig_only_on_dec) {
156
g_assert_false(triggered);
157
} else {
158
g_assert_true(triggered);
159
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
160
g_strlcat(policy_name, "no_counter_rounddown,", 256);
161
}
162
163
+ if (policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) {
164
+ g_strlcat(policy_name, "trigger_only_on_decrement,", 256);
165
+ }
35
+ }
166
+
36
env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
167
g_test_add_data_func_full(
37
168
tmp = g_strdup_printf("/ptimer/set_count policy=%s", policy_name),
38
if (arm_feature(env, ARM_FEATURE_M)) {
169
g_memdup(&policy, 1), check_set_count, g_free);
170
@@ -XXX,XX +XXX,XX @@ static void add_ptimer_tests(uint8_t policy)
171
172
static void add_all_ptimer_policies_comb_tests(void)
173
{
174
- int last_policy = PTIMER_POLICY_NO_COUNTER_ROUND_DOWN;
175
+ int last_policy = PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT;
176
int policy = PTIMER_POLICY_DEFAULT;
177
178
for (; policy < (last_policy << 1); policy++) {
179
+ if ((policy & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
180
+ (policy & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
181
+ /* Incompatible policy flag settings -- don't try to test them */
182
+ continue;
183
+ }
184
add_ptimer_tests(policy);
185
}
186
}
187
--
39
--
188
2.17.1
40
2.19.0
189
41
190
42
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