Hello Peter,

Changes since Richards v3:
 - Brought into my queue
 - Fixed the format warnings the print_insn_or1k patch
 - Added RB's

Please consider for pull.

The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:

  tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)

are available in the Git repository at:

  git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702

for you to fetch changes up to 11d2bfa3429d32af4a0dc03af91646ea9e6a2b8c:

  target/openrisc: Fix writes to interrupt mask register (2018-07-02 22:31:59 +0900)

----------------------------------------------------------------
OpenRISC cleanups and Fixes for QEMU 3.0

Mostly patches from Richard Henderson fixing multiple things:
 * Fix singlestepping in GDB.
 * Use more TB linking.
 * Fixes to exit TB after updating SPRs to enable registering of state
   changes.
 * Significant optimizations and refactors to the TLB
 * Split out disassembly from translation.
 * Add qemu-or1k to qemu-binfmt-conf.sh.
 * Implement signal handling for linux-user.

Then there are a few fixups from me:
 * Fix delay slot detections to match hardware, this was masking a bug
   in the linus kernel.
 * Fix stores to the PIC mask register

----------------------------------------------------------------
Richard Henderson (23):
  target/openrisc: Fix mtspr shadow gprs
  target/openrisc: Add print_insn_or1k
  target/openrisc: Log interrupts
  target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
  target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
  target/openrisc: Fix singlestep_enabled
  target/openrisc: Link more translation blocks
  target/openrisc: Split out is_user
  target/openrisc: Exit the TB after l.mtspr
  target/openrisc: Form the spr index from tcg
  target/openrisc: Merge tlb allocation into CPUOpenRISCState
  target/openrisc: Remove indirect function calls for mmu
  target/openrisc: Merge mmu_helper.c into mmu.c
  target/openrisc: Reduce tlb to a single dimension
  target/openrisc: Fix tlb flushing in mtspr
  target/openrisc: Fix cpu_mmu_index
  target/openrisc: Use identical sizes for ITLB and DTLB
  target/openrisc: Stub out handle_mmu_fault for softmmu
  target/openrisc: Increase the TLB size
  target/openrisc: Reorg tlb lookup
  target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
  linux-user: Implement signals for openrisc
  linux-user: Fix struct sigaltstack for openrisc

Stafford Horne (2):
  target/openrisc: Fix delay slot exception flag to match spec
  target/openrisc: Fix writes to interrupt mask register

 linux-user/openrisc/signal.c         | 217 ++++++++-----------
 linux-user/openrisc/target_signal.h  |   2 +-
 linux-user/openrisc/target_syscall.h |  28 +--
 linux-user/signal.c                  |   2 +-
 scripts/qemu-binfmt-conf.sh          |  10 +-
 target/openrisc/Makefile.objs        |   5 +-
 target/openrisc/cpu.c                |  17 +-
 target/openrisc/cpu.h                |  61 +++---
 target/openrisc/disas.c              | 170 +++++++++++++++
 target/openrisc/helper.h             |   4 +-
 target/openrisc/interrupt.c          |  55 +++--
 target/openrisc/interrupt_helper.c   |  35 +---
 target/openrisc/machine.c            |  44 +---
 target/openrisc/mmu.c                | 279 +++++++++---------------
 target/openrisc/mmu_helper.c         |  40 ----
 target/openrisc/sys_helper.c         |  84 ++++----
 target/openrisc/translate.c          | 303 ++++++++++-----------------
 17 files changed, 603 insertions(+), 753 deletions(-)
 create mode 100644 target/openrisc/disas.c
 delete mode 100644 target/openrisc/mmu_helper.c

-- 
2.17.0

On Mon, Jul 02, 2018 at 10:57:41PM +0900, Stafford Horne wrote:
> Hello Peter,
> 
> Changes since Richards v3:
>  - Brought into my queue
>  - Fixed the format warnings the print_insn_or1k patch
>  - Added RB's
> 
> Please consider for pull.

Please hold.

Sorry, Richard found one issue with a checkpatch fix I did.  Respinning this.

-Stafford

Stafford Horne <shorne@gmail.com> writes:

<snip>
> ----------------------------------------------------------------
> OpenRISC cleanups and Fixes for QEMU 3.0

In the interests of getting the tests/tcg/openrisc stuff up and running
again could you tell me if there are any distros that currently package
the or1k compilers as cross compilers?

Out of interest what do you develop/test on?

--
Alex Bennée

Hello Alex,

On Tue, Jul 3, 2018, 12:34 AM Alex Bennée <alex.bennee@linaro.org> wrote:

>
> Stafford Horne <shorne@gmail.com> writes:
>
> <snip>
> > ----------------------------------------------------------------
> > OpenRISC cleanups and Fixes for QEMU 3.0
>
> In the interests of getting the tests/tcg/openrisc stuff up and running
> again could you tell me if there are any distros that currently package
> the or1k compilers as cross compilers?
>

There are no distros, there is/was a copyright issue with the old gcc
toolchain.  However, that should be fixed now as I and Richard did a
cleanroom rewrite of the gcc backend for openrisc meaning we should be able
upstream after we sort out the last bugs.  I believe distros would be able
to pick it up after that.

Many of these fixes in this series were find during the compiler testing.

I use binaries I built here:

https://github.com/stffrdhrn/gcc/releases/tag/or1k-9.0.0-20180613

Perhaps you can use those?

Out of interest what do you develop/test on?
>

I test on Fedora 27 or so.  As mentioned above with my own toolchain.

-Stafford

>