Sai Pavan Boddu (1):

xilinx_spips: Make dma transactions as per dma_burst_size

accel/tcg/softmmu_template.h | 24 ++-

hw/arm/smmuv3-internal.h | 12 +-

include/exec/cpu-all.h | 5 +-

include/hw/arm/omap.h | 30 +--

include/hw/arm/smmu-common.h | 24 +++

include/hw/arm/smmuv3.h | 1 +

include/hw/misc/aspeed_scu.h | 70 ++++++-

include/hw/ssi/xilinx_spips.h | 5 +-

include/hw/timer/aspeed_timer.h | 4 +

accel/tcg/cputlb.c | 131 +++++++++++--

hw/arm/aspeed_soc.c | 42 ++--

hw/arm/omap1.c | 18 +-

hw/arm/smmu-common.c | 118 ++++++++++-

hw/arm/smmuv3.c | 420 ++++++++++++++++++++++++++++++++++++----

hw/arm/stellaris.c | 8 +-

hw/dma/omap_dma.c | 70 ++++---

hw/i2c/omap_i2c.c | 20 +-

hw/input/pckbd.c | 4 +-

hw/input/tsc2005.c | 13 +-

hw/misc/aspeed_scu.c | 106 ++++++++++

hw/net/smc91c111.c | 21 +-

hw/net/stellaris_enet.c | 11 +-

hw/sd/omap_mmc.c | 13 +-

hw/ssi/aspeed_smc.c | 48 ++---

hw/ssi/omap_spi.c | 15 +-

hw/ssi/xilinx_spips.c | 23 ++-

hw/timer/aspeed_timer.c | 19 +-

target/arm/helper.c | 115 +++++++----

MAINTAINERS | 14 +-

hw/arm/trace-events | 27 ++-

30 files changed, 1176 insertions(+), 255 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180620130619.11362-4-peter.maydell@linaro.org

static Property smmu_dev_properties[] = {

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/smmuv3.c

+++ b/hw/arm/smmuv3.c

@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid};

SMMUPTWEventInfo ptw_info = {};

SMMUTranslationStatus status;

+ SMMUState *bs = ARM_SMMU(s);

+ uint64_t page_mask, aligned_addr;

+ IOMMUTLBEntry *cached_entry = NULL;

+ SMMUTransTableInfo *tt;

SMMUTransCfg *cfg = NULL;

IOMMUTLBEntry entry = {

.target_as = &address_space_memory,

@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

.addr_mask = ~(hwaddr)0,

.perm = IOMMU_NONE,

};

+ SMMUIOTLBKey key, *new_key;

qemu_mutex_lock(&s->mutex);

@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

goto epilogue;

}

- if (smmu_ptw(cfg, addr, flag, &entry, &ptw_info)) {

+ tt = select_tt(cfg, addr);

+ if (!tt) {

+ if (event.record_trans_faults) {

+ event.type = SMMU_EVT_F_TRANSLATION;

+ event.u.f_translation.addr = addr;

+ event.u.f_translation.rnw = flag & 0x1;

+ }

+ status = SMMU_TRANS_ERROR;

+ goto epilogue;

+ }

+

+ page_mask = (1ULL << (tt->granule_sz)) - 1;

+ aligned_addr = addr & ~page_mask;

+

+ key.asid = cfg->asid;

+ key.iova = aligned_addr;

+

+ cached_entry = g_hash_table_lookup(bs->iotlb, &key);

+ if (cached_entry) {

+ cfg->iotlb_hits++;

+ trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr,

+ cfg->iotlb_hits, cfg->iotlb_misses,

+ 100 * cfg->iotlb_hits /

+ (cfg->iotlb_hits + cfg->iotlb_misses));

+ if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) {

+ status = SMMU_TRANS_ERROR;

+ if (event.record_trans_faults) {

+ event.type = SMMU_EVT_F_PERMISSION;

+ event.u.f_permission.addr = addr;

+ event.u.f_permission.rnw = flag & 0x1;

+ }

+ } else {

+ status = SMMU_TRANS_SUCCESS;

+ }

+ goto epilogue;

+ }

+

+ cfg->iotlb_misses++;

+ trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask,

+ cfg->iotlb_hits, cfg->iotlb_misses,

+ 100 * cfg->iotlb_hits /

+ (cfg->iotlb_hits + cfg->iotlb_misses));

+

+ if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {

+ smmu_iotlb_inv_all(bs);

+ }

+

+ cached_entry = g_new0(IOMMUTLBEntry, 1);

+

+ if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {

+ g_free(cached_entry);

switch (ptw_info.type) {

case SMMU_PTW_ERR_WALK_EABT:

event.type = SMMU_EVT_F_WALK_EABT;

@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,

}

status = SMMU_TRANS_ERROR;

} else {

+ new_key = g_new0(SMMUIOTLBKey, 1);

+ new_key->asid = cfg->asid;

+ new_key->iova = aligned_addr;

+ g_hash_table_insert(bs->iotlb, new_key, cached_entry);

status = SMMU_TRANS_SUCCESS;

}

@@ -XXX,XX +XXX,XX @@ epilogue:

switch (status) {

case SMMU_TRANS_SUCCESS:

entry.perm = flag;

+ entry.translated_addr = cached_entry->translated_addr +

+ (addr & page_mask);

+ entry.addr_mask = cached_entry->addr_mask;

trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr,

entry.translated_addr, entry.perm);

break;

@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)

smmuv3_flush_config(sdev);

break;

}

- case SMMU_CMD_TLBI_NH_ALL:

case SMMU_CMD_TLBI_NH_ASID:

- case SMMU_CMD_TLBI_NH_VA:

+ {

+ uint16_t asid = CMD_ASID(&cmd);

+

+ trace_smmuv3_cmdq_tlbi_nh_asid(asid);

+ smmu_iotlb_inv_asid(bs, asid);

+ break;

+ }

+ case SMMU_CMD_TLBI_NH_ALL:

+ case SMMU_CMD_TLBI_NSNH_ALL:

+ trace_smmuv3_cmdq_tlbi_nh();

+ smmu_iotlb_inv_all(bs);

+ break;

case SMMU_CMD_TLBI_NH_VAA:

+ {

+ dma_addr_t addr = CMD_ADDR(&cmd);

+ uint16_t vmid = CMD_VMID(&cmd);

+

+ trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr);

+ smmu_iotlb_inv_all(bs);

+ break;

+ }

+ case SMMU_CMD_TLBI_NH_VA:

+ {

+ uint16_t asid = CMD_ASID(&cmd);

+ uint16_t vmid = CMD_VMID(&cmd);

+ dma_addr_t addr = CMD_ADDR(&cmd);

+ bool leaf = CMD_LEAF(&cmd);

+

+ trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf);

+ smmu_iotlb_inv_iova(bs, asid, addr);

+ break;

+ }

case SMMU_CMD_TLBI_EL3_ALL:

case SMMU_CMD_TLBI_EL3_VA:

case SMMU_CMD_TLBI_EL2_ALL:

@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)

case SMMU_CMD_TLBI_EL2_VAA:

case SMMU_CMD_TLBI_S12_VMALL:

case SMMU_CMD_TLBI_S2_IPA:

- case SMMU_CMD_TLBI_NSNH_ALL:

case SMMU_CMD_ATC_INV:

case SMMU_CMD_PRI_RESP:

case SMMU_CMD_RESUME:

diff --git a/hw/arm/trace-events b/hw/arm/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/trace-events

+++ b/hw/arm/trace-events

@@ -XXX,XX +XXX,XX @@ smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr,

smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64

smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"

smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64

+smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"

+smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"

+smmu_iotlb_inv_all(void) "IOTLB invalidate all"

+smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"

+smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64

#hw/arm/smmuv3.c

smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"

@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"

smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"

smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"

smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"

+smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d"

+smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64

+smmuv3_cmdq_tlbi_nh(void) ""

+smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"

smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"

Suggested-by: Thomas Huth <thuth@redhat.com>