From: Richard Henderson <richard.henderson@linaro.org>
The parameters for tcg_gen_insn_start are target_ulong, which may be split
into two TCGArg parameters for storage in the opcode on 32-bit hosts.
Fixes the ARM target and its direct use of tcg_set_insn_param, which would
set the wrong argument in the 64-on-32 case.
Cc: qemu-stable@nongnu.org
Reported-by: alarson@ddci.com
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180410003558.2470-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
(cherry picked from commit 9743cd5736263e90d312b2c33bd739ffe1eae70d)
Conflicts:
target/arm/translate.h
tcg/tcg.h
* rework to avoid functional dependency on 15fa08f
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
---
target/arm/translate.h | 2 +-
tcg/tcg.h | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 410ba79c0d..0c6a24d287 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -118,7 +118,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
/* We check and clear insn_start_idx to catch multiple updates. */
assert(s->insn_start_idx != 0);
- tcg_set_insn_param(s->insn_start_idx, 2, syn);
+ tcg_set_insn_start_param(s->insn_start_idx, 2, syn);
s->insn_start_idx = 0;
}
diff --git a/tcg/tcg.h b/tcg/tcg.h
index cb7b329876..d88d3520ac 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -783,6 +783,16 @@ static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
tcg_ctx->gen_op_buf[op_idx].args[arg] = v;
}
+static inline void tcg_set_insn_start_param(int op_idx, int arg, target_ulong v)
+{
+#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ tcg_set_insn_param(op_idx, arg, v);
+#else
+ tcg_set_insn_param(op_idx, arg * 2, v);
+ tcg_set_insn_param(op_idx, arg * 2 + 1, v >> 32);
+#endif
+}
+
/* The number of opcodes emitted so far. */
static inline int tcg_op_buf_count(void)
{
--
2.11.0