1 | target-arm queue; this one has a fair scattering of more | 1 | Hi; here's the first target-arm pullreq for the 7.0 cycle. |
---|---|---|---|
2 | miscellaneous things in it which I've sent out this week. | ||
3 | I've shoved those in as well as it seemed the least-effort | ||
4 | way of getting them into master; a few of them are dependencies | ||
5 | on arm-related patches I have brewing. | ||
6 | 2 | ||
7 | thanks | 3 | thanks |
8 | -- PMM | 4 | -- PMM |
9 | 5 | ||
6 | The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e: | ||
10 | 7 | ||
11 | The following changes since commit 2702c2d3eb74e3908c0c5dbf3a71c8987595a86e: | 8 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800) |
12 | |||
13 | Merge remote-tracking branch 'remotes/stsquad/tags/pull-travis-updates-140618-1' into staging (2018-06-15 12:49:36 +0100) | ||
14 | 9 | ||
15 | are available in the Git repository at: | 10 | are available in the Git repository at: |
16 | 11 | ||
17 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180615 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215 |
18 | 13 | ||
19 | for you to fetch changes up to 14120108f87b3f9e1beacdf0a6096e464e62bb65: | 14 | for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359: |
20 | 15 | ||
21 | target/arm: Allow ARMv6-M Thumb2 instructions (2018-06-15 15:23:34 +0100) | 16 | tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000) |
22 | 17 | ||
23 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
24 | target-arm and miscellaneous queue: | 19 | target-arm queue: |
25 | * fix KVM state save/restore for GICv3 priority registers for high IRQ numbers | 20 | * ITS: error reporting cleanup |
26 | * hw/arm/mps2-tz: Put ethernet controller behind PPC | 21 | * aspeed: improve documentation |
27 | * hw/sh/sh7750: Convert away from old_mmio | 22 | * Fix STM32F2XX USART data register readout |
28 | * hw/m68k/mcf5206: Convert away from old_mmio | 23 | * allow emulated GICv3 to be disabled in non-TCG builds |
29 | * hw/block/pflash_cfi02: Convert away from old_mmio | 24 | * fix exception priority for singlestep, misaligned PC, bp, etc |
30 | * hw/watchdog/wdt_i6300esb: Convert away from old_mmio | 25 | * Correct calculation of tlb range invalidate length |
31 | * hw/input/pckbd: Convert away from old_mmio | 26 | * npcm7xx_emc: fix missing queue_flush |
32 | * hw/char/parallel: Convert away from old_mmio | 27 | * virt: Add VIOT ACPI table for virtio-iommu |
33 | * armv7m: refactor to get rid of armv7m_init() function | 28 | * target/i386: Use assert() to sanity-check b1 in SSE decode |
34 | * arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC | 29 | * Don't include qemu-common unnecessarily |
35 | * hw/core/or-irq: Support more than 16 inputs to an OR gate | ||
36 | * cpu-defs.h: Document CPUIOTLBEntry 'addr' field | ||
37 | * cputlb: Pass cpu_transaction_failed() the correct physaddr | ||
38 | * CODING_STYLE: Define our preferred form for multiline comments | ||
39 | * Add and use new stn_*_p() and ldn_*_p() memory access functions | ||
40 | * target/arm: More parts of the upcoming SVE support | ||
41 | * aspeed_scu: Implement RNG register | ||
42 | * m25p80: add support for two bytes WRSR for Macronix chips | ||
43 | * exec.c: Handle IOMMUs being in the path of TCG CPU memory accesses | ||
44 | * target/arm: Allow ARMv6-M Thumb2 instructions | ||
45 | 30 | ||
46 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
47 | Cédric Le Goater (1): | 32 | Alex Bennée (1): |
48 | m25p80: add support for two bytes WRSR for Macronix chips | 33 | hw/intc: clean-up error reporting for failed ITS cmd |
49 | 34 | ||
50 | Joel Stanley (1): | 35 | Jean-Philippe Brucker (8): |
51 | aspeed_scu: Implement RNG register | 36 | hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu |
37 | hw/arm/virt: Remove device tree restriction for virtio-iommu | ||
38 | hw/arm/virt: Reject instantiation of multiple IOMMUs | ||
39 | hw/arm/virt: Use object_property_set instead of qdev_prop_set | ||
40 | tests/acpi: allow updates of VIOT expected data files | ||
41 | tests/acpi: add test case for VIOT | ||
42 | tests/acpi: add expected blobs for VIOT test on q35 machine | ||
43 | tests/acpi: add expected blob for VIOT test on virt machine | ||
52 | 44 | ||
53 | Julia Suvorova (1): | 45 | Joel Stanley (4): |
54 | target/arm: Allow ARMv6-M Thumb2 instructions | 46 | docs: aspeed: Add new boards |
47 | docs: aspeed: Update OpenBMC image URL | ||
48 | docs: aspeed: Give an example of booting a kernel | ||
49 | docs: aspeed: ADC is now modelled | ||
55 | 50 | ||
56 | Peter Maydell (21): | 51 | Olivier Hériveaux (1): |
57 | hw/arm/mps2-tz: Put ethernet controller behind PPC | 52 | Fix STM32F2XX USART data register readout |
58 | hw/sh/sh7750: Convert away from old_mmio | ||
59 | hw/m68k/mcf5206: Convert away from old_mmio | ||
60 | hw/block/pflash_cfi02: Convert away from old_mmio | ||
61 | hw/watchdog/wdt_i6300esb: Convert away from old_mmio | ||
62 | hw/input/pckbd: Convert away from old_mmio | ||
63 | hw/char/parallel: Convert away from old_mmio | ||
64 | stellaris: Stop using armv7m_init() | ||
65 | hw/arm/armv7m: Remove unused armv7m_init() function | ||
66 | arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC | ||
67 | hw/core/or-irq: Support more than 16 inputs to an OR gate | ||
68 | cpu-defs.h: Document CPUIOTLBEntry 'addr' field | ||
69 | cputlb: Pass cpu_transaction_failed() the correct physaddr | ||
70 | CODING_STYLE: Define our preferred form for multiline comments | ||
71 | bswap: Add new stn_*_p() and ldn_*_p() memory access functions | ||
72 | exec.c: Don't accidentally sign-extend 4-byte loads in subpage_read() | ||
73 | exec.c: Use stn_p() and ldn_p() instead of explicit switches | ||
74 | iommu: Add IOMMU index concept to IOMMU API | ||
75 | iommu: Add IOMMU index argument to notifier APIs | ||
76 | iommu: Add IOMMU index argument to translate method | ||
77 | exec.c: Handle IOMMUs in address_space_translate_for_iotlb() | ||
78 | 53 | ||
79 | Richard Henderson (18): | 54 | Patrick Venture (1): |
80 | target/arm: Extend vec_reg_offset to larger sizes | 55 | hw/net: npcm7xx_emc fix missing queue_flush |
81 | target/arm: Implement SVE Permute - Unpredicated Group | ||
82 | target/arm: Implement SVE Permute - Predicates Group | ||
83 | target/arm: Implement SVE Permute - Interleaving Group | ||
84 | target/arm: Implement SVE compress active elements | ||
85 | target/arm: Implement SVE conditionally broadcast/extract element | ||
86 | target/arm: Implement SVE copy to vector (predicated) | ||
87 | target/arm: Implement SVE reverse within elements | ||
88 | target/arm: Implement SVE vector splice (predicated) | ||
89 | target/arm: Implement SVE Select Vectors Group | ||
90 | target/arm: Implement SVE Integer Compare - Vectors Group | ||
91 | target/arm: Implement SVE Integer Compare - Immediate Group | ||
92 | target/arm: Implement SVE Partition Break Group | ||
93 | target/arm: Implement SVE Predicate Count Group | ||
94 | target/arm: Implement SVE Integer Compare - Scalars Group | ||
95 | target/arm: Implement FDUP/DUP | ||
96 | target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group | ||
97 | target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group | ||
98 | 56 | ||
99 | Shannon Zhao (1): | 57 | Peter Maydell (6): |
100 | arm_gicv3_kvm: kvm_dist_get/put_priority: skip the registers banked by GICR_IPRIORITYR | 58 | target/i386: Use assert() to sanity-check b1 in SSE decode |
59 | include/hw/i386: Don't include qemu-common.h in .h files | ||
60 | target/hexagon/cpu.h: don't include qemu-common.h | ||
61 | target/rx/cpu.h: Don't include qemu-common.h | ||
62 | hw/arm: Don't include qemu-common.h unnecessarily | ||
63 | target/arm: Correct calculation of tlb range invalidate length | ||
101 | 64 | ||
102 | include/exec/cpu-all.h | 4 + | 65 | Philippe Mathieu-Daudé (2): |
103 | include/exec/cpu-defs.h | 9 + | 66 | hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c |
104 | include/exec/exec-all.h | 16 +- | 67 | hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector |
105 | include/exec/memory.h | 65 +- | ||
106 | include/hw/arm/arm.h | 8 +- | ||
107 | include/hw/or-irq.h | 5 +- | ||
108 | include/qemu/bswap.h | 52 ++ | ||
109 | include/qom/cpu.h | 3 + | ||
110 | target/arm/helper-sve.h | 294 +++++++++ | ||
111 | target/arm/helper.h | 19 + | ||
112 | target/arm/translate-a64.h | 26 +- | ||
113 | accel/tcg/cputlb.c | 59 +- | ||
114 | exec.c | 263 ++++---- | ||
115 | hw/alpha/typhoon.c | 3 +- | ||
116 | hw/arm/armv7m.c | 28 +- | ||
117 | hw/arm/mps2-tz.c | 32 +- | ||
118 | hw/arm/smmuv3.c | 2 +- | ||
119 | hw/arm/stellaris.c | 12 +- | ||
120 | hw/block/m25p80.c | 1 + | ||
121 | hw/block/pflash_cfi02.c | 97 +-- | ||
122 | hw/char/parallel.c | 50 +- | ||
123 | hw/core/or-irq.c | 39 +- | ||
124 | hw/dma/rc4030.c | 2 +- | ||
125 | hw/i386/amd_iommu.c | 2 +- | ||
126 | hw/i386/intel_iommu.c | 8 +- | ||
127 | hw/input/pckbd.c | 14 +- | ||
128 | hw/intc/arm_gicv3_kvm.c | 18 +- | ||
129 | hw/intc/armv7m_nvic.c | 6 +- | ||
130 | hw/m68k/mcf5206.c | 48 +- | ||
131 | hw/misc/aspeed_scu.c | 20 + | ||
132 | hw/ppc/spapr_iommu.c | 5 +- | ||
133 | hw/s390x/s390-pci-bus.c | 2 +- | ||
134 | hw/s390x/s390-pci-inst.c | 4 +- | ||
135 | hw/sh4/sh7750.c | 44 +- | ||
136 | hw/sparc/sun4m_iommu.c | 3 +- | ||
137 | hw/sparc64/sun4u_iommu.c | 2 +- | ||
138 | hw/vfio/common.c | 6 +- | ||
139 | hw/virtio/vhost.c | 7 +- | ||
140 | hw/watchdog/wdt_i6300esb.c | 48 +- | ||
141 | memory.c | 33 +- | ||
142 | target/arm/cpu.c | 18 + | ||
143 | target/arm/sve_helper.c | 1250 +++++++++++++++++++++++++++++++++++++ | ||
144 | target/arm/translate-sve.c | 1458 +++++++++++++++++++++++++++++++++++++++++++ | ||
145 | target/arm/translate.c | 43 +- | ||
146 | target/arm/vec_helper.c | 69 ++ | ||
147 | CODING_STYLE | 17 + | ||
148 | docs/devel/loads-stores.rst | 15 + | ||
149 | target/arm/sve.decode | 248 ++++++++ | ||
150 | 48 files changed, 4114 insertions(+), 363 deletions(-) | ||
151 | 68 | ||
69 | Richard Henderson (10): | ||
70 | target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn | ||
71 | target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn | ||
72 | target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn | ||
73 | target/arm: Split arm_pre_translate_insn | ||
74 | target/arm: Advance pc for arch single-step exception | ||
75 | target/arm: Split compute_fsr_fsc out of arm_deliver_fault | ||
76 | target/arm: Take an exception if PC is misaligned | ||
77 | target/arm: Assert thumb pc is aligned | ||
78 | target/arm: Suppress bp for exceptions with more priority | ||
79 | tests/tcg: Add arm and aarch64 pc alignment tests | ||
80 | |||
81 | docs/system/arm/aspeed.rst | 26 ++++++++++++---- | ||
82 | include/hw/i386/microvm.h | 1 - | ||
83 | include/hw/i386/x86.h | 1 - | ||
84 | target/arm/helper.h | 1 + | ||
85 | target/arm/syndrome.h | 5 +++ | ||
86 | target/hexagon/cpu.h | 1 - | ||
87 | target/rx/cpu.h | 1 - | ||
88 | hw/arm/boot.c | 1 - | ||
89 | hw/arm/digic_boards.c | 1 - | ||
90 | hw/arm/highbank.c | 1 - | ||
91 | hw/arm/npcm7xx_boards.c | 1 - | ||
92 | hw/arm/sbsa-ref.c | 1 - | ||
93 | hw/arm/stm32f405_soc.c | 1 - | ||
94 | hw/arm/vexpress.c | 1 - | ||
95 | hw/arm/virt-acpi-build.c | 7 +++++ | ||
96 | hw/arm/virt.c | 21 ++++++------- | ||
97 | hw/char/stm32f2xx_usart.c | 3 +- | ||
98 | hw/intc/arm_gicv3.c | 2 +- | ||
99 | hw/intc/arm_gicv3_cpuif.c | 10 +----- | ||
100 | hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++ | ||
101 | hw/intc/arm_gicv3_its.c | 39 +++++++++++++++-------- | ||
102 | hw/net/npcm7xx_emc.c | 18 +++++------ | ||
103 | hw/virtio/virtio-iommu-pci.c | 12 ++------ | ||
104 | linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------ | ||
105 | linux-user/hexagon/cpu_loop.c | 1 + | ||
106 | target/arm/debug_helper.c | 23 ++++++++++++++ | ||
107 | target/arm/gdbstub.c | 9 ++++-- | ||
108 | target/arm/helper.c | 6 ++-- | ||
109 | target/arm/machine.c | 10 ++++++ | ||
110 | target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++---------- | ||
111 | target/arm/translate-a64.c | 23 ++++++++++++-- | ||
112 | target/arm/translate.c | 58 ++++++++++++++++++++++++++--------- | ||
113 | target/i386/tcg/translate.c | 12 ++------ | ||
114 | tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++ | ||
115 | tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++ | ||
116 | tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++ | ||
117 | hw/arm/Kconfig | 1 + | ||
118 | hw/intc/Kconfig | 5 +++ | ||
119 | hw/intc/meson.build | 11 ++++--- | ||
120 | tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes | ||
121 | tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes | ||
122 | tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes | ||
123 | tests/tcg/aarch64/Makefile.target | 4 +-- | ||
124 | tests/tcg/arm/Makefile.target | 4 +++ | ||
125 | 44 files changed, 429 insertions(+), 145 deletions(-) | ||
126 | create mode 100644 hw/intc/arm_gicv3_cpuif_common.c | ||
127 | create mode 100644 tests/tcg/aarch64/pcalign-a64.c | ||
128 | create mode 100644 tests/tcg/arm/pcalign-a32.c | ||
129 | create mode 100644 tests/data/acpi/q35/DSDT.viot | ||
130 | create mode 100644 tests/data/acpi/q35/VIOT.viot | ||
131 | create mode 100644 tests/data/acpi/virt/VIOT | ||
132 | diff view generated by jsdifflib |
1 | Currently we don't support board configurations that put an IOMMU | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | in the path of the CPU's memory transactions, and instead just | ||
3 | assert() if the memory region fonud in address_space_translate_for_iotlb() | ||
4 | is an IOMMUMemoryRegion. | ||
5 | 2 | ||
6 | Remove this limitation by having the function handle IOMMUs. | 3 | While trying to debug a GIC ITS failure I saw some guest errors that |
7 | This is mostly straightforward, but we must make sure we have | 4 | had poor formatting as well as leaving me confused as to what failed. |
8 | a notifier registered for every IOMMU that a transaction has | 5 | As most of the checks aren't possible without a valid dte split that |
9 | passed through, so that we can flush the TLB appropriately | 6 | check apart and then check the other conditions in steps. This avoids |
10 | when any of the IOMMUs change their mappings. | 7 | us relying on undefined data. |
11 | 8 | ||
9 | I still get a failure with the current kvm-unit-tests but at least I | ||
10 | know (partially) why now: | ||
11 | |||
12 | Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588 | ||
13 | PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI | ||
14 | ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0 | ||
15 | INT dev_id=2 event_id=20 | ||
16 | process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0) | ||
17 | PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap | ||
18 | SUMMARY: 6 tests, 1 unexpected failures | ||
19 | |||
20 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org | ||
23 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | ||
24 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
14 | Message-id: 20180604152941.20374-5-peter.maydell@linaro.org | ||
15 | --- | 26 | --- |
16 | include/exec/exec-all.h | 3 +- | 27 | hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------ |
17 | include/qom/cpu.h | 3 + | 28 | 1 file changed, 27 insertions(+), 12 deletions(-) |
18 | accel/tcg/cputlb.c | 3 +- | ||
19 | exec.c | 135 +++++++++++++++++++++++++++++++++++++++- | ||
20 | 4 files changed, 140 insertions(+), 4 deletions(-) | ||
21 | 29 | ||
22 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h | 30 | diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c |
23 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/include/exec/exec-all.h | 32 | --- a/hw/intc/arm_gicv3_its.c |
25 | +++ b/include/exec/exec-all.h | 33 | +++ b/hw/intc/arm_gicv3_its.c |
26 | @@ -XXX,XX +XXX,XX @@ void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr); | 34 | @@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset, |
27 | 35 | if (res != MEMTX_OK) { | |
28 | MemoryRegionSection * | 36 | return result; |
29 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, | 37 | } |
30 | - hwaddr *xlat, hwaddr *plen); | 38 | + } else { |
31 | + hwaddr *xlat, hwaddr *plen, | 39 | + qemu_log_mask(LOG_GUEST_ERROR, |
32 | + MemTxAttrs attrs, int *prot); | 40 | + "%s: invalid command attributes: " |
33 | hwaddr memory_region_section_get_iotlb(CPUState *cpu, | 41 | + "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n", |
34 | MemoryRegionSection *section, | 42 | + __func__, dte, devid, res); |
35 | target_ulong vaddr, | 43 | + return result; |
36 | diff --git a/include/qom/cpu.h b/include/qom/cpu.h | 44 | } |
37 | index XXXXXXX..XXXXXXX 100644 | 45 | |
38 | --- a/include/qom/cpu.h | 46 | - if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid || |
39 | +++ b/include/qom/cpu.h | 47 | - !cte_valid || (eventid > max_eventid)) { |
40 | @@ -XXX,XX +XXX,XX @@ struct CPUState { | ||
41 | uint16_t pending_tlb_flush; | ||
42 | |||
43 | int hvf_fd; | ||
44 | + | 48 | + |
45 | + /* track IOMMUs whose translations we've cached in the TCG TLB */ | 49 | + /* |
46 | + GArray *iommu_notifiers; | 50 | + * In this implementation, in case of guest errors we ignore the |
47 | }; | 51 | + * command and move onto the next command in the queue. |
48 | 52 | + */ | |
49 | QTAILQ_HEAD(CPUTailQ, CPUState); | 53 | + if (devid > s->dt.maxids.max_devids) { |
50 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | 54 | qemu_log_mask(LOG_GUEST_ERROR, |
51 | index XXXXXXX..XXXXXXX 100644 | 55 | - "%s: invalid command attributes " |
52 | --- a/accel/tcg/cputlb.c | 56 | - "devid %d or eventid %d or invalid dte %d or" |
53 | +++ b/accel/tcg/cputlb.c | 57 | - "invalid cte %d or invalid ite %d\n", |
54 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | 58 | - __func__, devid, eventid, dte_valid, cte_valid, |
55 | } | 59 | - ite_valid); |
56 | 60 | - /* | |
57 | sz = size; | 61 | - * in this implementation, in case of error |
58 | - section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz); | 62 | - * we ignore this command and move onto the next |
59 | + section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz, | 63 | - * command in the queue |
60 | + attrs, &prot); | 64 | - */ |
61 | assert(sz >= TARGET_PAGE_SIZE); | 65 | + "%s: invalid command attributes: devid %d>%d", |
62 | 66 | + __func__, devid, s->dt.maxids.max_devids); | |
63 | tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx | ||
64 | diff --git a/exec.c b/exec.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/exec.c | ||
67 | +++ b/exec.c | ||
68 | @@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, | ||
69 | return mr; | ||
70 | } | ||
71 | |||
72 | +typedef struct TCGIOMMUNotifier { | ||
73 | + IOMMUNotifier n; | ||
74 | + MemoryRegion *mr; | ||
75 | + CPUState *cpu; | ||
76 | + int iommu_idx; | ||
77 | + bool active; | ||
78 | +} TCGIOMMUNotifier; | ||
79 | + | 67 | + |
80 | +static void tcg_iommu_unmap_notify(IOMMUNotifier *n, IOMMUTLBEntry *iotlb) | 68 | + } else if (!dte_valid || !ite_valid || !cte_valid) { |
81 | +{ | 69 | + qemu_log_mask(LOG_GUEST_ERROR, |
82 | + TCGIOMMUNotifier *notifier = container_of(n, TCGIOMMUNotifier, n); | 70 | + "%s: invalid command attributes: " |
83 | + | 71 | + "dte: %s, ite: %s, cte: %s\n", |
84 | + if (!notifier->active) { | 72 | + __func__, |
85 | + return; | 73 | + dte_valid ? "valid" : "invalid", |
86 | + } | 74 | + ite_valid ? "valid" : "invalid", |
87 | + tlb_flush(notifier->cpu); | 75 | + cte_valid ? "valid" : "invalid"); |
88 | + notifier->active = false; | 76 | + } else if (eventid > max_eventid) { |
89 | + /* We leave the notifier struct on the list to avoid reallocating it later. | 77 | + qemu_log_mask(LOG_GUEST_ERROR, |
90 | + * Generally the number of IOMMUs a CPU deals with will be small. | 78 | + "%s: invalid command attributes: eventid %d > %d\n", |
91 | + * In any case we can't unregister the iommu notifier from a notify | 79 | + __func__, eventid, max_eventid); |
92 | + * callback. | 80 | } else { |
93 | + */ | 81 | /* |
94 | +} | 82 | * Current implementation only supports rdbase == procnum |
95 | + | ||
96 | +static void tcg_register_iommu_notifier(CPUState *cpu, | ||
97 | + IOMMUMemoryRegion *iommu_mr, | ||
98 | + int iommu_idx) | ||
99 | +{ | ||
100 | + /* Make sure this CPU has an IOMMU notifier registered for this | ||
101 | + * IOMMU/IOMMU index combination, so that we can flush its TLB | ||
102 | + * when the IOMMU tells us the mappings we've cached have changed. | ||
103 | + */ | ||
104 | + MemoryRegion *mr = MEMORY_REGION(iommu_mr); | ||
105 | + TCGIOMMUNotifier *notifier; | ||
106 | + int i; | ||
107 | + | ||
108 | + for (i = 0; i < cpu->iommu_notifiers->len; i++) { | ||
109 | + notifier = &g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier, i); | ||
110 | + if (notifier->mr == mr && notifier->iommu_idx == iommu_idx) { | ||
111 | + break; | ||
112 | + } | ||
113 | + } | ||
114 | + if (i == cpu->iommu_notifiers->len) { | ||
115 | + /* Not found, add a new entry at the end of the array */ | ||
116 | + cpu->iommu_notifiers = g_array_set_size(cpu->iommu_notifiers, i + 1); | ||
117 | + notifier = &g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier, i); | ||
118 | + | ||
119 | + notifier->mr = mr; | ||
120 | + notifier->iommu_idx = iommu_idx; | ||
121 | + notifier->cpu = cpu; | ||
122 | + /* Rather than trying to register interest in the specific part | ||
123 | + * of the iommu's address space that we've accessed and then | ||
124 | + * expand it later as subsequent accesses touch more of it, we | ||
125 | + * just register interest in the whole thing, on the assumption | ||
126 | + * that iommu reconfiguration will be rare. | ||
127 | + */ | ||
128 | + iommu_notifier_init(¬ifier->n, | ||
129 | + tcg_iommu_unmap_notify, | ||
130 | + IOMMU_NOTIFIER_UNMAP, | ||
131 | + 0, | ||
132 | + HWADDR_MAX, | ||
133 | + iommu_idx); | ||
134 | + memory_region_register_iommu_notifier(notifier->mr, ¬ifier->n); | ||
135 | + } | ||
136 | + | ||
137 | + if (!notifier->active) { | ||
138 | + notifier->active = true; | ||
139 | + } | ||
140 | +} | ||
141 | + | ||
142 | +static void tcg_iommu_free_notifier_list(CPUState *cpu) | ||
143 | +{ | ||
144 | + /* Destroy the CPU's notifier list */ | ||
145 | + int i; | ||
146 | + TCGIOMMUNotifier *notifier; | ||
147 | + | ||
148 | + for (i = 0; i < cpu->iommu_notifiers->len; i++) { | ||
149 | + notifier = &g_array_index(cpu->iommu_notifiers, TCGIOMMUNotifier, i); | ||
150 | + memory_region_unregister_iommu_notifier(notifier->mr, ¬ifier->n); | ||
151 | + } | ||
152 | + g_array_free(cpu->iommu_notifiers, true); | ||
153 | +} | ||
154 | + | ||
155 | /* Called from RCU critical section */ | ||
156 | MemoryRegionSection * | ||
157 | address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, | ||
158 | - hwaddr *xlat, hwaddr *plen) | ||
159 | + hwaddr *xlat, hwaddr *plen, | ||
160 | + MemTxAttrs attrs, int *prot) | ||
161 | { | ||
162 | MemoryRegionSection *section; | ||
163 | + IOMMUMemoryRegion *iommu_mr; | ||
164 | + IOMMUMemoryRegionClass *imrc; | ||
165 | + IOMMUTLBEntry iotlb; | ||
166 | + int iommu_idx; | ||
167 | AddressSpaceDispatch *d = atomic_rcu_read(&cpu->cpu_ases[asidx].memory_dispatch); | ||
168 | |||
169 | - section = address_space_translate_internal(d, addr, xlat, plen, false); | ||
170 | + for (;;) { | ||
171 | + section = address_space_translate_internal(d, addr, &addr, plen, false); | ||
172 | + | ||
173 | + iommu_mr = memory_region_get_iommu(section->mr); | ||
174 | + if (!iommu_mr) { | ||
175 | + break; | ||
176 | + } | ||
177 | + | ||
178 | + imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | ||
179 | + | ||
180 | + iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | ||
181 | + tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); | ||
182 | + /* We need all the permissions, so pass IOMMU_NONE so the IOMMU | ||
183 | + * doesn't short-cut its translation table walk. | ||
184 | + */ | ||
185 | + iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); | ||
186 | + addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | ||
187 | + | (addr & iotlb.addr_mask)); | ||
188 | + /* Update the caller's prot bits to remove permissions the IOMMU | ||
189 | + * is giving us a failure response for. If we get down to no | ||
190 | + * permissions left at all we can give up now. | ||
191 | + */ | ||
192 | + if (!(iotlb.perm & IOMMU_RO)) { | ||
193 | + *prot &= ~(PAGE_READ | PAGE_EXEC); | ||
194 | + } | ||
195 | + if (!(iotlb.perm & IOMMU_WO)) { | ||
196 | + *prot &= ~PAGE_WRITE; | ||
197 | + } | ||
198 | + | ||
199 | + if (!*prot) { | ||
200 | + goto translate_fail; | ||
201 | + } | ||
202 | + | ||
203 | + d = flatview_to_dispatch(address_space_to_flatview(iotlb.target_as)); | ||
204 | + } | ||
205 | |||
206 | assert(!memory_region_is_iommu(section->mr)); | ||
207 | + *xlat = addr; | ||
208 | return section; | ||
209 | + | ||
210 | +translate_fail: | ||
211 | + return &d->map.sections[PHYS_SECTION_UNASSIGNED]; | ||
212 | } | ||
213 | #endif | ||
214 | |||
215 | @@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu) | ||
216 | if (qdev_get_vmsd(DEVICE(cpu)) == NULL) { | ||
217 | vmstate_unregister(NULL, &vmstate_cpu_common, cpu); | ||
218 | } | ||
219 | +#ifndef CONFIG_USER_ONLY | ||
220 | + tcg_iommu_free_notifier_list(cpu); | ||
221 | +#endif | ||
222 | } | ||
223 | |||
224 | Property cpu_common_props[] = { | ||
225 | @@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) | ||
226 | if (cc->vmsd != NULL) { | ||
227 | vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); | ||
228 | } | ||
229 | + | ||
230 | + cpu->iommu_notifiers = g_array_new(false, true, sizeof(TCGIOMMUNotifier)); | ||
231 | #endif | ||
232 | } | ||
233 | |||
234 | -- | 83 | -- |
235 | 2.17.1 | 84 | 2.25.1 |
236 | 85 | ||
237 | 86 | diff view generated by jsdifflib |
1 | From: Cédric Le Goater <clg@kaod.org> | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | 2 | ||
3 | On Macronix chips, two bytes can written to the WRSR. First byte will | 3 | Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be |
4 | configure the status register and the second the configuration | 4 | removed in v7.0. |
5 | register. It is important to save the configuration value as it | ||
6 | contains the dummy cycle setting when using dual or quad IO mode. | ||
7 | 5 | ||
8 | Signed-off-by: Cédric Le Goater <clg@kaod.org> | 6 | Signed-off-by: Joel Stanley <joel@jms.id.au> |
9 | Acked-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
8 | Message-id: 20211117065752.330632-2-joel@jms.id.au | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | hw/block/m25p80.c | 1 + | 11 | docs/system/arm/aspeed.rst | 7 ++++++- |
13 | 1 file changed, 1 insertion(+) | 12 | 1 file changed, 6 insertions(+), 1 deletion(-) |
14 | 13 | ||
15 | diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/block/m25p80.c | 16 | --- a/docs/system/arm/aspeed.rst |
18 | +++ b/hw/block/m25p80.c | 17 | +++ b/docs/system/arm/aspeed.rst |
19 | @@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s) | 18 | @@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines : |
20 | case MAN_MACRONIX: | 19 | |
21 | s->quad_enable = extract32(s->data[0], 6, 1); | 20 | - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC |
22 | if (s->len > 1) { | 21 | - ``quanta-q71l-bmc`` OpenBMC Quanta BMC |
23 | + s->volatile_cfg = s->data[1]; | 22 | +- ``supermicrox11-bmc`` Supermicro X11 BMC |
24 | s->four_bytes_address_mode = extract32(s->data[1], 5, 1); | 23 | |
25 | } | 24 | AST2500 SoC based machines : |
26 | break; | 25 | |
26 | @@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines : | ||
27 | - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC | ||
28 | - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC | ||
29 | - ``sonorapass-bmc`` OCP SonoraPass BMC | ||
30 | -- ``swift-bmc`` OpenPOWER Swift BMC POWER9 | ||
31 | +- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0) | ||
32 | +- ``fp5280g2-bmc`` Inspur FP5280G2 BMC | ||
33 | +- ``g220a-bmc`` Bytedance G220A BMC | ||
34 | |||
35 | AST2600 SoC based machines : | ||
36 | |||
37 | - ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7) | ||
38 | - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC | ||
39 | +- ``rainier-bmc`` IBM Rainier POWER10 BMC | ||
40 | +- ``fuji-bmc`` Facebook Fuji BMC | ||
41 | |||
42 | Supported devices | ||
43 | ----------------- | ||
27 | -- | 44 | -- |
28 | 2.17.1 | 45 | 2.25.1 |
29 | 46 | ||
30 | 47 | diff view generated by jsdifflib |
1 | The 'addr' field in the CPUIOTLBEntry struct has a rather non-obvious | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | use; add a comment documenting it (reverse-engineered from what | ||
3 | the code that sets it is doing). | ||
4 | 2 | ||
3 | This is the latest URL for the OpenBMC CI. The old URL still works, but | ||
4 | redirects. | ||
5 | |||
6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | ||
7 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
8 | Message-id: 20211117065752.330632-3-joel@jms.id.au | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20180611125633.32755-2-peter.maydell@linaro.org | ||
9 | --- | 10 | --- |
10 | include/exec/cpu-defs.h | 9 +++++++++ | 11 | docs/system/arm/aspeed.rst | 2 +- |
11 | accel/tcg/cputlb.c | 12 ++++++++++++ | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
12 | 2 files changed, 21 insertions(+) | ||
13 | 13 | ||
14 | diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/exec/cpu-defs.h | 16 | --- a/docs/system/arm/aspeed.rst |
17 | +++ b/include/exec/cpu-defs.h | 17 | +++ b/docs/system/arm/aspeed.rst |
18 | @@ -XXX,XX +XXX,XX @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); | 18 | @@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to |
19 | * structs into one.) | 19 | load a Linux kernel or from a firmware. Images can be downloaded from |
20 | */ | 20 | the OpenBMC jenkins : |
21 | typedef struct CPUIOTLBEntry { | 21 | |
22 | + /* | 22 | - https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder |
23 | + * @addr contains: | 23 | + https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ |
24 | + * - in the lower TARGET_PAGE_BITS, a physical section number | 24 | |
25 | + * - with the lower TARGET_PAGE_BITS masked off, an offset which | 25 | or directly from the OpenBMC GitHub release repository : |
26 | + * must be added to the virtual address to obtain: | ||
27 | + * + the ram_addr_t of the target RAM (if the physical section | ||
28 | + * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) | ||
29 | + * + the offset within the target MemoryRegion (otherwise) | ||
30 | + */ | ||
31 | hwaddr addr; | ||
32 | MemTxAttrs attrs; | ||
33 | } CPUIOTLBEntry; | ||
34 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/accel/tcg/cputlb.c | ||
37 | +++ b/accel/tcg/cputlb.c | ||
38 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | ||
39 | env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index]; | ||
40 | |||
41 | /* refill the tlb */ | ||
42 | + /* | ||
43 | + * At this point iotlb contains a physical section number in the lower | ||
44 | + * TARGET_PAGE_BITS, and either | ||
45 | + * + the ram_addr_t of the page base of the target RAM (if NOTDIRTY or ROM) | ||
46 | + * + the offset within section->mr of the page base (otherwise) | ||
47 | + * We subtract the vaddr (which is page aligned and thus won't | ||
48 | + * disturb the low bits) to give an offset which can be added to the | ||
49 | + * (non-page-aligned) vaddr of the eventual memory access to get | ||
50 | + * the MemoryRegion offset for the access. Note that the vaddr we | ||
51 | + * subtract here is that of the page base, and not the same as the | ||
52 | + * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). | ||
53 | + */ | ||
54 | env->iotlb[mmu_idx][index].addr = iotlb - vaddr; | ||
55 | env->iotlb[mmu_idx][index].attrs = attrs; | ||
56 | 26 | ||
57 | -- | 27 | -- |
58 | 2.17.1 | 28 | 2.25.1 |
59 | 29 | ||
60 | 30 | diff view generated by jsdifflib |
1 | From: Joel Stanley <joel@jms.id.au> | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | 2 | ||
3 | The ASPEED SoCs contain a single register that returns random data when | 3 | A common use case for the ASPEED machine is to boot a Linux kernel. |
4 | read. This models that register so that guests can use it. | 4 | Provide a full example command line. |
5 | |||
6 | The random number data register has a corresponding control register, | ||
7 | however it returns data regardless of the state of the enabled bit, so | ||
8 | the model follows this behaviour. | ||
9 | |||
10 | When the qcrypto call fails we exit as the guest uses the random number | ||
11 | device to feed it's entropy pool, which is used for cryptographic | ||
12 | purposes. | ||
13 | 5 | ||
14 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 6 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
15 | Signed-off-by: Joel Stanley <joel@jms.id.au> | 7 | Signed-off-by: Joel Stanley <joel@jms.id.au> |
16 | Message-id: 20180613114836.9265-1-joel@jms.id.au | 8 | Message-id: 20211117065752.330632-4-joel@jms.id.au |
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | --- | 10 | --- |
19 | hw/misc/aspeed_scu.c | 20 ++++++++++++++++++++ | 11 | docs/system/arm/aspeed.rst | 15 ++++++++++++--- |
20 | 1 file changed, 20 insertions(+) | 12 | 1 file changed, 12 insertions(+), 3 deletions(-) |
21 | 13 | ||
22 | diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c | 14 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
23 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/hw/misc/aspeed_scu.c | 16 | --- a/docs/system/arm/aspeed.rst |
25 | +++ b/hw/misc/aspeed_scu.c | 17 | +++ b/docs/system/arm/aspeed.rst |
26 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ Missing devices |
27 | #include "qapi/visitor.h" | 19 | Boot options |
28 | #include "qemu/bitops.h" | 20 | ------------ |
29 | #include "qemu/log.h" | 21 | |
30 | +#include "crypto/random.h" | 22 | -The Aspeed machines can be started using the ``-kernel`` option to |
31 | #include "trace.h" | 23 | -load a Linux kernel or from a firmware. Images can be downloaded from |
32 | 24 | -the OpenBMC jenkins : | |
33 | #define TO_REG(offset) ((offset) >> 2) | 25 | +The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options |
34 | @@ -XXX,XX +XXX,XX @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = { | 26 | +to load a Linux kernel or from a firmware. Images can be downloaded from the |
35 | [BMC_DEV_ID] = 0x00002402U | 27 | +OpenBMC jenkins : |
36 | }; | 28 | |
37 | 29 | https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/ | |
38 | +static uint32_t aspeed_scu_get_random(void) | 30 | |
39 | +{ | 31 | @@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository : |
40 | + Error *err = NULL; | 32 | |
41 | + uint32_t num; | 33 | https://github.com/openbmc/openbmc/releases |
34 | |||
35 | +To boot a kernel directly from a Linux build tree: | ||
42 | + | 36 | + |
43 | + if (qcrypto_random_bytes((uint8_t *)&num, sizeof(num), &err)) { | 37 | +.. code-block:: bash |
44 | + error_report_err(err); | ||
45 | + exit(1); | ||
46 | + } | ||
47 | + | 38 | + |
48 | + return num; | 39 | + $ qemu-system-arm -M ast2600-evb -nographic \ |
49 | +} | 40 | + -kernel arch/arm/boot/zImage \ |
41 | + -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ | ||
42 | + -initrd rootfs.cpio | ||
50 | + | 43 | + |
51 | static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) | 44 | The image should be attached as an MTD drive. Run : |
52 | { | 45 | |
53 | AspeedSCUState *s = ASPEED_SCU(opaque); | 46 | .. code-block:: bash |
54 | @@ -XXX,XX +XXX,XX @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) | ||
55 | } | ||
56 | |||
57 | switch (reg) { | ||
58 | + case RNG_DATA: | ||
59 | + /* On hardware, RNG_DATA works regardless of | ||
60 | + * the state of the enable bit in RNG_CTRL | ||
61 | + */ | ||
62 | + s->regs[RNG_DATA] = aspeed_scu_get_random(); | ||
63 | + break; | ||
64 | case WAKEUP_EN: | ||
65 | qemu_log_mask(LOG_GUEST_ERROR, | ||
66 | "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n", | ||
67 | -- | 47 | -- |
68 | 2.17.1 | 48 | 2.25.1 |
69 | 49 | ||
70 | 50 | diff view generated by jsdifflib |
1 | In subpage_read() we perform a load of the data into a local buffer | 1 | From: Joel Stanley <joel@jms.id.au> |
---|---|---|---|
2 | which we then access using ldub_p(), lduw_p(), ldl_p() or ldq_p() | ||
3 | depending on its size, storing the result into the uint64_t *data. | ||
4 | Since ldl_p() returns an 'int', this means that for the 4-byte | ||
5 | case we will sign-extend the data, whereas for 1 and 2 byte | ||
6 | reads we zero-extend it. | ||
7 | 2 | ||
8 | This ought not to matter since the caller will likely ignore values in | 3 | Move it to the supported list. |
9 | the high bytes of the data, but add a cast so that we're consistent. | ||
10 | 4 | ||
5 | Signed-off-by: Joel Stanley <joel@jms.id.au> | ||
6 | Message-id: 20211117065752.330632-5-joel@jms.id.au | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20180611171007.4165-3-peter.maydell@linaro.org | ||
14 | --- | 8 | --- |
15 | exec.c | 2 +- | 9 | docs/system/arm/aspeed.rst | 2 +- |
16 | 1 file changed, 1 insertion(+), 1 deletion(-) | 10 | 1 file changed, 1 insertion(+), 1 deletion(-) |
17 | 11 | ||
18 | diff --git a/exec.c b/exec.c | 12 | diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst |
19 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/exec.c | 14 | --- a/docs/system/arm/aspeed.rst |
21 | +++ b/exec.c | 15 | +++ b/docs/system/arm/aspeed.rst |
22 | @@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, | 16 | @@ -XXX,XX +XXX,XX @@ Supported devices |
23 | *data = lduw_p(buf); | 17 | * Front LEDs (PCA9552 on I2C bus) |
24 | return MEMTX_OK; | 18 | * LPC Peripheral Controller (a subset of subdevices are supported) |
25 | case 4: | 19 | * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA |
26 | - *data = ldl_p(buf); | 20 | + * ADC |
27 | + *data = (uint32_t)ldl_p(buf); | 21 | |
28 | return MEMTX_OK; | 22 | |
29 | case 8: | 23 | Missing devices |
30 | *data = ldq_p(buf); | 24 | --------------- |
25 | |||
26 | * Coprocessor support | ||
27 | - * ADC (out of tree implementation) | ||
28 | * PWM and Fan Controller | ||
29 | * Slave GPIO Controller | ||
30 | * Super I/O Controller | ||
31 | -- | 31 | -- |
32 | 2.17.1 | 32 | 2.25.1 |
33 | 33 | ||
34 | 34 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Olivier Hériveaux <olivier.heriveaux@ledger.fr> |
---|---|---|---|
2 | 2 | ||
3 | Fix issue where the data register may be overwritten by next character | ||
4 | reception before being read and returned. | ||
5 | |||
6 | Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
5 | Message-id: 20180613015641.5667-19-richard.henderson@linaro.org | 9 | Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/helper-sve.h | 14 ++++++++ | 12 | hw/char/stm32f2xx_usart.c | 3 ++- |
9 | target/arm/helper.h | 19 +++++++++++ | 13 | 1 file changed, 2 insertions(+), 1 deletion(-) |
10 | target/arm/translate-sve.c | 42 +++++++++++++++++++++++ | ||
11 | target/arm/vec_helper.c | 69 ++++++++++++++++++++++++++++++++++++++ | ||
12 | target/arm/sve.decode | 10 ++++++ | ||
13 | 5 files changed, 154 insertions(+) | ||
14 | 14 | ||
15 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 15 | diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c |
16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-sve.h | 17 | --- a/hw/char/stm32f2xx_usart.c |
18 | +++ b/target/arm/helper-sve.h | 18 | +++ b/hw/char/stm32f2xx_usart.c |
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_umini_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 19 | @@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr, |
20 | DEF_HELPER_FLAGS_4(sve_umini_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 20 | return retvalue; |
21 | DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 21 | case USART_DR: |
22 | DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 22 | DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr); |
23 | + | 23 | + retvalue = s->usart_dr & 0x3FF; |
24 | +DEF_HELPER_FLAGS_5(gvec_recps_h, TCG_CALL_NO_RWG, | 24 | s->usart_sr &= ~USART_SR_RXNE; |
25 | + void, ptr, ptr, ptr, ptr, i32) | 25 | qemu_chr_fe_accept_input(&s->chr); |
26 | +DEF_HELPER_FLAGS_5(gvec_recps_s, TCG_CALL_NO_RWG, | 26 | qemu_set_irq(s->irq, 0); |
27 | + void, ptr, ptr, ptr, ptr, i32) | 27 | - return s->usart_dr & 0x3FF; |
28 | +DEF_HELPER_FLAGS_5(gvec_recps_d, TCG_CALL_NO_RWG, | 28 | + return retvalue; |
29 | + void, ptr, ptr, ptr, ptr, i32) | 29 | case USART_BRR: |
30 | + | 30 | return s->usart_brr; |
31 | +DEF_HELPER_FLAGS_5(gvec_rsqrts_h, TCG_CALL_NO_RWG, | 31 | case USART_CR1: |
32 | + void, ptr, ptr, ptr, ptr, i32) | ||
33 | +DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG, | ||
34 | + void, ptr, ptr, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG, | ||
36 | + void, ptr, ptr, ptr, ptr, i32) | ||
37 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/helper.h | ||
40 | +++ b/target/arm/helper.h | ||
41 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fcmlas_idx, TCG_CALL_NO_RWG, | ||
42 | DEF_HELPER_FLAGS_5(gvec_fcmlad, TCG_CALL_NO_RWG, | ||
43 | void, ptr, ptr, ptr, ptr, i32) | ||
44 | |||
45 | +DEF_HELPER_FLAGS_5(gvec_fadd_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
46 | +DEF_HELPER_FLAGS_5(gvec_fadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
47 | +DEF_HELPER_FLAGS_5(gvec_fadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
48 | + | ||
49 | +DEF_HELPER_FLAGS_5(gvec_fsub_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
50 | +DEF_HELPER_FLAGS_5(gvec_fsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
51 | +DEF_HELPER_FLAGS_5(gvec_fsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
52 | + | ||
53 | +DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
54 | +DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
55 | +DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
56 | + | ||
57 | +DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG, | ||
58 | + void, ptr, ptr, ptr, ptr, i32) | ||
59 | +DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG, | ||
60 | + void, ptr, ptr, ptr, ptr, i32) | ||
61 | +DEF_HELPER_FLAGS_5(gvec_ftsmul_d, TCG_CALL_NO_RWG, | ||
62 | + void, ptr, ptr, ptr, ptr, i32) | ||
63 | + | ||
64 | #ifdef TARGET_AARCH64 | ||
65 | #include "helper-a64.h" | ||
66 | #include "helper-sve.h" | ||
67 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/target/arm/translate-sve.c | ||
70 | +++ b/target/arm/translate-sve.c | ||
71 | @@ -XXX,XX +XXX,XX @@ DO_ZZI(UMIN, umin) | ||
72 | |||
73 | #undef DO_ZZI | ||
74 | |||
75 | +/* | ||
76 | + *** SVE Floating Point Arithmetic - Unpredicated Group | ||
77 | + */ | ||
78 | + | ||
79 | +static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a, | ||
80 | + gen_helper_gvec_3_ptr *fn) | ||
81 | +{ | ||
82 | + if (fn == NULL) { | ||
83 | + return false; | ||
84 | + } | ||
85 | + if (sve_access_check(s)) { | ||
86 | + unsigned vsz = vec_full_reg_size(s); | ||
87 | + TCGv_ptr status = get_fpstatus_ptr(a->esz == MO_16); | ||
88 | + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd), | ||
89 | + vec_full_reg_offset(s, a->rn), | ||
90 | + vec_full_reg_offset(s, a->rm), | ||
91 | + status, vsz, vsz, 0, fn); | ||
92 | + tcg_temp_free_ptr(status); | ||
93 | + } | ||
94 | + return true; | ||
95 | +} | ||
96 | + | ||
97 | + | ||
98 | +#define DO_FP3(NAME, name) \ | ||
99 | +static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a, uint32_t insn) \ | ||
100 | +{ \ | ||
101 | + static gen_helper_gvec_3_ptr * const fns[4] = { \ | ||
102 | + NULL, gen_helper_gvec_##name##_h, \ | ||
103 | + gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \ | ||
104 | + }; \ | ||
105 | + return do_zzz_fp(s, a, fns[a->esz]); \ | ||
106 | +} | ||
107 | + | ||
108 | +DO_FP3(FADD_zzz, fadd) | ||
109 | +DO_FP3(FSUB_zzz, fsub) | ||
110 | +DO_FP3(FMUL_zzz, fmul) | ||
111 | +DO_FP3(FTSMUL, ftsmul) | ||
112 | +DO_FP3(FRECPS, recps) | ||
113 | +DO_FP3(FRSQRTS, rsqrts) | ||
114 | + | ||
115 | +#undef DO_FP3 | ||
116 | + | ||
117 | /* | ||
118 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
119 | */ | ||
120 | diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c | ||
121 | index XXXXXXX..XXXXXXX 100644 | ||
122 | --- a/target/arm/vec_helper.c | ||
123 | +++ b/target/arm/vec_helper.c | ||
124 | @@ -XXX,XX +XXX,XX @@ void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm, | ||
125 | } | ||
126 | clear_tail(d, opr_sz, simd_maxsz(desc)); | ||
127 | } | ||
128 | + | ||
129 | +/* Floating-point trigonometric starting value. | ||
130 | + * See the ARM ARM pseudocode function FPTrigSMul. | ||
131 | + */ | ||
132 | +static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat) | ||
133 | +{ | ||
134 | + float16 result = float16_mul(op1, op1, stat); | ||
135 | + if (!float16_is_any_nan(result)) { | ||
136 | + result = float16_set_sign(result, op2 & 1); | ||
137 | + } | ||
138 | + return result; | ||
139 | +} | ||
140 | + | ||
141 | +static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat) | ||
142 | +{ | ||
143 | + float32 result = float32_mul(op1, op1, stat); | ||
144 | + if (!float32_is_any_nan(result)) { | ||
145 | + result = float32_set_sign(result, op2 & 1); | ||
146 | + } | ||
147 | + return result; | ||
148 | +} | ||
149 | + | ||
150 | +static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat) | ||
151 | +{ | ||
152 | + float64 result = float64_mul(op1, op1, stat); | ||
153 | + if (!float64_is_any_nan(result)) { | ||
154 | + result = float64_set_sign(result, op2 & 1); | ||
155 | + } | ||
156 | + return result; | ||
157 | +} | ||
158 | + | ||
159 | +#define DO_3OP(NAME, FUNC, TYPE) \ | ||
160 | +void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ | ||
161 | +{ \ | ||
162 | + intptr_t i, oprsz = simd_oprsz(desc); \ | ||
163 | + TYPE *d = vd, *n = vn, *m = vm; \ | ||
164 | + for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ | ||
165 | + d[i] = FUNC(n[i], m[i], stat); \ | ||
166 | + } \ | ||
167 | +} | ||
168 | + | ||
169 | +DO_3OP(gvec_fadd_h, float16_add, float16) | ||
170 | +DO_3OP(gvec_fadd_s, float32_add, float32) | ||
171 | +DO_3OP(gvec_fadd_d, float64_add, float64) | ||
172 | + | ||
173 | +DO_3OP(gvec_fsub_h, float16_sub, float16) | ||
174 | +DO_3OP(gvec_fsub_s, float32_sub, float32) | ||
175 | +DO_3OP(gvec_fsub_d, float64_sub, float64) | ||
176 | + | ||
177 | +DO_3OP(gvec_fmul_h, float16_mul, float16) | ||
178 | +DO_3OP(gvec_fmul_s, float32_mul, float32) | ||
179 | +DO_3OP(gvec_fmul_d, float64_mul, float64) | ||
180 | + | ||
181 | +DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16) | ||
182 | +DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32) | ||
183 | +DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64) | ||
184 | + | ||
185 | +#ifdef TARGET_AARCH64 | ||
186 | + | ||
187 | +DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) | ||
188 | +DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) | ||
189 | +DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) | ||
190 | + | ||
191 | +DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) | ||
192 | +DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) | ||
193 | +DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) | ||
194 | + | ||
195 | +#endif | ||
196 | +#undef DO_3OP | ||
197 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
198 | index XXXXXXX..XXXXXXX 100644 | ||
199 | --- a/target/arm/sve.decode | ||
200 | +++ b/target/arm/sve.decode | ||
201 | @@ -XXX,XX +XXX,XX @@ UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | ||
202 | # SVE integer multiply immediate (unpredicated) | ||
203 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | ||
204 | |||
205 | +### SVE Floating Point Arithmetic - Unpredicated Group | ||
206 | + | ||
207 | +# SVE floating-point arithmetic (unpredicated) | ||
208 | +FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | ||
209 | +FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | ||
210 | +FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | ||
211 | +FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | ||
212 | +FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | ||
213 | +FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | ||
214 | + | ||
215 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
216 | |||
217 | # SVE load predicate register | ||
218 | -- | 32 | -- |
219 | 2.17.1 | 33 | 2.25.1 |
220 | 34 | ||
221 | 35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | gicv3_set_gicv3state() is used by arm_gicv3_common.c in | ||
4 | arm_gicv3_common_realize(). Since we want to restrict | ||
5 | arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state() | ||
6 | to a new file. Add this file to the meson 'specific' | ||
7 | source set, since it needs access to "cpu.h". | ||
8 | |||
9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Message-id: 20211115223619.2599282-2-philmd@redhat.com |
5 | Message-id: 20180613015641.5667-15-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/helper-sve.h | 2 + | 14 | hw/intc/arm_gicv3_cpuif.c | 10 +--------- |
9 | target/arm/sve_helper.c | 14 ++++ | 15 | hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++ |
10 | target/arm/translate-sve.c | 133 +++++++++++++++++++++++++++++++++++++ | 16 | hw/intc/meson.build | 1 + |
11 | target/arm/sve.decode | 27 ++++++++ | 17 | 3 files changed, 24 insertions(+), 9 deletions(-) |
12 | 4 files changed, 176 insertions(+) | 18 | create mode 100644 hw/intc/arm_gicv3_cpuif_common.c |
13 | 19 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 20 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 22 | --- a/hw/intc/arm_gicv3_cpuif.c |
17 | +++ b/target/arm/helper-sve.h | 23 | +++ b/hw/intc/arm_gicv3_cpuif.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_brkbs_m, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
19 | |||
20 | DEF_HELPER_FLAGS_4(sve_brkn, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
21 | DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
22 | + | ||
23 | +DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) | ||
24 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/sve_helper.c | ||
27 | +++ b/target/arm/sve_helper.c | ||
28 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
29 | return do_zero(vd, oprsz); | ||
30 | } | ||
31 | } | ||
32 | + | ||
33 | +uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc) | ||
34 | +{ | ||
35 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
36 | + intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | ||
37 | + uint64_t *n = vn, *g = vg, sum = 0, mask = pred_esz_masks[esz]; | ||
38 | + intptr_t i; | ||
39 | + | ||
40 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) { | ||
41 | + uint64_t t = n[i] & g[i] & mask; | ||
42 | + sum += ctpop64(t); | ||
43 | + } | ||
44 | + return sum; | ||
45 | +} | ||
46 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/translate-sve.c | ||
49 | +++ b/target/arm/translate-sve.c | ||
50 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
51 | #include "translate-a64.h" | 25 | /* |
52 | 26 | - * ARM Generic Interrupt Controller v3 | |
53 | 27 | + * ARM Generic Interrupt Controller v3 (emulation) | |
54 | +typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, | 28 | * |
55 | + TCGv_i64, uint32_t, uint32_t); | 29 | * Copyright (c) 2016 Linaro Limited |
56 | + | 30 | * Written by Peter Maydell |
57 | typedef void gen_helper_gvec_flags_3(TCGv_i32, TCGv_ptr, TCGv_ptr, | 31 | @@ -XXX,XX +XXX,XX @@ |
58 | TCGv_ptr, TCGv_i32); | 32 | #include "hw/irq.h" |
59 | typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr, | 33 | #include "cpu.h" |
60 | @@ -XXX,XX +XXX,XX @@ static bool trans_BRKN(DisasContext *s, arg_rpr_s *a, uint32_t insn) | 34 | |
61 | return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns); | 35 | -void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) |
62 | } | 36 | -{ |
63 | 37 | - ARMCPU *arm_cpu = ARM_CPU(cpu); | |
38 | - CPUARMState *env = &arm_cpu->env; | ||
39 | - | ||
40 | - env->gicv3state = (void *)s; | ||
41 | -}; | ||
42 | - | ||
43 | static GICv3CPUState *icc_cs_from_env(CPUARMState *env) | ||
44 | { | ||
45 | return env->gicv3state; | ||
46 | diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c | ||
47 | new file mode 100644 | ||
48 | index XXXXXXX..XXXXXXX | ||
49 | --- /dev/null | ||
50 | +++ b/hw/intc/arm_gicv3_cpuif_common.c | ||
51 | @@ -XXX,XX +XXX,XX @@ | ||
52 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
64 | +/* | 53 | +/* |
65 | + *** SVE Predicate Count Group | 54 | + * ARM Generic Interrupt Controller v3 |
55 | + * | ||
56 | + * Copyright (c) 2016 Linaro Limited | ||
57 | + * Written by Peter Maydell | ||
58 | + * | ||
59 | + * This code is licensed under the GPL, version 2 or (at your option) | ||
60 | + * any later version. | ||
66 | + */ | 61 | + */ |
67 | + | 62 | + |
68 | +static void do_cntp(DisasContext *s, TCGv_i64 val, int esz, int pn, int pg) | 63 | +#include "qemu/osdep.h" |
64 | +#include "gicv3_internal.h" | ||
65 | +#include "cpu.h" | ||
66 | + | ||
67 | +void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) | ||
69 | +{ | 68 | +{ |
70 | + unsigned psz = pred_full_reg_size(s); | 69 | + ARMCPU *arm_cpu = ARM_CPU(cpu); |
70 | + CPUARMState *env = &arm_cpu->env; | ||
71 | + | 71 | + |
72 | + if (psz <= 8) { | 72 | + env->gicv3state = (void *)s; |
73 | + uint64_t psz_mask; | 73 | +}; |
74 | + | 74 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build |
75 | + tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn)); | ||
76 | + if (pn != pg) { | ||
77 | + TCGv_i64 g = tcg_temp_new_i64(); | ||
78 | + tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); | ||
79 | + tcg_gen_and_i64(val, val, g); | ||
80 | + tcg_temp_free_i64(g); | ||
81 | + } | ||
82 | + | ||
83 | + /* Reduce the pred_esz_masks value simply to reduce the | ||
84 | + * size of the code generated here. | ||
85 | + */ | ||
86 | + psz_mask = MAKE_64BIT_MASK(0, psz * 8); | ||
87 | + tcg_gen_andi_i64(val, val, pred_esz_masks[esz] & psz_mask); | ||
88 | + | ||
89 | + tcg_gen_ctpop_i64(val, val); | ||
90 | + } else { | ||
91 | + TCGv_ptr t_pn = tcg_temp_new_ptr(); | ||
92 | + TCGv_ptr t_pg = tcg_temp_new_ptr(); | ||
93 | + unsigned desc; | ||
94 | + TCGv_i32 t_desc; | ||
95 | + | ||
96 | + desc = psz - 2; | ||
97 | + desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz); | ||
98 | + | ||
99 | + tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); | ||
100 | + tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); | ||
101 | + t_desc = tcg_const_i32(desc); | ||
102 | + | ||
103 | + gen_helper_sve_cntp(val, t_pn, t_pg, t_desc); | ||
104 | + tcg_temp_free_ptr(t_pn); | ||
105 | + tcg_temp_free_ptr(t_pg); | ||
106 | + tcg_temp_free_i32(t_desc); | ||
107 | + } | ||
108 | +} | ||
109 | + | ||
110 | +static bool trans_CNTP(DisasContext *s, arg_CNTP *a, uint32_t insn) | ||
111 | +{ | ||
112 | + if (sve_access_check(s)) { | ||
113 | + do_cntp(s, cpu_reg(s, a->rd), a->esz, a->rn, a->pg); | ||
114 | + } | ||
115 | + return true; | ||
116 | +} | ||
117 | + | ||
118 | +static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a, | ||
119 | + uint32_t insn) | ||
120 | +{ | ||
121 | + if (sve_access_check(s)) { | ||
122 | + TCGv_i64 reg = cpu_reg(s, a->rd); | ||
123 | + TCGv_i64 val = tcg_temp_new_i64(); | ||
124 | + | ||
125 | + do_cntp(s, val, a->esz, a->pg, a->pg); | ||
126 | + if (a->d) { | ||
127 | + tcg_gen_sub_i64(reg, reg, val); | ||
128 | + } else { | ||
129 | + tcg_gen_add_i64(reg, reg, val); | ||
130 | + } | ||
131 | + tcg_temp_free_i64(val); | ||
132 | + } | ||
133 | + return true; | ||
134 | +} | ||
135 | + | ||
136 | +static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a, | ||
137 | + uint32_t insn) | ||
138 | +{ | ||
139 | + if (a->esz == 0) { | ||
140 | + return false; | ||
141 | + } | ||
142 | + if (sve_access_check(s)) { | ||
143 | + unsigned vsz = vec_full_reg_size(s); | ||
144 | + TCGv_i64 val = tcg_temp_new_i64(); | ||
145 | + GVecGen2sFn *gvec_fn = a->d ? tcg_gen_gvec_subs : tcg_gen_gvec_adds; | ||
146 | + | ||
147 | + do_cntp(s, val, a->esz, a->pg, a->pg); | ||
148 | + gvec_fn(a->esz, vec_full_reg_offset(s, a->rd), | ||
149 | + vec_full_reg_offset(s, a->rn), val, vsz, vsz); | ||
150 | + } | ||
151 | + return true; | ||
152 | +} | ||
153 | + | ||
154 | +static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a, | ||
155 | + uint32_t insn) | ||
156 | +{ | ||
157 | + if (sve_access_check(s)) { | ||
158 | + TCGv_i64 reg = cpu_reg(s, a->rd); | ||
159 | + TCGv_i64 val = tcg_temp_new_i64(); | ||
160 | + | ||
161 | + do_cntp(s, val, a->esz, a->pg, a->pg); | ||
162 | + do_sat_addsub_32(reg, val, a->u, a->d); | ||
163 | + } | ||
164 | + return true; | ||
165 | +} | ||
166 | + | ||
167 | +static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a, | ||
168 | + uint32_t insn) | ||
169 | +{ | ||
170 | + if (sve_access_check(s)) { | ||
171 | + TCGv_i64 reg = cpu_reg(s, a->rd); | ||
172 | + TCGv_i64 val = tcg_temp_new_i64(); | ||
173 | + | ||
174 | + do_cntp(s, val, a->esz, a->pg, a->pg); | ||
175 | + do_sat_addsub_64(reg, val, a->u, a->d); | ||
176 | + } | ||
177 | + return true; | ||
178 | +} | ||
179 | + | ||
180 | +static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a, | ||
181 | + uint32_t insn) | ||
182 | +{ | ||
183 | + if (a->esz == 0) { | ||
184 | + return false; | ||
185 | + } | ||
186 | + if (sve_access_check(s)) { | ||
187 | + TCGv_i64 val = tcg_temp_new_i64(); | ||
188 | + do_cntp(s, val, a->esz, a->pg, a->pg); | ||
189 | + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, a->u, a->d); | ||
190 | + } | ||
191 | + return true; | ||
192 | +} | ||
193 | + | ||
194 | /* | ||
195 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
196 | */ | ||
197 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
198 | index XXXXXXX..XXXXXXX 100644 | 75 | index XXXXXXX..XXXXXXX 100644 |
199 | --- a/target/arm/sve.decode | 76 | --- a/hw/intc/meson.build |
200 | +++ b/target/arm/sve.decode | 77 | +++ b/hw/intc/meson.build |
201 | @@ -XXX,XX +XXX,XX @@ | 78 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in |
202 | &ptrue rd esz pat s | 79 | |
203 | &incdec_cnt rd pat esz imm d u | 80 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) |
204 | &incdec2_cnt rd rn pat esz imm d u | 81 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) |
205 | +&incdec_pred rd pg esz d u | 82 | +specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) |
206 | +&incdec2_pred rd rn pg esz d u | 83 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) |
207 | 84 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) | |
208 | ########################################################################### | 85 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) |
209 | # Named instruction formats. These are generally used to | ||
210 | @@ -XXX,XX +XXX,XX @@ | ||
211 | |||
212 | # One register operand, with governing predicate, vector element size | ||
213 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | ||
214 | +@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz | ||
215 | |||
216 | # Two register operands with a 6-bit signed immediate. | ||
217 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | ||
218 | @@ -XXX,XX +XXX,XX @@ | ||
219 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | ||
220 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | ||
221 | |||
222 | +# One register, predicate. | ||
223 | +# User must fill in U and D. | ||
224 | +@incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | ||
225 | +@incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | ||
226 | + &incdec2_pred rn=%reg_movprfx | ||
227 | + | ||
228 | ########################################################################### | ||
229 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | ||
230 | |||
231 | @@ -XXX,XX +XXX,XX @@ BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | ||
232 | # SVE propagate break to next partition | ||
233 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | ||
234 | |||
235 | +### SVE Predicate Count Group | ||
236 | + | ||
237 | +# SVE predicate count | ||
238 | +CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | ||
239 | + | ||
240 | +# SVE inc/dec register by predicate count | ||
241 | +INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | ||
242 | + | ||
243 | +# SVE inc/dec vector by predicate count | ||
244 | +INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | ||
245 | + | ||
246 | +# SVE saturating inc/dec register by predicate count | ||
247 | +SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | ||
248 | +SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | ||
249 | + | ||
250 | +# SVE saturating inc/dec vector by predicate count | ||
251 | +SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | ||
252 | + | ||
253 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
254 | |||
255 | # SVE load predicate register | ||
256 | -- | 86 | -- |
257 | 2.17.1 | 87 | 2.25.1 |
258 | 88 | ||
259 | 89 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | The TYPE_ARM_GICV3 device is an emulated one. When using | ||
4 | KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device | ||
5 | (which uses in-kernel support). | ||
6 | |||
7 | When using --with-devices-FOO, it is possible to build a | ||
8 | binary with a specific set of devices. When this binary is | ||
9 | restricted to KVM accelerator, the TYPE_ARM_GICV3 device is | ||
10 | irrelevant, and it is desirable to remove it from the binary. | ||
11 | |||
12 | Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector | ||
13 | which select the files required to have the TYPE_ARM_GICV3 | ||
14 | device, but also allowing to de-select this device. | ||
15 | |||
16 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Message-id: 20211115223619.2599282-3-philmd@redhat.com |
5 | Message-id: 20180613015641.5667-10-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 20 | --- |
8 | target/arm/helper-sve.h | 2 ++ | 21 | hw/intc/arm_gicv3.c | 2 +- |
9 | target/arm/sve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ | 22 | hw/intc/Kconfig | 5 +++++ |
10 | target/arm/translate-sve.c | 13 +++++++++++++ | 23 | hw/intc/meson.build | 10 ++++++---- |
11 | target/arm/sve.decode | 3 +++ | 24 | 3 files changed, 12 insertions(+), 5 deletions(-) |
12 | 4 files changed, 55 insertions(+) | ||
13 | 25 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 26 | diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c |
15 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 28 | --- a/hw/intc/arm_gicv3.c |
17 | +++ b/target/arm/helper-sve.h | 29 | +++ b/hw/intc/arm_gicv3.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 30 | @@ -XXX,XX +XXX,XX @@ |
19 | DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 31 | /* |
20 | DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 32 | - * ARM Generic Interrupt Controller v3 |
21 | 33 | + * ARM Generic Interrupt Controller v3 (emulation) | |
22 | +DEF_HELPER_FLAGS_5(sve_splice, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 34 | * |
35 | * Copyright (c) 2015 Huawei. | ||
36 | * Copyright (c) 2016 Linaro Limited | ||
37 | diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/intc/Kconfig | ||
40 | +++ b/hw/intc/Kconfig | ||
41 | @@ -XXX,XX +XXX,XX @@ config APIC | ||
42 | select MSI_NONBROKEN | ||
43 | select I8259 | ||
44 | |||
45 | +config ARM_GIC_TCG | ||
46 | + bool | ||
47 | + default y | ||
48 | + depends on ARM_GIC && TCG | ||
23 | + | 49 | + |
24 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 50 | config ARM_GIC_KVM |
25 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 51 | bool |
26 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 52 | default y |
27 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 53 | diff --git a/hw/intc/meson.build b/hw/intc/meson.build |
28 | index XXXXXXX..XXXXXXX 100644 | 54 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/target/arm/sve_helper.c | 55 | --- a/hw/intc/meson.build |
30 | +++ b/target/arm/sve_helper.c | 56 | +++ b/hw/intc/meson.build |
31 | @@ -XXX,XX +XXX,XX @@ int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc) | 57 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files( |
32 | 58 | 'arm_gic.c', | |
33 | return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz); | 59 | 'arm_gic_common.c', |
34 | } | 60 | 'arm_gicv2m.c', |
35 | + | 61 | - 'arm_gicv3.c', |
36 | +void HELPER(sve_splice)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) | 62 | 'arm_gicv3_common.c', |
37 | +{ | 63 | - 'arm_gicv3_dist.c', |
38 | + intptr_t opr_sz = simd_oprsz(desc) / 8; | 64 | 'arm_gicv3_its_common.c', |
39 | + int esz = simd_data(desc); | 65 | - 'arm_gicv3_redist.c', |
40 | + uint64_t pg, first_g, last_g, len, mask = pred_esz_masks[esz]; | 66 | +)) |
41 | + intptr_t i, first_i, last_i; | 67 | +softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files( |
42 | + ARMVectorReg tmp; | 68 | + 'arm_gicv3.c', |
43 | + | 69 | + 'arm_gicv3_dist.c', |
44 | + first_i = last_i = 0; | 70 | 'arm_gicv3_its.c', |
45 | + first_g = last_g = 0; | 71 | + 'arm_gicv3_redist.c', |
46 | + | 72 | )) |
47 | + /* Find the extent of the active elements within VG. */ | 73 | softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c')) |
48 | + for (i = QEMU_ALIGN_UP(opr_sz, 8) - 8; i >= 0; i -= 8) { | 74 | softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c')) |
49 | + pg = *(uint64_t *)(vg + i) & mask; | 75 | @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in |
50 | + if (pg) { | 76 | specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c')) |
51 | + if (last_g == 0) { | 77 | specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c')) |
52 | + last_g = pg; | 78 | specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c')) |
53 | + last_i = i; | 79 | -specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c')) |
54 | + } | 80 | +specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c')) |
55 | + first_g = pg; | 81 | specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c')) |
56 | + first_i = i; | 82 | specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) |
57 | + } | 83 | specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) |
58 | + } | ||
59 | + | ||
60 | + len = 0; | ||
61 | + if (first_g != 0) { | ||
62 | + first_i = first_i * 8 + ctz64(first_g); | ||
63 | + last_i = last_i * 8 + 63 - clz64(last_g); | ||
64 | + len = last_i - first_i + (1 << esz); | ||
65 | + if (vd == vm) { | ||
66 | + vm = memcpy(&tmp, vm, opr_sz * 8); | ||
67 | + } | ||
68 | + swap_memmove(vd, vn + first_i, len); | ||
69 | + } | ||
70 | + swap_memmove(vd + len, vm, opr_sz * 8 - len); | ||
71 | +} | ||
72 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/target/arm/translate-sve.c | ||
75 | +++ b/target/arm/translate-sve.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
77 | return do_zpz_ool(s, a, fns[a->esz]); | ||
78 | } | ||
79 | |||
80 | +static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | ||
81 | +{ | ||
82 | + if (sve_access_check(s)) { | ||
83 | + unsigned vsz = vec_full_reg_size(s); | ||
84 | + tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd), | ||
85 | + vec_full_reg_offset(s, a->rn), | ||
86 | + vec_full_reg_offset(s, a->rm), | ||
87 | + pred_full_reg_offset(s, a->pg), | ||
88 | + vsz, vsz, a->esz, gen_helper_sve_splice); | ||
89 | + } | ||
90 | + return true; | ||
91 | +} | ||
92 | + | ||
93 | /* | ||
94 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
95 | */ | ||
96 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/target/arm/sve.decode | ||
99 | +++ b/target/arm/sve.decode | ||
100 | @@ -XXX,XX +XXX,XX @@ REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | ||
101 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | ||
102 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | ||
103 | |||
104 | +# SVE vector splice (predicated) | ||
105 | +SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | ||
106 | + | ||
107 | ### SVE Predicate Logical Operations Group | ||
108 | |||
109 | # SVE predicate logical operations | ||
110 | -- | 84 | -- |
111 | 2.17.1 | 85 | 2.25.1 |
112 | 86 | ||
113 | 87 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Message-id: 20180613015641.5667-16-richard.henderson@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 6 | --- |
8 | target/arm/helper-sve.h | 2 + | 7 | target/arm/translate-a64.c | 7 ++++--- |
9 | target/arm/sve_helper.c | 31 ++++++++++++ | 8 | 1 file changed, 4 insertions(+), 3 deletions(-) |
10 | target/arm/translate-sve.c | 99 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/sve.decode | 8 +++ | ||
12 | 4 files changed, 140 insertions(+) | ||
13 | 9 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 10 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
15 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 12 | --- a/target/arm/translate-a64.c |
17 | +++ b/target/arm/helper-sve.h | 13 | +++ b/target/arm/translate-a64.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_brkn, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 14 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
19 | DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 15 | { |
20 | 16 | DisasContext *s = container_of(dcbase, DisasContext, base); | |
21 | DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) | 17 | CPUARMState *env = cpu->env_ptr; |
22 | + | 18 | + uint64_t pc = s->base.pc_next; |
23 | +DEF_HELPER_FLAGS_3(sve_while, TCG_CALL_NO_RWG, i32, ptr, i32, i32) | 19 | uint32_t insn; |
24 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 20 | |
25 | index XXXXXXX..XXXXXXX 100644 | 21 | if (s->ss_active && !s->pstate_ss) { |
26 | --- a/target/arm/sve_helper.c | 22 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
27 | +++ b/target/arm/sve_helper.c | 23 | return; |
28 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc) | ||
29 | } | 24 | } |
30 | return sum; | 25 | |
31 | } | 26 | - s->pc_curr = s->base.pc_next; |
32 | + | 27 | - insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b); |
33 | +uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) | 28 | + s->pc_curr = pc; |
34 | +{ | 29 | + insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); |
35 | + uintptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | 30 | s->insn = insn; |
36 | + intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | 31 | - s->base.pc_next += 4; |
37 | + uint64_t esz_mask = pred_esz_masks[esz]; | 32 | + s->base.pc_next = pc + 4; |
38 | + ARMPredicateReg *d = vd; | 33 | |
39 | + uint32_t flags; | 34 | s->fp_access_checked = false; |
40 | + intptr_t i; | 35 | s->sve_access_checked = false; |
41 | + | ||
42 | + /* Begin with a zero predicate register. */ | ||
43 | + flags = do_zero(d, oprsz); | ||
44 | + if (count == 0) { | ||
45 | + return flags; | ||
46 | + } | ||
47 | + | ||
48 | + /* Scale from predicate element count to bits. */ | ||
49 | + count <<= esz; | ||
50 | + /* Bound to the bits in the predicate. */ | ||
51 | + count = MIN(count, oprsz * 8); | ||
52 | + | ||
53 | + /* Set all of the requested bits. */ | ||
54 | + for (i = 0; i < count / 64; ++i) { | ||
55 | + d->p[i] = esz_mask; | ||
56 | + } | ||
57 | + if (count & 63) { | ||
58 | + d->p[i] = MAKE_64BIT_MASK(0, count & 63) & esz_mask; | ||
59 | + } | ||
60 | + | ||
61 | + return predtest_ones(d, oprsz, esz_mask); | ||
62 | +} | ||
63 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/translate-sve.c | ||
66 | +++ b/target/arm/translate-sve.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a, | ||
68 | return true; | ||
69 | } | ||
70 | |||
71 | +/* | ||
72 | + *** SVE Integer Compare Scalars Group | ||
73 | + */ | ||
74 | + | ||
75 | +static bool trans_CTERM(DisasContext *s, arg_CTERM *a, uint32_t insn) | ||
76 | +{ | ||
77 | + if (!sve_access_check(s)) { | ||
78 | + return true; | ||
79 | + } | ||
80 | + | ||
81 | + TCGCond cond = (a->ne ? TCG_COND_NE : TCG_COND_EQ); | ||
82 | + TCGv_i64 rn = read_cpu_reg(s, a->rn, a->sf); | ||
83 | + TCGv_i64 rm = read_cpu_reg(s, a->rm, a->sf); | ||
84 | + TCGv_i64 cmp = tcg_temp_new_i64(); | ||
85 | + | ||
86 | + tcg_gen_setcond_i64(cond, cmp, rn, rm); | ||
87 | + tcg_gen_extrl_i64_i32(cpu_NF, cmp); | ||
88 | + tcg_temp_free_i64(cmp); | ||
89 | + | ||
90 | + /* VF = !NF & !CF. */ | ||
91 | + tcg_gen_xori_i32(cpu_VF, cpu_NF, 1); | ||
92 | + tcg_gen_andc_i32(cpu_VF, cpu_VF, cpu_CF); | ||
93 | + | ||
94 | + /* Both NF and VF actually look at bit 31. */ | ||
95 | + tcg_gen_neg_i32(cpu_NF, cpu_NF); | ||
96 | + tcg_gen_neg_i32(cpu_VF, cpu_VF); | ||
97 | + return true; | ||
98 | +} | ||
99 | + | ||
100 | +static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) | ||
101 | +{ | ||
102 | + if (!sve_access_check(s)) { | ||
103 | + return true; | ||
104 | + } | ||
105 | + | ||
106 | + TCGv_i64 op0 = read_cpu_reg(s, a->rn, 1); | ||
107 | + TCGv_i64 op1 = read_cpu_reg(s, a->rm, 1); | ||
108 | + TCGv_i64 t0 = tcg_temp_new_i64(); | ||
109 | + TCGv_i64 t1 = tcg_temp_new_i64(); | ||
110 | + TCGv_i32 t2, t3; | ||
111 | + TCGv_ptr ptr; | ||
112 | + unsigned desc, vsz = vec_full_reg_size(s); | ||
113 | + TCGCond cond; | ||
114 | + | ||
115 | + if (!a->sf) { | ||
116 | + if (a->u) { | ||
117 | + tcg_gen_ext32u_i64(op0, op0); | ||
118 | + tcg_gen_ext32u_i64(op1, op1); | ||
119 | + } else { | ||
120 | + tcg_gen_ext32s_i64(op0, op0); | ||
121 | + tcg_gen_ext32s_i64(op1, op1); | ||
122 | + } | ||
123 | + } | ||
124 | + | ||
125 | + /* For the helper, compress the different conditions into a computation | ||
126 | + * of how many iterations for which the condition is true. | ||
127 | + * | ||
128 | + * This is slightly complicated by 0 <= UINT64_MAX, which is nominally | ||
129 | + * 2**64 iterations, overflowing to 0. Of course, predicate registers | ||
130 | + * aren't that large, so any value >= predicate size is sufficient. | ||
131 | + */ | ||
132 | + tcg_gen_sub_i64(t0, op1, op0); | ||
133 | + | ||
134 | + /* t0 = MIN(op1 - op0, vsz). */ | ||
135 | + tcg_gen_movi_i64(t1, vsz); | ||
136 | + tcg_gen_umin_i64(t0, t0, t1); | ||
137 | + if (a->eq) { | ||
138 | + /* Equality means one more iteration. */ | ||
139 | + tcg_gen_addi_i64(t0, t0, 1); | ||
140 | + } | ||
141 | + | ||
142 | + /* t0 = (condition true ? t0 : 0). */ | ||
143 | + cond = (a->u | ||
144 | + ? (a->eq ? TCG_COND_LEU : TCG_COND_LTU) | ||
145 | + : (a->eq ? TCG_COND_LE : TCG_COND_LT)); | ||
146 | + tcg_gen_movi_i64(t1, 0); | ||
147 | + tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); | ||
148 | + | ||
149 | + t2 = tcg_temp_new_i32(); | ||
150 | + tcg_gen_extrl_i64_i32(t2, t0); | ||
151 | + tcg_temp_free_i64(t0); | ||
152 | + tcg_temp_free_i64(t1); | ||
153 | + | ||
154 | + desc = (vsz / 8) - 2; | ||
155 | + desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); | ||
156 | + t3 = tcg_const_i32(desc); | ||
157 | + | ||
158 | + ptr = tcg_temp_new_ptr(); | ||
159 | + tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
160 | + | ||
161 | + gen_helper_sve_while(t2, ptr, t2, t3); | ||
162 | + do_pred_flags(t2); | ||
163 | + | ||
164 | + tcg_temp_free_ptr(ptr); | ||
165 | + tcg_temp_free_i32(t2); | ||
166 | + tcg_temp_free_i32(t3); | ||
167 | + return true; | ||
168 | +} | ||
169 | + | ||
170 | /* | ||
171 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
172 | */ | ||
173 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
174 | index XXXXXXX..XXXXXXX 100644 | ||
175 | --- a/target/arm/sve.decode | ||
176 | +++ b/target/arm/sve.decode | ||
177 | @@ -XXX,XX +XXX,XX @@ SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | ||
178 | # SVE saturating inc/dec vector by predicate count | ||
179 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | ||
180 | |||
181 | +### SVE Integer Compare - Scalars Group | ||
182 | + | ||
183 | +# SVE conditionally terminate scalars | ||
184 | +CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | ||
185 | + | ||
186 | +# SVE integer compare scalar count and limit | ||
187 | +WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 | ||
188 | + | ||
189 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
190 | |||
191 | # SVE load predicate register | ||
192 | -- | 36 | -- |
193 | 2.17.1 | 37 | 2.25.1 |
194 | 38 | ||
195 | 39 | diff view generated by jsdifflib |
1 | From: Julia Suvorova <jusual@mail.ru> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | ARMv6-M supports 6 Thumb2 instructions. This patch checks for these | 3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | instructions and allows their execution. | ||
5 | Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit. | ||
6 | |||
7 | This patch is required for future Cortex-M0 support. | ||
8 | |||
9 | Signed-off-by: Julia Suvorova <jusual@mail.ru> | ||
10 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
11 | Message-id: 20180612204632.28780-1-jusual@mail.ru | ||
12 | [PMM: move armv6m_insn[] and armv6m_mask[] closer to | ||
13 | point of use, and mark 'const'. Check for M-and-not-v7 | ||
14 | rather than M-and-6.] | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 6 | --- |
18 | target/arm/translate.c | 43 +++++++++++++++++++++++++++++++++++++----- | 7 | target/arm/translate.c | 9 +++++---- |
19 | 1 file changed, 38 insertions(+), 5 deletions(-) | 8 | 1 file changed, 5 insertions(+), 4 deletions(-) |
20 | 9 | ||
21 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 10 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
22 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/target/arm/translate.c | 12 | --- a/target/arm/translate.c |
24 | +++ b/target/arm/translate.c | 13 | +++ b/target/arm/translate.c |
25 | @@ -XXX,XX +XXX,XX @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) | 14 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
26 | * end up actually treating this as two 16-bit insns, though, | 15 | { |
27 | * if it's half of a bl/blx pair that might span a page boundary. | 16 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
28 | */ | 17 | CPUARMState *env = cpu->env_ptr; |
29 | - if (arm_dc_feature(s, ARM_FEATURE_THUMB2)) { | 18 | + uint32_t pc = dc->base.pc_next; |
30 | + if (arm_dc_feature(s, ARM_FEATURE_THUMB2) || | 19 | unsigned int insn; |
31 | + arm_dc_feature(s, ARM_FEATURE_M)) { | 20 | |
32 | /* Thumb2 cores (including all M profile ones) always treat | 21 | if (arm_pre_translate_insn(dc)) { |
33 | * 32-bit insns as 32-bit. | 22 | - dc->base.pc_next += 4; |
34 | */ | 23 | + dc->base.pc_next = pc + 4; |
35 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 24 | return; |
36 | int conds; | ||
37 | int logic_cc; | ||
38 | |||
39 | - /* The only 32 bit insn that's allowed for Thumb1 is the combined | ||
40 | - * BL/BLX prefix and suffix. | ||
41 | + /* | ||
42 | + * ARMv6-M supports a limited subset of Thumb2 instructions. | ||
43 | + * Other Thumb1 architectures allow only 32-bit | ||
44 | + * combined BL/BLX prefix and suffix. | ||
45 | */ | ||
46 | - if ((insn & 0xf800e800) != 0xf000e800) { | ||
47 | + if (arm_dc_feature(s, ARM_FEATURE_M) && | ||
48 | + !arm_dc_feature(s, ARM_FEATURE_V7)) { | ||
49 | + int i; | ||
50 | + bool found = false; | ||
51 | + const uint32_t armv6m_insn[] = {0xf3808000 /* msr */, | ||
52 | + 0xf3b08040 /* dsb */, | ||
53 | + 0xf3b08050 /* dmb */, | ||
54 | + 0xf3b08060 /* isb */, | ||
55 | + 0xf3e08000 /* mrs */, | ||
56 | + 0xf000d000 /* bl */}; | ||
57 | + const uint32_t armv6m_mask[] = {0xffe0d000, | ||
58 | + 0xfff0d0f0, | ||
59 | + 0xfff0d0f0, | ||
60 | + 0xfff0d0f0, | ||
61 | + 0xffe0d000, | ||
62 | + 0xf800d000}; | ||
63 | + | ||
64 | + for (i = 0; i < ARRAY_SIZE(armv6m_insn); i++) { | ||
65 | + if ((insn & armv6m_mask[i]) == armv6m_insn[i]) { | ||
66 | + found = true; | ||
67 | + break; | ||
68 | + } | ||
69 | + } | ||
70 | + if (!found) { | ||
71 | + goto illegal_op; | ||
72 | + } | ||
73 | + } else if ((insn & 0xf800e800) != 0xf000e800) { | ||
74 | ARCH(6T2); | ||
75 | } | 25 | } |
76 | 26 | ||
77 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 27 | - dc->pc_curr = dc->base.pc_next; |
78 | } | 28 | - insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); |
79 | break; | 29 | + dc->pc_curr = pc; |
80 | case 3: /* Special control operations. */ | 30 | + insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b); |
81 | - ARCH(7); | 31 | dc->insn = insn; |
82 | + if (!arm_dc_feature(s, ARM_FEATURE_V7) && | 32 | - dc->base.pc_next += 4; |
83 | + !(arm_dc_feature(s, ARM_FEATURE_V6) && | 33 | + dc->base.pc_next = pc + 4; |
84 | + arm_dc_feature(s, ARM_FEATURE_M))) { | 34 | disas_arm_insn(dc, insn); |
85 | + goto illegal_op; | 35 | |
86 | + } | 36 | arm_post_translate_insn(dc); |
87 | op = (insn >> 4) & 0xf; | ||
88 | switch (op) { | ||
89 | case 2: /* clrex */ | ||
90 | -- | 37 | -- |
91 | 2.17.1 | 38 | 2.25.1 |
92 | 39 | ||
93 | 40 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180613015641.5667-13-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 6 | --- |
8 | target/arm/helper-sve.h | 44 +++++++++++++++++++ | 7 | target/arm/translate.c | 16 ++++++++-------- |
9 | target/arm/sve_helper.c | 88 ++++++++++++++++++++++++++++++++++++++ | 8 | 1 file changed, 8 insertions(+), 8 deletions(-) |
10 | target/arm/translate-sve.c | 66 ++++++++++++++++++++++++++++ | ||
11 | target/arm/sve.decode | 23 ++++++++++ | ||
12 | 4 files changed, 221 insertions(+) | ||
13 | 9 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 10 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 12 | --- a/target/arm/translate.c |
17 | +++ b/target/arm/helper-sve.h | 13 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_s, TCG_CALL_NO_RWG, | 14 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
19 | DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_s, TCG_CALL_NO_RWG, | 15 | { |
20 | i32, ptr, ptr, ptr, ptr, i32) | 16 | DisasContext *dc = container_of(dcbase, DisasContext, base); |
21 | 17 | CPUARMState *env = cpu->env_ptr; | |
22 | +DEF_HELPER_FLAGS_4(sve_cmpeq_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 18 | + uint32_t pc = dc->base.pc_next; |
23 | +DEF_HELPER_FLAGS_4(sve_cmpne_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 19 | uint32_t insn; |
24 | +DEF_HELPER_FLAGS_4(sve_cmpgt_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 20 | bool is_16bit; |
25 | +DEF_HELPER_FLAGS_4(sve_cmpge_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 21 | |
26 | +DEF_HELPER_FLAGS_4(sve_cmplt_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 22 | if (arm_pre_translate_insn(dc)) { |
27 | +DEF_HELPER_FLAGS_4(sve_cmple_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 23 | - dc->base.pc_next += 2; |
28 | +DEF_HELPER_FLAGS_4(sve_cmphs_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 24 | + dc->base.pc_next = pc + 2; |
29 | +DEF_HELPER_FLAGS_4(sve_cmphi_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 25 | return; |
30 | +DEF_HELPER_FLAGS_4(sve_cmplo_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 26 | } |
31 | +DEF_HELPER_FLAGS_4(sve_cmpls_ppzi_b, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 27 | |
32 | + | 28 | - dc->pc_curr = dc->base.pc_next; |
33 | +DEF_HELPER_FLAGS_4(sve_cmpeq_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 29 | - insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b); |
34 | +DEF_HELPER_FLAGS_4(sve_cmpne_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 30 | + dc->pc_curr = pc; |
35 | +DEF_HELPER_FLAGS_4(sve_cmpgt_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 31 | + insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); |
36 | +DEF_HELPER_FLAGS_4(sve_cmpge_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 32 | is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn); |
37 | +DEF_HELPER_FLAGS_4(sve_cmplt_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 33 | - dc->base.pc_next += 2; |
38 | +DEF_HELPER_FLAGS_4(sve_cmple_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 34 | + pc += 2; |
39 | +DEF_HELPER_FLAGS_4(sve_cmphs_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 35 | if (!is_16bit) { |
40 | +DEF_HELPER_FLAGS_4(sve_cmphi_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 36 | - uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next, |
41 | +DEF_HELPER_FLAGS_4(sve_cmplo_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 37 | - dc->sctlr_b); |
42 | +DEF_HELPER_FLAGS_4(sve_cmpls_ppzi_h, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 38 | - |
43 | + | 39 | + uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b); |
44 | +DEF_HELPER_FLAGS_4(sve_cmpeq_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 40 | insn = insn << 16 | insn2; |
45 | +DEF_HELPER_FLAGS_4(sve_cmpne_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 41 | - dc->base.pc_next += 2; |
46 | +DEF_HELPER_FLAGS_4(sve_cmpgt_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 42 | + pc += 2; |
47 | +DEF_HELPER_FLAGS_4(sve_cmpge_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 43 | } |
48 | +DEF_HELPER_FLAGS_4(sve_cmplt_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 44 | + dc->base.pc_next = pc; |
49 | +DEF_HELPER_FLAGS_4(sve_cmple_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 45 | dc->insn = insn; |
50 | +DEF_HELPER_FLAGS_4(sve_cmphs_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 46 | |
51 | +DEF_HELPER_FLAGS_4(sve_cmphi_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 47 | if (dc->pstate_il) { |
52 | +DEF_HELPER_FLAGS_4(sve_cmplo_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
53 | +DEF_HELPER_FLAGS_4(sve_cmpls_ppzi_s, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
54 | + | ||
55 | +DEF_HELPER_FLAGS_4(sve_cmpeq_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
56 | +DEF_HELPER_FLAGS_4(sve_cmpne_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
57 | +DEF_HELPER_FLAGS_4(sve_cmpgt_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
58 | +DEF_HELPER_FLAGS_4(sve_cmpge_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
59 | +DEF_HELPER_FLAGS_4(sve_cmplt_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
60 | +DEF_HELPER_FLAGS_4(sve_cmple_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
61 | +DEF_HELPER_FLAGS_4(sve_cmphs_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
62 | +DEF_HELPER_FLAGS_4(sve_cmphi_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
63 | +DEF_HELPER_FLAGS_4(sve_cmplo_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
64 | +DEF_HELPER_FLAGS_4(sve_cmpls_ppzi_d, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
65 | + | ||
66 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
67 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
68 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
69 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/target/arm/sve_helper.c | ||
72 | +++ b/target/arm/sve_helper.c | ||
73 | @@ -XXX,XX +XXX,XX @@ DO_CMP_PPZW_S(sve_cmpls_ppzw_s, uint32_t, uint64_t, <=) | ||
74 | #undef DO_CMP_PPZW_H | ||
75 | #undef DO_CMP_PPZW_S | ||
76 | #undef DO_CMP_PPZW | ||
77 | + | ||
78 | +/* Similar, but the second source is immediate. */ | ||
79 | +#define DO_CMP_PPZI(NAME, TYPE, OP, H, MASK) \ | ||
80 | +uint32_t HELPER(NAME)(void *vd, void *vn, void *vg, uint32_t desc) \ | ||
81 | +{ \ | ||
82 | + intptr_t opr_sz = simd_oprsz(desc); \ | ||
83 | + uint32_t flags = PREDTEST_INIT; \ | ||
84 | + TYPE mm = simd_data(desc); \ | ||
85 | + intptr_t i = opr_sz; \ | ||
86 | + do { \ | ||
87 | + uint64_t out = 0, pg; \ | ||
88 | + do { \ | ||
89 | + i -= sizeof(TYPE), out <<= sizeof(TYPE); \ | ||
90 | + TYPE nn = *(TYPE *)(vn + H(i)); \ | ||
91 | + out |= nn OP mm; \ | ||
92 | + } while (i & 63); \ | ||
93 | + pg = *(uint64_t *)(vg + (i >> 3)) & MASK; \ | ||
94 | + out &= pg; \ | ||
95 | + *(uint64_t *)(vd + (i >> 3)) = out; \ | ||
96 | + flags = iter_predtest_bwd(out, pg, flags); \ | ||
97 | + } while (i > 0); \ | ||
98 | + return flags; \ | ||
99 | +} | ||
100 | + | ||
101 | +#define DO_CMP_PPZI_B(NAME, TYPE, OP) \ | ||
102 | + DO_CMP_PPZI(NAME, TYPE, OP, H1, 0xffffffffffffffffull) | ||
103 | +#define DO_CMP_PPZI_H(NAME, TYPE, OP) \ | ||
104 | + DO_CMP_PPZI(NAME, TYPE, OP, H1_2, 0x5555555555555555ull) | ||
105 | +#define DO_CMP_PPZI_S(NAME, TYPE, OP) \ | ||
106 | + DO_CMP_PPZI(NAME, TYPE, OP, H1_4, 0x1111111111111111ull) | ||
107 | +#define DO_CMP_PPZI_D(NAME, TYPE, OP) \ | ||
108 | + DO_CMP_PPZI(NAME, TYPE, OP, , 0x0101010101010101ull) | ||
109 | + | ||
110 | +DO_CMP_PPZI_B(sve_cmpeq_ppzi_b, uint8_t, ==) | ||
111 | +DO_CMP_PPZI_H(sve_cmpeq_ppzi_h, uint16_t, ==) | ||
112 | +DO_CMP_PPZI_S(sve_cmpeq_ppzi_s, uint32_t, ==) | ||
113 | +DO_CMP_PPZI_D(sve_cmpeq_ppzi_d, uint64_t, ==) | ||
114 | + | ||
115 | +DO_CMP_PPZI_B(sve_cmpne_ppzi_b, uint8_t, !=) | ||
116 | +DO_CMP_PPZI_H(sve_cmpne_ppzi_h, uint16_t, !=) | ||
117 | +DO_CMP_PPZI_S(sve_cmpne_ppzi_s, uint32_t, !=) | ||
118 | +DO_CMP_PPZI_D(sve_cmpne_ppzi_d, uint64_t, !=) | ||
119 | + | ||
120 | +DO_CMP_PPZI_B(sve_cmpgt_ppzi_b, int8_t, >) | ||
121 | +DO_CMP_PPZI_H(sve_cmpgt_ppzi_h, int16_t, >) | ||
122 | +DO_CMP_PPZI_S(sve_cmpgt_ppzi_s, int32_t, >) | ||
123 | +DO_CMP_PPZI_D(sve_cmpgt_ppzi_d, int64_t, >) | ||
124 | + | ||
125 | +DO_CMP_PPZI_B(sve_cmpge_ppzi_b, int8_t, >=) | ||
126 | +DO_CMP_PPZI_H(sve_cmpge_ppzi_h, int16_t, >=) | ||
127 | +DO_CMP_PPZI_S(sve_cmpge_ppzi_s, int32_t, >=) | ||
128 | +DO_CMP_PPZI_D(sve_cmpge_ppzi_d, int64_t, >=) | ||
129 | + | ||
130 | +DO_CMP_PPZI_B(sve_cmphi_ppzi_b, uint8_t, >) | ||
131 | +DO_CMP_PPZI_H(sve_cmphi_ppzi_h, uint16_t, >) | ||
132 | +DO_CMP_PPZI_S(sve_cmphi_ppzi_s, uint32_t, >) | ||
133 | +DO_CMP_PPZI_D(sve_cmphi_ppzi_d, uint64_t, >) | ||
134 | + | ||
135 | +DO_CMP_PPZI_B(sve_cmphs_ppzi_b, uint8_t, >=) | ||
136 | +DO_CMP_PPZI_H(sve_cmphs_ppzi_h, uint16_t, >=) | ||
137 | +DO_CMP_PPZI_S(sve_cmphs_ppzi_s, uint32_t, >=) | ||
138 | +DO_CMP_PPZI_D(sve_cmphs_ppzi_d, uint64_t, >=) | ||
139 | + | ||
140 | +DO_CMP_PPZI_B(sve_cmplt_ppzi_b, int8_t, <) | ||
141 | +DO_CMP_PPZI_H(sve_cmplt_ppzi_h, int16_t, <) | ||
142 | +DO_CMP_PPZI_S(sve_cmplt_ppzi_s, int32_t, <) | ||
143 | +DO_CMP_PPZI_D(sve_cmplt_ppzi_d, int64_t, <) | ||
144 | + | ||
145 | +DO_CMP_PPZI_B(sve_cmple_ppzi_b, int8_t, <=) | ||
146 | +DO_CMP_PPZI_H(sve_cmple_ppzi_h, int16_t, <=) | ||
147 | +DO_CMP_PPZI_S(sve_cmple_ppzi_s, int32_t, <=) | ||
148 | +DO_CMP_PPZI_D(sve_cmple_ppzi_d, int64_t, <=) | ||
149 | + | ||
150 | +DO_CMP_PPZI_B(sve_cmplo_ppzi_b, uint8_t, <) | ||
151 | +DO_CMP_PPZI_H(sve_cmplo_ppzi_h, uint16_t, <) | ||
152 | +DO_CMP_PPZI_S(sve_cmplo_ppzi_s, uint32_t, <) | ||
153 | +DO_CMP_PPZI_D(sve_cmplo_ppzi_d, uint64_t, <) | ||
154 | + | ||
155 | +DO_CMP_PPZI_B(sve_cmpls_ppzi_b, uint8_t, <=) | ||
156 | +DO_CMP_PPZI_H(sve_cmpls_ppzi_h, uint16_t, <=) | ||
157 | +DO_CMP_PPZI_S(sve_cmpls_ppzi_s, uint32_t, <=) | ||
158 | +DO_CMP_PPZI_D(sve_cmpls_ppzi_d, uint64_t, <=) | ||
159 | + | ||
160 | +#undef DO_CMP_PPZI_B | ||
161 | +#undef DO_CMP_PPZI_H | ||
162 | +#undef DO_CMP_PPZI_S | ||
163 | +#undef DO_CMP_PPZI_D | ||
164 | +#undef DO_CMP_PPZI | ||
165 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
166 | index XXXXXXX..XXXXXXX 100644 | ||
167 | --- a/target/arm/translate-sve.c | ||
168 | +++ b/target/arm/translate-sve.c | ||
169 | @@ -XXX,XX +XXX,XX @@ | ||
170 | #include "translate-a64.h" | ||
171 | |||
172 | |||
173 | +typedef void gen_helper_gvec_flags_3(TCGv_i32, TCGv_ptr, TCGv_ptr, | ||
174 | + TCGv_ptr, TCGv_i32); | ||
175 | typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr, | ||
176 | TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
177 | |||
178 | @@ -XXX,XX +XXX,XX @@ DO_PPZW(CMPLS, cmpls) | ||
179 | |||
180 | #undef DO_PPZW | ||
181 | |||
182 | +/* | ||
183 | + *** SVE Integer Compare - Immediate Groups | ||
184 | + */ | ||
185 | + | ||
186 | +static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a, | ||
187 | + gen_helper_gvec_flags_3 *gen_fn) | ||
188 | +{ | ||
189 | + TCGv_ptr pd, zn, pg; | ||
190 | + unsigned vsz; | ||
191 | + TCGv_i32 t; | ||
192 | + | ||
193 | + if (gen_fn == NULL) { | ||
194 | + return false; | ||
195 | + } | ||
196 | + if (!sve_access_check(s)) { | ||
197 | + return true; | ||
198 | + } | ||
199 | + | ||
200 | + vsz = vec_full_reg_size(s); | ||
201 | + t = tcg_const_i32(simd_desc(vsz, vsz, a->imm)); | ||
202 | + pd = tcg_temp_new_ptr(); | ||
203 | + zn = tcg_temp_new_ptr(); | ||
204 | + pg = tcg_temp_new_ptr(); | ||
205 | + | ||
206 | + tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
207 | + tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | ||
208 | + tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | ||
209 | + | ||
210 | + gen_fn(t, pd, zn, pg, t); | ||
211 | + | ||
212 | + tcg_temp_free_ptr(pd); | ||
213 | + tcg_temp_free_ptr(zn); | ||
214 | + tcg_temp_free_ptr(pg); | ||
215 | + | ||
216 | + do_pred_flags(t); | ||
217 | + | ||
218 | + tcg_temp_free_i32(t); | ||
219 | + return true; | ||
220 | +} | ||
221 | + | ||
222 | +#define DO_PPZI(NAME, name) \ | ||
223 | +static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a, \ | ||
224 | + uint32_t insn) \ | ||
225 | +{ \ | ||
226 | + static gen_helper_gvec_flags_3 * const fns[4] = { \ | ||
227 | + gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ | ||
228 | + gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \ | ||
229 | + }; \ | ||
230 | + return do_ppzi_flags(s, a, fns[a->esz]); \ | ||
231 | +} | ||
232 | + | ||
233 | +DO_PPZI(CMPEQ, cmpeq) | ||
234 | +DO_PPZI(CMPNE, cmpne) | ||
235 | +DO_PPZI(CMPGT, cmpgt) | ||
236 | +DO_PPZI(CMPGE, cmpge) | ||
237 | +DO_PPZI(CMPHI, cmphi) | ||
238 | +DO_PPZI(CMPHS, cmphs) | ||
239 | +DO_PPZI(CMPLT, cmplt) | ||
240 | +DO_PPZI(CMPLE, cmple) | ||
241 | +DO_PPZI(CMPLO, cmplo) | ||
242 | +DO_PPZI(CMPLS, cmpls) | ||
243 | + | ||
244 | +#undef DO_PPZI | ||
245 | + | ||
246 | /* | ||
247 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
248 | */ | ||
249 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
250 | index XXXXXXX..XXXXXXX 100644 | ||
251 | --- a/target/arm/sve.decode | ||
252 | +++ b/target/arm/sve.decode | ||
253 | @@ -XXX,XX +XXX,XX @@ | ||
254 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | ||
255 | &rr_dbm rn=%reg_movprfx | ||
256 | |||
257 | +# Predicate output, vector and immediate input, | ||
258 | +# controlling predicate, element size. | ||
259 | +@pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | ||
260 | +@pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | ||
261 | + | ||
262 | # Basic Load/Store with 9-bit immediate offset | ||
263 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | ||
264 | &rri imm=%imm9_16_10 | ||
265 | @@ -XXX,XX +XXX,XX @@ CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | ||
266 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | ||
267 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | ||
268 | |||
269 | +### SVE Integer Compare - Unsigned Immediate Group | ||
270 | + | ||
271 | +# SVE integer compare with unsigned immediate | ||
272 | +CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | ||
273 | +CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | ||
274 | +CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | ||
275 | +CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | ||
276 | + | ||
277 | +### SVE Integer Compare - Signed Immediate Group | ||
278 | + | ||
279 | +# SVE integer compare with signed immediate | ||
280 | +CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | ||
281 | +CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | ||
282 | +CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | ||
283 | +CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | ||
284 | +CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | ||
285 | +CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | ||
286 | + | ||
287 | ### SVE Predicate Logical Operations Group | ||
288 | |||
289 | # SVE predicate logical operations | ||
290 | -- | 48 | -- |
291 | 2.17.1 | 49 | 2.25.1 |
292 | 50 | ||
293 | 51 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Create arm_check_ss_active and arm_check_kernelpage. | ||
4 | |||
5 | Reverse the order of the tests. While it doesn't matter in practice, | ||
6 | because only user-only has a kernel page and user-only never sets | ||
7 | ss_active, ss_active has priority over execution exceptions and it | ||
8 | is best to keep them in the proper order. | ||
9 | |||
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180613015641.5667-12-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/helper-sve.h | 115 +++++++++++++++++++++++ | 14 | target/arm/translate.c | 10 +++++++--- |
9 | target/arm/sve_helper.c | 187 +++++++++++++++++++++++++++++++++++++ | 15 | 1 file changed, 7 insertions(+), 3 deletions(-) |
10 | target/arm/translate-sve.c | 91 ++++++++++++++++++ | ||
11 | target/arm/sve.decode | 24 +++++ | ||
12 | 4 files changed, 417 insertions(+) | ||
13 | 16 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 17 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 19 | --- a/target/arm/translate.c |
17 | +++ b/target/arm/helper-sve.h | 20 | +++ b/target/arm/translate.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 21 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) |
19 | 22 | dc->insn_start = tcg_last_op(); | |
20 | DEF_HELPER_FLAGS_5(sve_splice, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
21 | |||
22 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_b, TCG_CALL_NO_RWG, | ||
23 | + i32, ptr, ptr, ptr, ptr, i32) | ||
24 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_b, TCG_CALL_NO_RWG, | ||
25 | + i32, ptr, ptr, ptr, ptr, i32) | ||
26 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_b, TCG_CALL_NO_RWG, | ||
27 | + i32, ptr, ptr, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_b, TCG_CALL_NO_RWG, | ||
29 | + i32, ptr, ptr, ptr, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_b, TCG_CALL_NO_RWG, | ||
31 | + i32, ptr, ptr, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_b, TCG_CALL_NO_RWG, | ||
33 | + i32, ptr, ptr, ptr, ptr, i32) | ||
34 | + | ||
35 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_h, TCG_CALL_NO_RWG, | ||
36 | + i32, ptr, ptr, ptr, ptr, i32) | ||
37 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_h, TCG_CALL_NO_RWG, | ||
38 | + i32, ptr, ptr, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_h, TCG_CALL_NO_RWG, | ||
40 | + i32, ptr, ptr, ptr, ptr, i32) | ||
41 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_h, TCG_CALL_NO_RWG, | ||
42 | + i32, ptr, ptr, ptr, ptr, i32) | ||
43 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_h, TCG_CALL_NO_RWG, | ||
44 | + i32, ptr, ptr, ptr, ptr, i32) | ||
45 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_h, TCG_CALL_NO_RWG, | ||
46 | + i32, ptr, ptr, ptr, ptr, i32) | ||
47 | + | ||
48 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_s, TCG_CALL_NO_RWG, | ||
49 | + i32, ptr, ptr, ptr, ptr, i32) | ||
50 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_s, TCG_CALL_NO_RWG, | ||
51 | + i32, ptr, ptr, ptr, ptr, i32) | ||
52 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_s, TCG_CALL_NO_RWG, | ||
53 | + i32, ptr, ptr, ptr, ptr, i32) | ||
54 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_s, TCG_CALL_NO_RWG, | ||
55 | + i32, ptr, ptr, ptr, ptr, i32) | ||
56 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_s, TCG_CALL_NO_RWG, | ||
57 | + i32, ptr, ptr, ptr, ptr, i32) | ||
58 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_s, TCG_CALL_NO_RWG, | ||
59 | + i32, ptr, ptr, ptr, ptr, i32) | ||
60 | + | ||
61 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_d, TCG_CALL_NO_RWG, | ||
62 | + i32, ptr, ptr, ptr, ptr, i32) | ||
63 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_d, TCG_CALL_NO_RWG, | ||
64 | + i32, ptr, ptr, ptr, ptr, i32) | ||
65 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_d, TCG_CALL_NO_RWG, | ||
66 | + i32, ptr, ptr, ptr, ptr, i32) | ||
67 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_d, TCG_CALL_NO_RWG, | ||
68 | + i32, ptr, ptr, ptr, ptr, i32) | ||
69 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_d, TCG_CALL_NO_RWG, | ||
70 | + i32, ptr, ptr, ptr, ptr, i32) | ||
71 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_d, TCG_CALL_NO_RWG, | ||
72 | + i32, ptr, ptr, ptr, ptr, i32) | ||
73 | + | ||
74 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzw_b, TCG_CALL_NO_RWG, | ||
75 | + i32, ptr, ptr, ptr, ptr, i32) | ||
76 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzw_b, TCG_CALL_NO_RWG, | ||
77 | + i32, ptr, ptr, ptr, ptr, i32) | ||
78 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzw_b, TCG_CALL_NO_RWG, | ||
79 | + i32, ptr, ptr, ptr, ptr, i32) | ||
80 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzw_b, TCG_CALL_NO_RWG, | ||
81 | + i32, ptr, ptr, ptr, ptr, i32) | ||
82 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzw_b, TCG_CALL_NO_RWG, | ||
83 | + i32, ptr, ptr, ptr, ptr, i32) | ||
84 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzw_b, TCG_CALL_NO_RWG, | ||
85 | + i32, ptr, ptr, ptr, ptr, i32) | ||
86 | +DEF_HELPER_FLAGS_5(sve_cmple_ppzw_b, TCG_CALL_NO_RWG, | ||
87 | + i32, ptr, ptr, ptr, ptr, i32) | ||
88 | +DEF_HELPER_FLAGS_5(sve_cmplt_ppzw_b, TCG_CALL_NO_RWG, | ||
89 | + i32, ptr, ptr, ptr, ptr, i32) | ||
90 | +DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_b, TCG_CALL_NO_RWG, | ||
91 | + i32, ptr, ptr, ptr, ptr, i32) | ||
92 | +DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_b, TCG_CALL_NO_RWG, | ||
93 | + i32, ptr, ptr, ptr, ptr, i32) | ||
94 | + | ||
95 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzw_h, TCG_CALL_NO_RWG, | ||
96 | + i32, ptr, ptr, ptr, ptr, i32) | ||
97 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzw_h, TCG_CALL_NO_RWG, | ||
98 | + i32, ptr, ptr, ptr, ptr, i32) | ||
99 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzw_h, TCG_CALL_NO_RWG, | ||
100 | + i32, ptr, ptr, ptr, ptr, i32) | ||
101 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzw_h, TCG_CALL_NO_RWG, | ||
102 | + i32, ptr, ptr, ptr, ptr, i32) | ||
103 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzw_h, TCG_CALL_NO_RWG, | ||
104 | + i32, ptr, ptr, ptr, ptr, i32) | ||
105 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzw_h, TCG_CALL_NO_RWG, | ||
106 | + i32, ptr, ptr, ptr, ptr, i32) | ||
107 | +DEF_HELPER_FLAGS_5(sve_cmple_ppzw_h, TCG_CALL_NO_RWG, | ||
108 | + i32, ptr, ptr, ptr, ptr, i32) | ||
109 | +DEF_HELPER_FLAGS_5(sve_cmplt_ppzw_h, TCG_CALL_NO_RWG, | ||
110 | + i32, ptr, ptr, ptr, ptr, i32) | ||
111 | +DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_h, TCG_CALL_NO_RWG, | ||
112 | + i32, ptr, ptr, ptr, ptr, i32) | ||
113 | +DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_h, TCG_CALL_NO_RWG, | ||
114 | + i32, ptr, ptr, ptr, ptr, i32) | ||
115 | + | ||
116 | +DEF_HELPER_FLAGS_5(sve_cmpeq_ppzw_s, TCG_CALL_NO_RWG, | ||
117 | + i32, ptr, ptr, ptr, ptr, i32) | ||
118 | +DEF_HELPER_FLAGS_5(sve_cmpne_ppzw_s, TCG_CALL_NO_RWG, | ||
119 | + i32, ptr, ptr, ptr, ptr, i32) | ||
120 | +DEF_HELPER_FLAGS_5(sve_cmpge_ppzw_s, TCG_CALL_NO_RWG, | ||
121 | + i32, ptr, ptr, ptr, ptr, i32) | ||
122 | +DEF_HELPER_FLAGS_5(sve_cmpgt_ppzw_s, TCG_CALL_NO_RWG, | ||
123 | + i32, ptr, ptr, ptr, ptr, i32) | ||
124 | +DEF_HELPER_FLAGS_5(sve_cmphi_ppzw_s, TCG_CALL_NO_RWG, | ||
125 | + i32, ptr, ptr, ptr, ptr, i32) | ||
126 | +DEF_HELPER_FLAGS_5(sve_cmphs_ppzw_s, TCG_CALL_NO_RWG, | ||
127 | + i32, ptr, ptr, ptr, ptr, i32) | ||
128 | +DEF_HELPER_FLAGS_5(sve_cmple_ppzw_s, TCG_CALL_NO_RWG, | ||
129 | + i32, ptr, ptr, ptr, ptr, i32) | ||
130 | +DEF_HELPER_FLAGS_5(sve_cmplt_ppzw_s, TCG_CALL_NO_RWG, | ||
131 | + i32, ptr, ptr, ptr, ptr, i32) | ||
132 | +DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_s, TCG_CALL_NO_RWG, | ||
133 | + i32, ptr, ptr, ptr, ptr, i32) | ||
134 | +DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_s, TCG_CALL_NO_RWG, | ||
135 | + i32, ptr, ptr, ptr, ptr, i32) | ||
136 | + | ||
137 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
138 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
139 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
140 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
141 | index XXXXXXX..XXXXXXX 100644 | ||
142 | --- a/target/arm/sve_helper.c | ||
143 | +++ b/target/arm/sve_helper.c | ||
144 | @@ -XXX,XX +XXX,XX @@ static uint32_t iter_predtest_fwd(uint64_t d, uint64_t g, uint32_t flags) | ||
145 | return flags; | ||
146 | } | 23 | } |
147 | 24 | ||
148 | +/* This is an iterative function, called for each Pd and Pg word | 25 | -static bool arm_pre_translate_insn(DisasContext *dc) |
149 | + * moving backward. | 26 | +static bool arm_check_kernelpage(DisasContext *dc) |
150 | + */ | 27 | { |
151 | +static uint32_t iter_predtest_bwd(uint64_t d, uint64_t g, uint32_t flags) | 28 | #ifdef CONFIG_USER_ONLY |
29 | /* Intercept jump to the magic kernel page. */ | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc) | ||
31 | return true; | ||
32 | } | ||
33 | #endif | ||
34 | + return false; | ||
35 | +} | ||
36 | |||
37 | +static bool arm_check_ss_active(DisasContext *dc) | ||
152 | +{ | 38 | +{ |
153 | + if (likely(g)) { | 39 | if (dc->ss_active && !dc->pstate_ss) { |
154 | + /* Compute C from first (i.e last) !(D & G). | 40 | /* Singlestep state is Active-pending. |
155 | + Use bit 2 to signal first G bit seen. */ | 41 | * If we're in this state at the start of a TB then either |
156 | + if (!(flags & 4)) { | 42 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
157 | + flags += 4 - 1; /* add bit 2, subtract C from PREDTEST_INIT */ | 43 | uint32_t pc = dc->base.pc_next; |
158 | + flags |= (d & pow2floor(g)) == 0; | 44 | unsigned int insn; |
159 | + } | 45 | |
160 | + | 46 | - if (arm_pre_translate_insn(dc)) { |
161 | + /* Accumulate Z from each D & G. */ | 47 | + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
162 | + flags |= ((d & g) != 0) << 1; | 48 | dc->base.pc_next = pc + 4; |
163 | + | 49 | return; |
164 | + /* Compute N from last (i.e first) D & G. Replace previous. */ | ||
165 | + flags = deposit32(flags, 31, 1, (d & (g & -g)) != 0); | ||
166 | + } | ||
167 | + return flags; | ||
168 | +} | ||
169 | + | ||
170 | /* The same for a single word predicate. */ | ||
171 | uint32_t HELPER(sve_predtest1)(uint64_t d, uint64_t g) | ||
172 | { | ||
173 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm, | ||
174 | d[i] = (pg[H1(i)] & 1 ? nn : mm); | ||
175 | } | 50 | } |
176 | } | 51 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
177 | + | 52 | uint32_t insn; |
178 | +/* Two operand comparison controlled by a predicate. | 53 | bool is_16bit; |
179 | + * ??? It is very tempting to want to be able to expand this inline | 54 | |
180 | + * with x86 instructions, e.g. | 55 | - if (arm_pre_translate_insn(dc)) { |
181 | + * | 56 | + if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { |
182 | + * vcmpeqw zm, zn, %ymm0 | 57 | dc->base.pc_next = pc + 2; |
183 | + * vpmovmskb %ymm0, %eax | 58 | return; |
184 | + * and $0x5555, %eax | 59 | } |
185 | + * and pg, %eax | ||
186 | + * | ||
187 | + * or even aarch64, e.g. | ||
188 | + * | ||
189 | + * // mask = 4000 1000 0400 0100 0040 0010 0004 0001 | ||
190 | + * cmeq v0.8h, zn, zm | ||
191 | + * and v0.8h, v0.8h, mask | ||
192 | + * addv h0, v0.8h | ||
193 | + * and v0.8b, pg | ||
194 | + * | ||
195 | + * However, coming up with an abstraction that allows vector inputs and | ||
196 | + * a scalar output, and also handles the byte-ordering of sub-uint64_t | ||
197 | + * scalar outputs, is tricky. | ||
198 | + */ | ||
199 | +#define DO_CMP_PPZZ(NAME, TYPE, OP, H, MASK) \ | ||
200 | +uint32_t HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ | ||
201 | +{ \ | ||
202 | + intptr_t opr_sz = simd_oprsz(desc); \ | ||
203 | + uint32_t flags = PREDTEST_INIT; \ | ||
204 | + intptr_t i = opr_sz; \ | ||
205 | + do { \ | ||
206 | + uint64_t out = 0, pg; \ | ||
207 | + do { \ | ||
208 | + i -= sizeof(TYPE), out <<= sizeof(TYPE); \ | ||
209 | + TYPE nn = *(TYPE *)(vn + H(i)); \ | ||
210 | + TYPE mm = *(TYPE *)(vm + H(i)); \ | ||
211 | + out |= nn OP mm; \ | ||
212 | + } while (i & 63); \ | ||
213 | + pg = *(uint64_t *)(vg + (i >> 3)) & MASK; \ | ||
214 | + out &= pg; \ | ||
215 | + *(uint64_t *)(vd + (i >> 3)) = out; \ | ||
216 | + flags = iter_predtest_bwd(out, pg, flags); \ | ||
217 | + } while (i > 0); \ | ||
218 | + return flags; \ | ||
219 | +} | ||
220 | + | ||
221 | +#define DO_CMP_PPZZ_B(NAME, TYPE, OP) \ | ||
222 | + DO_CMP_PPZZ(NAME, TYPE, OP, H1, 0xffffffffffffffffull) | ||
223 | +#define DO_CMP_PPZZ_H(NAME, TYPE, OP) \ | ||
224 | + DO_CMP_PPZZ(NAME, TYPE, OP, H1_2, 0x5555555555555555ull) | ||
225 | +#define DO_CMP_PPZZ_S(NAME, TYPE, OP) \ | ||
226 | + DO_CMP_PPZZ(NAME, TYPE, OP, H1_4, 0x1111111111111111ull) | ||
227 | +#define DO_CMP_PPZZ_D(NAME, TYPE, OP) \ | ||
228 | + DO_CMP_PPZZ(NAME, TYPE, OP, , 0x0101010101010101ull) | ||
229 | + | ||
230 | +DO_CMP_PPZZ_B(sve_cmpeq_ppzz_b, uint8_t, ==) | ||
231 | +DO_CMP_PPZZ_H(sve_cmpeq_ppzz_h, uint16_t, ==) | ||
232 | +DO_CMP_PPZZ_S(sve_cmpeq_ppzz_s, uint32_t, ==) | ||
233 | +DO_CMP_PPZZ_D(sve_cmpeq_ppzz_d, uint64_t, ==) | ||
234 | + | ||
235 | +DO_CMP_PPZZ_B(sve_cmpne_ppzz_b, uint8_t, !=) | ||
236 | +DO_CMP_PPZZ_H(sve_cmpne_ppzz_h, uint16_t, !=) | ||
237 | +DO_CMP_PPZZ_S(sve_cmpne_ppzz_s, uint32_t, !=) | ||
238 | +DO_CMP_PPZZ_D(sve_cmpne_ppzz_d, uint64_t, !=) | ||
239 | + | ||
240 | +DO_CMP_PPZZ_B(sve_cmpgt_ppzz_b, int8_t, >) | ||
241 | +DO_CMP_PPZZ_H(sve_cmpgt_ppzz_h, int16_t, >) | ||
242 | +DO_CMP_PPZZ_S(sve_cmpgt_ppzz_s, int32_t, >) | ||
243 | +DO_CMP_PPZZ_D(sve_cmpgt_ppzz_d, int64_t, >) | ||
244 | + | ||
245 | +DO_CMP_PPZZ_B(sve_cmpge_ppzz_b, int8_t, >=) | ||
246 | +DO_CMP_PPZZ_H(sve_cmpge_ppzz_h, int16_t, >=) | ||
247 | +DO_CMP_PPZZ_S(sve_cmpge_ppzz_s, int32_t, >=) | ||
248 | +DO_CMP_PPZZ_D(sve_cmpge_ppzz_d, int64_t, >=) | ||
249 | + | ||
250 | +DO_CMP_PPZZ_B(sve_cmphi_ppzz_b, uint8_t, >) | ||
251 | +DO_CMP_PPZZ_H(sve_cmphi_ppzz_h, uint16_t, >) | ||
252 | +DO_CMP_PPZZ_S(sve_cmphi_ppzz_s, uint32_t, >) | ||
253 | +DO_CMP_PPZZ_D(sve_cmphi_ppzz_d, uint64_t, >) | ||
254 | + | ||
255 | +DO_CMP_PPZZ_B(sve_cmphs_ppzz_b, uint8_t, >=) | ||
256 | +DO_CMP_PPZZ_H(sve_cmphs_ppzz_h, uint16_t, >=) | ||
257 | +DO_CMP_PPZZ_S(sve_cmphs_ppzz_s, uint32_t, >=) | ||
258 | +DO_CMP_PPZZ_D(sve_cmphs_ppzz_d, uint64_t, >=) | ||
259 | + | ||
260 | +#undef DO_CMP_PPZZ_B | ||
261 | +#undef DO_CMP_PPZZ_H | ||
262 | +#undef DO_CMP_PPZZ_S | ||
263 | +#undef DO_CMP_PPZZ_D | ||
264 | +#undef DO_CMP_PPZZ | ||
265 | + | ||
266 | +/* Similar, but the second source is "wide". */ | ||
267 | +#define DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H, MASK) \ | ||
268 | +uint32_t HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ | ||
269 | +{ \ | ||
270 | + intptr_t opr_sz = simd_oprsz(desc); \ | ||
271 | + uint32_t flags = PREDTEST_INIT; \ | ||
272 | + intptr_t i = opr_sz; \ | ||
273 | + do { \ | ||
274 | + uint64_t out = 0, pg; \ | ||
275 | + do { \ | ||
276 | + TYPEW mm = *(TYPEW *)(vm + i - 8); \ | ||
277 | + do { \ | ||
278 | + i -= sizeof(TYPE), out <<= sizeof(TYPE); \ | ||
279 | + TYPE nn = *(TYPE *)(vn + H(i)); \ | ||
280 | + out |= nn OP mm; \ | ||
281 | + } while (i & 7); \ | ||
282 | + } while (i & 63); \ | ||
283 | + pg = *(uint64_t *)(vg + (i >> 3)) & MASK; \ | ||
284 | + out &= pg; \ | ||
285 | + *(uint64_t *)(vd + (i >> 3)) = out; \ | ||
286 | + flags = iter_predtest_bwd(out, pg, flags); \ | ||
287 | + } while (i > 0); \ | ||
288 | + return flags; \ | ||
289 | +} | ||
290 | + | ||
291 | +#define DO_CMP_PPZW_B(NAME, TYPE, TYPEW, OP) \ | ||
292 | + DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1, 0xffffffffffffffffull) | ||
293 | +#define DO_CMP_PPZW_H(NAME, TYPE, TYPEW, OP) \ | ||
294 | + DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1_2, 0x5555555555555555ull) | ||
295 | +#define DO_CMP_PPZW_S(NAME, TYPE, TYPEW, OP) \ | ||
296 | + DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1_4, 0x1111111111111111ull) | ||
297 | + | ||
298 | +DO_CMP_PPZW_B(sve_cmpeq_ppzw_b, uint8_t, uint64_t, ==) | ||
299 | +DO_CMP_PPZW_H(sve_cmpeq_ppzw_h, uint16_t, uint64_t, ==) | ||
300 | +DO_CMP_PPZW_S(sve_cmpeq_ppzw_s, uint32_t, uint64_t, ==) | ||
301 | + | ||
302 | +DO_CMP_PPZW_B(sve_cmpne_ppzw_b, uint8_t, uint64_t, !=) | ||
303 | +DO_CMP_PPZW_H(sve_cmpne_ppzw_h, uint16_t, uint64_t, !=) | ||
304 | +DO_CMP_PPZW_S(sve_cmpne_ppzw_s, uint32_t, uint64_t, !=) | ||
305 | + | ||
306 | +DO_CMP_PPZW_B(sve_cmpgt_ppzw_b, int8_t, int64_t, >) | ||
307 | +DO_CMP_PPZW_H(sve_cmpgt_ppzw_h, int16_t, int64_t, >) | ||
308 | +DO_CMP_PPZW_S(sve_cmpgt_ppzw_s, int32_t, int64_t, >) | ||
309 | + | ||
310 | +DO_CMP_PPZW_B(sve_cmpge_ppzw_b, int8_t, int64_t, >=) | ||
311 | +DO_CMP_PPZW_H(sve_cmpge_ppzw_h, int16_t, int64_t, >=) | ||
312 | +DO_CMP_PPZW_S(sve_cmpge_ppzw_s, int32_t, int64_t, >=) | ||
313 | + | ||
314 | +DO_CMP_PPZW_B(sve_cmphi_ppzw_b, uint8_t, uint64_t, >) | ||
315 | +DO_CMP_PPZW_H(sve_cmphi_ppzw_h, uint16_t, uint64_t, >) | ||
316 | +DO_CMP_PPZW_S(sve_cmphi_ppzw_s, uint32_t, uint64_t, >) | ||
317 | + | ||
318 | +DO_CMP_PPZW_B(sve_cmphs_ppzw_b, uint8_t, uint64_t, >=) | ||
319 | +DO_CMP_PPZW_H(sve_cmphs_ppzw_h, uint16_t, uint64_t, >=) | ||
320 | +DO_CMP_PPZW_S(sve_cmphs_ppzw_s, uint32_t, uint64_t, >=) | ||
321 | + | ||
322 | +DO_CMP_PPZW_B(sve_cmplt_ppzw_b, int8_t, int64_t, <) | ||
323 | +DO_CMP_PPZW_H(sve_cmplt_ppzw_h, int16_t, int64_t, <) | ||
324 | +DO_CMP_PPZW_S(sve_cmplt_ppzw_s, int32_t, int64_t, <) | ||
325 | + | ||
326 | +DO_CMP_PPZW_B(sve_cmple_ppzw_b, int8_t, int64_t, <=) | ||
327 | +DO_CMP_PPZW_H(sve_cmple_ppzw_h, int16_t, int64_t, <=) | ||
328 | +DO_CMP_PPZW_S(sve_cmple_ppzw_s, int32_t, int64_t, <=) | ||
329 | + | ||
330 | +DO_CMP_PPZW_B(sve_cmplo_ppzw_b, uint8_t, uint64_t, <) | ||
331 | +DO_CMP_PPZW_H(sve_cmplo_ppzw_h, uint16_t, uint64_t, <) | ||
332 | +DO_CMP_PPZW_S(sve_cmplo_ppzw_s, uint32_t, uint64_t, <) | ||
333 | + | ||
334 | +DO_CMP_PPZW_B(sve_cmpls_ppzw_b, uint8_t, uint64_t, <=) | ||
335 | +DO_CMP_PPZW_H(sve_cmpls_ppzw_h, uint16_t, uint64_t, <=) | ||
336 | +DO_CMP_PPZW_S(sve_cmpls_ppzw_s, uint32_t, uint64_t, <=) | ||
337 | + | ||
338 | +#undef DO_CMP_PPZW_B | ||
339 | +#undef DO_CMP_PPZW_H | ||
340 | +#undef DO_CMP_PPZW_S | ||
341 | +#undef DO_CMP_PPZW | ||
342 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
343 | index XXXXXXX..XXXXXXX 100644 | ||
344 | --- a/target/arm/translate-sve.c | ||
345 | +++ b/target/arm/translate-sve.c | ||
346 | @@ -XXX,XX +XXX,XX @@ | ||
347 | #include "trace-tcg.h" | ||
348 | #include "translate-a64.h" | ||
349 | |||
350 | + | ||
351 | +typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr, | ||
352 | + TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
353 | + | ||
354 | /* | ||
355 | * Helpers for extracting complex instruction fields. | ||
356 | */ | ||
357 | @@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | ||
358 | return true; | ||
359 | } | ||
360 | |||
361 | +/* | ||
362 | + *** SVE Integer Compare - Vectors Group | ||
363 | + */ | ||
364 | + | ||
365 | +static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a, | ||
366 | + gen_helper_gvec_flags_4 *gen_fn) | ||
367 | +{ | ||
368 | + TCGv_ptr pd, zn, zm, pg; | ||
369 | + unsigned vsz; | ||
370 | + TCGv_i32 t; | ||
371 | + | ||
372 | + if (gen_fn == NULL) { | ||
373 | + return false; | ||
374 | + } | ||
375 | + if (!sve_access_check(s)) { | ||
376 | + return true; | ||
377 | + } | ||
378 | + | ||
379 | + vsz = vec_full_reg_size(s); | ||
380 | + t = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
381 | + pd = tcg_temp_new_ptr(); | ||
382 | + zn = tcg_temp_new_ptr(); | ||
383 | + zm = tcg_temp_new_ptr(); | ||
384 | + pg = tcg_temp_new_ptr(); | ||
385 | + | ||
386 | + tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
387 | + tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); | ||
388 | + tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); | ||
389 | + tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); | ||
390 | + | ||
391 | + gen_fn(t, pd, zn, zm, pg, t); | ||
392 | + | ||
393 | + tcg_temp_free_ptr(pd); | ||
394 | + tcg_temp_free_ptr(zn); | ||
395 | + tcg_temp_free_ptr(zm); | ||
396 | + tcg_temp_free_ptr(pg); | ||
397 | + | ||
398 | + do_pred_flags(t); | ||
399 | + | ||
400 | + tcg_temp_free_i32(t); | ||
401 | + return true; | ||
402 | +} | ||
403 | + | ||
404 | +#define DO_PPZZ(NAME, name) \ | ||
405 | +static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a, \ | ||
406 | + uint32_t insn) \ | ||
407 | +{ \ | ||
408 | + static gen_helper_gvec_flags_4 * const fns[4] = { \ | ||
409 | + gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ | ||
410 | + gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \ | ||
411 | + }; \ | ||
412 | + return do_ppzz_flags(s, a, fns[a->esz]); \ | ||
413 | +} | ||
414 | + | ||
415 | +DO_PPZZ(CMPEQ, cmpeq) | ||
416 | +DO_PPZZ(CMPNE, cmpne) | ||
417 | +DO_PPZZ(CMPGT, cmpgt) | ||
418 | +DO_PPZZ(CMPGE, cmpge) | ||
419 | +DO_PPZZ(CMPHI, cmphi) | ||
420 | +DO_PPZZ(CMPHS, cmphs) | ||
421 | + | ||
422 | +#undef DO_PPZZ | ||
423 | + | ||
424 | +#define DO_PPZW(NAME, name) \ | ||
425 | +static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a, \ | ||
426 | + uint32_t insn) \ | ||
427 | +{ \ | ||
428 | + static gen_helper_gvec_flags_4 * const fns[4] = { \ | ||
429 | + gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ | ||
430 | + gen_helper_sve_##name##_ppzw_s, NULL \ | ||
431 | + }; \ | ||
432 | + return do_ppzz_flags(s, a, fns[a->esz]); \ | ||
433 | +} | ||
434 | + | ||
435 | +DO_PPZW(CMPEQ, cmpeq) | ||
436 | +DO_PPZW(CMPNE, cmpne) | ||
437 | +DO_PPZW(CMPGT, cmpgt) | ||
438 | +DO_PPZW(CMPGE, cmpge) | ||
439 | +DO_PPZW(CMPHI, cmphi) | ||
440 | +DO_PPZW(CMPHS, cmphs) | ||
441 | +DO_PPZW(CMPLT, cmplt) | ||
442 | +DO_PPZW(CMPLE, cmple) | ||
443 | +DO_PPZW(CMPLO, cmplo) | ||
444 | +DO_PPZW(CMPLS, cmpls) | ||
445 | + | ||
446 | +#undef DO_PPZW | ||
447 | + | ||
448 | /* | ||
449 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
450 | */ | ||
451 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
452 | index XXXXXXX..XXXXXXX 100644 | ||
453 | --- a/target/arm/sve.decode | ||
454 | +++ b/target/arm/sve.decode | ||
455 | @@ -XXX,XX +XXX,XX @@ | ||
456 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | ||
457 | &rprr_esz rm=%reg_movprfx | ||
458 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz | ||
459 | +@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz | ||
460 | |||
461 | # Three register operand, with governing predicate, vector element size | ||
462 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | ||
463 | @@ -XXX,XX +XXX,XX @@ SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | ||
464 | # SVE select vector elements (predicated) | ||
465 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | ||
466 | |||
467 | +### SVE Integer Compare - Vectors Group | ||
468 | + | ||
469 | +# SVE integer compare_vectors | ||
470 | +CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | ||
471 | +CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | ||
472 | +CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | ||
473 | +CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | ||
474 | +CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | ||
475 | +CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | ||
476 | + | ||
477 | +# SVE integer compare with wide elements | ||
478 | +# Note these require esz != 3. | ||
479 | +CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | ||
480 | +CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | ||
481 | +CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | ||
482 | +CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | ||
483 | +CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | ||
484 | +CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | ||
485 | +CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | ||
486 | +CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | ||
487 | +CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | ||
488 | +CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | ||
489 | + | ||
490 | ### SVE Predicate Logical Operations Group | ||
491 | |||
492 | # SVE predicate logical operations | ||
493 | -- | 60 | -- |
494 | 2.17.1 | 61 | 2.25.1 |
495 | 62 | ||
496 | 63 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The size of the code covered by a TranslationBlock cannot be 0; | ||
4 | this is checked via assert in tb_gen_code. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180613015641.5667-11-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/helper-sve.h | 9 +++++++ | 10 | target/arm/translate-a64.c | 1 + |
9 | target/arm/sve_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ | 11 | 1 file changed, 1 insertion(+) |
10 | target/arm/translate-sve.c | 2 ++ | ||
11 | target/arm/sve.decode | 6 +++++ | ||
12 | 4 files changed, 72 insertions(+) | ||
13 | 12 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 15 | --- a/target/arm/translate-a64.c |
17 | +++ b/target/arm/helper-sve.h | 16 | +++ b/target/arm/translate-a64.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG, | 17 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
19 | DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG, | 18 | assert(s->base.num_insns == 1); |
20 | void, ptr, ptr, ptr, ptr, i32) | 19 | gen_swstep_exception(s, 0, 0); |
21 | 20 | s->base.is_jmp = DISAS_NORETURN; | |
22 | +DEF_HELPER_FLAGS_5(sve_sel_zpzz_b, TCG_CALL_NO_RWG, | 21 | + s->base.pc_next = pc + 4; |
23 | + void, ptr, ptr, ptr, ptr, i32) | 22 | return; |
24 | +DEF_HELPER_FLAGS_5(sve_sel_zpzz_h, TCG_CALL_NO_RWG, | ||
25 | + void, ptr, ptr, ptr, ptr, i32) | ||
26 | +DEF_HELPER_FLAGS_5(sve_sel_zpzz_s, TCG_CALL_NO_RWG, | ||
27 | + void, ptr, ptr, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_5(sve_sel_zpzz_d, TCG_CALL_NO_RWG, | ||
29 | + void, ptr, ptr, ptr, ptr, i32) | ||
30 | + | ||
31 | DEF_HELPER_FLAGS_5(sve_asr_zpzw_b, TCG_CALL_NO_RWG, | ||
32 | void, ptr, ptr, ptr, ptr, i32) | ||
33 | DEF_HELPER_FLAGS_5(sve_asr_zpzw_h, TCG_CALL_NO_RWG, | ||
34 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/sve_helper.c | ||
37 | +++ b/target/arm/sve_helper.c | ||
38 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_splice)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) | ||
39 | } | 23 | } |
40 | swap_memmove(vd + len, vm, opr_sz * 8 - len); | 24 | |
41 | } | ||
42 | + | ||
43 | +void HELPER(sve_sel_zpzz_b)(void *vd, void *vn, void *vm, | ||
44 | + void *vg, uint32_t desc) | ||
45 | +{ | ||
46 | + intptr_t i, opr_sz = simd_oprsz(desc) / 8; | ||
47 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
48 | + uint8_t *pg = vg; | ||
49 | + | ||
50 | + for (i = 0; i < opr_sz; i += 1) { | ||
51 | + uint64_t nn = n[i], mm = m[i]; | ||
52 | + uint64_t pp = expand_pred_b(pg[H1(i)]); | ||
53 | + d[i] = (nn & pp) | (mm & ~pp); | ||
54 | + } | ||
55 | +} | ||
56 | + | ||
57 | +void HELPER(sve_sel_zpzz_h)(void *vd, void *vn, void *vm, | ||
58 | + void *vg, uint32_t desc) | ||
59 | +{ | ||
60 | + intptr_t i, opr_sz = simd_oprsz(desc) / 8; | ||
61 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
62 | + uint8_t *pg = vg; | ||
63 | + | ||
64 | + for (i = 0; i < opr_sz; i += 1) { | ||
65 | + uint64_t nn = n[i], mm = m[i]; | ||
66 | + uint64_t pp = expand_pred_h(pg[H1(i)]); | ||
67 | + d[i] = (nn & pp) | (mm & ~pp); | ||
68 | + } | ||
69 | +} | ||
70 | + | ||
71 | +void HELPER(sve_sel_zpzz_s)(void *vd, void *vn, void *vm, | ||
72 | + void *vg, uint32_t desc) | ||
73 | +{ | ||
74 | + intptr_t i, opr_sz = simd_oprsz(desc) / 8; | ||
75 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
76 | + uint8_t *pg = vg; | ||
77 | + | ||
78 | + for (i = 0; i < opr_sz; i += 1) { | ||
79 | + uint64_t nn = n[i], mm = m[i]; | ||
80 | + uint64_t pp = expand_pred_s(pg[H1(i)]); | ||
81 | + d[i] = (nn & pp) | (mm & ~pp); | ||
82 | + } | ||
83 | +} | ||
84 | + | ||
85 | +void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm, | ||
86 | + void *vg, uint32_t desc) | ||
87 | +{ | ||
88 | + intptr_t i, opr_sz = simd_oprsz(desc) / 8; | ||
89 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
90 | + uint8_t *pg = vg; | ||
91 | + | ||
92 | + for (i = 0; i < opr_sz; i += 1) { | ||
93 | + uint64_t nn = n[i], mm = m[i]; | ||
94 | + d[i] = (pg[H1(i)] & 1 ? nn : mm); | ||
95 | + } | ||
96 | +} | ||
97 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
98 | index XXXXXXX..XXXXXXX 100644 | ||
99 | --- a/target/arm/translate-sve.c | ||
100 | +++ b/target/arm/translate-sve.c | ||
101 | @@ -XXX,XX +XXX,XX @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | ||
102 | return do_zpzz_ool(s, a, fns[a->esz]); | ||
103 | } | ||
104 | |||
105 | +DO_ZPZZ(SEL, sel) | ||
106 | + | ||
107 | #undef DO_ZPZZ | ||
108 | |||
109 | /* | ||
110 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/target/arm/sve.decode | ||
113 | +++ b/target/arm/sve.decode | ||
114 | @@ -XXX,XX +XXX,XX @@ | ||
115 | &rprr_esz rn=%reg_movprfx | ||
116 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | ||
117 | &rprr_esz rm=%reg_movprfx | ||
118 | +@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz | ||
119 | |||
120 | # Three register operand, with governing predicate, vector element size | ||
121 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | ||
122 | @@ -XXX,XX +XXX,XX @@ RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | ||
123 | # SVE vector splice (predicated) | ||
124 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | ||
125 | |||
126 | +### SVE Select Vectors Group | ||
127 | + | ||
128 | +# SVE select vector elements (predicated) | ||
129 | +SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | ||
130 | + | ||
131 | ### SVE Predicate Logical Operations Group | ||
132 | |||
133 | # SVE predicate logical operations | ||
134 | -- | 25 | -- |
135 | 2.17.1 | 26 | 2.25.1 |
136 | 27 | ||
137 | 28 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We will reuse this section of arm_deliver_fault for | ||
4 | raising pc alignment faults. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180613015641.5667-3-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/helper-sve.h | 23 +++++++ | 10 | target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++---------------- |
9 | target/arm/sve_helper.c | 114 +++++++++++++++++++++++++++++++ | 11 | 1 file changed, 28 insertions(+), 17 deletions(-) |
10 | target/arm/translate-sve.c | 133 +++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/sve.decode | 27 ++++++++ | ||
12 | 4 files changed, 297 insertions(+) | ||
13 | 12 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 13 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 15 | --- a/target/arm/tlb_helper.c |
17 | +++ b/target/arm/helper-sve.h | 16 | +++ b/target/arm/tlb_helper.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 17 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, |
19 | 18 | return syn; | |
20 | DEF_HELPER_FLAGS_4(sve_ext, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 19 | } |
21 | 20 | ||
22 | +DEF_HELPER_FLAGS_4(sve_insr_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 21 | -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
23 | +DEF_HELPER_FLAGS_4(sve_insr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 22 | - MMUAccessType access_type, |
24 | +DEF_HELPER_FLAGS_4(sve_insr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 23 | - int mmu_idx, ARMMMUFaultInfo *fi) |
25 | +DEF_HELPER_FLAGS_4(sve_insr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 24 | +static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi, |
26 | + | 25 | + int target_el, int mmu_idx, uint32_t *ret_fsc) |
27 | +DEF_HELPER_FLAGS_3(sve_rev_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 26 | { |
28 | +DEF_HELPER_FLAGS_3(sve_rev_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 27 | - CPUARMState *env = &cpu->env; |
29 | +DEF_HELPER_FLAGS_3(sve_rev_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 28 | - int target_el; |
30 | +DEF_HELPER_FLAGS_3(sve_rev_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 29 | - bool same_el; |
31 | + | 30 | - uint32_t syn, exc, fsr, fsc; |
32 | +DEF_HELPER_FLAGS_4(sve_tbl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 31 | ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); |
33 | +DEF_HELPER_FLAGS_4(sve_tbl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 32 | - |
34 | +DEF_HELPER_FLAGS_4(sve_tbl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 33 | - target_el = exception_target_el(env); |
35 | +DEF_HELPER_FLAGS_4(sve_tbl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 34 | - if (fi->stage2) { |
36 | + | 35 | - target_el = 2; |
37 | +DEF_HELPER_FLAGS_3(sve_sunpk_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 36 | - env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; |
38 | +DEF_HELPER_FLAGS_3(sve_sunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 37 | - if (arm_is_secure_below_el3(env) && fi->s1ns) { |
39 | +DEF_HELPER_FLAGS_3(sve_sunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 38 | - env->cp15.hpfar_el2 |= HPFAR_NS; |
40 | + | 39 | - } |
41 | +DEF_HELPER_FLAGS_3(sve_uunpk_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 40 | - } |
42 | +DEF_HELPER_FLAGS_3(sve_uunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 41 | - same_el = (arm_current_el(env) == target_el); |
43 | +DEF_HELPER_FLAGS_3(sve_uunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 42 | + uint32_t fsr, fsc; |
44 | + | 43 | |
45 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 44 | if (target_el == 2 || arm_el_is_aa64(env, target_el) || |
46 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 45 | arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { |
47 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 46 | @@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
48 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 47 | fsc = 0x3f; |
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/sve_helper.c | ||
51 | +++ b/target/arm/sve_helper.c | ||
52 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_ext)(void *vd, void *vn, void *vm, uint32_t desc) | ||
53 | memcpy(vd + n_siz, &tmp, n_ofs); | ||
54 | } | 48 | } |
55 | } | 49 | |
56 | + | 50 | + *ret_fsc = fsc; |
57 | +#define DO_INSR(NAME, TYPE, H) \ | 51 | + return fsr; |
58 | +void HELPER(NAME)(void *vd, void *vn, uint64_t val, uint32_t desc) \ | ||
59 | +{ \ | ||
60 | + intptr_t opr_sz = simd_oprsz(desc); \ | ||
61 | + swap_memmove(vd + sizeof(TYPE), vn, opr_sz - sizeof(TYPE)); \ | ||
62 | + *(TYPE *)(vd + H(0)) = val; \ | ||
63 | +} | 52 | +} |
64 | + | 53 | + |
65 | +DO_INSR(sve_insr_b, uint8_t, H1) | 54 | +static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, |
66 | +DO_INSR(sve_insr_h, uint16_t, H1_2) | 55 | + MMUAccessType access_type, |
67 | +DO_INSR(sve_insr_s, uint32_t, H1_4) | 56 | + int mmu_idx, ARMMMUFaultInfo *fi) |
68 | +DO_INSR(sve_insr_d, uint64_t, ) | 57 | +{ |
58 | + CPUARMState *env = &cpu->env; | ||
59 | + int target_el; | ||
60 | + bool same_el; | ||
61 | + uint32_t syn, exc, fsr, fsc; | ||
69 | + | 62 | + |
70 | +#undef DO_INSR | 63 | + target_el = exception_target_el(env); |
71 | + | 64 | + if (fi->stage2) { |
72 | +void HELPER(sve_rev_b)(void *vd, void *vn, uint32_t desc) | 65 | + target_el = 2; |
73 | +{ | 66 | + env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; |
74 | + intptr_t i, j, opr_sz = simd_oprsz(desc); | 67 | + if (arm_is_secure_below_el3(env) && fi->s1ns) { |
75 | + for (i = 0, j = opr_sz - 8; i < opr_sz / 2; i += 8, j -= 8) { | 68 | + env->cp15.hpfar_el2 |= HPFAR_NS; |
76 | + uint64_t f = *(uint64_t *)(vn + i); | ||
77 | + uint64_t b = *(uint64_t *)(vn + j); | ||
78 | + *(uint64_t *)(vd + i) = bswap64(b); | ||
79 | + *(uint64_t *)(vd + j) = bswap64(f); | ||
80 | + } | ||
81 | +} | ||
82 | + | ||
83 | +static inline uint64_t hswap64(uint64_t h) | ||
84 | +{ | ||
85 | + uint64_t m = 0x0000ffff0000ffffull; | ||
86 | + h = rol64(h, 32); | ||
87 | + return ((h & m) << 16) | ((h >> 16) & m); | ||
88 | +} | ||
89 | + | ||
90 | +void HELPER(sve_rev_h)(void *vd, void *vn, uint32_t desc) | ||
91 | +{ | ||
92 | + intptr_t i, j, opr_sz = simd_oprsz(desc); | ||
93 | + for (i = 0, j = opr_sz - 8; i < opr_sz / 2; i += 8, j -= 8) { | ||
94 | + uint64_t f = *(uint64_t *)(vn + i); | ||
95 | + uint64_t b = *(uint64_t *)(vn + j); | ||
96 | + *(uint64_t *)(vd + i) = hswap64(b); | ||
97 | + *(uint64_t *)(vd + j) = hswap64(f); | ||
98 | + } | ||
99 | +} | ||
100 | + | ||
101 | +void HELPER(sve_rev_s)(void *vd, void *vn, uint32_t desc) | ||
102 | +{ | ||
103 | + intptr_t i, j, opr_sz = simd_oprsz(desc); | ||
104 | + for (i = 0, j = opr_sz - 8; i < opr_sz / 2; i += 8, j -= 8) { | ||
105 | + uint64_t f = *(uint64_t *)(vn + i); | ||
106 | + uint64_t b = *(uint64_t *)(vn + j); | ||
107 | + *(uint64_t *)(vd + i) = rol64(b, 32); | ||
108 | + *(uint64_t *)(vd + j) = rol64(f, 32); | ||
109 | + } | ||
110 | +} | ||
111 | + | ||
112 | +void HELPER(sve_rev_d)(void *vd, void *vn, uint32_t desc) | ||
113 | +{ | ||
114 | + intptr_t i, j, opr_sz = simd_oprsz(desc); | ||
115 | + for (i = 0, j = opr_sz - 8; i < opr_sz / 2; i += 8, j -= 8) { | ||
116 | + uint64_t f = *(uint64_t *)(vn + i); | ||
117 | + uint64_t b = *(uint64_t *)(vn + j); | ||
118 | + *(uint64_t *)(vd + i) = b; | ||
119 | + *(uint64_t *)(vd + j) = f; | ||
120 | + } | ||
121 | +} | ||
122 | + | ||
123 | +#define DO_TBL(NAME, TYPE, H) \ | ||
124 | +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ | ||
125 | +{ \ | ||
126 | + intptr_t i, opr_sz = simd_oprsz(desc); \ | ||
127 | + uintptr_t elem = opr_sz / sizeof(TYPE); \ | ||
128 | + TYPE *d = vd, *n = vn, *m = vm; \ | ||
129 | + ARMVectorReg tmp; \ | ||
130 | + if (unlikely(vd == vn)) { \ | ||
131 | + n = memcpy(&tmp, vn, opr_sz); \ | ||
132 | + } \ | ||
133 | + for (i = 0; i < elem; i++) { \ | ||
134 | + TYPE j = m[H(i)]; \ | ||
135 | + d[H(i)] = j < elem ? n[H(j)] : 0; \ | ||
136 | + } \ | ||
137 | +} | ||
138 | + | ||
139 | +DO_TBL(sve_tbl_b, uint8_t, H1) | ||
140 | +DO_TBL(sve_tbl_h, uint16_t, H2) | ||
141 | +DO_TBL(sve_tbl_s, uint32_t, H4) | ||
142 | +DO_TBL(sve_tbl_d, uint64_t, ) | ||
143 | + | ||
144 | +#undef TBL | ||
145 | + | ||
146 | +#define DO_UNPK(NAME, TYPED, TYPES, HD, HS) \ | ||
147 | +void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ | ||
148 | +{ \ | ||
149 | + intptr_t i, opr_sz = simd_oprsz(desc); \ | ||
150 | + TYPED *d = vd; \ | ||
151 | + TYPES *n = vn; \ | ||
152 | + ARMVectorReg tmp; \ | ||
153 | + if (unlikely(vn - vd < opr_sz)) { \ | ||
154 | + n = memcpy(&tmp, n, opr_sz / 2); \ | ||
155 | + } \ | ||
156 | + for (i = 0; i < opr_sz / sizeof(TYPED); i++) { \ | ||
157 | + d[HD(i)] = n[HS(i)]; \ | ||
158 | + } \ | ||
159 | +} | ||
160 | + | ||
161 | +DO_UNPK(sve_sunpk_h, int16_t, int8_t, H2, H1) | ||
162 | +DO_UNPK(sve_sunpk_s, int32_t, int16_t, H4, H2) | ||
163 | +DO_UNPK(sve_sunpk_d, int64_t, int32_t, , H4) | ||
164 | + | ||
165 | +DO_UNPK(sve_uunpk_h, uint16_t, uint8_t, H2, H1) | ||
166 | +DO_UNPK(sve_uunpk_s, uint32_t, uint16_t, H4, H2) | ||
167 | +DO_UNPK(sve_uunpk_d, uint64_t, uint32_t, , H4) | ||
168 | + | ||
169 | +#undef DO_UNPK | ||
170 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
171 | index XXXXXXX..XXXXXXX 100644 | ||
172 | --- a/target/arm/translate-sve.c | ||
173 | +++ b/target/arm/translate-sve.c | ||
174 | @@ -XXX,XX +XXX,XX @@ static bool trans_EXT(DisasContext *s, arg_EXT *a, uint32_t insn) | ||
175 | return true; | ||
176 | } | ||
177 | |||
178 | +/* | ||
179 | + *** SVE Permute - Unpredicated Group | ||
180 | + */ | ||
181 | + | ||
182 | +static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a, uint32_t insn) | ||
183 | +{ | ||
184 | + if (sve_access_check(s)) { | ||
185 | + unsigned vsz = vec_full_reg_size(s); | ||
186 | + tcg_gen_gvec_dup_i64(a->esz, vec_full_reg_offset(s, a->rd), | ||
187 | + vsz, vsz, cpu_reg_sp(s, a->rn)); | ||
188 | + } | ||
189 | + return true; | ||
190 | +} | ||
191 | + | ||
192 | +static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a, uint32_t insn) | ||
193 | +{ | ||
194 | + if ((a->imm & 0x1f) == 0) { | ||
195 | + return false; | ||
196 | + } | ||
197 | + if (sve_access_check(s)) { | ||
198 | + unsigned vsz = vec_full_reg_size(s); | ||
199 | + unsigned dofs = vec_full_reg_offset(s, a->rd); | ||
200 | + unsigned esz, index; | ||
201 | + | ||
202 | + esz = ctz32(a->imm); | ||
203 | + index = a->imm >> (esz + 1); | ||
204 | + | ||
205 | + if ((index << esz) < vsz) { | ||
206 | + unsigned nofs = vec_reg_offset(s, a->rn, index, esz); | ||
207 | + tcg_gen_gvec_dup_mem(esz, dofs, nofs, vsz, vsz); | ||
208 | + } else { | ||
209 | + tcg_gen_gvec_dup64i(dofs, vsz, vsz, 0); | ||
210 | + } | 69 | + } |
211 | + } | 70 | + } |
212 | + return true; | 71 | + same_el = (arm_current_el(env) == target_el); |
213 | +} | ||
214 | + | 72 | + |
215 | +static void do_insr_i64(DisasContext *s, arg_rrr_esz *a, TCGv_i64 val) | 73 | + fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); |
216 | +{ | ||
217 | + typedef void gen_insr(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); | ||
218 | + static gen_insr * const fns[4] = { | ||
219 | + gen_helper_sve_insr_b, gen_helper_sve_insr_h, | ||
220 | + gen_helper_sve_insr_s, gen_helper_sve_insr_d, | ||
221 | + }; | ||
222 | + unsigned vsz = vec_full_reg_size(s); | ||
223 | + TCGv_i32 desc = tcg_const_i32(simd_desc(vsz, vsz, 0)); | ||
224 | + TCGv_ptr t_zd = tcg_temp_new_ptr(); | ||
225 | + TCGv_ptr t_zn = tcg_temp_new_ptr(); | ||
226 | + | 74 | + |
227 | + tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); | 75 | if (access_type == MMU_INST_FETCH) { |
228 | + tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); | 76 | syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); |
229 | + | 77 | exc = EXCP_PREFETCH_ABORT; |
230 | + fns[a->esz](t_zd, t_zn, val, desc); | ||
231 | + | ||
232 | + tcg_temp_free_ptr(t_zd); | ||
233 | + tcg_temp_free_ptr(t_zn); | ||
234 | + tcg_temp_free_i32(desc); | ||
235 | +} | ||
236 | + | ||
237 | +static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
238 | +{ | ||
239 | + if (sve_access_check(s)) { | ||
240 | + TCGv_i64 t = tcg_temp_new_i64(); | ||
241 | + tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); | ||
242 | + do_insr_i64(s, a, t); | ||
243 | + tcg_temp_free_i64(t); | ||
244 | + } | ||
245 | + return true; | ||
246 | +} | ||
247 | + | ||
248 | +static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
249 | +{ | ||
250 | + if (sve_access_check(s)) { | ||
251 | + do_insr_i64(s, a, cpu_reg(s, a->rm)); | ||
252 | + } | ||
253 | + return true; | ||
254 | +} | ||
255 | + | ||
256 | +static bool trans_REV_v(DisasContext *s, arg_rr_esz *a, uint32_t insn) | ||
257 | +{ | ||
258 | + static gen_helper_gvec_2 * const fns[4] = { | ||
259 | + gen_helper_sve_rev_b, gen_helper_sve_rev_h, | ||
260 | + gen_helper_sve_rev_s, gen_helper_sve_rev_d | ||
261 | + }; | ||
262 | + | ||
263 | + if (sve_access_check(s)) { | ||
264 | + unsigned vsz = vec_full_reg_size(s); | ||
265 | + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), | ||
266 | + vec_full_reg_offset(s, a->rn), | ||
267 | + vsz, vsz, 0, fns[a->esz]); | ||
268 | + } | ||
269 | + return true; | ||
270 | +} | ||
271 | + | ||
272 | +static bool trans_TBL(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
273 | +{ | ||
274 | + static gen_helper_gvec_3 * const fns[4] = { | ||
275 | + gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, | ||
276 | + gen_helper_sve_tbl_s, gen_helper_sve_tbl_d | ||
277 | + }; | ||
278 | + | ||
279 | + if (sve_access_check(s)) { | ||
280 | + unsigned vsz = vec_full_reg_size(s); | ||
281 | + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | ||
282 | + vec_full_reg_offset(s, a->rn), | ||
283 | + vec_full_reg_offset(s, a->rm), | ||
284 | + vsz, vsz, 0, fns[a->esz]); | ||
285 | + } | ||
286 | + return true; | ||
287 | +} | ||
288 | + | ||
289 | +static bool trans_UNPK(DisasContext *s, arg_UNPK *a, uint32_t insn) | ||
290 | +{ | ||
291 | + static gen_helper_gvec_2 * const fns[4][2] = { | ||
292 | + { NULL, NULL }, | ||
293 | + { gen_helper_sve_sunpk_h, gen_helper_sve_uunpk_h }, | ||
294 | + { gen_helper_sve_sunpk_s, gen_helper_sve_uunpk_s }, | ||
295 | + { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, | ||
296 | + }; | ||
297 | + | ||
298 | + if (a->esz == 0) { | ||
299 | + return false; | ||
300 | + } | ||
301 | + if (sve_access_check(s)) { | ||
302 | + unsigned vsz = vec_full_reg_size(s); | ||
303 | + tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), | ||
304 | + vec_full_reg_offset(s, a->rn) | ||
305 | + + (a->h ? vsz / 2 : 0), | ||
306 | + vsz, vsz, 0, fns[a->esz][a->u]); | ||
307 | + } | ||
308 | + return true; | ||
309 | +} | ||
310 | + | ||
311 | /* | ||
312 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
313 | */ | ||
314 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/sve.decode | ||
317 | +++ b/target/arm/sve.decode | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | |||
320 | %imm4_16_p1 16:4 !function=plus1 | ||
321 | %imm6_22_5 22:1 5:5 | ||
322 | +%imm7_22_16 22:2 16:5 | ||
323 | %imm8_16_10 16:5 10:3 | ||
324 | %imm9_16_10 16:s6 10:3 | ||
325 | |||
326 | @@ -XXX,XX +XXX,XX @@ | ||
327 | |||
328 | # Three operand, vector element size | ||
329 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | ||
330 | +@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ | ||
331 | + &rrr_esz rn=%reg_movprfx | ||
332 | |||
333 | # Three operand with "memory" size, aka immediate left shift | ||
334 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | ||
335 | @@ -XXX,XX +XXX,XX @@ CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | ||
336 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | ||
337 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | ||
338 | |||
339 | +### SVE Permute - Unpredicated Group | ||
340 | + | ||
341 | +# SVE broadcast general register | ||
342 | +DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | ||
343 | + | ||
344 | +# SVE broadcast indexed element | ||
345 | +DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | ||
346 | + &rri imm=%imm7_22_16 | ||
347 | + | ||
348 | +# SVE insert SIMD&FP scalar register | ||
349 | +INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | ||
350 | + | ||
351 | +# SVE insert general register | ||
352 | +INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | ||
353 | + | ||
354 | +# SVE reverse vector elements | ||
355 | +REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | ||
356 | + | ||
357 | +# SVE vector table lookup | ||
358 | +TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | ||
359 | + | ||
360 | +# SVE unpack vector elements | ||
361 | +UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | ||
362 | + | ||
363 | ### SVE Predicate Logical Operations Group | ||
364 | |||
365 | # SVE predicate logical operations | ||
366 | -- | 78 | -- |
367 | 2.17.1 | 79 | 2.25.1 |
368 | 80 | ||
369 | 81 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | For A64, any input to an indirect branch can cause this. | ||
4 | |||
5 | For A32, many indirect branch paths force the branch to be aligned, | ||
6 | but BXWritePC does not. This includes the BX instruction but also | ||
7 | other interworking changes to PC. Prior to v8, this case is UNDEFINED. | ||
8 | With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an | ||
9 | exception or force align the PC. | ||
10 | |||
11 | We choose to raise an exception because we have the infrastructure, | ||
12 | it makes the generated code for gen_bx simpler, and it has the | ||
13 | possibility of catching more guest bugs. | ||
14 | |||
15 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20180613015641.5667-18-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 18 | --- |
8 | target/arm/helper-sve.h | 25 +++++++ | 19 | target/arm/helper.h | 1 + |
9 | target/arm/sve_helper.c | 41 +++++++++++ | 20 | target/arm/syndrome.h | 5 ++++ |
10 | target/arm/translate-sve.c | 144 +++++++++++++++++++++++++++++++++++++ | 21 | linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++--------------- |
11 | target/arm/sve.decode | 26 +++++++ | 22 | target/arm/tlb_helper.c | 18 ++++++++++++++ |
12 | 4 files changed, 236 insertions(+) | 23 | target/arm/translate-a64.c | 15 ++++++++++++ |
13 | 24 | target/arm/translate.c | 22 ++++++++++++++++- | |
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 25 | 6 files changed, 87 insertions(+), 20 deletions(-) |
15 | index XXXXXXX..XXXXXXX 100644 | 26 | |
16 | --- a/target/arm/helper-sve.h | 27 | diff --git a/target/arm/helper.h b/target/arm/helper.h |
17 | +++ b/target/arm/helper-sve.h | 28 | index XXXXXXX..XXXXXXX 100644 |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 29 | --- a/target/arm/helper.h |
19 | DEF_HELPER_FLAGS_3(sve_cntp, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) | 30 | +++ b/target/arm/helper.h |
20 | 31 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, | |
21 | DEF_HELPER_FLAGS_3(sve_while, TCG_CALL_NO_RWG, i32, ptr, i32, i32) | 32 | DEF_HELPER_2(exception_internal, void, env, i32) |
22 | + | 33 | DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) |
23 | +DEF_HELPER_FLAGS_4(sve_subri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 34 | DEF_HELPER_2(exception_bkpt_insn, void, env, i32) |
24 | +DEF_HELPER_FLAGS_4(sve_subri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 35 | +DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) |
25 | +DEF_HELPER_FLAGS_4(sve_subri_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 36 | DEF_HELPER_1(setend, void, env) |
26 | +DEF_HELPER_FLAGS_4(sve_subri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 37 | DEF_HELPER_2(wfi, void, env, i32) |
27 | + | 38 | DEF_HELPER_1(wfe, void, env) |
28 | +DEF_HELPER_FLAGS_4(sve_smaxi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 39 | diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h |
29 | +DEF_HELPER_FLAGS_4(sve_smaxi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 40 | index XXXXXXX..XXXXXXX 100644 |
30 | +DEF_HELPER_FLAGS_4(sve_smaxi_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 41 | --- a/target/arm/syndrome.h |
31 | +DEF_HELPER_FLAGS_4(sve_smaxi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 42 | +++ b/target/arm/syndrome.h |
32 | + | 43 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void) |
33 | +DEF_HELPER_FLAGS_4(sve_smini_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 44 | return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL; |
34 | +DEF_HELPER_FLAGS_4(sve_smini_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 45 | } |
35 | +DEF_HELPER_FLAGS_4(sve_smini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 46 | |
36 | +DEF_HELPER_FLAGS_4(sve_smini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 47 | +static inline uint32_t syn_pcalignment(void) |
37 | + | 48 | +{ |
38 | +DEF_HELPER_FLAGS_4(sve_umaxi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | 49 | + return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; |
39 | +DEF_HELPER_FLAGS_4(sve_umaxi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
40 | +DEF_HELPER_FLAGS_4(sve_umaxi_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
41 | +DEF_HELPER_FLAGS_4(sve_umaxi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
42 | + | ||
43 | +DEF_HELPER_FLAGS_4(sve_umini_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
44 | +DEF_HELPER_FLAGS_4(sve_umini_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
45 | +DEF_HELPER_FLAGS_4(sve_umini_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
46 | +DEF_HELPER_FLAGS_4(sve_umini_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) | ||
47 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/sve_helper.c | ||
50 | +++ b/target/arm/sve_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ DO_VPZ_D(sve_uminv_d, uint64_t, uint64_t, -1, DO_MIN) | ||
52 | #undef DO_VPZ | ||
53 | #undef DO_VPZ_D | ||
54 | |||
55 | +/* Two vector operand, one scalar operand, unpredicated. */ | ||
56 | +#define DO_ZZI(NAME, TYPE, OP) \ | ||
57 | +void HELPER(NAME)(void *vd, void *vn, uint64_t s64, uint32_t desc) \ | ||
58 | +{ \ | ||
59 | + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(TYPE); \ | ||
60 | + TYPE s = s64, *d = vd, *n = vn; \ | ||
61 | + for (i = 0; i < opr_sz; ++i) { \ | ||
62 | + d[i] = OP(n[i], s); \ | ||
63 | + } \ | ||
64 | +} | 50 | +} |
65 | + | 51 | + |
66 | +#define DO_SUBR(X, Y) (Y - X) | 52 | #endif /* TARGET_ARM_SYNDROME_H */ |
67 | + | 53 | diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c |
68 | +DO_ZZI(sve_subri_b, uint8_t, DO_SUBR) | 54 | index XXXXXXX..XXXXXXX 100644 |
69 | +DO_ZZI(sve_subri_h, uint16_t, DO_SUBR) | 55 | --- a/linux-user/aarch64/cpu_loop.c |
70 | +DO_ZZI(sve_subri_s, uint32_t, DO_SUBR) | 56 | +++ b/linux-user/aarch64/cpu_loop.c |
71 | +DO_ZZI(sve_subri_d, uint64_t, DO_SUBR) | 57 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
72 | + | 58 | break; |
73 | +DO_ZZI(sve_smaxi_b, int8_t, DO_MAX) | 59 | case EXCP_PREFETCH_ABORT: |
74 | +DO_ZZI(sve_smaxi_h, int16_t, DO_MAX) | 60 | case EXCP_DATA_ABORT: |
75 | +DO_ZZI(sve_smaxi_s, int32_t, DO_MAX) | 61 | - /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */ |
76 | +DO_ZZI(sve_smaxi_d, int64_t, DO_MAX) | 62 | ec = syn_get_ec(env->exception.syndrome); |
77 | + | 63 | - assert(ec == EC_DATAABORT || ec == EC_INSNABORT); |
78 | +DO_ZZI(sve_smini_b, int8_t, DO_MIN) | 64 | - |
79 | +DO_ZZI(sve_smini_h, int16_t, DO_MIN) | 65 | - /* Both EC have the same format for FSC, or close enough. */ |
80 | +DO_ZZI(sve_smini_s, int32_t, DO_MIN) | 66 | - fsc = extract32(env->exception.syndrome, 0, 6); |
81 | +DO_ZZI(sve_smini_d, int64_t, DO_MIN) | 67 | - switch (fsc) { |
82 | + | 68 | - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ |
83 | +DO_ZZI(sve_umaxi_b, uint8_t, DO_MAX) | 69 | - si_signo = TARGET_SIGSEGV; |
84 | +DO_ZZI(sve_umaxi_h, uint16_t, DO_MAX) | 70 | - si_code = TARGET_SEGV_MAPERR; |
85 | +DO_ZZI(sve_umaxi_s, uint32_t, DO_MAX) | 71 | + switch (ec) { |
86 | +DO_ZZI(sve_umaxi_d, uint64_t, DO_MAX) | 72 | + case EC_DATAABORT: |
87 | + | 73 | + case EC_INSNABORT: |
88 | +DO_ZZI(sve_umini_b, uint8_t, DO_MIN) | 74 | + /* Both EC have the same format for FSC, or close enough. */ |
89 | +DO_ZZI(sve_umini_h, uint16_t, DO_MIN) | 75 | + fsc = extract32(env->exception.syndrome, 0, 6); |
90 | +DO_ZZI(sve_umini_s, uint32_t, DO_MIN) | 76 | + switch (fsc) { |
91 | +DO_ZZI(sve_umini_d, uint64_t, DO_MIN) | 77 | + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ |
92 | + | 78 | + si_signo = TARGET_SIGSEGV; |
93 | +#undef DO_ZZI | 79 | + si_code = TARGET_SEGV_MAPERR; |
94 | + | 80 | + break; |
95 | #undef DO_AND | 81 | + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ |
96 | #undef DO_ORR | 82 | + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ |
97 | #undef DO_EOR | 83 | + si_signo = TARGET_SIGSEGV; |
98 | @@ -XXX,XX +XXX,XX @@ DO_VPZ_D(sve_uminv_d, uint64_t, uint64_t, -1, DO_MIN) | 84 | + si_code = TARGET_SEGV_ACCERR; |
99 | #undef DO_ASR | 85 | + break; |
100 | #undef DO_LSR | 86 | + case 0x11: /* Synchronous Tag Check Fault */ |
101 | #undef DO_LSL | 87 | + si_signo = TARGET_SIGSEGV; |
102 | +#undef DO_SUBR | 88 | + si_code = TARGET_SEGV_MTESERR; |
103 | 89 | + break; | |
104 | /* Similar to the ARM LastActiveElement pseudocode function, except the | 90 | + case 0x21: /* Alignment fault */ |
105 | result is multiplied by the element size. This includes the not found | 91 | + si_signo = TARGET_SIGBUS; |
106 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 92 | + si_code = TARGET_BUS_ADRALN; |
107 | index XXXXXXX..XXXXXXX 100644 | 93 | + break; |
108 | --- a/target/arm/translate-sve.c | 94 | + default: |
109 | +++ b/target/arm/translate-sve.c | 95 | + g_assert_not_reached(); |
110 | @@ -XXX,XX +XXX,XX @@ static inline int expand_imm_sh8s(int x) | 96 | + } |
111 | return (int8_t)x << (x & 0x100 ? 8 : 0); | 97 | break; |
98 | - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ | ||
99 | - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ | ||
100 | - si_signo = TARGET_SIGSEGV; | ||
101 | - si_code = TARGET_SEGV_ACCERR; | ||
102 | - break; | ||
103 | - case 0x11: /* Synchronous Tag Check Fault */ | ||
104 | - si_signo = TARGET_SIGSEGV; | ||
105 | - si_code = TARGET_SEGV_MTESERR; | ||
106 | - break; | ||
107 | - case 0x21: /* Alignment fault */ | ||
108 | + case EC_PCALIGNMENT: | ||
109 | si_signo = TARGET_SIGBUS; | ||
110 | si_code = TARGET_BUS_ADRALN; | ||
111 | break; | ||
112 | diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/tlb_helper.c | ||
115 | +++ b/target/arm/tlb_helper.c | ||
116 | @@ -XXX,XX +XXX,XX @@ | ||
117 | #include "cpu.h" | ||
118 | #include "internals.h" | ||
119 | #include "exec/exec-all.h" | ||
120 | +#include "exec/helper-proto.h" | ||
121 | |||
122 | static inline uint32_t merge_syn_data_abort(uint32_t template_syn, | ||
123 | unsigned int target_el, | ||
124 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | ||
125 | arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); | ||
112 | } | 126 | } |
113 | 127 | ||
114 | +static inline int expand_imm_sh8u(int x) | 128 | +void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) |
115 | +{ | 129 | +{ |
116 | + return (uint8_t)x << (x & 0x100 ? 8 : 0); | 130 | + ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; |
131 | + int target_el = exception_target_el(env); | ||
132 | + int mmu_idx = cpu_mmu_index(env, true); | ||
133 | + uint32_t fsc; | ||
134 | + | ||
135 | + env->exception.vaddress = pc; | ||
136 | + | ||
137 | + /* | ||
138 | + * Note that the fsc is not applicable to this exception, | ||
139 | + * since any syndrome is pcalignment not insn_abort. | ||
140 | + */ | ||
141 | + env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc); | ||
142 | + raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el); | ||
117 | +} | 143 | +} |
118 | + | 144 | + |
145 | #if !defined(CONFIG_USER_ONLY) | ||
146 | |||
119 | /* | 147 | /* |
120 | * Include the generated decoder. | 148 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
121 | */ | 149 | index XXXXXXX..XXXXXXX 100644 |
122 | @@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn) | 150 | --- a/target/arm/translate-a64.c |
123 | return true; | 151 | +++ b/target/arm/translate-a64.c |
124 | } | 152 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) |
125 | 153 | uint64_t pc = s->base.pc_next; | |
126 | +static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | 154 | uint32_t insn; |
127 | +{ | 155 | |
128 | + if (a->esz == 0 && extract32(insn, 13, 1)) { | 156 | + /* Singlestep exceptions have the highest priority. */ |
129 | + return false; | 157 | if (s->ss_active && !s->pstate_ss) { |
158 | /* Singlestep state is Active-pending. | ||
159 | * If we're in this state at the start of a TB then either | ||
160 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
161 | return; | ||
162 | } | ||
163 | |||
164 | + if (pc & 3) { | ||
165 | + /* | ||
166 | + * PC alignment fault. This has priority over the instruction abort | ||
167 | + * that we would receive from a translation fault via arm_ldl_code. | ||
168 | + * This should only be possible after an indirect branch, at the | ||
169 | + * start of the TB. | ||
170 | + */ | ||
171 | + assert(s->base.num_insns == 1); | ||
172 | + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); | ||
173 | + s->base.is_jmp = DISAS_NORETURN; | ||
174 | + s->base.pc_next = QEMU_ALIGN_UP(pc, 4); | ||
175 | + return; | ||
130 | + } | 176 | + } |
131 | + if (sve_access_check(s)) { | 177 | + |
132 | + unsigned vsz = vec_full_reg_size(s); | 178 | s->pc_curr = pc; |
133 | + tcg_gen_gvec_addi(a->esz, vec_full_reg_offset(s, a->rd), | 179 | insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b); |
134 | + vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | 180 | s->insn = insn; |
181 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
182 | index XXXXXXX..XXXXXXX 100644 | ||
183 | --- a/target/arm/translate.c | ||
184 | +++ b/target/arm/translate.c | ||
185 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
186 | uint32_t pc = dc->base.pc_next; | ||
187 | unsigned int insn; | ||
188 | |||
189 | - if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { | ||
190 | + /* Singlestep exceptions have the highest priority. */ | ||
191 | + if (arm_check_ss_active(dc)) { | ||
192 | + dc->base.pc_next = pc + 4; | ||
193 | + return; | ||
135 | + } | 194 | + } |
136 | + return true; | 195 | + |
137 | +} | 196 | + if (pc & 3) { |
138 | + | 197 | + /* |
139 | +static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | 198 | + * PC alignment fault. This has priority over the instruction abort |
140 | +{ | 199 | + * that we would receive from a translation fault via arm_ldl_code |
141 | + a->imm = -a->imm; | 200 | + * (or the execution of the kernelpage entrypoint). This should only |
142 | + return trans_ADD_zzi(s, a, insn); | 201 | + * be possible after an indirect branch, at the start of the TB. |
143 | +} | 202 | + */ |
144 | + | 203 | + assert(dc->base.num_insns == 1); |
145 | +static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | 204 | + gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); |
146 | +{ | 205 | + dc->base.is_jmp = DISAS_NORETURN; |
147 | + static const GVecGen2s op[4] = { | 206 | + dc->base.pc_next = QEMU_ALIGN_UP(pc, 4); |
148 | + { .fni8 = tcg_gen_vec_sub8_i64, | 207 | + return; |
149 | + .fniv = tcg_gen_sub_vec, | ||
150 | + .fno = gen_helper_sve_subri_b, | ||
151 | + .opc = INDEX_op_sub_vec, | ||
152 | + .vece = MO_8, | ||
153 | + .scalar_first = true }, | ||
154 | + { .fni8 = tcg_gen_vec_sub16_i64, | ||
155 | + .fniv = tcg_gen_sub_vec, | ||
156 | + .fno = gen_helper_sve_subri_h, | ||
157 | + .opc = INDEX_op_sub_vec, | ||
158 | + .vece = MO_16, | ||
159 | + .scalar_first = true }, | ||
160 | + { .fni4 = tcg_gen_sub_i32, | ||
161 | + .fniv = tcg_gen_sub_vec, | ||
162 | + .fno = gen_helper_sve_subri_s, | ||
163 | + .opc = INDEX_op_sub_vec, | ||
164 | + .vece = MO_32, | ||
165 | + .scalar_first = true }, | ||
166 | + { .fni8 = tcg_gen_sub_i64, | ||
167 | + .fniv = tcg_gen_sub_vec, | ||
168 | + .fno = gen_helper_sve_subri_d, | ||
169 | + .opc = INDEX_op_sub_vec, | ||
170 | + .prefer_i64 = TCG_TARGET_REG_BITS == 64, | ||
171 | + .vece = MO_64, | ||
172 | + .scalar_first = true } | ||
173 | + }; | ||
174 | + | ||
175 | + if (a->esz == 0 && extract32(insn, 13, 1)) { | ||
176 | + return false; | ||
177 | + } | 208 | + } |
178 | + if (sve_access_check(s)) { | 209 | + |
179 | + unsigned vsz = vec_full_reg_size(s); | 210 | + if (arm_check_kernelpage(dc)) { |
180 | + TCGv_i64 c = tcg_const_i64(a->imm); | 211 | dc->base.pc_next = pc + 4; |
181 | + tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), | 212 | return; |
182 | + vec_full_reg_offset(s, a->rn), | 213 | } |
183 | + vsz, vsz, c, &op[a->esz]); | ||
184 | + tcg_temp_free_i64(c); | ||
185 | + } | ||
186 | + return true; | ||
187 | +} | ||
188 | + | ||
189 | +static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | ||
190 | +{ | ||
191 | + if (sve_access_check(s)) { | ||
192 | + unsigned vsz = vec_full_reg_size(s); | ||
193 | + tcg_gen_gvec_muli(a->esz, vec_full_reg_offset(s, a->rd), | ||
194 | + vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz); | ||
195 | + } | ||
196 | + return true; | ||
197 | +} | ||
198 | + | ||
199 | +static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, uint32_t insn, | ||
200 | + bool u, bool d) | ||
201 | +{ | ||
202 | + if (a->esz == 0 && extract32(insn, 13, 1)) { | ||
203 | + return false; | ||
204 | + } | ||
205 | + if (sve_access_check(s)) { | ||
206 | + TCGv_i64 val = tcg_const_i64(a->imm); | ||
207 | + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d); | ||
208 | + tcg_temp_free_i64(val); | ||
209 | + } | ||
210 | + return true; | ||
211 | +} | ||
212 | + | ||
213 | +static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | ||
214 | +{ | ||
215 | + return do_zzi_sat(s, a, insn, false, false); | ||
216 | +} | ||
217 | + | ||
218 | +static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | ||
219 | +{ | ||
220 | + return do_zzi_sat(s, a, insn, true, false); | ||
221 | +} | ||
222 | + | ||
223 | +static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | ||
224 | +{ | ||
225 | + return do_zzi_sat(s, a, insn, false, true); | ||
226 | +} | ||
227 | + | ||
228 | +static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a, uint32_t insn) | ||
229 | +{ | ||
230 | + return do_zzi_sat(s, a, insn, true, true); | ||
231 | +} | ||
232 | + | ||
233 | +static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn) | ||
234 | +{ | ||
235 | + if (sve_access_check(s)) { | ||
236 | + unsigned vsz = vec_full_reg_size(s); | ||
237 | + TCGv_i64 c = tcg_const_i64(a->imm); | ||
238 | + | ||
239 | + tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), | ||
240 | + vec_full_reg_offset(s, a->rn), | ||
241 | + c, vsz, vsz, 0, fn); | ||
242 | + tcg_temp_free_i64(c); | ||
243 | + } | ||
244 | + return true; | ||
245 | +} | ||
246 | + | ||
247 | +#define DO_ZZI(NAME, name) \ | ||
248 | +static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a, \ | ||
249 | + uint32_t insn) \ | ||
250 | +{ \ | ||
251 | + static gen_helper_gvec_2i * const fns[4] = { \ | ||
252 | + gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ | ||
253 | + gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \ | ||
254 | + }; \ | ||
255 | + return do_zzi_ool(s, a, fns[a->esz]); \ | ||
256 | +} | ||
257 | + | ||
258 | +DO_ZZI(SMAX, smax) | ||
259 | +DO_ZZI(UMAX, umax) | ||
260 | +DO_ZZI(SMIN, smin) | ||
261 | +DO_ZZI(UMIN, umin) | ||
262 | + | ||
263 | +#undef DO_ZZI | ||
264 | + | ||
265 | /* | ||
266 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
267 | */ | ||
268 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
269 | index XXXXXXX..XXXXXXX 100644 | ||
270 | --- a/target/arm/sve.decode | ||
271 | +++ b/target/arm/sve.decode | ||
272 | @@ -XXX,XX +XXX,XX @@ | ||
273 | |||
274 | # Signed 8-bit immediate, optionally shifted left by 8. | ||
275 | %sh8_i8s 5:9 !function=expand_imm_sh8s | ||
276 | +# Unsigned 8-bit immediate, optionally shifted left by 8. | ||
277 | +%sh8_i8u 5:9 !function=expand_imm_sh8u | ||
278 | |||
279 | # Either a copy of rd (at bit 0), or a different source | ||
280 | # as propagated via the MOVPRFX instruction. | ||
281 | @@ -XXX,XX +XXX,XX @@ | ||
282 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz | ||
283 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ | ||
284 | &rrr_esz rn=%reg_movprfx | ||
285 | +@rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ | ||
286 | + &rri_esz rn=%reg_movprfx imm=%sh8_i8u | ||
287 | +@rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | ||
288 | + &rri_esz rn=%reg_movprfx | ||
289 | +@rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | ||
290 | + &rri_esz rn=%reg_movprfx | ||
291 | |||
292 | # Three operand with "memory" size, aka immediate left shift | ||
293 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | ||
294 | @@ -XXX,XX +XXX,XX @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | ||
295 | # SVE broadcast integer immediate (unpredicated) | ||
296 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | ||
297 | |||
298 | +# SVE integer add/subtract immediate (unpredicated) | ||
299 | +ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | ||
300 | +SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | ||
301 | +SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | ||
302 | +SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | ||
303 | +UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | ||
304 | +SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | ||
305 | +UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | ||
306 | + | ||
307 | +# SVE integer min/max immediate (unpredicated) | ||
308 | +SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | ||
309 | +UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | ||
310 | +SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | ||
311 | +UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | ||
312 | + | ||
313 | +# SVE integer multiply immediate (unpredicated) | ||
314 | +MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | ||
315 | + | ||
316 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
317 | |||
318 | # SVE load predicate register | ||
319 | -- | 214 | -- |
320 | 2.17.1 | 215 | 2.25.1 |
321 | 216 | ||
322 | 217 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Rearrange the arithmetic so that we are agnostic about the total size | 3 | Misaligned thumb PC is architecturally impossible. |
4 | of the vector and the size of the element. This will allow us to index | 4 | Assert is better than proceeding, in case we've missed |
5 | up to the 32nd byte and with 16-byte elements. | 5 | something somewhere. |
6 | |||
7 | Expand a comment about aligning the pc in gdbstub. | ||
8 | Fail an incoming migrate if a thumb pc is misaligned. | ||
6 | 9 | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20180613015641.5667-2-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 13 | --- |
12 | target/arm/translate-a64.h | 26 +++++++++++++++++--------- | 14 | target/arm/gdbstub.c | 9 +++++++-- |
13 | 1 file changed, 17 insertions(+), 9 deletions(-) | 15 | target/arm/machine.c | 10 ++++++++++ |
16 | target/arm/translate.c | 3 +++ | ||
17 | 3 files changed, 20 insertions(+), 2 deletions(-) | ||
14 | 18 | ||
15 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | 19 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.h | 21 | --- a/target/arm/gdbstub.c |
18 | +++ b/target/arm/translate-a64.h | 22 | +++ b/target/arm/gdbstub.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline void assert_fp_access_checked(DisasContext *s) | 23 | @@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
20 | static inline int vec_reg_offset(DisasContext *s, int regno, | 24 | |
21 | int element, TCGMemOp size) | 25 | tmp = ldl_p(mem_buf); |
22 | { | 26 | |
23 | - int offs = 0; | 27 | - /* Mask out low bit of PC to workaround gdb bugs. This will probably |
24 | + int element_size = 1 << size; | 28 | - cause problems if we ever implement the Jazelle DBX extensions. */ |
25 | + int offs = element * element_size; | 29 | + /* |
26 | #ifdef HOST_WORDS_BIGENDIAN | 30 | + * Mask out low bits of PC to workaround gdb bugs. |
27 | /* This is complicated slightly because vfp.zregs[n].d[0] is | 31 | + * This avoids an assert in thumb_tr_translate_insn, because it is |
28 | - * still the low half and vfp.zregs[n].d[1] the high half | 32 | + * architecturally impossible to misalign the pc. |
29 | - * of the 128 bit vector, even on big endian systems. | 33 | + * This will probably cause problems if we ever implement the |
30 | - * Calculate the offset assuming a fully bigendian 128 bits, | 34 | + * Jazelle DBX extensions. |
31 | - * then XOR to account for the order of the two 64 bit halves. | 35 | + */ |
32 | + * still the lowest and vfp.zregs[n].d[15] the highest of the | 36 | if (n == 15) { |
33 | + * 256 byte vector, even on big endian systems. | 37 | tmp &= ~1; |
34 | + * | 38 | } |
35 | + * Calculate the offset assuming fully little-endian, | 39 | diff --git a/target/arm/machine.c b/target/arm/machine.c |
36 | + * then XOR to account for the order of the 8-byte units. | 40 | index XXXXXXX..XXXXXXX 100644 |
37 | + * | 41 | --- a/target/arm/machine.c |
38 | + * For 16 byte elements, the two 8 byte halves will not form a | 42 | +++ b/target/arm/machine.c |
39 | + * host int128 if the host is bigendian, since they're in the | 43 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
40 | + * wrong order. However the only 16 byte operation we have is | 44 | return -1; |
41 | + * a move, so we can ignore this for the moment. More complicated | 45 | } |
42 | + * operations will have to special case loading and storing from | 46 | } |
43 | + * the zregs array. | 47 | + |
44 | */ | 48 | + /* |
45 | - offs += (16 - ((element + 1) * (1 << size))); | 49 | + * Misaligned thumb pc is architecturally impossible. |
46 | - offs ^= 8; | 50 | + * We have an assert in thumb_tr_translate_insn to verify this. |
47 | -#else | 51 | + * Fail an incoming migrate to avoid this assert. |
48 | - offs += element * (1 << size); | 52 | + */ |
49 | + if (element_size < 8) { | 53 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { |
50 | + offs ^= 8 - element_size; | 54 | + return -1; |
51 | + } | 55 | + } |
52 | #endif | 56 | + |
53 | offs += offsetof(CPUARMState, vfp.zregs[regno]); | 57 | if (!kvm_enabled()) { |
54 | assert_fp_access_checked(s); | 58 | pmu_op_finish(&cpu->env); |
59 | } | ||
60 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/translate.c | ||
63 | +++ b/target/arm/translate.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) | ||
65 | uint32_t insn; | ||
66 | bool is_16bit; | ||
67 | |||
68 | + /* Misaligned thumb PC is architecturally impossible. */ | ||
69 | + assert((dc->base.pc_next & 1) == 0); | ||
70 | + | ||
71 | if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) { | ||
72 | dc->base.pc_next = pc + 2; | ||
73 | return; | ||
55 | -- | 74 | -- |
56 | 2.17.1 | 75 | 2.25.1 |
57 | 76 | ||
58 | 77 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | |||
3 | Both single-step and pc alignment faults have priority over | ||
4 | breakpoint exceptions. | ||
2 | 5 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180613015641.5667-7-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 9 | --- |
8 | target/arm/helper-sve.h | 2 + | 10 | target/arm/debug_helper.c | 23 +++++++++++++++++++++++ |
9 | target/arm/sve_helper.c | 12 ++ | 11 | 1 file changed, 23 insertions(+) |
10 | target/arm/translate-sve.c | 328 +++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/sve.decode | 20 +++ | ||
12 | 4 files changed, 362 insertions(+) | ||
13 | 12 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 13 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 15 | --- a/target/arm/debug_helper.c |
17 | +++ b/target/arm/helper-sve.h | 16 | +++ b/target/arm/debug_helper.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_trn_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 17 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs) |
19 | DEF_HELPER_FLAGS_4(sve_compact_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 18 | { |
20 | DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 19 | ARMCPU *cpu = ARM_CPU(cs); |
21 | 20 | CPUARMState *env = &cpu->env; | |
22 | +DEF_HELPER_FLAGS_2(sve_last_active_element, TCG_CALL_NO_RWG, s32, ptr, i32) | 21 | + target_ulong pc; |
23 | + | 22 | int n; |
24 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 23 | |
25 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 24 | /* |
26 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 25 | @@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs) |
27 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 26 | return false; |
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/sve_helper.c | ||
30 | +++ b/target/arm/sve_helper.c | ||
31 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc) | ||
32 | d[j] = 0; | ||
33 | } | 27 | } |
34 | } | 28 | |
35 | + | 29 | + /* |
36 | +/* Similar to the ARM LastActiveElement pseudocode function, except the | 30 | + * Single-step exceptions have priority over breakpoint exceptions. |
37 | + * result is multiplied by the element size. This includes the not found | 31 | + * If single-step state is active-pending, suppress the bp. |
38 | + * indication; e.g. not found for esz=3 is -8. | ||
39 | + */ | ||
40 | +int32_t HELPER(sve_last_active_element)(void *vg, uint32_t pred_desc) | ||
41 | +{ | ||
42 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
43 | + intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | ||
44 | + | ||
45 | + return last_active_element(vg, DIV_ROUND_UP(oprsz, 8), esz); | ||
46 | +} | ||
47 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/translate-sve.c | ||
50 | +++ b/target/arm/translate-sve.c | ||
51 | @@ -XXX,XX +XXX,XX @@ static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
52 | return do_zpz_ool(s, a, fns[a->esz]); | ||
53 | } | ||
54 | |||
55 | +/* Call the helper that computes the ARM LastActiveElement pseudocode | ||
56 | + * function, scaled by the element size. This includes the not found | ||
57 | + * indication; e.g. not found for esz=3 is -8. | ||
58 | + */ | ||
59 | +static void find_last_active(DisasContext *s, TCGv_i32 ret, int esz, int pg) | ||
60 | +{ | ||
61 | + /* Predicate sizes may be smaller and cannot use simd_desc. We cannot | ||
62 | + * round up, as we do elsewhere, because we need the exact size. | ||
63 | + */ | 32 | + */ |
64 | + TCGv_ptr t_p = tcg_temp_new_ptr(); | 33 | + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { |
65 | + TCGv_i32 t_desc; | 34 | + return false; |
66 | + unsigned vsz = pred_full_reg_size(s); | ||
67 | + unsigned desc; | ||
68 | + | ||
69 | + desc = vsz - 2; | ||
70 | + desc = deposit32(desc, SIMD_DATA_SHIFT, 2, esz); | ||
71 | + | ||
72 | + tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); | ||
73 | + t_desc = tcg_const_i32(desc); | ||
74 | + | ||
75 | + gen_helper_sve_last_active_element(ret, t_p, t_desc); | ||
76 | + | ||
77 | + tcg_temp_free_i32(t_desc); | ||
78 | + tcg_temp_free_ptr(t_p); | ||
79 | +} | ||
80 | + | ||
81 | +/* Increment LAST to the offset of the next element in the vector, | ||
82 | + * wrapping around to 0. | ||
83 | + */ | ||
84 | +static void incr_last_active(DisasContext *s, TCGv_i32 last, int esz) | ||
85 | +{ | ||
86 | + unsigned vsz = vec_full_reg_size(s); | ||
87 | + | ||
88 | + tcg_gen_addi_i32(last, last, 1 << esz); | ||
89 | + if (is_power_of_2(vsz)) { | ||
90 | + tcg_gen_andi_i32(last, last, vsz - 1); | ||
91 | + } else { | ||
92 | + TCGv_i32 max = tcg_const_i32(vsz); | ||
93 | + TCGv_i32 zero = tcg_const_i32(0); | ||
94 | + tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); | ||
95 | + tcg_temp_free_i32(max); | ||
96 | + tcg_temp_free_i32(zero); | ||
97 | + } | ||
98 | +} | ||
99 | + | ||
100 | +/* If LAST < 0, set LAST to the offset of the last element in the vector. */ | ||
101 | +static void wrap_last_active(DisasContext *s, TCGv_i32 last, int esz) | ||
102 | +{ | ||
103 | + unsigned vsz = vec_full_reg_size(s); | ||
104 | + | ||
105 | + if (is_power_of_2(vsz)) { | ||
106 | + tcg_gen_andi_i32(last, last, vsz - 1); | ||
107 | + } else { | ||
108 | + TCGv_i32 max = tcg_const_i32(vsz - (1 << esz)); | ||
109 | + TCGv_i32 zero = tcg_const_i32(0); | ||
110 | + tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); | ||
111 | + tcg_temp_free_i32(max); | ||
112 | + tcg_temp_free_i32(zero); | ||
113 | + } | ||
114 | +} | ||
115 | + | ||
116 | +/* Load an unsigned element of ESZ from BASE+OFS. */ | ||
117 | +static TCGv_i64 load_esz(TCGv_ptr base, int ofs, int esz) | ||
118 | +{ | ||
119 | + TCGv_i64 r = tcg_temp_new_i64(); | ||
120 | + | ||
121 | + switch (esz) { | ||
122 | + case 0: | ||
123 | + tcg_gen_ld8u_i64(r, base, ofs); | ||
124 | + break; | ||
125 | + case 1: | ||
126 | + tcg_gen_ld16u_i64(r, base, ofs); | ||
127 | + break; | ||
128 | + case 2: | ||
129 | + tcg_gen_ld32u_i64(r, base, ofs); | ||
130 | + break; | ||
131 | + case 3: | ||
132 | + tcg_gen_ld_i64(r, base, ofs); | ||
133 | + break; | ||
134 | + default: | ||
135 | + g_assert_not_reached(); | ||
136 | + } | ||
137 | + return r; | ||
138 | +} | ||
139 | + | ||
140 | +/* Load an unsigned element of ESZ from RM[LAST]. */ | ||
141 | +static TCGv_i64 load_last_active(DisasContext *s, TCGv_i32 last, | ||
142 | + int rm, int esz) | ||
143 | +{ | ||
144 | + TCGv_ptr p = tcg_temp_new_ptr(); | ||
145 | + TCGv_i64 r; | ||
146 | + | ||
147 | + /* Convert offset into vector into offset into ENV. | ||
148 | + * The final adjustment for the vector register base | ||
149 | + * is added via constant offset to the load. | ||
150 | + */ | ||
151 | +#ifdef HOST_WORDS_BIGENDIAN | ||
152 | + /* Adjust for element ordering. See vec_reg_offset. */ | ||
153 | + if (esz < 3) { | ||
154 | + tcg_gen_xori_i32(last, last, 8 - (1 << esz)); | ||
155 | + } | ||
156 | +#endif | ||
157 | + tcg_gen_ext_i32_ptr(p, last); | ||
158 | + tcg_gen_add_ptr(p, p, cpu_env); | ||
159 | + | ||
160 | + r = load_esz(p, vec_full_reg_offset(s, rm), esz); | ||
161 | + tcg_temp_free_ptr(p); | ||
162 | + | ||
163 | + return r; | ||
164 | +} | ||
165 | + | ||
166 | +/* Compute CLAST for a Zreg. */ | ||
167 | +static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before) | ||
168 | +{ | ||
169 | + TCGv_i32 last; | ||
170 | + TCGLabel *over; | ||
171 | + TCGv_i64 ele; | ||
172 | + unsigned vsz, esz = a->esz; | ||
173 | + | ||
174 | + if (!sve_access_check(s)) { | ||
175 | + return true; | ||
176 | + } | 35 | + } |
177 | + | 36 | + |
178 | + last = tcg_temp_local_new_i32(); | 37 | + /* |
179 | + over = gen_new_label(); | 38 | + * PC alignment faults have priority over breakpoint exceptions. |
180 | + | ||
181 | + find_last_active(s, last, esz, a->pg); | ||
182 | + | ||
183 | + /* There is of course no movcond for a 2048-bit vector, | ||
184 | + * so we must branch over the actual store. | ||
185 | + */ | 39 | + */ |
186 | + tcg_gen_brcondi_i32(TCG_COND_LT, last, 0, over); | 40 | + pc = is_a64(env) ? env->pc : env->regs[15]; |
187 | + | 41 | + if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) { |
188 | + if (!before) { | 42 | + return false; |
189 | + incr_last_active(s, last, esz); | ||
190 | + } | 43 | + } |
191 | + | 44 | + |
192 | + ele = load_last_active(s, last, a->rm, esz); | 45 | + /* |
193 | + tcg_temp_free_i32(last); | 46 | + * Instruction aborts have priority over breakpoint exceptions. |
47 | + * TODO: We would need to look up the page for PC and verify that | ||
48 | + * it is present and executable. | ||
49 | + */ | ||
194 | + | 50 | + |
195 | + vsz = vec_full_reg_size(s); | 51 | for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { |
196 | + tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), vsz, vsz, ele); | 52 | if (bp_wp_matches(cpu, n, false)) { |
197 | + tcg_temp_free_i64(ele); | 53 | return true; |
198 | + | ||
199 | + /* If this insn used MOVPRFX, we may need a second move. */ | ||
200 | + if (a->rd != a->rn) { | ||
201 | + TCGLabel *done = gen_new_label(); | ||
202 | + tcg_gen_br(done); | ||
203 | + | ||
204 | + gen_set_label(over); | ||
205 | + do_mov_z(s, a->rd, a->rn); | ||
206 | + | ||
207 | + gen_set_label(done); | ||
208 | + } else { | ||
209 | + gen_set_label(over); | ||
210 | + } | ||
211 | + return true; | ||
212 | +} | ||
213 | + | ||
214 | +static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | ||
215 | +{ | ||
216 | + return do_clast_vector(s, a, false); | ||
217 | +} | ||
218 | + | ||
219 | +static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a, uint32_t insn) | ||
220 | +{ | ||
221 | + return do_clast_vector(s, a, true); | ||
222 | +} | ||
223 | + | ||
224 | +/* Compute CLAST for a scalar. */ | ||
225 | +static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, | ||
226 | + bool before, TCGv_i64 reg_val) | ||
227 | +{ | ||
228 | + TCGv_i32 last = tcg_temp_new_i32(); | ||
229 | + TCGv_i64 ele, cmp, zero; | ||
230 | + | ||
231 | + find_last_active(s, last, esz, pg); | ||
232 | + | ||
233 | + /* Extend the original value of last prior to incrementing. */ | ||
234 | + cmp = tcg_temp_new_i64(); | ||
235 | + tcg_gen_ext_i32_i64(cmp, last); | ||
236 | + | ||
237 | + if (!before) { | ||
238 | + incr_last_active(s, last, esz); | ||
239 | + } | ||
240 | + | ||
241 | + /* The conceit here is that while last < 0 indicates not found, after | ||
242 | + * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address | ||
243 | + * from which we can load garbage. We then discard the garbage with | ||
244 | + * a conditional move. | ||
245 | + */ | ||
246 | + ele = load_last_active(s, last, rm, esz); | ||
247 | + tcg_temp_free_i32(last); | ||
248 | + | ||
249 | + zero = tcg_const_i64(0); | ||
250 | + tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val); | ||
251 | + | ||
252 | + tcg_temp_free_i64(zero); | ||
253 | + tcg_temp_free_i64(cmp); | ||
254 | + tcg_temp_free_i64(ele); | ||
255 | +} | ||
256 | + | ||
257 | +/* Compute CLAST for a Vreg. */ | ||
258 | +static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before) | ||
259 | +{ | ||
260 | + if (sve_access_check(s)) { | ||
261 | + int esz = a->esz; | ||
262 | + int ofs = vec_reg_offset(s, a->rd, 0, esz); | ||
263 | + TCGv_i64 reg = load_esz(cpu_env, ofs, esz); | ||
264 | + | ||
265 | + do_clast_scalar(s, esz, a->pg, a->rn, before, reg); | ||
266 | + write_fp_dreg(s, a->rd, reg); | ||
267 | + tcg_temp_free_i64(reg); | ||
268 | + } | ||
269 | + return true; | ||
270 | +} | ||
271 | + | ||
272 | +static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
273 | +{ | ||
274 | + return do_clast_fp(s, a, false); | ||
275 | +} | ||
276 | + | ||
277 | +static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
278 | +{ | ||
279 | + return do_clast_fp(s, a, true); | ||
280 | +} | ||
281 | + | ||
282 | +/* Compute CLAST for a Xreg. */ | ||
283 | +static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before) | ||
284 | +{ | ||
285 | + TCGv_i64 reg; | ||
286 | + | ||
287 | + if (!sve_access_check(s)) { | ||
288 | + return true; | ||
289 | + } | ||
290 | + | ||
291 | + reg = cpu_reg(s, a->rd); | ||
292 | + switch (a->esz) { | ||
293 | + case 0: | ||
294 | + tcg_gen_ext8u_i64(reg, reg); | ||
295 | + break; | ||
296 | + case 1: | ||
297 | + tcg_gen_ext16u_i64(reg, reg); | ||
298 | + break; | ||
299 | + case 2: | ||
300 | + tcg_gen_ext32u_i64(reg, reg); | ||
301 | + break; | ||
302 | + case 3: | ||
303 | + break; | ||
304 | + default: | ||
305 | + g_assert_not_reached(); | ||
306 | + } | ||
307 | + | ||
308 | + do_clast_scalar(s, a->esz, a->pg, a->rn, before, reg); | ||
309 | + return true; | ||
310 | +} | ||
311 | + | ||
312 | +static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
313 | +{ | ||
314 | + return do_clast_general(s, a, false); | ||
315 | +} | ||
316 | + | ||
317 | +static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
318 | +{ | ||
319 | + return do_clast_general(s, a, true); | ||
320 | +} | ||
321 | + | ||
322 | +/* Compute LAST for a scalar. */ | ||
323 | +static TCGv_i64 do_last_scalar(DisasContext *s, int esz, | ||
324 | + int pg, int rm, bool before) | ||
325 | +{ | ||
326 | + TCGv_i32 last = tcg_temp_new_i32(); | ||
327 | + TCGv_i64 ret; | ||
328 | + | ||
329 | + find_last_active(s, last, esz, pg); | ||
330 | + if (before) { | ||
331 | + wrap_last_active(s, last, esz); | ||
332 | + } else { | ||
333 | + incr_last_active(s, last, esz); | ||
334 | + } | ||
335 | + | ||
336 | + ret = load_last_active(s, last, rm, esz); | ||
337 | + tcg_temp_free_i32(last); | ||
338 | + return ret; | ||
339 | +} | ||
340 | + | ||
341 | +/* Compute LAST for a Vreg. */ | ||
342 | +static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before) | ||
343 | +{ | ||
344 | + if (sve_access_check(s)) { | ||
345 | + TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | ||
346 | + write_fp_dreg(s, a->rd, val); | ||
347 | + tcg_temp_free_i64(val); | ||
348 | + } | ||
349 | + return true; | ||
350 | +} | ||
351 | + | ||
352 | +static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
353 | +{ | ||
354 | + return do_last_fp(s, a, false); | ||
355 | +} | ||
356 | + | ||
357 | +static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
358 | +{ | ||
359 | + return do_last_fp(s, a, true); | ||
360 | +} | ||
361 | + | ||
362 | +/* Compute LAST for a Xreg. */ | ||
363 | +static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before) | ||
364 | +{ | ||
365 | + if (sve_access_check(s)) { | ||
366 | + TCGv_i64 val = do_last_scalar(s, a->esz, a->pg, a->rn, before); | ||
367 | + tcg_gen_mov_i64(cpu_reg(s, a->rd), val); | ||
368 | + tcg_temp_free_i64(val); | ||
369 | + } | ||
370 | + return true; | ||
371 | +} | ||
372 | + | ||
373 | +static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
374 | +{ | ||
375 | + return do_last_general(s, a, false); | ||
376 | +} | ||
377 | + | ||
378 | +static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
379 | +{ | ||
380 | + return do_last_general(s, a, true); | ||
381 | +} | ||
382 | + | ||
383 | /* | ||
384 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
385 | */ | ||
386 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
387 | index XXXXXXX..XXXXXXX 100644 | ||
388 | --- a/target/arm/sve.decode | ||
389 | +++ b/target/arm/sve.decode | ||
390 | @@ -XXX,XX +XXX,XX @@ TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | ||
391 | # Note esz >= 2 | ||
392 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | ||
393 | |||
394 | +# SVE conditionally broadcast element to vector | ||
395 | +CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | ||
396 | +CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | ||
397 | + | ||
398 | +# SVE conditionally copy element to SIMD&FP scalar | ||
399 | +CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | ||
400 | +CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | ||
401 | + | ||
402 | +# SVE conditionally copy element to general register | ||
403 | +CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | ||
404 | +CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | ||
405 | + | ||
406 | +# SVE copy element to SIMD&FP scalar register | ||
407 | +LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | ||
408 | +LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | ||
409 | + | ||
410 | +# SVE copy element to general register | ||
411 | +LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | ||
412 | +LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | ||
413 | + | ||
414 | ### SVE Predicate Logical Operations Group | ||
415 | |||
416 | # SVE predicate logical operations | ||
417 | -- | 54 | -- |
418 | 2.17.1 | 55 | 2.25.1 |
419 | 56 | ||
420 | 57 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180613015641.5667-14-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 6 | --- |
8 | target/arm/helper-sve.h | 18 +++ | 7 | tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++ |
9 | target/arm/sve_helper.c | 248 +++++++++++++++++++++++++++++++++++++ | 8 | tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++ |
10 | target/arm/translate-sve.c | 106 ++++++++++++++++ | 9 | tests/tcg/aarch64/Makefile.target | 4 +-- |
11 | target/arm/sve.decode | 19 +++ | 10 | tests/tcg/arm/Makefile.target | 4 +++ |
12 | 4 files changed, 391 insertions(+) | 11 | 4 files changed, 89 insertions(+), 2 deletions(-) |
12 | create mode 100644 tests/tcg/aarch64/pcalign-a64.c | ||
13 | create mode 100644 tests/tcg/arm/pcalign-a32.c | ||
13 | 14 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 15 | diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | new file mode 100644 |
16 | --- a/target/arm/helper-sve.h | 17 | index XXXXXXX..XXXXXXX |
17 | +++ b/target/arm/helper-sve.h | 18 | --- /dev/null |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(sve_orn_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 19 | +++ b/tests/tcg/aarch64/pcalign-a64.c |
19 | DEF_HELPER_FLAGS_5(sve_nor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 20 | @@ -XXX,XX +XXX,XX @@ |
20 | DEF_HELPER_FLAGS_5(sve_nand_pppp, TCG_CALL_NO_RWG, | 21 | +/* Test PC misalignment exception */ |
21 | void, ptr, ptr, ptr, ptr, i32) | ||
22 | + | 22 | + |
23 | +DEF_HELPER_FLAGS_5(sve_brkpa, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 23 | +#include <assert.h> |
24 | +DEF_HELPER_FLAGS_5(sve_brkpb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 24 | +#include <signal.h> |
25 | +DEF_HELPER_FLAGS_5(sve_brkpas, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, ptr, i32) | 25 | +#include <stdlib.h> |
26 | +DEF_HELPER_FLAGS_5(sve_brkpbs, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, ptr, i32) | 26 | +#include <stdio.h> |
27 | + | 27 | + |
28 | +DEF_HELPER_FLAGS_4(sve_brka_z, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 28 | +static void *expected; |
29 | +DEF_HELPER_FLAGS_4(sve_brkb_z, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_4(sve_brka_m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_4(sve_brkb_m, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
32 | + | 29 | + |
33 | +DEF_HELPER_FLAGS_4(sve_brkas_z, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | 30 | +static void sigbus(int sig, siginfo_t *info, void *vuc) |
34 | +DEF_HELPER_FLAGS_4(sve_brkbs_z, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_4(sve_brkas_m, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
36 | +DEF_HELPER_FLAGS_4(sve_brkbs_m, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
37 | + | ||
38 | +DEF_HELPER_FLAGS_4(sve_brkn, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(sve_brkns, TCG_CALL_NO_RWG, i32, ptr, ptr, ptr, i32) | ||
40 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/sve_helper.c | ||
43 | +++ b/target/arm/sve_helper.c | ||
44 | @@ -XXX,XX +XXX,XX @@ DO_CMP_PPZI_D(sve_cmpls_ppzi_d, uint64_t, <=) | ||
45 | #undef DO_CMP_PPZI_S | ||
46 | #undef DO_CMP_PPZI_D | ||
47 | #undef DO_CMP_PPZI | ||
48 | + | ||
49 | +/* Similar to the ARM LastActive pseudocode function. */ | ||
50 | +static bool last_active_pred(void *vd, void *vg, intptr_t oprsz) | ||
51 | +{ | 31 | +{ |
52 | + intptr_t i; | 32 | + assert(info->si_code == BUS_ADRALN); |
53 | + | 33 | + assert(info->si_addr == expected); |
54 | + for (i = QEMU_ALIGN_UP(oprsz, 8) - 8; i >= 0; i -= 8) { | 34 | + exit(EXIT_SUCCESS); |
55 | + uint64_t pg = *(uint64_t *)(vg + i); | ||
56 | + if (pg) { | ||
57 | + return (pow2floor(pg) & *(uint64_t *)(vd + i)) != 0; | ||
58 | + } | ||
59 | + } | ||
60 | + return 0; | ||
61 | +} | 35 | +} |
62 | + | 36 | + |
63 | +/* Compute a mask into RETB that is true for all G, up to and including | 37 | +int main() |
64 | + * (if after) or excluding (if !after) the first G & N. | ||
65 | + * Return true if BRK found. | ||
66 | + */ | ||
67 | +static bool compute_brk(uint64_t *retb, uint64_t n, uint64_t g, | ||
68 | + bool brk, bool after) | ||
69 | +{ | 38 | +{ |
70 | + uint64_t b; | 39 | + void *tmp; |
71 | + | 40 | + |
72 | + if (brk) { | 41 | + struct sigaction sa = { |
73 | + b = 0; | 42 | + .sa_sigaction = sigbus, |
74 | + } else if ((g & n) == 0) { | 43 | + .sa_flags = SA_SIGINFO |
75 | + /* For all G, no N are set; break not found. */ | 44 | + }; |
76 | + b = g; | 45 | + |
77 | + } else { | 46 | + if (sigaction(SIGBUS, &sa, NULL) < 0) { |
78 | + /* Break somewhere in N. Locate it. */ | 47 | + perror("sigaction"); |
79 | + b = g & n; /* guard true, pred true */ | 48 | + return EXIT_FAILURE; |
80 | + b = b & -b; /* first such */ | ||
81 | + if (after) { | ||
82 | + b = b | (b - 1); /* break after same */ | ||
83 | + } else { | ||
84 | + b = b - 1; /* break before same */ | ||
85 | + } | ||
86 | + brk = true; | ||
87 | + } | 49 | + } |
88 | + | 50 | + |
89 | + *retb = b; | 51 | + asm volatile("adr %0, 1f + 1\n\t" |
90 | + return brk; | 52 | + "str %0, %1\n\t" |
53 | + "br %0\n" | ||
54 | + "1:" | ||
55 | + : "=&r"(tmp), "=m"(expected)); | ||
56 | + abort(); | ||
57 | +} | ||
58 | diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c | ||
59 | new file mode 100644 | ||
60 | index XXXXXXX..XXXXXXX | ||
61 | --- /dev/null | ||
62 | +++ b/tests/tcg/arm/pcalign-a32.c | ||
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | +/* Test PC misalignment exception */ | ||
65 | + | ||
66 | +#ifdef __thumb__ | ||
67 | +#error "This test must be compiled for ARM" | ||
68 | +#endif | ||
69 | + | ||
70 | +#include <assert.h> | ||
71 | +#include <signal.h> | ||
72 | +#include <stdlib.h> | ||
73 | +#include <stdio.h> | ||
74 | + | ||
75 | +static void *expected; | ||
76 | + | ||
77 | +static void sigbus(int sig, siginfo_t *info, void *vuc) | ||
78 | +{ | ||
79 | + assert(info->si_code == BUS_ADRALN); | ||
80 | + assert(info->si_addr == expected); | ||
81 | + exit(EXIT_SUCCESS); | ||
91 | +} | 82 | +} |
92 | + | 83 | + |
93 | +/* Compute a zeroing BRK. */ | 84 | +int main() |
94 | +static void compute_brk_z(uint64_t *d, uint64_t *n, uint64_t *g, | ||
95 | + intptr_t oprsz, bool after) | ||
96 | +{ | 85 | +{ |
97 | + bool brk = false; | 86 | + void *tmp; |
98 | + intptr_t i; | ||
99 | + | 87 | + |
100 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) { | 88 | + struct sigaction sa = { |
101 | + uint64_t this_b, this_g = g[i]; | 89 | + .sa_sigaction = sigbus, |
90 | + .sa_flags = SA_SIGINFO | ||
91 | + }; | ||
102 | + | 92 | + |
103 | + brk = compute_brk(&this_b, n[i], this_g, brk, after); | 93 | + if (sigaction(SIGBUS, &sa, NULL) < 0) { |
104 | + d[i] = this_b & this_g; | 94 | + perror("sigaction"); |
105 | + } | 95 | + return EXIT_FAILURE; |
106 | +} | ||
107 | + | ||
108 | +/* Likewise, but also compute flags. */ | ||
109 | +static uint32_t compute_brks_z(uint64_t *d, uint64_t *n, uint64_t *g, | ||
110 | + intptr_t oprsz, bool after) | ||
111 | +{ | ||
112 | + uint32_t flags = PREDTEST_INIT; | ||
113 | + bool brk = false; | ||
114 | + intptr_t i; | ||
115 | + | ||
116 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) { | ||
117 | + uint64_t this_b, this_d, this_g = g[i]; | ||
118 | + | ||
119 | + brk = compute_brk(&this_b, n[i], this_g, brk, after); | ||
120 | + d[i] = this_d = this_b & this_g; | ||
121 | + flags = iter_predtest_fwd(this_d, this_g, flags); | ||
122 | + } | ||
123 | + return flags; | ||
124 | +} | ||
125 | + | ||
126 | +/* Compute a merging BRK. */ | ||
127 | +static void compute_brk_m(uint64_t *d, uint64_t *n, uint64_t *g, | ||
128 | + intptr_t oprsz, bool after) | ||
129 | +{ | ||
130 | + bool brk = false; | ||
131 | + intptr_t i; | ||
132 | + | ||
133 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); ++i) { | ||
134 | + uint64_t this_b, this_g = g[i]; | ||
135 | + | ||
136 | + brk = compute_brk(&this_b, n[i], this_g, brk, after); | ||
137 | + d[i] = (this_b & this_g) | (d[i] & ~this_g); | ||
138 | + } | ||
139 | +} | ||
140 | + | ||
141 | +/* Likewise, but also compute flags. */ | ||
142 | +static uint32_t compute_brks_m(uint64_t *d, uint64_t *n, uint64_t *g, | ||
143 | + intptr_t oprsz, bool after) | ||
144 | +{ | ||
145 | + uint32_t flags = PREDTEST_INIT; | ||
146 | + bool brk = false; | ||
147 | + intptr_t i; | ||
148 | + | ||
149 | + for (i = 0; i < oprsz / 8; ++i) { | ||
150 | + uint64_t this_b, this_d = d[i], this_g = g[i]; | ||
151 | + | ||
152 | + brk = compute_brk(&this_b, n[i], this_g, brk, after); | ||
153 | + d[i] = this_d = (this_b & this_g) | (this_d & ~this_g); | ||
154 | + flags = iter_predtest_fwd(this_d, this_g, flags); | ||
155 | + } | ||
156 | + return flags; | ||
157 | +} | ||
158 | + | ||
159 | +static uint32_t do_zero(ARMPredicateReg *d, intptr_t oprsz) | ||
160 | +{ | ||
161 | + /* It is quicker to zero the whole predicate than loop on OPRSZ. | ||
162 | + * The compiler should turn this into 4 64-bit integer stores. | ||
163 | + */ | ||
164 | + memset(d, 0, sizeof(ARMPredicateReg)); | ||
165 | + return PREDTEST_INIT; | ||
166 | +} | ||
167 | + | ||
168 | +void HELPER(sve_brkpa)(void *vd, void *vn, void *vm, void *vg, | ||
169 | + uint32_t pred_desc) | ||
170 | +{ | ||
171 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
172 | + if (last_active_pred(vn, vg, oprsz)) { | ||
173 | + compute_brk_z(vd, vm, vg, oprsz, true); | ||
174 | + } else { | ||
175 | + do_zero(vd, oprsz); | ||
176 | + } | ||
177 | +} | ||
178 | + | ||
179 | +uint32_t HELPER(sve_brkpas)(void *vd, void *vn, void *vm, void *vg, | ||
180 | + uint32_t pred_desc) | ||
181 | +{ | ||
182 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
183 | + if (last_active_pred(vn, vg, oprsz)) { | ||
184 | + return compute_brks_z(vd, vm, vg, oprsz, true); | ||
185 | + } else { | ||
186 | + return do_zero(vd, oprsz); | ||
187 | + } | ||
188 | +} | ||
189 | + | ||
190 | +void HELPER(sve_brkpb)(void *vd, void *vn, void *vm, void *vg, | ||
191 | + uint32_t pred_desc) | ||
192 | +{ | ||
193 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
194 | + if (last_active_pred(vn, vg, oprsz)) { | ||
195 | + compute_brk_z(vd, vm, vg, oprsz, false); | ||
196 | + } else { | ||
197 | + do_zero(vd, oprsz); | ||
198 | + } | ||
199 | +} | ||
200 | + | ||
201 | +uint32_t HELPER(sve_brkpbs)(void *vd, void *vn, void *vm, void *vg, | ||
202 | + uint32_t pred_desc) | ||
203 | +{ | ||
204 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
205 | + if (last_active_pred(vn, vg, oprsz)) { | ||
206 | + return compute_brks_z(vd, vm, vg, oprsz, false); | ||
207 | + } else { | ||
208 | + return do_zero(vd, oprsz); | ||
209 | + } | ||
210 | +} | ||
211 | + | ||
212 | +void HELPER(sve_brka_z)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
213 | +{ | ||
214 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
215 | + compute_brk_z(vd, vn, vg, oprsz, true); | ||
216 | +} | ||
217 | + | ||
218 | +uint32_t HELPER(sve_brkas_z)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
219 | +{ | ||
220 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
221 | + return compute_brks_z(vd, vn, vg, oprsz, true); | ||
222 | +} | ||
223 | + | ||
224 | +void HELPER(sve_brkb_z)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
225 | +{ | ||
226 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
227 | + compute_brk_z(vd, vn, vg, oprsz, false); | ||
228 | +} | ||
229 | + | ||
230 | +uint32_t HELPER(sve_brkbs_z)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
231 | +{ | ||
232 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
233 | + return compute_brks_z(vd, vn, vg, oprsz, false); | ||
234 | +} | ||
235 | + | ||
236 | +void HELPER(sve_brka_m)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
237 | +{ | ||
238 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
239 | + compute_brk_m(vd, vn, vg, oprsz, true); | ||
240 | +} | ||
241 | + | ||
242 | +uint32_t HELPER(sve_brkas_m)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
243 | +{ | ||
244 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
245 | + return compute_brks_m(vd, vn, vg, oprsz, true); | ||
246 | +} | ||
247 | + | ||
248 | +void HELPER(sve_brkb_m)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
249 | +{ | ||
250 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
251 | + compute_brk_m(vd, vn, vg, oprsz, false); | ||
252 | +} | ||
253 | + | ||
254 | +uint32_t HELPER(sve_brkbs_m)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
255 | +{ | ||
256 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
257 | + return compute_brks_m(vd, vn, vg, oprsz, false); | ||
258 | +} | ||
259 | + | ||
260 | +void HELPER(sve_brkn)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
261 | +{ | ||
262 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
263 | + | ||
264 | + if (!last_active_pred(vn, vg, oprsz)) { | ||
265 | + do_zero(vd, oprsz); | ||
266 | + } | ||
267 | +} | ||
268 | + | ||
269 | +/* As if PredTest(Ones(PL), D, esz). */ | ||
270 | +static uint32_t predtest_ones(ARMPredicateReg *d, intptr_t oprsz, | ||
271 | + uint64_t esz_mask) | ||
272 | +{ | ||
273 | + uint32_t flags = PREDTEST_INIT; | ||
274 | + intptr_t i; | ||
275 | + | ||
276 | + for (i = 0; i < oprsz / 8; i++) { | ||
277 | + flags = iter_predtest_fwd(d->p[i], esz_mask, flags); | ||
278 | + } | ||
279 | + if (oprsz & 7) { | ||
280 | + uint64_t mask = ~(-1ULL << (8 * (oprsz & 7))); | ||
281 | + flags = iter_predtest_fwd(d->p[i], esz_mask & mask, flags); | ||
282 | + } | ||
283 | + return flags; | ||
284 | +} | ||
285 | + | ||
286 | +uint32_t HELPER(sve_brkns)(void *vd, void *vn, void *vg, uint32_t pred_desc) | ||
287 | +{ | ||
288 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
289 | + | ||
290 | + if (last_active_pred(vn, vg, oprsz)) { | ||
291 | + return predtest_ones(vd, oprsz, -1); | ||
292 | + } else { | ||
293 | + return do_zero(vd, oprsz); | ||
294 | + } | ||
295 | +} | ||
296 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
297 | index XXXXXXX..XXXXXXX 100644 | ||
298 | --- a/target/arm/translate-sve.c | ||
299 | +++ b/target/arm/translate-sve.c | ||
300 | @@ -XXX,XX +XXX,XX @@ DO_PPZI(CMPLS, cmpls) | ||
301 | |||
302 | #undef DO_PPZI | ||
303 | |||
304 | +/* | ||
305 | + *** SVE Partition Break Group | ||
306 | + */ | ||
307 | + | ||
308 | +static bool do_brk3(DisasContext *s, arg_rprr_s *a, | ||
309 | + gen_helper_gvec_4 *fn, gen_helper_gvec_flags_4 *fn_s) | ||
310 | +{ | ||
311 | + if (!sve_access_check(s)) { | ||
312 | + return true; | ||
313 | + } | 96 | + } |
314 | + | 97 | + |
315 | + unsigned vsz = pred_full_reg_size(s); | 98 | + asm volatile("adr %0, 1f + 2\n\t" |
99 | + "str %0, %1\n\t" | ||
100 | + "bx %0\n" | ||
101 | + "1:" | ||
102 | + : "=&r"(tmp), "=m"(expected)); | ||
316 | + | 103 | + |
317 | + /* Predicate sizes may be smaller and cannot use simd_desc. */ | 104 | + /* |
318 | + TCGv_ptr d = tcg_temp_new_ptr(); | 105 | + * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns |
319 | + TCGv_ptr n = tcg_temp_new_ptr(); | 106 | + * the address or not. If so, we can legitimately fall through. |
320 | + TCGv_ptr m = tcg_temp_new_ptr(); | 107 | + */ |
321 | + TCGv_ptr g = tcg_temp_new_ptr(); | 108 | + return EXIT_SUCCESS; |
322 | + TCGv_i32 t = tcg_const_i32(vsz - 2); | 109 | +} |
110 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | ||
111 | index XXXXXXX..XXXXXXX 100644 | ||
112 | --- a/tests/tcg/aarch64/Makefile.target | ||
113 | +++ b/tests/tcg/aarch64/Makefile.target | ||
114 | @@ -XXX,XX +XXX,XX @@ VPATH += $(ARM_SRC) | ||
115 | AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 | ||
116 | VPATH += $(AARCH64_SRC) | ||
117 | |||
118 | -# Float-convert Tests | ||
119 | -AARCH64_TESTS=fcvt | ||
120 | +# Base architecture tests | ||
121 | +AARCH64_TESTS=fcvt pcalign-a64 | ||
122 | |||
123 | fcvt: LDFLAGS+=-lm | ||
124 | |||
125 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/tests/tcg/arm/Makefile.target | ||
128 | +++ b/tests/tcg/arm/Makefile.target | ||
129 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
130 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") | ||
131 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) | ||
132 | |||
133 | +# PC alignment test | ||
134 | +ARM_TESTS += pcalign-a32 | ||
135 | +pcalign-a32: CFLAGS+=-marm | ||
323 | + | 136 | + |
324 | + tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | 137 | ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y) |
325 | + tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | 138 | |
326 | + tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm)); | 139 | # Semihosting smoke test for linux-user |
327 | + tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | ||
328 | + | ||
329 | + if (a->s) { | ||
330 | + fn_s(t, d, n, m, g, t); | ||
331 | + do_pred_flags(t); | ||
332 | + } else { | ||
333 | + fn(d, n, m, g, t); | ||
334 | + } | ||
335 | + tcg_temp_free_ptr(d); | ||
336 | + tcg_temp_free_ptr(n); | ||
337 | + tcg_temp_free_ptr(m); | ||
338 | + tcg_temp_free_ptr(g); | ||
339 | + tcg_temp_free_i32(t); | ||
340 | + return true; | ||
341 | +} | ||
342 | + | ||
343 | +static bool do_brk2(DisasContext *s, arg_rpr_s *a, | ||
344 | + gen_helper_gvec_3 *fn, gen_helper_gvec_flags_3 *fn_s) | ||
345 | +{ | ||
346 | + if (!sve_access_check(s)) { | ||
347 | + return true; | ||
348 | + } | ||
349 | + | ||
350 | + unsigned vsz = pred_full_reg_size(s); | ||
351 | + | ||
352 | + /* Predicate sizes may be smaller and cannot use simd_desc. */ | ||
353 | + TCGv_ptr d = tcg_temp_new_ptr(); | ||
354 | + TCGv_ptr n = tcg_temp_new_ptr(); | ||
355 | + TCGv_ptr g = tcg_temp_new_ptr(); | ||
356 | + TCGv_i32 t = tcg_const_i32(vsz - 2); | ||
357 | + | ||
358 | + tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
359 | + tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); | ||
360 | + tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); | ||
361 | + | ||
362 | + if (a->s) { | ||
363 | + fn_s(t, d, n, g, t); | ||
364 | + do_pred_flags(t); | ||
365 | + } else { | ||
366 | + fn(d, n, g, t); | ||
367 | + } | ||
368 | + tcg_temp_free_ptr(d); | ||
369 | + tcg_temp_free_ptr(n); | ||
370 | + tcg_temp_free_ptr(g); | ||
371 | + tcg_temp_free_i32(t); | ||
372 | + return true; | ||
373 | +} | ||
374 | + | ||
375 | +static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a, uint32_t insn) | ||
376 | +{ | ||
377 | + return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas); | ||
378 | +} | ||
379 | + | ||
380 | +static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a, uint32_t insn) | ||
381 | +{ | ||
382 | + return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs); | ||
383 | +} | ||
384 | + | ||
385 | +static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a, uint32_t insn) | ||
386 | +{ | ||
387 | + return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m); | ||
388 | +} | ||
389 | + | ||
390 | +static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a, uint32_t insn) | ||
391 | +{ | ||
392 | + return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m); | ||
393 | +} | ||
394 | + | ||
395 | +static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a, uint32_t insn) | ||
396 | +{ | ||
397 | + return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z); | ||
398 | +} | ||
399 | + | ||
400 | +static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a, uint32_t insn) | ||
401 | +{ | ||
402 | + return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z); | ||
403 | +} | ||
404 | + | ||
405 | +static bool trans_BRKN(DisasContext *s, arg_rpr_s *a, uint32_t insn) | ||
406 | +{ | ||
407 | + return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns); | ||
408 | +} | ||
409 | + | ||
410 | /* | ||
411 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
412 | */ | ||
413 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
414 | index XXXXXXX..XXXXXXX 100644 | ||
415 | --- a/target/arm/sve.decode | ||
416 | +++ b/target/arm/sve.decode | ||
417 | @@ -XXX,XX +XXX,XX @@ | ||
418 | &rri_esz rd rn imm esz | ||
419 | &rrr_esz rd rn rm esz | ||
420 | &rpr_esz rd pg rn esz | ||
421 | +&rpr_s rd pg rn s | ||
422 | &rprr_s rd pg rn rm s | ||
423 | &rprr_esz rd pg rn rm esz | ||
424 | &rprrr_esz rd pg rn rm ra esz | ||
425 | @@ -XXX,XX +XXX,XX @@ | ||
426 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | ||
427 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz | ||
428 | |||
429 | +# Two operand with governing predicate, flags setting | ||
430 | +@pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | ||
431 | + | ||
432 | # Three operand with unused vector element size | ||
433 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | ||
434 | |||
435 | @@ -XXX,XX +XXX,XX @@ PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | ||
436 | # SVE predicate next active | ||
437 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | ||
438 | |||
439 | +### SVE Partition Break Group | ||
440 | + | ||
441 | +# SVE propagate break from previous partition | ||
442 | +BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | ||
443 | +BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | ||
444 | + | ||
445 | +# SVE partition break condition | ||
446 | +BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | ||
447 | +BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | ||
448 | +BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | ||
449 | +BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s | ||
450 | + | ||
451 | +# SVE propagate break to next partition | ||
452 | +BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | ||
453 | + | ||
454 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
455 | |||
456 | # SVE load predicate register | ||
457 | -- | 140 | -- |
458 | 2.17.1 | 141 | 2.25.1 |
459 | 142 | ||
460 | 143 | diff view generated by jsdifflib |
1 | Add an IOMMU index argument to the translate method of | 1 | In the SSE decode function gen_sse(), we combine a byte |
---|---|---|---|
2 | IOMMUs. Since all of our current IOMMU implementations | 2 | 'b' and a value 'b1' which can be [0..3], and switch on them: |
3 | support only a single IOMMU index, this has no effect | 3 | b |= (b1 << 8); |
4 | on the behaviour. | 4 | switch (b) { |
5 | ... | ||
6 | default: | ||
7 | unknown_op: | ||
8 | gen_unknown_opcode(env, s); | ||
9 | return; | ||
10 | } | ||
5 | 11 | ||
12 | In three cases inside this switch, we were then also checking for | ||
13 | "if (b1 >= 2) { goto unknown_op; }". | ||
14 | However, this can never happen, because the 'case' values in each place | ||
15 | are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3) | ||
16 | cases to the default already. | ||
17 | |||
18 | This check was added in commit c045af25a52e9 in 2010; the added code | ||
19 | was unnecessary then as well, and was apparently intended only to | ||
20 | ensure that we never accidentally ended up indexing off the end | ||
21 | of an sse_op_table with only 2 entries as a result of future bugs | ||
22 | in the decode logic. | ||
23 | |||
24 | Change the checks to assert() instead, and make sure they're always | ||
25 | immediately before the array access they are protecting. | ||
26 | |||
27 | Fixes: Coverity CID 1460207 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 28 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 29 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Message-id: 20180604152941.20374-4-peter.maydell@linaro.org | ||
10 | --- | 30 | --- |
11 | include/exec/memory.h | 3 ++- | 31 | target/i386/tcg/translate.c | 12 +++--------- |
12 | exec.c | 11 +++++++++-- | 32 | 1 file changed, 3 insertions(+), 9 deletions(-) |
13 | hw/alpha/typhoon.c | 3 ++- | ||
14 | hw/arm/smmuv3.c | 2 +- | ||
15 | hw/dma/rc4030.c | 2 +- | ||
16 | hw/i386/amd_iommu.c | 2 +- | ||
17 | hw/i386/intel_iommu.c | 2 +- | ||
18 | hw/ppc/spapr_iommu.c | 3 ++- | ||
19 | hw/s390x/s390-pci-bus.c | 2 +- | ||
20 | hw/sparc/sun4m_iommu.c | 3 ++- | ||
21 | hw/sparc64/sun4u_iommu.c | 2 +- | ||
22 | memory.c | 2 +- | ||
23 | 12 files changed, 24 insertions(+), 13 deletions(-) | ||
24 | 33 | ||
25 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 34 | diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c |
26 | index XXXXXXX..XXXXXXX 100644 | 35 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/include/exec/memory.h | 36 | --- a/target/i386/tcg/translate.c |
28 | +++ b/include/exec/memory.h | 37 | +++ b/target/i386/tcg/translate.c |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct IOMMUMemoryRegionClass { | 38 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
30 | * @iommu: the IOMMUMemoryRegion | 39 | case 0x171: /* shift xmm, im */ |
31 | * @hwaddr: address to be translated within the memory region | 40 | case 0x172: |
32 | * @flag: requested access permissions | 41 | case 0x173: |
33 | + * @iommu_idx: IOMMU index for the translation | 42 | - if (b1 >= 2) { |
34 | */ | 43 | - goto unknown_op; |
35 | IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr, | 44 | - } |
36 | - IOMMUAccessFlags flag); | 45 | val = x86_ldub_code(env, s); |
37 | + IOMMUAccessFlags flag, int iommu_idx); | 46 | if (is_xmm) { |
38 | /* Returns minimum supported page size in bytes. | 47 | tcg_gen_movi_tl(s->T0, val); |
39 | * If this method is not provided then the minimum is assumed to | 48 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
40 | * be TARGET_PAGE_SIZE. | 49 | offsetof(CPUX86State, mmx_t0.MMX_L(1))); |
41 | diff --git a/exec.c b/exec.c | 50 | op1_offset = offsetof(CPUX86State,mmx_t0); |
42 | index XXXXXXX..XXXXXXX 100644 | 51 | } |
43 | --- a/exec.c | 52 | + assert(b1 < 2); |
44 | +++ b/exec.c | 53 | sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 + |
45 | @@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm | 54 | (((modrm >> 3)) & 7)][b1]; |
46 | do { | 55 | if (!sse_fn_epp) { |
47 | hwaddr addr = *xlat; | 56 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
48 | IOMMUMemoryRegionClass *imrc = memory_region_get_iommu_class_nocheck(iommu_mr); | 57 | rm = modrm & 7; |
49 | - IOMMUTLBEntry iotlb = imrc->translate(iommu_mr, addr, is_write ? | 58 | reg = ((modrm >> 3) & 7) | REX_R(s); |
50 | - IOMMU_WO : IOMMU_RO); | 59 | mod = (modrm >> 6) & 3; |
51 | + int iommu_idx = 0; | 60 | - if (b1 >= 2) { |
52 | + IOMMUTLBEntry iotlb; | 61 | - goto unknown_op; |
53 | + | 62 | - } |
54 | + if (imrc->attrs_to_index) { | 63 | |
55 | + iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); | 64 | + assert(b1 < 2); |
56 | + } | 65 | sse_fn_epp = sse_op_table6[b].op[b1]; |
57 | + | 66 | if (!sse_fn_epp) { |
58 | + iotlb = imrc->translate(iommu_mr, addr, is_write ? | 67 | goto unknown_op; |
59 | + IOMMU_WO : IOMMU_RO, iommu_idx); | 68 | @@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, |
60 | 69 | rm = modrm & 7; | |
61 | if (!(iotlb.perm & (1 << is_write))) { | 70 | reg = ((modrm >> 3) & 7) | REX_R(s); |
62 | goto unassigned; | 71 | mod = (modrm >> 6) & 3; |
63 | diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c | 72 | - if (b1 >= 2) { |
64 | index XXXXXXX..XXXXXXX 100644 | 73 | - goto unknown_op; |
65 | --- a/hw/alpha/typhoon.c | 74 | - } |
66 | +++ b/hw/alpha/typhoon.c | 75 | |
67 | @@ -XXX,XX +XXX,XX @@ static bool window_translate(TyphoonWindow *win, hwaddr addr, | 76 | + assert(b1 < 2); |
68 | Pchip and generate a machine check interrupt. */ | 77 | sse_fn_eppi = sse_op_table7[b].op[b1]; |
69 | static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, | 78 | if (!sse_fn_eppi) { |
70 | hwaddr addr, | 79 | goto unknown_op; |
71 | - IOMMUAccessFlags flag) | ||
72 | + IOMMUAccessFlags flag, | ||
73 | + int iommu_idx) | ||
74 | { | ||
75 | TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu); | ||
76 | IOMMUTLBEntry ret; | ||
77 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/hw/arm/smmuv3.c | ||
80 | +++ b/hw/arm/smmuv3.c | ||
81 | @@ -XXX,XX +XXX,XX @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg, | ||
82 | } | ||
83 | |||
84 | static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
85 | - IOMMUAccessFlags flag) | ||
86 | + IOMMUAccessFlags flag, int iommu_idx) | ||
87 | { | ||
88 | SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu); | ||
89 | SMMUv3State *s = sdev->smmu; | ||
90 | diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/hw/dma/rc4030.c | ||
93 | +++ b/hw/dma/rc4030.c | ||
94 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps jazzio_ops = { | ||
95 | }; | ||
96 | |||
97 | static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, | ||
98 | - IOMMUAccessFlags flag) | ||
99 | + IOMMUAccessFlags flag, int iommu_idx) | ||
100 | { | ||
101 | rc4030State *s = container_of(iommu, rc4030State, dma_mr); | ||
102 | IOMMUTLBEntry ret = { | ||
103 | diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/hw/i386/amd_iommu.c | ||
106 | +++ b/hw/i386/amd_iommu.c | ||
107 | @@ -XXX,XX +XXX,XX @@ static inline bool amdvi_is_interrupt_addr(hwaddr addr) | ||
108 | } | ||
109 | |||
110 | static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegion *iommu, hwaddr addr, | ||
111 | - IOMMUAccessFlags flag) | ||
112 | + IOMMUAccessFlags flag, int iommu_idx) | ||
113 | { | ||
114 | AMDVIAddressSpace *as = container_of(iommu, AMDVIAddressSpace, iommu); | ||
115 | AMDVIState *s = as->iommu_state; | ||
116 | diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/hw/i386/intel_iommu.c | ||
119 | +++ b/hw/i386/intel_iommu.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static void vtd_mem_write(void *opaque, hwaddr addr, | ||
121 | } | ||
122 | |||
123 | static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr, | ||
124 | - IOMMUAccessFlags flag) | ||
125 | + IOMMUAccessFlags flag, int iommu_idx) | ||
126 | { | ||
127 | VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); | ||
128 | IntelIOMMUState *s = vtd_as->iommu_state; | ||
129 | diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c | ||
130 | index XXXXXXX..XXXXXXX 100644 | ||
131 | --- a/hw/ppc/spapr_iommu.c | ||
132 | +++ b/hw/ppc/spapr_iommu.c | ||
133 | @@ -XXX,XX +XXX,XX @@ static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) | ||
134 | /* Called from RCU critical section */ | ||
135 | static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, | ||
136 | hwaddr addr, | ||
137 | - IOMMUAccessFlags flag) | ||
138 | + IOMMUAccessFlags flag, | ||
139 | + int iommu_idx) | ||
140 | { | ||
141 | sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); | ||
142 | uint64_t tce; | ||
143 | diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c | ||
144 | index XXXXXXX..XXXXXXX 100644 | ||
145 | --- a/hw/s390x/s390-pci-bus.c | ||
146 | +++ b/hw/s390x/s390-pci-bus.c | ||
147 | @@ -XXX,XX +XXX,XX @@ uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr, | ||
148 | } | ||
149 | |||
150 | static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr, | ||
151 | - IOMMUAccessFlags flag) | ||
152 | + IOMMUAccessFlags flag, int iommu_idx) | ||
153 | { | ||
154 | S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr); | ||
155 | S390IOTLBEntry *entry; | ||
156 | diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c | ||
157 | index XXXXXXX..XXXXXXX 100644 | ||
158 | --- a/hw/sparc/sun4m_iommu.c | ||
159 | +++ b/hw/sparc/sun4m_iommu.c | ||
160 | @@ -XXX,XX +XXX,XX @@ static void iommu_bad_addr(IOMMUState *s, hwaddr addr, | ||
161 | /* Called from RCU critical section */ | ||
162 | static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, | ||
163 | hwaddr addr, | ||
164 | - IOMMUAccessFlags flags) | ||
165 | + IOMMUAccessFlags flags, | ||
166 | + int iommu_idx) | ||
167 | { | ||
168 | IOMMUState *is = container_of(iommu, IOMMUState, iommu); | ||
169 | hwaddr page, pa; | ||
170 | diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c | ||
171 | index XXXXXXX..XXXXXXX 100644 | ||
172 | --- a/hw/sparc64/sun4u_iommu.c | ||
173 | +++ b/hw/sparc64/sun4u_iommu.c | ||
174 | @@ -XXX,XX +XXX,XX @@ | ||
175 | /* Called from RCU critical section */ | ||
176 | static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, | ||
177 | hwaddr addr, | ||
178 | - IOMMUAccessFlags flag) | ||
179 | + IOMMUAccessFlags flag, int iommu_idx) | ||
180 | { | ||
181 | IOMMUState *is = container_of(iommu, IOMMUState, iommu); | ||
182 | hwaddr baseaddr, offset; | ||
183 | diff --git a/memory.c b/memory.c | ||
184 | index XXXXXXX..XXXXXXX 100644 | ||
185 | --- a/memory.c | ||
186 | +++ b/memory.c | ||
187 | @@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) | ||
188 | granularity = memory_region_iommu_get_min_page_size(iommu_mr); | ||
189 | |||
190 | for (addr = 0; addr < memory_region_size(mr); addr += granularity) { | ||
191 | - iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE); | ||
192 | + iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx); | ||
193 | if (iotlb.perm != IOMMU_NONE) { | ||
194 | n->notify(n, &iotlb); | ||
195 | } | ||
196 | -- | 80 | -- |
197 | 2.17.1 | 81 | 2.25.1 |
198 | 82 | ||
199 | 83 | diff view generated by jsdifflib |
1 | Convert the mcf5206 device away from using the old_mmio field | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | of MemoryRegionOps. This device is used by the an5206 board. | 2 | other header files, only from .c files (as documented in a comment at |
3 | the start of it). | ||
4 | |||
5 | include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule. | ||
6 | In fact, the include is not required at all, so we can just drop it | ||
7 | from both files. | ||
3 | 8 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Acked-by: Thomas Huth <huth@tuxfamily.org> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20180601141223.26630-3-peter.maydell@linaro.org | 11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
12 | Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org | ||
7 | --- | 13 | --- |
8 | hw/m68k/mcf5206.c | 48 +++++++++++++++++++++++++++++++++++------------ | 14 | include/hw/i386/microvm.h | 1 - |
9 | 1 file changed, 36 insertions(+), 12 deletions(-) | 15 | include/hw/i386/x86.h | 1 - |
16 | 2 files changed, 2 deletions(-) | ||
10 | 17 | ||
11 | diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c | 18 | diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/m68k/mcf5206.c | 20 | --- a/include/hw/i386/microvm.h |
14 | +++ b/hw/m68k/mcf5206.c | 21 | +++ b/include/hw/i386/microvm.h |
15 | @@ -XXX,XX +XXX,XX @@ static void m5206_mbar_writel(void *opaque, hwaddr offset, | 22 | @@ -XXX,XX +XXX,XX @@ |
16 | m5206_mbar_write(s, offset, value, 4); | 23 | #ifndef HW_I386_MICROVM_H |
17 | } | 24 | #define HW_I386_MICROVM_H |
18 | 25 | ||
19 | +static uint64_t m5206_mbar_readfn(void *opaque, hwaddr addr, unsigned size) | 26 | -#include "qemu-common.h" |
20 | +{ | 27 | #include "exec/hwaddr.h" |
21 | + switch (size) { | 28 | #include "qemu/notify.h" |
22 | + case 1: | 29 | |
23 | + return m5206_mbar_readb(opaque, addr); | 30 | diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h |
24 | + case 2: | 31 | index XXXXXXX..XXXXXXX 100644 |
25 | + return m5206_mbar_readw(opaque, addr); | 32 | --- a/include/hw/i386/x86.h |
26 | + case 4: | 33 | +++ b/include/hw/i386/x86.h |
27 | + return m5206_mbar_readl(opaque, addr); | 34 | @@ -XXX,XX +XXX,XX @@ |
28 | + default: | 35 | #ifndef HW_I386_X86_H |
29 | + g_assert_not_reached(); | 36 | #define HW_I386_X86_H |
30 | + } | 37 | |
31 | +} | 38 | -#include "qemu-common.h" |
32 | + | 39 | #include "exec/hwaddr.h" |
33 | +static void m5206_mbar_writefn(void *opaque, hwaddr addr, | 40 | #include "qemu/notify.h" |
34 | + uint64_t value, unsigned size) | ||
35 | +{ | ||
36 | + switch (size) { | ||
37 | + case 1: | ||
38 | + m5206_mbar_writeb(opaque, addr, value); | ||
39 | + break; | ||
40 | + case 2: | ||
41 | + m5206_mbar_writew(opaque, addr, value); | ||
42 | + break; | ||
43 | + case 4: | ||
44 | + m5206_mbar_writel(opaque, addr, value); | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
48 | + } | ||
49 | +} | ||
50 | + | ||
51 | static const MemoryRegionOps m5206_mbar_ops = { | ||
52 | - .old_mmio = { | ||
53 | - .read = { | ||
54 | - m5206_mbar_readb, | ||
55 | - m5206_mbar_readw, | ||
56 | - m5206_mbar_readl, | ||
57 | - }, | ||
58 | - .write = { | ||
59 | - m5206_mbar_writeb, | ||
60 | - m5206_mbar_writew, | ||
61 | - m5206_mbar_writel, | ||
62 | - }, | ||
63 | - }, | ||
64 | + .read = m5206_mbar_readfn, | ||
65 | + .write = m5206_mbar_writefn, | ||
66 | + .valid.min_access_size = 1, | ||
67 | + .valid.max_access_size = 4, | ||
68 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
69 | }; | ||
70 | 41 | ||
71 | -- | 42 | -- |
72 | 2.17.1 | 43 | 2.25.1 |
73 | 44 | ||
74 | 45 | diff view generated by jsdifflib |
1 | If an IOMMU supports mappings that care about the memory | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | transaction attributes, then it no longer has a unique | 2 | other header files, only from .c files (as documented in a comment at |
3 | address -> output mapping, but more than one. We can | 3 | the start of it). |
4 | represent these using an IOMMU index, analogous to TCG's | 4 | |
5 | mmu indexes. | 5 | Move the include to linux-user/hexagon/cpu_loop.c, which needs it for |
6 | the declaration of cpu_exec_step_atomic(). | ||
6 | 7 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
10 | Message-id: 20180604152941.20374-2-peter.maydell@linaro.org | 11 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> |
12 | Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org | ||
11 | --- | 13 | --- |
12 | include/exec/memory.h | 55 +++++++++++++++++++++++++++++++++++++++++++ | 14 | target/hexagon/cpu.h | 1 - |
13 | memory.c | 23 ++++++++++++++++++ | 15 | linux-user/hexagon/cpu_loop.c | 1 + |
14 | 2 files changed, 78 insertions(+) | 16 | 2 files changed, 1 insertion(+), 1 deletion(-) |
15 | 17 | ||
16 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 18 | diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/exec/memory.h | 20 | --- a/target/hexagon/cpu.h |
19 | +++ b/include/exec/memory.h | 21 | +++ b/target/hexagon/cpu.h |
20 | @@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr { | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState; |
21 | * to report whenever mappings are changed, by calling | 23 | |
22 | * memory_region_notify_iommu() (or, if necessary, by calling | 24 | #include "fpu/softfloat-types.h" |
23 | * memory_region_notify_one() for each registered notifier). | 25 | |
24 | + * | 26 | -#include "qemu-common.h" |
25 | + * Conceptually an IOMMU provides a mapping from input address | 27 | #include "exec/cpu-defs.h" |
26 | + * to an output TLB entry. If the IOMMU is aware of memory transaction | 28 | #include "hex_regs.h" |
27 | + * attributes and the output TLB entry depends on the transaction | 29 | #include "mmvec/mmvec.h" |
28 | + * attributes, we represent this using IOMMU indexes. Each index | 30 | diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c |
29 | + * selects a particular translation table that the IOMMU has: | 31 | index XXXXXXX..XXXXXXX 100644 |
30 | + * @attrs_to_index returns the IOMMU index for a set of transaction attributes | 32 | --- a/linux-user/hexagon/cpu_loop.c |
31 | + * @translate takes an input address and an IOMMU index | 33 | +++ b/linux-user/hexagon/cpu_loop.c |
32 | + * and the mapping returned can only depend on the input address and the | 34 | @@ -XXX,XX +XXX,XX @@ |
33 | + * IOMMU index. | ||
34 | + * | ||
35 | + * Most IOMMUs don't care about the transaction attributes and support | ||
36 | + * only a single IOMMU index. A more complex IOMMU might have one index | ||
37 | + * for secure transactions and one for non-secure transactions. | ||
38 | */ | 35 | */ |
39 | typedef struct IOMMUMemoryRegionClass { | 36 | |
40 | /* private */ | 37 | #include "qemu/osdep.h" |
41 | @@ -XXX,XX +XXX,XX @@ typedef struct IOMMUMemoryRegionClass { | 38 | +#include "qemu-common.h" |
42 | */ | 39 | #include "qemu.h" |
43 | int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr, | 40 | #include "user-internals.h" |
44 | void *data); | 41 | #include "cpu_loop-common.h" |
45 | + | ||
46 | + /* Return the IOMMU index to use for a given set of transaction attributes. | ||
47 | + * | ||
48 | + * Optional method: if an IOMMU only supports a single IOMMU index then | ||
49 | + * the default implementation of memory_region_iommu_attrs_to_index() | ||
50 | + * will return 0. | ||
51 | + * | ||
52 | + * The indexes supported by an IOMMU must be contiguous, starting at 0. | ||
53 | + * | ||
54 | + * @iommu: the IOMMUMemoryRegion | ||
55 | + * @attrs: memory transaction attributes | ||
56 | + */ | ||
57 | + int (*attrs_to_index)(IOMMUMemoryRegion *iommu, MemTxAttrs attrs); | ||
58 | + | ||
59 | + /* Return the number of IOMMU indexes this IOMMU supports. | ||
60 | + * | ||
61 | + * Optional method: if this method is not provided, then | ||
62 | + * memory_region_iommu_num_indexes() will return 1, indicating that | ||
63 | + * only a single IOMMU index is supported. | ||
64 | + * | ||
65 | + * @iommu: the IOMMUMemoryRegion | ||
66 | + */ | ||
67 | + int (*num_indexes)(IOMMUMemoryRegion *iommu); | ||
68 | } IOMMUMemoryRegionClass; | ||
69 | |||
70 | typedef struct CoalescedMemoryRange CoalescedMemoryRange; | ||
71 | @@ -XXX,XX +XXX,XX @@ int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr, | ||
72 | enum IOMMUMemoryRegionAttr attr, | ||
73 | void *data); | ||
74 | |||
75 | +/** | ||
76 | + * memory_region_iommu_attrs_to_index: return the IOMMU index to | ||
77 | + * use for translations with the given memory transaction attributes. | ||
78 | + * | ||
79 | + * @iommu_mr: the memory region | ||
80 | + * @attrs: the memory transaction attributes | ||
81 | + */ | ||
82 | +int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr, | ||
83 | + MemTxAttrs attrs); | ||
84 | + | ||
85 | +/** | ||
86 | + * memory_region_iommu_num_indexes: return the total number of IOMMU | ||
87 | + * indexes that this IOMMU supports. | ||
88 | + * | ||
89 | + * @iommu_mr: the memory region | ||
90 | + */ | ||
91 | +int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr); | ||
92 | + | ||
93 | /** | ||
94 | * memory_region_name: get a memory region's name | ||
95 | * | ||
96 | diff --git a/memory.c b/memory.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/memory.c | ||
99 | +++ b/memory.c | ||
100 | @@ -XXX,XX +XXX,XX @@ int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr, | ||
101 | return imrc->get_attr(iommu_mr, attr, data); | ||
102 | } | ||
103 | |||
104 | +int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr, | ||
105 | + MemTxAttrs attrs) | ||
106 | +{ | ||
107 | + IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | ||
108 | + | ||
109 | + if (!imrc->attrs_to_index) { | ||
110 | + return 0; | ||
111 | + } | ||
112 | + | ||
113 | + return imrc->attrs_to_index(iommu_mr, attrs); | ||
114 | +} | ||
115 | + | ||
116 | +int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr) | ||
117 | +{ | ||
118 | + IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); | ||
119 | + | ||
120 | + if (!imrc->num_indexes) { | ||
121 | + return 1; | ||
122 | + } | ||
123 | + | ||
124 | + return imrc->num_indexes(iommu_mr); | ||
125 | +} | ||
126 | + | ||
127 | void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client) | ||
128 | { | ||
129 | uint8_t mask = 1 << client; | ||
130 | -- | 42 | -- |
131 | 2.17.1 | 43 | 2.25.1 |
132 | 44 | ||
133 | 45 | diff view generated by jsdifflib |
1 | Convert the sh7750 device away from using the old_mmio field | 1 | The qemu-common.h header is not supposed to be included from any |
---|---|---|---|
2 | of MemoryRegionOps. This device is used by the sh4 r2d board. | 2 | other header files, only from .c files (as documented in a comment at |
3 | the start of it). | ||
4 | |||
5 | Nothing actually relies on target/rx/cpu.h including it, so we can | ||
6 | just drop the include. | ||
3 | 7 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20180601141223.26630-2-peter.maydell@linaro.org | 11 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> |
12 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> | ||
13 | Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org | ||
7 | --- | 14 | --- |
8 | hw/sh4/sh7750.c | 44 ++++++++++++++++++++++++++++++++++++-------- | 15 | target/rx/cpu.h | 1 - |
9 | 1 file changed, 36 insertions(+), 8 deletions(-) | 16 | 1 file changed, 1 deletion(-) |
10 | 17 | ||
11 | diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c | 18 | diff --git a/target/rx/cpu.h b/target/rx/cpu.h |
12 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/sh4/sh7750.c | 20 | --- a/target/rx/cpu.h |
14 | +++ b/hw/sh4/sh7750.c | 21 | +++ b/target/rx/cpu.h |
15 | @@ -XXX,XX +XXX,XX @@ static void sh7750_mem_writel(void *opaque, hwaddr addr, | 22 | @@ -XXX,XX +XXX,XX @@ |
16 | } | 23 | #define RX_CPU_H |
17 | } | 24 | |
18 | 25 | #include "qemu/bitops.h" | |
19 | +static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size) | 26 | -#include "qemu-common.h" |
20 | +{ | 27 | #include "hw/registerfields.h" |
21 | + switch (size) { | 28 | #include "cpu-qom.h" |
22 | + case 1: | ||
23 | + return sh7750_mem_readb(opaque, addr); | ||
24 | + case 2: | ||
25 | + return sh7750_mem_readw(opaque, addr); | ||
26 | + case 4: | ||
27 | + return sh7750_mem_readl(opaque, addr); | ||
28 | + default: | ||
29 | + g_assert_not_reached(); | ||
30 | + } | ||
31 | +} | ||
32 | + | ||
33 | +static void sh7750_mem_writefn(void *opaque, hwaddr addr, | ||
34 | + uint64_t value, unsigned size) | ||
35 | +{ | ||
36 | + switch (size) { | ||
37 | + case 1: | ||
38 | + sh7750_mem_writeb(opaque, addr, value); | ||
39 | + break; | ||
40 | + case 2: | ||
41 | + sh7750_mem_writew(opaque, addr, value); | ||
42 | + break; | ||
43 | + case 4: | ||
44 | + sh7750_mem_writel(opaque, addr, value); | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
48 | + } | ||
49 | +} | ||
50 | + | ||
51 | static const MemoryRegionOps sh7750_mem_ops = { | ||
52 | - .old_mmio = { | ||
53 | - .read = {sh7750_mem_readb, | ||
54 | - sh7750_mem_readw, | ||
55 | - sh7750_mem_readl }, | ||
56 | - .write = {sh7750_mem_writeb, | ||
57 | - sh7750_mem_writew, | ||
58 | - sh7750_mem_writel }, | ||
59 | - }, | ||
60 | + .read = sh7750_mem_readfn, | ||
61 | + .write = sh7750_mem_writefn, | ||
62 | + .valid.min_access_size = 1, | ||
63 | + .valid.max_access_size = 4, | ||
64 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
65 | }; | ||
66 | 29 | ||
67 | -- | 30 | -- |
68 | 2.17.1 | 31 | 2.25.1 |
69 | 32 | ||
70 | 33 | diff view generated by jsdifflib |
1 | The stellaris board is still using the legacy armv7m_init() function, | 1 | A lot of C files in hw/arm include qemu-common.h when they don't |
---|---|---|---|
2 | which predates conversion of the ARMv7M into a proper QOM container | 2 | need anything from it. Drop the include lines. |
3 | object. Make the board code directly create the ARMv7M object instead. | 3 | |
4 | omap1.c, pxa2xx.c and strongarm.c retain the include because they | ||
5 | use it for the prototype of qemu_get_timedate(). | ||
4 | 6 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | 10 | Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> |
8 | Message-id: 20180601144328.23817-2-peter.maydell@linaro.org | 11 | Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> |
12 | Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org | ||
9 | --- | 13 | --- |
10 | hw/arm/stellaris.c | 12 ++++++++++-- | 14 | hw/arm/boot.c | 1 - |
11 | 1 file changed, 10 insertions(+), 2 deletions(-) | 15 | hw/arm/digic_boards.c | 1 - |
16 | hw/arm/highbank.c | 1 - | ||
17 | hw/arm/npcm7xx_boards.c | 1 - | ||
18 | hw/arm/sbsa-ref.c | 1 - | ||
19 | hw/arm/stm32f405_soc.c | 1 - | ||
20 | hw/arm/vexpress.c | 1 - | ||
21 | hw/arm/virt.c | 1 - | ||
22 | 8 files changed, 8 deletions(-) | ||
12 | 23 | ||
13 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 24 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
14 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/stellaris.c | 26 | --- a/hw/arm/boot.c |
16 | +++ b/hw/arm/stellaris.c | 27 | +++ b/hw/arm/boot.c |
17 | @@ -XXX,XX +XXX,XX @@ | 28 | @@ -XXX,XX +XXX,XX @@ |
18 | #include "qemu/log.h" | 29 | */ |
30 | |||
31 | #include "qemu/osdep.h" | ||
32 | -#include "qemu-common.h" | ||
33 | #include "qemu/datadir.h" | ||
34 | #include "qemu/error-report.h" | ||
35 | #include "qapi/error.h" | ||
36 | diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/hw/arm/digic_boards.c | ||
39 | +++ b/hw/arm/digic_boards.c | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | |||
42 | #include "qemu/osdep.h" | ||
43 | #include "qapi/error.h" | ||
44 | -#include "qemu-common.h" | ||
45 | #include "qemu/datadir.h" | ||
46 | #include "hw/boards.h" | ||
47 | #include "qemu/error-report.h" | ||
48 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/hw/arm/highbank.c | ||
51 | +++ b/hw/arm/highbank.c | ||
52 | @@ -XXX,XX +XXX,XX @@ | ||
53 | */ | ||
54 | |||
55 | #include "qemu/osdep.h" | ||
56 | -#include "qemu-common.h" | ||
57 | #include "qemu/datadir.h" | ||
58 | #include "qapi/error.h" | ||
59 | #include "hw/sysbus.h" | ||
60 | diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/hw/arm/npcm7xx_boards.c | ||
63 | +++ b/hw/arm/npcm7xx_boards.c | ||
64 | @@ -XXX,XX +XXX,XX @@ | ||
65 | #include "hw/qdev-core.h" | ||
66 | #include "hw/qdev-properties.h" | ||
67 | #include "qapi/error.h" | ||
68 | -#include "qemu-common.h" | ||
69 | #include "qemu/datadir.h" | ||
70 | #include "qemu/units.h" | ||
71 | #include "sysemu/blockdev.h" | ||
72 | diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/arm/sbsa-ref.c | ||
75 | +++ b/hw/arm/sbsa-ref.c | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
77 | */ | ||
78 | |||
79 | #include "qemu/osdep.h" | ||
80 | -#include "qemu-common.h" | ||
81 | #include "qemu/datadir.h" | ||
82 | #include "qapi/error.h" | ||
83 | #include "qemu/error-report.h" | ||
84 | diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/hw/arm/stm32f405_soc.c | ||
87 | +++ b/hw/arm/stm32f405_soc.c | ||
88 | @@ -XXX,XX +XXX,XX @@ | ||
89 | |||
90 | #include "qemu/osdep.h" | ||
91 | #include "qapi/error.h" | ||
92 | -#include "qemu-common.h" | ||
19 | #include "exec/address-spaces.h" | 93 | #include "exec/address-spaces.h" |
20 | #include "sysemu/sysemu.h" | 94 | #include "sysemu/sysemu.h" |
21 | +#include "hw/arm/armv7m.h" | 95 | #include "hw/arm/stm32f405_soc.h" |
22 | #include "hw/char/pl011.h" | 96 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c |
23 | #include "hw/misc/unimp.h" | 97 | index XXXXXXX..XXXXXXX 100644 |
98 | --- a/hw/arm/vexpress.c | ||
99 | +++ b/hw/arm/vexpress.c | ||
100 | @@ -XXX,XX +XXX,XX @@ | ||
101 | |||
102 | #include "qemu/osdep.h" | ||
103 | #include "qapi/error.h" | ||
104 | -#include "qemu-common.h" | ||
105 | #include "qemu/datadir.h" | ||
24 | #include "cpu.h" | 106 | #include "cpu.h" |
25 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 107 | #include "hw/sysbus.h" |
26 | &error_fatal); | 108 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
27 | memory_region_add_subregion(system_memory, 0x20000000, sram); | 109 | index XXXXXXX..XXXXXXX 100644 |
28 | 110 | --- a/hw/arm/virt.c | |
29 | - nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES, | 111 | +++ b/hw/arm/virt.c |
30 | - ms->kernel_filename, ms->cpu_type); | 112 | @@ -XXX,XX +XXX,XX @@ |
31 | + nvic = qdev_create(NULL, TYPE_ARMV7M); | 113 | */ |
32 | + qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); | 114 | |
33 | + qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); | 115 | #include "qemu/osdep.h" |
34 | + object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()), | 116 | -#include "qemu-common.h" |
35 | + "memory", &error_abort); | 117 | #include "qemu/datadir.h" |
36 | + /* This will exit with an error if the user passed us a bad cpu_type */ | 118 | #include "qemu/units.h" |
37 | + qdev_init_nofail(nvic); | 119 | #include "qemu/option.h" |
38 | |||
39 | qdev_connect_gpio_out_named(nvic, "SYSRESETREQ", 0, | ||
40 | qemu_allocate_irq(&do_sys_reset, NULL, 0)); | ||
41 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | ||
42 | create_unimplemented_device("analogue-comparator", 0x4003c000, 0x1000); | ||
43 | create_unimplemented_device("hibernation", 0x400fc000, 0x1000); | ||
44 | create_unimplemented_device("flash-control", 0x400fd000, 0x1000); | ||
45 | + | ||
46 | + armv7m_load_kernel(ARM_CPU(first_cpu), ms->kernel_filename, flash_size); | ||
47 | } | ||
48 | |||
49 | /* FIXME: Figure out how to generate these from stellaris_boards. */ | ||
50 | -- | 120 | -- |
51 | 2.17.1 | 121 | 2.25.1 |
52 | 122 | ||
53 | 123 | diff view generated by jsdifflib |
1 | Add support for multiple IOMMU indexes to the IOMMU notifier APIs. | 1 | The calculation of the length of TLB range invalidate operations |
---|---|---|---|
2 | When initializing a notifier with iommu_notifier_init(), the caller | 2 | in tlbi_aa64_range_get_length() is incorrect in two ways: |
3 | must pass the IOMMU index that it is interested in. When a change | 3 | * the NUM field is 5 bits, but we read only 4 bits |
4 | happens, the IOMMU implementation must pass | 4 | * we miscalculate the page_shift value, because of an |
5 | memory_region_notify_iommu() the IOMMU index that has changed and | 5 | off-by-one error: |
6 | that notifiers must be called for. | 6 | TG 0b00 is invalid |
7 | TG 0b01 is 4K granule size == 4096 == 2^12 | ||
8 | TG 0b10 is 16K granule size == 16384 == 2^14 | ||
9 | TG 0b11 is 64K granule size == 65536 == 2^16 | ||
10 | so page_shift should be (TG - 1) * 2 + 12 | ||
7 | 11 | ||
8 | IOMMUs which support only a single index don't need to change. | 12 | Thanks to the bug report submitter Cha HyunSoo for identifying |
9 | Callers which only really support working with IOMMUs with a single | 13 | both these errors. |
10 | index can use the result of passing MEMTXATTRS_UNSPECIFIED to | ||
11 | memory_region_iommu_attrs_to_index(). | ||
12 | 14 | ||
15 | Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE") | ||
16 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 19 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
16 | Message-id: 20180604152941.20374-3-peter.maydell@linaro.org | 20 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
21 | Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org | ||
17 | --- | 22 | --- |
18 | include/exec/memory.h | 7 ++++++- | 23 | target/arm/helper.c | 6 +++--- |
19 | hw/i386/intel_iommu.c | 6 +++--- | 24 | 1 file changed, 3 insertions(+), 3 deletions(-) |
20 | hw/ppc/spapr_iommu.c | 2 +- | ||
21 | hw/s390x/s390-pci-inst.c | 4 ++-- | ||
22 | hw/vfio/common.c | 6 +++++- | ||
23 | hw/virtio/vhost.c | 7 ++++++- | ||
24 | memory.c | 8 +++++++- | ||
25 | 7 files changed, 30 insertions(+), 10 deletions(-) | ||
26 | 25 | ||
27 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 26 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
28 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/include/exec/memory.h | 28 | --- a/target/arm/helper.c |
30 | +++ b/include/exec/memory.h | 29 | +++ b/target/arm/helper.c |
31 | @@ -XXX,XX +XXX,XX @@ struct IOMMUNotifier { | 30 | @@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, |
32 | /* Notify for address space range start <= addr <= end */ | 31 | uint64_t exponent; |
33 | hwaddr start; | 32 | uint64_t length; |
34 | hwaddr end; | 33 | |
35 | + int iommu_idx; | 34 | - num = extract64(value, 39, 4); |
36 | QLIST_ENTRY(IOMMUNotifier) node; | 35 | + num = extract64(value, 39, 5); |
37 | }; | 36 | scale = extract64(value, 44, 2); |
38 | typedef struct IOMMUNotifier IOMMUNotifier; | 37 | page_size_granule = extract64(value, 46, 2); |
39 | 38 | ||
40 | static inline void iommu_notifier_init(IOMMUNotifier *n, IOMMUNotify fn, | 39 | - page_shift = page_size_granule * 2 + 12; |
41 | IOMMUNotifierFlag flags, | 40 | - |
42 | - hwaddr start, hwaddr end) | 41 | if (page_size_granule == 0) { |
43 | + hwaddr start, hwaddr end, | 42 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", |
44 | + int iommu_idx) | 43 | page_size_granule); |
45 | { | 44 | return 0; |
46 | n->notify = fn; | ||
47 | n->notifier_flags = flags; | ||
48 | n->start = start; | ||
49 | n->end = end; | ||
50 | + n->iommu_idx = iommu_idx; | ||
51 | } | ||
52 | |||
53 | /* | ||
54 | @@ -XXX,XX +XXX,XX @@ uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr); | ||
55 | * should be notified with an UNMAP followed by a MAP. | ||
56 | * | ||
57 | * @iommu_mr: the memory region that was changed | ||
58 | + * @iommu_idx: the IOMMU index for the translation table which has changed | ||
59 | * @entry: the new entry in the IOMMU translation table. The entry | ||
60 | * replaces all old entries for the same virtual I/O address range. | ||
61 | * Deleted entries have .@perm == 0. | ||
62 | */ | ||
63 | void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr, | ||
64 | + int iommu_idx, | ||
65 | IOMMUTLBEntry entry); | ||
66 | |||
67 | /** | ||
68 | diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/i386/intel_iommu.c | ||
71 | +++ b/hw/i386/intel_iommu.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, | ||
73 | static int vtd_sync_shadow_page_hook(IOMMUTLBEntry *entry, | ||
74 | void *private) | ||
75 | { | ||
76 | - memory_region_notify_iommu((IOMMUMemoryRegion *)private, *entry); | ||
77 | + memory_region_notify_iommu((IOMMUMemoryRegion *)private, 0, *entry); | ||
78 | return 0; | ||
79 | } | ||
80 | |||
81 | @@ -XXX,XX +XXX,XX @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, | ||
82 | .addr_mask = size - 1, | ||
83 | .perm = IOMMU_NONE, | ||
84 | }; | ||
85 | - memory_region_notify_iommu(&vtd_as->iommu, entry); | ||
86 | + memory_region_notify_iommu(&vtd_as->iommu, 0, entry); | ||
87 | } | ||
88 | } | ||
89 | } | 45 | } |
90 | @@ -XXX,XX +XXX,XX @@ static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s, | 46 | |
91 | entry.iova = addr; | 47 | + page_shift = (page_size_granule - 1) * 2 + 12; |
92 | entry.perm = IOMMU_NONE; | ||
93 | entry.translated_addr = 0; | ||
94 | - memory_region_notify_iommu(&vtd_dev_as->iommu, entry); | ||
95 | + memory_region_notify_iommu(&vtd_dev_as->iommu, 0, entry); | ||
96 | |||
97 | done: | ||
98 | return true; | ||
99 | diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/hw/ppc/spapr_iommu.c | ||
102 | +++ b/hw/ppc/spapr_iommu.c | ||
103 | @@ -XXX,XX +XXX,XX @@ static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, | ||
104 | entry.translated_addr = tce & page_mask; | ||
105 | entry.addr_mask = ~page_mask; | ||
106 | entry.perm = spapr_tce_iommu_access_flags(tce); | ||
107 | - memory_region_notify_iommu(&tcet->iommu, entry); | ||
108 | + memory_region_notify_iommu(&tcet->iommu, 0, entry); | ||
109 | |||
110 | return H_SUCCESS; | ||
111 | } | ||
112 | diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/hw/s390x/s390-pci-inst.c | ||
115 | +++ b/hw/s390x/s390-pci-inst.c | ||
116 | @@ -XXX,XX +XXX,XX @@ static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry) | ||
117 | } | ||
118 | |||
119 | notify.perm = IOMMU_NONE; | ||
120 | - memory_region_notify_iommu(&iommu->iommu_mr, notify); | ||
121 | + memory_region_notify_iommu(&iommu->iommu_mr, 0, notify); | ||
122 | notify.perm = entry->perm; | ||
123 | } | ||
124 | |||
125 | @@ -XXX,XX +XXX,XX @@ static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry) | ||
126 | g_hash_table_replace(iommu->iotlb, &cache->iova, cache); | ||
127 | } | ||
128 | |||
129 | - memory_region_notify_iommu(&iommu->iommu_mr, notify); | ||
130 | + memory_region_notify_iommu(&iommu->iommu_mr, 0, notify); | ||
131 | } | ||
132 | |||
133 | int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) | ||
134 | diff --git a/hw/vfio/common.c b/hw/vfio/common.c | ||
135 | index XXXXXXX..XXXXXXX 100644 | ||
136 | --- a/hw/vfio/common.c | ||
137 | +++ b/hw/vfio/common.c | ||
138 | @@ -XXX,XX +XXX,XX @@ static void vfio_listener_region_add(MemoryListener *listener, | ||
139 | if (memory_region_is_iommu(section->mr)) { | ||
140 | VFIOGuestIOMMU *giommu; | ||
141 | IOMMUMemoryRegion *iommu_mr = IOMMU_MEMORY_REGION(section->mr); | ||
142 | + int iommu_idx; | ||
143 | |||
144 | trace_vfio_listener_region_add_iommu(iova, end); | ||
145 | /* | ||
146 | @@ -XXX,XX +XXX,XX @@ static void vfio_listener_region_add(MemoryListener *listener, | ||
147 | llend = int128_add(int128_make64(section->offset_within_region), | ||
148 | section->size); | ||
149 | llend = int128_sub(llend, int128_one()); | ||
150 | + iommu_idx = memory_region_iommu_attrs_to_index(iommu_mr, | ||
151 | + MEMTXATTRS_UNSPECIFIED); | ||
152 | iommu_notifier_init(&giommu->n, vfio_iommu_map_notify, | ||
153 | IOMMU_NOTIFIER_ALL, | ||
154 | section->offset_within_region, | ||
155 | - int128_get64(llend)); | ||
156 | + int128_get64(llend), | ||
157 | + iommu_idx); | ||
158 | QLIST_INSERT_HEAD(&container->giommu_list, giommu, giommu_next); | ||
159 | |||
160 | memory_region_register_iommu_notifier(section->mr, &giommu->n); | ||
161 | diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c | ||
162 | index XXXXXXX..XXXXXXX 100644 | ||
163 | --- a/hw/virtio/vhost.c | ||
164 | +++ b/hw/virtio/vhost.c | ||
165 | @@ -XXX,XX +XXX,XX @@ static void vhost_iommu_region_add(MemoryListener *listener, | ||
166 | iommu_listener); | ||
167 | struct vhost_iommu *iommu; | ||
168 | Int128 end; | ||
169 | + int iommu_idx; | ||
170 | + IOMMUMemoryRegion *iommu_mr = IOMMU_MEMORY_REGION(section->mr); | ||
171 | |||
172 | if (!memory_region_is_iommu(section->mr)) { | ||
173 | return; | ||
174 | @@ -XXX,XX +XXX,XX @@ static void vhost_iommu_region_add(MemoryListener *listener, | ||
175 | end = int128_add(int128_make64(section->offset_within_region), | ||
176 | section->size); | ||
177 | end = int128_sub(end, int128_one()); | ||
178 | + iommu_idx = memory_region_iommu_attrs_to_index(iommu_mr, | ||
179 | + MEMTXATTRS_UNSPECIFIED); | ||
180 | iommu_notifier_init(&iommu->n, vhost_iommu_unmap_notify, | ||
181 | IOMMU_NOTIFIER_UNMAP, | ||
182 | section->offset_within_region, | ||
183 | - int128_get64(end)); | ||
184 | + int128_get64(end), | ||
185 | + iommu_idx); | ||
186 | iommu->mr = section->mr; | ||
187 | iommu->iommu_offset = section->offset_within_address_space - | ||
188 | section->offset_within_region; | ||
189 | diff --git a/memory.c b/memory.c | ||
190 | index XXXXXXX..XXXXXXX 100644 | ||
191 | --- a/memory.c | ||
192 | +++ b/memory.c | ||
193 | @@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr, | ||
194 | iommu_mr = IOMMU_MEMORY_REGION(mr); | ||
195 | assert(n->notifier_flags != IOMMU_NOTIFIER_NONE); | ||
196 | assert(n->start <= n->end); | ||
197 | + assert(n->iommu_idx >= 0 && | ||
198 | + n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr)); | ||
199 | + | 48 | + |
200 | QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node); | 49 | exponent = (5 * scale) + 1; |
201 | memory_region_update_iommu_notify_flags(iommu_mr); | 50 | length = (num + 1) << (exponent + page_shift); |
202 | } | ||
203 | @@ -XXX,XX +XXX,XX @@ void memory_region_notify_one(IOMMUNotifier *notifier, | ||
204 | } | ||
205 | |||
206 | void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr, | ||
207 | + int iommu_idx, | ||
208 | IOMMUTLBEntry entry) | ||
209 | { | ||
210 | IOMMUNotifier *iommu_notifier; | ||
211 | @@ -XXX,XX +XXX,XX @@ void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr, | ||
212 | assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr))); | ||
213 | |||
214 | IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) { | ||
215 | - memory_region_notify_one(iommu_notifier, &entry); | ||
216 | + if (iommu_notifier->iommu_idx == iommu_idx) { | ||
217 | + memory_region_notify_one(iommu_notifier, &entry); | ||
218 | + } | ||
219 | } | ||
220 | } | ||
221 | 51 | ||
222 | -- | 52 | -- |
223 | 2.17.1 | 53 | 2.25.1 |
224 | 54 | ||
225 | 55 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Patrick Venture <venture@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | The rx_active boolean change to true should always trigger a try_read |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | call that flushes the queue. |
5 | Message-id: 20180613015641.5667-9-richard.henderson@linaro.org | 5 | |
6 | Signed-off-by: Patrick Venture <venture@google.com> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20211203221002.1719306-1-venture@google.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | target/arm/helper-sve.h | 14 +++++++++++++ | 11 | hw/net/npcm7xx_emc.c | 18 ++++++++---------- |
9 | target/arm/sve_helper.c | 41 +++++++++++++++++++++++++++++++------- | 12 | 1 file changed, 8 insertions(+), 10 deletions(-) |
10 | target/arm/translate-sve.c | 38 +++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/sve.decode | 7 +++++++ | ||
12 | 4 files changed, 93 insertions(+), 7 deletions(-) | ||
13 | 13 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 14 | diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 16 | --- a/hw/net/npcm7xx_emc.c |
17 | +++ b/target/arm/helper-sve.h | 17 | +++ b/hw/net/npcm7xx_emc.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 18 | @@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag) |
19 | 19 | emc_set_mista(emc, mista_flag); | |
20 | DEF_HELPER_FLAGS_2(sve_last_active_element, TCG_CALL_NO_RWG, s32, ptr, i32) | ||
21 | |||
22 | +DEF_HELPER_FLAGS_4(sve_revb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
23 | +DEF_HELPER_FLAGS_4(sve_revb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
24 | +DEF_HELPER_FLAGS_4(sve_revb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
25 | + | ||
26 | +DEF_HELPER_FLAGS_4(sve_revh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
28 | + | ||
29 | +DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
30 | + | ||
31 | +DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
33 | +DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
35 | + | ||
36 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
37 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
38 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
39 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/sve_helper.c | ||
42 | +++ b/target/arm/sve_helper.c | ||
43 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t expand_pred_s(uint8_t byte) | ||
44 | return word[byte & 0x11]; | ||
45 | } | 20 | } |
46 | 21 | ||
47 | +/* Swap 16-bit words within a 32-bit word. */ | 22 | +static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc) |
48 | +static inline uint32_t hswap32(uint32_t h) | ||
49 | +{ | 23 | +{ |
50 | + return rol32(h, 16); | 24 | + emc->rx_active = true; |
25 | + qemu_flush_queued_packets(qemu_get_queue(emc->nic)); | ||
51 | +} | 26 | +} |
52 | + | 27 | + |
53 | +/* Swap 16-bit words within a 64-bit word. */ | 28 | static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc, |
54 | +static inline uint64_t hswap64(uint64_t h) | 29 | const NPCM7xxEMCTxDesc *tx_desc, |
55 | +{ | 30 | uint32_t desc_addr) |
56 | + uint64_t m = 0x0000ffff0000ffffull; | 31 | @@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1) |
57 | + h = rol64(h, 32); | 32 | return len; |
58 | + return ((h & m) << 16) | ((h >> 16) & m); | ||
59 | +} | ||
60 | + | ||
61 | +/* Swap 32-bit words within a 64-bit word. */ | ||
62 | +static inline uint64_t wswap64(uint64_t h) | ||
63 | +{ | ||
64 | + return rol64(h, 32); | ||
65 | +} | ||
66 | + | ||
67 | #define LOGICAL_PPPP(NAME, FUNC) \ | ||
68 | void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ | ||
69 | { \ | ||
70 | @@ -XXX,XX +XXX,XX @@ DO_ZPZ(sve_neg_h, uint16_t, H1_2, DO_NEG) | ||
71 | DO_ZPZ(sve_neg_s, uint32_t, H1_4, DO_NEG) | ||
72 | DO_ZPZ_D(sve_neg_d, uint64_t, DO_NEG) | ||
73 | |||
74 | +DO_ZPZ(sve_revb_h, uint16_t, H1_2, bswap16) | ||
75 | +DO_ZPZ(sve_revb_s, uint32_t, H1_4, bswap32) | ||
76 | +DO_ZPZ_D(sve_revb_d, uint64_t, bswap64) | ||
77 | + | ||
78 | +DO_ZPZ(sve_revh_s, uint32_t, H1_4, hswap32) | ||
79 | +DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) | ||
80 | + | ||
81 | +DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) | ||
82 | + | ||
83 | +DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) | ||
84 | +DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) | ||
85 | +DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) | ||
86 | +DO_ZPZ_D(sve_rbit_d, uint64_t, revbit64) | ||
87 | + | ||
88 | /* Three-operand expander, unpredicated, in which the third operand is "wide". | ||
89 | */ | ||
90 | #define DO_ZZW(NAME, TYPE, TYPEW, H, OP) \ | ||
91 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_rev_b)(void *vd, void *vn, uint32_t desc) | ||
92 | } | ||
93 | } | 33 | } |
94 | 34 | ||
95 | -static inline uint64_t hswap64(uint64_t h) | 35 | -static void emc_try_receive_next_packet(NPCM7xxEMCState *emc) |
96 | -{ | 36 | -{ |
97 | - uint64_t m = 0x0000ffff0000ffffull; | 37 | - if (emc_can_receive(qemu_get_queue(emc->nic))) { |
98 | - h = rol64(h, 32); | 38 | - qemu_flush_queued_packets(qemu_get_queue(emc->nic)); |
99 | - return ((h & m) << 16) | ((h >> 16) & m); | 39 | - } |
100 | -} | 40 | -} |
101 | - | 41 | - |
102 | void HELPER(sve_rev_h)(void *vd, void *vn, uint32_t desc) | 42 | static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size) |
103 | { | 43 | { |
104 | intptr_t i, j, opr_sz = simd_oprsz(desc); | 44 | NPCM7xxEMCState *emc = opaque; |
105 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 45 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, |
106 | index XXXXXXX..XXXXXXX 100644 | 46 | emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA; |
107 | --- a/target/arm/translate-sve.c | 47 | } |
108 | +++ b/target/arm/translate-sve.c | 48 | if (value & REG_MCMDR_RXON) { |
109 | @@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 49 | - emc->rx_active = true; |
110 | return true; | 50 | + emc_enable_rx_and_flush(emc); |
111 | } | 51 | } else { |
112 | 52 | emc_halt_rx(emc, 0); | |
113 | +static bool trans_REVB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 53 | } |
114 | +{ | 54 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset, |
115 | + static gen_helper_gvec_3 * const fns[4] = { | 55 | break; |
116 | + NULL, | 56 | case REG_RSDR: |
117 | + gen_helper_sve_revb_h, | 57 | if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) { |
118 | + gen_helper_sve_revb_s, | 58 | - emc->rx_active = true; |
119 | + gen_helper_sve_revb_d, | 59 | - emc_try_receive_next_packet(emc); |
120 | + }; | 60 | + emc_enable_rx_and_flush(emc); |
121 | + return do_zpz_ool(s, a, fns[a->esz]); | 61 | } |
122 | +} | 62 | break; |
123 | + | 63 | case REG_MIIDA: |
124 | +static bool trans_REVH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
125 | +{ | ||
126 | + static gen_helper_gvec_3 * const fns[4] = { | ||
127 | + NULL, | ||
128 | + NULL, | ||
129 | + gen_helper_sve_revh_s, | ||
130 | + gen_helper_sve_revh_d, | ||
131 | + }; | ||
132 | + return do_zpz_ool(s, a, fns[a->esz]); | ||
133 | +} | ||
134 | + | ||
135 | +static bool trans_REVW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
136 | +{ | ||
137 | + return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL); | ||
138 | +} | ||
139 | + | ||
140 | +static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
141 | +{ | ||
142 | + static gen_helper_gvec_3 * const fns[4] = { | ||
143 | + gen_helper_sve_rbit_b, | ||
144 | + gen_helper_sve_rbit_h, | ||
145 | + gen_helper_sve_rbit_s, | ||
146 | + gen_helper_sve_rbit_d, | ||
147 | + }; | ||
148 | + return do_zpz_ool(s, a, fns[a->esz]); | ||
149 | +} | ||
150 | + | ||
151 | /* | ||
152 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
153 | */ | ||
154 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
155 | index XXXXXXX..XXXXXXX 100644 | ||
156 | --- a/target/arm/sve.decode | ||
157 | +++ b/target/arm/sve.decode | ||
158 | @@ -XXX,XX +XXX,XX @@ CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | ||
159 | # SVE copy element from general register to vector (predicated) | ||
160 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | ||
161 | |||
162 | +# SVE reverse within elements | ||
163 | +# Note esz >= operation size | ||
164 | +REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | ||
165 | +REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | ||
166 | +REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | ||
167 | +RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | ||
168 | + | ||
169 | ### SVE Predicate Logical Operations Group | ||
170 | |||
171 | # SVE predicate logical operations | ||
172 | -- | 64 | -- |
173 | 2.17.1 | 65 | 2.25.1 |
174 | 66 | ||
175 | 67 | diff view generated by jsdifflib |
1 | There's a common pattern in QEMU where a function needs to perform | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | a data load or store of an N byte integer in a particular endianness. | ||
3 | At the moment this is handled by doing a switch() on the size and | ||
4 | calling the appropriate ld*_p or st*_p function for each size. | ||
5 | 2 | ||
6 | Provide a new family of functions ldn_*_p() and stn_*_p() which | 3 | When a virtio-iommu is instantiated, describe it using the ACPI VIOT |
7 | take the size as an argument and do the switch() themselves. | 4 | table. |
8 | 5 | ||
6 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
8 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
9 | Message-id: 20211210170415.583179-2-jean-philippe@linaro.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180611171007.4165-2-peter.maydell@linaro.org | ||
13 | --- | 11 | --- |
14 | include/exec/cpu-all.h | 4 +++ | 12 | hw/arm/virt-acpi-build.c | 7 +++++++ |
15 | include/qemu/bswap.h | 52 +++++++++++++++++++++++++++++++++++++ | 13 | hw/arm/Kconfig | 1 + |
16 | docs/devel/loads-stores.rst | 15 +++++++++++ | 14 | 2 files changed, 8 insertions(+) |
17 | 3 files changed, 71 insertions(+) | ||
18 | 15 | ||
19 | diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h | 16 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c |
20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/exec/cpu-all.h | 18 | --- a/hw/arm/virt-acpi-build.c |
22 | +++ b/include/exec/cpu-all.h | 19 | +++ b/hw/arm/virt-acpi-build.c |
23 | @@ -XXX,XX +XXX,XX @@ static inline void tswap64s(uint64_t *s) | 20 | @@ -XXX,XX +XXX,XX @@ |
24 | #define stq_p(p, v) stq_be_p(p, v) | 21 | #include "kvm_arm.h" |
25 | #define stfl_p(p, v) stfl_be_p(p, v) | 22 | #include "migration/vmstate.h" |
26 | #define stfq_p(p, v) stfq_be_p(p, v) | 23 | #include "hw/acpi/ghes.h" |
27 | +#define ldn_p(p, sz) ldn_be_p(p, sz) | 24 | +#include "hw/acpi/viot.h" |
28 | +#define stn_p(p, sz, v) stn_be_p(p, sz, v) | 25 | |
29 | #else | 26 | #define ARM_SPI_BASE 32 |
30 | #define lduw_p(p) lduw_le_p(p) | 27 | |
31 | #define ldsw_p(p) ldsw_le_p(p) | 28 | @@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) |
32 | @@ -XXX,XX +XXX,XX @@ static inline void tswap64s(uint64_t *s) | 29 | } |
33 | #define stq_p(p, v) stq_le_p(p, v) | ||
34 | #define stfl_p(p, v) stfl_le_p(p, v) | ||
35 | #define stfq_p(p, v) stfq_le_p(p, v) | ||
36 | +#define ldn_p(p, sz) ldn_le_p(p, sz) | ||
37 | +#define stn_p(p, sz, v) stn_le_p(p, sz, v) | ||
38 | #endif | 30 | #endif |
39 | 31 | ||
40 | /* MMU memory access macros */ | 32 | + if (vms->iommu == VIRT_IOMMU_VIRTIO) { |
41 | diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h | 33 | + acpi_add_table(table_offsets, tables_blob); |
42 | index XXXXXXX..XXXXXXX 100644 | 34 | + build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf, |
43 | --- a/include/qemu/bswap.h | 35 | + vms->oem_id, vms->oem_table_id); |
44 | +++ b/include/qemu/bswap.h | ||
45 | @@ -XXX,XX +XXX,XX @@ typedef union { | ||
46 | * For accessors that take a guest address rather than a | ||
47 | * host address, see the cpu_{ld,st}_* accessors defined in | ||
48 | * cpu_ldst.h. | ||
49 | + * | ||
50 | + * For cases where the size to be used is not fixed at compile time, | ||
51 | + * there are | ||
52 | + * stn{endian}_p(ptr, sz, val) | ||
53 | + * which stores @val to @ptr as an @endian-order number @sz bytes in size | ||
54 | + * and | ||
55 | + * ldn{endian}_p(ptr, sz) | ||
56 | + * which loads @sz bytes from @ptr as an unsigned @endian-order number | ||
57 | + * and returns it in a uint64_t. | ||
58 | */ | ||
59 | |||
60 | static inline int ldub_p(const void *ptr) | ||
61 | @@ -XXX,XX +XXX,XX @@ static inline unsigned long leul_to_cpu(unsigned long v) | ||
62 | #endif | ||
63 | } | ||
64 | |||
65 | +/* Store v to p as a sz byte value in host order */ | ||
66 | +#define DO_STN_LDN_P(END) \ | ||
67 | + static inline void stn_## END ## _p(void *ptr, int sz, uint64_t v) \ | ||
68 | + { \ | ||
69 | + switch (sz) { \ | ||
70 | + case 1: \ | ||
71 | + stb_p(ptr, v); \ | ||
72 | + break; \ | ||
73 | + case 2: \ | ||
74 | + stw_ ## END ## _p(ptr, v); \ | ||
75 | + break; \ | ||
76 | + case 4: \ | ||
77 | + stl_ ## END ## _p(ptr, v); \ | ||
78 | + break; \ | ||
79 | + case 8: \ | ||
80 | + stq_ ## END ## _p(ptr, v); \ | ||
81 | + break; \ | ||
82 | + default: \ | ||
83 | + g_assert_not_reached(); \ | ||
84 | + } \ | ||
85 | + } \ | ||
86 | + static inline uint64_t ldn_## END ## _p(const void *ptr, int sz) \ | ||
87 | + { \ | ||
88 | + switch (sz) { \ | ||
89 | + case 1: \ | ||
90 | + return ldub_p(ptr); \ | ||
91 | + case 2: \ | ||
92 | + return lduw_ ## END ## _p(ptr); \ | ||
93 | + case 4: \ | ||
94 | + return (uint32_t)ldl_ ## END ## _p(ptr); \ | ||
95 | + case 8: \ | ||
96 | + return ldq_ ## END ## _p(ptr); \ | ||
97 | + default: \ | ||
98 | + g_assert_not_reached(); \ | ||
99 | + } \ | ||
100 | + } | 36 | + } |
101 | + | 37 | + |
102 | +DO_STN_LDN_P(he) | 38 | /* XSDT is pointed to by RSDP */ |
103 | +DO_STN_LDN_P(le) | 39 | xsdt = tables_blob->len; |
104 | +DO_STN_LDN_P(be) | 40 | build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id, |
105 | + | 41 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
106 | +#undef DO_STN_LDN_P | ||
107 | + | ||
108 | #undef le_bswap | ||
109 | #undef be_bswap | ||
110 | #undef le_bswaps | ||
111 | diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst | ||
112 | index XXXXXXX..XXXXXXX 100644 | 42 | index XXXXXXX..XXXXXXX 100644 |
113 | --- a/docs/devel/loads-stores.rst | 43 | --- a/hw/arm/Kconfig |
114 | +++ b/docs/devel/loads-stores.rst | 44 | +++ b/hw/arm/Kconfig |
115 | @@ -XXX,XX +XXX,XX @@ The ``_{endian}`` infix is omitted for target-endian accesses. | 45 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT |
116 | The target endian accessors are only available to source | 46 | select DIMM |
117 | files which are built per-target. | 47 | select ACPI_HW_REDUCED |
118 | 48 | select ACPI_APEI | |
119 | +There are also functions which take the size as an argument: | 49 | + select ACPI_VIOT |
120 | + | 50 | |
121 | +load: ``ldn{endian}_p(ptr, sz)`` | 51 | config CHEETAH |
122 | + | 52 | bool |
123 | +which performs an unsigned load of ``sz`` bytes from ``ptr`` | ||
124 | +as an ``{endian}`` order value and returns it in a uint64_t. | ||
125 | + | ||
126 | +store: ``stn{endian}_p(ptr, sz, val)`` | ||
127 | + | ||
128 | +which stores ``val`` to ``ptr`` as an ``{endian}`` order value | ||
129 | +of size ``sz`` bytes. | ||
130 | + | ||
131 | + | ||
132 | Regexes for git grep | ||
133 | - ``\<ldf\?[us]\?[bwlq]\(_[hbl]e\)\?_p\>`` | ||
134 | - ``\<stf\?[bwlq]\(_[hbl]e\)\?_p\>`` | ||
135 | + - ``\<ldn_\([hbl]e\)?_p\>`` | ||
136 | + - ``\<stn_\([hbl]e\)?_p\>`` | ||
137 | |||
138 | ``cpu_{ld,st}_*`` | ||
139 | ~~~~~~~~~~~~~~~~~ | ||
140 | -- | 53 | -- |
141 | 2.17.1 | 54 | 2.25.1 |
142 | 55 | ||
143 | 56 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | virtio-iommu is now supported with ACPI VIOT as well as device tree. |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Remove the restriction that prevents from instantiating a virtio-iommu |
5 | Message-id: 20180613015641.5667-17-richard.henderson@linaro.org | 5 | device under ACPI. |
6 | |||
7 | Acked-by: Igor Mammedov <imammedo@redhat.com> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
10 | Message-id: 20211210170415.583179-3-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | target/arm/translate-sve.c | 37 +++++++++++++++++++++++++++++++++++++ | 13 | hw/arm/virt.c | 10 ++-------- |
9 | target/arm/sve.decode | 8 ++++++++ | 14 | hw/virtio/virtio-iommu-pci.c | 12 ++---------- |
10 | 2 files changed, 45 insertions(+) | 15 | 2 files changed, 4 insertions(+), 18 deletions(-) |
11 | 16 | ||
12 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/translate-sve.c | 19 | --- a/hw/arm/virt.c |
15 | +++ b/target/arm/translate-sve.c | 20 | +++ b/hw/arm/virt.c |
16 | @@ -XXX,XX +XXX,XX @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) | 21 | @@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, |
17 | return true; | 22 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
23 | |||
24 | if (device_is_dynamic_sysbus(mc, dev) || | ||
25 | - (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) { | ||
26 | + object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || | ||
27 | + object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | ||
28 | return HOTPLUG_HANDLER(machine); | ||
29 | } | ||
30 | - if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) { | ||
31 | - VirtMachineState *vms = VIRT_MACHINE(machine); | ||
32 | - | ||
33 | - if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) { | ||
34 | - return HOTPLUG_HANDLER(machine); | ||
35 | - } | ||
36 | - } | ||
37 | return NULL; | ||
18 | } | 38 | } |
19 | 39 | ||
20 | +/* | 40 | diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c |
21 | + *** SVE Integer Wide Immediate - Unpredicated Group | ||
22 | + */ | ||
23 | + | ||
24 | +static bool trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn) | ||
25 | +{ | ||
26 | + if (a->esz == 0) { | ||
27 | + return false; | ||
28 | + } | ||
29 | + if (sve_access_check(s)) { | ||
30 | + unsigned vsz = vec_full_reg_size(s); | ||
31 | + int dofs = vec_full_reg_offset(s, a->rd); | ||
32 | + uint64_t imm; | ||
33 | + | ||
34 | + /* Decode the VFP immediate. */ | ||
35 | + imm = vfp_expand_imm(a->esz, a->imm); | ||
36 | + imm = dup_const(a->esz, imm); | ||
37 | + | ||
38 | + tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm); | ||
39 | + } | ||
40 | + return true; | ||
41 | +} | ||
42 | + | ||
43 | +static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn) | ||
44 | +{ | ||
45 | + if (a->esz == 0 && extract32(insn, 13, 1)) { | ||
46 | + return false; | ||
47 | + } | ||
48 | + if (sve_access_check(s)) { | ||
49 | + unsigned vsz = vec_full_reg_size(s); | ||
50 | + int dofs = vec_full_reg_offset(s, a->rd); | ||
51 | + | ||
52 | + tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm)); | ||
53 | + } | ||
54 | + return true; | ||
55 | +} | ||
56 | + | ||
57 | /* | ||
58 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
59 | */ | ||
60 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
61 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
62 | --- a/target/arm/sve.decode | 42 | --- a/hw/virtio/virtio-iommu-pci.c |
63 | +++ b/target/arm/sve.decode | 43 | +++ b/hw/virtio/virtio-iommu-pci.c |
64 | @@ -XXX,XX +XXX,XX @@ CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | 44 | @@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) |
65 | # SVE integer compare scalar count and limit | 45 | VirtIOIOMMU *s = VIRTIO_IOMMU(vdev); |
66 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 | 46 | |
67 | 47 | if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) { | |
68 | +### SVE Integer Wide Immediate - Unpredicated Group | 48 | - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); |
69 | + | 49 | - |
70 | +# SVE broadcast floating-point immediate (unpredicated) | 50 | - error_setg(errp, |
71 | +FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | 51 | - "%s machine fails to create iommu-map device tree bindings", |
72 | + | 52 | - mc->name); |
73 | +# SVE broadcast integer immediate (unpredicated) | 53 | - error_append_hint(errp, |
74 | +DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | 54 | - "Check your machine implements a hotplug handler " |
75 | + | 55 | - "for the virtio-iommu-pci device\n"); |
76 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | 56 | - error_append_hint(errp, "Check the guest is booted without FW or with " |
77 | 57 | - "-no-acpi\n"); | |
78 | # SVE load predicate register | 58 | + error_setg(errp, "Check your machine implements a hotplug handler " |
59 | + "for the virtio-iommu-pci device"); | ||
60 | return; | ||
61 | } | ||
62 | for (int i = 0; i < s->nb_reserved_regions; i++) { | ||
79 | -- | 63 | -- |
80 | 2.17.1 | 64 | 2.25.1 |
81 | 65 | ||
82 | 66 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | We do not support instantiating multiple IOMMUs. Before adding a |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | virtio-iommu, check that no other IOMMU is present. This will detect |
5 | Message-id: 20180613015641.5667-4-richard.henderson@linaro.org | 5 | both "iommu=smmuv3" machine parameter and another virtio-iommu instance. |
6 | |||
7 | Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings") | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20211210170415.583179-4-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/helper-sve.h | 6 + | 14 | hw/arm/virt.c | 5 +++++ |
9 | target/arm/sve_helper.c | 290 +++++++++++++++++++++++++++++++++++++ | 15 | 1 file changed, 5 insertions(+) |
10 | target/arm/translate-sve.c | 120 +++++++++++++++ | ||
11 | target/arm/sve.decode | 18 +++ | ||
12 | 4 files changed, 434 insertions(+) | ||
13 | 16 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 19 | --- a/hw/arm/virt.c |
17 | +++ b/target/arm/helper-sve.h | 20 | +++ b/hw/arm/virt.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sve_uunpk_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
19 | DEF_HELPER_FLAGS_3(sve_uunpk_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 22 | hwaddr db_start = 0, db_end = 0; |
20 | DEF_HELPER_FLAGS_3(sve_uunpk_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 23 | char *resv_prop_str; |
21 | 24 | ||
22 | +DEF_HELPER_FLAGS_4(sve_zip_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 25 | + if (vms->iommu != VIRT_IOMMU_NONE) { |
23 | +DEF_HELPER_FLAGS_4(sve_uzp_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 26 | + error_setg(errp, "virt machine does not support multiple IOMMUs"); |
24 | +DEF_HELPER_FLAGS_4(sve_trn_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 27 | + return; |
25 | +DEF_HELPER_FLAGS_3(sve_rev_p, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
26 | +DEF_HELPER_FLAGS_3(sve_punpk_p, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | ||
27 | + | ||
28 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
29 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
30 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
31 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/sve_helper.c | ||
34 | +++ b/target/arm/sve_helper.c | ||
35 | @@ -XXX,XX +XXX,XX @@ DO_UNPK(sve_uunpk_s, uint32_t, uint16_t, H4, H2) | ||
36 | DO_UNPK(sve_uunpk_d, uint64_t, uint32_t, , H4) | ||
37 | |||
38 | #undef DO_UNPK | ||
39 | + | ||
40 | +/* Mask of bits included in the even numbered predicates of width esz. | ||
41 | + * We also use this for expand_bits/compress_bits, and so extend the | ||
42 | + * same pattern out to 16-bit units. | ||
43 | + */ | ||
44 | +static const uint64_t even_bit_esz_masks[5] = { | ||
45 | + 0x5555555555555555ull, | ||
46 | + 0x3333333333333333ull, | ||
47 | + 0x0f0f0f0f0f0f0f0full, | ||
48 | + 0x00ff00ff00ff00ffull, | ||
49 | + 0x0000ffff0000ffffull, | ||
50 | +}; | ||
51 | + | ||
52 | +/* Zero-extend units of 2**N bits to units of 2**(N+1) bits. | ||
53 | + * For N==0, this corresponds to the operation that in qemu/bitops.h | ||
54 | + * we call half_shuffle64; this algorithm is from Hacker's Delight, | ||
55 | + * section 7-2 Shuffling Bits. | ||
56 | + */ | ||
57 | +static uint64_t expand_bits(uint64_t x, int n) | ||
58 | +{ | ||
59 | + int i; | ||
60 | + | ||
61 | + x &= 0xffffffffu; | ||
62 | + for (i = 4; i >= n; i--) { | ||
63 | + int sh = 1 << i; | ||
64 | + x = ((x << sh) | x) & even_bit_esz_masks[i]; | ||
65 | + } | ||
66 | + return x; | ||
67 | +} | ||
68 | + | ||
69 | +/* Compress units of 2**(N+1) bits to units of 2**N bits. | ||
70 | + * For N==0, this corresponds to the operation that in qemu/bitops.h | ||
71 | + * we call half_unshuffle64; this algorithm is from Hacker's Delight, | ||
72 | + * section 7-2 Shuffling Bits, where it is called an inverse half shuffle. | ||
73 | + */ | ||
74 | +static uint64_t compress_bits(uint64_t x, int n) | ||
75 | +{ | ||
76 | + int i; | ||
77 | + | ||
78 | + for (i = n; i <= 4; i++) { | ||
79 | + int sh = 1 << i; | ||
80 | + x &= even_bit_esz_masks[i]; | ||
81 | + x = (x >> sh) | x; | ||
82 | + } | ||
83 | + return x & 0xffffffffu; | ||
84 | +} | ||
85 | + | ||
86 | +void HELPER(sve_zip_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) | ||
87 | +{ | ||
88 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
89 | + int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | ||
90 | + intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); | ||
91 | + uint64_t *d = vd; | ||
92 | + intptr_t i; | ||
93 | + | ||
94 | + if (oprsz <= 8) { | ||
95 | + uint64_t nn = *(uint64_t *)vn; | ||
96 | + uint64_t mm = *(uint64_t *)vm; | ||
97 | + int half = 4 * oprsz; | ||
98 | + | ||
99 | + nn = extract64(nn, high * half, half); | ||
100 | + mm = extract64(mm, high * half, half); | ||
101 | + nn = expand_bits(nn, esz); | ||
102 | + mm = expand_bits(mm, esz); | ||
103 | + d[0] = nn + (mm << (1 << esz)); | ||
104 | + } else { | ||
105 | + ARMPredicateReg tmp_n, tmp_m; | ||
106 | + | ||
107 | + /* We produce output faster than we consume input. | ||
108 | + Therefore we must be mindful of possible overlap. */ | ||
109 | + if ((vn - vd) < (uintptr_t)oprsz) { | ||
110 | + vn = memcpy(&tmp_n, vn, oprsz); | ||
111 | + } | ||
112 | + if ((vm - vd) < (uintptr_t)oprsz) { | ||
113 | + vm = memcpy(&tmp_m, vm, oprsz); | ||
114 | + } | ||
115 | + if (high) { | ||
116 | + high = oprsz >> 1; | ||
117 | + } | 28 | + } |
118 | + | 29 | + |
119 | + if ((high & 3) == 0) { | 30 | switch (vms->msi_controller) { |
120 | + uint32_t *n = vn, *m = vm; | 31 | case VIRT_MSI_CTRL_NONE: |
121 | + high >>= 2; | 32 | return; |
122 | + | ||
123 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); i++) { | ||
124 | + uint64_t nn = n[H4(high + i)]; | ||
125 | + uint64_t mm = m[H4(high + i)]; | ||
126 | + | ||
127 | + nn = expand_bits(nn, esz); | ||
128 | + mm = expand_bits(mm, esz); | ||
129 | + d[i] = nn + (mm << (1 << esz)); | ||
130 | + } | ||
131 | + } else { | ||
132 | + uint8_t *n = vn, *m = vm; | ||
133 | + uint16_t *d16 = vd; | ||
134 | + | ||
135 | + for (i = 0; i < oprsz / 2; i++) { | ||
136 | + uint16_t nn = n[H1(high + i)]; | ||
137 | + uint16_t mm = m[H1(high + i)]; | ||
138 | + | ||
139 | + nn = expand_bits(nn, esz); | ||
140 | + mm = expand_bits(mm, esz); | ||
141 | + d16[H2(i)] = nn + (mm << (1 << esz)); | ||
142 | + } | ||
143 | + } | ||
144 | + } | ||
145 | +} | ||
146 | + | ||
147 | +void HELPER(sve_uzp_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) | ||
148 | +{ | ||
149 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
150 | + int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | ||
151 | + int odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1) << esz; | ||
152 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
153 | + uint64_t l, h; | ||
154 | + intptr_t i; | ||
155 | + | ||
156 | + if (oprsz <= 8) { | ||
157 | + l = compress_bits(n[0] >> odd, esz); | ||
158 | + h = compress_bits(m[0] >> odd, esz); | ||
159 | + d[0] = extract64(l + (h << (4 * oprsz)), 0, 8 * oprsz); | ||
160 | + } else { | ||
161 | + ARMPredicateReg tmp_m; | ||
162 | + intptr_t oprsz_16 = oprsz / 16; | ||
163 | + | ||
164 | + if ((vm - vd) < (uintptr_t)oprsz) { | ||
165 | + m = memcpy(&tmp_m, vm, oprsz); | ||
166 | + } | ||
167 | + | ||
168 | + for (i = 0; i < oprsz_16; i++) { | ||
169 | + l = n[2 * i + 0]; | ||
170 | + h = n[2 * i + 1]; | ||
171 | + l = compress_bits(l >> odd, esz); | ||
172 | + h = compress_bits(h >> odd, esz); | ||
173 | + d[i] = l + (h << 32); | ||
174 | + } | ||
175 | + | ||
176 | + /* For VL which is not a power of 2, the results from M do not | ||
177 | + align nicely with the uint64_t for D. Put the aligned results | ||
178 | + from M into TMP_M and then copy it into place afterward. */ | ||
179 | + if (oprsz & 15) { | ||
180 | + d[i] = compress_bits(n[2 * i] >> odd, esz); | ||
181 | + | ||
182 | + for (i = 0; i < oprsz_16; i++) { | ||
183 | + l = m[2 * i + 0]; | ||
184 | + h = m[2 * i + 1]; | ||
185 | + l = compress_bits(l >> odd, esz); | ||
186 | + h = compress_bits(h >> odd, esz); | ||
187 | + tmp_m.p[i] = l + (h << 32); | ||
188 | + } | ||
189 | + tmp_m.p[i] = compress_bits(m[2 * i] >> odd, esz); | ||
190 | + | ||
191 | + swap_memmove(vd + oprsz / 2, &tmp_m, oprsz / 2); | ||
192 | + } else { | ||
193 | + for (i = 0; i < oprsz_16; i++) { | ||
194 | + l = m[2 * i + 0]; | ||
195 | + h = m[2 * i + 1]; | ||
196 | + l = compress_bits(l >> odd, esz); | ||
197 | + h = compress_bits(h >> odd, esz); | ||
198 | + d[oprsz_16 + i] = l + (h << 32); | ||
199 | + } | ||
200 | + } | ||
201 | + } | ||
202 | +} | ||
203 | + | ||
204 | +void HELPER(sve_trn_p)(void *vd, void *vn, void *vm, uint32_t pred_desc) | ||
205 | +{ | ||
206 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
207 | + uintptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | ||
208 | + bool odd = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); | ||
209 | + uint64_t *d = vd, *n = vn, *m = vm; | ||
210 | + uint64_t mask; | ||
211 | + int shr, shl; | ||
212 | + intptr_t i; | ||
213 | + | ||
214 | + shl = 1 << esz; | ||
215 | + shr = 0; | ||
216 | + mask = even_bit_esz_masks[esz]; | ||
217 | + if (odd) { | ||
218 | + mask <<= shl; | ||
219 | + shr = shl; | ||
220 | + shl = 0; | ||
221 | + } | ||
222 | + | ||
223 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); i++) { | ||
224 | + uint64_t nn = (n[i] & mask) >> shr; | ||
225 | + uint64_t mm = (m[i] & mask) << shl; | ||
226 | + d[i] = nn + mm; | ||
227 | + } | ||
228 | +} | ||
229 | + | ||
230 | +/* Reverse units of 2**N bits. */ | ||
231 | +static uint64_t reverse_bits_64(uint64_t x, int n) | ||
232 | +{ | ||
233 | + int i, sh; | ||
234 | + | ||
235 | + x = bswap64(x); | ||
236 | + for (i = 2, sh = 4; i >= n; i--, sh >>= 1) { | ||
237 | + uint64_t mask = even_bit_esz_masks[i]; | ||
238 | + x = ((x & mask) << sh) | ((x >> sh) & mask); | ||
239 | + } | ||
240 | + return x; | ||
241 | +} | ||
242 | + | ||
243 | +static uint8_t reverse_bits_8(uint8_t x, int n) | ||
244 | +{ | ||
245 | + static const uint8_t mask[3] = { 0x55, 0x33, 0x0f }; | ||
246 | + int i, sh; | ||
247 | + | ||
248 | + for (i = 2, sh = 4; i >= n; i--, sh >>= 1) { | ||
249 | + x = ((x & mask[i]) << sh) | ((x >> sh) & mask[i]); | ||
250 | + } | ||
251 | + return x; | ||
252 | +} | ||
253 | + | ||
254 | +void HELPER(sve_rev_p)(void *vd, void *vn, uint32_t pred_desc) | ||
255 | +{ | ||
256 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
257 | + int esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); | ||
258 | + intptr_t i, oprsz_2 = oprsz / 2; | ||
259 | + | ||
260 | + if (oprsz <= 8) { | ||
261 | + uint64_t l = *(uint64_t *)vn; | ||
262 | + l = reverse_bits_64(l << (64 - 8 * oprsz), esz); | ||
263 | + *(uint64_t *)vd = l; | ||
264 | + } else if ((oprsz & 15) == 0) { | ||
265 | + for (i = 0; i < oprsz_2; i += 8) { | ||
266 | + intptr_t ih = oprsz - 8 - i; | ||
267 | + uint64_t l = reverse_bits_64(*(uint64_t *)(vn + i), esz); | ||
268 | + uint64_t h = reverse_bits_64(*(uint64_t *)(vn + ih), esz); | ||
269 | + *(uint64_t *)(vd + i) = h; | ||
270 | + *(uint64_t *)(vd + ih) = l; | ||
271 | + } | ||
272 | + } else { | ||
273 | + for (i = 0; i < oprsz_2; i += 1) { | ||
274 | + intptr_t il = H1(i); | ||
275 | + intptr_t ih = H1(oprsz - 1 - i); | ||
276 | + uint8_t l = reverse_bits_8(*(uint8_t *)(vn + il), esz); | ||
277 | + uint8_t h = reverse_bits_8(*(uint8_t *)(vn + ih), esz); | ||
278 | + *(uint8_t *)(vd + il) = h; | ||
279 | + *(uint8_t *)(vd + ih) = l; | ||
280 | + } | ||
281 | + } | ||
282 | +} | ||
283 | + | ||
284 | +void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc) | ||
285 | +{ | ||
286 | + intptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; | ||
287 | + intptr_t high = extract32(pred_desc, SIMD_DATA_SHIFT + 2, 1); | ||
288 | + uint64_t *d = vd; | ||
289 | + intptr_t i; | ||
290 | + | ||
291 | + if (oprsz <= 8) { | ||
292 | + uint64_t nn = *(uint64_t *)vn; | ||
293 | + int half = 4 * oprsz; | ||
294 | + | ||
295 | + nn = extract64(nn, high * half, half); | ||
296 | + nn = expand_bits(nn, 0); | ||
297 | + d[0] = nn; | ||
298 | + } else { | ||
299 | + ARMPredicateReg tmp_n; | ||
300 | + | ||
301 | + /* We produce output faster than we consume input. | ||
302 | + Therefore we must be mindful of possible overlap. */ | ||
303 | + if ((vn - vd) < (uintptr_t)oprsz) { | ||
304 | + vn = memcpy(&tmp_n, vn, oprsz); | ||
305 | + } | ||
306 | + if (high) { | ||
307 | + high = oprsz >> 1; | ||
308 | + } | ||
309 | + | ||
310 | + if ((high & 3) == 0) { | ||
311 | + uint32_t *n = vn; | ||
312 | + high >>= 2; | ||
313 | + | ||
314 | + for (i = 0; i < DIV_ROUND_UP(oprsz, 8); i++) { | ||
315 | + uint64_t nn = n[H4(high + i)]; | ||
316 | + d[i] = expand_bits(nn, 0); | ||
317 | + } | ||
318 | + } else { | ||
319 | + uint16_t *d16 = vd; | ||
320 | + uint8_t *n = vn; | ||
321 | + | ||
322 | + for (i = 0; i < oprsz / 2; i++) { | ||
323 | + uint16_t nn = n[H1(high + i)]; | ||
324 | + d16[H2(i)] = expand_bits(nn, 0); | ||
325 | + } | ||
326 | + } | ||
327 | + } | ||
328 | +} | ||
329 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
330 | index XXXXXXX..XXXXXXX 100644 | ||
331 | --- a/target/arm/translate-sve.c | ||
332 | +++ b/target/arm/translate-sve.c | ||
333 | @@ -XXX,XX +XXX,XX @@ static bool trans_UNPK(DisasContext *s, arg_UNPK *a, uint32_t insn) | ||
334 | return true; | ||
335 | } | ||
336 | |||
337 | +/* | ||
338 | + *** SVE Permute - Predicates Group | ||
339 | + */ | ||
340 | + | ||
341 | +static bool do_perm_pred3(DisasContext *s, arg_rrr_esz *a, bool high_odd, | ||
342 | + gen_helper_gvec_3 *fn) | ||
343 | +{ | ||
344 | + if (!sve_access_check(s)) { | ||
345 | + return true; | ||
346 | + } | ||
347 | + | ||
348 | + unsigned vsz = pred_full_reg_size(s); | ||
349 | + | ||
350 | + /* Predicate sizes may be smaller and cannot use simd_desc. | ||
351 | + We cannot round up, as we do elsewhere, because we need | ||
352 | + the exact size for ZIP2 and REV. We retain the style for | ||
353 | + the other helpers for consistency. */ | ||
354 | + TCGv_ptr t_d = tcg_temp_new_ptr(); | ||
355 | + TCGv_ptr t_n = tcg_temp_new_ptr(); | ||
356 | + TCGv_ptr t_m = tcg_temp_new_ptr(); | ||
357 | + TCGv_i32 t_desc; | ||
358 | + int desc; | ||
359 | + | ||
360 | + desc = vsz - 2; | ||
361 | + desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); | ||
362 | + desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); | ||
363 | + | ||
364 | + tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
365 | + tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | ||
366 | + tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); | ||
367 | + t_desc = tcg_const_i32(desc); | ||
368 | + | ||
369 | + fn(t_d, t_n, t_m, t_desc); | ||
370 | + | ||
371 | + tcg_temp_free_ptr(t_d); | ||
372 | + tcg_temp_free_ptr(t_n); | ||
373 | + tcg_temp_free_ptr(t_m); | ||
374 | + tcg_temp_free_i32(t_desc); | ||
375 | + return true; | ||
376 | +} | ||
377 | + | ||
378 | +static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd, | ||
379 | + gen_helper_gvec_2 *fn) | ||
380 | +{ | ||
381 | + if (!sve_access_check(s)) { | ||
382 | + return true; | ||
383 | + } | ||
384 | + | ||
385 | + unsigned vsz = pred_full_reg_size(s); | ||
386 | + TCGv_ptr t_d = tcg_temp_new_ptr(); | ||
387 | + TCGv_ptr t_n = tcg_temp_new_ptr(); | ||
388 | + TCGv_i32 t_desc; | ||
389 | + int desc; | ||
390 | + | ||
391 | + tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); | ||
392 | + tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); | ||
393 | + | ||
394 | + /* Predicate sizes may be smaller and cannot use simd_desc. | ||
395 | + We cannot round up, as we do elsewhere, because we need | ||
396 | + the exact size for ZIP2 and REV. We retain the style for | ||
397 | + the other helpers for consistency. */ | ||
398 | + | ||
399 | + desc = vsz - 2; | ||
400 | + desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); | ||
401 | + desc = deposit32(desc, SIMD_DATA_SHIFT + 2, 2, high_odd); | ||
402 | + t_desc = tcg_const_i32(desc); | ||
403 | + | ||
404 | + fn(t_d, t_n, t_desc); | ||
405 | + | ||
406 | + tcg_temp_free_i32(t_desc); | ||
407 | + tcg_temp_free_ptr(t_d); | ||
408 | + tcg_temp_free_ptr(t_n); | ||
409 | + return true; | ||
410 | +} | ||
411 | + | ||
412 | +static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
413 | +{ | ||
414 | + return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p); | ||
415 | +} | ||
416 | + | ||
417 | +static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
418 | +{ | ||
419 | + return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p); | ||
420 | +} | ||
421 | + | ||
422 | +static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
423 | +{ | ||
424 | + return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p); | ||
425 | +} | ||
426 | + | ||
427 | +static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
428 | +{ | ||
429 | + return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p); | ||
430 | +} | ||
431 | + | ||
432 | +static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
433 | +{ | ||
434 | + return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p); | ||
435 | +} | ||
436 | + | ||
437 | +static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
438 | +{ | ||
439 | + return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p); | ||
440 | +} | ||
441 | + | ||
442 | +static bool trans_REV_p(DisasContext *s, arg_rr_esz *a, uint32_t insn) | ||
443 | +{ | ||
444 | + return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p); | ||
445 | +} | ||
446 | + | ||
447 | +static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a, uint32_t insn) | ||
448 | +{ | ||
449 | + return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p); | ||
450 | +} | ||
451 | + | ||
452 | +static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a, uint32_t insn) | ||
453 | +{ | ||
454 | + return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p); | ||
455 | +} | ||
456 | + | ||
457 | /* | ||
458 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
459 | */ | ||
460 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
461 | index XXXXXXX..XXXXXXX 100644 | ||
462 | --- a/target/arm/sve.decode | ||
463 | +++ b/target/arm/sve.decode | ||
464 | @@ -XXX,XX +XXX,XX @@ | ||
465 | |||
466 | # Three operand, vector element size | ||
467 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | ||
468 | +@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz | ||
469 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ | ||
470 | &rrr_esz rn=%reg_movprfx | ||
471 | |||
472 | @@ -XXX,XX +XXX,XX @@ TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | ||
473 | # SVE unpack vector elements | ||
474 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | ||
475 | |||
476 | +### SVE Permute - Predicates Group | ||
477 | + | ||
478 | +# SVE permute predicate elements | ||
479 | +ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | ||
480 | +ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | ||
481 | +UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | ||
482 | +UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | ||
483 | +TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | ||
484 | +TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | ||
485 | + | ||
486 | +# SVE reverse predicate elements | ||
487 | +REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | ||
488 | + | ||
489 | +# SVE unpack predicate elements | ||
490 | +PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | ||
491 | +PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | ||
492 | + | ||
493 | ### SVE Predicate Logical Operations Group | ||
494 | |||
495 | # SVE predicate logical operations | ||
496 | -- | 33 | -- |
497 | 2.17.1 | 34 | 2.25.1 |
498 | 35 | ||
499 | 36 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | To propagate errors to the caller of the pre_plug callback, use the |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | object_poperty_set*() functions directly instead of the qdev_prop_set*() |
5 | Message-id: 20180613015641.5667-5-richard.henderson@linaro.org | 5 | helpers. |
6 | |||
7 | Suggested-by: Igor Mammedov <imammedo@redhat.com> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20211210170415.583179-5-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/helper-sve.h | 15 ++++++++ | 14 | hw/arm/virt.c | 5 +++-- |
9 | target/arm/sve_helper.c | 72 ++++++++++++++++++++++++++++++++++++ | 15 | 1 file changed, 3 insertions(+), 2 deletions(-) |
10 | target/arm/translate-sve.c | 75 ++++++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/sve.decode | 10 +++++ | ||
12 | 4 files changed, 172 insertions(+) | ||
13 | 16 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 17 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 19 | --- a/hw/arm/virt.c |
17 | +++ b/target/arm/helper-sve.h | 20 | +++ b/hw/arm/virt.c |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_trn_p, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 21 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, |
19 | DEF_HELPER_FLAGS_3(sve_rev_p, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 22 | db_start, db_end, |
20 | DEF_HELPER_FLAGS_3(sve_punpk_p, TCG_CALL_NO_RWG, void, ptr, ptr, i32) | 23 | VIRTIO_IOMMU_RESV_MEM_T_MSI); |
21 | 24 | ||
22 | +DEF_HELPER_FLAGS_4(sve_zip_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 25 | - qdev_prop_set_uint32(dev, "len-reserved-regions", 1); |
23 | +DEF_HELPER_FLAGS_4(sve_zip_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 26 | - qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str); |
24 | +DEF_HELPER_FLAGS_4(sve_zip_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 27 | + object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp); |
25 | +DEF_HELPER_FLAGS_4(sve_zip_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 28 | + object_property_set_str(OBJECT(dev), "reserved-regions[0]", |
26 | + | 29 | + resv_prop_str, errp); |
27 | +DEF_HELPER_FLAGS_4(sve_uzp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 30 | g_free(resv_prop_str); |
28 | +DEF_HELPER_FLAGS_4(sve_uzp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_4(sve_uzp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_4(sve_uzp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
31 | + | ||
32 | +DEF_HELPER_FLAGS_4(sve_trn_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
33 | +DEF_HELPER_FLAGS_4(sve_trn_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_4(sve_trn_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_4(sve_trn_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | ||
36 | + | ||
37 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
38 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
39 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | ||
40 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/sve_helper.c | ||
43 | +++ b/target/arm/sve_helper.c | ||
44 | @@ -XXX,XX +XXX,XX @@ void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc) | ||
45 | } | ||
46 | } | 31 | } |
47 | } | 32 | } |
48 | + | ||
49 | +#define DO_ZIP(NAME, TYPE, H) \ | ||
50 | +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ | ||
51 | +{ \ | ||
52 | + intptr_t oprsz = simd_oprsz(desc); \ | ||
53 | + intptr_t i, oprsz_2 = oprsz / 2; \ | ||
54 | + ARMVectorReg tmp_n, tmp_m; \ | ||
55 | + /* We produce output faster than we consume input. \ | ||
56 | + Therefore we must be mindful of possible overlap. */ \ | ||
57 | + if (unlikely((vn - vd) < (uintptr_t)oprsz)) { \ | ||
58 | + vn = memcpy(&tmp_n, vn, oprsz_2); \ | ||
59 | + } \ | ||
60 | + if (unlikely((vm - vd) < (uintptr_t)oprsz)) { \ | ||
61 | + vm = memcpy(&tmp_m, vm, oprsz_2); \ | ||
62 | + } \ | ||
63 | + for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \ | ||
64 | + *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + H(i)); \ | ||
65 | + *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = *(TYPE *)(vm + H(i)); \ | ||
66 | + } \ | ||
67 | +} | ||
68 | + | ||
69 | +DO_ZIP(sve_zip_b, uint8_t, H1) | ||
70 | +DO_ZIP(sve_zip_h, uint16_t, H1_2) | ||
71 | +DO_ZIP(sve_zip_s, uint32_t, H1_4) | ||
72 | +DO_ZIP(sve_zip_d, uint64_t, ) | ||
73 | + | ||
74 | +#define DO_UZP(NAME, TYPE, H) \ | ||
75 | +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ | ||
76 | +{ \ | ||
77 | + intptr_t oprsz = simd_oprsz(desc); \ | ||
78 | + intptr_t oprsz_2 = oprsz / 2; \ | ||
79 | + intptr_t odd_ofs = simd_data(desc); \ | ||
80 | + intptr_t i; \ | ||
81 | + ARMVectorReg tmp_m; \ | ||
82 | + if (unlikely((vm - vd) < (uintptr_t)oprsz)) { \ | ||
83 | + vm = memcpy(&tmp_m, vm, oprsz); \ | ||
84 | + } \ | ||
85 | + for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \ | ||
86 | + *(TYPE *)(vd + H(i)) = *(TYPE *)(vn + H(2 * i + odd_ofs)); \ | ||
87 | + } \ | ||
88 | + for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \ | ||
89 | + *(TYPE *)(vd + H(oprsz_2 + i)) = *(TYPE *)(vm + H(2 * i + odd_ofs)); \ | ||
90 | + } \ | ||
91 | +} | ||
92 | + | ||
93 | +DO_UZP(sve_uzp_b, uint8_t, H1) | ||
94 | +DO_UZP(sve_uzp_h, uint16_t, H1_2) | ||
95 | +DO_UZP(sve_uzp_s, uint32_t, H1_4) | ||
96 | +DO_UZP(sve_uzp_d, uint64_t, ) | ||
97 | + | ||
98 | +#define DO_TRN(NAME, TYPE, H) \ | ||
99 | +void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ | ||
100 | +{ \ | ||
101 | + intptr_t oprsz = simd_oprsz(desc); \ | ||
102 | + intptr_t odd_ofs = simd_data(desc); \ | ||
103 | + intptr_t i; \ | ||
104 | + for (i = 0; i < oprsz; i += 2 * sizeof(TYPE)) { \ | ||
105 | + TYPE ae = *(TYPE *)(vn + H(i + odd_ofs)); \ | ||
106 | + TYPE be = *(TYPE *)(vm + H(i + odd_ofs)); \ | ||
107 | + *(TYPE *)(vd + H(i + 0)) = ae; \ | ||
108 | + *(TYPE *)(vd + H(i + sizeof(TYPE))) = be; \ | ||
109 | + } \ | ||
110 | +} | ||
111 | + | ||
112 | +DO_TRN(sve_trn_b, uint8_t, H1) | ||
113 | +DO_TRN(sve_trn_h, uint16_t, H1_2) | ||
114 | +DO_TRN(sve_trn_s, uint32_t, H1_4) | ||
115 | +DO_TRN(sve_trn_d, uint64_t, ) | ||
116 | + | ||
117 | +#undef DO_ZIP | ||
118 | +#undef DO_UZP | ||
119 | +#undef DO_TRN | ||
120 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
121 | index XXXXXXX..XXXXXXX 100644 | ||
122 | --- a/target/arm/translate-sve.c | ||
123 | +++ b/target/arm/translate-sve.c | ||
124 | @@ -XXX,XX +XXX,XX @@ static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a, uint32_t insn) | ||
125 | return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p); | ||
126 | } | ||
127 | |||
128 | +/* | ||
129 | + *** SVE Permute - Interleaving Group | ||
130 | + */ | ||
131 | + | ||
132 | +static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high) | ||
133 | +{ | ||
134 | + static gen_helper_gvec_3 * const fns[4] = { | ||
135 | + gen_helper_sve_zip_b, gen_helper_sve_zip_h, | ||
136 | + gen_helper_sve_zip_s, gen_helper_sve_zip_d, | ||
137 | + }; | ||
138 | + | ||
139 | + if (sve_access_check(s)) { | ||
140 | + unsigned vsz = vec_full_reg_size(s); | ||
141 | + unsigned high_ofs = high ? vsz / 2 : 0; | ||
142 | + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | ||
143 | + vec_full_reg_offset(s, a->rn) + high_ofs, | ||
144 | + vec_full_reg_offset(s, a->rm) + high_ofs, | ||
145 | + vsz, vsz, 0, fns[a->esz]); | ||
146 | + } | ||
147 | + return true; | ||
148 | +} | ||
149 | + | ||
150 | +static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data, | ||
151 | + gen_helper_gvec_3 *fn) | ||
152 | +{ | ||
153 | + if (sve_access_check(s)) { | ||
154 | + unsigned vsz = vec_full_reg_size(s); | ||
155 | + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), | ||
156 | + vec_full_reg_offset(s, a->rn), | ||
157 | + vec_full_reg_offset(s, a->rm), | ||
158 | + vsz, vsz, data, fn); | ||
159 | + } | ||
160 | + return true; | ||
161 | +} | ||
162 | + | ||
163 | +static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
164 | +{ | ||
165 | + return do_zip(s, a, false); | ||
166 | +} | ||
167 | + | ||
168 | +static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
169 | +{ | ||
170 | + return do_zip(s, a, true); | ||
171 | +} | ||
172 | + | ||
173 | +static gen_helper_gvec_3 * const uzp_fns[4] = { | ||
174 | + gen_helper_sve_uzp_b, gen_helper_sve_uzp_h, | ||
175 | + gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, | ||
176 | +}; | ||
177 | + | ||
178 | +static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
179 | +{ | ||
180 | + return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]); | ||
181 | +} | ||
182 | + | ||
183 | +static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
184 | +{ | ||
185 | + return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]); | ||
186 | +} | ||
187 | + | ||
188 | +static gen_helper_gvec_3 * const trn_fns[4] = { | ||
189 | + gen_helper_sve_trn_b, gen_helper_sve_trn_h, | ||
190 | + gen_helper_sve_trn_s, gen_helper_sve_trn_d, | ||
191 | +}; | ||
192 | + | ||
193 | +static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
194 | +{ | ||
195 | + return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]); | ||
196 | +} | ||
197 | + | ||
198 | +static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
199 | +{ | ||
200 | + return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]); | ||
201 | +} | ||
202 | + | ||
203 | /* | ||
204 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
205 | */ | ||
206 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
207 | index XXXXXXX..XXXXXXX 100644 | ||
208 | --- a/target/arm/sve.decode | ||
209 | +++ b/target/arm/sve.decode | ||
210 | @@ -XXX,XX +XXX,XX @@ REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | ||
211 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | ||
212 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | ||
213 | |||
214 | +### SVE Permute - Interleaving Group | ||
215 | + | ||
216 | +# SVE permute vector elements | ||
217 | +ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | ||
218 | +ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | ||
219 | +UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | ||
220 | +UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | ||
221 | +TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | ||
222 | +TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | ||
223 | + | ||
224 | ### SVE Predicate Logical Operations Group | ||
225 | |||
226 | # SVE predicate logical operations | ||
227 | -- | 33 | -- |
228 | 2.17.1 | 34 | 2.25.1 |
229 | 35 | ||
230 | 36 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Create empty data files and allow updates for the upcoming VIOT tests. |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | |
5 | Message-id: 20180613015641.5667-6-richard.henderson@linaro.org | 5 | Acked-by: Igor Mammedov <imammedo@redhat.com> |
6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
8 | Message-id: 20211210170415.583179-6-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | target/arm/helper-sve.h | 3 +++ | 11 | tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ |
9 | target/arm/sve_helper.c | 34 ++++++++++++++++++++++++++++++++++ | 12 | tests/data/acpi/q35/DSDT.viot | 0 |
10 | target/arm/translate-sve.c | 12 ++++++++++++ | 13 | tests/data/acpi/q35/VIOT.viot | 0 |
11 | target/arm/sve.decode | 6 ++++++ | 14 | tests/data/acpi/virt/VIOT | 0 |
12 | 4 files changed, 55 insertions(+) | 15 | 4 files changed, 3 insertions(+) |
16 | create mode 100644 tests/data/acpi/q35/DSDT.viot | ||
17 | create mode 100644 tests/data/acpi/q35/VIOT.viot | ||
18 | create mode 100644 tests/data/acpi/virt/VIOT | ||
13 | 19 | ||
14 | diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h | 20 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h |
15 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper-sve.h | 22 | --- a/tests/qtest/bios-tables-test-allowed-diff.h |
17 | +++ b/target/arm/helper-sve.h | 23 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h |
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(sve_trn_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 24 | @@ -1 +1,4 @@ |
19 | DEF_HELPER_FLAGS_4(sve_trn_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 25 | /* List of comma-separated changed AML files to ignore */ |
20 | DEF_HELPER_FLAGS_4(sve_trn_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 26 | +"tests/data/acpi/virt/VIOT", |
21 | 27 | +"tests/data/acpi/q35/DSDT.viot", | |
22 | +DEF_HELPER_FLAGS_4(sve_compact_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 28 | +"tests/data/acpi/q35/VIOT.viot", |
23 | +DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) | 29 | diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot |
24 | + | 30 | new file mode 100644 |
25 | DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 31 | index XXXXXXX..XXXXXXX |
26 | DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 32 | diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot |
27 | DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) | 33 | new file mode 100644 |
28 | diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c | 34 | index XXXXXXX..XXXXXXX |
29 | index XXXXXXX..XXXXXXX 100644 | 35 | diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT |
30 | --- a/target/arm/sve_helper.c | 36 | new file mode 100644 |
31 | +++ b/target/arm/sve_helper.c | 37 | index XXXXXXX..XXXXXXX |
32 | @@ -XXX,XX +XXX,XX @@ DO_TRN(sve_trn_d, uint64_t, ) | ||
33 | #undef DO_ZIP | ||
34 | #undef DO_UZP | ||
35 | #undef DO_TRN | ||
36 | + | ||
37 | +void HELPER(sve_compact_s)(void *vd, void *vn, void *vg, uint32_t desc) | ||
38 | +{ | ||
39 | + intptr_t i, j, opr_sz = simd_oprsz(desc) / 4; | ||
40 | + uint32_t *d = vd, *n = vn; | ||
41 | + uint8_t *pg = vg; | ||
42 | + | ||
43 | + for (i = j = 0; i < opr_sz; i++) { | ||
44 | + if (pg[H1(i / 2)] & (i & 1 ? 0x10 : 0x01)) { | ||
45 | + d[H4(j)] = n[H4(i)]; | ||
46 | + j++; | ||
47 | + } | ||
48 | + } | ||
49 | + for (; j < opr_sz; j++) { | ||
50 | + d[H4(j)] = 0; | ||
51 | + } | ||
52 | +} | ||
53 | + | ||
54 | +void HELPER(sve_compact_d)(void *vd, void *vn, void *vg, uint32_t desc) | ||
55 | +{ | ||
56 | + intptr_t i, j, opr_sz = simd_oprsz(desc) / 8; | ||
57 | + uint64_t *d = vd, *n = vn; | ||
58 | + uint8_t *pg = vg; | ||
59 | + | ||
60 | + for (i = j = 0; i < opr_sz; i++) { | ||
61 | + if (pg[H1(i)] & 1) { | ||
62 | + d[j] = n[i]; | ||
63 | + j++; | ||
64 | + } | ||
65 | + } | ||
66 | + for (; j < opr_sz; j++) { | ||
67 | + d[j] = 0; | ||
68 | + } | ||
69 | +} | ||
70 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/translate-sve.c | ||
73 | +++ b/target/arm/translate-sve.c | ||
74 | @@ -XXX,XX +XXX,XX @@ static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a, uint32_t insn) | ||
75 | return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]); | ||
76 | } | ||
77 | |||
78 | +/* | ||
79 | + *** SVE Permute Vector - Predicated Group | ||
80 | + */ | ||
81 | + | ||
82 | +static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | ||
83 | +{ | ||
84 | + static gen_helper_gvec_3 * const fns[4] = { | ||
85 | + NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d | ||
86 | + }; | ||
87 | + return do_zpz_ool(s, a, fns[a->esz]); | ||
88 | +} | ||
89 | + | ||
90 | /* | ||
91 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | ||
92 | */ | ||
93 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/sve.decode | ||
96 | +++ b/target/arm/sve.decode | ||
97 | @@ -XXX,XX +XXX,XX @@ UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | ||
98 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | ||
99 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | ||
100 | |||
101 | +### SVE Permute - Predicated Group | ||
102 | + | ||
103 | +# SVE compress active elements | ||
104 | +# Note esz >= 2 | ||
105 | +COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | ||
106 | + | ||
107 | ### SVE Predicate Logical Operations Group | ||
108 | |||
109 | # SVE predicate logical operations | ||
110 | -- | 38 | -- |
111 | 2.17.1 | 39 | 2.25.1 |
112 | 40 | ||
113 | 41 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Add two test cases for VIOT, one on the q35 machine and the other on |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | virt. To test complex topologies the q35 test has two PCIe buses that |
5 | Message-id: 20180613015641.5667-8-richard.henderson@linaro.org | 5 | bypass the IOMMU (and are therefore not described by VIOT), and two |
6 | buses that are translated by virtio-iommu. | ||
7 | |||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20211210170415.583179-7-jean-philippe@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | target/arm/translate-sve.c | 19 +++++++++++++++++++ | 14 | tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++ |
9 | target/arm/sve.decode | 6 ++++++ | 15 | 1 file changed, 38 insertions(+) |
10 | 2 files changed, 25 insertions(+) | ||
11 | 16 | ||
12 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c | 17 | diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c |
13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/translate-sve.c | 19 | --- a/tests/qtest/bios-tables-test.c |
15 | +++ b/target/arm/translate-sve.c | 20 | +++ b/tests/qtest/bios-tables-test.c |
16 | @@ -XXX,XX +XXX,XX @@ static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 21 | @@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void) |
17 | return do_last_general(s, a, true); | 22 | free_test_data(&data); |
18 | } | 23 | } |
19 | 24 | ||
20 | +static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 25 | +static void test_acpi_q35_viot(void) |
21 | +{ | 26 | +{ |
22 | + if (sve_access_check(s)) { | 27 | + test_data data = { |
23 | + do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn)); | 28 | + .machine = MACHINE_Q35, |
24 | + } | 29 | + .variant = ".viot", |
25 | + return true; | 30 | + }; |
31 | + | ||
32 | + /* | ||
33 | + * To keep things interesting, two buses bypass the IOMMU. | ||
34 | + * VIOT should only describes the other two buses. | ||
35 | + */ | ||
36 | + test_acpi_one("-machine default_bus_bypass_iommu=on " | ||
37 | + "-device virtio-iommu-pci " | ||
38 | + "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 " | ||
39 | + "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on " | ||
40 | + "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0", | ||
41 | + &data); | ||
42 | + free_test_data(&data); | ||
26 | +} | 43 | +} |
27 | + | 44 | + |
28 | +static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) | 45 | +static void test_acpi_virt_viot(void) |
29 | +{ | 46 | +{ |
30 | + if (sve_access_check(s)) { | 47 | + test_data data = { |
31 | + int ofs = vec_reg_offset(s, a->rn, 0, a->esz); | 48 | + .machine = "virt", |
32 | + TCGv_i64 t = load_esz(cpu_env, ofs, a->esz); | 49 | + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", |
33 | + do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); | 50 | + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", |
34 | + tcg_temp_free_i64(t); | 51 | + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", |
35 | + } | 52 | + .ram_start = 0x40000000ULL, |
36 | + return true; | 53 | + .scan_len = 128ULL * 1024 * 1024, |
54 | + }; | ||
55 | + | ||
56 | + test_acpi_one("-cpu cortex-a57 " | ||
57 | + "-device virtio-iommu-pci", &data); | ||
58 | + free_test_data(&data); | ||
37 | +} | 59 | +} |
38 | + | 60 | + |
39 | /* | 61 | static void test_oem_fields(test_data *data) |
40 | *** SVE Memory - 32-bit Gather and Unsized Contiguous Group | 62 | { |
41 | */ | 63 | int i; |
42 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | 64 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
43 | index XXXXXXX..XXXXXXX 100644 | 65 | qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic); |
44 | --- a/target/arm/sve.decode | 66 | qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar); |
45 | +++ b/target/arm/sve.decode | 67 | } |
46 | @@ -XXX,XX +XXX,XX @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | 68 | + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); |
47 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | 69 | } else if (strcmp(arch, "aarch64") == 0) { |
48 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | 70 | if (has_tcg) { |
49 | 71 | qtest_add_func("acpi/virt", test_acpi_virt_tcg); | |
50 | +# SVE copy element from SIMD&FP scalar register | 72 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[]) |
51 | +CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | 73 | qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); |
52 | + | 74 | qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); |
53 | +# SVE copy element from general register to vector (predicated) | 75 | qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); |
54 | +CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | 76 | + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); |
55 | + | 77 | } |
56 | ### SVE Predicate Logical Operations Group | 78 | } |
57 | 79 | ret = g_test_run(); | |
58 | # SVE predicate logical operations | ||
59 | -- | 80 | -- |
60 | 2.17.1 | 81 | 2.25.1 |
61 | 82 | ||
62 | 83 | diff view generated by jsdifflib |
1 | The Cortex-M CPU and its NVIC are two intimately intertwined parts of | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | the same hardware; it is not possible to use one without the other. | 2 | |
3 | Unfortunately a lot of our board models don't do any sanity checking | 3 | Add expected blobs of the VIOT and DSDT table for the VIOT test on the |
4 | on the CPU type the user asks for, so a command line like | 4 | q35 machine. |
5 | qemu-system-arm -M versatilepb -cpu cortex-m3 | 5 | |
6 | will create an M3 without an NVIC, and coredump immediately. | 6 | Since the test instantiates a virtio device and two PCIe expander |
7 | In the other direction, trying a non-M-profile CPU in an M-profile | 7 | bridges, DSDT.viot has more blocks than the base DSDT. |
8 | board won't blow up, but doesn't do anything useful either: | 8 | |
9 | qemu-system-arm -M lm3s6965evb -cpu arm926 | 9 | The VIOT table generated for the q35 test is: |
10 | 10 | ||
11 | Add some checking in the NVIC and CPU realize functions that the | 11 | [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] |
12 | user isn't trying to use an NVIC without an M-profile CPU or | 12 | [004h 0004 4] Table Length : 00000070 |
13 | an M-profile CPU without an NVIC, so we can produce a helpful | 13 | [008h 0008 1] Revision : 00 |
14 | error message rather than a core dump. | 14 | [009h 0009 1] Checksum : 3D |
15 | 15 | [00Ah 0010 6] Oem ID : "BOCHS " | |
16 | Fixes: https://bugs.launchpad.net/qemu/+bug/1766896 | 16 | [010h 0016 8] Oem Table ID : "BXPC " |
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | [018h 0024 4] Oem Revision : 00000001 |
18 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 18 | [01Ch 0028 4] Asl Compiler ID : "BXPC" |
19 | Message-id: 20180601160355.15393-1-peter.maydell@linaro.org | 19 | [020h 0032 4] Asl Compiler Revision : 00000001 |
20 | --- | 20 | |
21 | hw/arm/armv7m.c | 7 ++++++- | 21 | [024h 0036 2] Node count : 0003 |
22 | hw/intc/armv7m_nvic.c | 6 +++++- | 22 | [026h 0038 2] Node offset : 0030 |
23 | target/arm/cpu.c | 18 ++++++++++++++++++ | 23 | [028h 0040 8] Reserved : 0000000000000000 |
24 | 3 files changed, 29 insertions(+), 2 deletions(-) | 24 | |
25 | 25 | [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] | |
26 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | 26 | [031h 0049 1] Reserved : 00 |
27 | index XXXXXXX..XXXXXXX 100644 | 27 | [032h 0050 2] Length : 0010 |
28 | --- a/hw/arm/armv7m.c | 28 | |
29 | +++ b/hw/arm/armv7m.c | 29 | [034h 0052 2] PCI Segment : 0000 |
30 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 30 | [036h 0054 2] PCI BDF number : 0010 |
31 | return; | 31 | [038h 0056 8] Reserved : 0000000000000000 |
32 | |||
33 | [040h 0064 1] Type : 01 [PCI Range] | ||
34 | [041h 0065 1] Reserved : 00 | ||
35 | [042h 0066 2] Length : 0018 | ||
36 | |||
37 | [044h 0068 4] Endpoint start : 00003000 | ||
38 | [048h 0072 2] PCI Segment start : 0000 | ||
39 | [04Ah 0074 2] PCI Segment end : 0000 | ||
40 | [04Ch 0076 2] PCI BDF start : 3000 | ||
41 | [04Eh 0078 2] PCI BDF end : 30FF | ||
42 | [050h 0080 2] Output node : 0030 | ||
43 | [052h 0082 6] Reserved : 000000000000 | ||
44 | |||
45 | [058h 0088 1] Type : 01 [PCI Range] | ||
46 | [059h 0089 1] Reserved : 00 | ||
47 | [05Ah 0090 2] Length : 0018 | ||
48 | |||
49 | [05Ch 0092 4] Endpoint start : 00001000 | ||
50 | [060h 0096 2] PCI Segment start : 0000 | ||
51 | [062h 0098 2] PCI Segment end : 0000 | ||
52 | [064h 0100 2] PCI BDF start : 1000 | ||
53 | [066h 0102 2] PCI BDF end : 10FF | ||
54 | [068h 0104 2] Output node : 0030 | ||
55 | [06Ah 0106 6] Reserved : 000000000000 | ||
56 | |||
57 | And the DSDT diff is: | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | * | ||
61 | * Disassembling to symbolic ASL+ operators | ||
62 | * | ||
63 | - * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021 | ||
64 | + * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021 | ||
65 | * | ||
66 | * Original Table Header: | ||
67 | * Signature "DSDT" | ||
68 | - * Length 0x00002061 (8289) | ||
69 | + * Length 0x000024B6 (9398) | ||
70 | * Revision 0x01 **** 32-bit table (V1), no 64-bit math support | ||
71 | - * Checksum 0xFA | ||
72 | + * Checksum 0xA7 | ||
73 | * OEM ID "BOCHS " | ||
74 | * OEM Table ID "BXPC " | ||
75 | * OEM Revision 0x00000001 (1) | ||
76 | @@ -XXX,XX +XXX,XX @@ | ||
32 | } | 77 | } |
33 | } | 78 | } |
34 | + | 79 | |
35 | + /* Tell the CPU where the NVIC is; it will fail realize if it doesn't | 80 | + Scope (\_SB) |
36 | + * have one. | 81 | + { |
37 | + */ | 82 | + Device (PC30) |
38 | + s->cpu->env.nvic = &s->nvic; | 83 | + { |
39 | + | 84 | + Name (_UID, 0x30) // _UID: Unique ID |
40 | object_property_set_bool(OBJECT(s->cpu), true, "realized", &err); | 85 | + Name (_BBN, 0x30) // _BBN: BIOS Bus Number |
41 | if (err != NULL) { | 86 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID |
42 | error_propagate(errp, err); | 87 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID |
43 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | 88 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities |
44 | sbd = SYS_BUS_DEVICE(&s->nvic); | 89 | + { |
45 | sysbus_connect_irq(sbd, 0, | 90 | + CreateDWordField (Arg3, Zero, CDW1) |
46 | qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); | 91 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) |
47 | - s->cpu->env.nvic = &s->nvic; | 92 | + { |
48 | 93 | + CreateDWordField (Arg3, 0x04, CDW2) | |
49 | memory_region_add_subregion(&s->container, 0xe000e000, | 94 | + CreateDWordField (Arg3, 0x08, CDW3) |
50 | sysbus_mmio_get_region(sbd, 0)); | 95 | + Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */ |
51 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 96 | + Local0 &= 0x1F |
52 | index XXXXXXX..XXXXXXX 100644 | 97 | + If ((Arg1 != One)) |
53 | --- a/hw/intc/armv7m_nvic.c | 98 | + { |
54 | +++ b/hw/intc/armv7m_nvic.c | 99 | + CDW1 |= 0x08 |
55 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) | 100 | + } |
56 | int regionlen; | 101 | + |
57 | 102 | + If ((CDW3 != Local0)) | |
58 | s->cpu = ARM_CPU(qemu_get_cpu(0)); | 103 | + { |
59 | - assert(s->cpu); | 104 | + CDW1 |= 0x10 |
60 | + | 105 | + } |
61 | + if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { | 106 | + |
62 | + error_setg(errp, "The NVIC can only be used with a Cortex-M CPU"); | 107 | + CDW3 = Local0 |
63 | + return; | 108 | + } |
64 | + } | 109 | + Else |
65 | 110 | + { | |
66 | if (s->num_irq > NVIC_MAX_IRQ) { | 111 | + CDW1 |= 0x04 |
67 | error_setg(errp, "num-irq %d exceeds NVIC maximum", s->num_irq); | 112 | + } |
68 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 113 | + |
69 | index XXXXXXX..XXXXXXX 100644 | 114 | + Return (Arg3) |
70 | --- a/target/arm/cpu.c | 115 | + } |
71 | +++ b/target/arm/cpu.c | 116 | + |
72 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 117 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table |
73 | return; | 118 | + { |
74 | } | 119 | + Local0 = Package (0x80){} |
75 | 120 | + Local1 = Zero | |
76 | +#ifndef CONFIG_USER_ONLY | 121 | + While ((Local1 < 0x80)) |
77 | + /* The NVIC and M-profile CPU are two halves of a single piece of | 122 | + { |
78 | + * hardware; trying to use one without the other is a command line | 123 | + Local2 = (Local1 >> 0x02) |
79 | + * error and will result in segfaults if not caught here. | 124 | + Local3 = ((Local1 + Local2) & 0x03) |
80 | + */ | 125 | + If ((Local3 == Zero)) |
81 | + if (arm_feature(env, ARM_FEATURE_M)) { | 126 | + { |
82 | + if (!env->nvic) { | 127 | + Local4 = Package (0x04) |
83 | + error_setg(errp, "This board cannot be used with Cortex-M CPUs"); | 128 | + { |
84 | + return; | 129 | + Zero, |
85 | + } | 130 | + Zero, |
86 | + } else { | 131 | + LNKD, |
87 | + if (env->nvic) { | 132 | + Zero |
88 | + error_setg(errp, "This board can only be used with Cortex-M CPUs"); | 133 | + } |
89 | + return; | 134 | + } |
135 | + | ||
136 | + If ((Local3 == One)) | ||
137 | + { | ||
138 | + Local4 = Package (0x04) | ||
139 | + { | ||
140 | + Zero, | ||
141 | + Zero, | ||
142 | + LNKA, | ||
143 | + Zero | ||
144 | + } | ||
145 | + } | ||
146 | + | ||
147 | + If ((Local3 == 0x02)) | ||
148 | + { | ||
149 | + Local4 = Package (0x04) | ||
150 | + { | ||
151 | + Zero, | ||
152 | + Zero, | ||
153 | + LNKB, | ||
154 | + Zero | ||
155 | + } | ||
156 | + } | ||
157 | + | ||
158 | + If ((Local3 == 0x03)) | ||
159 | + { | ||
160 | + Local4 = Package (0x04) | ||
161 | + { | ||
162 | + Zero, | ||
163 | + Zero, | ||
164 | + LNKC, | ||
165 | + Zero | ||
166 | + } | ||
167 | + } | ||
168 | + | ||
169 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
170 | + Local4 [One] = (Local1 & 0x03) | ||
171 | + Local0 [Local1] = Local4 | ||
172 | + Local1++ | ||
173 | + } | ||
174 | + | ||
175 | + Return (Local0) | ||
176 | + } | ||
177 | + | ||
178 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
179 | + { | ||
180 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
181 | + 0x0000, // Granularity | ||
182 | + 0x0030, // Range Minimum | ||
183 | + 0x0030, // Range Maximum | ||
184 | + 0x0000, // Translation Offset | ||
185 | + 0x0001, // Length | ||
186 | + ,, ) | ||
187 | + }) | ||
90 | + } | 188 | + } |
91 | + } | 189 | + } |
92 | +#endif | 190 | + |
93 | + | 191 | + Scope (\_SB) |
94 | cpu_exec_realizefn(cs, &local_err); | 192 | + { |
95 | if (local_err != NULL) { | 193 | + Device (PC20) |
96 | error_propagate(errp, local_err); | 194 | + { |
195 | + Name (_UID, 0x20) // _UID: Unique ID | ||
196 | + Name (_BBN, 0x20) // _BBN: BIOS Bus Number | ||
197 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
198 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
199 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
200 | + { | ||
201 | + CreateDWordField (Arg3, Zero, CDW1) | ||
202 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
203 | + { | ||
204 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
205 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
206 | + Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */ | ||
207 | + Local0 &= 0x1F | ||
208 | + If ((Arg1 != One)) | ||
209 | + { | ||
210 | + CDW1 |= 0x08 | ||
211 | + } | ||
212 | + | ||
213 | + If ((CDW3 != Local0)) | ||
214 | + { | ||
215 | + CDW1 |= 0x10 | ||
216 | + } | ||
217 | + | ||
218 | + CDW3 = Local0 | ||
219 | + } | ||
220 | + Else | ||
221 | + { | ||
222 | + CDW1 |= 0x04 | ||
223 | + } | ||
224 | + | ||
225 | + Return (Arg3) | ||
226 | + } | ||
227 | + | ||
228 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
229 | + { | ||
230 | + Local0 = Package (0x80){} | ||
231 | + Local1 = Zero | ||
232 | + While ((Local1 < 0x80)) | ||
233 | + { | ||
234 | + Local2 = (Local1 >> 0x02) | ||
235 | + Local3 = ((Local1 + Local2) & 0x03) | ||
236 | + If ((Local3 == Zero)) | ||
237 | + { | ||
238 | + Local4 = Package (0x04) | ||
239 | + { | ||
240 | + Zero, | ||
241 | + Zero, | ||
242 | + LNKD, | ||
243 | + Zero | ||
244 | + } | ||
245 | + } | ||
246 | + | ||
247 | + If ((Local3 == One)) | ||
248 | + { | ||
249 | + Local4 = Package (0x04) | ||
250 | + { | ||
251 | + Zero, | ||
252 | + Zero, | ||
253 | + LNKA, | ||
254 | + Zero | ||
255 | + } | ||
256 | + } | ||
257 | + | ||
258 | + If ((Local3 == 0x02)) | ||
259 | + { | ||
260 | + Local4 = Package (0x04) | ||
261 | + { | ||
262 | + Zero, | ||
263 | + Zero, | ||
264 | + LNKB, | ||
265 | + Zero | ||
266 | + } | ||
267 | + } | ||
268 | + | ||
269 | + If ((Local3 == 0x03)) | ||
270 | + { | ||
271 | + Local4 = Package (0x04) | ||
272 | + { | ||
273 | + Zero, | ||
274 | + Zero, | ||
275 | + LNKC, | ||
276 | + Zero | ||
277 | + } | ||
278 | + } | ||
279 | + | ||
280 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
281 | + Local4 [One] = (Local1 & 0x03) | ||
282 | + Local0 [Local1] = Local4 | ||
283 | + Local1++ | ||
284 | + } | ||
285 | + | ||
286 | + Return (Local0) | ||
287 | + } | ||
288 | + | ||
289 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
290 | + { | ||
291 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
292 | + 0x0000, // Granularity | ||
293 | + 0x0020, // Range Minimum | ||
294 | + 0x0020, // Range Maximum | ||
295 | + 0x0000, // Translation Offset | ||
296 | + 0x0001, // Length | ||
297 | + ,, ) | ||
298 | + }) | ||
299 | + } | ||
300 | + } | ||
301 | + | ||
302 | + Scope (\_SB) | ||
303 | + { | ||
304 | + Device (PC10) | ||
305 | + { | ||
306 | + Name (_UID, 0x10) // _UID: Unique ID | ||
307 | + Name (_BBN, 0x10) // _BBN: BIOS Bus Number | ||
308 | + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID | ||
309 | + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID | ||
310 | + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities | ||
311 | + { | ||
312 | + CreateDWordField (Arg3, Zero, CDW1) | ||
313 | + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) | ||
314 | + { | ||
315 | + CreateDWordField (Arg3, 0x04, CDW2) | ||
316 | + CreateDWordField (Arg3, 0x08, CDW3) | ||
317 | + Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */ | ||
318 | + Local0 &= 0x1F | ||
319 | + If ((Arg1 != One)) | ||
320 | + { | ||
321 | + CDW1 |= 0x08 | ||
322 | + } | ||
323 | + | ||
324 | + If ((CDW3 != Local0)) | ||
325 | + { | ||
326 | + CDW1 |= 0x10 | ||
327 | + } | ||
328 | + | ||
329 | + CDW3 = Local0 | ||
330 | + } | ||
331 | + Else | ||
332 | + { | ||
333 | + CDW1 |= 0x04 | ||
334 | + } | ||
335 | + | ||
336 | + Return (Arg3) | ||
337 | + } | ||
338 | + | ||
339 | + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table | ||
340 | + { | ||
341 | + Local0 = Package (0x80){} | ||
342 | + Local1 = Zero | ||
343 | + While ((Local1 < 0x80)) | ||
344 | + { | ||
345 | + Local2 = (Local1 >> 0x02) | ||
346 | + Local3 = ((Local1 + Local2) & 0x03) | ||
347 | + If ((Local3 == Zero)) | ||
348 | + { | ||
349 | + Local4 = Package (0x04) | ||
350 | + { | ||
351 | + Zero, | ||
352 | + Zero, | ||
353 | + LNKD, | ||
354 | + Zero | ||
355 | + } | ||
356 | + } | ||
357 | + | ||
358 | + If ((Local3 == One)) | ||
359 | + { | ||
360 | + Local4 = Package (0x04) | ||
361 | + { | ||
362 | + Zero, | ||
363 | + Zero, | ||
364 | + LNKA, | ||
365 | + Zero | ||
366 | + } | ||
367 | + } | ||
368 | + | ||
369 | + If ((Local3 == 0x02)) | ||
370 | + { | ||
371 | + Local4 = Package (0x04) | ||
372 | + { | ||
373 | + Zero, | ||
374 | + Zero, | ||
375 | + LNKB, | ||
376 | + Zero | ||
377 | + } | ||
378 | + } | ||
379 | + | ||
380 | + If ((Local3 == 0x03)) | ||
381 | + { | ||
382 | + Local4 = Package (0x04) | ||
383 | + { | ||
384 | + Zero, | ||
385 | + Zero, | ||
386 | + LNKC, | ||
387 | + Zero | ||
388 | + } | ||
389 | + } | ||
390 | + | ||
391 | + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) | ||
392 | + Local4 [One] = (Local1 & 0x03) | ||
393 | + Local0 [Local1] = Local4 | ||
394 | + Local1++ | ||
395 | + } | ||
396 | + | ||
397 | + Return (Local0) | ||
398 | + } | ||
399 | + | ||
400 | + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
401 | + { | ||
402 | + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
403 | + 0x0000, // Granularity | ||
404 | + 0x0010, // Range Minimum | ||
405 | + 0x0010, // Range Maximum | ||
406 | + 0x0000, // Translation Offset | ||
407 | + 0x0001, // Length | ||
408 | + ,, ) | ||
409 | + }) | ||
410 | + } | ||
411 | + } | ||
412 | + | ||
413 | Scope (\_SB.PCI0) | ||
414 | { | ||
415 | Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings | ||
416 | @@ -XXX,XX +XXX,XX @@ | ||
417 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, | ||
418 | 0x0000, // Granularity | ||
419 | 0x0000, // Range Minimum | ||
420 | - 0x00FF, // Range Maximum | ||
421 | + 0x000F, // Range Maximum | ||
422 | 0x0000, // Translation Offset | ||
423 | - 0x0100, // Length | ||
424 | + 0x0010, // Length | ||
425 | ,, ) | ||
426 | IO (Decode16, | ||
427 | 0x0CF8, // Range Minimum | ||
428 | @@ -XXX,XX +XXX,XX @@ | ||
429 | } | ||
430 | } | ||
431 | |||
432 | + Device (S10) | ||
433 | + { | ||
434 | + Name (_ADR, 0x00020000) // _ADR: Address | ||
435 | + } | ||
436 | + | ||
437 | + Device (S18) | ||
438 | + { | ||
439 | + Name (_ADR, 0x00030000) // _ADR: Address | ||
440 | + } | ||
441 | + | ||
442 | + Device (S20) | ||
443 | + { | ||
444 | + Name (_ADR, 0x00040000) // _ADR: Address | ||
445 | + } | ||
446 | + | ||
447 | + Device (S28) | ||
448 | + { | ||
449 | + Name (_ADR, 0x00050000) // _ADR: Address | ||
450 | + } | ||
451 | + | ||
452 | Method (PCNT, 0, NotSerialized) | ||
453 | { | ||
454 | } | ||
455 | |||
456 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
457 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
458 | Message-id: 20211210170415.583179-8-jean-philippe@linaro.org | ||
459 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
460 | --- | ||
461 | tests/qtest/bios-tables-test-allowed-diff.h | 2 -- | ||
462 | tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes | ||
463 | tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes | ||
464 | 3 files changed, 2 deletions(-) | ||
465 | |||
466 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
467 | index XXXXXXX..XXXXXXX 100644 | ||
468 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
469 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
470 | @@ -XXX,XX +XXX,XX @@ | ||
471 | /* List of comma-separated changed AML files to ignore */ | ||
472 | "tests/data/acpi/virt/VIOT", | ||
473 | -"tests/data/acpi/q35/DSDT.viot", | ||
474 | -"tests/data/acpi/q35/VIOT.viot", | ||
475 | diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot | ||
476 | index XXXXXXX..XXXXXXX 100644 | ||
477 | GIT binary patch | ||
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543 | Gu>S+TT-130 | ||
544 | |||
545 | literal 0 | ||
546 | HcmV?d00001 | ||
547 | |||
548 | diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot | ||
549 | index XXXXXXX..XXXXXXX 100644 | ||
550 | GIT binary patch | ||
551 | literal 112 | ||
552 | zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj | ||
553 | Q0Zb)W9Hva*zW_`e0M!8s0RR91 | ||
554 | |||
555 | literal 0 | ||
556 | HcmV?d00001 | ||
557 | |||
97 | -- | 558 | -- |
98 | 2.17.1 | 559 | 2.25.1 |
99 | 560 | ||
100 | 561 | diff view generated by jsdifflib |
1 | From: Shannon Zhao <zhaoshenglong@huawei.com> | 1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | While for_each_dist_irq_reg loop starts from GIC_INTERNAL, it forgot to | 3 | The VIOT blob contains the following: |
4 | offset the date array and index. This will overlap the GICR registers | ||
5 | value and leave the last GIC_INTERNAL irq's registers out of update. | ||
6 | 4 | ||
7 | Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 | 5 | [000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table] |
8 | Cc: qemu-stable@nongnu.org | 6 | [004h 0004 4] Table Length : 00000058 |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | [008h 0008 1] Revision : 00 |
8 | [009h 0009 1] Checksum : 66 | ||
9 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
10 | [010h 0016 8] Oem Table ID : "BXPC " | ||
11 | [018h 0024 4] Oem Revision : 00000001 | ||
12 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
13 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
14 | |||
15 | [024h 0036 2] Node count : 0002 | ||
16 | [026h 0038 2] Node offset : 0030 | ||
17 | [028h 0040 8] Reserved : 0000000000000000 | ||
18 | |||
19 | [030h 0048 1] Type : 03 [VirtIO-PCI IOMMU] | ||
20 | [031h 0049 1] Reserved : 00 | ||
21 | [032h 0050 2] Length : 0010 | ||
22 | |||
23 | [034h 0052 2] PCI Segment : 0000 | ||
24 | [036h 0054 2] PCI BDF number : 0008 | ||
25 | [038h 0056 8] Reserved : 0000000000000000 | ||
26 | |||
27 | [040h 0064 1] Type : 01 [PCI Range] | ||
28 | [041h 0065 1] Reserved : 00 | ||
29 | [042h 0066 2] Length : 0018 | ||
30 | |||
31 | [044h 0068 4] Endpoint start : 00000000 | ||
32 | [048h 0072 2] PCI Segment start : 0000 | ||
33 | [04Ah 0074 2] PCI Segment end : 0000 | ||
34 | [04Ch 0076 2] PCI BDF start : 0000 | ||
35 | [04Eh 0078 2] PCI BDF end : 00FF | ||
36 | [050h 0080 2] Output node : 0030 | ||
37 | [052h 0082 6] Reserved : 000000000000 | ||
38 | |||
39 | Acked-by: Ani Sinha <ani@anisinha.ca> | ||
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | 40 | Reviewed-by: Eric Auger <eric.auger@redhat.com> |
11 | Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> | 41 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> |
42 | Message-id: 20211210170415.583179-9-jean-philippe@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 43 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 44 | --- |
14 | hw/intc/arm_gicv3_kvm.c | 18 ++++++++++++++++-- | 45 | tests/qtest/bios-tables-test-allowed-diff.h | 1 - |
15 | 1 file changed, 16 insertions(+), 2 deletions(-) | 46 | tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes |
47 | 2 files changed, 1 deletion(-) | ||
16 | 48 | ||
17 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | 49 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h |
18 | index XXXXXXX..XXXXXXX 100644 | 50 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/intc/arm_gicv3_kvm.c | 51 | --- a/tests/qtest/bios-tables-test-allowed-diff.h |
20 | +++ b/hw/intc/arm_gicv3_kvm.c | 52 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h |
21 | @@ -XXX,XX +XXX,XX @@ static void kvm_dist_get_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) | 53 | @@ -1,2 +1 @@ |
22 | uint32_t reg, *field; | 54 | /* List of comma-separated changed AML files to ignore */ |
23 | int irq; | 55 | -"tests/data/acpi/virt/VIOT", |
24 | 56 | diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT | |
25 | - field = (uint32_t *)bmp; | 57 | index XXXXXXX..XXXXXXX 100644 |
26 | + /* For the KVM GICv3, affinity routing is always enabled, and the first 8 | 58 | GIT binary patch |
27 | + * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding | 59 | literal 88 |
28 | + * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to | 60 | zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX |
29 | + * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and | 61 | I{D-Rq0Q5fy0RR91 |
30 | + * offset. | 62 | |
31 | + */ | 63 | literal 0 |
32 | + field = (uint32_t *)(bmp + GIC_INTERNAL); | 64 | HcmV?d00001 |
33 | + offset += (GIC_INTERNAL * 8) / 8; | 65 | |
34 | for_each_dist_irq_reg(irq, s->num_irq, 8) { | ||
35 | kvm_gicd_access(s, offset, ®, false); | ||
36 | *field = reg; | ||
37 | @@ -XXX,XX +XXX,XX @@ static void kvm_dist_put_priority(GICv3State *s, uint32_t offset, uint8_t *bmp) | ||
38 | uint32_t reg, *field; | ||
39 | int irq; | ||
40 | |||
41 | - field = (uint32_t *)bmp; | ||
42 | + /* For the KVM GICv3, affinity routing is always enabled, and the first 8 | ||
43 | + * GICD_IPRIORITYR<n> registers are always RAZ/WI. The corresponding | ||
44 | + * functionality is replaced by GICR_IPRIORITYR<n>. It doesn't need to | ||
45 | + * sync them. So it needs to skip the field of GIC_INTERNAL irqs in bmp and | ||
46 | + * offset. | ||
47 | + */ | ||
48 | + field = (uint32_t *)(bmp + GIC_INTERNAL); | ||
49 | + offset += (GIC_INTERNAL * 8) / 8; | ||
50 | for_each_dist_irq_reg(irq, s->num_irq, 8) { | ||
51 | reg = *field; | ||
52 | kvm_gicd_access(s, offset, ®, true); | ||
53 | -- | 66 | -- |
54 | 2.17.1 | 67 | 2.25.1 |
55 | 68 | ||
56 | 69 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The ethernet controller in the AN505 MPC FPGA image is behind | ||
2 | the same AHB Peripheral Protection Controller that handles | ||
3 | the graphics and GPIOs. (In the documentation this is clear | ||
4 | in the block diagram but the ethernet controller was omitted | ||
5 | from the table listing devices connected to the PPC.) | ||
6 | The ethernet sits behind AHB PPCEXP0 interface 5. We had | ||
7 | incorrectly claimed that this was a "gpio4", but there are | ||
8 | only 4 GPIOs in this image. | ||
9 | 1 | ||
10 | Correct the QEMU model to match the hardware. | ||
11 | |||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Message-id: 20180515171446.10834-1-peter.maydell@linaro.org | ||
15 | --- | ||
16 | hw/arm/mps2-tz.c | 32 +++++++++++++++++++++++--------- | ||
17 | 1 file changed, 23 insertions(+), 9 deletions(-) | ||
18 | |||
19 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/hw/arm/mps2-tz.c | ||
22 | +++ b/hw/arm/mps2-tz.c | ||
23 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
24 | UnimplementedDeviceState spi[5]; | ||
25 | UnimplementedDeviceState i2c[4]; | ||
26 | UnimplementedDeviceState i2s_audio; | ||
27 | - UnimplementedDeviceState gpio[5]; | ||
28 | + UnimplementedDeviceState gpio[4]; | ||
29 | UnimplementedDeviceState dma[4]; | ||
30 | UnimplementedDeviceState gfx; | ||
31 | CMSDKAPBUART uart[5]; | ||
32 | SplitIRQ sec_resp_splitter; | ||
33 | qemu_or_irq uart_irq_orgate; | ||
34 | + DeviceState *lan9118; | ||
35 | } MPS2TZMachineState; | ||
36 | |||
37 | #define TYPE_MPS2TZ_MACHINE "mps2tz" | ||
38 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, | ||
39 | return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); | ||
40 | } | ||
41 | |||
42 | +static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, | ||
43 | + const char *name, hwaddr size) | ||
44 | +{ | ||
45 | + SysBusDevice *s; | ||
46 | + DeviceState *iotkitdev = DEVICE(&mms->iotkit); | ||
47 | + NICInfo *nd = &nd_table[0]; | ||
48 | + | ||
49 | + /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
50 | + * except that it doesn't support the checksum-offload feature. | ||
51 | + */ | ||
52 | + qemu_check_nic_model(nd, "lan9118"); | ||
53 | + mms->lan9118 = qdev_create(NULL, "lan9118"); | ||
54 | + qdev_set_nic_properties(mms->lan9118, nd); | ||
55 | + qdev_init_nofail(mms->lan9118); | ||
56 | + | ||
57 | + s = SYS_BUS_DEVICE(mms->lan9118); | ||
58 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | ||
59 | + return sysbus_mmio_get_region(s, 0); | ||
60 | +} | ||
61 | + | ||
62 | static void mps2tz_common_init(MachineState *machine) | ||
63 | { | ||
64 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
65 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
66 | { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, | ||
67 | { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, | ||
68 | { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, | ||
69 | - { "gpio4", make_unimp_dev, &mms->gpio[4], 0x40104000, 0x1000 }, | ||
70 | + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, | ||
71 | }, | ||
72 | }, { | ||
73 | .name = "ahb_ppcexp1", | ||
74 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
75 | "cfg_sec_resp", 0)); | ||
76 | } | ||
77 | |||
78 | - /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
79 | - * except that it doesn't support the checksum-offload feature. | ||
80 | - * The ethernet controller is not behind a PPC. | ||
81 | - */ | ||
82 | - lan9118_init(&nd_table[0], 0x42000000, | ||
83 | - qdev_get_gpio_in_named(iotkitdev, "EXP_IRQ", 16)); | ||
84 | - | ||
85 | create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); | ||
86 | |||
87 | armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); | ||
88 | -- | ||
89 | 2.17.1 | ||
90 | |||
91 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the pflash_cfi02 device away from using the old_mmio field | ||
2 | of MemoryRegionOps. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Acked-by: Max Reitz <mreitz@redhat.com> | ||
7 | Message-id: 20180601141223.26630-4-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/block/pflash_cfi02.c | 97 ++++++++--------------------------------- | ||
10 | 1 file changed, 18 insertions(+), 79 deletions(-) | ||
11 | |||
12 | diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/block/pflash_cfi02.c | ||
15 | +++ b/hw/block/pflash_cfi02.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void pflash_write (pflash_t *pfl, hwaddr offset, | ||
17 | pfl->cmd = 0; | ||
18 | } | ||
19 | |||
20 | - | ||
21 | -static uint32_t pflash_readb_be(void *opaque, hwaddr addr) | ||
22 | +static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size) | ||
23 | { | ||
24 | - return pflash_read(opaque, addr, 1, 1); | ||
25 | + return pflash_read(opaque, addr, size, 1); | ||
26 | } | ||
27 | |||
28 | -static uint32_t pflash_readb_le(void *opaque, hwaddr addr) | ||
29 | +static void pflash_be_writefn(void *opaque, hwaddr addr, | ||
30 | + uint64_t value, unsigned size) | ||
31 | { | ||
32 | - return pflash_read(opaque, addr, 1, 0); | ||
33 | + pflash_write(opaque, addr, value, size, 1); | ||
34 | } | ||
35 | |||
36 | -static uint32_t pflash_readw_be(void *opaque, hwaddr addr) | ||
37 | +static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size) | ||
38 | { | ||
39 | - pflash_t *pfl = opaque; | ||
40 | - | ||
41 | - return pflash_read(pfl, addr, 2, 1); | ||
42 | + return pflash_read(opaque, addr, size, 0); | ||
43 | } | ||
44 | |||
45 | -static uint32_t pflash_readw_le(void *opaque, hwaddr addr) | ||
46 | +static void pflash_le_writefn(void *opaque, hwaddr addr, | ||
47 | + uint64_t value, unsigned size) | ||
48 | { | ||
49 | - pflash_t *pfl = opaque; | ||
50 | - | ||
51 | - return pflash_read(pfl, addr, 2, 0); | ||
52 | -} | ||
53 | - | ||
54 | -static uint32_t pflash_readl_be(void *opaque, hwaddr addr) | ||
55 | -{ | ||
56 | - pflash_t *pfl = opaque; | ||
57 | - | ||
58 | - return pflash_read(pfl, addr, 4, 1); | ||
59 | -} | ||
60 | - | ||
61 | -static uint32_t pflash_readl_le(void *opaque, hwaddr addr) | ||
62 | -{ | ||
63 | - pflash_t *pfl = opaque; | ||
64 | - | ||
65 | - return pflash_read(pfl, addr, 4, 0); | ||
66 | -} | ||
67 | - | ||
68 | -static void pflash_writeb_be(void *opaque, hwaddr addr, | ||
69 | - uint32_t value) | ||
70 | -{ | ||
71 | - pflash_write(opaque, addr, value, 1, 1); | ||
72 | -} | ||
73 | - | ||
74 | -static void pflash_writeb_le(void *opaque, hwaddr addr, | ||
75 | - uint32_t value) | ||
76 | -{ | ||
77 | - pflash_write(opaque, addr, value, 1, 0); | ||
78 | -} | ||
79 | - | ||
80 | -static void pflash_writew_be(void *opaque, hwaddr addr, | ||
81 | - uint32_t value) | ||
82 | -{ | ||
83 | - pflash_t *pfl = opaque; | ||
84 | - | ||
85 | - pflash_write(pfl, addr, value, 2, 1); | ||
86 | -} | ||
87 | - | ||
88 | -static void pflash_writew_le(void *opaque, hwaddr addr, | ||
89 | - uint32_t value) | ||
90 | -{ | ||
91 | - pflash_t *pfl = opaque; | ||
92 | - | ||
93 | - pflash_write(pfl, addr, value, 2, 0); | ||
94 | -} | ||
95 | - | ||
96 | -static void pflash_writel_be(void *opaque, hwaddr addr, | ||
97 | - uint32_t value) | ||
98 | -{ | ||
99 | - pflash_t *pfl = opaque; | ||
100 | - | ||
101 | - pflash_write(pfl, addr, value, 4, 1); | ||
102 | -} | ||
103 | - | ||
104 | -static void pflash_writel_le(void *opaque, hwaddr addr, | ||
105 | - uint32_t value) | ||
106 | -{ | ||
107 | - pflash_t *pfl = opaque; | ||
108 | - | ||
109 | - pflash_write(pfl, addr, value, 4, 0); | ||
110 | + pflash_write(opaque, addr, value, size, 0); | ||
111 | } | ||
112 | |||
113 | static const MemoryRegionOps pflash_cfi02_ops_be = { | ||
114 | - .old_mmio = { | ||
115 | - .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, | ||
116 | - .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, | ||
117 | - }, | ||
118 | + .read = pflash_be_readfn, | ||
119 | + .write = pflash_be_writefn, | ||
120 | + .valid.min_access_size = 1, | ||
121 | + .valid.max_access_size = 4, | ||
122 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
123 | }; | ||
124 | |||
125 | static const MemoryRegionOps pflash_cfi02_ops_le = { | ||
126 | - .old_mmio = { | ||
127 | - .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, | ||
128 | - .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, | ||
129 | - }, | ||
130 | + .read = pflash_le_readfn, | ||
131 | + .write = pflash_le_writefn, | ||
132 | + .valid.min_access_size = 1, | ||
133 | + .valid.max_access_size = 4, | ||
134 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
135 | }; | ||
136 | |||
137 | -- | ||
138 | 2.17.1 | ||
139 | |||
140 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the wdt_i6300esb device away from using the old_mmio field | ||
2 | of MemoryRegionOps. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Message-id: 20180601141223.26630-5-peter.maydell@linaro.org | ||
7 | --- | ||
8 | hw/watchdog/wdt_i6300esb.c | 48 ++++++++++++++++++++++++++++---------- | ||
9 | 1 file changed, 36 insertions(+), 12 deletions(-) | ||
10 | |||
11 | diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/watchdog/wdt_i6300esb.c | ||
14 | +++ b/hw/watchdog/wdt_i6300esb.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static void i6300esb_mem_writel(void *vp, hwaddr addr, uint32_t val) | ||
16 | } | ||
17 | } | ||
18 | |||
19 | +static uint64_t i6300esb_mem_readfn(void *opaque, hwaddr addr, unsigned size) | ||
20 | +{ | ||
21 | + switch (size) { | ||
22 | + case 1: | ||
23 | + return i6300esb_mem_readb(opaque, addr); | ||
24 | + case 2: | ||
25 | + return i6300esb_mem_readw(opaque, addr); | ||
26 | + case 4: | ||
27 | + return i6300esb_mem_readl(opaque, addr); | ||
28 | + default: | ||
29 | + g_assert_not_reached(); | ||
30 | + } | ||
31 | +} | ||
32 | + | ||
33 | +static void i6300esb_mem_writefn(void *opaque, hwaddr addr, | ||
34 | + uint64_t value, unsigned size) | ||
35 | +{ | ||
36 | + switch (size) { | ||
37 | + case 1: | ||
38 | + i6300esb_mem_writeb(opaque, addr, value); | ||
39 | + break; | ||
40 | + case 2: | ||
41 | + i6300esb_mem_writew(opaque, addr, value); | ||
42 | + break; | ||
43 | + case 4: | ||
44 | + i6300esb_mem_writel(opaque, addr, value); | ||
45 | + break; | ||
46 | + default: | ||
47 | + g_assert_not_reached(); | ||
48 | + } | ||
49 | +} | ||
50 | + | ||
51 | static const MemoryRegionOps i6300esb_ops = { | ||
52 | - .old_mmio = { | ||
53 | - .read = { | ||
54 | - i6300esb_mem_readb, | ||
55 | - i6300esb_mem_readw, | ||
56 | - i6300esb_mem_readl, | ||
57 | - }, | ||
58 | - .write = { | ||
59 | - i6300esb_mem_writeb, | ||
60 | - i6300esb_mem_writew, | ||
61 | - i6300esb_mem_writel, | ||
62 | - }, | ||
63 | - }, | ||
64 | + .read = i6300esb_mem_readfn, | ||
65 | + .write = i6300esb_mem_writefn, | ||
66 | + .valid.min_access_size = 1, | ||
67 | + .valid.max_access_size = 4, | ||
68 | .endianness = DEVICE_LITTLE_ENDIAN, | ||
69 | }; | ||
70 | |||
71 | -- | ||
72 | 2.17.1 | ||
73 | |||
74 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the pckbd device away from using the old_mmio field | ||
2 | of MemoryRegionOps. This change only affects the memory-mapped | ||
3 | variant of the i8042, which is used by the Unicore32 'puv3' | ||
4 | board and the MIPS Jazz boards 'magnum' and 'pica61'. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Message-id: 20180601141223.26630-6-peter.maydell@linaro.org | ||
9 | --- | ||
10 | hw/input/pckbd.c | 14 ++++++++------ | ||
11 | 1 file changed, 8 insertions(+), 6 deletions(-) | ||
12 | |||
13 | diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/hw/input/pckbd.c | ||
16 | +++ b/hw/input/pckbd.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_kbd = { | ||
18 | }; | ||
19 | |||
20 | /* Memory mapped interface */ | ||
21 | -static uint32_t kbd_mm_readb (void *opaque, hwaddr addr) | ||
22 | +static uint64_t kbd_mm_readfn(void *opaque, hwaddr addr, unsigned size) | ||
23 | { | ||
24 | KBDState *s = opaque; | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ static uint32_t kbd_mm_readb (void *opaque, hwaddr addr) | ||
27 | return kbd_read_data(s, 0, 1) & 0xff; | ||
28 | } | ||
29 | |||
30 | -static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value) | ||
31 | +static void kbd_mm_writefn(void *opaque, hwaddr addr, | ||
32 | + uint64_t value, unsigned size) | ||
33 | { | ||
34 | KBDState *s = opaque; | ||
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value) | ||
37 | kbd_write_data(s, 0, value & 0xff, 1); | ||
38 | } | ||
39 | |||
40 | + | ||
41 | static const MemoryRegionOps i8042_mmio_ops = { | ||
42 | + .read = kbd_mm_readfn, | ||
43 | + .write = kbd_mm_writefn, | ||
44 | + .valid.min_access_size = 1, | ||
45 | + .valid.max_access_size = 4, | ||
46 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
47 | - .old_mmio = { | ||
48 | - .read = { kbd_mm_readb, kbd_mm_readb, kbd_mm_readb }, | ||
49 | - .write = { kbd_mm_writeb, kbd_mm_writeb, kbd_mm_writeb }, | ||
50 | - }, | ||
51 | }; | ||
52 | |||
53 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, | ||
54 | -- | ||
55 | 2.17.1 | ||
56 | |||
57 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the parallel device away from using the old_mmio field | ||
2 | of MemoryRegionOps. This change only affects the memory-mapped | ||
3 | variant, which is used by the MIPS Jazz boards 'magnum' and 'pica61'. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
7 | Message-id: 20180601141223.26630-7-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/char/parallel.c | 50 ++++++++++------------------------------------ | ||
10 | 1 file changed, 11 insertions(+), 39 deletions(-) | ||
11 | |||
12 | diff --git a/hw/char/parallel.c b/hw/char/parallel.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/char/parallel.c | ||
15 | +++ b/hw/char/parallel.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void parallel_isa_realizefn(DeviceState *dev, Error **errp) | ||
17 | } | ||
18 | |||
19 | /* Memory mapped interface */ | ||
20 | -static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) | ||
21 | +static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) | ||
22 | { | ||
23 | ParallelState *s = opaque; | ||
24 | |||
25 | - return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; | ||
26 | + return parallel_ioport_read_sw(s, addr >> s->it_shift) & | ||
27 | + MAKE_64BIT_MASK(0, size * 8); | ||
28 | } | ||
29 | |||
30 | -static void parallel_mm_writeb (void *opaque, | ||
31 | - hwaddr addr, uint32_t value) | ||
32 | +static void parallel_mm_writefn(void *opaque, hwaddr addr, | ||
33 | + uint64_t value, unsigned size) | ||
34 | { | ||
35 | ParallelState *s = opaque; | ||
36 | |||
37 | - parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); | ||
38 | -} | ||
39 | - | ||
40 | -static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) | ||
41 | -{ | ||
42 | - ParallelState *s = opaque; | ||
43 | - | ||
44 | - return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; | ||
45 | -} | ||
46 | - | ||
47 | -static void parallel_mm_writew (void *opaque, | ||
48 | - hwaddr addr, uint32_t value) | ||
49 | -{ | ||
50 | - ParallelState *s = opaque; | ||
51 | - | ||
52 | - parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); | ||
53 | -} | ||
54 | - | ||
55 | -static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) | ||
56 | -{ | ||
57 | - ParallelState *s = opaque; | ||
58 | - | ||
59 | - return parallel_ioport_read_sw(s, addr >> s->it_shift); | ||
60 | -} | ||
61 | - | ||
62 | -static void parallel_mm_writel (void *opaque, | ||
63 | - hwaddr addr, uint32_t value) | ||
64 | -{ | ||
65 | - ParallelState *s = opaque; | ||
66 | - | ||
67 | - parallel_ioport_write_sw(s, addr >> s->it_shift, value); | ||
68 | + parallel_ioport_write_sw(s, addr >> s->it_shift, | ||
69 | + value & MAKE_64BIT_MASK(0, size * 8)); | ||
70 | } | ||
71 | |||
72 | static const MemoryRegionOps parallel_mm_ops = { | ||
73 | - .old_mmio = { | ||
74 | - .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, | ||
75 | - .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, | ||
76 | - }, | ||
77 | + .read = parallel_mm_readfn, | ||
78 | + .write = parallel_mm_writefn, | ||
79 | + .valid.min_access_size = 1, | ||
80 | + .valid.max_access_size = 4, | ||
81 | .endianness = DEVICE_NATIVE_ENDIAN, | ||
82 | }; | ||
83 | |||
84 | -- | ||
85 | 2.17.1 | ||
86 | |||
87 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Remove the now-unused armv7m_init() function. This was a legacy from | ||
2 | before we properly QOMified ARMv7M, and it has some flaws: | ||
3 | 1 | ||
4 | * it combines work that needs to be done by an SoC object (creating | ||
5 | and initializing the TYPE_ARMV7M object) with work that needs to | ||
6 | be done by the board model (setting the system up to load the ELF | ||
7 | file specified with -kernel) | ||
8 | * TYPE_ARMV7M creation failure is fatal, but an SoC object wants to | ||
9 | arrange to propagate the failure outward | ||
10 | * it uses allocate-and-create via qdev_create() whereas the current | ||
11 | preferred style for SoC objects is to do creation in-place | ||
12 | |||
13 | Board and SoC models can instead do the two jobs this function | ||
14 | was doing themselves, in the right places and with whatever their | ||
15 | preferred style/error handling is. | ||
16 | |||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
19 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
20 | Message-id: 20180601144328.23817-3-peter.maydell@linaro.org | ||
21 | --- | ||
22 | include/hw/arm/arm.h | 8 ++------ | ||
23 | hw/arm/armv7m.c | 21 --------------------- | ||
24 | 2 files changed, 2 insertions(+), 27 deletions(-) | ||
25 | |||
26 | diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/include/hw/arm/arm.h | ||
29 | +++ b/include/hw/arm/arm.h | ||
30 | @@ -XXX,XX +XXX,XX @@ typedef enum { | ||
31 | ARM_ENDIANNESS_BE32, | ||
32 | } arm_endianness; | ||
33 | |||
34 | -/* armv7m.c */ | ||
35 | -DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, | ||
36 | - const char *kernel_filename, const char *cpu_type); | ||
37 | /** | ||
38 | * armv7m_load_kernel: | ||
39 | * @cpu: CPU | ||
40 | @@ -XXX,XX +XXX,XX @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, | ||
41 | * @mem_size: mem_size: maximum image size to load | ||
42 | * | ||
43 | * Load the guest image for an ARMv7M system. This must be called by | ||
44 | - * any ARMv7M board, either directly or via armv7m_init(). (This is | ||
45 | - * necessary to ensure that the CPU resets correctly on system reset, | ||
46 | - * as well as for kernel loading.) | ||
47 | + * any ARMv7M board. (This is necessary to ensure that the CPU resets | ||
48 | + * correctly on system reset, as well as for kernel loading.) | ||
49 | */ | ||
50 | void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size); | ||
51 | |||
52 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/hw/arm/armv7m.c | ||
55 | +++ b/hw/arm/armv7m.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void armv7m_reset(void *opaque) | ||
57 | cpu_reset(CPU(cpu)); | ||
58 | } | ||
59 | |||
60 | -/* Init CPU and memory for a v7-M based board. | ||
61 | - mem_size is in bytes. | ||
62 | - Returns the ARMv7M device. */ | ||
63 | - | ||
64 | -DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, | ||
65 | - const char *kernel_filename, const char *cpu_type) | ||
66 | -{ | ||
67 | - DeviceState *armv7m; | ||
68 | - | ||
69 | - armv7m = qdev_create(NULL, TYPE_ARMV7M); | ||
70 | - qdev_prop_set_uint32(armv7m, "num-irq", num_irq); | ||
71 | - qdev_prop_set_string(armv7m, "cpu-type", cpu_type); | ||
72 | - object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()), | ||
73 | - "memory", &error_abort); | ||
74 | - /* This will exit with an error if the user passed us a bad cpu_type */ | ||
75 | - qdev_init_nofail(armv7m); | ||
76 | - | ||
77 | - armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size); | ||
78 | - return armv7m; | ||
79 | -} | ||
80 | - | ||
81 | void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) | ||
82 | { | ||
83 | int image_size; | ||
84 | -- | ||
85 | 2.17.1 | ||
86 | |||
87 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | For the IoTKit MPC support, we need to wire together the | ||
2 | interrupt outputs of 17 MPCs; this exceeds the current | ||
3 | value of MAX_OR_LINES. Increase MAX_OR_LINES to 32 (which | ||
4 | should be enough for anyone). | ||
5 | 1 | ||
6 | The tricky part is retaining the migration compatibility for | ||
7 | existing OR gates; we add a subsection which is only used | ||
8 | for larger OR gates, and define it such that we can freely | ||
9 | increase MAX_OR_LINES in future (or even move to a dynamically | ||
10 | allocated levels[] array without an upper size limit) without | ||
11 | breaking compatibility. | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
15 | Message-id: 20180604152941.20374-10-peter.maydell@linaro.org | ||
16 | --- | ||
17 | include/hw/or-irq.h | 5 ++++- | ||
18 | hw/core/or-irq.c | 39 +++++++++++++++++++++++++++++++++++++-- | ||
19 | 2 files changed, 41 insertions(+), 3 deletions(-) | ||
20 | |||
21 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/include/hw/or-irq.h | ||
24 | +++ b/include/hw/or-irq.h | ||
25 | @@ -XXX,XX +XXX,XX @@ | ||
26 | |||
27 | #define TYPE_OR_IRQ "or-irq" | ||
28 | |||
29 | -#define MAX_OR_LINES 16 | ||
30 | +/* This can safely be increased if necessary without breaking | ||
31 | + * migration compatibility (as long as it remains greater than 15). | ||
32 | + */ | ||
33 | +#define MAX_OR_LINES 32 | ||
34 | |||
35 | typedef struct OrIRQState qemu_or_irq; | ||
36 | |||
37 | diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/hw/core/or-irq.c | ||
40 | +++ b/hw/core/or-irq.c | ||
41 | @@ -XXX,XX +XXX,XX @@ static void or_irq_init(Object *obj) | ||
42 | qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1); | ||
43 | } | ||
44 | |||
45 | +/* The original version of this device had a fixed 16 entries in its | ||
46 | + * VMState array; devices with more inputs than this need to | ||
47 | + * migrate the extra lines via a subsection. | ||
48 | + * The subsection migrates as much of the levels[] array as is needed | ||
49 | + * (including repeating the first 16 elements), to avoid the awkwardness | ||
50 | + * of splitting it in two to meet the requirements of VMSTATE_VARRAY_UINT16. | ||
51 | + */ | ||
52 | +#define OLD_MAX_OR_LINES 16 | ||
53 | +#if MAX_OR_LINES < OLD_MAX_OR_LINES | ||
54 | +#error MAX_OR_LINES must be at least 16 for migration compatibility | ||
55 | +#endif | ||
56 | + | ||
57 | +static bool vmstate_extras_needed(void *opaque) | ||
58 | +{ | ||
59 | + qemu_or_irq *s = OR_IRQ(opaque); | ||
60 | + | ||
61 | + return s->num_lines >= OLD_MAX_OR_LINES; | ||
62 | +} | ||
63 | + | ||
64 | +static const VMStateDescription vmstate_or_irq_extras = { | ||
65 | + .name = "or-irq-extras", | ||
66 | + .version_id = 1, | ||
67 | + .minimum_version_id = 1, | ||
68 | + .needed = vmstate_extras_needed, | ||
69 | + .fields = (VMStateField[]) { | ||
70 | + VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0, | ||
71 | + vmstate_info_bool, bool), | ||
72 | + VMSTATE_END_OF_LIST(), | ||
73 | + }, | ||
74 | +}; | ||
75 | + | ||
76 | static const VMStateDescription vmstate_or_irq = { | ||
77 | .name = TYPE_OR_IRQ, | ||
78 | .version_id = 1, | ||
79 | .minimum_version_id = 1, | ||
80 | .fields = (VMStateField[]) { | ||
81 | - VMSTATE_BOOL_ARRAY(levels, qemu_or_irq, MAX_OR_LINES), | ||
82 | + VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES), | ||
83 | VMSTATE_END_OF_LIST(), | ||
84 | - } | ||
85 | + }, | ||
86 | + .subsections = (const VMStateDescription*[]) { | ||
87 | + &vmstate_or_irq_extras, | ||
88 | + NULL | ||
89 | + }, | ||
90 | }; | ||
91 | |||
92 | static Property or_irq_properties[] = { | ||
93 | -- | ||
94 | 2.17.1 | ||
95 | |||
96 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The API for cpu_transaction_failed() says that it takes the physical | ||
2 | address for the failed transaction. However we were actually passing | ||
3 | it the offset within the target MemoryRegion. We don't currently | ||
4 | have any target CPU implementations of this hook that require the | ||
5 | physical address; fix this bug so we don't get confused if we ever | ||
6 | do add one. | ||
7 | 1 | ||
8 | Suggested-by: Paolo Bonzini <pbonzini@redhat.com> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20180611125633.32755-3-peter.maydell@linaro.org | ||
13 | --- | ||
14 | include/exec/exec-all.h | 13 ++++++++++-- | ||
15 | accel/tcg/cputlb.c | 44 +++++++++++++++++++++++++++++------------ | ||
16 | exec.c | 5 +++-- | ||
17 | 3 files changed, 45 insertions(+), 17 deletions(-) | ||
18 | |||
19 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/exec/exec-all.h | ||
22 | +++ b/include/exec/exec-all.h | ||
23 | @@ -XXX,XX +XXX,XX @@ void tb_lock_reset(void); | ||
24 | |||
25 | #if !defined(CONFIG_USER_ONLY) | ||
26 | |||
27 | -struct MemoryRegion *iotlb_to_region(CPUState *cpu, | ||
28 | - hwaddr index, MemTxAttrs attrs); | ||
29 | +/** | ||
30 | + * iotlb_to_section: | ||
31 | + * @cpu: CPU performing the access | ||
32 | + * @index: TCG CPU IOTLB entry | ||
33 | + * | ||
34 | + * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that | ||
35 | + * it refers to. @index will have been initially created and returned | ||
36 | + * by memory_region_section_get_iotlb(). | ||
37 | + */ | ||
38 | +struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, | ||
39 | + hwaddr index, MemTxAttrs attrs); | ||
40 | |||
41 | void tlb_fill(CPUState *cpu, target_ulong addr, int size, | ||
42 | MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); | ||
43 | diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/accel/tcg/cputlb.c | ||
46 | +++ b/accel/tcg/cputlb.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
48 | target_ulong addr, uintptr_t retaddr, int size) | ||
49 | { | ||
50 | CPUState *cpu = ENV_GET_CPU(env); | ||
51 | - hwaddr physaddr = iotlbentry->addr; | ||
52 | - MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs); | ||
53 | + hwaddr mr_offset; | ||
54 | + MemoryRegionSection *section; | ||
55 | + MemoryRegion *mr; | ||
56 | uint64_t val; | ||
57 | bool locked = false; | ||
58 | MemTxResult r; | ||
59 | |||
60 | - physaddr = (physaddr & TARGET_PAGE_MASK) + addr; | ||
61 | + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); | ||
62 | + mr = section->mr; | ||
63 | + mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
64 | cpu->mem_io_pc = retaddr; | ||
65 | if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { | ||
66 | cpu_io_recompile(cpu, retaddr); | ||
67 | @@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
68 | qemu_mutex_lock_iothread(); | ||
69 | locked = true; | ||
70 | } | ||
71 | - r = memory_region_dispatch_read(mr, physaddr, | ||
72 | + r = memory_region_dispatch_read(mr, mr_offset, | ||
73 | &val, size, iotlbentry->attrs); | ||
74 | if (r != MEMTX_OK) { | ||
75 | + hwaddr physaddr = mr_offset + | ||
76 | + section->offset_within_address_space - | ||
77 | + section->offset_within_region; | ||
78 | + | ||
79 | cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD, | ||
80 | mmu_idx, iotlbentry->attrs, r, retaddr); | ||
81 | } | ||
82 | @@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
83 | uintptr_t retaddr, int size) | ||
84 | { | ||
85 | CPUState *cpu = ENV_GET_CPU(env); | ||
86 | - hwaddr physaddr = iotlbentry->addr; | ||
87 | - MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs); | ||
88 | + hwaddr mr_offset; | ||
89 | + MemoryRegionSection *section; | ||
90 | + MemoryRegion *mr; | ||
91 | bool locked = false; | ||
92 | MemTxResult r; | ||
93 | |||
94 | - physaddr = (physaddr & TARGET_PAGE_MASK) + addr; | ||
95 | + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); | ||
96 | + mr = section->mr; | ||
97 | + mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
98 | if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) { | ||
99 | cpu_io_recompile(cpu, retaddr); | ||
100 | } | ||
101 | @@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, | ||
102 | qemu_mutex_lock_iothread(); | ||
103 | locked = true; | ||
104 | } | ||
105 | - r = memory_region_dispatch_write(mr, physaddr, | ||
106 | + r = memory_region_dispatch_write(mr, mr_offset, | ||
107 | val, size, iotlbentry->attrs); | ||
108 | if (r != MEMTX_OK) { | ||
109 | + hwaddr physaddr = mr_offset + | ||
110 | + section->offset_within_address_space - | ||
111 | + section->offset_within_region; | ||
112 | + | ||
113 | cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, | ||
114 | mmu_idx, iotlbentry->attrs, r, retaddr); | ||
115 | } | ||
116 | @@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, | ||
117 | */ | ||
118 | tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) | ||
119 | { | ||
120 | - int mmu_idx, index, pd; | ||
121 | + int mmu_idx, index; | ||
122 | void *p; | ||
123 | MemoryRegion *mr; | ||
124 | + MemoryRegionSection *section; | ||
125 | CPUState *cpu = ENV_GET_CPU(env); | ||
126 | CPUIOTLBEntry *iotlbentry; | ||
127 | - hwaddr physaddr; | ||
128 | + hwaddr physaddr, mr_offset; | ||
129 | |||
130 | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); | ||
131 | mmu_idx = cpu_mmu_index(env, true); | ||
132 | @@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) | ||
133 | } | ||
134 | } | ||
135 | iotlbentry = &env->iotlb[mmu_idx][index]; | ||
136 | - pd = iotlbentry->addr & ~TARGET_PAGE_MASK; | ||
137 | - mr = iotlb_to_region(cpu, pd, iotlbentry->attrs); | ||
138 | + section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs); | ||
139 | + mr = section->mr; | ||
140 | if (memory_region_is_unassigned(mr)) { | ||
141 | qemu_mutex_lock_iothread(); | ||
142 | if (memory_region_request_mmio_ptr(mr, addr)) { | ||
143 | @@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr) | ||
144 | * and use the MemTXResult it produced). However it is the | ||
145 | * simplest place we have currently available for the check. | ||
146 | */ | ||
147 | - physaddr = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
148 | + mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr; | ||
149 | + physaddr = mr_offset + | ||
150 | + section->offset_within_address_space - | ||
151 | + section->offset_within_region; | ||
152 | cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu_idx, | ||
153 | iotlbentry->attrs, MEMTX_DECODE_ERROR, 0); | ||
154 | |||
155 | diff --git a/exec.c b/exec.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/exec.c | ||
158 | +++ b/exec.c | ||
159 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps readonly_mem_ops = { | ||
160 | }, | ||
161 | }; | ||
162 | |||
163 | -MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs) | ||
164 | +MemoryRegionSection *iotlb_to_section(CPUState *cpu, | ||
165 | + hwaddr index, MemTxAttrs attrs) | ||
166 | { | ||
167 | int asidx = cpu_asidx_from_attrs(cpu, attrs); | ||
168 | CPUAddressSpace *cpuas = &cpu->cpu_ases[asidx]; | ||
169 | AddressSpaceDispatch *d = atomic_rcu_read(&cpuas->memory_dispatch); | ||
170 | MemoryRegionSection *sections = d->map.sections; | ||
171 | |||
172 | - return sections[index & ~TARGET_PAGE_MASK].mr; | ||
173 | + return §ions[index & ~TARGET_PAGE_MASK]; | ||
174 | } | ||
175 | |||
176 | static void io_mem_init(void) | ||
177 | -- | ||
178 | 2.17.1 | ||
179 | |||
180 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The codebase has a bit of a mix of different multiline | ||
2 | comment styles. State a preference for the Linux kernel | ||
3 | style: | ||
4 | /* | ||
5 | * Star on the left for each line. | ||
6 | * Leading slash-star and trailing star-slash | ||
7 | * each go on a line of their own. | ||
8 | */ | ||
9 | 1 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Eric Blake <eblake@redhat.com> | ||
12 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
13 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
14 | Reviewed-by: Alex Williamson <alex.williamson@redhat.com> | ||
15 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
16 | Reviewed-by: John Snow <jsnow@redhat.com> | ||
17 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
18 | Message-id: 20180611141716.3813-1-peter.maydell@linaro.org | ||
19 | --- | ||
20 | CODING_STYLE | 17 +++++++++++++++++ | ||
21 | 1 file changed, 17 insertions(+) | ||
22 | |||
23 | diff --git a/CODING_STYLE b/CODING_STYLE | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/CODING_STYLE | ||
26 | +++ b/CODING_STYLE | ||
27 | @@ -XXX,XX +XXX,XX @@ We use traditional C-style /* */ comments and avoid // comments. | ||
28 | Rationale: The // form is valid in C99, so this is purely a matter of | ||
29 | consistency of style. The checkpatch script will warn you about this. | ||
30 | |||
31 | +Multiline comment blocks should have a row of stars on the left, | ||
32 | +and the initial /* and terminating */ both on their own lines: | ||
33 | + /* | ||
34 | + * like | ||
35 | + * this | ||
36 | + */ | ||
37 | +This is the same format required by the Linux kernel coding style. | ||
38 | + | ||
39 | +(Some of the existing comments in the codebase use the GNU Coding | ||
40 | +Standards form which does not have stars on the left, or other | ||
41 | +variations; avoid these when writing new comments, but don't worry | ||
42 | +about converting to the preferred form unless you're editing that | ||
43 | +comment anyway.) | ||
44 | + | ||
45 | +Rationale: Consistency, and ease of visually picking out a multiline | ||
46 | +comment from the surrounding code. | ||
47 | + | ||
48 | 8. trace-events style | ||
49 | |||
50 | 8.1 0x prefix | ||
51 | -- | ||
52 | 2.17.1 | ||
53 | |||
54 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Now we have stn_p() and ldn_p() we can use them in various | ||
2 | functions in exec.c that used to have their own switch-on-size code. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20180611171007.4165-4-peter.maydell@linaro.org | ||
8 | --- | ||
9 | exec.c | 112 +++++---------------------------------------------------- | ||
10 | 1 file changed, 8 insertions(+), 104 deletions(-) | ||
11 | |||
12 | diff --git a/exec.c b/exec.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/exec.c | ||
15 | +++ b/exec.c | ||
16 | @@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | ||
17 | memory_notdirty_write_prepare(&ndi, current_cpu, current_cpu->mem_io_vaddr, | ||
18 | ram_addr, size); | ||
19 | |||
20 | - switch (size) { | ||
21 | - case 1: | ||
22 | - stb_p(qemu_map_ram_ptr(NULL, ram_addr), val); | ||
23 | - break; | ||
24 | - case 2: | ||
25 | - stw_p(qemu_map_ram_ptr(NULL, ram_addr), val); | ||
26 | - break; | ||
27 | - case 4: | ||
28 | - stl_p(qemu_map_ram_ptr(NULL, ram_addr), val); | ||
29 | - break; | ||
30 | - case 8: | ||
31 | - stq_p(qemu_map_ram_ptr(NULL, ram_addr), val); | ||
32 | - break; | ||
33 | - default: | ||
34 | - abort(); | ||
35 | - } | ||
36 | + stn_p(qemu_map_ram_ptr(NULL, ram_addr), size, val); | ||
37 | memory_notdirty_write_complete(&ndi); | ||
38 | } | ||
39 | |||
40 | @@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, | ||
41 | if (res) { | ||
42 | return res; | ||
43 | } | ||
44 | - switch (len) { | ||
45 | - case 1: | ||
46 | - *data = ldub_p(buf); | ||
47 | - return MEMTX_OK; | ||
48 | - case 2: | ||
49 | - *data = lduw_p(buf); | ||
50 | - return MEMTX_OK; | ||
51 | - case 4: | ||
52 | - *data = (uint32_t)ldl_p(buf); | ||
53 | - return MEMTX_OK; | ||
54 | - case 8: | ||
55 | - *data = ldq_p(buf); | ||
56 | - return MEMTX_OK; | ||
57 | - default: | ||
58 | - abort(); | ||
59 | - } | ||
60 | + *data = ldn_p(buf, len); | ||
61 | + return MEMTX_OK; | ||
62 | } | ||
63 | |||
64 | static MemTxResult subpage_write(void *opaque, hwaddr addr, | ||
65 | @@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, | ||
66 | " value %"PRIx64"\n", | ||
67 | __func__, subpage, len, addr, value); | ||
68 | #endif | ||
69 | - switch (len) { | ||
70 | - case 1: | ||
71 | - stb_p(buf, value); | ||
72 | - break; | ||
73 | - case 2: | ||
74 | - stw_p(buf, value); | ||
75 | - break; | ||
76 | - case 4: | ||
77 | - stl_p(buf, value); | ||
78 | - break; | ||
79 | - case 8: | ||
80 | - stq_p(buf, value); | ||
81 | - break; | ||
82 | - default: | ||
83 | - abort(); | ||
84 | - } | ||
85 | + stn_p(buf, len, value); | ||
86 | return flatview_write(subpage->fv, addr + subpage->base, attrs, buf, len); | ||
87 | } | ||
88 | |||
89 | @@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, | ||
90 | l = memory_access_size(mr, l, addr1); | ||
91 | /* XXX: could force current_cpu to NULL to avoid | ||
92 | potential bugs */ | ||
93 | - switch (l) { | ||
94 | - case 8: | ||
95 | - /* 64 bit write access */ | ||
96 | - val = ldq_p(buf); | ||
97 | - result |= memory_region_dispatch_write(mr, addr1, val, 8, | ||
98 | - attrs); | ||
99 | - break; | ||
100 | - case 4: | ||
101 | - /* 32 bit write access */ | ||
102 | - val = (uint32_t)ldl_p(buf); | ||
103 | - result |= memory_region_dispatch_write(mr, addr1, val, 4, | ||
104 | - attrs); | ||
105 | - break; | ||
106 | - case 2: | ||
107 | - /* 16 bit write access */ | ||
108 | - val = lduw_p(buf); | ||
109 | - result |= memory_region_dispatch_write(mr, addr1, val, 2, | ||
110 | - attrs); | ||
111 | - break; | ||
112 | - case 1: | ||
113 | - /* 8 bit write access */ | ||
114 | - val = ldub_p(buf); | ||
115 | - result |= memory_region_dispatch_write(mr, addr1, val, 1, | ||
116 | - attrs); | ||
117 | - break; | ||
118 | - default: | ||
119 | - abort(); | ||
120 | - } | ||
121 | + val = ldn_p(buf, l); | ||
122 | + result |= memory_region_dispatch_write(mr, addr1, val, l, attrs); | ||
123 | } else { | ||
124 | /* RAM case */ | ||
125 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); | ||
126 | @@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, | ||
127 | /* I/O case */ | ||
128 | release_lock |= prepare_mmio_access(mr); | ||
129 | l = memory_access_size(mr, l, addr1); | ||
130 | - switch (l) { | ||
131 | - case 8: | ||
132 | - /* 64 bit read access */ | ||
133 | - result |= memory_region_dispatch_read(mr, addr1, &val, 8, | ||
134 | - attrs); | ||
135 | - stq_p(buf, val); | ||
136 | - break; | ||
137 | - case 4: | ||
138 | - /* 32 bit read access */ | ||
139 | - result |= memory_region_dispatch_read(mr, addr1, &val, 4, | ||
140 | - attrs); | ||
141 | - stl_p(buf, val); | ||
142 | - break; | ||
143 | - case 2: | ||
144 | - /* 16 bit read access */ | ||
145 | - result |= memory_region_dispatch_read(mr, addr1, &val, 2, | ||
146 | - attrs); | ||
147 | - stw_p(buf, val); | ||
148 | - break; | ||
149 | - case 1: | ||
150 | - /* 8 bit read access */ | ||
151 | - result |= memory_region_dispatch_read(mr, addr1, &val, 1, | ||
152 | - attrs); | ||
153 | - stb_p(buf, val); | ||
154 | - break; | ||
155 | - default: | ||
156 | - abort(); | ||
157 | - } | ||
158 | + result |= memory_region_dispatch_read(mr, addr1, &val, l, attrs); | ||
159 | + stn_p(buf, l, val); | ||
160 | } else { | ||
161 | /* RAM case */ | ||
162 | ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); | ||
163 | -- | ||
164 | 2.17.1 | ||
165 | |||
166 | diff view generated by jsdifflib |