[Qemu-devel] [PULL 00/31] target-arm queue
[PULL 00/24] target-arm queue
1
target-arm queue: aspeed patches from Cédric, and
1
The following changes since commit 5a67d7735d4162630769ef495cf813244fc850df:
2
cleanup and sd card patches from Philippe.
3
2
4
thanks
3
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/tls-deps-pull-request' into staging (2021-07-02 08:22:39 +0100)
5
-- PMM
6
7
The following changes since commit bac5ba3dc5da706f52c149fa6c0bd1dc96899bec:
8
9
Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging (2018-06-08 10:26:16 +0100)
10
4
11
are available in the Git repository at:
5
are available in the Git repository at:
12
6
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180608
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210702
14
8
15
for you to fetch changes up to 113f31c06c6bf16451892b2459d83c9b9c5e9844:
9
for you to fetch changes up to 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8:
16
10
17
sdcard: Disable CMD19/CMD23 for Spec v2 (2018-06-08 13:15:34 +0100)
11
target/arm: Implement MVE shifts by register (2021-07-02 11:48:38 +0100)
18
12
19
----------------------------------------------------------------
13
----------------------------------------------------------------
20
target-arm queue:
14
target-arm queue:
21
* arm_gicv3_kvm: fix migration of registers corresponding to
15
* more MVE instructions
22
IRQs 992 to 1020 in the KVM GIC
16
* hw/gpio/gpio_pwr: use shutdown function for reboot
23
* aspeed: remove ignore_memory_transaction_failures on all boards
17
* target/arm: Check NaN mode before silencing NaN
24
* aspeed: add support for the witherspoon-bmc board
18
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
25
* aspeed: add an I2C RTC device and EEPROM I2C devices
19
* hw/arm: Add basic power management to raspi.
26
* aspeed: add the pc9552 chips to the witherspoon machine
20
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
27
* ftgmac100: fix various bugs
28
* hw/arm: Remove the deprecated xlnx-ep108 machine
29
* hw/i2c: Add trace events
30
* add missing '\n' on various qemu_log() logging strings
31
* sdcard: clean up spec version support so we report the
32
right spec version to the guest and only implement the
33
commands that are supposed to be present in that version
34
21
35
----------------------------------------------------------------
22
----------------------------------------------------------------
36
Cédric Le Goater (11):
23
Joe Komlodi (1):
37
aspeed: remove ignore_memory_transaction_failures on all boards
24
target/arm: Check NaN mode before silencing NaN
38
aspeed: add support for the witherspoon-bmc board
39
aspeed: add an I2C RTC device to all machines
40
smbus: add a smbus_eeprom_init_one() routine
41
aspeed: Add EEPROM I2C devices
42
misc: add pca9552 LED blinker model
43
aspeed: add the pc9552 chips to the witherspoon machine
44
ftgmac100: compute maximum frame size depending on the protocol
45
ftgmac100: add IEEE 802.1Q VLAN support
46
ftgmac100: fix multicast hash routine
47
ftgmac100: remove check on runt messages
48
25
49
Philippe Mathieu-Daudé (18):
26
Maxim Uvarov (1):
50
hw/i2c: Add trace events
27
hw/gpio/gpio_pwr: use shutdown function for reboot
51
hw/sd/milkymist-memcard: Add trailing '\n' to qemu_log() call
52
hw/digic: Add trailing '\n' to qemu_log() calls
53
xilinx-dp: Add trailing '\n' to qemu_log() call
54
ppc/pnv: Add trailing '\n' to qemu_log() calls
55
hw/core/register: Add trailing '\n' to qemu_log() call
56
hw/mips/boston: Add trailing '\n' to qemu_log() calls
57
stellaris: Add trailing '\n' to qemu_log() calls
58
target/arm: Add trailing '\n' to qemu_log() calls
59
target/m68k: Add trailing '\n' to qemu_log() call
60
RISC-V: Add trailing '\n' to qemu_log() calls
61
target/xtensa: Add trailing '\n' to qemu_log() calls
62
sdcard: Update the Configuration Register (SCR) to Spec Version 1.10
63
sdcard: Allow commands valid in SPI mode
64
sdcard: Add a 'spec_version' property, default to Spec v2.00
65
sdcard: Disable SEND_IF_COND (CMD8) for Spec v1
66
sdcard: Reflect when the Spec v3 is supported in the Config Register (SCR)
67
sdcard: Disable CMD19/CMD23 for Spec v2
68
28
69
Shannon Zhao (1):
29
Nolan Leake (1):
70
arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
30
hw/arm: Add basic power management to raspi.
71
31
72
Thomas Huth (1):
32
Patrick Venture (2):
73
hw/arm: Remove the deprecated xlnx-ep108 machine
33
docs/system/arm: Add quanta-q7l1-bmc reference
34
docs/system/arm: Add quanta-gbs-bmc reference
74
35
75
Makefile.objs | 1 +
36
Peter Maydell (18):
76
hw/misc/Makefile.objs | 1 +
37
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
77
tests/Makefile.include | 2 +
38
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
78
include/hw/i2c/smbus.h | 1 +
39
target/arm: Make asimd_imm_const() public
79
include/hw/intc/arm_gicv3_common.h | 1 +
40
target/arm: Use asimd_imm_const for A64 decode
80
include/hw/misc/pca9552.h | 32 +++++
41
target/arm: Use dup_const() instead of bitfield_replicate()
81
include/hw/misc/pca9552_regs.h | 32 +++++
42
target/arm: Implement MVE logical immediate insns
82
include/hw/net/ftgmac100.h | 7 +-
43
target/arm: Implement MVE vector shift left by immediate insns
83
include/hw/sd/sd.h | 6 +
44
target/arm: Implement MVE vector shift right by immediate insns
84
tests/libqos/i2c.h | 2 +
45
target/arm: Implement MVE VSHLL
85
hw/arm/aspeed.c | 88 +++++++++++++-
46
target/arm: Implement MVE VSRI, VSLI
86
hw/arm/stellaris.c | 11 +-
47
target/arm: Implement MVE VSHRN, VRSHRN
87
hw/arm/xlnx-zcu102.c | 62 +---------
48
target/arm: Implement MVE saturating narrowing shifts
88
hw/char/digic-uart.c | 4 +-
49
target/arm: Implement MVE VSHLC
89
hw/core/register.c | 2 +-
50
target/arm: Implement MVE VADDLV
90
hw/display/xlnx_dp.c | 4 +-
51
target/arm: Implement MVE long shifts by immediate
91
hw/i2c/core.c | 25 ++--
52
target/arm: Implement MVE long shifts by register
92
hw/i2c/smbus_eeprom.c | 16 ++-
53
target/arm: Implement MVE shifts by immediate
93
hw/intc/arm_gicv3_common.c | 79 ++++++++++++
54
target/arm: Implement MVE shifts by register
94
hw/intc/arm_gicv3_kvm.c | 38 ++++++
95
hw/mips/boston.c | 8 +-
96
hw/misc/pca9552.c | 240 +++++++++++++++++++++++++++++++++++++
97
hw/net/ftgmac100.c | 64 ++++++----
98
hw/ppc/pnv_core.c | 4 +-
99
hw/sd/milkymist-memcard.c | 2 +-
100
hw/sd/sd.c | 50 +++++---
101
hw/timer/digic-timer.c | 4 +-
102
target/arm/helper.c | 4 +-
103
target/m68k/translate.c | 2 +-
104
target/riscv/op_helper.c | 6 +-
105
target/xtensa/translate.c | 6 +-
106
tests/pca9552-test.c | 116 ++++++++++++++++++
107
tests/tmp105-test.c | 2 -
108
default-configs/arm-softmmu.mak | 1 +
109
hw/i2c/trace-events | 7 ++
110
qemu-doc.texi | 5 -
111
36 files changed, 788 insertions(+), 147 deletions(-)
112
create mode 100644 include/hw/misc/pca9552.h
113
create mode 100644 include/hw/misc/pca9552_regs.h
114
create mode 100644 hw/misc/pca9552.c
115
create mode 100644 tests/pca9552-test.c
116
create mode 100644 hw/i2c/trace-events
117
55
56
Philippe Mathieu-Daudé (1):
57
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
58
59
docs/system/arm/aspeed.rst | 1 +
60
docs/system/arm/nuvoton.rst | 5 +-
61
include/hw/arm/bcm2835_peripherals.h | 3 +-
62
include/hw/misc/bcm2835_powermgt.h | 29 ++
63
target/arm/helper-mve.h | 108 +++++++
64
target/arm/translate.h | 41 +++
65
target/arm/mve.decode | 177 ++++++++++-
66
target/arm/t32.decode | 71 ++++-
67
hw/arm/bcm2835_peripherals.c | 13 +-
68
hw/gpio/gpio_pwr.c | 2 +-
69
hw/misc/bcm2835_powermgt.c | 160 ++++++++++
70
target/arm/helper-a64.c | 12 +-
71
target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--
72
target/arm/translate-a64.c | 86 +-----
73
target/arm/translate-mve.c | 261 +++++++++++++++-
74
target/arm/translate-neon.c | 81 -----
75
target/arm/translate.c | 327 +++++++++++++++++++-
76
target/arm/vfp_helper.c | 24 +-
77
hw/misc/meson.build | 1 +
78
tests/acceptance/boot_linux_console.py | 43 +++
79
20 files changed, 1760 insertions(+), 209 deletions(-)
80
create mode 100644 include/hw/misc/bcm2835_powermgt.h
81
create mode 100644 hw/misc/bcm2835_powermgt.c
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/31] hw/core/register: Add trailing '\n' to qemu_log() call
[PULL 01/24] docs/system/arm: Add quanta-q7l1-bmc reference
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
entry.
5
Message-id: 20180606152128.449-6-f4bug@amsat.org
5
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20210615192848.1065297-2-venture@google.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/core/register.c | 2 +-
11
docs/system/arm/aspeed.rst | 1 +
9
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 1 insertion(+)
10
13
11
diff --git a/hw/core/register.c b/hw/core/register.c
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/core/register.c
16
--- a/docs/system/arm/aspeed.rst
14
+++ b/hw/core/register.c
17
+++ b/docs/system/arm/aspeed.rst
15
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
18
@@ -XXX,XX +XXX,XX @@ etc.
16
if (test) {
19
AST2400 SoC based machines :
17
qemu_log_mask(LOG_UNIMP,
20
18
"%s:%s writing %#" PRIx64 " to unimplemented bits:" \
21
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
19
- " %#" PRIx64 "",
22
+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
20
+ " %#" PRIx64 "\n",
23
21
prefix, reg->access->name, val, ac->unimp);
24
AST2500 SoC based machines :
22
}
23
25
24
--
26
--
25
2.17.1
27
2.20.1
26
28
27
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/31] sdcard: Disable CMD19/CMD23 for Spec v2
[PULL 02/24] docs/system/arm: Add quanta-gbs-bmc reference
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
These commands got introduced by Spec v3
3
Add line item reference to quanta-gbs-bmc machine.
4
(see 0c3fb03f7ec and 4481bbc79d2).
5
4
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Signed-off-by: Patrick Venture <venture@google.com>
7
Message-id: 20180607180641.874-7-f4bug@amsat.org
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20210615192848.1065297-3-venture@google.com
8
[PMM: fixed underline Sphinx warning]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/sd/sd.c | 6 ++++++
11
docs/system/arm/nuvoton.rst | 5 +++--
12
1 file changed, 6 insertions(+)
12
1 file changed, 3 insertions(+), 2 deletions(-)
13
13
14
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/sd/sd.c
16
--- a/docs/system/arm/nuvoton.rst
17
+++ b/hw/sd/sd.c
17
+++ b/docs/system/arm/nuvoton.rst
18
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
18
@@ -XXX,XX +XXX,XX @@
19
break;
19
-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)
20
20
-=====================================================
21
case 19: /* CMD19: SEND_TUNING_BLOCK (SD) */
21
+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)
22
+ if (sd->spec_version < SD_PHY_SPECv3_01_VERS) {
22
+================================================================
23
+ break;
23
24
+ }
24
The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are
25
if (sd->state == sd_transfer_state) {
25
designed to be used as Baseboard Management Controllers (BMCs) in various
26
sd->state = sd_sendingdata_state;
26
@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :
27
sd->data_offset = 0;
27
The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
28
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
28
Hyperscale applications. The following machines are based on this chip :
29
break;
29
30
30
+- ``quanta-gbs-bmc`` Quanta GBS server BMC
31
case 23: /* CMD23: SET_BLOCK_COUNT */
31
- ``quanta-gsj`` Quanta GSJ server BMC
32
+ if (sd->spec_version < SD_PHY_SPECv3_01_VERS) {
32
33
+ break;
33
There are also two more SoCs, NPCM710 and NPCM705, which are single-core
34
+ }
35
switch (sd->state) {
36
case sd_transfer_state:
37
sd->multi_blk_cnt = req.arg;
38
--
34
--
39
2.17.1
35
2.20.1
40
36
41
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/31] misc: add pca9552 LED blinker model
[PULL 03/24] hw/arm: Add basic power management to raspi.
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Nolan Leake <nolan@sigbus.net>
2
2
3
Specs are available here :
3
This is just enough to make reboot and poweroff work. Works for
4
4
linux, u-boot, and the arm trusted firmware. Not tested, but should
5
https://www.nxp.com/docs/en/application-note/AN264.pdf
5
work for plan9, and bare-metal/hobby OSes, since they seem to generally
6
6
do what linux does for reset.
7
This is a simple model supporting the basic registers for led and GPIO
7
8
mode. The device also supports two blinking rates but not the model
8
The watchdog timer functionality is not yet implemented.
9
yet.
9
10
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
11
Signed-off-by: Nolan Leake <nolan@sigbus.net>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20180530064049.27976-7-clg@kaod.org
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
15
[PMM: tweaked commit title; fixed region size to 0x200;
16
moved header file to include/]
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
18
---
17
hw/misc/Makefile.objs | 1 +
19
include/hw/arm/bcm2835_peripherals.h | 3 +-
18
tests/Makefile.include | 2 +
20
include/hw/misc/bcm2835_powermgt.h | 29 +++++
19
include/hw/misc/pca9552.h | 32 +++++
21
hw/arm/bcm2835_peripherals.c | 13 ++-
20
include/hw/misc/pca9552_regs.h | 32 +++++
22
hw/misc/bcm2835_powermgt.c | 160 +++++++++++++++++++++++++++
21
tests/libqos/i2c.h | 2 +
23
hw/misc/meson.build | 1 +
22
hw/misc/pca9552.c | 240 ++++++++++++++++++++++++++++++++
24
5 files changed, 204 insertions(+), 2 deletions(-)
23
tests/pca9552-test.c | 116 +++++++++++++++
25
create mode 100644 include/hw/misc/bcm2835_powermgt.h
24
tests/tmp105-test.c | 2 -
26
create mode 100644 hw/misc/bcm2835_powermgt.c
25
default-configs/arm-softmmu.mak | 1 +
27
26
9 files changed, 426 insertions(+), 2 deletions(-)
28
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
27
create mode 100644 include/hw/misc/pca9552.h
28
create mode 100644 include/hw/misc/pca9552_regs.h
29
create mode 100644 hw/misc/pca9552.c
30
create mode 100644 tests/pca9552-test.c
31
32
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
33
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/misc/Makefile.objs
30
--- a/include/hw/arm/bcm2835_peripherals.h
35
+++ b/hw/misc/Makefile.objs
31
+++ b/include/hw/arm/bcm2835_peripherals.h
36
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
32
@@ -XXX,XX +XXX,XX @@
37
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
33
#include "hw/misc/bcm2835_mphi.h"
38
common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
34
#include "hw/misc/bcm2835_thermal.h"
39
common-obj-$(CONFIG_EDU) += edu.o
35
#include "hw/misc/bcm2835_cprman.h"
40
+common-obj-$(CONFIG_PCA9552) += pca9552.o
36
+#include "hw/misc/bcm2835_powermgt.h"
41
37
#include "hw/sd/sdhci.h"
42
common-obj-y += unimp.o
38
#include "hw/sd/bcm2835_sdhost.h"
43
common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o
39
#include "hw/gpio/bcm2835_gpio.h"
44
diff --git a/tests/Makefile.include b/tests/Makefile.include
40
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
45
index XXXXXXX..XXXXXXX 100644
41
BCM2835MphiState mphi;
46
--- a/tests/Makefile.include
42
UnimplementedDeviceState txp;
47
+++ b/tests/Makefile.include
43
UnimplementedDeviceState armtmr;
48
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
44
- UnimplementedDeviceState powermgt;
49
check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
45
+ BCM2835PowerMgtState powermgt;
50
46
BCM2835CprmanState cprman;
51
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
47
PL011State uart0;
52
+check-qtest-arm-y += tests/pca9552-test$(EXESUF)
48
BCM2835AuxState aux;
53
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
49
diff --git a/include/hw/misc/bcm2835_powermgt.h b/include/hw/misc/bcm2835_powermgt.h
54
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
55
gcov-files-arm-y += hw/misc/tmp105.c
56
@@ -XXX,XX +XXX,XX @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
57
    tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y)
58
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
59
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
60
+tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y)
61
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
62
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
63
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
64
diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h
65
new file mode 100644
50
new file mode 100644
66
index XXXXXXX..XXXXXXX
51
index XXXXXXX..XXXXXXX
67
--- /dev/null
52
--- /dev/null
68
+++ b/include/hw/misc/pca9552.h
53
+++ b/include/hw/misc/bcm2835_powermgt.h
69
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@
70
+/*
55
+/*
71
+ * PCA9552 I2C LED blinker
56
+ * BCM2835 Power Management emulation
72
+ *
57
+ *
73
+ * Copyright (c) 2017-2018, IBM Corporation.
58
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
74
+ *
59
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
75
+ * This work is licensed under the terms of the GNU GPL, version 2 or
60
+ *
76
+ * later. See the COPYING file in the top-level directory.
61
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
62
+ * See the COPYING file in the top-level directory.
77
+ */
63
+ */
78
+#ifndef PCA9552_H
64
+
79
+#define PCA9552_H
65
+#ifndef BCM2835_POWERMGT_H
80
+
66
+#define BCM2835_POWERMGT_H
81
+#include "hw/i2c/i2c.h"
67
+
82
+
68
+#include "hw/sysbus.h"
83
+#define TYPE_PCA9552 "pca9552"
69
+#include "qom/object.h"
84
+#define PCA9552(obj) OBJECT_CHECK(PCA9552State, (obj), TYPE_PCA9552)
70
+
85
+
71
+#define TYPE_BCM2835_POWERMGT "bcm2835-powermgt"
86
+#define PCA9552_NR_REGS 10
72
+OBJECT_DECLARE_SIMPLE_TYPE(BCM2835PowerMgtState, BCM2835_POWERMGT)
87
+
73
+
88
+typedef struct PCA9552State {
74
+struct BCM2835PowerMgtState {
89
+ /*< private >*/
75
+ SysBusDevice busdev;
90
+ I2CSlave i2c;
76
+ MemoryRegion iomem;
91
+ /*< public >*/
77
+
92
+
78
+ uint32_t rstc;
93
+ uint8_t len;
79
+ uint32_t rsts;
94
+ uint8_t pointer;
80
+ uint32_t wdog;
95
+
81
+};
96
+ uint8_t regs[PCA9552_NR_REGS];
97
+ uint8_t max_reg;
98
+ uint8_t nr_leds;
99
+} PCA9552State;
100
+
82
+
101
+#endif
83
+#endif
102
diff --git a/include/hw/misc/pca9552_regs.h b/include/hw/misc/pca9552_regs.h
84
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/arm/bcm2835_peripherals.c
87
+++ b/hw/arm/bcm2835_peripherals.c
88
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_init(Object *obj)
89
90
object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr",
91
OBJECT(&s->gpu_bus_mr));
92
+
93
+ /* Power Management */
94
+ object_initialize_child(obj, "powermgt", &s->powermgt,
95
+ TYPE_BCM2835_POWERMGT);
96
}
97
98
static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
99
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
100
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
101
INTERRUPT_USB));
102
103
+ /* Power Management */
104
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->powermgt), errp)) {
105
+ return;
106
+ }
107
+
108
+ memory_region_add_subregion(&s->peri_mr, PM_OFFSET,
109
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->powermgt), 0));
110
+
111
create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
112
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
113
- create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114);
114
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
115
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
116
create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20);
117
diff --git a/hw/misc/bcm2835_powermgt.c b/hw/misc/bcm2835_powermgt.c
103
new file mode 100644
118
new file mode 100644
104
index XXXXXXX..XXXXXXX
119
index XXXXXXX..XXXXXXX
105
--- /dev/null
120
--- /dev/null
106
+++ b/include/hw/misc/pca9552_regs.h
121
+++ b/hw/misc/bcm2835_powermgt.c
107
@@ -XXX,XX +XXX,XX @@
122
@@ -XXX,XX +XXX,XX @@
108
+/*
123
+/*
109
+ * PCA9552 I2C LED blinker registers
124
+ * BCM2835 Power Management emulation
110
+ *
125
+ *
111
+ * Copyright (c) 2017-2018, IBM Corporation.
126
+ * Copyright (C) 2017 Marcin Chojnacki <marcinch7@gmail.com>
112
+ *
127
+ * Copyright (C) 2021 Nolan Leake <nolan@sigbus.net>
113
+ * This work is licensed under the terms of the GNU GPL, version 2 or
114
+ * later. See the COPYING file in the top-level directory.
115
+ */
116
+#ifndef PCA9552_REGS_H
117
+#define PCA9552_REGS_H
118
+
119
+/*
120
+ * Bits [0:3] are used to address a specific register.
121
+ */
122
+#define PCA9552_INPUT0 0 /* read only input register 0 */
123
+#define PCA9552_INPUT1 1 /* read only input register 1 */
124
+#define PCA9552_PSC0 2 /* read/write frequency prescaler 0 */
125
+#define PCA9552_PWM0 3 /* read/write PWM register 0 */
126
+#define PCA9552_PSC1 4 /* read/write frequency prescaler 1 */
127
+#define PCA9552_PWM1 5 /* read/write PWM register 1 */
128
+#define PCA9552_LS0 6 /* read/write LED0 to LED3 selector */
129
+#define PCA9552_LS1 7 /* read/write LED4 to LED7 selector */
130
+#define PCA9552_LS2 8 /* read/write LED8 to LED11 selector */
131
+#define PCA9552_LS3 9 /* read/write LED12 to LED15 selector */
132
+
133
+/*
134
+ * Bit [4] is used to activate the Auto-Increment option of the
135
+ * register address
136
+ */
137
+#define PCA9552_AUTOINC (1 << 4)
138
+
139
+#endif
140
diff --git a/tests/libqos/i2c.h b/tests/libqos/i2c.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/tests/libqos/i2c.h
143
+++ b/tests/libqos/i2c.h
144
@@ -XXX,XX +XXX,XX @@ struct I2CAdapter {
145
QTestState *qts;
146
};
147
148
+#define OMAP2_I2C_1_BASE 0x48070000
149
+
150
void i2c_send(I2CAdapter *i2c, uint8_t addr,
151
const uint8_t *buf, uint16_t len);
152
void i2c_recv(I2CAdapter *i2c, uint8_t addr,
153
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
154
new file mode 100644
155
index XXXXXXX..XXXXXXX
156
--- /dev/null
157
+++ b/hw/misc/pca9552.c
158
@@ -XXX,XX +XXX,XX @@
159
+/*
160
+ * PCA9552 I2C LED blinker
161
+ *
162
+ * https://www.nxp.com/docs/en/application-note/AN264.pdf
163
+ *
164
+ * Copyright (c) 2017-2018, IBM Corporation.
165
+ *
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or
167
+ * later. See the COPYING file in the top-level directory.
168
+ */
169
+
170
+#include "qemu/osdep.h"
171
+#include "qemu/log.h"
172
+#include "hw/hw.h"
173
+#include "hw/misc/pca9552.h"
174
+#include "hw/misc/pca9552_regs.h"
175
+
176
+#define PCA9552_LED_ON 0x0
177
+#define PCA9552_LED_OFF 0x1
178
+#define PCA9552_LED_PWM0 0x2
179
+#define PCA9552_LED_PWM1 0x3
180
+
181
+static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin)
182
+{
183
+ uint8_t reg = PCA9552_LS0 + (pin / 4);
184
+ uint8_t shift = (pin % 4) << 1;
185
+
186
+ return extract32(s->regs[reg], shift, 2);
187
+}
188
+
189
+static void pca9552_update_pin_input(PCA9552State *s)
190
+{
191
+ int i;
192
+
193
+ for (i = 0; i < s->nr_leds; i++) {
194
+ uint8_t input_reg = PCA9552_INPUT0 + (i / 8);
195
+ uint8_t input_shift = (i % 8);
196
+ uint8_t config = pca9552_pin_get_config(s, i);
197
+
198
+ switch (config) {
199
+ case PCA9552_LED_ON:
200
+ s->regs[input_reg] |= 1 << input_shift;
201
+ break;
202
+ case PCA9552_LED_OFF:
203
+ s->regs[input_reg] &= ~(1 << input_shift);
204
+ break;
205
+ case PCA9552_LED_PWM0:
206
+ case PCA9552_LED_PWM1:
207
+ /* TODO */
208
+ default:
209
+ break;
210
+ }
211
+ }
212
+}
213
+
214
+static uint8_t pca9552_read(PCA9552State *s, uint8_t reg)
215
+{
216
+ switch (reg) {
217
+ case PCA9552_INPUT0:
218
+ case PCA9552_INPUT1:
219
+ case PCA9552_PSC0:
220
+ case PCA9552_PWM0:
221
+ case PCA9552_PSC1:
222
+ case PCA9552_PWM1:
223
+ case PCA9552_LS0:
224
+ case PCA9552_LS1:
225
+ case PCA9552_LS2:
226
+ case PCA9552_LS3:
227
+ return s->regs[reg];
228
+ default:
229
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected read to register %d\n",
230
+ __func__, reg);
231
+ return 0xFF;
232
+ }
233
+}
234
+
235
+static void pca9552_write(PCA9552State *s, uint8_t reg, uint8_t data)
236
+{
237
+ switch (reg) {
238
+ case PCA9552_PSC0:
239
+ case PCA9552_PWM0:
240
+ case PCA9552_PSC1:
241
+ case PCA9552_PWM1:
242
+ s->regs[reg] = data;
243
+ break;
244
+
245
+ case PCA9552_LS0:
246
+ case PCA9552_LS1:
247
+ case PCA9552_LS2:
248
+ case PCA9552_LS3:
249
+ s->regs[reg] = data;
250
+ pca9552_update_pin_input(s);
251
+ break;
252
+
253
+ case PCA9552_INPUT0:
254
+ case PCA9552_INPUT1:
255
+ default:
256
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected write to register %d\n",
257
+ __func__, reg);
258
+ }
259
+}
260
+
261
+/*
262
+ * When Auto-Increment is on, the register address is incremented
263
+ * after each byte is sent to or received by the device. The index
264
+ * rollovers to 0 when the maximum register address is reached.
265
+ */
266
+static void pca9552_autoinc(PCA9552State *s)
267
+{
268
+ if (s->pointer != 0xFF && s->pointer & PCA9552_AUTOINC) {
269
+ uint8_t reg = s->pointer & 0xf;
270
+
271
+ reg = (reg + 1) % (s->max_reg + 1);
272
+ s->pointer = reg | PCA9552_AUTOINC;
273
+ }
274
+}
275
+
276
+static int pca9552_recv(I2CSlave *i2c)
277
+{
278
+ PCA9552State *s = PCA9552(i2c);
279
+ uint8_t ret;
280
+
281
+ ret = pca9552_read(s, s->pointer & 0xf);
282
+
283
+ /*
284
+ * From the Specs:
285
+ *
286
+ * Important Note: When a Read sequence is initiated and the
287
+ * AI bit is set to Logic Level 1, the Read Sequence MUST
288
+ * start by a register different from 0.
289
+ *
290
+ * I don't know what should be done in this case, so throw an
291
+ * error.
292
+ */
293
+ if (s->pointer == PCA9552_AUTOINC) {
294
+ qemu_log_mask(LOG_GUEST_ERROR,
295
+ "%s: Autoincrement read starting with register 0\n",
296
+ __func__);
297
+ }
298
+
299
+ pca9552_autoinc(s);
300
+
301
+ return ret;
302
+}
303
+
304
+static int pca9552_send(I2CSlave *i2c, uint8_t data)
305
+{
306
+ PCA9552State *s = PCA9552(i2c);
307
+
308
+ /* First byte sent by is the register address */
309
+ if (s->len == 0) {
310
+ s->pointer = data;
311
+ s->len++;
312
+ } else {
313
+ pca9552_write(s, s->pointer & 0xf, data);
314
+
315
+ pca9552_autoinc(s);
316
+ }
317
+
318
+ return 0;
319
+}
320
+
321
+static int pca9552_event(I2CSlave *i2c, enum i2c_event event)
322
+{
323
+ PCA9552State *s = PCA9552(i2c);
324
+
325
+ s->len = 0;
326
+ return 0;
327
+}
328
+
329
+static const VMStateDescription pca9552_vmstate = {
330
+ .name = "PCA9552",
331
+ .version_id = 0,
332
+ .minimum_version_id = 0,
333
+ .fields = (VMStateField[]) {
334
+ VMSTATE_UINT8(len, PCA9552State),
335
+ VMSTATE_UINT8(pointer, PCA9552State),
336
+ VMSTATE_UINT8_ARRAY(regs, PCA9552State, PCA9552_NR_REGS),
337
+ VMSTATE_I2C_SLAVE(i2c, PCA9552State),
338
+ VMSTATE_END_OF_LIST()
339
+ }
340
+};
341
+
342
+static void pca9552_reset(DeviceState *dev)
343
+{
344
+ PCA9552State *s = PCA9552(dev);
345
+
346
+ s->regs[PCA9552_PSC0] = 0xFF;
347
+ s->regs[PCA9552_PWM0] = 0x80;
348
+ s->regs[PCA9552_PSC1] = 0xFF;
349
+ s->regs[PCA9552_PWM1] = 0x80;
350
+ s->regs[PCA9552_LS0] = 0x55; /* all OFF */
351
+ s->regs[PCA9552_LS1] = 0x55;
352
+ s->regs[PCA9552_LS2] = 0x55;
353
+ s->regs[PCA9552_LS3] = 0x55;
354
+
355
+ pca9552_update_pin_input(s);
356
+
357
+ s->pointer = 0xFF;
358
+ s->len = 0;
359
+}
360
+
361
+static void pca9552_initfn(Object *obj)
362
+{
363
+ PCA9552State *s = PCA9552(obj);
364
+
365
+ /* If support for the other PCA955X devices are implemented, these
366
+ * constant values might be part of class structure describing the
367
+ * PCA955X device
368
+ */
369
+ s->max_reg = PCA9552_LS3;
370
+ s->nr_leds = 16;
371
+}
372
+
373
+static void pca9552_class_init(ObjectClass *klass, void *data)
374
+{
375
+ DeviceClass *dc = DEVICE_CLASS(klass);
376
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
377
+
378
+ k->event = pca9552_event;
379
+ k->recv = pca9552_recv;
380
+ k->send = pca9552_send;
381
+ dc->reset = pca9552_reset;
382
+ dc->vmsd = &pca9552_vmstate;
383
+}
384
+
385
+static const TypeInfo pca9552_info = {
386
+ .name = TYPE_PCA9552,
387
+ .parent = TYPE_I2C_SLAVE,
388
+ .instance_init = pca9552_initfn,
389
+ .instance_size = sizeof(PCA9552State),
390
+ .class_init = pca9552_class_init,
391
+};
392
+
393
+static void pca9552_register_types(void)
394
+{
395
+ type_register_static(&pca9552_info);
396
+}
397
+
398
+type_init(pca9552_register_types)
399
diff --git a/tests/pca9552-test.c b/tests/pca9552-test.c
400
new file mode 100644
401
index XXXXXXX..XXXXXXX
402
--- /dev/null
403
+++ b/tests/pca9552-test.c
404
@@ -XXX,XX +XXX,XX @@
405
+/*
406
+ * QTest testcase for the PCA9552 LED blinker
407
+ *
408
+ * Copyright (c) 2017-2018, IBM Corporation.
409
+ *
128
+ *
410
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
129
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
411
+ * See the COPYING file in the top-level directory.
130
+ * See the COPYING file in the top-level directory.
412
+ */
131
+ */
413
+
132
+
414
+#include "qemu/osdep.h"
133
+#include "qemu/osdep.h"
415
+
134
+#include "qemu/log.h"
416
+#include "libqtest.h"
135
+#include "qemu/module.h"
417
+#include "libqos/i2c.h"
136
+#include "hw/misc/bcm2835_powermgt.h"
418
+#include "hw/misc/pca9552_regs.h"
137
+#include "migration/vmstate.h"
419
+
138
+#include "sysemu/runstate.h"
420
+#define PCA9552_TEST_ID "pca9552-test"
139
+
421
+#define PCA9552_TEST_ADDR 0x60
140
+#define PASSWORD 0x5a000000
422
+
141
+#define PASSWORD_MASK 0xff000000
423
+static I2CAdapter *i2c;
142
+
424
+
143
+#define R_RSTC 0x1c
425
+static uint8_t pca9552_get8(I2CAdapter *i2c, uint8_t addr, uint8_t reg)
144
+#define V_RSTC_RESET 0x20
426
+{
145
+#define R_RSTS 0x20
427
+ uint8_t resp[1];
146
+#define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
428
+ i2c_send(i2c, addr, &reg, 1);
147
+#define R_WDOG 0x24
429
+ i2c_recv(i2c, addr, resp, 1);
148
+
430
+ return resp[0];
149
+static uint64_t bcm2835_powermgt_read(void *opaque, hwaddr offset,
431
+}
150
+ unsigned size)
432
+
151
+{
433
+static void pca9552_set8(I2CAdapter *i2c, uint8_t addr, uint8_t reg,
152
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
434
+ uint8_t value)
153
+ uint32_t res = 0;
435
+{
154
+
436
+ uint8_t cmd[2];
155
+ switch (offset) {
437
+ uint8_t resp[1];
156
+ case R_RSTC:
438
+
157
+ res = s->rstc;
439
+ cmd[0] = reg;
158
+ break;
440
+ cmd[1] = value;
159
+ case R_RSTS:
441
+ i2c_send(i2c, addr, cmd, 2);
160
+ res = s->rsts;
442
+ i2c_recv(i2c, addr, resp, 1);
161
+ break;
443
+ g_assert_cmphex(resp[0], ==, cmd[1]);
162
+ case R_WDOG:
444
+}
163
+ res = s->wdog;
445
+
164
+ break;
446
+static void receive_autoinc(void)
165
+
447
+{
166
+ default:
448
+ uint8_t resp;
167
+ qemu_log_mask(LOG_UNIMP,
449
+ uint8_t reg = PCA9552_LS0 | PCA9552_AUTOINC;
168
+ "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx
450
+
169
+ "\n", offset);
451
+ i2c_send(i2c, PCA9552_TEST_ADDR, &reg, 1);
170
+ res = 0;
452
+
171
+ break;
453
+ /* PCA9552_LS0 */
172
+ }
454
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
173
+
455
+ g_assert_cmphex(resp, ==, 0x54);
174
+ return res;
456
+
175
+}
457
+ /* PCA9552_LS1 */
176
+
458
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
177
+static void bcm2835_powermgt_write(void *opaque, hwaddr offset,
459
+ g_assert_cmphex(resp, ==, 0x55);
178
+ uint64_t value, unsigned size)
460
+
179
+{
461
+ /* PCA9552_LS2 */
180
+ BCM2835PowerMgtState *s = (BCM2835PowerMgtState *)opaque;
462
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
181
+
463
+ g_assert_cmphex(resp, ==, 0x55);
182
+ if ((value & PASSWORD_MASK) != PASSWORD) {
464
+
183
+ qemu_log_mask(LOG_GUEST_ERROR,
465
+ /* PCA9552_LS3 */
184
+ "bcm2835_powermgt_write: Bad password 0x%"PRIx64
466
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
185
+ " at offset 0x%08"HWADDR_PRIx"\n",
467
+ g_assert_cmphex(resp, ==, 0x54);
186
+ value, offset);
468
+}
187
+ return;
469
+
188
+ }
470
+static void send_and_receive(void)
189
+
471
+{
190
+ value = value & ~PASSWORD_MASK;
472
+ uint8_t value;
191
+
473
+
192
+ switch (offset) {
474
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_LS0);
193
+ case R_RSTC:
475
+ g_assert_cmphex(value, ==, 0x55);
194
+ s->rstc = value;
476
+
195
+ if (value & V_RSTC_RESET) {
477
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_INPUT0);
196
+ if ((s->rsts & 0xfff) == V_RSTS_POWEROFF) {
478
+ g_assert_cmphex(value, ==, 0x0);
197
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
479
+
198
+ } else {
480
+ /* Switch on LED 0 */
199
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
481
+ pca9552_set8(i2c, PCA9552_TEST_ADDR, PCA9552_LS0, 0x54);
200
+ }
482
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_LS0);
201
+ }
483
+ g_assert_cmphex(value, ==, 0x54);
202
+ break;
484
+
203
+ case R_RSTS:
485
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_INPUT0);
204
+ qemu_log_mask(LOG_UNIMP,
486
+ g_assert_cmphex(value, ==, 0x01);
205
+ "bcm2835_powermgt_write: RSTS\n");
487
+
206
+ s->rsts = value;
488
+ /* Switch on LED 12 */
207
+ break;
489
+ pca9552_set8(i2c, PCA9552_TEST_ADDR, PCA9552_LS3, 0x54);
208
+ case R_WDOG:
490
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_LS3);
209
+ qemu_log_mask(LOG_UNIMP,
491
+ g_assert_cmphex(value, ==, 0x54);
210
+ "bcm2835_powermgt_write: WDOG\n");
492
+
211
+ s->wdog = value;
493
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_INPUT1);
212
+ break;
494
+ g_assert_cmphex(value, ==, 0x10);
213
+
495
+}
214
+ default:
496
+
215
+ qemu_log_mask(LOG_UNIMP,
497
+int main(int argc, char **argv)
216
+ "bcm2835_powermgt_write: Unknown offset 0x%08"HWADDR_PRIx
498
+{
217
+ "\n", offset);
499
+ QTestState *s = NULL;
218
+ break;
500
+ int ret;
219
+ }
501
+
220
+}
502
+ g_test_init(&argc, &argv, NULL);
221
+
503
+
222
+static const MemoryRegionOps bcm2835_powermgt_ops = {
504
+ s = qtest_start("-machine n800 "
223
+ .read = bcm2835_powermgt_read,
505
+ "-device pca9552,bus=i2c-bus.0,id=" PCA9552_TEST_ID
224
+ .write = bcm2835_powermgt_write,
506
+ ",address=0x60");
225
+ .endianness = DEVICE_NATIVE_ENDIAN,
507
+ i2c = omap_i2c_create(s, OMAP2_I2C_1_BASE);
226
+ .impl.min_access_size = 4,
508
+
227
+ .impl.max_access_size = 4,
509
+ qtest_add_func("/pca9552/tx-rx", send_and_receive);
228
+};
510
+ qtest_add_func("/pca9552/rx-autoinc", receive_autoinc);
229
+
511
+
230
+static const VMStateDescription vmstate_bcm2835_powermgt = {
512
+ ret = g_test_run();
231
+ .name = TYPE_BCM2835_POWERMGT,
513
+
232
+ .version_id = 1,
514
+ if (s) {
233
+ .minimum_version_id = 1,
515
+ qtest_quit(s);
234
+ .fields = (VMStateField[]) {
516
+ }
235
+ VMSTATE_UINT32(rstc, BCM2835PowerMgtState),
517
+ g_free(i2c);
236
+ VMSTATE_UINT32(rsts, BCM2835PowerMgtState),
518
+
237
+ VMSTATE_UINT32(wdog, BCM2835PowerMgtState),
519
+ return ret;
238
+ VMSTATE_END_OF_LIST()
520
+}
239
+ }
521
diff --git a/tests/tmp105-test.c b/tests/tmp105-test.c
240
+};
241
+
242
+static void bcm2835_powermgt_init(Object *obj)
243
+{
244
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(obj);
245
+
246
+ memory_region_init_io(&s->iomem, obj, &bcm2835_powermgt_ops, s,
247
+ TYPE_BCM2835_POWERMGT, 0x200);
248
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
249
+}
250
+
251
+static void bcm2835_powermgt_reset(DeviceState *dev)
252
+{
253
+ BCM2835PowerMgtState *s = BCM2835_POWERMGT(dev);
254
+
255
+ /* https://elinux.org/BCM2835_registers#PM */
256
+ s->rstc = 0x00000102;
257
+ s->rsts = 0x00001000;
258
+ s->wdog = 0x00000000;
259
+}
260
+
261
+static void bcm2835_powermgt_class_init(ObjectClass *klass, void *data)
262
+{
263
+ DeviceClass *dc = DEVICE_CLASS(klass);
264
+
265
+ dc->reset = bcm2835_powermgt_reset;
266
+ dc->vmsd = &vmstate_bcm2835_powermgt;
267
+}
268
+
269
+static TypeInfo bcm2835_powermgt_info = {
270
+ .name = TYPE_BCM2835_POWERMGT,
271
+ .parent = TYPE_SYS_BUS_DEVICE,
272
+ .instance_size = sizeof(BCM2835PowerMgtState),
273
+ .class_init = bcm2835_powermgt_class_init,
274
+ .instance_init = bcm2835_powermgt_init,
275
+};
276
+
277
+static void bcm2835_powermgt_register_types(void)
278
+{
279
+ type_register_static(&bcm2835_powermgt_info);
280
+}
281
+
282
+type_init(bcm2835_powermgt_register_types)
283
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
522
index XXXXXXX..XXXXXXX 100644
284
index XXXXXXX..XXXXXXX 100644
523
--- a/tests/tmp105-test.c
285
--- a/hw/misc/meson.build
524
+++ b/tests/tmp105-test.c
286
+++ b/hw/misc/meson.build
525
@@ -XXX,XX +XXX,XX @@
287
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
526
#include "qapi/qmp/qdict.h"
288
'bcm2835_rng.c',
527
#include "hw/misc/tmp105_regs.h"
289
'bcm2835_thermal.c',
528
290
'bcm2835_cprman.c',
529
-#define OMAP2_I2C_1_BASE 0x48070000
291
+ 'bcm2835_powermgt.c',
530
-
292
))
531
#define TMP105_TEST_ID "tmp105-test"
293
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
532
#define TMP105_TEST_ADDR 0x49
294
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c'))
533
534
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
535
index XXXXXXX..XXXXXXX 100644
536
--- a/default-configs/arm-softmmu.mak
537
+++ b/default-configs/arm-softmmu.mak
538
@@ -XXX,XX +XXX,XX @@ CONFIG_TSC2005=y
539
CONFIG_LM832X=y
540
CONFIG_TMP105=y
541
CONFIG_TMP421=y
542
+CONFIG_PCA9552=y
543
CONFIG_STELLARIS=y
544
CONFIG_STELLARIS_INPUT=y
545
CONFIG_STELLARIS_ENET=y
546
--
295
--
547
2.17.1
296
2.20.1
548
297
549
298
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/31] sdcard: Allow commands valid in SPI mode
[PULL 04/24] tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
From the "Physical Layer Simplified Specification Version 1.10"
3
Add a test booting and quickly shutdown a raspi2 machine,
4
Chapter 7.3 "SPI Mode Transaction Packets"
4
to test the power management model:
5
Table 57: "Commands and arguments"
5
6
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
7
console: [ 0.000000] Booting Linux on physical CPU 0xf00
8
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019
9
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
10
console: [ 0.000000] CPU: div instructions available: patching division code
11
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
12
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
13
...
14
console: Boot successful.
15
console: cat /proc/cpuinfo
16
console: / # cat /proc/cpuinfo
17
...
18
console: processor : 3
19
console: model name : ARMv7 Processor rev 5 (v7l)
20
console: BogoMIPS : 125.00
21
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
22
console: CPU implementer : 0x41
23
console: CPU architecture: 7
24
console: CPU variant : 0x0
25
console: CPU part : 0xc07
26
console: CPU revision : 5
27
console: Hardware : BCM2835
28
console: Revision : 0000
29
console: Serial : 0000000000000000
30
console: cat /proc/iomem
31
console: / # cat /proc/iomem
32
console: 00000000-3bffffff : System RAM
33
console: 00008000-00afffff : Kernel code
34
console: 00c00000-00d468ef : Kernel data
35
console: 3f006000-3f006fff : dwc_otg
36
console: 3f007000-3f007eff : /soc/dma@7e007000
37
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
38
console: 3f100000-3f100027 : /soc/watchdog@7e100000
39
console: 3f101000-3f102fff : /soc/cprman@7e101000
40
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
41
PASS (24.59 s)
42
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
43
JOB TIME : 25.02 s
6
44
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
45
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
46
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
9
Message-id: 20180607180641.874-3-f4bug@amsat.org
47
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
49
---
13
hw/sd/sd.c | 14 --------------
50
tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++
14
1 file changed, 14 deletions(-)
51
1 file changed, 43 insertions(+)
15
52
16
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
53
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py
17
index XXXXXXX..XXXXXXX 100644
54
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/sd/sd.c
55
--- a/tests/acceptance/boot_linux_console.py
19
+++ b/hw/sd/sd.c
56
+++ b/tests/acceptance/boot_linux_console.py
20
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
57
@@ -XXX,XX +XXX,XX @@
21
return sd_illegal;
58
from avocado import skip
22
59
from avocado import skipUnless
23
case 6:    /* CMD6: SWITCH_FUNCTION */
60
from avocado_qemu import Test
24
- if (sd->spi)
61
+from avocado_qemu import exec_command
25
- goto bad_cmd;
62
from avocado_qemu import exec_command_and_wait_for_pattern
26
switch (sd->mode) {
63
from avocado_qemu import interrupt_interactive_console_until_pattern
27
case sd_data_transfer_mode:
64
from avocado_qemu import wait_for_console_pattern
28
sd_function_switch(sd, req.arg);
65
@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):
29
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
66
"""
30
67
self.do_test_arm_raspi2(0)
31
/* Block write commands (Class 4) */
68
32
case 24:    /* CMD24: WRITE_SINGLE_BLOCK */
69
+ def test_arm_raspi2_initrd(self):
33
- if (sd->spi) {
70
+ """
34
- goto unimplemented_spi_cmd;
71
+ :avocado: tags=arch:arm
35
- }
72
+ :avocado: tags=machine:raspi2
36
switch (sd->state) {
73
+ """
37
case sd_transfer_state:
74
+ deb_url = ('http://archive.raspberrypi.org/debian/'
38
/* Writing in SPI mode not implemented. */
75
+ 'pool/main/r/raspberrypi-firmware/'
39
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
76
+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')
40
break;
77
+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'
41
78
+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
42
case 25:    /* CMD25: WRITE_MULTIPLE_BLOCK */
79
+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')
43
- if (sd->spi) {
80
+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')
44
- goto unimplemented_spi_cmd;
81
+
45
- }
82
+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
46
switch (sd->state) {
83
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
47
case sd_transfer_state:
84
+ 'arm/rootfs-armv7a.cpio.gz')
48
/* Writing in SPI mode not implemented. */
85
+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
49
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
86
+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
50
break;
87
+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')
51
88
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
52
case 27:    /* CMD27: PROGRAM_CSD */
89
+
53
- if (sd->spi) {
90
+ self.vm.set_console()
54
- goto unimplemented_spi_cmd;
91
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
55
- }
92
+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '
56
switch (sd->state) {
93
+ 'panic=-1 noreboot ' +
57
case sd_transfer_state:
94
+ 'dwc_otg.fiq_fsm_enable=0')
58
sd->state = sd_receivingdata_state;
95
+ self.vm.add_args('-kernel', kernel_path,
59
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
96
+ '-dtb', dtb_path,
60
97
+ '-initrd', initrd_path,
61
/* Lock card commands (Class 7) */
98
+ '-append', kernel_command_line,
62
case 42:    /* CMD42: LOCK_UNLOCK */
99
+ '-no-reboot')
63
- if (sd->spi) {
100
+ self.vm.launch()
64
- goto unimplemented_spi_cmd;
101
+ self.wait_for_console_pattern('Boot successful.')
65
- }
102
+
66
switch (sd->state) {
103
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
67
case sd_transfer_state:
104
+ 'BCM2835')
68
sd->state = sd_receivingdata_state;
105
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
106
+ '/soc/cprman@7e101000')
107
+ exec_command(self, 'halt')
108
+ # Wait for VM to shut down gracefully
109
+ self.vm.wait()
110
+
111
def test_arm_exynos4210_initrd(self):
112
"""
113
:avocado: tags=arch:arm
69
--
114
--
70
2.17.1
115
2.20.1
71
116
72
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/31] sdcard: Disable SEND_IF_COND (CMD8) for Spec v1
[PULL 05/24] target/arm: Check NaN mode before silencing NaN
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Joe Komlodi <joe.komlodi@xilinx.com>
2
2
3
CMD8 is "Reserved" in Spec v1.10.
3
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
4
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
5
assert due to fpst->default_nan_mode being set.
4
6
5
Spec v2.00 introduces the SEND_IF_COND command:
7
To avoid this, we check to see what NaN mode we're running in before we call
8
floatxx_silence_nan().
6
9
7
6.4.1 Power Up
10
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
8
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
CMD8 is newly added in the Physical Layer Specification Version
12
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
10
2.00 to support multiple voltage ranges and used to check whether
11
the card supports supplied voltage. The version 2.00 or later host
12
shall issue CMD8 and verify voltage before card initialization.
13
The host that does not support CMD8 shall supply high voltage range.
14
15
Message-Id: 201204252110.20873.paul@codesourcery.com
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180607180641.874-5-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
15
---
21
hw/sd/sd.c | 4 +++-
16
target/arm/helper-a64.c | 12 +++++++++---
22
1 file changed, 3 insertions(+), 1 deletion(-)
17
target/arm/vfp_helper.c | 24 ++++++++++++++++++------
18
2 files changed, 27 insertions(+), 9 deletions(-)
23
19
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
20
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
25
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
22
--- a/target/arm/helper-a64.c
27
+++ b/hw/sd/sd.c
23
+++ b/target/arm/helper-a64.c
28
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
24
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
29
break;
25
float16 nan = a;
30
26
if (float16_is_signaling_nan(a, fpst)) {
31
case 8:    /* CMD8: SEND_IF_COND */
27
float_raise(float_flag_invalid, fpst);
32
- /* Physical Layer Specification Version 2.00 command */
28
- nan = float16_silence_nan(a, fpst);
33
+ if (sd->spec_version < SD_PHY_SPECv2_00_VERS) {
29
+ if (!fpst->default_nan_mode) {
34
+ break;
30
+ nan = float16_silence_nan(a, fpst);
35
+ }
31
+ }
36
if (sd->state != sd_idle_state) {
37
break;
38
}
32
}
33
if (fpst->default_nan_mode) {
34
nan = float16_default_nan(fpst);
35
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
36
float32 nan = a;
37
if (float32_is_signaling_nan(a, fpst)) {
38
float_raise(float_flag_invalid, fpst);
39
- nan = float32_silence_nan(a, fpst);
40
+ if (!fpst->default_nan_mode) {
41
+ nan = float32_silence_nan(a, fpst);
42
+ }
43
}
44
if (fpst->default_nan_mode) {
45
nan = float32_default_nan(fpst);
46
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
47
float64 nan = a;
48
if (float64_is_signaling_nan(a, fpst)) {
49
float_raise(float_flag_invalid, fpst);
50
- nan = float64_silence_nan(a, fpst);
51
+ if (!fpst->default_nan_mode) {
52
+ nan = float64_silence_nan(a, fpst);
53
+ }
54
}
55
if (fpst->default_nan_mode) {
56
nan = float64_default_nan(fpst);
57
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/vfp_helper.c
60
+++ b/target/arm/vfp_helper.c
61
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
62
float16 nan = f16;
63
if (float16_is_signaling_nan(f16, fpst)) {
64
float_raise(float_flag_invalid, fpst);
65
- nan = float16_silence_nan(f16, fpst);
66
+ if (!fpst->default_nan_mode) {
67
+ nan = float16_silence_nan(f16, fpst);
68
+ }
69
}
70
if (fpst->default_nan_mode) {
71
nan = float16_default_nan(fpst);
72
@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)
73
float32 nan = f32;
74
if (float32_is_signaling_nan(f32, fpst)) {
75
float_raise(float_flag_invalid, fpst);
76
- nan = float32_silence_nan(f32, fpst);
77
+ if (!fpst->default_nan_mode) {
78
+ nan = float32_silence_nan(f32, fpst);
79
+ }
80
}
81
if (fpst->default_nan_mode) {
82
nan = float32_default_nan(fpst);
83
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
84
float64 nan = f64;
85
if (float64_is_signaling_nan(f64, fpst)) {
86
float_raise(float_flag_invalid, fpst);
87
- nan = float64_silence_nan(f64, fpst);
88
+ if (!fpst->default_nan_mode) {
89
+ nan = float64_silence_nan(f64, fpst);
90
+ }
91
}
92
if (fpst->default_nan_mode) {
93
nan = float64_default_nan(fpst);
94
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
95
float16 nan = f16;
96
if (float16_is_signaling_nan(f16, s)) {
97
float_raise(float_flag_invalid, s);
98
- nan = float16_silence_nan(f16, s);
99
+ if (!s->default_nan_mode) {
100
+ nan = float16_silence_nan(f16, fpstp);
101
+ }
102
}
103
if (s->default_nan_mode) {
104
nan = float16_default_nan(s);
105
@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
106
float32 nan = f32;
107
if (float32_is_signaling_nan(f32, s)) {
108
float_raise(float_flag_invalid, s);
109
- nan = float32_silence_nan(f32, s);
110
+ if (!s->default_nan_mode) {
111
+ nan = float32_silence_nan(f32, fpstp);
112
+ }
113
}
114
if (s->default_nan_mode) {
115
nan = float32_default_nan(s);
116
@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
117
float64 nan = f64;
118
if (float64_is_signaling_nan(f64, s)) {
119
float_raise(float_flag_invalid, s);
120
- nan = float64_silence_nan(f64, s);
121
+ if (!s->default_nan_mode) {
122
+ nan = float64_silence_nan(f64, fpstp);
123
+ }
124
}
125
if (s->default_nan_mode) {
126
nan = float64_default_nan(s);
39
--
127
--
40
2.17.1
128
2.20.1
41
129
42
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/31] ppc/pnv: Add trailing '\n' to qemu_log() calls
[PULL 06/24] hw/gpio/gpio_pwr: use shutdown function for reboot
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Maxim Uvarov <maxim.uvarov@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
qemu has 2 type of functions: shutdown and reboot. Shutdown
4
Acked-by: David Gibson <david@gibson.dropbear.id.au>
4
function has to be used for machine shutdown. Otherwise we cause
5
Message-id: 20180606152128.449-5-f4bug@amsat.org
5
a reset with a bogus "cause" value, when we intended a shutdown.
6
7
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
10
[PMM: tweaked commit message]
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/ppc/pnv_core.c | 4 ++--
13
hw/gpio/gpio_pwr.c | 2 +-
9
1 file changed, 2 insertions(+), 2 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
10
15
11
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
16
diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/ppc/pnv_core.c
18
--- a/hw/gpio/gpio_pwr.c
14
+++ b/hw/ppc/pnv_core.c
19
+++ b/hw/gpio/gpio_pwr.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
20
@@ -XXX,XX +XXX,XX @@ static void gpio_pwr_reset(void *opaque, int n, int level)
16
val = 0x24f000000000000ull;
21
static void gpio_pwr_shutdown(void *opaque, int n, int level)
17
break;
22
{
18
default:
23
if (level) {
19
- qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
24
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
20
+ qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
25
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
21
addr);
22
}
26
}
23
24
@@ -XXX,XX +XXX,XX @@ static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
25
static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
26
unsigned int width)
27
{
28
- qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
29
+ qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
30
addr);
31
}
27
}
32
28
33
--
29
--
34
2.17.1
30
2.20.1
35
31
36
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/31] hw/digic: Add trailing '\n' to qemu_log() calls
[PULL 07/24] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
In do_ldst(), the calculation of the offset needs to be based on the
2
size of the memory access, not the size of the elements in the
3
vector. This meant we were getting it wrong for the widening and
4
narrowing variants of the various VLDR and VSTR insns.
2
5
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-3-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
7
---
9
---
8
hw/char/digic-uart.c | 4 ++--
10
target/arm/translate-mve.c | 17 +++++++++--------
9
hw/timer/digic-timer.c | 4 ++--
11
1 file changed, 9 insertions(+), 8 deletions(-)
10
2 files changed, 4 insertions(+), 4 deletions(-)
11
12
12
diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c
13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
13
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/char/digic-uart.c
15
--- a/target/arm/translate-mve.c
15
+++ b/hw/char/digic-uart.c
16
+++ b/target/arm/translate-mve.c
16
@@ -XXX,XX +XXX,XX @@ static uint64_t digic_uart_read(void *opaque, hwaddr addr,
17
@@ -XXX,XX +XXX,XX @@ static bool mve_skip_first_beat(DisasContext *s)
17
default:
18
qemu_log_mask(LOG_UNIMP,
19
"digic-uart: read access to unknown register 0x"
20
- TARGET_FMT_plx, addr << 2);
21
+ TARGET_FMT_plx "\n", addr << 2);
22
}
23
24
return ret;
25
@@ -XXX,XX +XXX,XX @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
26
default:
27
qemu_log_mask(LOG_UNIMP,
28
"digic-uart: write access to unknown register 0x"
29
- TARGET_FMT_plx, addr << 2);
30
+ TARGET_FMT_plx "\n", addr << 2);
31
}
18
}
32
}
19
}
33
20
34
diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c
21
-static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
35
index XXXXXXX..XXXXXXX 100644
22
+static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn,
36
--- a/hw/timer/digic-timer.c
23
+ unsigned msize)
37
+++ b/hw/timer/digic-timer.c
24
{
38
@@ -XXX,XX +XXX,XX @@ static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
25
TCGv_i32 addr;
39
default:
26
uint32_t offset;
40
qemu_log_mask(LOG_UNIMP,
27
@@ -XXX,XX +XXX,XX @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn)
41
"digic-timer: read access to unknown register 0x"
28
return true;
42
- TARGET_FMT_plx, offset);
43
+ TARGET_FMT_plx "\n", offset);
44
}
29
}
45
30
46
return ret;
31
- offset = a->imm << a->size;
47
@@ -XXX,XX +XXX,XX @@ static void digic_timer_write(void *opaque, hwaddr offset,
32
+ offset = a->imm << msize;
48
default:
33
if (!a->a) {
49
qemu_log_mask(LOG_UNIMP,
34
offset = -offset;
50
"digic-timer: read access to unknown register 0x"
51
- TARGET_FMT_plx, offset);
52
+ TARGET_FMT_plx "\n", offset);
53
}
35
}
36
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)
37
{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },
38
{ NULL, NULL }
39
};
40
- return do_ldst(s, a, ldstfns[a->size][a->l]);
41
+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);
54
}
42
}
55
43
44
-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \
45
+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \
46
static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \
47
{ \
48
static MVEGenLdStFn * const ldstfns[2][2] = { \
49
{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \
50
{ NULL, gen_helper_mve_##ULD }, \
51
}; \
52
- return do_ldst(s, a, ldstfns[a->u][a->l]); \
53
+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \
54
}
55
56
-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)
57
-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)
58
-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)
59
+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)
60
+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)
61
+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)
62
63
static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
64
{
56
--
65
--
57
2.17.1
66
2.20.1
58
67
59
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/31] hw/i2c: Add trace events
[PULL 08/24] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
2
insns had some bugs:
3
* the 32x32 multiply of elements was being done as 32x32->32,
4
not 32x32->64
5
* we were incorrectly maintaining the accumulator in its full
6
72-bit form across all 4 beats of the insn; in the pseudocode
7
it is squashed back into the 64 bits of the RdaHi:RdaLo
8
registers after each beat
2
9
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
In particular, fixing the second of these allows us to recast
4
Message-id: 20180606191801.6331-1-f4bug@amsat.org
11
the implementation to avoid 128-bit arithmetic entirely.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
13
Since the element size here is always 4, we can also drop the
14
parameterization of ESIZE to make the code a little more readable.
15
16
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
7
---
20
---
8
Makefile.objs | 1 +
21
target/arm/mve_helper.c | 38 +++++++++++++++++++++-----------------
9
hw/i2c/core.c | 25 ++++++++++++++++++-------
22
1 file changed, 21 insertions(+), 17 deletions(-)
10
hw/i2c/trace-events | 7 +++++++
11
3 files changed, 26 insertions(+), 7 deletions(-)
12
create mode 100644 hw/i2c/trace-events
13
23
14
diff --git a/Makefile.objs b/Makefile.objs
24
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/Makefile.objs
26
--- a/target/arm/mve_helper.c
17
+++ b/Makefile.objs
27
+++ b/target/arm/mve_helper.c
18
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/char
19
trace-events-subdirs += hw/display
20
trace-events-subdirs += hw/dma
21
trace-events-subdirs += hw/hppa
22
+trace-events-subdirs += hw/i2c
23
trace-events-subdirs += hw/i386
24
trace-events-subdirs += hw/i386/xen
25
trace-events-subdirs += hw/ide
26
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/i2c/core.c
29
+++ b/hw/i2c/core.c
30
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
29
*/
31
30
32
#include "qemu/osdep.h"
31
#include "qemu/osdep.h"
33
#include "hw/i2c/i2c.h"
32
-#include "qemu/int128.h"
34
+#include "trace.h"
33
#include "cpu.h"
35
34
#include "internals.h"
36
#define I2C_BROADCAST 0x00
35
#include "vec_internal.h"
37
36
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=)
38
@@ -XXX,XX +XXX,XX @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
37
DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
38
39
/*
40
- * Rounding multiply add long dual accumulate high: we must keep
41
- * a 72-bit internal accumulator value and return the top 64 bits.
42
+ * Rounding multiply add long dual accumulate high. In the pseudocode
43
+ * this is implemented with a 72-bit internal accumulator value of which
44
+ * the top 64 bits are returned. We optimize this to avoid having to
45
+ * use 128-bit arithmetic -- we can do this because the 74-bit accumulator
46
+ * is squashed back into 64-bits after each beat.
47
*/
48
-#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \
49
+#define DO_LDAVH(OP, TYPE, LTYPE, XCHG, SUB) \
50
uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
51
void *vm, uint64_t a) \
52
{ \
53
uint16_t mask = mve_element_mask(env); \
54
unsigned e; \
55
TYPE *n = vn, *m = vm; \
56
- Int128 acc = int128_lshift(TO128(a), 8); \
57
- for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
58
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
59
if (mask & 1) { \
60
+ LTYPE mul; \
61
if (e & 1) { \
62
- acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \
63
- m[H##ESIZE(e)])); \
64
+ mul = (LTYPE)n[H4(e - 1 * XCHG)] * m[H4(e)]; \
65
+ if (SUB) { \
66
+ mul = -mul; \
67
+ } \
68
} else { \
69
- acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
70
- m[H##ESIZE(e)])); \
71
+ mul = (LTYPE)n[H4(e + 1 * XCHG)] * m[H4(e)]; \
72
} \
73
- acc = int128_add(acc, int128_make64(1 << 7)); \
74
+ mul = (mul >> 8) + ((mul >> 7) & 1); \
75
+ a += mul; \
76
} \
77
} \
78
mve_advance_vpt(env); \
79
- return int128_getlo(int128_rshift(acc, 8)); \
80
+ return a; \
39
}
81
}
40
82
41
QLIST_FOREACH(node, &bus->current_devs, next) {
83
-DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64)
42
+ I2CSlave *s = node->elt;
84
-DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64)
43
int rv;
85
+DO_LDAVH(vrmlaldavhsw, int32_t, int64_t, false, false)
44
86
+DO_LDAVH(vrmlaldavhxsw, int32_t, int64_t, true, false)
45
- sc = I2C_SLAVE_GET_CLASS(node->elt);
87
46
+ sc = I2C_SLAVE_GET_CLASS(s);
88
-DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64)
47
/* If the bus is already busy, assume this is a repeated
89
+DO_LDAVH(vrmlaldavhuw, uint32_t, uint64_t, false, false)
48
start condition. */
90
49
91
-DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64)
50
if (sc->event) {
92
-DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64)
51
- rv = sc->event(node->elt, recv ? I2C_START_RECV : I2C_START_SEND);
93
+DO_LDAVH(vrmlsldavhsw, int32_t, int64_t, false, true)
52
+ trace_i2c_event("start", s->address);
94
+DO_LDAVH(vrmlsldavhxsw, int32_t, int64_t, true, true)
53
+ rv = sc->event(s, recv ? I2C_START_RECV : I2C_START_SEND);
95
54
if (rv && !bus->broadcast) {
96
/* Vector add across vector */
55
if (bus_scanned) {
97
#define DO_VADDV(OP, ESIZE, TYPE) \
56
/* First call, terminate the transfer. */
57
@@ -XXX,XX +XXX,XX @@ void i2c_end_transfer(I2CBus *bus)
58
I2CNode *node, *next;
59
60
QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
61
- sc = I2C_SLAVE_GET_CLASS(node->elt);
62
+ I2CSlave *s = node->elt;
63
+ sc = I2C_SLAVE_GET_CLASS(s);
64
if (sc->event) {
65
- sc->event(node->elt, I2C_FINISH);
66
+ trace_i2c_event("finish", s->address);
67
+ sc->event(s, I2C_FINISH);
68
}
69
QLIST_REMOVE(node, next);
70
g_free(node);
71
@@ -XXX,XX +XXX,XX @@ void i2c_end_transfer(I2CBus *bus)
72
int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
73
{
74
I2CSlaveClass *sc;
75
+ I2CSlave *s;
76
I2CNode *node;
77
int ret = 0;
78
79
if (send) {
80
QLIST_FOREACH(node, &bus->current_devs, next) {
81
- sc = I2C_SLAVE_GET_CLASS(node->elt);
82
+ s = node->elt;
83
+ sc = I2C_SLAVE_GET_CLASS(s);
84
if (sc->send) {
85
- ret = ret || sc->send(node->elt, *data);
86
+ trace_i2c_send(s->address, *data);
87
+ ret = ret || sc->send(s, *data);
88
} else {
89
ret = -1;
90
}
91
@@ -XXX,XX +XXX,XX @@ int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
92
93
sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
94
if (sc->recv) {
95
- ret = sc->recv(QLIST_FIRST(&bus->current_devs)->elt);
96
+ s = QLIST_FIRST(&bus->current_devs)->elt;
97
+ ret = sc->recv(s);
98
+ trace_i2c_recv(s->address, ret);
99
if (ret < 0) {
100
return ret;
101
} else {
102
@@ -XXX,XX +XXX,XX @@ void i2c_nack(I2CBus *bus)
103
QLIST_FOREACH(node, &bus->current_devs, next) {
104
sc = I2C_SLAVE_GET_CLASS(node->elt);
105
if (sc->event) {
106
+ trace_i2c_event("nack", node->elt->address);
107
sc->event(node->elt, I2C_NACK);
108
}
109
}
110
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
111
new file mode 100644
112
index XXXXXXX..XXXXXXX
113
--- /dev/null
114
+++ b/hw/i2c/trace-events
115
@@ -XXX,XX +XXX,XX @@
116
+# See docs/devel/tracing.txt for syntax documentation.
117
+
118
+# hw/i2c/core.c
119
+
120
+i2c_event(const char *event, uint8_t address) "%s(addr:0x%02x)"
121
+i2c_send(uint8_t address, uint8_t data) "send(addr:0x%02x) data:0x%02x"
122
+i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
123
--
98
--
124
2.17.1
99
2.20.1
125
100
126
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/31] aspeed: remove ignore_memory_transaction_failures on all boards
[PULL 09/24] target/arm: Make asimd_imm_const() public
1
From: Cédric Le Goater <clg@kaod.org>
1
The function asimd_imm_const() in translate-neon.c is an
2
implementation of the pseudocode AdvSIMDExpandImm(), which we will
3
also want for MVE. Move the implementation to translate.c, with a
4
prototype in translate.h.
2
5
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180530064049.27976-2-clg@kaod.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
7
---
9
---
8
hw/arm/aspeed.c | 3 ---
10
target/arm/translate.h | 16 ++++++++++
9
1 file changed, 3 deletions(-)
11
target/arm/translate-neon.c | 63 -------------------------------------
12
target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++
13
3 files changed, 73 insertions(+), 63 deletions(-)
10
14
11
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/aspeed.c
17
--- a/target/arm/translate.h
14
+++ b/hw/arm/aspeed.c
18
+++ b/target/arm/translate.h
15
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
16
mc->no_floppy = 1;
20
return opc | s->be_data;
17
mc->no_cdrom = 1;
18
mc->no_parallel = 1;
19
- mc->ignore_memory_transaction_failures = true;
20
}
21
}
21
22
22
static const TypeInfo palmetto_bmc_type = {
23
+/**
23
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data)
24
+ * asimd_imm_const: Expand an encoded SIMD constant value
24
mc->no_floppy = 1;
25
+ *
25
mc->no_cdrom = 1;
26
+ * Expand a SIMD constant value. This is essentially the pseudocode
26
mc->no_parallel = 1;
27
+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
27
- mc->ignore_memory_transaction_failures = true;
28
+ * VMVN and VBIC (when cmode < 14 && op == 1).
29
+ *
30
+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
31
+ * callers must catch this.
32
+ *
33
+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
34
+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
35
+ * we produce an immediate constant value of 0 in these cases.
36
+ */
37
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
38
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-neon.c
43
+++ b/target/arm/translate-neon.c
44
@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)
45
DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)
46
DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)
47
48
-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
49
-{
50
- /*
51
- * Expand the encoded constant.
52
- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
53
- * We choose to not special-case this and will behave as if a
54
- * valid constant encoding of 0 had been given.
55
- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.
56
- */
57
- switch (cmode) {
58
- case 0: case 1:
59
- /* no-op */
60
- break;
61
- case 2: case 3:
62
- imm <<= 8;
63
- break;
64
- case 4: case 5:
65
- imm <<= 16;
66
- break;
67
- case 6: case 7:
68
- imm <<= 24;
69
- break;
70
- case 8: case 9:
71
- imm |= imm << 16;
72
- break;
73
- case 10: case 11:
74
- imm = (imm << 8) | (imm << 24);
75
- break;
76
- case 12:
77
- imm = (imm << 8) | 0xff;
78
- break;
79
- case 13:
80
- imm = (imm << 16) | 0xffff;
81
- break;
82
- case 14:
83
- if (op) {
84
- /*
85
- * This is the only case where the top and bottom 32 bits
86
- * of the encoded constant differ.
87
- */
88
- uint64_t imm64 = 0;
89
- int n;
90
-
91
- for (n = 0; n < 8; n++) {
92
- if (imm & (1 << n)) {
93
- imm64 |= (0xffULL << (n * 8));
94
- }
95
- }
96
- return imm64;
97
- }
98
- imm |= (imm << 8) | (imm << 16) | (imm << 24);
99
- break;
100
- case 15:
101
- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
102
- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
103
- break;
104
- }
105
- if (op) {
106
- imm = ~imm;
107
- }
108
- return dup_const(MO_32, imm);
109
-}
110
-
111
static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,
112
GVecGen2iFn *fn)
113
{
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
119
a64_translate_init();
28
}
120
}
29
121
30
static const TypeInfo ast2500_evb_type = {
122
+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
31
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data)
123
+{
32
mc->no_floppy = 1;
124
+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */
33
mc->no_cdrom = 1;
125
+ switch (cmode) {
34
mc->no_parallel = 1;
126
+ case 0: case 1:
35
- mc->ignore_memory_transaction_failures = true;
127
+ /* no-op */
36
}
128
+ break;
37
129
+ case 2: case 3:
38
static const TypeInfo romulus_bmc_type = {
130
+ imm <<= 8;
131
+ break;
132
+ case 4: case 5:
133
+ imm <<= 16;
134
+ break;
135
+ case 6: case 7:
136
+ imm <<= 24;
137
+ break;
138
+ case 8: case 9:
139
+ imm |= imm << 16;
140
+ break;
141
+ case 10: case 11:
142
+ imm = (imm << 8) | (imm << 24);
143
+ break;
144
+ case 12:
145
+ imm = (imm << 8) | 0xff;
146
+ break;
147
+ case 13:
148
+ imm = (imm << 16) | 0xffff;
149
+ break;
150
+ case 14:
151
+ if (op) {
152
+ /*
153
+ * This is the only case where the top and bottom 32 bits
154
+ * of the encoded constant differ.
155
+ */
156
+ uint64_t imm64 = 0;
157
+ int n;
158
+
159
+ for (n = 0; n < 8; n++) {
160
+ if (imm & (1 << n)) {
161
+ imm64 |= (0xffULL << (n * 8));
162
+ }
163
+ }
164
+ return imm64;
165
+ }
166
+ imm |= (imm << 8) | (imm << 16) | (imm << 24);
167
+ break;
168
+ case 15:
169
+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
170
+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
171
+ break;
172
+ }
173
+ if (op) {
174
+ imm = ~imm;
175
+ }
176
+ return dup_const(MO_32, imm);
177
+}
178
+
179
/* Generate a label used for skipping this instruction */
180
void arm_gen_condlabel(DisasContext *s)
181
{
39
--
182
--
40
2.17.1
183
2.20.1
41
184
42
185
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/31] hw/mips/boston: Add trailing '\n' to qemu_log() calls
[PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
The A64 AdvSIMD modified-immediate grouping uses almost the same
2
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
3
which we add the AArch64-specific case for cmode 15 op 1) instead of
4
reimplementing it all.
2
5
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-7-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
7
---
9
---
8
hw/mips/boston.c | 8 ++++----
10
target/arm/translate.h | 3 +-
9
1 file changed, 4 insertions(+), 4 deletions(-)
11
target/arm/translate-a64.c | 86 ++++----------------------------------
12
target/arm/translate.c | 17 +++++++-
13
3 files changed, 24 insertions(+), 82 deletions(-)
10
14
11
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
15
diff --git a/target/arm/translate.h b/target/arm/translate.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/mips/boston.c
17
--- a/target/arm/translate.h
14
+++ b/hw/mips/boston.c
18
+++ b/target/arm/translate.h
15
@@ -XXX,XX +XXX,XX @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
19
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
16
uint32_t gic_freq, val;
20
* VMVN and VBIC (when cmode < 14 && op == 1).
17
21
*
18
if (size != 4) {
22
* The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
19
- qemu_log_mask(LOG_UNIMP, "%uB platform register read", size);
23
- * callers must catch this.
20
+ qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
24
+ * callers must catch this; we return the 64-bit constant value defined
21
return 0;
25
+ * for AArch64.
22
}
26
*
23
27
* cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
24
@@ -XXX,XX +XXX,XX @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
28
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
25
val |= PLAT_DDR_CFG_MHZ;
29
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
return val;
30
index XXXXXXX..XXXXXXX 100644
27
default:
31
--- a/target/arm/translate-a64.c
28
- qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx,
32
+++ b/target/arm/translate-a64.c
29
+ qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
33
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
30
addr & 0xffff);
31
return 0;
32
}
33
@@ -XXX,XX +XXX,XX @@ static void boston_platreg_write(void *opaque, hwaddr addr,
34
uint64_t val, unsigned size)
35
{
34
{
36
if (size != 4) {
35
int rd = extract32(insn, 0, 5);
37
- qemu_log_mask(LOG_UNIMP, "%uB platform register write", size);
36
int cmode = extract32(insn, 12, 4);
38
+ qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
37
- int cmode_3_1 = extract32(cmode, 1, 3);
38
- int cmode_0 = extract32(cmode, 0, 1);
39
int o2 = extract32(insn, 11, 1);
40
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
41
bool is_neg = extract32(insn, 29, 1);
42
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
39
return;
43
return;
40
}
44
}
41
45
42
@@ -XXX,XX +XXX,XX @@ static void boston_platreg_write(void *opaque, hwaddr addr,
46
- /* See AdvSIMDExpandImm() in ARM ARM */
47
- switch (cmode_3_1) {
48
- case 0: /* Replicate(Zeros(24):imm8, 2) */
49
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
50
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
51
- case 3: /* Replicate(imm8:Zeros(24), 2) */
52
- {
53
- int shift = cmode_3_1 * 8;
54
- imm = bitfield_replicate(abcdefgh << shift, 32);
55
- break;
56
- }
57
- case 4: /* Replicate(Zeros(8):imm8, 4) */
58
- case 5: /* Replicate(imm8:Zeros(8), 4) */
59
- {
60
- int shift = (cmode_3_1 & 0x1) * 8;
61
- imm = bitfield_replicate(abcdefgh << shift, 16);
62
- break;
63
- }
64
- case 6:
65
- if (cmode_0) {
66
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
67
- imm = (abcdefgh << 16) | 0xffff;
68
- } else {
69
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
70
- imm = (abcdefgh << 8) | 0xff;
71
- }
72
- imm = bitfield_replicate(imm, 32);
73
- break;
74
- case 7:
75
- if (!cmode_0 && !is_neg) {
76
- imm = bitfield_replicate(abcdefgh, 8);
77
- } else if (!cmode_0 && is_neg) {
78
- int i;
79
- imm = 0;
80
- for (i = 0; i < 8; i++) {
81
- if ((abcdefgh) & (1 << i)) {
82
- imm |= 0xffULL << (i * 8);
83
- }
84
- }
85
- } else if (cmode_0) {
86
- if (is_neg) {
87
- imm = (abcdefgh & 0x3f) << 48;
88
- if (abcdefgh & 0x80) {
89
- imm |= 0x8000000000000000ULL;
90
- }
91
- if (abcdefgh & 0x40) {
92
- imm |= 0x3fc0000000000000ULL;
93
- } else {
94
- imm |= 0x4000000000000000ULL;
95
- }
96
- } else {
97
- if (o2) {
98
- /* FMOV (vector, immediate) - half-precision */
99
- imm = vfp_expand_imm(MO_16, abcdefgh);
100
- /* now duplicate across the lanes */
101
- imm = bitfield_replicate(imm, 16);
102
- } else {
103
- imm = (abcdefgh & 0x3f) << 19;
104
- if (abcdefgh & 0x80) {
105
- imm |= 0x80000000;
106
- }
107
- if (abcdefgh & 0x40) {
108
- imm |= 0x3e000000;
109
- } else {
110
- imm |= 0x40000000;
111
- }
112
- imm |= (imm << 32);
113
- }
114
- }
115
- }
116
- break;
117
- default:
118
- g_assert_not_reached();
119
- }
120
-
121
- if (cmode_3_1 != 7 && is_neg) {
122
- imm = ~imm;
123
+ if (cmode == 15 && o2 && !is_neg) {
124
+ /* FMOV (vector, immediate) - half-precision */
125
+ imm = vfp_expand_imm(MO_16, abcdefgh);
126
+ /* now duplicate across the lanes */
127
+ imm = bitfield_replicate(imm, 16);
128
+ } else {
129
+ imm = asimd_imm_const(abcdefgh, cmode, is_neg);
130
}
131
132
if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
133
diff --git a/target/arm/translate.c b/target/arm/translate.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/arm/translate.c
136
+++ b/target/arm/translate.c
137
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
138
case 14:
139
if (op) {
140
/*
141
- * This is the only case where the top and bottom 32 bits
142
- * of the encoded constant differ.
143
+ * This and cmode == 15 op == 1 are the only cases where
144
+ * the top and bottom 32 bits of the encoded constant differ.
145
*/
146
uint64_t imm64 = 0;
147
int n;
148
@@ -XXX,XX +XXX,XX @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)
149
imm |= (imm << 8) | (imm << 16) | (imm << 24);
43
break;
150
break;
44
default:
151
case 15:
45
qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
152
+ if (op) {
46
- " = 0x%" PRIx64, addr & 0xffff, val);
153
+ /* Reserved encoding for AArch32; valid for AArch64 */
47
+ " = 0x%" PRIx64 "\n", addr & 0xffff, val);
154
+ uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48;
155
+ if (imm & 0x80) {
156
+ imm64 |= 0x8000000000000000ULL;
157
+ }
158
+ if (imm & 0x40) {
159
+ imm64 |= 0x3fc0000000000000ULL;
160
+ } else {
161
+ imm64 |= 0x4000000000000000ULL;
162
+ }
163
+ return imm64;
164
+ }
165
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
166
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
48
break;
167
break;
49
}
50
}
51
--
168
--
52
2.17.1
169
2.20.1
53
170
54
171
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/31] target/m68k: Add trailing '\n' to qemu_log() call
[PULL 11/24] target/arm: Use dup_const() instead of bitfield_replicate()
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Use dup_const() instead of bitfield_replicate() in
2
disas_simd_mod_imm().
2
3
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
(We can't replace the other use of bitfield_replicate() in this file,
4
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
5
in logic_imm_decode_wmask(), because that location needs to handle 2
5
Message-id: 20180606152128.449-10-f4bug@amsat.org
6
and 4 bit elements, which dup_const() cannot.)
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
7
---
11
---
8
target/m68k/translate.c | 2 +-
12
target/arm/translate-a64.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
10
14
11
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/translate.c
17
--- a/target/arm/translate-a64.c
14
+++ b/target/m68k/translate.c
18
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ DISAS_INSN(undef)
19
@@ -XXX,XX +XXX,XX @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
16
/* ??? This is both instructions that are as yet unimplemented
20
/* FMOV (vector, immediate) - half-precision */
17
for the 680x0 series, as well as those that are implemented
21
imm = vfp_expand_imm(MO_16, abcdefgh);
18
but actually illegal for CPU32 or pre-68020. */
22
/* now duplicate across the lanes */
19
- qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
23
- imm = bitfield_replicate(imm, 16);
20
+ qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
24
+ imm = dup_const(MO_16, imm);
21
insn, s->insn_pc);
25
} else {
22
gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
26
imm = asimd_imm_const(abcdefgh, cmode, is_neg);
23
}
27
}
24
--
28
--
25
2.17.1
29
2.20.1
26
30
27
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/31] sdcard: Reflect when the Spec v3 is supported in the Config Register (SCR)
[PULL 12/24] target/arm: Implement MVE logical immediate insns
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE logical-immediate insns (VMOV, VMVN,
2
VORR and VBIC). These have essentially the same encoding
3
as their Neon equivalents, and we implement the decode
4
in the same way.
2
5
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20180607180641.874-6-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
7
---
9
---
8
include/hw/sd/sd.h | 1 +
10
target/arm/helper-mve.h | 4 +++
9
hw/sd/sd.c | 7 +++++--
11
target/arm/mve.decode | 17 +++++++++++++
10
2 files changed, 6 insertions(+), 2 deletions(-)
12
target/arm/mve_helper.c | 24 ++++++++++++++++++
13
target/arm/translate-mve.c | 50 ++++++++++++++++++++++++++++++++++++++
14
4 files changed, 95 insertions(+)
11
15
12
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/sd/sd.h
18
--- a/target/arm/helper-mve.h
15
+++ b/include/hw/sd/sd.h
19
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32)
21
DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
+
25
+DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
26
+DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
27
+DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
28
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/mve.decode
31
+++ b/target/arm/mve.decode
16
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
17
enum SDPhySpecificationVersion {
33
# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
18
SD_PHY_SPECv1_10_VERS = 1,
34
%size_28 28:1 !function=plus_1
19
SD_PHY_SPECv2_00_VERS = 2,
35
20
+ SD_PHY_SPECv3_01_VERS = 3,
36
+# 1imm format immediate
21
};
37
+%imm_28_16_0 28:1 16:3 0:4
22
38
+
23
typedef enum {
39
&vldr_vstr rn qd imm p a w size l u
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
40
&1op qd qm size
41
&2op qd qm qn size
42
&2scalar qd qn rm size
43
+&1imm qd imm cmode op
44
45
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
46
# Note that both Rn and Qd are 3 bits only (no D bit)
47
@@ -XXX,XX +XXX,XX @@
48
@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0
49
@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \
50
size=%size_28
51
+@1imm .... .... .... .... .... cmode:4 .. op:1 . .... &1imm qd=%qd imm=%imm_28_16_0
52
53
# The _rev suffix indicates that Vn and Vm are reversed. This is
54
# the case for shifts. In the Arm ARM these insns are documented
55
@@ -XXX,XX +XXX,XX @@ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rd
56
# Predicate operations
57
%mask_22_13 22:1 13:3
58
VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
59
+
60
+# Logical immediate operations (1 reg and modified-immediate)
61
+
62
+# The cmode/op bits here decode VORR/VBIC/VMOV/VMVN, but
63
+# not in a way we can conveniently represent in decodetree without
64
+# a lot of repetition:
65
+# VORR: op=0, (cmode & 1) && cmode < 12
66
+# VBIC: op=1, (cmode & 1) && cmode < 12
67
+# VMOV: everything else
68
+# So we have a single decode line and check the cmode/op in the
69
+# trans function.
70
+Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
71
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
25
index XXXXXXX..XXXXXXX 100644
72
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
73
--- a/target/arm/mve_helper.c
27
+++ b/hw/sd/sd.c
74
+++ b/target/arm/mve_helper.c
28
@@ -XXX,XX +XXX,XX @@ static void sd_set_scr(SDState *sd)
75
@@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG)
29
if (sd->spec_version == SD_PHY_SPECv1_10_VERS) {
76
DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH)
30
sd->scr[0] |= 1; /* Spec Version 1.10 */
77
DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS)
31
} else {
78
32
- sd->scr[0] |= 2; /* Spec Version 2.00 */
79
+/*
33
+ sd->scr[0] |= 2; /* Spec Version 2.00 or Version 3.0X */
80
+ * 1 operand immediates: Vda is destination and possibly also one source.
34
}
81
+ * All these insns work at 64-bit widths.
35
sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
82
+ */
36
| 0b0101; /* 1-bit or 4-bit width bus modes */
83
+#define DO_1OP_IMM(OP, FN) \
37
sd->scr[2] = 0x00; /* Extended Security is not supported. */
84
+ void HELPER(mve_##OP)(CPUARMState *env, void *vda, uint64_t imm) \
38
+ if (sd->spec_version >= SD_PHY_SPECv3_01_VERS) {
85
+ { \
39
+ sd->scr[2] |= 1 << 7; /* Spec Version 3.0X */
86
+ uint64_t *da = vda; \
87
+ uint16_t mask = mve_element_mask(env); \
88
+ unsigned e; \
89
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
90
+ mergemask(&da[H8(e)], FN(da[H8(e)], imm), mask); \
91
+ } \
92
+ mve_advance_vpt(env); \
40
+ }
93
+ }
41
sd->scr[3] = 0x00;
94
+
42
/* reserved for manufacturer usage */
95
+#define DO_MOVI(N, I) (I)
43
sd->scr[4] = 0x00;
96
+#define DO_ANDI(N, I) ((N) & (I))
44
@@ -XXX,XX +XXX,XX @@ static void sd_realize(DeviceState *dev, Error **errp)
97
+#define DO_ORRI(N, I) ((N) | (I))
45
98
+
46
switch (sd->spec_version) {
99
+DO_1OP_IMM(vmovi, DO_MOVI)
47
case SD_PHY_SPECv1_10_VERS
100
+DO_1OP_IMM(vandi, DO_ANDI)
48
- ... SD_PHY_SPECv2_00_VERS:
101
+DO_1OP_IMM(vorri, DO_ORRI)
49
+ ... SD_PHY_SPECv3_01_VERS:
102
+
50
break;
103
#define DO_2OP(OP, ESIZE, TYPE, FN) \
51
default:
104
void HELPER(glue(mve_, OP))(CPUARMState *env, \
52
error_setg(errp, "Invalid SD card Spec version: %u", sd->spec_version);
105
void *vd, void *vn, void *vm) \
106
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/translate-mve.c
109
+++ b/target/arm/translate-mve.c
110
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
111
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
112
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
113
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
114
+typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
115
116
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
117
static inline long mve_qreg_offset(unsigned reg)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
119
mve_update_eci(s);
120
return true;
121
}
122
+
123
+static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
124
+{
125
+ TCGv_ptr qd;
126
+ uint64_t imm;
127
+
128
+ if (!dc_isar_feature(aa32_mve, s) ||
129
+ !mve_check_qreg_bank(s, a->qd) ||
130
+ !fn) {
131
+ return false;
132
+ }
133
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
134
+ return true;
135
+ }
136
+
137
+ imm = asimd_imm_const(a->imm, a->cmode, a->op);
138
+
139
+ qd = mve_qreg_ptr(a->qd);
140
+ fn(cpu_env, qd, tcg_constant_i64(imm));
141
+ tcg_temp_free_ptr(qd);
142
+ mve_update_eci(s);
143
+ return true;
144
+}
145
+
146
+static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
147
+{
148
+ /* Handle decode of cmode/op here between VORR/VBIC/VMOV */
149
+ MVEGenOneOpImmFn *fn;
150
+
151
+ if ((a->cmode & 1) && a->cmode < 12) {
152
+ if (a->op) {
153
+ /*
154
+ * For op=1, the immediate will be inverted by asimd_imm_const(),
155
+ * so the VBIC becomes a logical AND operation.
156
+ */
157
+ fn = gen_helper_mve_vandi;
158
+ } else {
159
+ fn = gen_helper_mve_vorri;
160
+ }
161
+ } else {
162
+ /* There is one unallocated cmode/op combination in this space */
163
+ if (a->cmode == 15 && a->op == 1) {
164
+ return false;
165
+ }
166
+ /* asimd_imm_const() sorts out VMVNI vs VMOVI for us */
167
+ fn = gen_helper_mve_vmovi;
168
+ }
169
+ return do_1imm(s, a, fn);
170
+}
53
--
171
--
54
2.17.1
172
2.20.1
55
173
56
174
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/31] sdcard: Update the Configuration Register (SCR) to Spec Version 1.10
[PULL 13/24] target/arm: Implement MVE vector shift left by immediate insns
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
2
2
and VQSHLU.
3
The initial implementation is based on the Specs v1.10 (see a1bb27b1e98).
3
4
4
The size-and-immediate encoding here is the same as Neon, and we
5
However the SCR is anouncing the card being v1.01.
5
handle it the same way neon-dp.decode does.
6
6
7
The new chapters added in version 1.10 are:
8
9
4.3.10 Switch function command
10
11
Switch function command (CMD6) 1 is used to switch or expand
12
memory card functions. [...]
13
This is a new feature, introduced in SD physical Layer
14
Specification Version 1.10. Therefore, cards that are
15
compatible with earlier versions of the spec do not support
16
it. The host shall check the "SD_SPEC" field in the SCR
17
register to recognize what version of the spec the card
18
complies with before using CMD6. It is mandatory for SD
19
memory card of Ver1.10 to support CMD6.
20
21
4.3.11 High-Speed mode (25MB/sec interface speed)
22
23
Though the Rev 1.01 SD memory card supports up to 12.5MB/sec
24
interface speed, the speed of 25MB/sec is necessary to support
25
increasing performance needs of the host and because of memory
26
size which continues to grow.
27
To achieve 25MB/sec interface speed, clock rate is increased to
28
50MHz and CLK/CMD/DAT signal timing and circuit conditions are
29
reconsidered and changed from Physical Layer Specification
30
Version 1.01.
31
32
4.3.12 Command system (This chapter is newly added in version 1.10)
33
34
SD commands CMD34-37, CMD50, CMD57 are reserved for SD command
35
system expansion via the switch command.
36
[These commands] will be considered as illegal commands (as
37
defined in revision 1.01 of the SD physical layer specification).
38
39
The SWITCH_FUNCTION is implemented since the first commit, a1bb27b1e98.
40
41
The 25MB/sec High-Speed mode was already updated in d7ecb867529.
42
43
The current implementation does not implements CMD34-37, CMD50 and
44
CMD57, thus these commands already return ILLEGAL.
45
46
With this patch, the SCR register now matches the description of the header:
47
48
* SD Memory Card emulation as defined in the "SD Memory Card Physical
49
* layer specification, Version 1.10."
50
51
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
52
Message-id: 20180607180641.874-2-f4bug@amsat.org
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
55
---
10
---
56
hw/sd/sd.c | 4 ++--
11
target/arm/helper-mve.h | 16 +++++++++++
57
1 file changed, 2 insertions(+), 2 deletions(-)
12
target/arm/mve.decode | 23 +++++++++++++++
58
13
target/arm/mve_helper.c | 57 ++++++++++++++++++++++++++++++++++++++
59
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
target/arm/translate-mve.c | 51 ++++++++++++++++++++++++++++++++++
60
index XXXXXXX..XXXXXXX 100644
15
4 files changed, 147 insertions(+)
61
--- a/hw/sd/sd.c
16
62
+++ b/hw/sd/sd.c
17
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
63
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
18
index XXXXXXX..XXXXXXX 100644
64
19
--- a/target/arm/helper-mve.h
65
static void sd_set_scr(SDState *sd)
20
+++ b/target/arm/helper-mve.h
66
{
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
67
- sd->scr[0] = (0 << 4) /* SCR version 1.0 */
22
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
68
- | 0; /* Spec Versions 1.0 and 1.01 */
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
69
+ sd->scr[0] = (0 << 4) /* SCR structure version 1.0 */
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
70
+ | 1; /* Spec Version 1.10 */
25
+
71
sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
26
+DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
72
| 0b0101; /* 1-bit or 4-bit width bus modes */
27
+DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
73
sd->scr[2] = 0x00; /* Extended Security is not supported. */
28
+DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
+
30
+DEF_HELPER_FLAGS_4(mve_vqshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vqshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+
34
+DEF_HELPER_FLAGS_4(mve_vqshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
+DEF_HELPER_FLAGS_4(mve_vqshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/mve.decode
44
+++ b/target/arm/mve.decode
45
@@ -XXX,XX +XXX,XX @@
46
&2op qd qm qn size
47
&2scalar qd qn rm size
48
&1imm qd imm cmode op
49
+&2shift qd qm shift size
50
51
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
52
# Note that both Rn and Qd are 3 bits only (no D bit)
53
@@ -XXX,XX +XXX,XX @@
54
@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
55
@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn
56
57
+@2_shl_b .... .... .. 001 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
58
+@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
59
+@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
60
+
61
# Vector loads and stores
62
63
# Widening loads and narrowing stores:
64
@@ -XXX,XX +XXX,XX @@ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
65
# So we have a single decode line and check the cmode/op in the
66
# trans function.
67
Vimm_1r 111 . 1111 1 . 00 0 ... ... 0 .... 0 1 . 1 .... @1imm
68
+
69
+# Shifts by immediate
70
+
71
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
72
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
73
+VSHLI 111 0 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
74
+
75
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
76
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
77
+VQSHLI_S 111 0 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
78
+
79
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_b
80
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_h
81
+VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
82
+
83
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
84
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
85
+VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
86
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/mve_helper.c
89
+++ b/target/arm/mve_helper.c
90
@@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
91
WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp)
92
#define DO_UQRSHL_OP(N, M, satp) \
93
WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp)
94
+#define DO_SUQSHL_OP(N, M, satp) \
95
+ WRAP_QRSHL_HELPER(do_suqrshl_bhs, N, M, false, satp)
96
97
DO_2OP_SAT_S(vqshls, DO_SQSHL_OP)
98
DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP)
99
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvsw, 4, uint32_t)
100
DO_VADDV(vaddvub, 1, uint8_t)
101
DO_VADDV(vaddvuh, 2, uint16_t)
102
DO_VADDV(vaddvuw, 4, uint32_t)
103
+
104
+/* Shifts by immediate */
105
+#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
106
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
107
+ void *vm, uint32_t shift) \
108
+ { \
109
+ TYPE *d = vd, *m = vm; \
110
+ uint16_t mask = mve_element_mask(env); \
111
+ unsigned e; \
112
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
113
+ mergemask(&d[H##ESIZE(e)], \
114
+ FN(m[H##ESIZE(e)], shift), mask); \
115
+ } \
116
+ mve_advance_vpt(env); \
117
+ }
118
+
119
+#define DO_2SHIFT_SAT(OP, ESIZE, TYPE, FN) \
120
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
121
+ void *vm, uint32_t shift) \
122
+ { \
123
+ TYPE *d = vd, *m = vm; \
124
+ uint16_t mask = mve_element_mask(env); \
125
+ unsigned e; \
126
+ bool qc = false; \
127
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
128
+ bool sat = false; \
129
+ mergemask(&d[H##ESIZE(e)], \
130
+ FN(m[H##ESIZE(e)], shift, &sat), mask); \
131
+ qc |= sat & mask & 1; \
132
+ } \
133
+ if (qc) { \
134
+ env->vfp.qc[0] = qc; \
135
+ } \
136
+ mve_advance_vpt(env); \
137
+ }
138
+
139
+/* provide unsigned 2-op shift helpers for all sizes */
140
+#define DO_2SHIFT_U(OP, FN) \
141
+ DO_2SHIFT(OP##b, 1, uint8_t, FN) \
142
+ DO_2SHIFT(OP##h, 2, uint16_t, FN) \
143
+ DO_2SHIFT(OP##w, 4, uint32_t, FN)
144
+
145
+#define DO_2SHIFT_SAT_U(OP, FN) \
146
+ DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
147
+ DO_2SHIFT_SAT(OP##h, 2, uint16_t, FN) \
148
+ DO_2SHIFT_SAT(OP##w, 4, uint32_t, FN)
149
+#define DO_2SHIFT_SAT_S(OP, FN) \
150
+ DO_2SHIFT_SAT(OP##b, 1, int8_t, FN) \
151
+ DO_2SHIFT_SAT(OP##h, 2, int16_t, FN) \
152
+ DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
153
+
154
+DO_2SHIFT_U(vshli_u, DO_VSHLU)
155
+DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
156
+DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
157
+DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
158
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/translate-mve.c
161
+++ b/target/arm/translate-mve.c
162
@@ -XXX,XX +XXX,XX @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
163
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
164
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
165
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
166
+typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
167
typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64);
168
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
169
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
170
@@ -XXX,XX +XXX,XX @@ static bool trans_Vimm_1r(DisasContext *s, arg_1imm *a)
171
}
172
return do_1imm(s, a, fn);
173
}
174
+
175
+static bool do_2shift(DisasContext *s, arg_2shift *a, MVEGenTwoOpShiftFn fn,
176
+ bool negateshift)
177
+{
178
+ TCGv_ptr qd, qm;
179
+ int shift = a->shift;
180
+
181
+ if (!dc_isar_feature(aa32_mve, s) ||
182
+ !mve_check_qreg_bank(s, a->qd | a->qm) ||
183
+ !fn) {
184
+ return false;
185
+ }
186
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
187
+ return true;
188
+ }
189
+
190
+ /*
191
+ * When we handle a right shift insn using a left-shift helper
192
+ * which permits a negative shift count to indicate a right-shift,
193
+ * we must negate the shift count.
194
+ */
195
+ if (negateshift) {
196
+ shift = -shift;
197
+ }
198
+
199
+ qd = mve_qreg_ptr(a->qd);
200
+ qm = mve_qreg_ptr(a->qm);
201
+ fn(cpu_env, qd, qm, tcg_constant_i32(shift));
202
+ tcg_temp_free_ptr(qd);
203
+ tcg_temp_free_ptr(qm);
204
+ mve_update_eci(s);
205
+ return true;
206
+}
207
+
208
+#define DO_2SHIFT(INSN, FN, NEGATESHIFT) \
209
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
210
+ { \
211
+ static MVEGenTwoOpShiftFn * const fns[] = { \
212
+ gen_helper_mve_##FN##b, \
213
+ gen_helper_mve_##FN##h, \
214
+ gen_helper_mve_##FN##w, \
215
+ NULL, \
216
+ }; \
217
+ return do_2shift(s, a, fns[a->size], NEGATESHIFT); \
218
+ }
219
+
220
+DO_2SHIFT(VSHLI, vshli_u, false)
221
+DO_2SHIFT(VQSHLI_S, vqshli_s, false)
222
+DO_2SHIFT(VQSHLI_U, vqshli_u, false)
223
+DO_2SHIFT(VQSHLUI, vqshlui_s, false)
74
--
224
--
75
2.17.1
225
2.20.1
76
226
77
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/31] hw/arm: Remove the deprecated xlnx-ep108 machine
[PULL 14/24] target/arm: Implement MVE vector shift right by immediate insns
1
From: Thomas Huth <thuth@redhat.com>
1
Implement the MVE vector shift right by immediate insns VSHRI and
2
VRSHRI. As with Neon, we implement these by using helper functions
3
which perform left shifts but allow negative shift counts to indicate
4
right shifts.
2
5
3
It has been marked as deprecated since QEMU v2.11, so it is time to
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
remove this now. The xlnx-zcu102 machine is very much the same and
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
can be used as a replacement instead.
8
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 12 ++++++++++++
11
target/arm/translate.h | 20 ++++++++++++++++++++
12
target/arm/mve.decode | 28 ++++++++++++++++++++++++++++
13
target/arm/mve_helper.c | 7 +++++++
14
target/arm/translate-mve.c | 5 +++++
15
target/arm/translate-neon.c | 18 ------------------
16
6 files changed, 72 insertions(+), 18 deletions(-)
6
17
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/xlnx-zcu102.c | 62 ++------------------------------------------
12
qemu-doc.texi | 5 ----
13
2 files changed, 2 insertions(+), 65 deletions(-)
14
15
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-zcu102.c
20
--- a/target/arm/helper-mve.h
18
+++ b/hw/arm/xlnx-zcu102.c
21
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
20
#define ZCU102_MACHINE(obj) \
23
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
21
OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
24
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
22
25
23
-#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108")
26
+DEF_HELPER_FLAGS_4(mve_vshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
-#define EP108_MACHINE(obj) \
27
+DEF_HELPER_FLAGS_4(mve_vshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
- OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE)
28
+DEF_HELPER_FLAGS_4(mve_vshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
-
29
+
27
static struct arm_boot_info xlnx_zcu102_binfo;
30
DEF_HELPER_FLAGS_4(mve_vshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
31
DEF_HELPER_FLAGS_4(mve_vshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
static bool zcu102_get_secure(Object *obj, Error **errp)
32
DEF_HELPER_FLAGS_4(mve_vshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
@@ -XXX,XX +XXX,XX @@ static void zcu102_set_virt(Object *obj, bool value, Error **errp)
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
s->virt = value;
34
DEF_HELPER_FLAGS_4(mve_vqshlui_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
DEF_HELPER_FLAGS_4(mve_vqshlui_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
DEF_HELPER_FLAGS_4(mve_vqshlui_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+
38
+DEF_HELPER_FLAGS_4(mve_vrshli_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+DEF_HELPER_FLAGS_4(mve_vrshli_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
+DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+
42
+DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
45
diff --git a/target/arm/translate.h b/target/arm/translate.h
46
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/translate.h
48
+++ b/target/arm/translate.h
49
@@ -XXX,XX +XXX,XX @@ static inline int times_2_plus_1(DisasContext *s, int x)
50
return x * 2 + 1;
32
}
51
}
33
52
34
-static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
53
+static inline int rsub_64(DisasContext *s, int x)
35
+static void xlnx_zcu102_init(MachineState *machine)
54
+{
55
+ return 64 - x;
56
+}
57
+
58
+static inline int rsub_32(DisasContext *s, int x)
59
+{
60
+ return 32 - x;
61
+}
62
+
63
+static inline int rsub_16(DisasContext *s, int x)
64
+{
65
+ return 16 - x;
66
+}
67
+
68
+static inline int rsub_8(DisasContext *s, int x)
69
+{
70
+ return 8 - x;
71
+}
72
+
73
static inline int arm_dc_feature(DisasContext *dc, int feature)
36
{
74
{
37
+ XlnxZCU102 *s = ZCU102_MACHINE(machine);
75
return (dc->features & (1ULL << feature)) != 0;
38
int i;
76
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
39
uint64_t ram_size = machine->ram_size;
77
index XXXXXXX..XXXXXXX 100644
40
78
--- a/target/arm/mve.decode
41
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
79
+++ b/target/arm/mve.decode
42
arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
80
@@ -XXX,XX +XXX,XX @@
81
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
82
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
83
84
+# Right shifts are encoded as N - shift, where N is the element size in bits.
85
+%rshift_i5 16:5 !function=rsub_32
86
+%rshift_i4 16:4 !function=rsub_16
87
+%rshift_i3 16:3 !function=rsub_8
88
+
89
+@2_shr_b .... .... .. 001 ... .... .... .... .... &2shift qd=%qd qm=%qm \
90
+ size=0 shift=%rshift_i3
91
+@2_shr_h .... .... .. 01 .... .... .... .... .... &2shift qd=%qd qm=%qm \
92
+ size=1 shift=%rshift_i4
93
+@2_shr_w .... .... .. 1 ..... .... .... .... .... &2shift qd=%qd qm=%qm \
94
+ size=2 shift=%rshift_i5
95
+
96
# Vector loads and stores
97
98
# Widening loads and narrowing stores:
99
@@ -XXX,XX +XXX,XX @@ VQSHLI_U 111 1 1111 1 . ... ... ... 0 0111 0 1 . 1 ... 0 @2_shl_w
100
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_b
101
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_h
102
VQSHLUI 111 1 1111 1 . ... ... ... 0 0110 0 1 . 1 ... 0 @2_shl_w
103
+
104
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
105
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
106
+VSHRI_S 111 0 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
107
+
108
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_b
109
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_h
110
+VSHRI_U 111 1 1111 1 . ... ... ... 0 0000 0 1 . 1 ... 0 @2_shr_w
111
+
112
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
113
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
114
+VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
115
+
116
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
117
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
118
+VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
119
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/mve_helper.c
122
+++ b/target/arm/mve_helper.c
123
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
124
DO_2SHIFT(OP##b, 1, uint8_t, FN) \
125
DO_2SHIFT(OP##h, 2, uint16_t, FN) \
126
DO_2SHIFT(OP##w, 4, uint32_t, FN)
127
+#define DO_2SHIFT_S(OP, FN) \
128
+ DO_2SHIFT(OP##b, 1, int8_t, FN) \
129
+ DO_2SHIFT(OP##h, 2, int16_t, FN) \
130
+ DO_2SHIFT(OP##w, 4, int32_t, FN)
131
132
#define DO_2SHIFT_SAT_U(OP, FN) \
133
DO_2SHIFT_SAT(OP##b, 1, uint8_t, FN) \
134
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvuw, 4, uint32_t)
135
DO_2SHIFT_SAT(OP##w, 4, int32_t, FN)
136
137
DO_2SHIFT_U(vshli_u, DO_VSHLU)
138
+DO_2SHIFT_S(vshli_s, DO_VSHLS)
139
DO_2SHIFT_SAT_U(vqshli_u, DO_UQSHL_OP)
140
DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
141
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
142
+DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
143
+DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
144
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
145
index XXXXXXX..XXXXXXX 100644
146
--- a/target/arm/translate-mve.c
147
+++ b/target/arm/translate-mve.c
148
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHLI, vshli_u, false)
149
DO_2SHIFT(VQSHLI_S, vqshli_s, false)
150
DO_2SHIFT(VQSHLI_U, vqshli_u, false)
151
DO_2SHIFT(VQSHLUI, vqshlui_s, false)
152
+/* These right shifts use a left-shift helper with negated shift count */
153
+DO_2SHIFT(VSHRI_S, vshli_s, true)
154
+DO_2SHIFT(VSHRI_U, vshli_u, true)
155
+DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
+DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/target/arm/translate-neon.c
160
+++ b/target/arm/translate-neon.c
161
@@ -XXX,XX +XXX,XX @@ static inline int plus1(DisasContext *s, int x)
162
return x + 1;
43
}
163
}
44
164
45
-static void xlnx_ep108_init(MachineState *machine)
165
-static inline int rsub_64(DisasContext *s, int x)
46
-{
166
-{
47
- XlnxZCU102 *s = EP108_MACHINE(machine);
167
- return 64 - x;
48
-
49
- if (!qtest_enabled()) {
50
- info_report("The Xilinx EP108 machine is deprecated, please use the "
51
- "ZCU102 machine (which has the same features) instead.");
52
- }
53
-
54
- xlnx_zynqmp_init(s, machine);
55
-}
168
-}
56
-
169
-
57
-static void xlnx_ep108_machine_instance_init(Object *obj)
170
-static inline int rsub_32(DisasContext *s, int x)
58
-{
171
-{
59
- XlnxZCU102 *s = EP108_MACHINE(obj);
172
- return 32 - x;
60
-
173
-}
61
- /* EP108, we don't support setting secure or virt */
174
-static inline int rsub_16(DisasContext *s, int x)
62
- s->secure = false;
175
-{
63
- s->virt = false;
176
- return 16 - x;
177
-}
178
-static inline int rsub_8(DisasContext *s, int x)
179
-{
180
- return 8 - x;
64
-}
181
-}
65
-
182
-
66
-static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
183
static inline int neon_3same_fp_size(DisasContext *s, int x)
67
-{
68
- MachineClass *mc = MACHINE_CLASS(oc);
69
-
70
- mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)";
71
- mc->init = xlnx_ep108_init;
72
- mc->block_default_type = IF_IDE;
73
- mc->units_per_default_bus = 1;
74
- mc->ignore_memory_transaction_failures = true;
75
- mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
76
- mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
77
-}
78
-
79
-static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
80
- .name = MACHINE_TYPE_NAME("xlnx-ep108"),
81
- .parent = TYPE_MACHINE,
82
- .class_init = xlnx_ep108_machine_class_init,
83
- .instance_init = xlnx_ep108_machine_instance_init,
84
- .instance_size = sizeof(XlnxZCU102),
85
-};
86
-
87
-static void xlnx_ep108_machine_init_register_types(void)
88
-{
89
- type_register_static(&xlnx_ep108_machine_init_typeinfo);
90
-}
91
-
92
-static void xlnx_zcu102_init(MachineState *machine)
93
-{
94
- XlnxZCU102 *s = ZCU102_MACHINE(machine);
95
-
96
- xlnx_zynqmp_init(s, machine);
97
-}
98
-
99
static void xlnx_zcu102_machine_instance_init(Object *obj)
100
{
184
{
101
XlnxZCU102 *s = ZCU102_MACHINE(obj);
185
/* Convert 0==fp32, 1==fp16 into a MO_* value */
102
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init_register_types(void)
103
}
104
105
type_init(xlnx_zcu102_machine_init_register_types)
106
-type_init(xlnx_ep108_machine_init_register_types)
107
diff --git a/qemu-doc.texi b/qemu-doc.texi
108
index XXXXXXX..XXXXXXX 100644
109
--- a/qemu-doc.texi
110
+++ b/qemu-doc.texi
111
@@ -XXX,XX +XXX,XX @@ support page sizes < 4096 any longer.
112
113
@section System emulator machines
114
115
-@subsection Xilinx EP108 (since 2.11.0)
116
-
117
-The ``xlnx-ep108'' machine has been replaced by the ``xlnx-zcu102'' machine.
118
-The ``xlnx-zcu102'' machine has the same features and capabilites in QEMU.
119
-
120
@section Block device options
121
122
@subsection "backing": "" (since 2.12.0)
123
--
186
--
124
2.17.1
187
2.20.1
125
188
126
189
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/31] aspeed: add support for the witherspoon-bmc board
[PULL 15/24] target/arm: Implement MVE VSHLL
1
From: Cédric Le Goater <clg@kaod.org>
1
Implement the MVE VHLL (vector shift left long) insn. This has two
2
encodings: the T1 encoding is the usual shift-by-immediate format,
3
and the T2 encoding is a special case where the shift count is always
4
equal to the element size.
2
5
3
The Witherspoon boards are OpenPOWER system hosting POWER9 Processors.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Add support for their BMC including a couple of I2C devices as found
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
on real HW.
8
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
9
---
10
target/arm/helper-mve.h | 9 +++++++
11
target/arm/mve.decode | 53 +++++++++++++++++++++++++++++++++++---
12
target/arm/mve_helper.c | 32 +++++++++++++++++++++++
13
target/arm/translate-mve.c | 15 +++++++++++
14
4 files changed, 105 insertions(+), 4 deletions(-)
6
15
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
9
Message-id: 20180530064049.27976-3-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 49 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
18
--- a/target/arm/helper-mve.h
18
+++ b/hw/arm/aspeed.c
19
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ enum {
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshli_sw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
PALMETTO_BMC,
21
DEF_HELPER_FLAGS_4(mve_vrshli_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
AST2500_EVB,
22
DEF_HELPER_FLAGS_4(mve_vrshli_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
ROMULUS_BMC,
23
DEF_HELPER_FLAGS_4(mve_vrshli_uw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ WITHERSPOON_BMC,
24
};
25
26
/* Palmetto hardware value: 0x120CE416 */
27
@@ -XXX,XX +XXX,XX @@ enum {
28
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
29
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
30
31
+/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
32
+#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
33
+
24
+
34
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
25
+DEF_HELPER_FLAGS_4(mve_vshllbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
35
static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
26
+DEF_HELPER_FLAGS_4(mve_vshllbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc);
27
+DEF_HELPER_FLAGS_4(mve_vshllbub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
28
+DEF_HELPER_FLAGS_4(mve_vshllbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
static const AspeedBoardConfig aspeed_boards[] = {
29
+DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
[PALMETTO_BMC] = {
30
+DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
31
+DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
.spi_model = "mx66l1g45g",
32
+DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
.num_cs = 2,
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
43
},
34
index XXXXXXX..XXXXXXX 100644
44
+ [WITHERSPOON_BMC] = {
35
--- a/target/arm/mve.decode
45
+ .soc_name = "ast2500-a1",
36
+++ b/target/arm/mve.decode
46
+ .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
37
@@ -XXX,XX +XXX,XX @@
47
+ .fmc_model = "mx25l25635e",
38
@2_shl_h .... .... .. 01 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
48
+ .spi_model = "mx66l1g45g",
39
@2_shl_w .... .... .. 1 shift:5 .... .... .... .... &2shift qd=%qd qm=%qm size=2
49
+ .num_cs = 2,
40
50
+ .i2c_init = witherspoon_bmc_i2c_init,
41
+@2_shll_b .... .... ... 01 shift:3 .... .... .... .... &2shift qd=%qd qm=%qm size=0
51
+ },
42
+@2_shll_h .... .... ... 1 shift:4 .... .... .... .... &2shift qd=%qd qm=%qm size=1
52
};
43
+# VSHLL encoding T2 where shift == esize
53
44
+@2_shll_esize_b .... .... .... 00 .. .... .... .... .... &2shift \
54
#define FIRMWARE_ADDR 0x0
45
+ qd=%qd qm=%qm size=0 shift=8
55
@@ -XXX,XX +XXX,XX @@ static const TypeInfo romulus_bmc_type = {
46
+@2_shll_esize_h .... .... .... 01 .. .... .... .... .... &2shift \
56
.class_init = romulus_bmc_class_init,
47
+ qd=%qd qm=%qm size=1 shift=16
57
};
48
+
58
49
# Right shifts are encoded as N - shift, where N is the element size in bits.
59
+static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
50
%rshift_i5 16:5 !function=rsub_32
51
%rshift_i4 16:4 !function=rsub_16
52
@@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
53
VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op
54
VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op
55
56
-VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
57
-VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
58
+# The VSHLL T2 encoding is not a @2op pattern, but is here because it
59
+# overlaps what would be size=0b11 VMULH/VRMULH
60
+{
60
+{
61
+ AspeedSoCState *soc = &bmc->soc;
61
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
62
+
62
+ VSHLL_BS 111 0 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
63
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
63
64
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
64
-VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
65
+
65
-VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
66
+ /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
66
+ VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
67
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp105", 0x4a);
68
+}
67
+}
69
+
68
+
70
+static void witherspoon_bmc_init(MachineState *machine)
71
+{
69
+{
72
+ aspeed_board_init(machine, &aspeed_boards[WITHERSPOON_BMC]);
70
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_b
71
+ VSHLL_BU 111 1 1110 0 . 11 .. 01 ... 0 1110 0 0 . 0 ... 1 @2_shll_esize_h
72
+
73
+ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op
73
+}
74
+}
74
+
75
+
75
+static void witherspoon_bmc_class_init(ObjectClass *oc, void *data)
76
+{
76
+{
77
+ MachineClass *mc = MACHINE_CLASS(oc);
77
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
78
+ VSHLL_TS 111 0 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
78
+
79
+
79
+ mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
80
+ VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
80
+ mc->init = witherspoon_bmc_init;
81
+ mc->max_cpus = 1;
82
+ mc->no_sdcard = 1;
83
+ mc->no_floppy = 1;
84
+ mc->no_cdrom = 1;
85
+ mc->no_parallel = 1;
86
+}
81
+}
87
+
82
+
88
+static const TypeInfo witherspoon_bmc_type = {
83
+{
89
+ .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
84
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_b
90
+ .parent = TYPE_MACHINE,
85
+ VSHLL_TU 111 1 1110 0 . 11 .. 01 ... 1 1110 0 0 . 0 ... 1 @2_shll_esize_h
91
+ .class_init = witherspoon_bmc_class_init,
92
+};
93
+
86
+
94
static void aspeed_machine_init(void)
87
+ VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op
95
{
88
+}
96
type_register_static(&palmetto_bmc_type);
89
97
type_register_static(&ast2500_evb_type);
90
VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
98
type_register_static(&romulus_bmc_type);
91
VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op
99
+ type_register_static(&witherspoon_bmc_type);
92
@@ -XXX,XX +XXX,XX @@ VRSHRI_S 111 0 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
100
}
93
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_b
101
94
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_h
102
type_init(aspeed_machine_init)
95
VRSHRI_U 111 1 1111 1 . ... ... ... 0 0010 0 1 . 1 ... 0 @2_shr_w
96
+
97
+# VSHLL T1 encoding; the T2 VSHLL encoding is elsewhere in this file
98
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
99
+VSHLL_BS 111 0 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
100
+
101
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_b
102
+VSHLL_BU 111 1 1110 1 . 1 .. ... ... 0 1111 0 1 . 0 ... 0 @2_shll_h
103
+
104
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
105
+VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
106
+
107
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
108
+VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
109
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
110
index XXXXXXX..XXXXXXX 100644
111
--- a/target/arm/mve_helper.c
112
+++ b/target/arm/mve_helper.c
113
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshli_s, DO_SQSHL_OP)
114
DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
115
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
116
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
117
+
118
+/*
119
+ * Long shifts taking half-sized inputs from top or bottom of the input
120
+ * vector and producing a double-width result. ESIZE, TYPE are for
121
+ * the input, and LESIZE, LTYPE for the output.
122
+ * Unlike the normal shift helpers, we do not handle negative shift counts,
123
+ * because the long shift is strictly left-only.
124
+ */
125
+#define DO_VSHLL(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE) \
126
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
127
+ void *vm, uint32_t shift) \
128
+ { \
129
+ LTYPE *d = vd; \
130
+ TYPE *m = vm; \
131
+ uint16_t mask = mve_element_mask(env); \
132
+ unsigned le; \
133
+ assert(shift <= 16); \
134
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
135
+ LTYPE r = (LTYPE)m[H##ESIZE(le * 2 + TOP)] << shift; \
136
+ mergemask(&d[H##LESIZE(le)], r, mask); \
137
+ } \
138
+ mve_advance_vpt(env); \
139
+ }
140
+
141
+#define DO_VSHLL_ALL(OP, TOP) \
142
+ DO_VSHLL(OP##sb, TOP, 1, int8_t, 2, int16_t) \
143
+ DO_VSHLL(OP##ub, TOP, 1, uint8_t, 2, uint16_t) \
144
+ DO_VSHLL(OP##sh, TOP, 2, int16_t, 4, int32_t) \
145
+ DO_VSHLL(OP##uh, TOP, 2, uint16_t, 4, uint32_t) \
146
+
147
+DO_VSHLL_ALL(vshllb, false)
148
+DO_VSHLL_ALL(vshllt, true)
149
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/target/arm/translate-mve.c
152
+++ b/target/arm/translate-mve.c
153
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_S, vshli_s, true)
154
DO_2SHIFT(VSHRI_U, vshli_u, true)
155
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
156
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
157
+
158
+#define DO_VSHLL(INSN, FN) \
159
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
160
+ { \
161
+ static MVEGenTwoOpShiftFn * const fns[] = { \
162
+ gen_helper_mve_##FN##b, \
163
+ gen_helper_mve_##FN##h, \
164
+ }; \
165
+ return do_2shift(s, a, fns[a->size], false); \
166
+ }
167
+
168
+DO_VSHLL(VSHLL_BS, vshllbs)
169
+DO_VSHLL(VSHLL_BU, vshllbu)
170
+DO_VSHLL(VSHLL_TS, vshllts)
171
+DO_VSHLL(VSHLL_TU, vshlltu)
103
--
172
--
104
2.17.1
173
2.20.1
105
174
106
175
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/31] target/xtensa: Add trailing '\n' to qemu_log() calls
[PULL 16/24] target/arm: Implement MVE VSRI, VSLI
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE VSRI and VSLI insns, which perform a
2
shift-and-insert operation.
2
3
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
5
Message-id: 20180606152128.449-12-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
7
---
7
---
8
target/xtensa/translate.c | 6 +++---
8
target/arm/helper-mve.h | 8 ++++++++
9
1 file changed, 3 insertions(+), 3 deletions(-)
9
target/arm/mve.decode | 9 ++++++++
10
target/arm/mve_helper.c | 42 ++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-mve.c | 3 +++
12
4 files changed, 62 insertions(+)
10
13
11
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
14
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
12
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
13
--- a/target/xtensa/translate.c
16
--- a/target/arm/helper-mve.h
14
+++ b/target/xtensa/translate.c
17
+++ b/target/arm/helper-mve.h
15
@@ -XXX,XX +XXX,XX @@ static void translate_rur(DisasContext *dc, const uint32_t arg[],
18
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
16
if (uregnames[par[0]].name) {
19
DEF_HELPER_FLAGS_4(mve_vshlltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
17
tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]);
20
DEF_HELPER_FLAGS_4(mve_vshlltub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
18
} else {
21
DEF_HELPER_FLAGS_4(mve_vshlltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
19
- qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", par[0]);
22
+
20
+ qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]);
23
+DEF_HELPER_FLAGS_4(mve_vsrib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
}
24
+DEF_HELPER_FLAGS_4(mve_vsrih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
}
25
+DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
}
26
+
24
@@ -XXX,XX +XXX,XX @@ static void translate_slli(DisasContext *dc, const uint32_t arg[],
27
+DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
{
28
+DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
if (gen_window_check2(dc, arg[0], arg[1])) {
29
+DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
if (arg[2] == 32) {
30
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
28
- qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined",
31
index XXXXXXX..XXXXXXX 100644
29
+ qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
32
--- a/target/arm/mve.decode
30
arg[0], arg[1]);
33
+++ b/target/arm/mve.decode
31
}
34
@@ -XXX,XX +XXX,XX @@ VSHLL_TS 111 0 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
32
tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f);
35
33
@@ -XXX,XX +XXX,XX @@ static void translate_wur(DisasContext *dc, const uint32_t arg[],
36
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_b
34
if (uregnames[par[0]].name) {
37
VSHLL_TU 111 1 1110 1 . 1 .. ... ... 1 1111 0 1 . 0 ... 0 @2_shll_h
35
gen_wur(par[0], cpu_R[arg[0]]);
38
+
36
} else {
39
+# Shift-and-insert
37
- qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", par[0]);
40
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_b
38
+ qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]);
41
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_h
39
}
42
+VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
40
}
43
+
41
}
44
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
45
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
46
+VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
47
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/mve_helper.c
50
+++ b/target/arm/mve_helper.c
51
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_SAT_S(vqshlui_s, DO_SUQSHL_OP)
52
DO_2SHIFT_U(vrshli_u, DO_VRSHLU)
53
DO_2SHIFT_S(vrshli_s, DO_VRSHLS)
54
55
+/* Shift-and-insert; we always work with 64 bits at a time */
56
+#define DO_2SHIFT_INSERT(OP, ESIZE, SHIFTFN, MASKFN) \
57
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
58
+ void *vm, uint32_t shift) \
59
+ { \
60
+ uint64_t *d = vd, *m = vm; \
61
+ uint16_t mask; \
62
+ uint64_t shiftmask; \
63
+ unsigned e; \
64
+ if (shift == 0 || shift == ESIZE * 8) { \
65
+ /* \
66
+ * Only VSLI can shift by 0; only VSRI can shift by <dt>. \
67
+ * The generic logic would give the right answer for 0 but \
68
+ * fails for <dt>. \
69
+ */ \
70
+ goto done; \
71
+ } \
72
+ assert(shift < ESIZE * 8); \
73
+ mask = mve_element_mask(env); \
74
+ /* ESIZE / 2 gives the MO_* value if ESIZE is in [1,2,4] */ \
75
+ shiftmask = dup_const(ESIZE / 2, MASKFN(ESIZE * 8, shift)); \
76
+ for (e = 0; e < 16 / 8; e++, mask >>= 8) { \
77
+ uint64_t r = (SHIFTFN(m[H8(e)], shift) & shiftmask) | \
78
+ (d[H8(e)] & ~shiftmask); \
79
+ mergemask(&d[H8(e)], r, mask); \
80
+ } \
81
+done: \
82
+ mve_advance_vpt(env); \
83
+ }
84
+
85
+#define DO_SHL(N, SHIFT) ((N) << (SHIFT))
86
+#define DO_SHR(N, SHIFT) ((N) >> (SHIFT))
87
+#define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT))
88
+#define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT))
89
+
90
+DO_2SHIFT_INSERT(vsrib, 1, DO_SHR, SHR_MASK)
91
+DO_2SHIFT_INSERT(vsrih, 2, DO_SHR, SHR_MASK)
92
+DO_2SHIFT_INSERT(vsriw, 4, DO_SHR, SHR_MASK)
93
+DO_2SHIFT_INSERT(vslib, 1, DO_SHL, SHL_MASK)
94
+DO_2SHIFT_INSERT(vslih, 2, DO_SHL, SHL_MASK)
95
+DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
96
+
97
/*
98
* Long shifts taking half-sized inputs from top or bottom of the input
99
* vector and producing a double-width result. ESIZE, TYPE are for
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/translate-mve.c
103
+++ b/target/arm/translate-mve.c
104
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT(VSHRI_U, vshli_u, true)
105
DO_2SHIFT(VRSHRI_S, vrshli_s, true)
106
DO_2SHIFT(VRSHRI_U, vrshli_u, true)
107
108
+DO_2SHIFT(VSRI, vsri, false)
109
+DO_2SHIFT(VSLI, vsli, false)
110
+
111
#define DO_VSHLL(INSN, FN) \
112
static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
113
{ \
42
--
114
--
43
2.17.1
115
2.20.1
44
116
45
117
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/31] smbus: add a smbus_eeprom_init_one() routine
[PULL 17/24] target/arm: Implement MVE VSHRN, VRSHRN
1
From: Cédric Le Goater <clg@kaod.org>
1
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
2
2
3
This is an helper routine to add a single EEPROM on an I2C bus. It can
3
do_urshr() is borrowed from sve_helper.c.
4
be directly used by smbus_eeprom_init() which adds a certain number of
5
EEPROMs on mips and x86 machines.
6
4
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180530064049.27976-5-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
11
---
8
---
12
include/hw/i2c/smbus.h | 1 +
9
target/arm/helper-mve.h | 10 ++++++++++
13
hw/i2c/smbus_eeprom.c | 16 +++++++++++-----
10
target/arm/mve.decode | 11 +++++++++++
14
2 files changed, 12 insertions(+), 5 deletions(-)
11
target/arm/mve_helper.c | 40 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 15 ++++++++++++++
13
4 files changed, 76 insertions(+)
15
14
16
diff --git a/include/hw/i2c/smbus.h b/include/hw/i2c/smbus.h
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/i2c/smbus.h
17
--- a/target/arm/helper-mve.h
19
+++ b/include/hw/i2c/smbus.h
18
+++ b/target/arm/helper-mve.h
20
@@ -XXX,XX +XXX,XX @@ int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data);
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsriw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
20
DEF_HELPER_FLAGS_4(mve_vslib, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
int len);
21
DEF_HELPER_FLAGS_4(mve_vslih, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
22
DEF_HELPER_FLAGS_4(mve_vsliw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf);
23
+
25
void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
24
+DEF_HELPER_FLAGS_4(mve_vshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
const uint8_t *eeprom_spd, int size);
25
+DEF_HELPER_FLAGS_4(mve_vshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
27
26
+DEF_HELPER_FLAGS_4(mve_vshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
27
+DEF_HELPER_FLAGS_4(mve_vshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
+
29
+DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
+DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
29
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/i2c/smbus_eeprom.c
35
--- a/target/arm/mve.decode
31
+++ b/hw/i2c/smbus_eeprom.c
36
+++ b/target/arm/mve.decode
32
@@ -XXX,XX +XXX,XX @@ static void smbus_eeprom_register_types(void)
37
@@ -XXX,XX +XXX,XX @@ VSRI 111 1 1111 1 . ... ... ... 0 0100 0 1 . 1 ... 0 @2_shr_w
33
38
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_b
34
type_init(smbus_eeprom_register_types)
39
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_h
35
40
VSLI 111 1 1111 1 . ... ... ... 0 0101 0 1 . 1 ... 0 @2_shl_w
36
+void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
41
+
42
+# Narrowing shifts (which only support b and h sizes)
43
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
44
+VSHRNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
45
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
46
+VSHRNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
47
+
48
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
49
+VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
50
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
51
+VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
52
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/mve_helper.c
55
+++ b/target/arm/mve_helper.c
56
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_INSERT(vsliw, 4, DO_SHL, SHL_MASK)
57
58
DO_VSHLL_ALL(vshllb, false)
59
DO_VSHLL_ALL(vshllt, true)
60
+
61
+/*
62
+ * Narrowing right shifts, taking a double sized input, shifting it
63
+ * and putting the result in either the top or bottom half of the output.
64
+ * ESIZE, TYPE are the output, and LESIZE, LTYPE the input.
65
+ */
66
+#define DO_VSHRN(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
67
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
68
+ void *vm, uint32_t shift) \
69
+ { \
70
+ LTYPE *m = vm; \
71
+ TYPE *d = vd; \
72
+ uint16_t mask = mve_element_mask(env); \
73
+ unsigned le; \
74
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
75
+ TYPE r = FN(m[H##LESIZE(le)], shift); \
76
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
77
+ } \
78
+ mve_advance_vpt(env); \
79
+ }
80
+
81
+#define DO_VSHRN_ALL(OP, FN) \
82
+ DO_VSHRN(OP##bb, false, 1, uint8_t, 2, uint16_t, FN) \
83
+ DO_VSHRN(OP##bh, false, 2, uint16_t, 4, uint32_t, FN) \
84
+ DO_VSHRN(OP##tb, true, 1, uint8_t, 2, uint16_t, FN) \
85
+ DO_VSHRN(OP##th, true, 2, uint16_t, 4, uint32_t, FN)
86
+
87
+static inline uint64_t do_urshr(uint64_t x, unsigned sh)
37
+{
88
+{
38
+ DeviceState *dev;
89
+ if (likely(sh < 64)) {
39
+
90
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
40
+ dev = qdev_create((BusState *) smbus, "smbus-eeprom");
91
+ } else if (sh == 64) {
41
+ qdev_prop_set_uint8(dev, "address", address);
92
+ return x >> 63;
42
+ qdev_prop_set_ptr(dev, "data", eeprom_buf);
93
+ } else {
43
+ qdev_init_nofail(dev);
94
+ return 0;
95
+ }
44
+}
96
+}
45
+
97
+
46
void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
98
+DO_VSHRN_ALL(vshrn, DO_SHR)
47
const uint8_t *eeprom_spd, int eeprom_spd_size)
99
+DO_VSHRN_ALL(vrshrn, do_urshr)
48
{
100
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
49
@@ -XXX,XX +XXX,XX @@ void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
101
index XXXXXXX..XXXXXXX 100644
50
}
102
--- a/target/arm/translate-mve.c
51
103
+++ b/target/arm/translate-mve.c
52
for (i = 0; i < nb_eeprom; i++) {
104
@@ -XXX,XX +XXX,XX @@ DO_VSHLL(VSHLL_BS, vshllbs)
53
- DeviceState *eeprom;
105
DO_VSHLL(VSHLL_BU, vshllbu)
54
- eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
106
DO_VSHLL(VSHLL_TS, vshllts)
55
- qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
107
DO_VSHLL(VSHLL_TU, vshlltu)
56
- qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
108
+
57
- qdev_init_nofail(eeprom);
109
+#define DO_2SHIFT_N(INSN, FN) \
58
+ smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256));
110
+ static bool trans_##INSN(DisasContext *s, arg_2shift *a) \
59
}
111
+ { \
60
}
112
+ static MVEGenTwoOpShiftFn * const fns[] = { \
113
+ gen_helper_mve_##FN##b, \
114
+ gen_helper_mve_##FN##h, \
115
+ }; \
116
+ return do_2shift(s, a, fns[a->size], false); \
117
+ }
118
+
119
+DO_2SHIFT_N(VSHRNB, vshrnb)
120
+DO_2SHIFT_N(VSHRNT, vshrnt)
121
+DO_2SHIFT_N(VRSHRNB, vrshrnb)
122
+DO_2SHIFT_N(VRSHRNT, vrshrnt)
61
--
123
--
62
2.17.1
124
2.20.1
63
125
64
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/31] aspeed: add the pc9552 chips to the witherspoon machine
[PULL 18/24] target/arm: Implement MVE saturating narrowing shifts
1
From: Cédric Le Goater <clg@kaod.org>
1
Implement the MVE saturating shift-right-and-narrow insns
2
2
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
3
The pca9552 LED blinkers on the Witherspoon machine are used for leds
3
4
but also as GPIOs to control fans and GPUs.
4
do_srshr() is borrowed from sve_helper.c.
5
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180530064049.27976-8-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
11
---
9
---
12
hw/arm/aspeed.c | 4 ++++
10
target/arm/helper-mve.h | 30 +++++++++++
13
1 file changed, 4 insertions(+)
11
target/arm/mve.decode | 28 ++++++++++
14
12
target/arm/mve_helper.c | 104 +++++++++++++++++++++++++++++++++++++
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
13
target/arm/translate-mve.c | 12 +++++
16
index XXXXXXX..XXXXXXX 100644
14
4 files changed, 174 insertions(+)
17
--- a/hw/arm/aspeed.c
15
18
+++ b/hw/arm/aspeed.c
16
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
17
index XXXXXXX..XXXXXXX 100644
20
AspeedSoCState *soc = &bmc->soc;
18
--- a/target/arm/helper-mve.h
21
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
19
+++ b/target/arm/helper-mve.h
22
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrshrnbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60);
21
DEF_HELPER_FLAGS_4(mve_vrshrnbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
24
+
22
DEF_HELPER_FLAGS_4(mve_vrshrntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
25
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
23
DEF_HELPER_FLAGS_4(mve_vrshrnth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
26
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
24
+
27
25
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
28
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
26
+DEF_HELPER_FLAGS_4(mve_vqshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
29
27
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
30
smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
28
+DEF_HELPER_FLAGS_4(mve_vqshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
31
eeprom_buf);
29
+
32
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "pca9552",
30
+DEF_HELPER_FLAGS_4(mve_vqshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+ 0x60);
31
+DEF_HELPER_FLAGS_4(mve_vqshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
32
+DEF_HELPER_FLAGS_4(mve_vqshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
33
+DEF_HELPER_FLAGS_4(mve_vqshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
34
+
35
+DEF_HELPER_FLAGS_4(mve_vqshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
36
+DEF_HELPER_FLAGS_4(mve_vqshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
37
+DEF_HELPER_FLAGS_4(mve_vqshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
38
+DEF_HELPER_FLAGS_4(mve_vqshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
39
+
40
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
42
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
43
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_sh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
44
+
45
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
46
+DEF_HELPER_FLAGS_4(mve_vqrshrnb_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
47
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_ub, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
48
+DEF_HELPER_FLAGS_4(mve_vqrshrnt_uh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
49
+
50
+DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
51
+DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
52
+DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
53
+DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
54
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/mve.decode
57
+++ b/target/arm/mve.decode
58
@@ -XXX,XX +XXX,XX @@ VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_b
59
VRSHRNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 1 @2_shr_h
60
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_b
61
VRSHRNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 1 @2_shr_h
62
+
63
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
64
+VQSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
65
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
66
+VQSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
67
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_b
68
+VQSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 0 @2_shr_h
69
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_b
70
+VQSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 0 @2_shr_h
71
+
72
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
73
+VQSHRUNB 111 0 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
74
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
75
+VQSHRUNT 111 0 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
76
+
77
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
78
+VQRSHRNB_S 111 0 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
79
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
80
+VQRSHRNT_S 111 0 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
81
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_b
82
+VQRSHRNB_U 111 1 1110 1 . ... ... ... 0 1111 0 1 . 0 ... 1 @2_shr_h
83
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_b
84
+VQRSHRNT_U 111 1 1110 1 . ... ... ... 1 1111 0 1 . 0 ... 1 @2_shr_h
85
+
86
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
87
+VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
88
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
89
+VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
90
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/mve_helper.c
93
+++ b/target/arm/mve_helper.c
94
@@ -XXX,XX +XXX,XX @@ static inline uint64_t do_urshr(uint64_t x, unsigned sh)
95
}
34
}
96
}
35
97
36
static void witherspoon_bmc_init(MachineState *machine)
98
+static inline int64_t do_srshr(int64_t x, unsigned sh)
99
+{
100
+ if (likely(sh < 64)) {
101
+ return (x >> sh) + ((x >> (sh - 1)) & 1);
102
+ } else {
103
+ /* Rounding the sign bit always produces 0. */
104
+ return 0;
105
+ }
106
+}
107
+
108
DO_VSHRN_ALL(vshrn, DO_SHR)
109
DO_VSHRN_ALL(vrshrn, do_urshr)
110
+
111
+static inline int32_t do_sat_bhs(int64_t val, int64_t min, int64_t max,
112
+ bool *satp)
113
+{
114
+ if (val > max) {
115
+ *satp = true;
116
+ return max;
117
+ } else if (val < min) {
118
+ *satp = true;
119
+ return min;
120
+ } else {
121
+ return val;
122
+ }
123
+}
124
+
125
+/* Saturating narrowing right shifts */
126
+#define DO_VSHRN_SAT(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \
127
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
128
+ void *vm, uint32_t shift) \
129
+ { \
130
+ LTYPE *m = vm; \
131
+ TYPE *d = vd; \
132
+ uint16_t mask = mve_element_mask(env); \
133
+ bool qc = false; \
134
+ unsigned le; \
135
+ for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \
136
+ bool sat = false; \
137
+ TYPE r = FN(m[H##LESIZE(le)], shift, &sat); \
138
+ mergemask(&d[H##ESIZE(le * 2 + TOP)], r, mask); \
139
+ qc |= sat && (mask & 1 << (TOP * ESIZE)); \
140
+ } \
141
+ if (qc) { \
142
+ env->vfp.qc[0] = qc; \
143
+ } \
144
+ mve_advance_vpt(env); \
145
+ }
146
+
147
+#define DO_VSHRN_SAT_UB(BOP, TOP, FN) \
148
+ DO_VSHRN_SAT(BOP, false, 1, uint8_t, 2, uint16_t, FN) \
149
+ DO_VSHRN_SAT(TOP, true, 1, uint8_t, 2, uint16_t, FN)
150
+
151
+#define DO_VSHRN_SAT_UH(BOP, TOP, FN) \
152
+ DO_VSHRN_SAT(BOP, false, 2, uint16_t, 4, uint32_t, FN) \
153
+ DO_VSHRN_SAT(TOP, true, 2, uint16_t, 4, uint32_t, FN)
154
+
155
+#define DO_VSHRN_SAT_SB(BOP, TOP, FN) \
156
+ DO_VSHRN_SAT(BOP, false, 1, int8_t, 2, int16_t, FN) \
157
+ DO_VSHRN_SAT(TOP, true, 1, int8_t, 2, int16_t, FN)
158
+
159
+#define DO_VSHRN_SAT_SH(BOP, TOP, FN) \
160
+ DO_VSHRN_SAT(BOP, false, 2, int16_t, 4, int32_t, FN) \
161
+ DO_VSHRN_SAT(TOP, true, 2, int16_t, 4, int32_t, FN)
162
+
163
+#define DO_SHRN_SB(N, M, SATP) \
164
+ do_sat_bhs((int64_t)(N) >> (M), INT8_MIN, INT8_MAX, SATP)
165
+#define DO_SHRN_UB(N, M, SATP) \
166
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT8_MAX, SATP)
167
+#define DO_SHRUN_B(N, M, SATP) \
168
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT8_MAX, SATP)
169
+
170
+#define DO_SHRN_SH(N, M, SATP) \
171
+ do_sat_bhs((int64_t)(N) >> (M), INT16_MIN, INT16_MAX, SATP)
172
+#define DO_SHRN_UH(N, M, SATP) \
173
+ do_sat_bhs((uint64_t)(N) >> (M), 0, UINT16_MAX, SATP)
174
+#define DO_SHRUN_H(N, M, SATP) \
175
+ do_sat_bhs((int64_t)(N) >> (M), 0, UINT16_MAX, SATP)
176
+
177
+#define DO_RSHRN_SB(N, M, SATP) \
178
+ do_sat_bhs(do_srshr(N, M), INT8_MIN, INT8_MAX, SATP)
179
+#define DO_RSHRN_UB(N, M, SATP) \
180
+ do_sat_bhs(do_urshr(N, M), 0, UINT8_MAX, SATP)
181
+#define DO_RSHRUN_B(N, M, SATP) \
182
+ do_sat_bhs(do_srshr(N, M), 0, UINT8_MAX, SATP)
183
+
184
+#define DO_RSHRN_SH(N, M, SATP) \
185
+ do_sat_bhs(do_srshr(N, M), INT16_MIN, INT16_MAX, SATP)
186
+#define DO_RSHRN_UH(N, M, SATP) \
187
+ do_sat_bhs(do_urshr(N, M), 0, UINT16_MAX, SATP)
188
+#define DO_RSHRUN_H(N, M, SATP) \
189
+ do_sat_bhs(do_srshr(N, M), 0, UINT16_MAX, SATP)
190
+
191
+DO_VSHRN_SAT_SB(vqshrnb_sb, vqshrnt_sb, DO_SHRN_SB)
192
+DO_VSHRN_SAT_SH(vqshrnb_sh, vqshrnt_sh, DO_SHRN_SH)
193
+DO_VSHRN_SAT_UB(vqshrnb_ub, vqshrnt_ub, DO_SHRN_UB)
194
+DO_VSHRN_SAT_UH(vqshrnb_uh, vqshrnt_uh, DO_SHRN_UH)
195
+DO_VSHRN_SAT_SB(vqshrunbb, vqshruntb, DO_SHRUN_B)
196
+DO_VSHRN_SAT_SH(vqshrunbh, vqshrunth, DO_SHRUN_H)
197
+
198
+DO_VSHRN_SAT_SB(vqrshrnb_sb, vqrshrnt_sb, DO_RSHRN_SB)
199
+DO_VSHRN_SAT_SH(vqrshrnb_sh, vqrshrnt_sh, DO_RSHRN_SH)
200
+DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
201
+DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
202
+DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
203
+DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
204
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/translate-mve.c
207
+++ b/target/arm/translate-mve.c
208
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VSHRNB, vshrnb)
209
DO_2SHIFT_N(VSHRNT, vshrnt)
210
DO_2SHIFT_N(VRSHRNB, vrshrnb)
211
DO_2SHIFT_N(VRSHRNT, vrshrnt)
212
+DO_2SHIFT_N(VQSHRNB_S, vqshrnb_s)
213
+DO_2SHIFT_N(VQSHRNT_S, vqshrnt_s)
214
+DO_2SHIFT_N(VQSHRNB_U, vqshrnb_u)
215
+DO_2SHIFT_N(VQSHRNT_U, vqshrnt_u)
216
+DO_2SHIFT_N(VQSHRUNB, vqshrunb)
217
+DO_2SHIFT_N(VQSHRUNT, vqshrunt)
218
+DO_2SHIFT_N(VQRSHRNB_S, vqrshrnb_s)
219
+DO_2SHIFT_N(VQRSHRNT_S, vqrshrnt_s)
220
+DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
221
+DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
222
+DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
223
+DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
37
--
224
--
38
2.17.1
225
2.20.1
39
226
40
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/31] sdcard: Add a 'spec_version' property, default to Spec v2.00
[PULL 19/24] target/arm: Implement MVE VSHLC
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE VSHLC insn, which performs a shift left of the
2
entire vector with carry in bits provided from a general purpose
3
register and carry out bits written back to that register.
2
4
3
As of this commit, the Spec v1 is not working, and all controllers
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
expect the cards to be conformant to Spec v2.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 2 ++
10
target/arm/mve.decode | 2 ++
11
target/arm/mve_helper.c | 38 ++++++++++++++++++++++++++++++++++++++
12
target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++
13
4 files changed, 72 insertions(+)
5
14
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20180607180641.874-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/sd/sd.h | 5 +++++
12
hw/sd/sd.c | 23 ++++++++++++++++++++---
13
2 files changed, 25 insertions(+), 3 deletions(-)
14
15
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/sd/sd.h
17
--- a/target/arm/helper-mve.h
18
+++ b/include/hw/sd/sd.h
18
+++ b/target/arm/helper-mve.h
19
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunbb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
#define APP_CMD            (1 << 5)
20
DEF_HELPER_FLAGS_4(mve_vqrshrunbh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
21
#define AKE_SEQ_ERROR        (1 << 3)
21
DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
22
22
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
23
+enum SDPhySpecificationVersion {
24
+ SD_PHY_SPECv1_10_VERS = 1,
25
+ SD_PHY_SPECv2_00_VERS = 2,
26
+};
27
+
23
+
28
typedef enum {
24
+DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
29
SD_VOLTAGE_0_4V = 400, /* currently not supported */
25
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
SD_VOLTAGE_1_8V = 1800,
31
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
32
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/sd/sd.c
27
--- a/target/arm/mve.decode
34
+++ b/hw/sd/sd.c
28
+++ b/target/arm/mve.decode
35
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_b
36
/*
30
VQRSHRUNB 111 1 1110 1 . ... ... ... 0 1111 1 1 . 0 ... 0 @2_shr_h
37
* SD Memory Card emulation as defined in the "SD Memory Card Physical
31
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_b
38
- * layer specification, Version 1.10."
32
VQRSHRUNT 111 1 1110 1 . ... ... ... 1 1111 1 1 . 0 ... 0 @2_shr_h
39
+ * layer specification, Version 2.00."
33
+
40
*
34
+VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
41
* Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
35
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
42
* Copyright (c) 2007 CodeSourcery
36
index XXXXXXX..XXXXXXX 100644
43
+ * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>
37
--- a/target/arm/mve_helper.c
44
*
38
+++ b/target/arm/mve_helper.c
45
* Redistribution and use in source and binary forms, with or without
39
@@ -XXX,XX +XXX,XX @@ DO_VSHRN_SAT_UB(vqrshrnb_ub, vqrshrnt_ub, DO_RSHRN_UB)
46
* modification, are permitted provided that the following conditions
40
DO_VSHRN_SAT_UH(vqrshrnb_uh, vqrshrnt_uh, DO_RSHRN_UH)
47
@@ -XXX,XX +XXX,XX @@ struct SDState {
41
DO_VSHRN_SAT_SB(vqrshrunbb, vqrshruntb, DO_RSHRUN_B)
48
uint8_t sd_status[64];
42
DO_VSHRN_SAT_SH(vqrshrunbh, vqrshrunth, DO_RSHRUN_H)
49
43
+
50
/* Configurable properties */
44
+uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
51
+ uint8_t spec_version;
45
+ uint32_t shift)
52
BlockBackend *blk;
46
+{
53
bool spi;
47
+ uint32_t *d = vd;
54
48
+ uint16_t mask = mve_element_mask(env);
55
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
49
+ unsigned e;
56
50
+ uint32_t r;
57
static void sd_set_scr(SDState *sd)
51
+
58
{
52
+ /*
59
- sd->scr[0] = (0 << 4) /* SCR structure version 1.0 */
53
+ * For each 32-bit element, we shift it left, bringing in the
60
- | 1; /* Spec Version 1.10 */
54
+ * low 'shift' bits of rdm at the bottom. Bits shifted out at
61
+ sd->scr[0] = 0 << 4; /* SCR structure version 1.0 */
55
+ * the top become the new rdm, if the predicate mask permits.
62
+ if (sd->spec_version == SD_PHY_SPECv1_10_VERS) {
56
+ * The final rdm value is returned to update the register.
63
+ sd->scr[0] |= 1; /* Spec Version 1.10 */
57
+ * shift == 0 here means "shift by 32 bits".
58
+ */
59
+ if (shift == 0) {
60
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
61
+ r = rdm;
62
+ if (mask & 1) {
63
+ rdm = d[H4(e)];
64
+ }
65
+ mergemask(&d[H4(e)], r, mask);
66
+ }
64
+ } else {
67
+ } else {
65
+ sd->scr[0] |= 2; /* Spec Version 2.00 */
68
+ uint32_t shiftmask = MAKE_64BIT_MASK(0, shift);
69
+
70
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) {
71
+ r = (d[H4(e)] << shift) | (rdm & shiftmask);
72
+ if (mask & 1) {
73
+ rdm = d[H4(e)] >> (32 - shift);
74
+ }
75
+ mergemask(&d[H4(e)], r, mask);
76
+ }
66
+ }
77
+ }
67
sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
78
+ mve_advance_vpt(env);
68
| 0b0101; /* 1-bit or 4-bit width bus modes */
79
+ return rdm;
69
sd->scr[2] = 0x00; /* Extended Security is not supported. */
80
+}
70
@@ -XXX,XX +XXX,XX @@ static void sd_realize(DeviceState *dev, Error **errp)
81
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
71
82
index XXXXXXX..XXXXXXX 100644
72
sd->proto_name = sd->spi ? "SPI" : "SD";
83
--- a/target/arm/translate-mve.c
73
84
+++ b/target/arm/translate-mve.c
74
+ switch (sd->spec_version) {
85
@@ -XXX,XX +XXX,XX @@ DO_2SHIFT_N(VQRSHRNB_U, vqrshrnb_u)
75
+ case SD_PHY_SPECv1_10_VERS
86
DO_2SHIFT_N(VQRSHRNT_U, vqrshrnt_u)
76
+ ... SD_PHY_SPECv2_00_VERS:
87
DO_2SHIFT_N(VQRSHRUNB, vqrshrunb)
77
+ break;
88
DO_2SHIFT_N(VQRSHRUNT, vqrshrunt)
78
+ default:
89
+
79
+ error_setg(errp, "Invalid SD card Spec version: %u", sd->spec_version);
90
+static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a)
80
+ return;
91
+{
92
+ /*
93
+ * Whole Vector Left Shift with Carry. The carry is taken
94
+ * from a general purpose register and written back there.
95
+ * An imm of 0 means "shift by 32".
96
+ */
97
+ TCGv_ptr qd;
98
+ TCGv_i32 rdm;
99
+
100
+ if (!dc_isar_feature(aa32_mve, s) || !mve_check_qreg_bank(s, a->qd)) {
101
+ return false;
102
+ }
103
+ if (a->rdm == 13 || a->rdm == 15) {
104
+ /* CONSTRAINED UNPREDICTABLE: we UNDEF */
105
+ return false;
106
+ }
107
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
108
+ return true;
81
+ }
109
+ }
82
+
110
+
83
if (sd->blk && blk_is_read_only(sd->blk)) {
111
+ qd = mve_qreg_ptr(a->qd);
84
error_setg(errp, "Cannot use read-only drive as SD card");
112
+ rdm = load_reg(s, a->rdm);
85
return;
113
+ gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm));
86
@@ -XXX,XX +XXX,XX @@ static void sd_realize(DeviceState *dev, Error **errp)
114
+ store_reg(s, a->rdm, rdm);
87
}
115
+ tcg_temp_free_ptr(qd);
88
116
+ mve_update_eci(s);
89
static Property sd_properties[] = {
117
+ return true;
90
+ DEFINE_PROP_UINT8("spec_version", SDState,
118
+}
91
+ spec_version, SD_PHY_SPECv2_00_VERS),
92
DEFINE_PROP_DRIVE("drive", SDState, blk),
93
/* We do not model the chip select pin, so allow the board to select
94
* whether card should be in SSI or MMC/SD mode. It is also up to the
95
--
119
--
96
2.17.1
120
2.20.1
97
121
98
122
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/31] aspeed: add an I2C RTC device to all machines
[PULL 20/24] target/arm: Implement MVE VADDLV
1
From: Cédric Le Goater <clg@kaod.org>
1
Implement the MVE VADDLV insn; this is similar to VADDV, except
2
that it accumulates 32-bit elements into a 64-bit accumulator
3
stored in a pair of general-purpose registers.
2
4
3
The AST2500 EVB does not have an RTC but we can pretend that one is
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
plugged on the I2C bus header.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
8
---
9
target/arm/helper-mve.h | 3 ++
10
target/arm/mve.decode | 6 +++-
11
target/arm/mve_helper.c | 19 ++++++++++++
12
target/arm/translate-mve.c | 63 ++++++++++++++++++++++++++++++++++++++
13
4 files changed, 90 insertions(+), 1 deletion(-)
5
14
6
The romulus and witherspoon boards expects an Epson RX8900 I2C RTC but
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
7
a ds1338 is good enough for the basic features we need.
8
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11
Message-id: 20180530064049.27976-4-clg@kaod.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/aspeed.c | 19 +++++++++++++++++++
15
1 file changed, 19 insertions(+)
16
17
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/aspeed.c
17
--- a/target/arm/helper-mve.h
20
+++ b/hw/arm/aspeed.c
18
+++ b/target/arm/helper-mve.h
21
@@ -XXX,XX +XXX,XX @@ enum {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32)
22
20
DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32)
23
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
21
DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32)
24
static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
22
25
+static void romulus_bmc_i2c_init(AspeedBoardState *bmc);
23
+DEF_HELPER_FLAGS_3(mve_vaddlv_s, TCG_CALL_NO_WG, i64, env, ptr, i64)
26
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc);
24
+DEF_HELPER_FLAGS_3(mve_vaddlv_u, TCG_CALL_NO_WG, i64, env, ptr, i64)
27
28
static const AspeedBoardConfig aspeed_boards[] = {
29
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
30
.fmc_model = "n25q256a",
31
.spi_model = "mx66l1g45g",
32
.num_cs = 2,
33
+ .i2c_init = romulus_bmc_i2c_init,
34
},
35
[WITHERSPOON_BMC] = {
36
.soc_name = "ast2500-a1",
37
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
38
39
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
40
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
41
+
25
+
42
+ /* The AST2500 EVB does not have an RTC. Let's pretend that one is
26
DEF_HELPER_FLAGS_3(mve_vmovi, TCG_CALL_NO_WG, void, env, ptr, i64)
43
+ * plugged on the I2C bus header */
27
DEF_HELPER_FLAGS_3(mve_vandi, TCG_CALL_NO_WG, void, env, ptr, i64)
44
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
28
DEF_HELPER_FLAGS_3(mve_vorri, TCG_CALL_NO_WG, void, env, ptr, i64)
29
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
30
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/mve.decode
32
+++ b/target/arm/mve.decode
33
@@ -XXX,XX +XXX,XX @@ VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
34
VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar
35
36
# Vector add across vector
37
-VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
38
+{
39
+ VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo
40
+ VADDLV 111 u:1 1110 1 ... 1001 ... 0 1111 00 a:1 0 qm:3 0 \
41
+ rdahi=%rdahi rdalo=%rdalo
42
+}
43
44
# Predicate operations
45
%mask_22_13 22:1 13:3
46
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/mve_helper.c
49
+++ b/target/arm/mve_helper.c
50
@@ -XXX,XX +XXX,XX @@ DO_VADDV(vaddvub, 1, uint8_t)
51
DO_VADDV(vaddvuh, 2, uint16_t)
52
DO_VADDV(vaddvuw, 4, uint32_t)
53
54
+#define DO_VADDLV(OP, TYPE, LTYPE) \
55
+ uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \
56
+ uint64_t ra) \
57
+ { \
58
+ uint16_t mask = mve_element_mask(env); \
59
+ unsigned e; \
60
+ TYPE *m = vm; \
61
+ for (e = 0; e < 16 / 4; e++, mask >>= 4) { \
62
+ if (mask & 1) { \
63
+ ra += (LTYPE)m[H4(e)]; \
64
+ } \
65
+ } \
66
+ mve_advance_vpt(env); \
67
+ return ra; \
68
+ } \
69
+
70
+DO_VADDLV(vaddlv_s, int32_t, int64_t)
71
+DO_VADDLV(vaddlv_u, uint32_t, uint64_t)
72
+
73
/* Shifts by immediate */
74
#define DO_2SHIFT(OP, ESIZE, TYPE, FN) \
75
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \
76
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/translate-mve.c
79
+++ b/target/arm/translate-mve.c
80
@@ -XXX,XX +XXX,XX @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
81
return true;
45
}
82
}
46
83
47
static void ast2500_evb_init(MachineState *machine)
84
+static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ast2500_evb_type = {
49
.class_init = ast2500_evb_class_init,
50
};
51
52
+static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
53
+{
85
+{
54
+ AspeedSoCState *soc = &bmc->soc;
86
+ /*
87
+ * Vector Add Long Across Vector: accumulate the 32-bit
88
+ * elements of the vector into a 64-bit result stored in
89
+ * a pair of general-purpose registers.
90
+ * No need to check Qm's bank: it is only 3 bits in decode.
91
+ */
92
+ TCGv_ptr qm;
93
+ TCGv_i64 rda;
94
+ TCGv_i32 rdalo, rdahi;
55
+
95
+
56
+ /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
96
+ if (!dc_isar_feature(aa32_mve, s)) {
57
+ * good enough */
97
+ return false;
58
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
98
+ }
99
+ /*
100
+ * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related
101
+ * encoding; rdalo always has bit 0 clear so cannot be 13 or 15.
102
+ */
103
+ if (a->rdahi == 13 || a->rdahi == 15) {
104
+ return false;
105
+ }
106
+ if (!mve_eci_check(s) || !vfp_access_check(s)) {
107
+ return true;
108
+ }
109
+
110
+ /*
111
+ * This insn is subject to beat-wise execution. Partial execution
112
+ * of an A=0 (no-accumulate) insn which does not execute the first
113
+ * beat must start with the current value of RdaHi:RdaLo, not zero.
114
+ */
115
+ if (a->a || mve_skip_first_beat(s)) {
116
+ /* Accumulate input from RdaHi:RdaLo */
117
+ rda = tcg_temp_new_i64();
118
+ rdalo = load_reg(s, a->rdalo);
119
+ rdahi = load_reg(s, a->rdahi);
120
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
121
+ tcg_temp_free_i32(rdalo);
122
+ tcg_temp_free_i32(rdahi);
123
+ } else {
124
+ /* Accumulate starting at zero */
125
+ rda = tcg_const_i64(0);
126
+ }
127
+
128
+ qm = mve_qreg_ptr(a->qm);
129
+ if (a->u) {
130
+ gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
131
+ } else {
132
+ gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
133
+ }
134
+ tcg_temp_free_ptr(qm);
135
+
136
+ rdalo = tcg_temp_new_i32();
137
+ rdahi = tcg_temp_new_i32();
138
+ tcg_gen_extrl_i64_i32(rdalo, rda);
139
+ tcg_gen_extrh_i64_i32(rdahi, rda);
140
+ store_reg(s, a->rdalo, rdalo);
141
+ store_reg(s, a->rdahi, rdahi);
142
+ tcg_temp_free_i64(rda);
143
+ mve_update_eci(s);
144
+ return true;
59
+}
145
+}
60
+
146
+
61
static void romulus_bmc_init(MachineState *machine)
147
static bool do_1imm(DisasContext *s, arg_1imm *a, MVEGenOneOpImmFn *fn)
62
{
148
{
63
aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]);
149
TCGv_ptr qd;
64
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
65
66
/* The Witherspoon expects a TMP275 but a TMP105 is compatible */
67
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp105", 0x4a);
68
+
69
+ /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
70
+ * good enough */
71
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
72
}
73
74
static void witherspoon_bmc_init(MachineState *machine)
75
--
150
--
76
2.17.1
151
2.20.1
77
152
78
153
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/31] ftgmac100: compute maximum frame size depending on the protocol
[PULL 21/24] target/arm: Implement MVE long shifts by immediate
1
From: Cédric Le Goater <clg@kaod.org>
1
The MVE extension to v8.1M includes some new shift instructions which
2
2
sit entirely within the non-coprocessor part of the encoding space
3
The maximum frame size includes the CRC and depends if a VLAN tag is
3
and which operate only on general-purpose registers. They take up
4
inserted or not. Adjust the frame size limit in the transmit handler
4
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
5
using on the FTGMAC100State buffer size and in the receive handler use
5
with Rm == 13 or 15.
6
the packet protocol.
6
7
7
Implement the long shifts by immediate, which perform shifts on a
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
pair of general-purpose registers treated as a 64-bit quantity, with
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
an immediate shift count between 1 and 32.
10
Message-id: 20180530061711.23673-2-clg@kaod.org
10
11
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
12
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
13
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
14
is too difficult, because the functions that generate the code are
15
shared between a dozen different kinds of arithmetic or logical
16
instruction for all A32, T16 and T32 encodings, and for some insns
17
and some encodings Rm==13,15 are valid.)
18
19
We make the helper functions we need for UQSHLL and SQSHLL take
20
a 32-bit value which the helper casts to int8_t because we'll need
21
these helpers also for the shift-by-register insns, where the shift
22
count might be < 0 or > 32.
23
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
12
---
27
---
13
include/hw/net/ftgmac100.h | 7 ++++++-
28
target/arm/helper-mve.h | 3 ++
14
hw/net/ftgmac100.c | 23 ++++++++++++-----------
29
target/arm/translate.h | 1 +
15
2 files changed, 18 insertions(+), 12 deletions(-)
30
target/arm/t32.decode | 28 +++++++++++++
16
31
target/arm/mve_helper.c | 10 +++++
17
diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h
32
target/arm/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++
18
index XXXXXXX..XXXXXXX 100644
33
5 files changed, 132 insertions(+)
19
--- a/include/hw/net/ftgmac100.h
34
20
+++ b/include/hw/net/ftgmac100.h
35
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper-mve.h
38
+++ b/target/arm/helper-mve.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshruntb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
40
DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
41
42
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
43
+
44
+DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
45
+DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
46
diff --git a/target/arm/translate.h b/target/arm/translate.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.h
49
+++ b/target/arm/translate.h
50
@@ -XXX,XX +XXX,XX @@ typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
51
typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
52
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
53
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
54
+typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
55
56
/**
57
* arm_tbflags_from_tb:
58
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/t32.decode
61
+++ b/target/arm/t32.decode
21
@@ -XXX,XX +XXX,XX @@
62
@@ -XXX,XX +XXX,XX @@
22
#include "hw/sysbus.h"
63
&mcr !extern cp opc1 crn crm opc2 rt
23
#include "net/net.h"
64
&mcrr !extern cp opc1 crm rt rt2
65
66
+&mve_shl_ri rdalo rdahi shim
67
+
68
+# rdahi: bits [3:1] from insn, bit 0 is 1
69
+# rdalo: bits [3:1] from insn, bit 0 is 0
70
+%rdahi_9 9:3 !function=times_2_plus_1
71
+%rdalo_17 17:3 !function=times_2
72
+
73
# Data-processing (register)
74
75
%imm5_12_6 12:3 6:2
76
@@ -XXX,XX +XXX,XX @@
77
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
78
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
79
80
+@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
81
+ &mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
82
+
83
{
84
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
85
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
86
}
87
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
88
{
89
+ # The v8.1M MVE shift insns overlap in encoding with MOVS/ORRS
90
+ # and are distinguished by having Rm==13 or 15. Those are UNPREDICTABLE
91
+ # cases for MOVS/ORRS. We decode the MVE cases first, ensuring that
92
+ # they explicitly call unallocated_encoding() for cases that must UNDEF
93
+ # (eg "using a new shift insn on a v8.1M CPU without MVE"), and letting
94
+ # the rest fall through (where ORR_rrri and MOV_rxri will end up
95
+ # handling them as r13 and r15 accesses with the same semantics as A32).
96
+ [
97
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
98
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
99
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
100
+
101
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
102
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
103
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
104
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
105
+ ]
106
+
107
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
108
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
109
}
110
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/target/arm/mve_helper.c
113
+++ b/target/arm/mve_helper.c
114
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
115
mve_advance_vpt(env);
116
return rdm;
117
}
118
+
119
+uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
120
+{
121
+ return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
122
+}
123
+
124
+uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
+{
126
+ return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
+}
128
diff --git a/target/arm/translate.c b/target/arm/translate.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/target/arm/translate.c
131
+++ b/target/arm/translate.c
132
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
133
return true;
134
}
24
135
25
+/*
136
+/*
26
+ * Max frame size for the receiving buffer
137
+ * v8.1M MVE wide-shifts
27
+ */
138
+ */
28
+#define FTGMAC100_MAX_FRAME_SIZE 9220
139
+static bool do_mve_shl_ri(DisasContext *s, arg_mve_shl_ri *a,
29
+
140
+ WideShiftImmFn *fn)
30
typedef struct FTGMAC100State {
141
+{
31
/*< private >*/
142
+ TCGv_i64 rda;
32
SysBusDevice parent_obj;
143
+ TCGv_i32 rdalo, rdahi;
33
@@ -XXX,XX +XXX,XX @@ typedef struct FTGMAC100State {
144
+
34
qemu_irq irq;
145
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
35
MemoryRegion iomem;
146
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
36
147
+ return false;
37
- uint8_t *frame;
148
+ }
38
+ uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];
149
+ if (a->rdahi == 15) {
39
150
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
40
uint32_t irq_state;
151
+ return false;
41
uint32_t isr;
152
+ }
42
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
153
+ if (!dc_isar_feature(aa32_mve, s) ||
43
index XXXXXXX..XXXXXXX 100644
154
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
44
--- a/hw/net/ftgmac100.c
155
+ a->rdahi == 13) {
45
+++ b/hw/net/ftgmac100.c
156
+ /* RdaHi == 13 is UNPREDICTABLE; we choose to UNDEF */
46
@@ -XXX,XX +XXX,XX @@ typedef struct {
157
+ unallocated_encoding(s);
158
+ return true;
159
+ }
160
+
161
+ if (a->shim == 0) {
162
+ a->shim = 32;
163
+ }
164
+
165
+ rda = tcg_temp_new_i64();
166
+ rdalo = load_reg(s, a->rdalo);
167
+ rdahi = load_reg(s, a->rdahi);
168
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
169
+
170
+ fn(rda, rda, a->shim);
171
+
172
+ tcg_gen_extrl_i64_i32(rdalo, rda);
173
+ tcg_gen_extrh_i64_i32(rdahi, rda);
174
+ store_reg(s, a->rdalo, rdalo);
175
+ store_reg(s, a->rdahi, rdahi);
176
+ tcg_temp_free_i64(rda);
177
+
178
+ return true;
179
+}
180
+
181
+static bool trans_ASRL_ri(DisasContext *s, arg_mve_shl_ri *a)
182
+{
183
+ return do_mve_shl_ri(s, a, tcg_gen_sari_i64);
184
+}
185
+
186
+static bool trans_LSLL_ri(DisasContext *s, arg_mve_shl_ri *a)
187
+{
188
+ return do_mve_shl_ri(s, a, tcg_gen_shli_i64);
189
+}
190
+
191
+static bool trans_LSRL_ri(DisasContext *s, arg_mve_shl_ri *a)
192
+{
193
+ return do_mve_shl_ri(s, a, tcg_gen_shri_i64);
194
+}
195
+
196
+static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
197
+{
198
+ gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift));
199
+}
200
+
201
+static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
202
+{
203
+ return do_mve_shl_ri(s, a, gen_mve_sqshll);
204
+}
205
+
206
+static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift)
207
+{
208
+ gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift));
209
+}
210
+
211
+static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a)
212
+{
213
+ return do_mve_shl_ri(s, a, gen_mve_uqshll);
214
+}
215
+
216
+static bool trans_SRSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
217
+{
218
+ return do_mve_shl_ri(s, a, gen_srshr64_i64);
219
+}
220
+
221
+static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
222
+{
223
+ return do_mve_shl_ri(s, a, gen_urshr64_i64);
224
+}
225
+
47
/*
226
/*
48
* Max frame size for the receiving buffer
227
* Multiply and multiply accumulate
49
*/
228
*/
50
-#define FTGMAC100_MAX_FRAME_SIZE 10240
51
+#define FTGMAC100_MAX_FRAME_SIZE 9220
52
53
/* Limits depending on the type of the frame
54
*
55
* 9216 for Jumbo frames (+ 4 for VLAN)
56
* 1518 for other frames (+ 4 for VLAN)
57
*/
58
-static int ftgmac100_max_frame_size(FTGMAC100State *s)
59
+static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
60
{
61
- return (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518) + 4;
62
+ int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
63
+
64
+ return max + (proto == ETH_P_VLAN ? 4 : 0);
65
}
66
67
static void ftgmac100_update_irq(FTGMAC100State *s)
68
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
69
uint8_t *ptr = s->frame;
70
uint32_t addr = tx_descriptor;
71
uint32_t flags = 0;
72
- int max_frame_size = ftgmac100_max_frame_size(s);
73
74
while (1) {
75
FTGMAC100Desc bd;
76
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
77
flags = bd.des1;
78
}
79
80
- len = bd.des0 & 0x3FFF;
81
- if (frame_size + len > max_frame_size) {
82
+ len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
83
+ if (frame_size + len > sizeof(s->frame)) {
84
qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
85
__func__, len);
86
- len = max_frame_size - frame_size;
87
+ s->isr |= FTGMAC100_INT_XPKT_LOST;
88
+ len = sizeof(s->frame) - frame_size;
89
}
90
91
if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
92
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
93
uint32_t buf_len;
94
size_t size = len;
95
uint32_t first = FTGMAC100_RXDES0_FRS;
96
- int max_frame_size = ftgmac100_max_frame_size(s);
97
+ uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
98
+ int max_frame_size = ftgmac100_max_frame_size(s, proto);
99
100
if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
101
!= (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
102
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
103
104
/* Huge frames are truncated. */
105
if (size > max_frame_size) {
106
- size = max_frame_size;
107
qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
108
__func__, size);
109
+ size = max_frame_size;
110
flags |= FTGMAC100_RXDES0_FTL;
111
}
112
113
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
114
object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
115
s);
116
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
117
-
118
- s->frame = g_malloc(FTGMAC100_MAX_FRAME_SIZE);
119
}
120
121
static const VMStateDescription vmstate_ftgmac100 = {
122
--
229
--
123
2.17.1
230
2.20.1
124
231
125
232
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/31] target/arm: Add trailing '\n' to qemu_log() calls
[PULL 22/24] target/arm: Implement MVE long shifts by register
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE long shifts by register, which perform shifts on a
2
2
pair of general-purpose registers treated as a 64-bit quantity, with
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
the shift count in another general-purpose register, which might be
4
Message-id: 20180606152128.449-9-f4bug@amsat.org
4
either positive or negative.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Like the long-shifts-by-immediate, these encodings sit in the space
7
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
8
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
9
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
10
we have to move the CSEL pattern into the same decodetree group.
11
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
7
---
15
---
8
target/arm/helper.c | 4 ++--
16
target/arm/helper-mve.h | 6 +++
9
1 file changed, 2 insertions(+), 2 deletions(-)
17
target/arm/translate.h | 1 +
10
18
target/arm/t32.decode | 16 +++++--
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
target/arm/mve_helper.c | 93 +++++++++++++++++++++++++++++++++++++++++
12
index XXXXXXX..XXXXXXX 100644
20
target/arm/translate.c | 69 ++++++++++++++++++++++++++++++
13
--- a/target/arm/helper.c
21
5 files changed, 182 insertions(+), 3 deletions(-)
14
+++ b/target/arm/helper.c
22
15
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
23
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
16
case 4: /* unlinked address mismatch (reserved if AArch64) */
24
index XXXXXXX..XXXXXXX 100644
17
case 5: /* linked address mismatch (reserved if AArch64) */
25
--- a/target/arm/helper-mve.h
18
qemu_log_mask(LOG_UNIMP,
26
+++ b/target/arm/helper-mve.h
19
- "arm: address mismatch breakpoint types not implemented");
27
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshrunth, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
20
+ "arm: address mismatch breakpoint types not implemented\n");
28
21
return;
29
DEF_HELPER_FLAGS_4(mve_vshlc, TCG_CALL_NO_WG, i32, env, ptr, i32, i32)
22
case 0: /* unlinked address match */
30
23
case 1: /* linked address match */
31
+DEF_HELPER_FLAGS_3(mve_sshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
24
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
32
+DEF_HELPER_FLAGS_3(mve_ushll, TCG_CALL_NO_RWG, i64, env, i64, i32)
25
case 8: /* unlinked VMID match (reserved if no EL2) */
33
DEF_HELPER_FLAGS_3(mve_sqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
26
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
34
DEF_HELPER_FLAGS_3(mve_uqshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
27
qemu_log_mask(LOG_UNIMP,
35
+DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
28
- "arm: unlinked context breakpoint types not implemented");
36
+DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
29
+ "arm: unlinked context breakpoint types not implemented\n");
37
+DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
30
return;
38
+DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
case 9: /* linked VMID match (reserved if no EL2) */
39
diff --git a/target/arm/translate.h b/target/arm/translate.h
32
case 11: /* linked context ID and VMID match (reserved if no EL2) */
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/translate.h
42
+++ b/target/arm/translate.h
43
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
44
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
45
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
46
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
47
+typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
48
49
/**
50
* arm_tbflags_from_tb:
51
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
52
index XXXXXXX..XXXXXXX 100644
53
--- a/target/arm/t32.decode
54
+++ b/target/arm/t32.decode
55
@@ -XXX,XX +XXX,XX @@
56
&mcrr !extern cp opc1 crm rt rt2
57
58
&mve_shl_ri rdalo rdahi shim
59
+&mve_shl_rr rdalo rdahi rm
60
61
# rdahi: bits [3:1] from insn, bit 0 is 1
62
# rdalo: bits [3:1] from insn, bit 0 is 0
63
@@ -XXX,XX +XXX,XX @@
64
65
@mve_shl_ri ....... .... . ... . . ... ... . .. .. .... \
66
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
67
+@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
68
+ &mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
69
70
{
71
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
72
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
73
URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
74
SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
75
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
76
+
77
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
78
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
79
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
80
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
81
+ UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
82
+ SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
83
]
84
85
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
86
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
87
+
88
+ # v8.1M CSEL and friends
89
+ CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
90
}
91
{
92
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
93
@@ -XXX,XX +XXX,XX @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
94
}
95
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
96
97
-# v8.1M CSEL and friends
98
-CSEL 1110101 0010 1 rn:4 10 op:2 rd:4 fcond:4 rm:4
99
-
100
# Data-processing (register-shifted register)
101
102
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
103
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/mve_helper.c
106
+++ b/target/arm/mve_helper.c
107
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_vshlc)(CPUARMState *env, void *vd, uint32_t rdm,
108
return rdm;
109
}
110
111
+uint64_t HELPER(mve_sshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
112
+{
113
+ return do_sqrshl_d(n, -(int8_t)shift, false, NULL);
114
+}
115
+
116
+uint64_t HELPER(mve_ushll)(CPUARMState *env, uint64_t n, uint32_t shift)
117
+{
118
+ return do_uqrshl_d(n, (int8_t)shift, false, NULL);
119
+}
120
+
121
uint64_t HELPER(mve_sqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
122
{
123
return do_sqrshl_d(n, (int8_t)shift, false, &env->QF);
124
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqshll)(CPUARMState *env, uint64_t n, uint32_t shift)
125
{
126
return do_uqrshl_d(n, (int8_t)shift, false, &env->QF);
127
}
128
+
129
+uint64_t HELPER(mve_sqrshrl)(CPUARMState *env, uint64_t n, uint32_t shift)
130
+{
131
+ return do_sqrshl_d(n, -(int8_t)shift, true, &env->QF);
132
+}
133
+
134
+uint64_t HELPER(mve_uqrshll)(CPUARMState *env, uint64_t n, uint32_t shift)
135
+{
136
+ return do_uqrshl_d(n, (int8_t)shift, true, &env->QF);
137
+}
138
+
139
+/* Operate on 64-bit values, but saturate at 48 bits */
140
+static inline int64_t do_sqrshl48_d(int64_t src, int64_t shift,
141
+ bool round, uint32_t *sat)
142
+{
143
+ if (shift <= -48) {
144
+ /* Rounding the sign bit always produces 0. */
145
+ if (round) {
146
+ return 0;
147
+ }
148
+ return src >> 63;
149
+ } else if (shift < 0) {
150
+ if (round) {
151
+ src >>= -shift - 1;
152
+ return (src >> 1) + (src & 1);
153
+ }
154
+ return src >> -shift;
155
+ } else if (shift < 48) {
156
+ int64_t val = src << shift;
157
+ int64_t extval = sextract64(val, 0, 48);
158
+ if (!sat || val == extval) {
159
+ return extval;
160
+ }
161
+ } else if (!sat || src == 0) {
162
+ return 0;
163
+ }
164
+
165
+ *sat = 1;
166
+ return (1ULL << 47) - (src >= 0);
167
+}
168
+
169
+/* Operate on 64-bit values, but saturate at 48 bits */
170
+static inline uint64_t do_uqrshl48_d(uint64_t src, int64_t shift,
171
+ bool round, uint32_t *sat)
172
+{
173
+ uint64_t val, extval;
174
+
175
+ if (shift <= -(48 + round)) {
176
+ return 0;
177
+ } else if (shift < 0) {
178
+ if (round) {
179
+ val = src >> (-shift - 1);
180
+ val = (val >> 1) + (val & 1);
181
+ } else {
182
+ val = src >> -shift;
183
+ }
184
+ extval = extract64(val, 0, 48);
185
+ if (!sat || val == extval) {
186
+ return extval;
187
+ }
188
+ } else if (shift < 48) {
189
+ uint64_t val = src << shift;
190
+ uint64_t extval = extract64(val, 0, 48);
191
+ if (!sat || val == extval) {
192
+ return extval;
193
+ }
194
+ } else if (!sat || src == 0) {
195
+ return 0;
196
+ }
197
+
198
+ *sat = 1;
199
+ return MAKE_64BIT_MASK(0, 48);
200
+}
201
+
202
+uint64_t HELPER(mve_sqrshrl48)(CPUARMState *env, uint64_t n, uint32_t shift)
203
+{
204
+ return do_sqrshl48_d(n, -(int8_t)shift, true, &env->QF);
205
+}
206
+
207
+uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
208
+{
209
+ return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
210
+}
211
diff --git a/target/arm/translate.c b/target/arm/translate.c
212
index XXXXXXX..XXXXXXX 100644
213
--- a/target/arm/translate.c
214
+++ b/target/arm/translate.c
215
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHRL_ri(DisasContext *s, arg_mve_shl_ri *a)
216
return do_mve_shl_ri(s, a, gen_urshr64_i64);
217
}
218
219
+static bool do_mve_shl_rr(DisasContext *s, arg_mve_shl_rr *a, WideShiftFn *fn)
220
+{
221
+ TCGv_i64 rda;
222
+ TCGv_i32 rdalo, rdahi;
223
+
224
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
225
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
226
+ return false;
227
+ }
228
+ if (a->rdahi == 15) {
229
+ /* These are a different encoding (SQSHL/SRSHR/UQSHL/URSHR) */
230
+ return false;
231
+ }
232
+ if (!dc_isar_feature(aa32_mve, s) ||
233
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
234
+ a->rdahi == 13 || a->rm == 13 || a->rm == 15 ||
235
+ a->rm == a->rdahi || a->rm == a->rdalo) {
236
+ /* These rdahi/rdalo/rm cases are UNPREDICTABLE; we choose to UNDEF */
237
+ unallocated_encoding(s);
238
+ return true;
239
+ }
240
+
241
+ rda = tcg_temp_new_i64();
242
+ rdalo = load_reg(s, a->rdalo);
243
+ rdahi = load_reg(s, a->rdahi);
244
+ tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
245
+
246
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
247
+ fn(rda, cpu_env, rda, cpu_R[a->rm]);
248
+
249
+ tcg_gen_extrl_i64_i32(rdalo, rda);
250
+ tcg_gen_extrh_i64_i32(rdahi, rda);
251
+ store_reg(s, a->rdalo, rdalo);
252
+ store_reg(s, a->rdahi, rdahi);
253
+ tcg_temp_free_i64(rda);
254
+
255
+ return true;
256
+}
257
+
258
+static bool trans_LSLL_rr(DisasContext *s, arg_mve_shl_rr *a)
259
+{
260
+ return do_mve_shl_rr(s, a, gen_helper_mve_ushll);
261
+}
262
+
263
+static bool trans_ASRL_rr(DisasContext *s, arg_mve_shl_rr *a)
264
+{
265
+ return do_mve_shl_rr(s, a, gen_helper_mve_sshrl);
266
+}
267
+
268
+static bool trans_UQRSHLL64_rr(DisasContext *s, arg_mve_shl_rr *a)
269
+{
270
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll);
271
+}
272
+
273
+static bool trans_SQRSHRL64_rr(DisasContext *s, arg_mve_shl_rr *a)
274
+{
275
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl);
276
+}
277
+
278
+static bool trans_UQRSHLL48_rr(DisasContext *s, arg_mve_shl_rr *a)
279
+{
280
+ return do_mve_shl_rr(s, a, gen_helper_mve_uqrshll48);
281
+}
282
+
283
+static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
284
+{
285
+ return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
286
+}
287
+
288
/*
289
* Multiply and multiply accumulate
290
*/
33
--
291
--
34
2.17.1
292
2.20.1
35
293
36
294
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/31] RISC-V: Add trailing '\n' to qemu_log() calls
[PULL 23/24] target/arm: Implement MVE shifts by immediate
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Implement the MVE shifts by immediate, which perform shifts
2
2
on a single general-purpose register.
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
4
Message-id: 20180606152128.449-11-f4bug@amsat.org
4
These patterns overlap with the long-shift-by-immediates,
5
so we have to rearrange the grouping a little here.
6
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
6
---
10
---
7
target/riscv/op_helper.c | 6 ++++--
11
target/arm/helper-mve.h | 3 ++
8
1 file changed, 4 insertions(+), 2 deletions(-)
12
target/arm/translate.h | 1 +
9
13
target/arm/t32.decode | 31 ++++++++++++++-----
10
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
14
target/arm/mve_helper.c | 10 ++++++
11
index XXXXXXX..XXXXXXX 100644
15
target/arm/translate.c | 68 +++++++++++++++++++++++++++++++++++++++--
12
--- a/target/riscv/op_helper.c
16
5 files changed, 104 insertions(+), 9 deletions(-)
13
+++ b/target/riscv/op_helper.c
17
14
@@ -XXX,XX +XXX,XX @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
18
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
15
if ((val_to_write & 3) == 0) {
19
index XXXXXXX..XXXXXXX 100644
16
env->stvec = val_to_write >> 2 << 2;
20
--- a/target/arm/helper-mve.h
17
} else {
21
+++ b/target/arm/helper-mve.h
18
- qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported");
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_sqrshrl, TCG_CALL_NO_RWG, i64, env, i64, i32)
19
+ qemu_log_mask(LOG_UNIMP,
23
DEF_HELPER_FLAGS_3(mve_uqrshll, TCG_CALL_NO_RWG, i64, env, i64, i32)
20
+ "CSR_STVEC: vectored traps not supported\n");
24
DEF_HELPER_FLAGS_3(mve_sqrshrl48, TCG_CALL_NO_RWG, i64, env, i64, i32)
21
}
25
DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
22
break;
26
+
23
case CSR_SCOUNTEREN:
27
+DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
24
@@ -XXX,XX +XXX,XX @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
28
+DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
25
if ((val_to_write & 3) == 0) {
29
diff --git a/target/arm/translate.h b/target/arm/translate.h
26
env->mtvec = val_to_write >> 2 << 2;
30
index XXXXXXX..XXXXXXX 100644
27
} else {
31
--- a/target/arm/translate.h
28
- qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported");
32
+++ b/target/arm/translate.h
29
+ qemu_log_mask(LOG_UNIMP,
33
@@ -XXX,XX +XXX,XX @@ typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
30
+ "CSR_MTVEC: vectored traps not supported\n");
34
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
31
}
35
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
32
break;
36
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
33
case CSR_MCOUNTEREN:
37
+typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
38
39
/**
40
* arm_tbflags_from_tb:
41
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/t32.decode
44
+++ b/target/arm/t32.decode
45
@@ -XXX,XX +XXX,XX @@
46
47
&mve_shl_ri rdalo rdahi shim
48
&mve_shl_rr rdalo rdahi rm
49
+&mve_sh_ri rda shim
50
51
# rdahi: bits [3:1] from insn, bit 0 is 1
52
# rdalo: bits [3:1] from insn, bit 0 is 0
53
@@ -XXX,XX +XXX,XX @@
54
&mve_shl_ri shim=%imm5_12_6 rdalo=%rdalo_17 rdahi=%rdahi_9
55
@mve_shl_rr ....... .... . ... . rm:4 ... . .. .. .... \
56
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
57
+@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
58
+ &mve_sh_ri shim=%imm5_12_6
59
60
{
61
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
62
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
63
# the rest fall through (where ORR_rrri and MOV_rxri will end up
64
# handling them as r13 and r15 accesses with the same semantics as A32).
65
[
66
- LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
67
- LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
68
- ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
69
+ {
70
+ UQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 00 1111 @mve_sh_ri
71
+ LSLL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 00 1111 @mve_shl_ri
72
+ UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
73
+ }
74
75
- UQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 00 1111 @mve_shl_ri
76
- URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
77
- SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
78
- SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
79
+ {
80
+ URSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 01 1111 @mve_sh_ri
81
+ LSRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 01 1111 @mve_shl_ri
82
+ URSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 01 1111 @mve_shl_ri
83
+ }
84
+
85
+ {
86
+ SRSHR_ri 1110101 0010 1 .... 0 ... 1111 .. 10 1111 @mve_sh_ri
87
+ ASRL_ri 1110101 0010 1 ... 0 0 ... ... 1 .. 10 1111 @mve_shl_ri
88
+ SRSHRL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 10 1111 @mve_shl_ri
89
+ }
90
+
91
+ {
92
+ SQSHL_ri 1110101 0010 1 .... 0 ... 1111 .. 11 1111 @mve_sh_ri
93
+ SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
94
+ }
95
96
LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
97
ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
98
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/mve_helper.c
101
+++ b/target/arm/mve_helper.c
102
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(mve_uqrshll48)(CPUARMState *env, uint64_t n, uint32_t shift)
103
{
104
return do_uqrshl48_d(n, (int8_t)shift, true, &env->QF);
105
}
106
+
107
+uint32_t HELPER(mve_uqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
108
+{
109
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
110
+}
111
+
112
+uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
113
+{
114
+ return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
115
+}
116
diff --git a/target/arm/translate.c b/target/arm/translate.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/arm/translate.c
119
+++ b/target/arm/translate.c
120
@@ -XXX,XX +XXX,XX @@ static void gen_srshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
121
122
static void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
123
{
124
- TCGv_i32 t = tcg_temp_new_i32();
125
+ TCGv_i32 t;
126
127
+ /* Handle shift by the input size for the benefit of trans_SRSHR_ri */
128
+ if (sh == 32) {
129
+ tcg_gen_movi_i32(d, 0);
130
+ return;
131
+ }
132
+ t = tcg_temp_new_i32();
133
tcg_gen_extract_i32(t, a, sh - 1, 1);
134
tcg_gen_sari_i32(d, a, sh);
135
tcg_gen_add_i32(d, d, t);
136
@@ -XXX,XX +XXX,XX @@ static void gen_urshr16_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh)
137
138
static void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh)
139
{
140
- TCGv_i32 t = tcg_temp_new_i32();
141
+ TCGv_i32 t;
142
143
+ /* Handle shift by the input size for the benefit of trans_URSHR_ri */
144
+ if (sh == 32) {
145
+ tcg_gen_extract_i32(d, a, sh - 1, 1);
146
+ return;
147
+ }
148
+ t = tcg_temp_new_i32();
149
tcg_gen_extract_i32(t, a, sh - 1, 1);
150
tcg_gen_shri_i32(d, a, sh);
151
tcg_gen_add_i32(d, d, t);
152
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRSHRL48_rr(DisasContext *s, arg_mve_shl_rr *a)
153
return do_mve_shl_rr(s, a, gen_helper_mve_sqrshrl48);
154
}
155
156
+static bool do_mve_sh_ri(DisasContext *s, arg_mve_sh_ri *a, ShiftImmFn *fn)
157
+{
158
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
159
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
160
+ return false;
161
+ }
162
+ if (!dc_isar_feature(aa32_mve, s) ||
163
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
164
+ a->rda == 13 || a->rda == 15) {
165
+ /* These rda cases are UNPREDICTABLE; we choose to UNDEF */
166
+ unallocated_encoding(s);
167
+ return true;
168
+ }
169
+
170
+ if (a->shim == 0) {
171
+ a->shim = 32;
172
+ }
173
+ fn(cpu_R[a->rda], cpu_R[a->rda], a->shim);
174
+
175
+ return true;
176
+}
177
+
178
+static bool trans_URSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
179
+{
180
+ return do_mve_sh_ri(s, a, gen_urshr32_i32);
181
+}
182
+
183
+static bool trans_SRSHR_ri(DisasContext *s, arg_mve_sh_ri *a)
184
+{
185
+ return do_mve_sh_ri(s, a, gen_srshr32_i32);
186
+}
187
+
188
+static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
189
+{
190
+ gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift));
191
+}
192
+
193
+static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
194
+{
195
+ return do_mve_sh_ri(s, a, gen_mve_sqshl);
196
+}
197
+
198
+static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift)
199
+{
200
+ gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift));
201
+}
202
+
203
+static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
204
+{
205
+ return do_mve_sh_ri(s, a, gen_mve_uqshl);
206
+}
207
+
208
/*
209
* Multiply and multiply accumulate
210
*/
34
--
211
--
35
2.17.1
212
2.20.1
36
213
37
214
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/31] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
[PULL 24/24] target/arm: Implement MVE shifts by register
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
Implement the MVE shifts by register, which perform
2
shifts on a single general-purpose register.
2
3
3
While we skip the GIC_INTERNAL irqs, we don't change the register offset
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
accordingly. This will overlap the GICR registers value and leave the
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
last GIC_INTERNAL irq's registers out of update.
6
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
7
---
8
target/arm/helper-mve.h | 2 ++
9
target/arm/translate.h | 1 +
10
target/arm/t32.decode | 18 ++++++++++++++----
11
target/arm/mve_helper.c | 10 ++++++++++
12
target/arm/translate.c | 30 ++++++++++++++++++++++++++++++
13
5 files changed, 57 insertions(+), 4 deletions(-)
6
14
7
Fix this by skipping the registers banked by GICR.
15
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
8
9
Also for migration compatibility if the migration source (old version
10
qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then
11
we shift the data of PPI to get the right data for SPI.
12
13
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
14
Cc: qemu-stable@nongnu.org
15
Reviewed-by: Eric Auger <eric.auger@redhat.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
18
Message-id: 1527816987-16108-1-git-send-email-zhaoshenglong@huawei.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/intc/arm_gicv3_common.h | 1 +
22
hw/intc/arm_gicv3_common.c | 79 ++++++++++++++++++++++++++++++
23
hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++
24
3 files changed, 118 insertions(+)
25
26
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
27
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/intc/arm_gicv3_common.h
17
--- a/target/arm/helper-mve.h
29
+++ b/include/hw/intc/arm_gicv3_common.h
18
+++ b/target/arm/helper-mve.h
30
@@ -XXX,XX +XXX,XX @@ struct GICv3State {
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_uqrshll48, TCG_CALL_NO_RWG, i64, env, i64, i32)
31
uint32_t revision;
20
32
bool security_extn;
21
DEF_HELPER_FLAGS_3(mve_uqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
33
bool irq_reset_nonsecure;
22
DEF_HELPER_FLAGS_3(mve_sqshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
34
+ bool gicd_no_migration_shift_bug;
23
+DEF_HELPER_FLAGS_3(mve_uqrshl, TCG_CALL_NO_RWG, i32, env, i32, i32)
35
24
+DEF_HELPER_FLAGS_3(mve_sqrshr, TCG_CALL_NO_RWG, i32, env, i32, i32)
36
int dev_fd; /* kvm device fd if backed by kvm vgic support */
25
diff --git a/target/arm/translate.h b/target/arm/translate.h
37
Error *migration_blocker;
38
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
39
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/intc/arm_gicv3_common.c
27
--- a/target/arm/translate.h
41
+++ b/hw/intc/arm_gicv3_common.c
28
+++ b/target/arm/translate.h
29
@@ -XXX,XX +XXX,XX @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
30
typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
31
typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
32
typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
33
+typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
34
35
/**
36
* arm_tbflags_from_tb:
37
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/t32.decode
40
+++ b/target/arm/t32.decode
42
@@ -XXX,XX +XXX,XX @@
41
@@ -XXX,XX +XXX,XX @@
43
#include "hw/intc/arm_gicv3_common.h"
42
&mve_shl_ri rdalo rdahi shim
44
#include "gicv3_internal.h"
43
&mve_shl_rr rdalo rdahi rm
45
#include "hw/arm/linux-boot-if.h"
44
&mve_sh_ri rda shim
46
+#include "sysemu/kvm.h"
45
+&mve_sh_rr rda rm
47
46
48
static int gicv3_pre_save(void *opaque)
47
# rdahi: bits [3:1] from insn, bit 0 is 1
48
# rdalo: bits [3:1] from insn, bit 0 is 0
49
@@ -XXX,XX +XXX,XX @@
50
&mve_shl_rr rdalo=%rdalo_17 rdahi=%rdahi_9
51
@mve_sh_ri ....... .... . rda:4 . ... ... . .. .. .... \
52
&mve_sh_ri shim=%imm5_12_6
53
+@mve_sh_rr ....... .... . rda:4 rm:4 .... .... .... &mve_sh_rr
54
49
{
55
{
50
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
56
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
57
@@ -XXX,XX +XXX,XX @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
58
SQSHLL_ri 1110101 0010 1 ... 1 0 ... ... 1 .. 11 1111 @mve_shl_ri
51
}
59
}
52
};
60
53
61
- LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
54
+static int gicv3_gicd_no_migration_shift_bug_pre_load(void *opaque)
62
- ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
55
+{
63
- UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
56
+ GICv3State *cs = opaque;
64
- SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
57
+
65
+ {
58
+ /*
66
+ UQRSHL_rr 1110101 0010 1 .... .... 1111 0000 1101 @mve_sh_rr
59
+ * The gicd_no_migration_shift_bug flag is used for migration compatibility
67
+ LSLL_rr 1110101 0010 1 ... 0 .... ... 1 0000 1101 @mve_shl_rr
60
+ * for old version QEMU which may have the GICD bmp shift bug under KVM mode.
68
+ UQRSHLL64_rr 1110101 0010 1 ... 1 .... ... 1 0000 1101 @mve_shl_rr
61
+ * Strictly, what we want to know is whether the migration source is using
62
+ * KVM. Since we don't have any way to determine that, we look at whether the
63
+ * destination is using KVM; this is close enough because for the older QEMU
64
+ * versions with this bug KVM -> TCG migration didn't work anyway. If the
65
+ * source is a newer QEMU without this bug it will transmit the migration
66
+ * subsection which sets the flag to true; otherwise it will remain set to
67
+ * the value we select here.
68
+ */
69
+ if (kvm_enabled()) {
70
+ cs->gicd_no_migration_shift_bug = false;
71
+ }
69
+ }
72
+
70
+
73
+ return 0;
71
+ {
72
+ SQRSHR_rr 1110101 0010 1 .... .... 1111 0010 1101 @mve_sh_rr
73
+ ASRL_rr 1110101 0010 1 ... 0 .... ... 1 0010 1101 @mve_shl_rr
74
+ SQRSHRL64_rr 1110101 0010 1 ... 1 .... ... 1 0010 1101 @mve_shl_rr
75
+ }
76
+
77
UQRSHLL48_rr 1110101 0010 1 ... 1 .... ... 1 1000 1101 @mve_shl_rr
78
SQRSHRL48_rr 1110101 0010 1 ... 1 .... ... 1 1010 1101 @mve_shl_rr
79
]
80
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/mve_helper.c
83
+++ b/target/arm/mve_helper.c
84
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mve_sqshl)(CPUARMState *env, uint32_t n, uint32_t shift)
85
{
86
return do_sqrshl_bhs(n, (int8_t)shift, 32, false, &env->QF);
87
}
88
+
89
+uint32_t HELPER(mve_uqrshl)(CPUARMState *env, uint32_t n, uint32_t shift)
90
+{
91
+ return do_uqrshl_bhs(n, (int8_t)shift, 32, true, &env->QF);
74
+}
92
+}
75
+
93
+
76
+static int gicv3_gicd_no_migration_shift_bug_post_load(void *opaque,
94
+uint32_t HELPER(mve_sqrshr)(CPUARMState *env, uint32_t n, uint32_t shift)
77
+ int version_id)
78
+{
95
+{
79
+ GICv3State *cs = opaque;
96
+ return do_sqrshl_bhs(n, -(int8_t)shift, 32, true, &env->QF);
80
+
97
+}
81
+ if (cs->gicd_no_migration_shift_bug) {
98
diff --git a/target/arm/translate.c b/target/arm/translate.c
82
+ return 0;
99
index XXXXXXX..XXXXXXX 100644
100
--- a/target/arm/translate.c
101
+++ b/target/arm/translate.c
102
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a)
103
return do_mve_sh_ri(s, a, gen_mve_uqshl);
104
}
105
106
+static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_rr *a, ShiftFn *fn)
107
+{
108
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
109
+ /* Decode falls through to ORR/MOV UNPREDICTABLE handling */
110
+ return false;
111
+ }
112
+ if (!dc_isar_feature(aa32_mve, s) ||
113
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN) ||
114
+ a->rda == 13 || a->rda == 15 || a->rm == 13 || a->rm == 15 ||
115
+ a->rm == a->rda) {
116
+ /* These rda/rm cases are UNPREDICTABLE; we choose to UNDEF */
117
+ unallocated_encoding(s);
118
+ return true;
83
+ }
119
+ }
84
+
120
+
85
+ /* Older versions of QEMU had a bug in the handling of state save/restore
121
+ /* The helper takes care of the sign-extension of the low 8 bits of Rm */
86
+ * to the KVM GICv3: they got the offset in the bitmap arrays wrong,
122
+ fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]);
87
+ * so that instead of the data for external interrupts 32 and up
123
+ return true;
88
+ * starting at bit position 32 in the bitmap, it started at bit
89
+ * position 64. If we're receiving data from a QEMU with that bug,
90
+ * we must move the data down into the right place.
91
+ */
92
+ memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8,
93
+ sizeof(cs->group) - GIC_INTERNAL / 8);
94
+ memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8,
95
+ sizeof(cs->grpmod) - GIC_INTERNAL / 8);
96
+ memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8,
97
+ sizeof(cs->enabled) - GIC_INTERNAL / 8);
98
+ memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8,
99
+ sizeof(cs->pending) - GIC_INTERNAL / 8);
100
+ memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8,
101
+ sizeof(cs->active) - GIC_INTERNAL / 8);
102
+ memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8,
103
+ sizeof(cs->edge_trigger) - GIC_INTERNAL / 8);
104
+
105
+ /*
106
+ * While this new version QEMU doesn't have this kind of bug as we fix it,
107
+ * so it needs to set the flag to true to indicate that and it's necessary
108
+ * for next migration to work from this new version QEMU.
109
+ */
110
+ cs->gicd_no_migration_shift_bug = true;
111
+
112
+ return 0;
113
+}
124
+}
114
+
125
+
115
+const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
126
+static bool trans_SQRSHR_rr(DisasContext *s, arg_mve_sh_rr *a)
116
+ .name = "arm_gicv3/gicd_no_migration_shift_bug",
127
+{
117
+ .version_id = 1,
128
+ return do_mve_sh_rr(s, a, gen_helper_mve_sqrshr);
118
+ .minimum_version_id = 1,
129
+}
119
+ .pre_load = gicv3_gicd_no_migration_shift_bug_pre_load,
120
+ .post_load = gicv3_gicd_no_migration_shift_bug_post_load,
121
+ .fields = (VMStateField[]) {
122
+ VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State),
123
+ VMSTATE_END_OF_LIST()
124
+ }
125
+};
126
+
130
+
127
static const VMStateDescription vmstate_gicv3 = {
131
+static bool trans_UQRSHL_rr(DisasContext *s, arg_mve_sh_rr *a)
128
.name = "arm_gicv3",
132
+{
129
.version_id = 1,
133
+ return do_mve_sh_rr(s, a, gen_helper_mve_uqrshl);
130
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
134
+}
131
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
132
vmstate_gicv3_cpu, GICv3CPUState),
133
VMSTATE_END_OF_LIST()
134
+ },
135
+ .subsections = (const VMStateDescription * []) {
136
+ &vmstate_gicv3_gicd_no_migration_shift_bug,
137
+ NULL
138
}
139
};
140
141
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_reset(DeviceState *dev)
142
gicv3_gicd_group_set(s, i);
143
}
144
}
145
+ s->gicd_no_migration_shift_bug = true;
146
}
147
148
static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
149
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/hw/intc/arm_gicv3_kvm.c
152
+++ b/hw/intc/arm_gicv3_kvm.c
153
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
154
uint32_t reg;
155
int irq;
156
157
+ /* For the KVM GICv3, affinity routing is always enabled, and the first 2
158
+ * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
159
+ * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
160
+ * them. So it should increase the offset to skip GIC_INTERNAL irqs.
161
+ * This matches the for_each_dist_irq_reg() macro which also skips the
162
+ * first GIC_INTERNAL irqs.
163
+ */
164
+ offset += (GIC_INTERNAL * 2) / 8;
165
for_each_dist_irq_reg(irq, s->num_irq, 2) {
166
kvm_gicd_access(s, offset, &reg, false);
167
reg = half_unshuffle32(reg >> 1);
168
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
169
uint32_t reg;
170
int irq;
171
172
+ /* For the KVM GICv3, affinity routing is always enabled, and the first 2
173
+ * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
174
+ * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
175
+ * them. So it should increase the offset to skip GIC_INTERNAL irqs.
176
+ * This matches the for_each_dist_irq_reg() macro which also skips the
177
+ * first GIC_INTERNAL irqs.
178
+ */
179
+ offset += (GIC_INTERNAL * 2) / 8;
180
for_each_dist_irq_reg(irq, s->num_irq, 2) {
181
reg = *gic_bmp_ptr32(bmp, irq);
182
if (irq % 32 != 0) {
183
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
184
uint32_t reg;
185
int irq;
186
187
+ /* For the KVM GICv3, affinity routing is always enabled, and the
188
+ * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
189
+ * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
190
+ * functionality is replaced by the GICR registers. It doesn't need to sync
191
+ * them. So it should increase the offset to skip GIC_INTERNAL irqs.
192
+ * This matches the for_each_dist_irq_reg() macro which also skips the
193
+ * first GIC_INTERNAL irqs.
194
+ */
195
+ offset += (GIC_INTERNAL * 1) / 8;
196
for_each_dist_irq_reg(irq, s->num_irq, 1) {
197
kvm_gicd_access(s, offset, &reg, false);
198
*gic_bmp_ptr32(bmp, irq) = reg;
199
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
200
uint32_t reg;
201
int irq;
202
203
+ /* For the KVM GICv3, affinity routing is always enabled, and the
204
+ * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
205
+ * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
206
+ * functionality is replaced by the GICR registers. It doesn't need to sync
207
+ * them. So it should increase the offset and clroffset to skip GIC_INTERNAL
208
+ * irqs. This matches the for_each_dist_irq_reg() macro which also skips the
209
+ * first GIC_INTERNAL irqs.
210
+ */
211
+ offset += (GIC_INTERNAL * 1) / 8;
212
+ if (clroffset != 0) {
213
+ clroffset += (GIC_INTERNAL * 1) / 8;
214
+ }
215
+
135
+
216
for_each_dist_irq_reg(irq, s->num_irq, 1) {
136
/*
217
/* If this bitmap is a set/clear register pair, first write to the
137
* Multiply and multiply accumulate
218
* clear-reg to clear all bits before using the set-reg to write
138
*/
219
--
139
--
220
2.17.1
140
2.20.1
221
141
222
142
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/31] aspeed: Add EEPROM I2C devices
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The Aspeed boards have at least one EEPROM to hold the Vital Product
4
Data (VPD).
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
8
Message-id: 20180530064049.27976-6-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/aspeed.c | 13 +++++++++++++
12
1 file changed, 13 insertions(+)
13
14
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/aspeed.c
17
+++ b/hw/arm/aspeed.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/arm/arm.h"
20
#include "hw/arm/aspeed_soc.h"
21
#include "hw/boards.h"
22
+#include "hw/i2c/smbus.h"
23
#include "qemu/log.h"
24
#include "sysemu/block-backend.h"
25
#include "hw/loader.h"
26
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
27
{
28
AspeedSoCState *soc = &bmc->soc;
29
DeviceState *dev;
30
+ uint8_t *eeprom_buf = g_malloc0(32 * 1024);
31
32
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
33
* enough to provide basic RTC features. Alarms will be missing */
34
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
35
36
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
37
+ eeprom_buf);
38
+
39
/* add a TMP423 temperature sensor */
40
dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
41
"tmp423", 0x4c);
42
@@ -XXX,XX +XXX,XX @@ static const TypeInfo palmetto_bmc_type = {
43
static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
44
{
45
AspeedSoCState *soc = &bmc->soc;
46
+ uint8_t *eeprom_buf = g_malloc0(8 * 1024);
47
+
48
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
49
+ eeprom_buf);
50
51
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
52
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
53
@@ -XXX,XX +XXX,XX @@ static const TypeInfo romulus_bmc_type = {
54
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
55
{
56
AspeedSoCState *soc = &bmc->soc;
57
+ uint8_t *eeprom_buf = g_malloc0(8 * 1024);
58
59
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
60
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
61
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
62
/* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
63
* good enough */
64
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
65
+
66
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
67
+ eeprom_buf);
68
}
69
70
static void witherspoon_bmc_init(MachineState *machine)
71
--
72
2.17.1
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/31] ftgmac100: add IEEE 802.1Q VLAN support
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The ftgmac100 NIC supports VLAN tag insertion and the MAC engine also
4
has a control to remove VLAN tags from received packets.
5
6
The VLAN control bits and VLAN tag information are contained in the
7
second word of the transmit and receive descriptors. The Insert VLAN
8
bit and the VLAN Tag available bit are only valid in the first segment
9
of the packet.
10
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180530061711.23673-3-clg@kaod.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/net/ftgmac100.c | 31 ++++++++++++++++++++++++++++++-
17
1 file changed, 30 insertions(+), 1 deletion(-)
18
19
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/ftgmac100.c
22
+++ b/hw/net/ftgmac100.c
23
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
24
break;
25
}
26
27
+ /* Check for VLAN */
28
+ if (bd.des0 & FTGMAC100_TXDES0_FTS &&
29
+ bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
30
+ be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
31
+ if (frame_size + len + 4 > sizeof(s->frame)) {
32
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
33
+ __func__, len);
34
+ s->isr |= FTGMAC100_INT_XPKT_LOST;
35
+ len = sizeof(s->frame) - frame_size - 4;
36
+ }
37
+ memmove(ptr + 16, ptr + 12, len - 12);
38
+ stw_be_p(ptr + 12, ETH_P_VLAN);
39
+ stw_be_p(ptr + 14, bd.des1);
40
+ len += 4;
41
+ }
42
+
43
ptr += len;
44
frame_size += len;
45
if (bd.des0 & FTGMAC100_TXDES0_LTS) {
46
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
47
buf_len += size - 4;
48
}
49
buf_addr = bd.des3;
50
- dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
51
+ if (first && proto == ETH_P_VLAN && buf_len >= 18) {
52
+ bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
53
+
54
+ if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
55
+ dma_memory_write(&address_space_memory, buf_addr, buf, 12);
56
+ dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
57
+ buf_len - 16);
58
+ } else {
59
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
60
+ }
61
+ } else {
62
+ bd.des1 = 0;
63
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
64
+ }
65
buf += buf_len;
66
if (size < 4) {
67
dma_memory_write(&address_space_memory, buf_addr + buf_len,
68
--
69
2.17.1
70
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/31] ftgmac100: fix multicast hash routine
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Based on the multicast hash calculation of the FTGMAC100 Linux driver.
4
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180530061711.23673-4-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/ftgmac100.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/ftgmac100.c
16
+++ b/hw/net/ftgmac100.c
17
@@ -XXX,XX +XXX,XX @@ static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
18
return 0;
19
}
20
21
- /* TODO: this does not seem to work for ftgmac100 */
22
- mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
23
+ mcast_idx = net_crc32_le(buf, ETH_ALEN);
24
+ mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
25
if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
26
return 0;
27
}
28
--
29
2.17.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/31] ftgmac100: remove check on runt messages
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
This is a ethernet wire limitation not needed in emulation. It breaks
4
U-Boot n/w stack also.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 20180530061711.23673-5-clg@kaod.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/ftgmac100.c | 6 ------
12
1 file changed, 6 deletions(-)
13
14
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/ftgmac100.c
17
+++ b/hw/net/ftgmac100.c
18
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
19
return size;
20
}
21
22
- if (size < 64 && !(s->maccr & FTGMAC100_MACCR_RX_RUNT)) {
23
- qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped runt frame of %zd bytes\n",
24
- __func__, size);
25
- return size;
26
- }
27
-
28
if (!ftgmac100_filter(s, buf, size)) {
29
return size;
30
}
31
--
32
2.17.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/31] hw/sd/milkymist-memcard: Add trailing '\n' to qemu_log() call
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-2-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/sd/milkymist-memcard.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/milkymist-memcard.c
14
+++ b/hw/sd/milkymist-memcard.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t memcard_read(void *opaque, hwaddr addr,
16
r = s->response[s->response_read_ptr++];
17
if (s->response_read_ptr > s->response_len) {
18
qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
19
- "read more cmd bytes than available. Clipping.");
20
+ "read more cmd bytes than available: clipping\n");
21
s->response_read_ptr = 0;
22
}
23
}
24
--
25
2.17.1
26
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/31] xilinx-dp: Add trailing '\n' to qemu_log() call
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20180606152128.449-4-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/display/xlnx_dp.c | 4 +++-
9
1 file changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/display/xlnx_dp.c
14
+++ b/hw/display/xlnx_dp.c
15
@@ -XXX,XX +XXX,XX @@ static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
16
case AV_BUF_STC_SNAPSHOT1:
17
case AV_BUF_HCOUNT_VCOUNT_INT0:
18
case AV_BUF_HCOUNT_VCOUNT_INT1:
19
- qemu_log_mask(LOG_UNIMP, "avbufm: unimplmented");
20
+ qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04"
21
+ PRIx64 "\n",
22
+ offset << 2);
23
break;
24
default:
25
s->avbufm_registers[offset] = value;
26
--
27
2.17.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/31] stellaris: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-8-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/stellaris.c | 11 ++++++-----
9
1 file changed, 6 insertions(+), 5 deletions(-)
10
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/stellaris.c
14
+++ b/hw/arm/stellaris.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t gptm_read(void *opaque, hwaddr offset,
16
return s->rtc;
17
}
18
qemu_log_mask(LOG_UNIMP,
19
- "GPTM: read of TAR but timer read not supported");
20
+ "GPTM: read of TAR but timer read not supported\n");
21
return 0;
22
case 0x4c: /* TBR */
23
qemu_log_mask(LOG_UNIMP,
24
- "GPTM: read of TBR but timer read not supported");
25
+ "GPTM: read of TBR but timer read not supported\n");
26
return 0;
27
default:
28
qemu_log_mask(LOG_GUEST_ERROR,
29
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
30
break;
31
case 0x20: /* MCR */
32
if (value & 1) {
33
- qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
34
+ qemu_log_mask(LOG_UNIMP,
35
+ "stellaris_i2c: Loopback not implemented\n");
36
}
37
if (value & 0x20) {
38
qemu_log_mask(LOG_UNIMP,
39
- "stellaris_i2c: Slave mode not implemented");
40
+ "stellaris_i2c: Slave mode not implemented\n");
41
}
42
s->mcr = value & 0x31;
43
break;
44
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
45
s->sspri = value;
46
break;
47
case 0x28: /* PSSI */
48
- qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
49
+ qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
50
break;
51
case 0x30: /* SAC */
52
s->sac = value;
53
--
54
2.17.1
55
56
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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