[Qemu-devel] [PULL 00/31] target-arm queue
[Qemu-devel] [PULL 00/17] target-arm queue
1
target-arm queue: aspeed patches from Cédric, and
1
v2: dropped a couple of cadence_gem changes to ID regs that
2
cleanup and sd card patches from Philippe.
2
caused new clang sanitizer warnings.
3
3
4
thanks
4
-- PMM
5
-- PMM
6
5
7
The following changes since commit bac5ba3dc5da706f52c149fa6c0bd1dc96899bec:
6
The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
8
7
9
Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging (2018-06-08 10:26:16 +0100)
8
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
10
9
11
are available in the Git repository at:
10
are available in the Git repository at:
12
11
13
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180608
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
14
13
15
for you to fetch changes up to 113f31c06c6bf16451892b2459d83c9b9c5e9844:
14
for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
16
15
17
sdcard: Disable CMD19/CMD23 for Spec v2 (2018-06-08 13:15:34 +0100)
16
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
18
17
19
----------------------------------------------------------------
18
----------------------------------------------------------------
20
target-arm queue:
19
target-arm queue:
21
* arm_gicv3_kvm: fix migration of registers corresponding to
20
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
22
IRQs 992 to 1020 in the KVM GIC
21
* target/arm: Fix aarch64_sve_change_el wrt EL0
23
* aspeed: remove ignore_memory_transaction_failures on all boards
22
* target/arm: Define fields of ISAR registers
24
* aspeed: add support for the witherspoon-bmc board
23
* target/arm: Align cortex-r5 id_isar0
25
* aspeed: add an I2C RTC device and EEPROM I2C devices
24
* target/arm: Fix cortex-a7 id_isar0
26
* aspeed: add the pc9552 chips to the witherspoon machine
25
* net/cadence_gem: Fix various bugs, add support for new
27
* ftgmac100: fix various bugs
26
features that will be used by the Xilinx Versal board
28
* hw/arm: Remove the deprecated xlnx-ep108 machine
27
* target-arm: powerctl: Enable HVC when starting CPUs to EL2
29
* hw/i2c: Add trace events
28
* target/arm: Add the Cortex-A72
30
* add missing '\n' on various qemu_log() logging strings
29
* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
31
* sdcard: clean up spec version support so we report the
30
* target/arm: Mask PMOVSR writes based on supported counters
32
right spec version to the guest and only implement the
31
* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
33
commands that are supposed to be present in that version
32
* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
34
33
35
----------------------------------------------------------------
34
----------------------------------------------------------------
36
Cédric Le Goater (11):
35
Aaron Lindsay (2):
37
aspeed: remove ignore_memory_transaction_failures on all boards
36
target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
38
aspeed: add support for the witherspoon-bmc board
37
target/arm: Mask PMOVSR writes based on supported counters
39
aspeed: add an I2C RTC device to all machines
40
smbus: add a smbus_eeprom_init_one() routine
41
aspeed: Add EEPROM I2C devices
42
misc: add pca9552 LED blinker model
43
aspeed: add the pc9552 chips to the witherspoon machine
44
ftgmac100: compute maximum frame size depending on the protocol
45
ftgmac100: add IEEE 802.1Q VLAN support
46
ftgmac100: fix multicast hash routine
47
ftgmac100: remove check on runt messages
48
38
49
Philippe Mathieu-Daudé (18):
39
Edgar E. Iglesias (8):
50
hw/i2c: Add trace events
40
net: cadence_gem: Disable TSU feature bit
51
hw/sd/milkymist-memcard: Add trailing '\n' to qemu_log() call
41
net: cadence_gem: Use uint32_t for 32bit descriptor words
52
hw/digic: Add trailing '\n' to qemu_log() calls
42
net: cadence_gem: Add macro with max number of descriptor words
53
xilinx-dp: Add trailing '\n' to qemu_log() call
43
net: cadence_gem: Add support for extended descriptors
54
ppc/pnv: Add trailing '\n' to qemu_log() calls
44
net: cadence_gem: Add support for selecting the DMA MemoryRegion
55
hw/core/register: Add trailing '\n' to qemu_log() call
45
net: cadence_gem: Implement support for 64bit descriptor addresses
56
hw/mips/boston: Add trailing '\n' to qemu_log() calls
46
target-arm: powerctl: Enable HVC when starting CPUs to EL2
57
stellaris: Add trailing '\n' to qemu_log() calls
47
target/arm: Add the Cortex-A72
58
target/arm: Add trailing '\n' to qemu_log() calls
59
target/m68k: Add trailing '\n' to qemu_log() call
60
RISC-V: Add trailing '\n' to qemu_log() calls
61
target/xtensa: Add trailing '\n' to qemu_log() calls
62
sdcard: Update the Configuration Register (SCR) to Spec Version 1.10
63
sdcard: Allow commands valid in SPI mode
64
sdcard: Add a 'spec_version' property, default to Spec v2.00
65
sdcard: Disable SEND_IF_COND (CMD8) for Spec v1
66
sdcard: Reflect when the Spec v3 is supported in the Config Register (SCR)
67
sdcard: Disable CMD19/CMD23 for Spec v2
68
48
69
Shannon Zhao (1):
49
Jerome Forissier (1):
70
arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
50
hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
71
51
72
Thomas Huth (1):
52
Peter Maydell (2):
73
hw/arm: Remove the deprecated xlnx-ep108 machine
53
target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
54
coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
74
55
75
Makefile.objs | 1 +
56
Richard Henderson (4):
76
hw/misc/Makefile.objs | 1 +
57
target/arm: Fix aarch64_sve_change_el wrt EL0
77
tests/Makefile.include | 2 +
58
target/arm: Define fields of ISAR registers
78
include/hw/i2c/smbus.h | 1 +
59
target/arm: Align cortex-r5 id_isar0
79
include/hw/intc/arm_gicv3_common.h | 1 +
60
target/arm: Fix cortex-a7 id_isar0
80
include/hw/misc/pca9552.h | 32 +++++
81
include/hw/misc/pca9552_regs.h | 32 +++++
82
include/hw/net/ftgmac100.h | 7 +-
83
include/hw/sd/sd.h | 6 +
84
tests/libqos/i2c.h | 2 +
85
hw/arm/aspeed.c | 88 +++++++++++++-
86
hw/arm/stellaris.c | 11 +-
87
hw/arm/xlnx-zcu102.c | 62 +---------
88
hw/char/digic-uart.c | 4 +-
89
hw/core/register.c | 2 +-
90
hw/display/xlnx_dp.c | 4 +-
91
hw/i2c/core.c | 25 ++--
92
hw/i2c/smbus_eeprom.c | 16 ++-
93
hw/intc/arm_gicv3_common.c | 79 ++++++++++++
94
hw/intc/arm_gicv3_kvm.c | 38 ++++++
95
hw/mips/boston.c | 8 +-
96
hw/misc/pca9552.c | 240 +++++++++++++++++++++++++++++++++++++
97
hw/net/ftgmac100.c | 64 ++++++----
98
hw/ppc/pnv_core.c | 4 +-
99
hw/sd/milkymist-memcard.c | 2 +-
100
hw/sd/sd.c | 50 +++++---
101
hw/timer/digic-timer.c | 4 +-
102
target/arm/helper.c | 4 +-
103
target/m68k/translate.c | 2 +-
104
target/riscv/op_helper.c | 6 +-
105
target/xtensa/translate.c | 6 +-
106
tests/pca9552-test.c | 116 ++++++++++++++++++
107
tests/tmp105-test.c | 2 -
108
default-configs/arm-softmmu.mak | 1 +
109
hw/i2c/trace-events | 7 ++
110
qemu-doc.texi | 5 -
111
36 files changed, 788 insertions(+), 147 deletions(-)
112
create mode 100644 include/hw/misc/pca9552.h
113
create mode 100644 include/hw/misc/pca9552_regs.h
114
create mode 100644 hw/misc/pca9552.c
115
create mode 100644 tests/pca9552-test.c
116
create mode 100644 hw/i2c/trace-events
117
61
62
include/hw/net/cadence_gem.h | 7 +-
63
target/arm/cpu.h | 95 ++++++++++++++-
64
hw/arm/virt.c | 4 +
65
hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
66
target/arm/arm-powerctl.c | 10 ++
67
target/arm/cpu.c | 7 +-
68
target/arm/cpu64.c | 66 +++++++++-
69
target/arm/helper.c | 27 +++--
70
target/arm/op_helper.c | 6 +-
71
scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
72
10 files changed, 402 insertions(+), 70 deletions(-)
73
create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/31] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR
Deleted patch
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
2
1
3
While we skip the GIC_INTERNAL irqs, we don't change the register offset
4
accordingly. This will overlap the GICR registers value and leave the
5
last GIC_INTERNAL irq's registers out of update.
6
7
Fix this by skipping the registers banked by GICR.
8
9
Also for migration compatibility if the migration source (old version
10
qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then
11
we shift the data of PPI to get the right data for SPI.
12
13
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
14
Cc: qemu-stable@nongnu.org
15
Reviewed-by: Eric Auger <eric.auger@redhat.com>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
18
Message-id: 1527816987-16108-1-git-send-email-zhaoshenglong@huawei.com
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/hw/intc/arm_gicv3_common.h | 1 +
22
hw/intc/arm_gicv3_common.c | 79 ++++++++++++++++++++++++++++++
23
hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++
24
3 files changed, 118 insertions(+)
25
26
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/intc/arm_gicv3_common.h
29
+++ b/include/hw/intc/arm_gicv3_common.h
30
@@ -XXX,XX +XXX,XX @@ struct GICv3State {
31
uint32_t revision;
32
bool security_extn;
33
bool irq_reset_nonsecure;
34
+ bool gicd_no_migration_shift_bug;
35
36
int dev_fd; /* kvm device fd if backed by kvm vgic support */
37
Error *migration_blocker;
38
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/intc/arm_gicv3_common.c
41
+++ b/hw/intc/arm_gicv3_common.c
42
@@ -XXX,XX +XXX,XX @@
43
#include "hw/intc/arm_gicv3_common.h"
44
#include "gicv3_internal.h"
45
#include "hw/arm/linux-boot-if.h"
46
+#include "sysemu/kvm.h"
47
48
static int gicv3_pre_save(void *opaque)
49
{
50
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3_cpu = {
51
}
52
};
53
54
+static int gicv3_gicd_no_migration_shift_bug_pre_load(void *opaque)
55
+{
56
+ GICv3State *cs = opaque;
57
+
58
+ /*
59
+ * The gicd_no_migration_shift_bug flag is used for migration compatibility
60
+ * for old version QEMU which may have the GICD bmp shift bug under KVM mode.
61
+ * Strictly, what we want to know is whether the migration source is using
62
+ * KVM. Since we don't have any way to determine that, we look at whether the
63
+ * destination is using KVM; this is close enough because for the older QEMU
64
+ * versions with this bug KVM -> TCG migration didn't work anyway. If the
65
+ * source is a newer QEMU without this bug it will transmit the migration
66
+ * subsection which sets the flag to true; otherwise it will remain set to
67
+ * the value we select here.
68
+ */
69
+ if (kvm_enabled()) {
70
+ cs->gicd_no_migration_shift_bug = false;
71
+ }
72
+
73
+ return 0;
74
+}
75
+
76
+static int gicv3_gicd_no_migration_shift_bug_post_load(void *opaque,
77
+ int version_id)
78
+{
79
+ GICv3State *cs = opaque;
80
+
81
+ if (cs->gicd_no_migration_shift_bug) {
82
+ return 0;
83
+ }
84
+
85
+ /* Older versions of QEMU had a bug in the handling of state save/restore
86
+ * to the KVM GICv3: they got the offset in the bitmap arrays wrong,
87
+ * so that instead of the data for external interrupts 32 and up
88
+ * starting at bit position 32 in the bitmap, it started at bit
89
+ * position 64. If we're receiving data from a QEMU with that bug,
90
+ * we must move the data down into the right place.
91
+ */
92
+ memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8,
93
+ sizeof(cs->group) - GIC_INTERNAL / 8);
94
+ memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8,
95
+ sizeof(cs->grpmod) - GIC_INTERNAL / 8);
96
+ memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8,
97
+ sizeof(cs->enabled) - GIC_INTERNAL / 8);
98
+ memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8,
99
+ sizeof(cs->pending) - GIC_INTERNAL / 8);
100
+ memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8,
101
+ sizeof(cs->active) - GIC_INTERNAL / 8);
102
+ memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL / 8,
103
+ sizeof(cs->edge_trigger) - GIC_INTERNAL / 8);
104
+
105
+ /*
106
+ * While this new version QEMU doesn't have this kind of bug as we fix it,
107
+ * so it needs to set the flag to true to indicate that and it's necessary
108
+ * for next migration to work from this new version QEMU.
109
+ */
110
+ cs->gicd_no_migration_shift_bug = true;
111
+
112
+ return 0;
113
+}
114
+
115
+const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = {
116
+ .name = "arm_gicv3/gicd_no_migration_shift_bug",
117
+ .version_id = 1,
118
+ .minimum_version_id = 1,
119
+ .pre_load = gicv3_gicd_no_migration_shift_bug_pre_load,
120
+ .post_load = gicv3_gicd_no_migration_shift_bug_post_load,
121
+ .fields = (VMStateField[]) {
122
+ VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State),
123
+ VMSTATE_END_OF_LIST()
124
+ }
125
+};
126
+
127
static const VMStateDescription vmstate_gicv3 = {
128
.name = "arm_gicv3",
129
.version_id = 1,
130
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_gicv3 = {
131
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
132
vmstate_gicv3_cpu, GICv3CPUState),
133
VMSTATE_END_OF_LIST()
134
+ },
135
+ .subsections = (const VMStateDescription * []) {
136
+ &vmstate_gicv3_gicd_no_migration_shift_bug,
137
+ NULL
138
}
139
};
140
141
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_reset(DeviceState *dev)
142
gicv3_gicd_group_set(s, i);
143
}
144
}
145
+ s->gicd_no_migration_shift_bug = true;
146
}
147
148
static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
149
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/hw/intc/arm_gicv3_kvm.c
152
+++ b/hw/intc/arm_gicv3_kvm.c
153
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_get_edge_trigger(GICv3State *s, uint32_t offset,
154
uint32_t reg;
155
int irq;
156
157
+ /* For the KVM GICv3, affinity routing is always enabled, and the first 2
158
+ * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
159
+ * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
160
+ * them. So it should increase the offset to skip GIC_INTERNAL irqs.
161
+ * This matches the for_each_dist_irq_reg() macro which also skips the
162
+ * first GIC_INTERNAL irqs.
163
+ */
164
+ offset += (GIC_INTERNAL * 2) / 8;
165
for_each_dist_irq_reg(irq, s->num_irq, 2) {
166
kvm_gicd_access(s, offset, &reg, false);
167
reg = half_unshuffle32(reg >> 1);
168
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_put_edge_trigger(GICv3State *s, uint32_t offset,
169
uint32_t reg;
170
int irq;
171
172
+ /* For the KVM GICv3, affinity routing is always enabled, and the first 2
173
+ * GICD_ICFGR<n> registers are always RAZ/WI. The corresponding
174
+ * functionality is replaced by GICR_ICFGR<n>. It doesn't need to sync
175
+ * them. So it should increase the offset to skip GIC_INTERNAL irqs.
176
+ * This matches the for_each_dist_irq_reg() macro which also skips the
177
+ * first GIC_INTERNAL irqs.
178
+ */
179
+ offset += (GIC_INTERNAL * 2) / 8;
180
for_each_dist_irq_reg(irq, s->num_irq, 2) {
181
reg = *gic_bmp_ptr32(bmp, irq);
182
if (irq % 32 != 0) {
183
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
184
uint32_t reg;
185
int irq;
186
187
+ /* For the KVM GICv3, affinity routing is always enabled, and the
188
+ * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
189
+ * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
190
+ * functionality is replaced by the GICR registers. It doesn't need to sync
191
+ * them. So it should increase the offset to skip GIC_INTERNAL irqs.
192
+ * This matches the for_each_dist_irq_reg() macro which also skips the
193
+ * first GIC_INTERNAL irqs.
194
+ */
195
+ offset += (GIC_INTERNAL * 1) / 8;
196
for_each_dist_irq_reg(irq, s->num_irq, 1) {
197
kvm_gicd_access(s, offset, &reg, false);
198
*gic_bmp_ptr32(bmp, irq) = reg;
199
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
200
uint32_t reg;
201
int irq;
202
203
+ /* For the KVM GICv3, affinity routing is always enabled, and the
204
+ * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
205
+ * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
206
+ * functionality is replaced by the GICR registers. It doesn't need to sync
207
+ * them. So it should increase the offset and clroffset to skip GIC_INTERNAL
208
+ * irqs. This matches the for_each_dist_irq_reg() macro which also skips the
209
+ * first GIC_INTERNAL irqs.
210
+ */
211
+ offset += (GIC_INTERNAL * 1) / 8;
212
+ if (clroffset != 0) {
213
+ clroffset += (GIC_INTERNAL * 1) / 8;
214
+ }
215
+
216
for_each_dist_irq_reg(irq, s->num_irq, 1) {
217
/* If this bitmap is a set/clear register pair, first write to the
218
* clear-reg to clear all bits before using the set-reg to write
219
--
220
2.17.1
221
222
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/31] aspeed: remove ignore_memory_transaction_failures on all boards
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180530064049.27976-2-clg@kaod.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/aspeed.c | 3 ---
9
1 file changed, 3 deletions(-)
10
11
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/aspeed.c
14
+++ b/hw/arm/aspeed.c
15
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data)
16
mc->no_floppy = 1;
17
mc->no_cdrom = 1;
18
mc->no_parallel = 1;
19
- mc->ignore_memory_transaction_failures = true;
20
}
21
22
static const TypeInfo palmetto_bmc_type = {
23
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data)
24
mc->no_floppy = 1;
25
mc->no_cdrom = 1;
26
mc->no_parallel = 1;
27
- mc->ignore_memory_transaction_failures = true;
28
}
29
30
static const TypeInfo ast2500_evb_type = {
31
@@ -XXX,XX +XXX,XX @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data)
32
mc->no_floppy = 1;
33
mc->no_cdrom = 1;
34
mc->no_parallel = 1;
35
- mc->ignore_memory_transaction_failures = true;
36
}
37
38
static const TypeInfo romulus_bmc_type = {
39
--
40
2.17.1
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/31] aspeed: add support for the witherspoon-bmc board
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The Witherspoon boards are OpenPOWER system hosting POWER9 Processors.
4
Add support for their BMC including a couple of I2C devices as found
5
on real HW.
6
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
9
Message-id: 20180530064049.27976-3-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 49 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
18
+++ b/hw/arm/aspeed.c
19
@@ -XXX,XX +XXX,XX @@ enum {
20
PALMETTO_BMC,
21
AST2500_EVB,
22
ROMULUS_BMC,
23
+ WITHERSPOON_BMC,
24
};
25
26
/* Palmetto hardware value: 0x120CE416 */
27
@@ -XXX,XX +XXX,XX @@ enum {
28
SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
29
SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
30
31
+/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
32
+#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
33
+
34
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
35
static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
36
+static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc);
37
38
static const AspeedBoardConfig aspeed_boards[] = {
39
[PALMETTO_BMC] = {
40
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
41
.spi_model = "mx66l1g45g",
42
.num_cs = 2,
43
},
44
+ [WITHERSPOON_BMC] = {
45
+ .soc_name = "ast2500-a1",
46
+ .hw_strap1 = WITHERSPOON_BMC_HW_STRAP1,
47
+ .fmc_model = "mx25l25635e",
48
+ .spi_model = "mx66l1g45g",
49
+ .num_cs = 2,
50
+ .i2c_init = witherspoon_bmc_i2c_init,
51
+ },
52
};
53
54
#define FIRMWARE_ADDR 0x0
55
@@ -XXX,XX +XXX,XX @@ static const TypeInfo romulus_bmc_type = {
56
.class_init = romulus_bmc_class_init,
57
};
58
59
+static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
60
+{
61
+ AspeedSoCState *soc = &bmc->soc;
62
+
63
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
64
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
65
+
66
+ /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
67
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp105", 0x4a);
68
+}
69
+
70
+static void witherspoon_bmc_init(MachineState *machine)
71
+{
72
+ aspeed_board_init(machine, &aspeed_boards[WITHERSPOON_BMC]);
73
+}
74
+
75
+static void witherspoon_bmc_class_init(ObjectClass *oc, void *data)
76
+{
77
+ MachineClass *mc = MACHINE_CLASS(oc);
78
+
79
+ mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
80
+ mc->init = witherspoon_bmc_init;
81
+ mc->max_cpus = 1;
82
+ mc->no_sdcard = 1;
83
+ mc->no_floppy = 1;
84
+ mc->no_cdrom = 1;
85
+ mc->no_parallel = 1;
86
+}
87
+
88
+static const TypeInfo witherspoon_bmc_type = {
89
+ .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
90
+ .parent = TYPE_MACHINE,
91
+ .class_init = witherspoon_bmc_class_init,
92
+};
93
+
94
static void aspeed_machine_init(void)
95
{
96
type_register_static(&palmetto_bmc_type);
97
type_register_static(&ast2500_evb_type);
98
type_register_static(&romulus_bmc_type);
99
+ type_register_static(&witherspoon_bmc_type);
100
}
101
102
type_init(aspeed_machine_init)
103
--
104
2.17.1
105
106
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/31] aspeed: add an I2C RTC device to all machines
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The AST2500 EVB does not have an RTC but we can pretend that one is
4
plugged on the I2C bus header.
5
6
The romulus and witherspoon boards expects an Epson RX8900 I2C RTC but
7
a ds1338 is good enough for the basic features we need.
8
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
11
Message-id: 20180530064049.27976-4-clg@kaod.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/aspeed.c | 19 +++++++++++++++++++
15
1 file changed, 19 insertions(+)
16
17
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/aspeed.c
20
+++ b/hw/arm/aspeed.c
21
@@ -XXX,XX +XXX,XX @@ enum {
22
23
static void palmetto_bmc_i2c_init(AspeedBoardState *bmc);
24
static void ast2500_evb_i2c_init(AspeedBoardState *bmc);
25
+static void romulus_bmc_i2c_init(AspeedBoardState *bmc);
26
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc);
27
28
static const AspeedBoardConfig aspeed_boards[] = {
29
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
30
.fmc_model = "n25q256a",
31
.spi_model = "mx66l1g45g",
32
.num_cs = 2,
33
+ .i2c_init = romulus_bmc_i2c_init,
34
},
35
[WITHERSPOON_BMC] = {
36
.soc_name = "ast2500-a1",
37
@@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
38
39
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
40
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
41
+
42
+ /* The AST2500 EVB does not have an RTC. Let's pretend that one is
43
+ * plugged on the I2C bus header */
44
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
45
}
46
47
static void ast2500_evb_init(MachineState *machine)
48
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ast2500_evb_type = {
49
.class_init = ast2500_evb_class_init,
50
};
51
52
+static void romulus_bmc_i2c_init(AspeedBoardState *bmc)
53
+{
54
+ AspeedSoCState *soc = &bmc->soc;
55
+
56
+ /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
57
+ * good enough */
58
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
59
+}
60
+
61
static void romulus_bmc_init(MachineState *machine)
62
{
63
aspeed_board_init(machine, &aspeed_boards[ROMULUS_BMC]);
64
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
65
66
/* The Witherspoon expects a TMP275 but a TMP105 is compatible */
67
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp105", 0x4a);
68
+
69
+ /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
70
+ * good enough */
71
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
72
}
73
74
static void witherspoon_bmc_init(MachineState *machine)
75
--
76
2.17.1
77
78
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/31] smbus: add a smbus_eeprom_init_one() routine
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
This is an helper routine to add a single EEPROM on an I2C bus. It can
4
be directly used by smbus_eeprom_init() which adds a certain number of
5
EEPROMs on mips and x86 machines.
6
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180530064049.27976-5-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/i2c/smbus.h | 1 +
13
hw/i2c/smbus_eeprom.c | 16 +++++++++++-----
14
2 files changed, 12 insertions(+), 5 deletions(-)
15
16
diff --git a/include/hw/i2c/smbus.h b/include/hw/i2c/smbus.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/i2c/smbus.h
19
+++ b/include/hw/i2c/smbus.h
20
@@ -XXX,XX +XXX,XX @@ int smbus_read_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data);
21
int smbus_write_block(I2CBus *bus, uint8_t addr, uint8_t command, uint8_t *data,
22
int len);
23
24
+void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf);
25
void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
26
const uint8_t *eeprom_spd, int size);
27
28
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/i2c/smbus_eeprom.c
31
+++ b/hw/i2c/smbus_eeprom.c
32
@@ -XXX,XX +XXX,XX @@ static void smbus_eeprom_register_types(void)
33
34
type_init(smbus_eeprom_register_types)
35
36
+void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
37
+{
38
+ DeviceState *dev;
39
+
40
+ dev = qdev_create((BusState *) smbus, "smbus-eeprom");
41
+ qdev_prop_set_uint8(dev, "address", address);
42
+ qdev_prop_set_ptr(dev, "data", eeprom_buf);
43
+ qdev_init_nofail(dev);
44
+}
45
+
46
void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
47
const uint8_t *eeprom_spd, int eeprom_spd_size)
48
{
49
@@ -XXX,XX +XXX,XX @@ void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
50
}
51
52
for (i = 0; i < nb_eeprom; i++) {
53
- DeviceState *eeprom;
54
- eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
55
- qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
56
- qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
57
- qdev_init_nofail(eeprom);
58
+ smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256));
59
}
60
}
61
--
62
2.17.1
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/31] aspeed: Add EEPROM I2C devices
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The Aspeed boards have at least one EEPROM to hold the Vital Product
4
Data (VPD).
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
8
Message-id: 20180530064049.27976-6-clg@kaod.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/aspeed.c | 13 +++++++++++++
12
1 file changed, 13 insertions(+)
13
14
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/aspeed.c
17
+++ b/hw/arm/aspeed.c
18
@@ -XXX,XX +XXX,XX @@
19
#include "hw/arm/arm.h"
20
#include "hw/arm/aspeed_soc.h"
21
#include "hw/boards.h"
22
+#include "hw/i2c/smbus.h"
23
#include "qemu/log.h"
24
#include "sysemu/block-backend.h"
25
#include "hw/loader.h"
26
@@ -XXX,XX +XXX,XX @@ static void palmetto_bmc_i2c_init(AspeedBoardState *bmc)
27
{
28
AspeedSoCState *soc = &bmc->soc;
29
DeviceState *dev;
30
+ uint8_t *eeprom_buf = g_malloc0(32 * 1024);
31
32
/* The palmetto platform expects a ds3231 RTC but a ds1338 is
33
* enough to provide basic RTC features. Alarms will be missing */
34
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), "ds1338", 0x68);
35
36
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 0), 0x50,
37
+ eeprom_buf);
38
+
39
/* add a TMP423 temperature sensor */
40
dev = i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 2),
41
"tmp423", 0x4c);
42
@@ -XXX,XX +XXX,XX @@ static const TypeInfo palmetto_bmc_type = {
43
static void ast2500_evb_i2c_init(AspeedBoardState *bmc)
44
{
45
AspeedSoCState *soc = &bmc->soc;
46
+ uint8_t *eeprom_buf = g_malloc0(8 * 1024);
47
+
48
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), 0x50,
49
+ eeprom_buf);
50
51
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
52
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d);
53
@@ -XXX,XX +XXX,XX @@ static const TypeInfo romulus_bmc_type = {
54
static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
55
{
56
AspeedSoCState *soc = &bmc->soc;
57
+ uint8_t *eeprom_buf = g_malloc0(8 * 1024);
58
59
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
60
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
61
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
62
/* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
63
* good enough */
64
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "ds1338", 0x32);
65
+
66
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
67
+ eeprom_buf);
68
}
69
70
static void witherspoon_bmc_init(MachineState *machine)
71
--
72
2.17.1
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/31] misc: add pca9552 LED blinker model
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Specs are available here :
4
5
https://www.nxp.com/docs/en/application-note/AN264.pdf
6
7
This is a simple model supporting the basic registers for led and GPIO
8
mode. The device also supports two blinking rates but not the model
9
yet.
10
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20180530064049.27976-7-clg@kaod.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/misc/Makefile.objs | 1 +
18
tests/Makefile.include | 2 +
19
include/hw/misc/pca9552.h | 32 +++++
20
include/hw/misc/pca9552_regs.h | 32 +++++
21
tests/libqos/i2c.h | 2 +
22
hw/misc/pca9552.c | 240 ++++++++++++++++++++++++++++++++
23
tests/pca9552-test.c | 116 +++++++++++++++
24
tests/tmp105-test.c | 2 -
25
default-configs/arm-softmmu.mak | 1 +
26
9 files changed, 426 insertions(+), 2 deletions(-)
27
create mode 100644 include/hw/misc/pca9552.h
28
create mode 100644 include/hw/misc/pca9552_regs.h
29
create mode 100644 hw/misc/pca9552.c
30
create mode 100644 tests/pca9552-test.c
31
32
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/misc/Makefile.objs
35
+++ b/hw/misc/Makefile.objs
36
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_SGA) += sga.o
37
common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
38
common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
39
common-obj-$(CONFIG_EDU) += edu.o
40
+common-obj-$(CONFIG_PCA9552) += pca9552.o
41
42
common-obj-y += unimp.o
43
common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o
44
diff --git a/tests/Makefile.include b/tests/Makefile.include
45
index XXXXXXX..XXXXXXX 100644
46
--- a/tests/Makefile.include
47
+++ b/tests/Makefile.include
48
@@ -XXX,XX +XXX,XX @@ check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
49
check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
50
51
check-qtest-arm-y = tests/tmp105-test$(EXESUF)
52
+check-qtest-arm-y += tests/pca9552-test$(EXESUF)
53
check-qtest-arm-y += tests/ds1338-test$(EXESUF)
54
check-qtest-arm-y += tests/m25p80-test$(EXESUF)
55
gcov-files-arm-y += hw/misc/tmp105.c
56
@@ -XXX,XX +XXX,XX @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
57
    tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y)
58
tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
59
tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
60
+tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y)
61
tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
62
tests/m25p80-test$(EXESUF): tests/m25p80-test.o
63
tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
64
diff --git a/include/hw/misc/pca9552.h b/include/hw/misc/pca9552.h
65
new file mode 100644
66
index XXXXXXX..XXXXXXX
67
--- /dev/null
68
+++ b/include/hw/misc/pca9552.h
69
@@ -XXX,XX +XXX,XX @@
70
+/*
71
+ * PCA9552 I2C LED blinker
72
+ *
73
+ * Copyright (c) 2017-2018, IBM Corporation.
74
+ *
75
+ * This work is licensed under the terms of the GNU GPL, version 2 or
76
+ * later. See the COPYING file in the top-level directory.
77
+ */
78
+#ifndef PCA9552_H
79
+#define PCA9552_H
80
+
81
+#include "hw/i2c/i2c.h"
82
+
83
+#define TYPE_PCA9552 "pca9552"
84
+#define PCA9552(obj) OBJECT_CHECK(PCA9552State, (obj), TYPE_PCA9552)
85
+
86
+#define PCA9552_NR_REGS 10
87
+
88
+typedef struct PCA9552State {
89
+ /*< private >*/
90
+ I2CSlave i2c;
91
+ /*< public >*/
92
+
93
+ uint8_t len;
94
+ uint8_t pointer;
95
+
96
+ uint8_t regs[PCA9552_NR_REGS];
97
+ uint8_t max_reg;
98
+ uint8_t nr_leds;
99
+} PCA9552State;
100
+
101
+#endif
102
diff --git a/include/hw/misc/pca9552_regs.h b/include/hw/misc/pca9552_regs.h
103
new file mode 100644
104
index XXXXXXX..XXXXXXX
105
--- /dev/null
106
+++ b/include/hw/misc/pca9552_regs.h
107
@@ -XXX,XX +XXX,XX @@
108
+/*
109
+ * PCA9552 I2C LED blinker registers
110
+ *
111
+ * Copyright (c) 2017-2018, IBM Corporation.
112
+ *
113
+ * This work is licensed under the terms of the GNU GPL, version 2 or
114
+ * later. See the COPYING file in the top-level directory.
115
+ */
116
+#ifndef PCA9552_REGS_H
117
+#define PCA9552_REGS_H
118
+
119
+/*
120
+ * Bits [0:3] are used to address a specific register.
121
+ */
122
+#define PCA9552_INPUT0 0 /* read only input register 0 */
123
+#define PCA9552_INPUT1 1 /* read only input register 1 */
124
+#define PCA9552_PSC0 2 /* read/write frequency prescaler 0 */
125
+#define PCA9552_PWM0 3 /* read/write PWM register 0 */
126
+#define PCA9552_PSC1 4 /* read/write frequency prescaler 1 */
127
+#define PCA9552_PWM1 5 /* read/write PWM register 1 */
128
+#define PCA9552_LS0 6 /* read/write LED0 to LED3 selector */
129
+#define PCA9552_LS1 7 /* read/write LED4 to LED7 selector */
130
+#define PCA9552_LS2 8 /* read/write LED8 to LED11 selector */
131
+#define PCA9552_LS3 9 /* read/write LED12 to LED15 selector */
132
+
133
+/*
134
+ * Bit [4] is used to activate the Auto-Increment option of the
135
+ * register address
136
+ */
137
+#define PCA9552_AUTOINC (1 << 4)
138
+
139
+#endif
140
diff --git a/tests/libqos/i2c.h b/tests/libqos/i2c.h
141
index XXXXXXX..XXXXXXX 100644
142
--- a/tests/libqos/i2c.h
143
+++ b/tests/libqos/i2c.h
144
@@ -XXX,XX +XXX,XX @@ struct I2CAdapter {
145
QTestState *qts;
146
};
147
148
+#define OMAP2_I2C_1_BASE 0x48070000
149
+
150
void i2c_send(I2CAdapter *i2c, uint8_t addr,
151
const uint8_t *buf, uint16_t len);
152
void i2c_recv(I2CAdapter *i2c, uint8_t addr,
153
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
154
new file mode 100644
155
index XXXXXXX..XXXXXXX
156
--- /dev/null
157
+++ b/hw/misc/pca9552.c
158
@@ -XXX,XX +XXX,XX @@
159
+/*
160
+ * PCA9552 I2C LED blinker
161
+ *
162
+ * https://www.nxp.com/docs/en/application-note/AN264.pdf
163
+ *
164
+ * Copyright (c) 2017-2018, IBM Corporation.
165
+ *
166
+ * This work is licensed under the terms of the GNU GPL, version 2 or
167
+ * later. See the COPYING file in the top-level directory.
168
+ */
169
+
170
+#include "qemu/osdep.h"
171
+#include "qemu/log.h"
172
+#include "hw/hw.h"
173
+#include "hw/misc/pca9552.h"
174
+#include "hw/misc/pca9552_regs.h"
175
+
176
+#define PCA9552_LED_ON 0x0
177
+#define PCA9552_LED_OFF 0x1
178
+#define PCA9552_LED_PWM0 0x2
179
+#define PCA9552_LED_PWM1 0x3
180
+
181
+static uint8_t pca9552_pin_get_config(PCA9552State *s, int pin)
182
+{
183
+ uint8_t reg = PCA9552_LS0 + (pin / 4);
184
+ uint8_t shift = (pin % 4) << 1;
185
+
186
+ return extract32(s->regs[reg], shift, 2);
187
+}
188
+
189
+static void pca9552_update_pin_input(PCA9552State *s)
190
+{
191
+ int i;
192
+
193
+ for (i = 0; i < s->nr_leds; i++) {
194
+ uint8_t input_reg = PCA9552_INPUT0 + (i / 8);
195
+ uint8_t input_shift = (i % 8);
196
+ uint8_t config = pca9552_pin_get_config(s, i);
197
+
198
+ switch (config) {
199
+ case PCA9552_LED_ON:
200
+ s->regs[input_reg] |= 1 << input_shift;
201
+ break;
202
+ case PCA9552_LED_OFF:
203
+ s->regs[input_reg] &= ~(1 << input_shift);
204
+ break;
205
+ case PCA9552_LED_PWM0:
206
+ case PCA9552_LED_PWM1:
207
+ /* TODO */
208
+ default:
209
+ break;
210
+ }
211
+ }
212
+}
213
+
214
+static uint8_t pca9552_read(PCA9552State *s, uint8_t reg)
215
+{
216
+ switch (reg) {
217
+ case PCA9552_INPUT0:
218
+ case PCA9552_INPUT1:
219
+ case PCA9552_PSC0:
220
+ case PCA9552_PWM0:
221
+ case PCA9552_PSC1:
222
+ case PCA9552_PWM1:
223
+ case PCA9552_LS0:
224
+ case PCA9552_LS1:
225
+ case PCA9552_LS2:
226
+ case PCA9552_LS3:
227
+ return s->regs[reg];
228
+ default:
229
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected read to register %d\n",
230
+ __func__, reg);
231
+ return 0xFF;
232
+ }
233
+}
234
+
235
+static void pca9552_write(PCA9552State *s, uint8_t reg, uint8_t data)
236
+{
237
+ switch (reg) {
238
+ case PCA9552_PSC0:
239
+ case PCA9552_PWM0:
240
+ case PCA9552_PSC1:
241
+ case PCA9552_PWM1:
242
+ s->regs[reg] = data;
243
+ break;
244
+
245
+ case PCA9552_LS0:
246
+ case PCA9552_LS1:
247
+ case PCA9552_LS2:
248
+ case PCA9552_LS3:
249
+ s->regs[reg] = data;
250
+ pca9552_update_pin_input(s);
251
+ break;
252
+
253
+ case PCA9552_INPUT0:
254
+ case PCA9552_INPUT1:
255
+ default:
256
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected write to register %d\n",
257
+ __func__, reg);
258
+ }
259
+}
260
+
261
+/*
262
+ * When Auto-Increment is on, the register address is incremented
263
+ * after each byte is sent to or received by the device. The index
264
+ * rollovers to 0 when the maximum register address is reached.
265
+ */
266
+static void pca9552_autoinc(PCA9552State *s)
267
+{
268
+ if (s->pointer != 0xFF && s->pointer & PCA9552_AUTOINC) {
269
+ uint8_t reg = s->pointer & 0xf;
270
+
271
+ reg = (reg + 1) % (s->max_reg + 1);
272
+ s->pointer = reg | PCA9552_AUTOINC;
273
+ }
274
+}
275
+
276
+static int pca9552_recv(I2CSlave *i2c)
277
+{
278
+ PCA9552State *s = PCA9552(i2c);
279
+ uint8_t ret;
280
+
281
+ ret = pca9552_read(s, s->pointer & 0xf);
282
+
283
+ /*
284
+ * From the Specs:
285
+ *
286
+ * Important Note: When a Read sequence is initiated and the
287
+ * AI bit is set to Logic Level 1, the Read Sequence MUST
288
+ * start by a register different from 0.
289
+ *
290
+ * I don't know what should be done in this case, so throw an
291
+ * error.
292
+ */
293
+ if (s->pointer == PCA9552_AUTOINC) {
294
+ qemu_log_mask(LOG_GUEST_ERROR,
295
+ "%s: Autoincrement read starting with register 0\n",
296
+ __func__);
297
+ }
298
+
299
+ pca9552_autoinc(s);
300
+
301
+ return ret;
302
+}
303
+
304
+static int pca9552_send(I2CSlave *i2c, uint8_t data)
305
+{
306
+ PCA9552State *s = PCA9552(i2c);
307
+
308
+ /* First byte sent by is the register address */
309
+ if (s->len == 0) {
310
+ s->pointer = data;
311
+ s->len++;
312
+ } else {
313
+ pca9552_write(s, s->pointer & 0xf, data);
314
+
315
+ pca9552_autoinc(s);
316
+ }
317
+
318
+ return 0;
319
+}
320
+
321
+static int pca9552_event(I2CSlave *i2c, enum i2c_event event)
322
+{
323
+ PCA9552State *s = PCA9552(i2c);
324
+
325
+ s->len = 0;
326
+ return 0;
327
+}
328
+
329
+static const VMStateDescription pca9552_vmstate = {
330
+ .name = "PCA9552",
331
+ .version_id = 0,
332
+ .minimum_version_id = 0,
333
+ .fields = (VMStateField[]) {
334
+ VMSTATE_UINT8(len, PCA9552State),
335
+ VMSTATE_UINT8(pointer, PCA9552State),
336
+ VMSTATE_UINT8_ARRAY(regs, PCA9552State, PCA9552_NR_REGS),
337
+ VMSTATE_I2C_SLAVE(i2c, PCA9552State),
338
+ VMSTATE_END_OF_LIST()
339
+ }
340
+};
341
+
342
+static void pca9552_reset(DeviceState *dev)
343
+{
344
+ PCA9552State *s = PCA9552(dev);
345
+
346
+ s->regs[PCA9552_PSC0] = 0xFF;
347
+ s->regs[PCA9552_PWM0] = 0x80;
348
+ s->regs[PCA9552_PSC1] = 0xFF;
349
+ s->regs[PCA9552_PWM1] = 0x80;
350
+ s->regs[PCA9552_LS0] = 0x55; /* all OFF */
351
+ s->regs[PCA9552_LS1] = 0x55;
352
+ s->regs[PCA9552_LS2] = 0x55;
353
+ s->regs[PCA9552_LS3] = 0x55;
354
+
355
+ pca9552_update_pin_input(s);
356
+
357
+ s->pointer = 0xFF;
358
+ s->len = 0;
359
+}
360
+
361
+static void pca9552_initfn(Object *obj)
362
+{
363
+ PCA9552State *s = PCA9552(obj);
364
+
365
+ /* If support for the other PCA955X devices are implemented, these
366
+ * constant values might be part of class structure describing the
367
+ * PCA955X device
368
+ */
369
+ s->max_reg = PCA9552_LS3;
370
+ s->nr_leds = 16;
371
+}
372
+
373
+static void pca9552_class_init(ObjectClass *klass, void *data)
374
+{
375
+ DeviceClass *dc = DEVICE_CLASS(klass);
376
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
377
+
378
+ k->event = pca9552_event;
379
+ k->recv = pca9552_recv;
380
+ k->send = pca9552_send;
381
+ dc->reset = pca9552_reset;
382
+ dc->vmsd = &pca9552_vmstate;
383
+}
384
+
385
+static const TypeInfo pca9552_info = {
386
+ .name = TYPE_PCA9552,
387
+ .parent = TYPE_I2C_SLAVE,
388
+ .instance_init = pca9552_initfn,
389
+ .instance_size = sizeof(PCA9552State),
390
+ .class_init = pca9552_class_init,
391
+};
392
+
393
+static void pca9552_register_types(void)
394
+{
395
+ type_register_static(&pca9552_info);
396
+}
397
+
398
+type_init(pca9552_register_types)
399
diff --git a/tests/pca9552-test.c b/tests/pca9552-test.c
400
new file mode 100644
401
index XXXXXXX..XXXXXXX
402
--- /dev/null
403
+++ b/tests/pca9552-test.c
404
@@ -XXX,XX +XXX,XX @@
405
+/*
406
+ * QTest testcase for the PCA9552 LED blinker
407
+ *
408
+ * Copyright (c) 2017-2018, IBM Corporation.
409
+ *
410
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
411
+ * See the COPYING file in the top-level directory.
412
+ */
413
+
414
+#include "qemu/osdep.h"
415
+
416
+#include "libqtest.h"
417
+#include "libqos/i2c.h"
418
+#include "hw/misc/pca9552_regs.h"
419
+
420
+#define PCA9552_TEST_ID "pca9552-test"
421
+#define PCA9552_TEST_ADDR 0x60
422
+
423
+static I2CAdapter *i2c;
424
+
425
+static uint8_t pca9552_get8(I2CAdapter *i2c, uint8_t addr, uint8_t reg)
426
+{
427
+ uint8_t resp[1];
428
+ i2c_send(i2c, addr, &reg, 1);
429
+ i2c_recv(i2c, addr, resp, 1);
430
+ return resp[0];
431
+}
432
+
433
+static void pca9552_set8(I2CAdapter *i2c, uint8_t addr, uint8_t reg,
434
+ uint8_t value)
435
+{
436
+ uint8_t cmd[2];
437
+ uint8_t resp[1];
438
+
439
+ cmd[0] = reg;
440
+ cmd[1] = value;
441
+ i2c_send(i2c, addr, cmd, 2);
442
+ i2c_recv(i2c, addr, resp, 1);
443
+ g_assert_cmphex(resp[0], ==, cmd[1]);
444
+}
445
+
446
+static void receive_autoinc(void)
447
+{
448
+ uint8_t resp;
449
+ uint8_t reg = PCA9552_LS0 | PCA9552_AUTOINC;
450
+
451
+ i2c_send(i2c, PCA9552_TEST_ADDR, &reg, 1);
452
+
453
+ /* PCA9552_LS0 */
454
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
455
+ g_assert_cmphex(resp, ==, 0x54);
456
+
457
+ /* PCA9552_LS1 */
458
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
459
+ g_assert_cmphex(resp, ==, 0x55);
460
+
461
+ /* PCA9552_LS2 */
462
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
463
+ g_assert_cmphex(resp, ==, 0x55);
464
+
465
+ /* PCA9552_LS3 */
466
+ i2c_recv(i2c, PCA9552_TEST_ADDR, &resp, 1);
467
+ g_assert_cmphex(resp, ==, 0x54);
468
+}
469
+
470
+static void send_and_receive(void)
471
+{
472
+ uint8_t value;
473
+
474
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_LS0);
475
+ g_assert_cmphex(value, ==, 0x55);
476
+
477
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_INPUT0);
478
+ g_assert_cmphex(value, ==, 0x0);
479
+
480
+ /* Switch on LED 0 */
481
+ pca9552_set8(i2c, PCA9552_TEST_ADDR, PCA9552_LS0, 0x54);
482
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_LS0);
483
+ g_assert_cmphex(value, ==, 0x54);
484
+
485
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_INPUT0);
486
+ g_assert_cmphex(value, ==, 0x01);
487
+
488
+ /* Switch on LED 12 */
489
+ pca9552_set8(i2c, PCA9552_TEST_ADDR, PCA9552_LS3, 0x54);
490
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_LS3);
491
+ g_assert_cmphex(value, ==, 0x54);
492
+
493
+ value = pca9552_get8(i2c, PCA9552_TEST_ADDR, PCA9552_INPUT1);
494
+ g_assert_cmphex(value, ==, 0x10);
495
+}
496
+
497
+int main(int argc, char **argv)
498
+{
499
+ QTestState *s = NULL;
500
+ int ret;
501
+
502
+ g_test_init(&argc, &argv, NULL);
503
+
504
+ s = qtest_start("-machine n800 "
505
+ "-device pca9552,bus=i2c-bus.0,id=" PCA9552_TEST_ID
506
+ ",address=0x60");
507
+ i2c = omap_i2c_create(s, OMAP2_I2C_1_BASE);
508
+
509
+ qtest_add_func("/pca9552/tx-rx", send_and_receive);
510
+ qtest_add_func("/pca9552/rx-autoinc", receive_autoinc);
511
+
512
+ ret = g_test_run();
513
+
514
+ if (s) {
515
+ qtest_quit(s);
516
+ }
517
+ g_free(i2c);
518
+
519
+ return ret;
520
+}
521
diff --git a/tests/tmp105-test.c b/tests/tmp105-test.c
522
index XXXXXXX..XXXXXXX 100644
523
--- a/tests/tmp105-test.c
524
+++ b/tests/tmp105-test.c
525
@@ -XXX,XX +XXX,XX @@
526
#include "qapi/qmp/qdict.h"
527
#include "hw/misc/tmp105_regs.h"
528
529
-#define OMAP2_I2C_1_BASE 0x48070000
530
-
531
#define TMP105_TEST_ID "tmp105-test"
532
#define TMP105_TEST_ADDR 0x49
533
534
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
535
index XXXXXXX..XXXXXXX 100644
536
--- a/default-configs/arm-softmmu.mak
537
+++ b/default-configs/arm-softmmu.mak
538
@@ -XXX,XX +XXX,XX @@ CONFIG_TSC2005=y
539
CONFIG_LM832X=y
540
CONFIG_TMP105=y
541
CONFIG_TMP421=y
542
+CONFIG_PCA9552=y
543
CONFIG_STELLARIS=y
544
CONFIG_STELLARIS_INPUT=y
545
CONFIG_STELLARIS_ENET=y
546
--
547
2.17.1
548
549
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/31] aspeed: add the pc9552 chips to the witherspoon machine
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The pca9552 LED blinkers on the Witherspoon machine are used for leds
4
but also as GPIOs to control fans and GPUs.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180530064049.27976-8-clg@kaod.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/aspeed.c | 4 ++++
13
1 file changed, 4 insertions(+)
14
15
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/aspeed.c
18
+++ b/hw/arm/aspeed.c
19
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
20
AspeedSoCState *soc = &bmc->soc;
21
uint8_t *eeprom_buf = g_malloc0(8 * 1024);
22
23
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60);
24
+
25
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c);
26
i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c);
27
28
@@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc)
29
30
smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51,
31
eeprom_buf);
32
+ i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "pca9552",
33
+ 0x60);
34
}
35
36
static void witherspoon_bmc_init(MachineState *machine)
37
--
38
2.17.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/31] ftgmac100: compute maximum frame size depending on the protocol
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The maximum frame size includes the CRC and depends if a VLAN tag is
4
inserted or not. Adjust the frame size limit in the transmit handler
5
using on the FTGMAC100State buffer size and in the receive handler use
6
the packet protocol.
7
8
Signed-off-by: Cédric Le Goater <clg@kaod.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20180530061711.23673-2-clg@kaod.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/net/ftgmac100.h | 7 ++++++-
14
hw/net/ftgmac100.c | 23 ++++++++++++-----------
15
2 files changed, 18 insertions(+), 12 deletions(-)
16
17
diff --git a/include/hw/net/ftgmac100.h b/include/hw/net/ftgmac100.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/net/ftgmac100.h
20
+++ b/include/hw/net/ftgmac100.h
21
@@ -XXX,XX +XXX,XX @@
22
#include "hw/sysbus.h"
23
#include "net/net.h"
24
25
+/*
26
+ * Max frame size for the receiving buffer
27
+ */
28
+#define FTGMAC100_MAX_FRAME_SIZE 9220
29
+
30
typedef struct FTGMAC100State {
31
/*< private >*/
32
SysBusDevice parent_obj;
33
@@ -XXX,XX +XXX,XX @@ typedef struct FTGMAC100State {
34
qemu_irq irq;
35
MemoryRegion iomem;
36
37
- uint8_t *frame;
38
+ uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];
39
40
uint32_t irq_state;
41
uint32_t isr;
42
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/net/ftgmac100.c
45
+++ b/hw/net/ftgmac100.c
46
@@ -XXX,XX +XXX,XX @@ typedef struct {
47
/*
48
* Max frame size for the receiving buffer
49
*/
50
-#define FTGMAC100_MAX_FRAME_SIZE 10240
51
+#define FTGMAC100_MAX_FRAME_SIZE 9220
52
53
/* Limits depending on the type of the frame
54
*
55
* 9216 for Jumbo frames (+ 4 for VLAN)
56
* 1518 for other frames (+ 4 for VLAN)
57
*/
58
-static int ftgmac100_max_frame_size(FTGMAC100State *s)
59
+static int ftgmac100_max_frame_size(FTGMAC100State *s, uint16_t proto)
60
{
61
- return (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518) + 4;
62
+ int max = (s->maccr & FTGMAC100_MACCR_JUMBO_LF ? 9216 : 1518);
63
+
64
+ return max + (proto == ETH_P_VLAN ? 4 : 0);
65
}
66
67
static void ftgmac100_update_irq(FTGMAC100State *s)
68
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
69
uint8_t *ptr = s->frame;
70
uint32_t addr = tx_descriptor;
71
uint32_t flags = 0;
72
- int max_frame_size = ftgmac100_max_frame_size(s);
73
74
while (1) {
75
FTGMAC100Desc bd;
76
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
77
flags = bd.des1;
78
}
79
80
- len = bd.des0 & 0x3FFF;
81
- if (frame_size + len > max_frame_size) {
82
+ len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
83
+ if (frame_size + len > sizeof(s->frame)) {
84
qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
85
__func__, len);
86
- len = max_frame_size - frame_size;
87
+ s->isr |= FTGMAC100_INT_XPKT_LOST;
88
+ len = sizeof(s->frame) - frame_size;
89
}
90
91
if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
92
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
93
uint32_t buf_len;
94
size_t size = len;
95
uint32_t first = FTGMAC100_RXDES0_FRS;
96
- int max_frame_size = ftgmac100_max_frame_size(s);
97
+ uint16_t proto = be16_to_cpu(PKT_GET_ETH_HDR(buf)->h_proto);
98
+ int max_frame_size = ftgmac100_max_frame_size(s, proto);
99
100
if ((s->maccr & (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN))
101
!= (FTGMAC100_MACCR_RXDMA_EN | FTGMAC100_MACCR_RXMAC_EN)) {
102
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
103
104
/* Huge frames are truncated. */
105
if (size > max_frame_size) {
106
- size = max_frame_size;
107
qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %zd bytes\n",
108
__func__, size);
109
+ size = max_frame_size;
110
flags |= FTGMAC100_RXDES0_FTL;
111
}
112
113
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_realize(DeviceState *dev, Error **errp)
114
object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
115
s);
116
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
117
-
118
- s->frame = g_malloc(FTGMAC100_MAX_FRAME_SIZE);
119
}
120
121
static const VMStateDescription vmstate_ftgmac100 = {
122
--
123
2.17.1
124
125
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/31] ftgmac100: add IEEE 802.1Q VLAN support
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
The ftgmac100 NIC supports VLAN tag insertion and the MAC engine also
4
has a control to remove VLAN tags from received packets.
5
6
The VLAN control bits and VLAN tag information are contained in the
7
second word of the transmit and receive descriptors. The Insert VLAN
8
bit and the VLAN Tag available bit are only valid in the first segment
9
of the packet.
10
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180530061711.23673-3-clg@kaod.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/net/ftgmac100.c | 31 ++++++++++++++++++++++++++++++-
17
1 file changed, 30 insertions(+), 1 deletion(-)
18
19
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/ftgmac100.c
22
+++ b/hw/net/ftgmac100.c
23
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
24
break;
25
}
26
27
+ /* Check for VLAN */
28
+ if (bd.des0 & FTGMAC100_TXDES0_FTS &&
29
+ bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
30
+ be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
31
+ if (frame_size + len + 4 > sizeof(s->frame)) {
32
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
33
+ __func__, len);
34
+ s->isr |= FTGMAC100_INT_XPKT_LOST;
35
+ len = sizeof(s->frame) - frame_size - 4;
36
+ }
37
+ memmove(ptr + 16, ptr + 12, len - 12);
38
+ stw_be_p(ptr + 12, ETH_P_VLAN);
39
+ stw_be_p(ptr + 14, bd.des1);
40
+ len += 4;
41
+ }
42
+
43
ptr += len;
44
frame_size += len;
45
if (bd.des0 & FTGMAC100_TXDES0_LTS) {
46
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
47
buf_len += size - 4;
48
}
49
buf_addr = bd.des3;
50
- dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
51
+ if (first && proto == ETH_P_VLAN && buf_len >= 18) {
52
+ bd.des1 = lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVAIL;
53
+
54
+ if (s->maccr & FTGMAC100_MACCR_RM_VLAN) {
55
+ dma_memory_write(&address_space_memory, buf_addr, buf, 12);
56
+ dma_memory_write(&address_space_memory, buf_addr + 12, buf + 16,
57
+ buf_len - 16);
58
+ } else {
59
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
60
+ }
61
+ } else {
62
+ bd.des1 = 0;
63
+ dma_memory_write(&address_space_memory, buf_addr, buf, buf_len);
64
+ }
65
buf += buf_len;
66
if (size < 4) {
67
dma_memory_write(&address_space_memory, buf_addr + buf_len,
68
--
69
2.17.1
70
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/31] ftgmac100: fix multicast hash routine
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
Based on the multicast hash calculation of the FTGMAC100 Linux driver.
4
5
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180530061711.23673-4-clg@kaod.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/net/ftgmac100.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/net/ftgmac100.c
16
+++ b/hw/net/ftgmac100.c
17
@@ -XXX,XX +XXX,XX @@ static int ftgmac100_filter(FTGMAC100State *s, const uint8_t *buf, size_t len)
18
return 0;
19
}
20
21
- /* TODO: this does not seem to work for ftgmac100 */
22
- mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
23
+ mcast_idx = net_crc32_le(buf, ETH_ALEN);
24
+ mcast_idx = (~(mcast_idx >> 2)) & 0x3f;
25
if (!(s->math[mcast_idx / 32] & (1 << (mcast_idx % 32)))) {
26
return 0;
27
}
28
--
29
2.17.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/31] ftgmac100: remove check on runt messages
Deleted patch
1
From: Cédric Le Goater <clg@kaod.org>
2
1
3
This is a ethernet wire limitation not needed in emulation. It breaks
4
U-Boot n/w stack also.
5
6
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Message-id: 20180530061711.23673-5-clg@kaod.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/net/ftgmac100.c | 6 ------
12
1 file changed, 6 deletions(-)
13
14
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/net/ftgmac100.c
17
+++ b/hw/net/ftgmac100.c
18
@@ -XXX,XX +XXX,XX @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
19
return size;
20
}
21
22
- if (size < 64 && !(s->maccr & FTGMAC100_MACCR_RX_RUNT)) {
23
- qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped runt frame of %zd bytes\n",
24
- __func__, size);
25
- return size;
26
- }
27
-
28
if (!ftgmac100_filter(s, buf, size)) {
29
return size;
30
}
31
--
32
2.17.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/31] hw/arm: Remove the deprecated xlnx-ep108 machine
Deleted patch
1
From: Thomas Huth <thuth@redhat.com>
2
1
3
It has been marked as deprecated since QEMU v2.11, so it is time to
4
remove this now. The xlnx-zcu102 machine is very much the same and
5
can be used as a replacement instead.
6
7
Signed-off-by: Thomas Huth <thuth@redhat.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/xlnx-zcu102.c | 62 ++------------------------------------------
12
qemu-doc.texi | 5 ----
13
2 files changed, 2 insertions(+), 65 deletions(-)
14
15
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-zcu102.c
18
+++ b/hw/arm/xlnx-zcu102.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct XlnxZCU102 {
20
#define ZCU102_MACHINE(obj) \
21
OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE)
22
23
-#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108")
24
-#define EP108_MACHINE(obj) \
25
- OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE)
26
-
27
static struct arm_boot_info xlnx_zcu102_binfo;
28
29
static bool zcu102_get_secure(Object *obj, Error **errp)
30
@@ -XXX,XX +XXX,XX @@ static void zcu102_set_virt(Object *obj, bool value, Error **errp)
31
s->virt = value;
32
}
33
34
-static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
35
+static void xlnx_zcu102_init(MachineState *machine)
36
{
37
+ XlnxZCU102 *s = ZCU102_MACHINE(machine);
38
int i;
39
uint64_t ram_size = machine->ram_size;
40
41
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
42
arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
43
}
44
45
-static void xlnx_ep108_init(MachineState *machine)
46
-{
47
- XlnxZCU102 *s = EP108_MACHINE(machine);
48
-
49
- if (!qtest_enabled()) {
50
- info_report("The Xilinx EP108 machine is deprecated, please use the "
51
- "ZCU102 machine (which has the same features) instead.");
52
- }
53
-
54
- xlnx_zynqmp_init(s, machine);
55
-}
56
-
57
-static void xlnx_ep108_machine_instance_init(Object *obj)
58
-{
59
- XlnxZCU102 *s = EP108_MACHINE(obj);
60
-
61
- /* EP108, we don't support setting secure or virt */
62
- s->secure = false;
63
- s->virt = false;
64
-}
65
-
66
-static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data)
67
-{
68
- MachineClass *mc = MACHINE_CLASS(oc);
69
-
70
- mc->desc = "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-zcu102)";
71
- mc->init = xlnx_ep108_init;
72
- mc->block_default_type = IF_IDE;
73
- mc->units_per_default_bus = 1;
74
- mc->ignore_memory_transaction_failures = true;
75
- mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
76
- mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
77
-}
78
-
79
-static const TypeInfo xlnx_ep108_machine_init_typeinfo = {
80
- .name = MACHINE_TYPE_NAME("xlnx-ep108"),
81
- .parent = TYPE_MACHINE,
82
- .class_init = xlnx_ep108_machine_class_init,
83
- .instance_init = xlnx_ep108_machine_instance_init,
84
- .instance_size = sizeof(XlnxZCU102),
85
-};
86
-
87
-static void xlnx_ep108_machine_init_register_types(void)
88
-{
89
- type_register_static(&xlnx_ep108_machine_init_typeinfo);
90
-}
91
-
92
-static void xlnx_zcu102_init(MachineState *machine)
93
-{
94
- XlnxZCU102 *s = ZCU102_MACHINE(machine);
95
-
96
- xlnx_zynqmp_init(s, machine);
97
-}
98
-
99
static void xlnx_zcu102_machine_instance_init(Object *obj)
100
{
101
XlnxZCU102 *s = ZCU102_MACHINE(obj);
102
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_init_register_types(void)
103
}
104
105
type_init(xlnx_zcu102_machine_init_register_types)
106
-type_init(xlnx_ep108_machine_init_register_types)
107
diff --git a/qemu-doc.texi b/qemu-doc.texi
108
index XXXXXXX..XXXXXXX 100644
109
--- a/qemu-doc.texi
110
+++ b/qemu-doc.texi
111
@@ -XXX,XX +XXX,XX @@ support page sizes < 4096 any longer.
112
113
@section System emulator machines
114
115
-@subsection Xilinx EP108 (since 2.11.0)
116
-
117
-The ``xlnx-ep108'' machine has been replaced by the ``xlnx-zcu102'' machine.
118
-The ``xlnx-zcu102'' machine has the same features and capabilites in QEMU.
119
-
120
@section Block device options
121
122
@subsection "backing": "" (since 2.12.0)
123
--
124
2.17.1
125
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/31] hw/i2c: Add trace events
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606191801.6331-1-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
Makefile.objs | 1 +
9
hw/i2c/core.c | 25 ++++++++++++++++++-------
10
hw/i2c/trace-events | 7 +++++++
11
3 files changed, 26 insertions(+), 7 deletions(-)
12
create mode 100644 hw/i2c/trace-events
13
14
diff --git a/Makefile.objs b/Makefile.objs
15
index XXXXXXX..XXXXXXX 100644
16
--- a/Makefile.objs
17
+++ b/Makefile.objs
18
@@ -XXX,XX +XXX,XX @@ trace-events-subdirs += hw/char
19
trace-events-subdirs += hw/display
20
trace-events-subdirs += hw/dma
21
trace-events-subdirs += hw/hppa
22
+trace-events-subdirs += hw/i2c
23
trace-events-subdirs += hw/i386
24
trace-events-subdirs += hw/i386/xen
25
trace-events-subdirs += hw/ide
26
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/i2c/core.c
29
+++ b/hw/i2c/core.c
30
@@ -XXX,XX +XXX,XX @@
31
32
#include "qemu/osdep.h"
33
#include "hw/i2c/i2c.h"
34
+#include "trace.h"
35
36
#define I2C_BROADCAST 0x00
37
38
@@ -XXX,XX +XXX,XX @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
39
}
40
41
QLIST_FOREACH(node, &bus->current_devs, next) {
42
+ I2CSlave *s = node->elt;
43
int rv;
44
45
- sc = I2C_SLAVE_GET_CLASS(node->elt);
46
+ sc = I2C_SLAVE_GET_CLASS(s);
47
/* If the bus is already busy, assume this is a repeated
48
start condition. */
49
50
if (sc->event) {
51
- rv = sc->event(node->elt, recv ? I2C_START_RECV : I2C_START_SEND);
52
+ trace_i2c_event("start", s->address);
53
+ rv = sc->event(s, recv ? I2C_START_RECV : I2C_START_SEND);
54
if (rv && !bus->broadcast) {
55
if (bus_scanned) {
56
/* First call, terminate the transfer. */
57
@@ -XXX,XX +XXX,XX @@ void i2c_end_transfer(I2CBus *bus)
58
I2CNode *node, *next;
59
60
QLIST_FOREACH_SAFE(node, &bus->current_devs, next, next) {
61
- sc = I2C_SLAVE_GET_CLASS(node->elt);
62
+ I2CSlave *s = node->elt;
63
+ sc = I2C_SLAVE_GET_CLASS(s);
64
if (sc->event) {
65
- sc->event(node->elt, I2C_FINISH);
66
+ trace_i2c_event("finish", s->address);
67
+ sc->event(s, I2C_FINISH);
68
}
69
QLIST_REMOVE(node, next);
70
g_free(node);
71
@@ -XXX,XX +XXX,XX @@ void i2c_end_transfer(I2CBus *bus)
72
int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
73
{
74
I2CSlaveClass *sc;
75
+ I2CSlave *s;
76
I2CNode *node;
77
int ret = 0;
78
79
if (send) {
80
QLIST_FOREACH(node, &bus->current_devs, next) {
81
- sc = I2C_SLAVE_GET_CLASS(node->elt);
82
+ s = node->elt;
83
+ sc = I2C_SLAVE_GET_CLASS(s);
84
if (sc->send) {
85
- ret = ret || sc->send(node->elt, *data);
86
+ trace_i2c_send(s->address, *data);
87
+ ret = ret || sc->send(s, *data);
88
} else {
89
ret = -1;
90
}
91
@@ -XXX,XX +XXX,XX @@ int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
92
93
sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(&bus->current_devs)->elt);
94
if (sc->recv) {
95
- ret = sc->recv(QLIST_FIRST(&bus->current_devs)->elt);
96
+ s = QLIST_FIRST(&bus->current_devs)->elt;
97
+ ret = sc->recv(s);
98
+ trace_i2c_recv(s->address, ret);
99
if (ret < 0) {
100
return ret;
101
} else {
102
@@ -XXX,XX +XXX,XX @@ void i2c_nack(I2CBus *bus)
103
QLIST_FOREACH(node, &bus->current_devs, next) {
104
sc = I2C_SLAVE_GET_CLASS(node->elt);
105
if (sc->event) {
106
+ trace_i2c_event("nack", node->elt->address);
107
sc->event(node->elt, I2C_NACK);
108
}
109
}
110
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
111
new file mode 100644
112
index XXXXXXX..XXXXXXX
113
--- /dev/null
114
+++ b/hw/i2c/trace-events
115
@@ -XXX,XX +XXX,XX @@
116
+# See docs/devel/tracing.txt for syntax documentation.
117
+
118
+# hw/i2c/core.c
119
+
120
+i2c_event(const char *event, uint8_t address) "%s(addr:0x%02x)"
121
+i2c_send(uint8_t address, uint8_t data) "send(addr:0x%02x) data:0x%02x"
122
+i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
123
--
124
2.17.1
125
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/31] hw/sd/milkymist-memcard: Add trailing '\n' to qemu_log() call
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-2-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/sd/milkymist-memcard.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/milkymist-memcard.c
14
+++ b/hw/sd/milkymist-memcard.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t memcard_read(void *opaque, hwaddr addr,
16
r = s->response[s->response_read_ptr++];
17
if (s->response_read_ptr > s->response_len) {
18
qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
19
- "read more cmd bytes than available. Clipping.");
20
+ "read more cmd bytes than available: clipping\n");
21
s->response_read_ptr = 0;
22
}
23
}
24
--
25
2.17.1
26
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/31] hw/digic: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-3-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/char/digic-uart.c | 4 ++--
9
hw/timer/digic-timer.c | 4 ++--
10
2 files changed, 4 insertions(+), 4 deletions(-)
11
12
diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/char/digic-uart.c
15
+++ b/hw/char/digic-uart.c
16
@@ -XXX,XX +XXX,XX @@ static uint64_t digic_uart_read(void *opaque, hwaddr addr,
17
default:
18
qemu_log_mask(LOG_UNIMP,
19
"digic-uart: read access to unknown register 0x"
20
- TARGET_FMT_plx, addr << 2);
21
+ TARGET_FMT_plx "\n", addr << 2);
22
}
23
24
return ret;
25
@@ -XXX,XX +XXX,XX @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
26
default:
27
qemu_log_mask(LOG_UNIMP,
28
"digic-uart: write access to unknown register 0x"
29
- TARGET_FMT_plx, addr << 2);
30
+ TARGET_FMT_plx "\n", addr << 2);
31
}
32
}
33
34
diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/timer/digic-timer.c
37
+++ b/hw/timer/digic-timer.c
38
@@ -XXX,XX +XXX,XX @@ static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size)
39
default:
40
qemu_log_mask(LOG_UNIMP,
41
"digic-timer: read access to unknown register 0x"
42
- TARGET_FMT_plx, offset);
43
+ TARGET_FMT_plx "\n", offset);
44
}
45
46
return ret;
47
@@ -XXX,XX +XXX,XX @@ static void digic_timer_write(void *opaque, hwaddr offset,
48
default:
49
qemu_log_mask(LOG_UNIMP,
50
"digic-timer: read access to unknown register 0x"
51
- TARGET_FMT_plx, offset);
52
+ TARGET_FMT_plx "\n", offset);
53
}
54
}
55
56
--
57
2.17.1
58
59
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/31] xilinx-dp: Add trailing '\n' to qemu_log() call
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20180606152128.449-4-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/display/xlnx_dp.c | 4 +++-
9
1 file changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/display/xlnx_dp.c
14
+++ b/hw/display/xlnx_dp.c
15
@@ -XXX,XX +XXX,XX @@ static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
16
case AV_BUF_STC_SNAPSHOT1:
17
case AV_BUF_HCOUNT_VCOUNT_INT0:
18
case AV_BUF_HCOUNT_VCOUNT_INT1:
19
- qemu_log_mask(LOG_UNIMP, "avbufm: unimplmented");
20
+ qemu_log_mask(LOG_UNIMP, "avbufm: unimplemented register 0x%04"
21
+ PRIx64 "\n",
22
+ offset << 2);
23
break;
24
default:
25
s->avbufm_registers[offset] = value;
26
--
27
2.17.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/31] ppc/pnv: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Acked-by: David Gibson <david@gibson.dropbear.id.au>
5
Message-id: 20180606152128.449-5-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/ppc/pnv_core.c | 4 ++--
9
1 file changed, 2 insertions(+), 2 deletions(-)
10
11
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/ppc/pnv_core.c
14
+++ b/hw/ppc/pnv_core.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
16
val = 0x24f000000000000ull;
17
break;
18
default:
19
- qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx,
20
+ qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
21
addr);
22
}
23
24
@@ -XXX,XX +XXX,XX @@ static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr,
25
static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val,
26
unsigned int width)
27
{
28
- qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx,
29
+ qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
30
addr);
31
}
32
33
--
34
2.17.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/31] hw/core/register: Add trailing '\n' to qemu_log() call
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20180606152128.449-6-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/core/register.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/hw/core/register.c b/hw/core/register.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/core/register.c
14
+++ b/hw/core/register.c
15
@@ -XXX,XX +XXX,XX @@ void register_write(RegisterInfo *reg, uint64_t val, uint64_t we,
16
if (test) {
17
qemu_log_mask(LOG_UNIMP,
18
"%s:%s writing %#" PRIx64 " to unimplemented bits:" \
19
- " %#" PRIx64 "",
20
+ " %#" PRIx64 "\n",
21
prefix, reg->access->name, val, ac->unimp);
22
}
23
24
--
25
2.17.1
26
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/31] hw/mips/boston: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-7-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/mips/boston.c | 8 ++++----
9
1 file changed, 4 insertions(+), 4 deletions(-)
10
11
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/mips/boston.c
14
+++ b/hw/mips/boston.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
16
uint32_t gic_freq, val;
17
18
if (size != 4) {
19
- qemu_log_mask(LOG_UNIMP, "%uB platform register read", size);
20
+ qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
21
return 0;
22
}
23
24
@@ -XXX,XX +XXX,XX @@ static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
25
val |= PLAT_DDR_CFG_MHZ;
26
return val;
27
default:
28
- qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx,
29
+ qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
30
addr & 0xffff);
31
return 0;
32
}
33
@@ -XXX,XX +XXX,XX @@ static void boston_platreg_write(void *opaque, hwaddr addr,
34
uint64_t val, unsigned size)
35
{
36
if (size != 4) {
37
- qemu_log_mask(LOG_UNIMP, "%uB platform register write", size);
38
+ qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
39
return;
40
}
41
42
@@ -XXX,XX +XXX,XX @@ static void boston_platreg_write(void *opaque, hwaddr addr,
43
break;
44
default:
45
qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
46
- " = 0x%" PRIx64, addr & 0xffff, val);
47
+ " = 0x%" PRIx64 "\n", addr & 0xffff, val);
48
break;
49
}
50
}
51
--
52
2.17.1
53
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/31] stellaris: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-8-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/arm/stellaris.c | 11 ++++++-----
9
1 file changed, 6 insertions(+), 5 deletions(-)
10
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/stellaris.c
14
+++ b/hw/arm/stellaris.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t gptm_read(void *opaque, hwaddr offset,
16
return s->rtc;
17
}
18
qemu_log_mask(LOG_UNIMP,
19
- "GPTM: read of TAR but timer read not supported");
20
+ "GPTM: read of TAR but timer read not supported\n");
21
return 0;
22
case 0x4c: /* TBR */
23
qemu_log_mask(LOG_UNIMP,
24
- "GPTM: read of TBR but timer read not supported");
25
+ "GPTM: read of TBR but timer read not supported\n");
26
return 0;
27
default:
28
qemu_log_mask(LOG_GUEST_ERROR,
29
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset,
30
break;
31
case 0x20: /* MCR */
32
if (value & 1) {
33
- qemu_log_mask(LOG_UNIMP, "stellaris_i2c: Loopback not implemented");
34
+ qemu_log_mask(LOG_UNIMP,
35
+ "stellaris_i2c: Loopback not implemented\n");
36
}
37
if (value & 0x20) {
38
qemu_log_mask(LOG_UNIMP,
39
- "stellaris_i2c: Slave mode not implemented");
40
+ "stellaris_i2c: Slave mode not implemented\n");
41
}
42
s->mcr = value & 0x31;
43
break;
44
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_write(void *opaque, hwaddr offset,
45
s->sspri = value;
46
break;
47
case 0x28: /* PSSI */
48
- qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented");
49
+ qemu_log_mask(LOG_UNIMP, "ADC: sample initiate unimplemented\n");
50
break;
51
case 0x30: /* SAC */
52
s->sac = value;
53
--
54
2.17.1
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/31] target/arm: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-9-f4bug@amsat.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/helper.c | 4 ++--
9
1 file changed, 2 insertions(+), 2 deletions(-)
10
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
14
+++ b/target/arm/helper.c
15
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
16
case 4: /* unlinked address mismatch (reserved if AArch64) */
17
case 5: /* linked address mismatch (reserved if AArch64) */
18
qemu_log_mask(LOG_UNIMP,
19
- "arm: address mismatch breakpoint types not implemented");
20
+ "arm: address mismatch breakpoint types not implemented\n");
21
return;
22
case 0: /* unlinked address match */
23
case 1: /* linked address match */
24
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
25
case 8: /* unlinked VMID match (reserved if no EL2) */
26
case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
27
qemu_log_mask(LOG_UNIMP,
28
- "arm: unlinked context breakpoint types not implemented");
29
+ "arm: unlinked context breakpoint types not implemented\n");
30
return;
31
case 9: /* linked VMID match (reserved if no EL2) */
32
case 11: /* linked context ID and VMID match (reserved if no EL2) */
33
--
34
2.17.1
35
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/31] target/m68k: Add trailing '\n' to qemu_log() call
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
5
Message-id: 20180606152128.449-10-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/m68k/translate.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/translate.c
14
+++ b/target/m68k/translate.c
15
@@ -XXX,XX +XXX,XX @@ DISAS_INSN(undef)
16
/* ??? This is both instructions that are as yet unimplemented
17
for the 680x0 series, as well as those that are implemented
18
but actually illegal for CPU32 or pre-68020. */
19
- qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
20
+ qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
21
insn, s->insn_pc);
22
gen_exception(s, s->insn_pc, EXCP_UNSUPPORTED);
23
}
24
--
25
2.17.1
26
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/31] RISC-V: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Message-id: 20180606152128.449-11-f4bug@amsat.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
---
7
target/riscv/op_helper.c | 6 ++++--
8
1 file changed, 4 insertions(+), 2 deletions(-)
9
10
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/riscv/op_helper.c
13
+++ b/target/riscv/op_helper.c
14
@@ -XXX,XX +XXX,XX @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
15
if ((val_to_write & 3) == 0) {
16
env->stvec = val_to_write >> 2 << 2;
17
} else {
18
- qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported");
19
+ qemu_log_mask(LOG_UNIMP,
20
+ "CSR_STVEC: vectored traps not supported\n");
21
}
22
break;
23
case CSR_SCOUNTEREN:
24
@@ -XXX,XX +XXX,XX @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
25
if ((val_to_write & 3) == 0) {
26
env->mtvec = val_to_write >> 2 << 2;
27
} else {
28
- qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported");
29
+ qemu_log_mask(LOG_UNIMP,
30
+ "CSR_MTVEC: vectored traps not supported\n");
31
}
32
break;
33
case CSR_MCOUNTEREN:
34
--
35
2.17.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/31] target/xtensa: Add trailing '\n' to qemu_log() calls
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
5
Message-id: 20180606152128.449-12-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/xtensa/translate.c | 6 +++---
9
1 file changed, 3 insertions(+), 3 deletions(-)
10
11
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/xtensa/translate.c
14
+++ b/target/xtensa/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void translate_rur(DisasContext *dc, const uint32_t arg[],
16
if (uregnames[par[0]].name) {
17
tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]);
18
} else {
19
- qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", par[0]);
20
+ qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]);
21
}
22
}
23
}
24
@@ -XXX,XX +XXX,XX @@ static void translate_slli(DisasContext *dc, const uint32_t arg[],
25
{
26
if (gen_window_check2(dc, arg[0], arg[1])) {
27
if (arg[2] == 32) {
28
- qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined",
29
+ qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n",
30
arg[0], arg[1]);
31
}
32
tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f);
33
@@ -XXX,XX +XXX,XX @@ static void translate_wur(DisasContext *dc, const uint32_t arg[],
34
if (uregnames[par[0]].name) {
35
gen_wur(par[0], cpu_R[arg[0]]);
36
} else {
37
- qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", par[0]);
38
+ qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]);
39
}
40
}
41
}
42
--
43
2.17.1
44
45
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/31] sdcard: Update the Configuration Register (SCR) to Spec Version 1.10
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
The initial implementation is based on the Specs v1.10 (see a1bb27b1e98).
4
5
However the SCR is anouncing the card being v1.01.
6
7
The new chapters added in version 1.10 are:
8
9
4.3.10 Switch function command
10
11
Switch function command (CMD6) 1 is used to switch or expand
12
memory card functions. [...]
13
This is a new feature, introduced in SD physical Layer
14
Specification Version 1.10. Therefore, cards that are
15
compatible with earlier versions of the spec do not support
16
it. The host shall check the "SD_SPEC" field in the SCR
17
register to recognize what version of the spec the card
18
complies with before using CMD6. It is mandatory for SD
19
memory card of Ver1.10 to support CMD6.
20
21
4.3.11 High-Speed mode (25MB/sec interface speed)
22
23
Though the Rev 1.01 SD memory card supports up to 12.5MB/sec
24
interface speed, the speed of 25MB/sec is necessary to support
25
increasing performance needs of the host and because of memory
26
size which continues to grow.
27
To achieve 25MB/sec interface speed, clock rate is increased to
28
50MHz and CLK/CMD/DAT signal timing and circuit conditions are
29
reconsidered and changed from Physical Layer Specification
30
Version 1.01.
31
32
4.3.12 Command system (This chapter is newly added in version 1.10)
33
34
SD commands CMD34-37, CMD50, CMD57 are reserved for SD command
35
system expansion via the switch command.
36
[These commands] will be considered as illegal commands (as
37
defined in revision 1.01 of the SD physical layer specification).
38
39
The SWITCH_FUNCTION is implemented since the first commit, a1bb27b1e98.
40
41
The 25MB/sec High-Speed mode was already updated in d7ecb867529.
42
43
The current implementation does not implements CMD34-37, CMD50 and
44
CMD57, thus these commands already return ILLEGAL.
45
46
With this patch, the SCR register now matches the description of the header:
47
48
* SD Memory Card emulation as defined in the "SD Memory Card Physical
49
* layer specification, Version 1.10."
50
51
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
52
Message-id: 20180607180641.874-2-f4bug@amsat.org
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
56
hw/sd/sd.c | 4 ++--
57
1 file changed, 2 insertions(+), 2 deletions(-)
58
59
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/sd/sd.c
62
+++ b/hw/sd/sd.c
63
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
64
65
static void sd_set_scr(SDState *sd)
66
{
67
- sd->scr[0] = (0 << 4) /* SCR version 1.0 */
68
- | 0; /* Spec Versions 1.0 and 1.01 */
69
+ sd->scr[0] = (0 << 4) /* SCR structure version 1.0 */
70
+ | 1; /* Spec Version 1.10 */
71
sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
72
| 0b0101; /* 1-bit or 4-bit width bus modes */
73
sd->scr[2] = 0x00; /* Extended Security is not supported. */
74
--
75
2.17.1
76
77
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/31] sdcard: Allow commands valid in SPI mode
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
From the "Physical Layer Simplified Specification Version 1.10"
4
Chapter 7.3 "SPI Mode Transaction Packets"
5
Table 57: "Commands and arguments"
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20180607180641.874-3-f4bug@amsat.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/sd/sd.c | 14 --------------
14
1 file changed, 14 deletions(-)
15
16
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/sd/sd.c
19
+++ b/hw/sd/sd.c
20
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
21
return sd_illegal;
22
23
case 6:    /* CMD6: SWITCH_FUNCTION */
24
- if (sd->spi)
25
- goto bad_cmd;
26
switch (sd->mode) {
27
case sd_data_transfer_mode:
28
sd_function_switch(sd, req.arg);
29
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
30
31
/* Block write commands (Class 4) */
32
case 24:    /* CMD24: WRITE_SINGLE_BLOCK */
33
- if (sd->spi) {
34
- goto unimplemented_spi_cmd;
35
- }
36
switch (sd->state) {
37
case sd_transfer_state:
38
/* Writing in SPI mode not implemented. */
39
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
40
break;
41
42
case 25:    /* CMD25: WRITE_MULTIPLE_BLOCK */
43
- if (sd->spi) {
44
- goto unimplemented_spi_cmd;
45
- }
46
switch (sd->state) {
47
case sd_transfer_state:
48
/* Writing in SPI mode not implemented. */
49
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
50
break;
51
52
case 27:    /* CMD27: PROGRAM_CSD */
53
- if (sd->spi) {
54
- goto unimplemented_spi_cmd;
55
- }
56
switch (sd->state) {
57
case sd_transfer_state:
58
sd->state = sd_receivingdata_state;
59
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
60
61
/* Lock card commands (Class 7) */
62
case 42:    /* CMD42: LOCK_UNLOCK */
63
- if (sd->spi) {
64
- goto unimplemented_spi_cmd;
65
- }
66
switch (sd->state) {
67
case sd_transfer_state:
68
sd->state = sd_receivingdata_state;
69
--
70
2.17.1
71
72
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/31] sdcard: Add a 'spec_version' property, default to Spec v2.00
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
As of this commit, the Spec v1 is not working, and all controllers
4
expect the cards to be conformant to Spec v2.
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20180607180641.874-4-f4bug@amsat.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/sd/sd.h | 5 +++++
12
hw/sd/sd.c | 23 ++++++++++++++++++++---
13
2 files changed, 25 insertions(+), 3 deletions(-)
14
15
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/sd/sd.h
18
+++ b/include/hw/sd/sd.h
19
@@ -XXX,XX +XXX,XX @@
20
#define APP_CMD            (1 << 5)
21
#define AKE_SEQ_ERROR        (1 << 3)
22
23
+enum SDPhySpecificationVersion {
24
+ SD_PHY_SPECv1_10_VERS = 1,
25
+ SD_PHY_SPECv2_00_VERS = 2,
26
+};
27
+
28
typedef enum {
29
SD_VOLTAGE_0_4V = 400, /* currently not supported */
30
SD_VOLTAGE_1_8V = 1800,
31
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/sd/sd.c
34
+++ b/hw/sd/sd.c
35
@@ -XXX,XX +XXX,XX @@
36
/*
37
* SD Memory Card emulation as defined in the "SD Memory Card Physical
38
- * layer specification, Version 1.10."
39
+ * layer specification, Version 2.00."
40
*
41
* Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
42
* Copyright (c) 2007 CodeSourcery
43
+ * Copyright (c) 2018 Philippe Mathieu-Daudé <f4bug@amsat.org>
44
*
45
* Redistribution and use in source and binary forms, with or without
46
* modification, are permitted provided that the following conditions
47
@@ -XXX,XX +XXX,XX @@ struct SDState {
48
uint8_t sd_status[64];
49
50
/* Configurable properties */
51
+ uint8_t spec_version;
52
BlockBackend *blk;
53
bool spi;
54
55
@@ -XXX,XX +XXX,XX @@ static void sd_ocr_powerup(void *opaque)
56
57
static void sd_set_scr(SDState *sd)
58
{
59
- sd->scr[0] = (0 << 4) /* SCR structure version 1.0 */
60
- | 1; /* Spec Version 1.10 */
61
+ sd->scr[0] = 0 << 4; /* SCR structure version 1.0 */
62
+ if (sd->spec_version == SD_PHY_SPECv1_10_VERS) {
63
+ sd->scr[0] |= 1; /* Spec Version 1.10 */
64
+ } else {
65
+ sd->scr[0] |= 2; /* Spec Version 2.00 */
66
+ }
67
sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
68
| 0b0101; /* 1-bit or 4-bit width bus modes */
69
sd->scr[2] = 0x00; /* Extended Security is not supported. */
70
@@ -XXX,XX +XXX,XX @@ static void sd_realize(DeviceState *dev, Error **errp)
71
72
sd->proto_name = sd->spi ? "SPI" : "SD";
73
74
+ switch (sd->spec_version) {
75
+ case SD_PHY_SPECv1_10_VERS
76
+ ... SD_PHY_SPECv2_00_VERS:
77
+ break;
78
+ default:
79
+ error_setg(errp, "Invalid SD card Spec version: %u", sd->spec_version);
80
+ return;
81
+ }
82
+
83
if (sd->blk && blk_is_read_only(sd->blk)) {
84
error_setg(errp, "Cannot use read-only drive as SD card");
85
return;
86
@@ -XXX,XX +XXX,XX @@ static void sd_realize(DeviceState *dev, Error **errp)
87
}
88
89
static Property sd_properties[] = {
90
+ DEFINE_PROP_UINT8("spec_version", SDState,
91
+ spec_version, SD_PHY_SPECv2_00_VERS),
92
DEFINE_PROP_DRIVE("drive", SDState, blk),
93
/* We do not model the chip select pin, so allow the board to select
94
* whether card should be in SSI or MMC/SD mode. It is also up to the
95
--
96
2.17.1
97
98
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/31] sdcard: Disable SEND_IF_COND (CMD8) for Spec v1
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
CMD8 is "Reserved" in Spec v1.10.
4
5
Spec v2.00 introduces the SEND_IF_COND command:
6
7
6.4.1 Power Up
8
9
CMD8 is newly added in the Physical Layer Specification Version
10
2.00 to support multiple voltage ranges and used to check whether
11
the card supports supplied voltage. The version 2.00 or later host
12
shall issue CMD8 and verify voltage before card initialization.
13
The host that does not support CMD8 shall supply high voltage range.
14
15
Message-Id: 201204252110.20873.paul@codesourcery.com
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180607180641.874-5-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/sd/sd.c | 4 +++-
22
1 file changed, 3 insertions(+), 1 deletion(-)
23
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
27
+++ b/hw/sd/sd.c
28
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
29
break;
30
31
case 8:    /* CMD8: SEND_IF_COND */
32
- /* Physical Layer Specification Version 2.00 command */
33
+ if (sd->spec_version < SD_PHY_SPECv2_00_VERS) {
34
+ break;
35
+ }
36
if (sd->state != sd_idle_state) {
37
break;
38
}
39
--
40
2.17.1
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/31] sdcard: Reflect when the Spec v3 is supported in the Config Register (SCR)
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20180607180641.874-6-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/sd/sd.h | 1 +
9
hw/sd/sd.c | 7 +++++--
10
2 files changed, 6 insertions(+), 2 deletions(-)
11
12
diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/sd/sd.h
15
+++ b/include/hw/sd/sd.h
16
@@ -XXX,XX +XXX,XX @@
17
enum SDPhySpecificationVersion {
18
SD_PHY_SPECv1_10_VERS = 1,
19
SD_PHY_SPECv2_00_VERS = 2,
20
+ SD_PHY_SPECv3_01_VERS = 3,
21
};
22
23
typedef enum {
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
27
+++ b/hw/sd/sd.c
28
@@ -XXX,XX +XXX,XX @@ static void sd_set_scr(SDState *sd)
29
if (sd->spec_version == SD_PHY_SPECv1_10_VERS) {
30
sd->scr[0] |= 1; /* Spec Version 1.10 */
31
} else {
32
- sd->scr[0] |= 2; /* Spec Version 2.00 */
33
+ sd->scr[0] |= 2; /* Spec Version 2.00 or Version 3.0X */
34
}
35
sd->scr[1] = (2 << 4) /* SDSC Card (Security Version 1.01) */
36
| 0b0101; /* 1-bit or 4-bit width bus modes */
37
sd->scr[2] = 0x00; /* Extended Security is not supported. */
38
+ if (sd->spec_version >= SD_PHY_SPECv3_01_VERS) {
39
+ sd->scr[2] |= 1 << 7; /* Spec Version 3.0X */
40
+ }
41
sd->scr[3] = 0x00;
42
/* reserved for manufacturer usage */
43
sd->scr[4] = 0x00;
44
@@ -XXX,XX +XXX,XX @@ static void sd_realize(DeviceState *dev, Error **errp)
45
46
switch (sd->spec_version) {
47
case SD_PHY_SPECv1_10_VERS
48
- ... SD_PHY_SPECv2_00_VERS:
49
+ ... SD_PHY_SPECv3_01_VERS:
50
break;
51
default:
52
error_setg(errp, "Invalid SD card Spec version: %u", sd->spec_version);
53
--
54
2.17.1
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/31] sdcard: Disable CMD19/CMD23 for Spec v2
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
These commands got introduced by Spec v3
4
(see 0c3fb03f7ec and 4481bbc79d2).
5
6
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180607180641.874-7-f4bug@amsat.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/sd/sd.c | 6 ++++++
12
1 file changed, 6 insertions(+)
13
14
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/sd/sd.c
17
+++ b/hw/sd/sd.c
18
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
19
break;
20
21
case 19: /* CMD19: SEND_TUNING_BLOCK (SD) */
22
+ if (sd->spec_version < SD_PHY_SPECv3_01_VERS) {
23
+ break;
24
+ }
25
if (sd->state == sd_transfer_state) {
26
sd->state = sd_sendingdata_state;
27
sd->data_offset = 0;
28
@@ -XXX,XX +XXX,XX @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req)
29
break;
30
31
case 23: /* CMD23: SET_BLOCK_COUNT */
32
+ if (sd->spec_version < SD_PHY_SPECv3_01_VERS) {
33
+ break;
34
+ }
35
switch (sd->state) {
36
case sd_transfer_state:
37
sd->multi_blk_cnt = req.arg;
38
--
39
2.17.1
40
41
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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