[Qemu-devel] [PULL 00/25] target-arm queue
[PULL 0/2] target-arm queue
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target-arm queue. This has the "plumb txattrs through various
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This bug seemed worth fixing for 8.0 since we need an rc4 anyway:
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bits of exec.c" patches, and a collection of bug fixes from
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we were using uninitialized data for the guarded bit when
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various people.
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combining stage 1 and stage 2 attrs.
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v2: fix compile error on arm hosts...
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thanks
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thanks
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-- PMM
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-- PMM
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The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
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The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
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Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into staging (2023-04-10 11:47:52 +0100)
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Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230410
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for you to fetch changes up to 2f15b79280cf71b7991dfd3f0312a1797630e376:
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for you to fetch changes up to 8539dc00552e8ea60420856fc1262c8299bc6308:
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KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 16:32:35 +0100)
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target/arm: Copy guarded bit in combine_cacheattrs (2023-04-10 14:31:40 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm: Fix bug where we weren't initializing
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* target/arm: Honour FPCR.FZ in FRECPX
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guarded bit state when combining S1/S2 attrs
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* MAINTAINERS: Add entries for newer MPS2 boards and devices
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* hw/intc/arm_gicv3: Fix APxR<n> register dispatching
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* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
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GIC state
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* tcg: Fix helper function vs host abi for float16
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* arm: fix qemu crash on startup with -bios option
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* arm: fix malloc type mismatch
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* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
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* Correct CPACR reset value for v7 cores
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* memory.h: Improve IOMMU related documentation
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* exec: Plumb transaction attributes through various functions in
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preparation for allowing IOMMUs to see them
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* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
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* ARM: ACPI: Fix use-after-free due to memory realloc
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* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
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----------------------------------------------------------------
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----------------------------------------------------------------
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Francisco Iglesias (1):
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Richard Henderson (2):
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xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
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target/arm: PTE bit GP only applies to stage1
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target/arm: Copy guarded bit in combine_cacheattrs
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Igor Mammedov (1):
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target/arm/ptw.c | 11 ++++++-----
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arm: fix qemu crash on startup with -bios option
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1 file changed, 6 insertions(+), 5 deletions(-)
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Jan Kiszka (1):
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hw/intc/arm_gicv3: Fix APxR<n> register dispatching
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Paolo Bonzini (1):
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arm: fix malloc type mismatch
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Peter Maydell (17):
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target/arm: Honour FPCR.FZ in FRECPX
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MAINTAINERS: Add entries for newer MPS2 boards and devices
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Correct CPACR reset value for v7 cores
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memory.h: Improve IOMMU related documentation
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Make tb_invalidate_phys_addr() take a MemTxAttrs argument
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Make address_space_translate{, _cached}() take a MemTxAttrs argument
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Make address_space_map() take a MemTxAttrs argument
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Make address_space_access_valid() take a MemTxAttrs argument
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Make flatview_extend_translation() take a MemTxAttrs argument
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Make memory_region_access_valid() take a MemTxAttrs argument
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Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
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Make flatview_access_valid() take a MemTxAttrs argument
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Make flatview_translate() take a MemTxAttrs argument
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Make address_space_get_iotlb_entry() take a MemTxAttrs argument
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Make flatview_do_translate() take a MemTxAttrs argument
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Make address_space_translate_iommu take a MemTxAttrs argument
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vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
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Richard Henderson (1):
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tcg: Fix helper function vs host abi for float16
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Shannon Zhao (3):
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arm_gicv3_kvm: increase clroffset accordingly
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ARM: ACPI: Fix use-after-free due to memory realloc
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KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
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include/exec/exec-all.h | 5 +-
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include/exec/helper-head.h | 2 +-
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include/exec/memory-internal.h | 3 +-
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include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------
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include/migration/vmstate.h | 3 +
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include/sysemu/dma.h | 6 +-
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accel/tcg/translate-all.c | 4 +-
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exec.c | 95 ++++++++++++++++++------------
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hw/arm/boot.c | 18 +++---
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hw/arm/virt-acpi-build.c | 20 +++++--
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hw/dma/xlnx-zdma.c | 10 +++-
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hw/hppa/dino.c | 3 +-
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hw/intc/arm_gic_kvm.c | 1 -
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hw/intc/arm_gicv3_cpuif.c | 12 ++--
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hw/intc/arm_gicv3_kvm.c | 2 +-
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hw/nvram/fw_cfg.c | 12 ++--
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hw/s390x/s390-pci-inst.c | 3 +-
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hw/scsi/esp.c | 3 +-
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hw/vfio/common.c | 3 +-
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hw/virtio/vhost.c | 3 +-
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hw/xen/xen_pt_msi.c | 3 +-
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memory.c | 12 ++--
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memory_ldst.inc.c | 18 +++---
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target/arm/gdbstub.c | 3 +-
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target/arm/helper-a64.c | 41 +++++++------
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target/arm/helper.c | 90 ++++++++++++++++-------------
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target/arm/kvm.c | 3 +-
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target/ppc/mmu-hash64.c | 3 +-
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target/riscv/helper.c | 2 +-
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target/s390x/diag.c | 6 +-
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target/s390x/excp_helper.c | 3 +-
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target/s390x/mmu_helper.c | 3 +-
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target/s390x/sigp.c | 3 +-
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target/xtensa/op_helper.c | 3 +-
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MAINTAINERS | 9 ++-
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35 files changed, 355 insertions(+), 183 deletions(-)
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diff view generated by jsdifflib
New patch
[PULL 1/2] target/arm: PTE bit GP only applies to stage1
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From: Richard Henderson <richard.henderson@linaro.org>
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Only perform the extract of GP during the stage1 walk.
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Reported-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 10 +++++-----
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1 file changed, 5 insertions(+), 5 deletions(-)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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result->f.attrs.secure = false;
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}
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- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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- result->f.guarded = extract64(attrs, 50, 1); /* GP */
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- }
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-
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if (regime_is_stage2(mmu_idx)) {
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result->cacheattrs.is_s2_format = true;
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result->cacheattrs.attrs = extract32(attrs, 2, 4);
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@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
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assert(attrindx <= 7);
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result->cacheattrs.is_s2_format = false;
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result->cacheattrs.attrs = extract64(mair, attrindx * 8, 8);
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+
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+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */
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+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
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+ result->f.guarded = extract64(attrs, 50, 1); /* GP */
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+ }
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}
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/*
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--
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2.34.1
diff view generated by jsdifflib
New patch
[PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
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From: Richard Henderson <richard.henderson@linaro.org>
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The guarded bit comes from the stage1 walk.
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Fixes: Coverity CID 1507929
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/ptw.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/target/arm/ptw.c b/target/arm/ptw.c
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index XXXXXXX..XXXXXXX 100644
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--- a/target/arm/ptw.c
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+++ b/target/arm/ptw.c
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@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
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assert(!s1.is_s2_format);
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ret.is_s2_format = false;
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+ ret.guarded = s1.guarded;
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if (s1.attrs == 0xf0) {
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tagged = true;
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--
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2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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