1
target-arm queue. This has the "plumb txattrs through various
1
The following changes since commit 3db29dcac23da85486704ef9e7a8e7217f7829cd:
2
bits of exec.c" patches, and a collection of bug fixes from
3
various people.
4
2
5
thanks
3
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-01-12 13:51:36 +0000)
6
-- PMM
7
8
9
10
The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
11
12
Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
13
4
14
are available in the Git repository at:
5
are available in the Git repository at:
15
6
16
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230113
17
8
18
for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
9
for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31:
19
10
20
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
11
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled (2023-01-13 13:19:36 +0000)
21
12
22
----------------------------------------------------------------
13
----------------------------------------------------------------
23
target-arm queue:
14
target-arm queue:
24
* target/arm: Honour FPCR.FZ in FRECPX
15
hw/arm/stm32f405: correctly describe the memory layout
25
* MAINTAINERS: Add entries for newer MPS2 boards and devices
16
hw/arm: Add Olimex H405 board
26
* hw/intc/arm_gicv3: Fix APxR<n> register dispatching
17
cubieboard: Support booting from an SD card image with u-boot on it
27
* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
18
target/arm: Fix sve_probe_page
28
GIC state
19
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
29
* tcg: Fix helper function vs host abi for float16
20
various code cleanups
30
* arm: fix qemu crash on startup with -bios option
31
* arm: fix malloc type mismatch
32
* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
33
* Correct CPACR reset value for v7 cores
34
* memory.h: Improve IOMMU related documentation
35
* exec: Plumb transaction attributes through various functions in
36
preparation for allowing IOMMUs to see them
37
* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
38
* ARM: ACPI: Fix use-after-free due to memory realloc
39
* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
40
21
41
----------------------------------------------------------------
22
----------------------------------------------------------------
42
Francisco Iglesias (1):
23
Evgeny Iakovlev (1):
43
xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
24
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
44
25
45
Igor Mammedov (1):
26
Felipe Balbi (2):
46
arm: fix qemu crash on startup with -bios option
27
hw/arm/stm32f405: correctly describe the memory layout
28
hw/arm: Add Olimex H405
47
29
48
Jan Kiszka (1):
30
Philippe Mathieu-Daudé (27):
49
hw/intc/arm_gicv3: Fix APxR<n> register dispatching
31
hw/arm/pxa2xx: Simplify pxa255_init()
50
32
hw/arm/pxa2xx: Simplify pxa270_init()
51
Paolo Bonzini (1):
33
hw/arm/collie: Use the IEC binary prefix definitions
52
arm: fix malloc type mismatch
34
hw/arm/collie: Simplify flash creation using for() loop
53
35
hw/arm/gumstix: Improve documentation
54
Peter Maydell (17):
36
hw/arm/gumstix: Use the IEC binary prefix definitions
55
target/arm: Honour FPCR.FZ in FRECPX
37
hw/arm/mainstone: Use the IEC binary prefix definitions
56
MAINTAINERS: Add entries for newer MPS2 boards and devices
38
hw/arm/musicpal: Use the IEC binary prefix definitions
57
Correct CPACR reset value for v7 cores
39
hw/arm/omap_sx1: Remove unused 'total_ram' definitions
58
memory.h: Improve IOMMU related documentation
40
hw/arm/omap_sx1: Use the IEC binary prefix definitions
59
Make tb_invalidate_phys_addr() take a MemTxAttrs argument
41
hw/arm/z2: Use the IEC binary prefix definitions
60
Make address_space_translate{, _cached}() take a MemTxAttrs argument
42
hw/arm/vexpress: Remove dead code in vexpress_common_init()
61
Make address_space_map() take a MemTxAttrs argument
43
hw/arm: Remove unreachable code calling pflash_cfi01_register()
62
Make address_space_access_valid() take a MemTxAttrs argument
44
hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState
63
Make flatview_extend_translation() take a MemTxAttrs argument
45
hw/gpio/omap_gpio: Add local variable to avoid embedded cast
64
Make memory_region_access_valid() take a MemTxAttrs argument
46
hw/arm/omap: Drop useless casts from void * to pointer
65
Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
47
hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name
66
Make flatview_access_valid() take a MemTxAttrs argument
48
hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name
67
Make flatview_translate() take a MemTxAttrs argument
49
hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name
68
Make address_space_get_iotlb_entry() take a MemTxAttrs argument
50
hw/arm/stellaris: Drop useless casts from void * to pointer
69
Make flatview_do_translate() take a MemTxAttrs argument
51
hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name
70
Make address_space_translate_iommu take a MemTxAttrs argument
52
hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE()
71
vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
53
hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
54
hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC
55
hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()
56
hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'
57
hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock'
72
58
73
Richard Henderson (1):
59
Richard Henderson (1):
74
tcg: Fix helper function vs host abi for float16
60
target/arm: Fix sve_probe_page
75
61
76
Shannon Zhao (3):
62
Strahinja Jankovic (7):
77
arm_gicv3_kvm: increase clroffset accordingly
63
hw/misc: Allwinner-A10 Clock Controller Module Emulation
78
ARM: ACPI: Fix use-after-free due to memory realloc
64
hw/misc: Allwinner A10 DRAM Controller Emulation
79
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
65
{hw/i2c,docs/system/arm}: Allwinner TWI/I2C Emulation
66
hw/misc: AXP209 PMU Emulation
67
hw/arm: Add AXP209 to Cubieboard
68
hw/arm: Allwinner A10 enable SPL load from MMC
69
tests/avocado: Add SD boot test to Cubieboard
80
70
81
include/exec/exec-all.h | 5 +-
71
docs/system/arm/cubieboard.rst | 1 +
82
include/exec/helper-head.h | 2 +-
72
docs/system/arm/orangepi.rst | 1 +
83
include/exec/memory-internal.h | 3 +-
73
docs/system/arm/stm32.rst | 1 +
84
include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------
74
configs/devices/arm-softmmu/default.mak | 1 +
85
include/migration/vmstate.h | 3 +
75
include/hw/adc/npcm7xx_adc.h | 7 +-
86
include/sysemu/dma.h | 6 +-
76
include/hw/arm/allwinner-a10.h | 27 ++
87
accel/tcg/translate-all.c | 4 +-
77
include/hw/arm/allwinner-h3.h | 3 +
88
exec.c | 95 ++++++++++++++++++------------
78
include/hw/arm/npcm7xx.h | 18 +-
89
hw/arm/boot.c | 18 +++---
79
include/hw/arm/omap.h | 24 +-
90
hw/arm/virt-acpi-build.c | 20 +++++--
80
include/hw/arm/pxa.h | 11 +-
91
hw/dma/xlnx-zdma.c | 10 +++-
81
include/hw/arm/stm32f405_soc.h | 5 +-
92
hw/hppa/dino.c | 3 +-
82
include/hw/i2c/allwinner-i2c.h | 55 ++++
93
hw/intc/arm_gic_kvm.c | 1 -
83
include/hw/i2c/npcm7xx_smbus.h | 7 +-
94
hw/intc/arm_gicv3_cpuif.c | 12 ++--
84
include/hw/misc/allwinner-a10-ccm.h | 67 +++++
95
hw/intc/arm_gicv3_kvm.c | 2 +-
85
include/hw/misc/allwinner-a10-dramc.h | 68 +++++
96
hw/nvram/fw_cfg.c | 12 ++--
86
include/hw/misc/npcm7xx_clk.h | 2 +-
97
hw/s390x/s390-pci-inst.c | 3 +-
87
include/hw/misc/npcm7xx_gcr.h | 6 +-
98
hw/scsi/esp.c | 3 +-
88
include/hw/misc/npcm7xx_mft.h | 7 +-
99
hw/vfio/common.c | 3 +-
89
include/hw/misc/npcm7xx_pwm.h | 3 +-
100
hw/virtio/vhost.c | 3 +-
90
include/hw/misc/npcm7xx_rng.h | 6 +-
101
hw/xen/xen_pt_msi.c | 3 +-
91
include/hw/net/npcm7xx_emc.h | 5 +-
102
memory.c | 12 ++--
92
include/hw/sd/npcm7xx_sdhci.h | 4 +-
103
memory_ldst.inc.c | 18 +++---
93
hw/arm/allwinner-a10.c | 40 +++
104
target/arm/gdbstub.c | 3 +-
94
hw/arm/allwinner-h3.c | 11 +-
105
target/arm/helper-a64.c | 41 +++++++------
95
hw/arm/bcm2836.c | 9 +-
106
target/arm/helper.c | 90 ++++++++++++++++-------------
96
hw/arm/collie.c | 25 +-
107
target/ppc/mmu-hash64.c | 3 +-
97
hw/arm/cubieboard.c | 11 +
108
target/riscv/helper.c | 2 +-
98
hw/arm/gumstix.c | 45 ++--
109
target/s390x/diag.c | 6 +-
99
hw/arm/mainstone.c | 37 ++-
110
target/s390x/excp_helper.c | 3 +-
100
hw/arm/musicpal.c | 9 +-
111
target/s390x/mmu_helper.c | 3 +-
101
hw/arm/olimex-stm32-h405.c | 69 +++++
112
target/s390x/sigp.c | 3 +-
102
hw/arm/omap1.c | 115 ++++----
113
target/xtensa/op_helper.c | 3 +-
103
hw/arm/omap2.c | 40 ++-
114
MAINTAINERS | 9 ++-
104
hw/arm/omap_sx1.c | 53 ++--
115
34 files changed, 353 insertions(+), 182 deletions(-)
105
hw/arm/palm.c | 2 +-
106
hw/arm/pxa2xx.c | 8 +-
107
hw/arm/spitz.c | 6 +-
108
hw/arm/stellaris.c | 73 +++--
109
hw/arm/stm32f405_soc.c | 8 +
110
hw/arm/tosa.c | 2 +-
111
hw/arm/versatilepb.c | 6 +-
112
hw/arm/vexpress.c | 10 +-
113
hw/arm/z2.c | 16 +-
114
hw/char/omap_uart.c | 7 +-
115
hw/display/omap_dss.c | 15 +-
116
hw/display/omap_lcdc.c | 9 +-
117
hw/dma/omap_dma.c | 15 +-
118
hw/gpio/omap_gpio.c | 48 ++--
119
hw/i2c/allwinner-i2c.c | 459 ++++++++++++++++++++++++++++++++
120
hw/intc/omap_intc.c | 38 +--
121
hw/intc/xilinx_intc.c | 28 +-
122
hw/misc/allwinner-a10-ccm.c | 224 ++++++++++++++++
123
hw/misc/allwinner-a10-dramc.c | 179 +++++++++++++
124
hw/misc/axp209.c | 238 +++++++++++++++++
125
hw/misc/omap_gpmc.c | 12 +-
126
hw/misc/omap_l4.c | 7 +-
127
hw/misc/omap_sdrc.c | 7 +-
128
hw/misc/omap_tap.c | 5 +-
129
hw/misc/sbsa_ec.c | 12 +-
130
hw/sd/omap_mmc.c | 9 +-
131
hw/ssi/omap_spi.c | 7 +-
132
hw/timer/omap_gptimer.c | 22 +-
133
hw/timer/omap_synctimer.c | 4 +-
134
hw/timer/xilinx_timer.c | 27 +-
135
target/arm/helper.c | 3 +
136
target/arm/sve_helper.c | 14 +-
137
MAINTAINERS | 8 +
138
hw/arm/Kconfig | 9 +
139
hw/arm/meson.build | 1 +
140
hw/i2c/Kconfig | 4 +
141
hw/i2c/meson.build | 1 +
142
hw/i2c/trace-events | 5 +
143
hw/misc/Kconfig | 10 +
144
hw/misc/meson.build | 3 +
145
hw/misc/trace-events | 5 +
146
tests/avocado/boot_linux_console.py | 47 ++++
147
76 files changed, 1951 insertions(+), 455 deletions(-)
148
create mode 100644 include/hw/i2c/allwinner-i2c.h
149
create mode 100644 include/hw/misc/allwinner-a10-ccm.h
150
create mode 100644 include/hw/misc/allwinner-a10-dramc.h
151
create mode 100644 hw/arm/olimex-stm32-h405.c
152
create mode 100644 hw/i2c/allwinner-i2c.c
153
create mode 100644 hw/misc/allwinner-a10-ccm.c
154
create mode 100644 hw/misc/allwinner-a10-dramc.c
155
create mode 100644 hw/misc/axp209.c
116
156
diff view generated by jsdifflib
New patch
1
From: Felipe Balbi <balbi@kernel.org>
1
2
3
STM32F405 has 128K of SRAM and another 64K of CCM (Core-coupled
4
Memory) at a different base address. Correctly describe the memory
5
layout to give existing FW images a chance to run unmodified.
6
7
Reviewed-by: Alistair Francis <alistair@alistair23.me>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Felipe Balbi <balbi@kernel.org>
10
Message-id: 20221230145733.200496-2-balbi@kernel.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/arm/stm32f405_soc.h | 5 ++++-
14
hw/arm/stm32f405_soc.c | 8 ++++++++
15
2 files changed, 12 insertions(+), 1 deletion(-)
16
17
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/stm32f405_soc.h
20
+++ b/include/hw/arm/stm32f405_soc.h
21
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(STM32F405State, STM32F405_SOC)
22
#define FLASH_BASE_ADDRESS 0x08000000
23
#define FLASH_SIZE (1024 * 1024)
24
#define SRAM_BASE_ADDRESS 0x20000000
25
-#define SRAM_SIZE (192 * 1024)
26
+#define SRAM_SIZE (128 * 1024)
27
+#define CCM_BASE_ADDRESS 0x10000000
28
+#define CCM_SIZE (64 * 1024)
29
30
struct STM32F405State {
31
/*< private >*/
32
@@ -XXX,XX +XXX,XX @@ struct STM32F405State {
33
STM32F2XXADCState adc[STM_NUM_ADCS];
34
STM32F2XXSPIState spi[STM_NUM_SPIS];
35
36
+ MemoryRegion ccm;
37
MemoryRegion sram;
38
MemoryRegion flash;
39
MemoryRegion flash_alias;
40
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/stm32f405_soc.c
43
+++ b/hw/arm/stm32f405_soc.c
44
@@ -XXX,XX +XXX,XX @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
45
}
46
memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
47
48
+ memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
49
+ &err);
50
+ if (err != NULL) {
51
+ error_propagate(errp, err);
52
+ return;
53
+ }
54
+ memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
55
+
56
armv7m = DEVICE(&s->armv7m);
57
qdev_prop_set_uint32(armv7m, "num-irq", 96);
58
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
59
--
60
2.34.1
61
62
diff view generated by jsdifflib
1
Add entries to MAINTAINERS to cover the newer MPS2 boards and
1
From: Felipe Balbi <balbi@kernel.org>
2
the new devices they use.
3
2
3
Olimex makes a series of low-cost STM32 boards. This commit introduces
4
the minimum setup to support SMT32-H405. See [1] for details
5
6
[1] https://www.olimex.com/Products/ARM/ST/STM32-H405/
7
8
Signed-off-by: Felipe Balbi <balbi@kernel.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20221230145733.200496-3-balbi@kernel.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
6
---
13
---
7
MAINTAINERS | 9 +++++++--
14
docs/system/arm/stm32.rst | 1 +
8
1 file changed, 7 insertions(+), 2 deletions(-)
15
configs/devices/arm-softmmu/default.mak | 1 +
16
hw/arm/olimex-stm32-h405.c | 69 +++++++++++++++++++++++++
17
MAINTAINERS | 6 +++
18
hw/arm/Kconfig | 4 ++
19
hw/arm/meson.build | 1 +
20
6 files changed, 82 insertions(+)
21
create mode 100644 hw/arm/olimex-stm32-h405.c
9
22
23
diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
24
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/system/arm/stm32.rst
26
+++ b/docs/system/arm/stm32.rst
27
@@ -XXX,XX +XXX,XX @@ The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
28
compatible with STM32F2 series. The following machines are based on this chip :
29
30
- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller
31
+- ``olimex-stm32-h405`` Olimex STM32 H405 board with STM32F405RGT6 microcontroller
32
33
There are many other STM32 series that are currently not supported by QEMU.
34
35
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
36
index XXXXXXX..XXXXXXX 100644
37
--- a/configs/devices/arm-softmmu/default.mak
38
+++ b/configs/devices/arm-softmmu/default.mak
39
@@ -XXX,XX +XXX,XX @@ CONFIG_COLLIE=y
40
CONFIG_ASPEED_SOC=y
41
CONFIG_NETDUINO2=y
42
CONFIG_NETDUINOPLUS2=y
43
+CONFIG_OLIMEX_STM32_H405=y
44
CONFIG_MPS2=y
45
CONFIG_RASPI=y
46
CONFIG_DIGIC=y
47
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
48
new file mode 100644
49
index XXXXXXX..XXXXXXX
50
--- /dev/null
51
+++ b/hw/arm/olimex-stm32-h405.c
52
@@ -XXX,XX +XXX,XX @@
53
+/*
54
+ * ST STM32VLDISCOVERY machine
55
+ * Olimex STM32-H405 machine
56
+ *
57
+ * Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
58
+ *
59
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
60
+ * of this software and associated documentation files (the "Software"), to deal
61
+ * in the Software without restriction, including without limitation the rights
62
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
63
+ * copies of the Software, and to permit persons to whom the Software is
64
+ * furnished to do so, subject to the following conditions:
65
+ *
66
+ * The above copyright notice and this permission notice shall be included in
67
+ * all copies or substantial portions of the Software.
68
+ *
69
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
70
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
71
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
72
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
73
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
74
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
75
+ * THE SOFTWARE.
76
+ */
77
+
78
+#include "qemu/osdep.h"
79
+#include "qapi/error.h"
80
+#include "hw/boards.h"
81
+#include "hw/qdev-properties.h"
82
+#include "hw/qdev-clock.h"
83
+#include "qemu/error-report.h"
84
+#include "hw/arm/stm32f405_soc.h"
85
+#include "hw/arm/boot.h"
86
+
87
+/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
88
+
89
+/* Main SYSCLK frequency in Hz (168MHz) */
90
+#define SYSCLK_FRQ 168000000ULL
91
+
92
+static void olimex_stm32_h405_init(MachineState *machine)
93
+{
94
+ DeviceState *dev;
95
+ Clock *sysclk;
96
+
97
+ /* This clock doesn't need migration because it is fixed-frequency */
98
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
99
+ clock_set_hz(sysclk, SYSCLK_FRQ);
100
+
101
+ dev = qdev_new(TYPE_STM32F405_SOC);
102
+ qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
103
+ qdev_connect_clock_in(dev, "sysclk", sysclk);
104
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
105
+
106
+ armv7m_load_kernel(ARM_CPU(first_cpu),
107
+ machine->kernel_filename,
108
+ 0, FLASH_SIZE);
109
+}
110
+
111
+static void olimex_stm32_h405_machine_init(MachineClass *mc)
112
+{
113
+ mc->desc = "Olimex STM32-H405 (Cortex-M4)";
114
+ mc->init = olimex_stm32_h405_init;
115
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
116
+
117
+ /* SRAM pre-allocated as part of the SoC instantiation */
118
+ mc->default_ram_size = 0;
119
+}
120
+
121
+DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
10
diff --git a/MAINTAINERS b/MAINTAINERS
122
diff --git a/MAINTAINERS b/MAINTAINERS
11
index XXXXXXX..XXXXXXX 100644
123
index XXXXXXX..XXXXXXX 100644
12
--- a/MAINTAINERS
124
--- a/MAINTAINERS
13
+++ b/MAINTAINERS
125
+++ b/MAINTAINERS
14
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
126
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
15
F: include/hw/timer/cmsdk-apb-timer.h
127
S: Maintained
16
F: hw/char/cmsdk-apb-uart.c
128
F: hw/arm/netduinoplus2.c
17
F: include/hw/char/cmsdk-apb-uart.h
129
18
+F: hw/misc/tz-ppc.c
130
+Olimex STM32 H405
19
+F: include/hw/misc/tz-ppc.h
131
+M: Felipe Balbi <balbi@kernel.org>
20
132
+L: qemu-arm@nongnu.org
21
ARM cores
133
+S: Maintained
134
+F: hw/arm/olimex-stm32-h405.c
135
+
136
SmartFusion2
137
M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
22
M: Peter Maydell <peter.maydell@linaro.org>
138
M: Peter Maydell <peter.maydell@linaro.org>
23
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
139
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
24
L: qemu-arm@nongnu.org
140
index XXXXXXX..XXXXXXX 100644
25
S: Maintained
141
--- a/hw/arm/Kconfig
26
F: hw/arm/mps2.c
142
+++ b/hw/arm/Kconfig
27
-F: hw/misc/mps2-scc.c
143
@@ -XXX,XX +XXX,XX @@ config NETDUINOPLUS2
28
-F: include/hw/misc/mps2-scc.h
144
bool
29
+F: hw/arm/mps2-tz.c
145
select STM32F405_SOC
30
+F: hw/misc/mps2-*.c
146
31
+F: include/hw/misc/mps2-*.h
147
+config OLIMEX_STM32_H405
32
+F: hw/arm/iotkit.c
148
+ bool
33
+F: include/hw/arm/iotkit.h
149
+ select STM32F405_SOC
34
150
+
35
Musicpal
151
config NSERIES
36
M: Jan Kiszka <jan.kiszka@web.de>
152
bool
153
select OMAP
154
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
155
index XXXXXXX..XXXXXXX 100644
156
--- a/hw/arm/meson.build
157
+++ b/hw/arm/meson.build
158
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
159
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
160
arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
161
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
162
+arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
163
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
164
arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
165
arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
37
--
166
--
38
2.17.1
167
2.34.1
39
168
40
169
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
During SPL boot several Clock Controller Module (CCM) registers are
4
read, most important are PLL and Tuning, as well as divisor registers.
5
6
This patch adds these registers and initializes reset values from user's
7
guide.
8
9
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
10
11
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
12
Message-id: 20221226220303.14420-2-strahinja.p.jankovic@gmail.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/arm/allwinner-a10.h | 2 +
16
include/hw/misc/allwinner-a10-ccm.h | 67 +++++++++
17
hw/arm/allwinner-a10.c | 7 +
18
hw/misc/allwinner-a10-ccm.c | 224 ++++++++++++++++++++++++++++
19
hw/arm/Kconfig | 1 +
20
hw/misc/Kconfig | 3 +
21
hw/misc/meson.build | 1 +
22
7 files changed, 305 insertions(+)
23
create mode 100644 include/hw/misc/allwinner-a10-ccm.h
24
create mode 100644 hw/misc/allwinner-a10-ccm.c
25
26
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/hw/arm/allwinner-a10.h
29
+++ b/include/hw/arm/allwinner-a10.h
30
@@ -XXX,XX +XXX,XX @@
31
#include "hw/usb/hcd-ohci.h"
32
#include "hw/usb/hcd-ehci.h"
33
#include "hw/rtc/allwinner-rtc.h"
34
+#include "hw/misc/allwinner-a10-ccm.h"
35
36
#include "target/arm/cpu.h"
37
#include "qom/object.h"
38
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
39
/*< public >*/
40
41
ARMCPU cpu;
42
+ AwA10ClockCtlState ccm;
43
AwA10PITState timer;
44
AwA10PICState intc;
45
AwEmacState emac;
46
diff --git a/include/hw/misc/allwinner-a10-ccm.h b/include/hw/misc/allwinner-a10-ccm.h
47
new file mode 100644
48
index XXXXXXX..XXXXXXX
49
--- /dev/null
50
+++ b/include/hw/misc/allwinner-a10-ccm.h
51
@@ -XXX,XX +XXX,XX @@
52
+/*
53
+ * Allwinner A10 Clock Control Module emulation
54
+ *
55
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
56
+ *
57
+ * This file is derived from Allwinner H3 CCU,
58
+ * by Niek Linnenbank.
59
+ *
60
+ * This program is free software: you can redistribute it and/or modify
61
+ * it under the terms of the GNU General Public License as published by
62
+ * the Free Software Foundation, either version 2 of the License, or
63
+ * (at your option) any later version.
64
+ *
65
+ * This program is distributed in the hope that it will be useful,
66
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
67
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
68
+ * GNU General Public License for more details.
69
+ *
70
+ * You should have received a copy of the GNU General Public License
71
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
72
+ */
73
+
74
+#ifndef HW_MISC_ALLWINNER_A10_CCM_H
75
+#define HW_MISC_ALLWINNER_A10_CCM_H
76
+
77
+#include "qom/object.h"
78
+#include "hw/sysbus.h"
79
+
80
+/**
81
+ * @name Constants
82
+ * @{
83
+ */
84
+
85
+/** Size of register I/O address space used by CCM device */
86
+#define AW_A10_CCM_IOSIZE (0x400)
87
+
88
+/** Total number of known registers */
89
+#define AW_A10_CCM_REGS_NUM (AW_A10_CCM_IOSIZE / sizeof(uint32_t))
90
+
91
+/** @} */
92
+
93
+/**
94
+ * @name Object model
95
+ * @{
96
+ */
97
+
98
+#define TYPE_AW_A10_CCM "allwinner-a10-ccm"
99
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10ClockCtlState, AW_A10_CCM)
100
+
101
+/** @} */
102
+
103
+/**
104
+ * Allwinner A10 CCM object instance state.
105
+ */
106
+struct AwA10ClockCtlState {
107
+ /*< private >*/
108
+ SysBusDevice parent_obj;
109
+ /*< public >*/
110
+
111
+ /** Maps I/O registers in physical memory */
112
+ MemoryRegion iomem;
113
+
114
+ /** Array of hardware registers */
115
+ uint32_t regs[AW_A10_CCM_REGS_NUM];
116
+};
117
+
118
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
119
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/hw/arm/allwinner-a10.c
122
+++ b/hw/arm/allwinner-a10.c
123
@@ -XXX,XX +XXX,XX @@
124
#include "hw/usb/hcd-ohci.h"
125
126
#define AW_A10_MMC0_BASE 0x01c0f000
127
+#define AW_A10_CCM_BASE 0x01c20000
128
#define AW_A10_PIC_REG_BASE 0x01c20400
129
#define AW_A10_PIT_REG_BASE 0x01c20c00
130
#define AW_A10_UART0_REG_BASE 0x01c28000
131
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
132
133
object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
134
135
+ object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
136
+
137
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
138
139
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
140
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
141
memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
142
create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
143
144
+ /* Clock Control Module */
145
+ sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
146
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
147
+
148
/* FIXME use qdev NIC properties instead of nd_table[] */
149
if (nd_table[0].used) {
150
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
151
diff --git a/hw/misc/allwinner-a10-ccm.c b/hw/misc/allwinner-a10-ccm.c
152
new file mode 100644
153
index XXXXXXX..XXXXXXX
154
--- /dev/null
155
+++ b/hw/misc/allwinner-a10-ccm.c
156
@@ -XXX,XX +XXX,XX @@
157
+/*
158
+ * Allwinner A10 Clock Control Module emulation
159
+ *
160
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
161
+ *
162
+ * This file is derived from Allwinner H3 CCU,
163
+ * by Niek Linnenbank.
164
+ *
165
+ * This program is free software: you can redistribute it and/or modify
166
+ * it under the terms of the GNU General Public License as published by
167
+ * the Free Software Foundation, either version 2 of the License, or
168
+ * (at your option) any later version.
169
+ *
170
+ * This program is distributed in the hope that it will be useful,
171
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
172
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
173
+ * GNU General Public License for more details.
174
+ *
175
+ * You should have received a copy of the GNU General Public License
176
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
177
+ */
178
+
179
+#include "qemu/osdep.h"
180
+#include "qemu/units.h"
181
+#include "hw/sysbus.h"
182
+#include "migration/vmstate.h"
183
+#include "qemu/log.h"
184
+#include "qemu/module.h"
185
+#include "hw/misc/allwinner-a10-ccm.h"
186
+
187
+/* CCM register offsets */
188
+enum {
189
+ REG_PLL1_CFG = 0x0000, /* PLL1 Control */
190
+ REG_PLL1_TUN = 0x0004, /* PLL1 Tuning */
191
+ REG_PLL2_CFG = 0x0008, /* PLL2 Control */
192
+ REG_PLL2_TUN = 0x000C, /* PLL2 Tuning */
193
+ REG_PLL3_CFG = 0x0010, /* PLL3 Control */
194
+ REG_PLL4_CFG = 0x0018, /* PLL4 Control */
195
+ REG_PLL5_CFG = 0x0020, /* PLL5 Control */
196
+ REG_PLL5_TUN = 0x0024, /* PLL5 Tuning */
197
+ REG_PLL6_CFG = 0x0028, /* PLL6 Control */
198
+ REG_PLL6_TUN = 0x002C, /* PLL6 Tuning */
199
+ REG_PLL7_CFG = 0x0030, /* PLL7 Control */
200
+ REG_PLL1_TUN2 = 0x0038, /* PLL1 Tuning2 */
201
+ REG_PLL5_TUN2 = 0x003C, /* PLL5 Tuning2 */
202
+ REG_PLL8_CFG = 0x0040, /* PLL8 Control */
203
+ REG_OSC24M_CFG = 0x0050, /* OSC24M Control */
204
+ REG_CPU_AHB_APB0_CFG = 0x0054, /* CPU, AHB and APB0 Divide Ratio */
205
+};
206
+
207
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
208
+
209
+/* CCM register reset values */
210
+enum {
211
+ REG_PLL1_CFG_RST = 0x21005000,
212
+ REG_PLL1_TUN_RST = 0x0A101000,
213
+ REG_PLL2_CFG_RST = 0x08100010,
214
+ REG_PLL2_TUN_RST = 0x00000000,
215
+ REG_PLL3_CFG_RST = 0x0010D063,
216
+ REG_PLL4_CFG_RST = 0x21009911,
217
+ REG_PLL5_CFG_RST = 0x11049280,
218
+ REG_PLL5_TUN_RST = 0x14888000,
219
+ REG_PLL6_CFG_RST = 0x21009911,
220
+ REG_PLL6_TUN_RST = 0x00000000,
221
+ REG_PLL7_CFG_RST = 0x0010D063,
222
+ REG_PLL1_TUN2_RST = 0x00000000,
223
+ REG_PLL5_TUN2_RST = 0x00000000,
224
+ REG_PLL8_CFG_RST = 0x21009911,
225
+ REG_OSC24M_CFG_RST = 0x00138013,
226
+ REG_CPU_AHB_APB0_CFG_RST = 0x00010010,
227
+};
228
+
229
+static uint64_t allwinner_a10_ccm_read(void *opaque, hwaddr offset,
230
+ unsigned size)
231
+{
232
+ const AwA10ClockCtlState *s = AW_A10_CCM(opaque);
233
+ const uint32_t idx = REG_INDEX(offset);
234
+
235
+ switch (offset) {
236
+ case REG_PLL1_CFG:
237
+ case REG_PLL1_TUN:
238
+ case REG_PLL2_CFG:
239
+ case REG_PLL2_TUN:
240
+ case REG_PLL3_CFG:
241
+ case REG_PLL4_CFG:
242
+ case REG_PLL5_CFG:
243
+ case REG_PLL5_TUN:
244
+ case REG_PLL6_CFG:
245
+ case REG_PLL6_TUN:
246
+ case REG_PLL7_CFG:
247
+ case REG_PLL1_TUN2:
248
+ case REG_PLL5_TUN2:
249
+ case REG_PLL8_CFG:
250
+ case REG_OSC24M_CFG:
251
+ case REG_CPU_AHB_APB0_CFG:
252
+ break;
253
+ case 0x158 ... AW_A10_CCM_IOSIZE:
254
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
255
+ __func__, (uint32_t)offset);
256
+ return 0;
257
+ default:
258
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
259
+ __func__, (uint32_t)offset);
260
+ return 0;
261
+ }
262
+
263
+ return s->regs[idx];
264
+}
265
+
266
+static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
267
+ uint64_t val, unsigned size)
268
+{
269
+ AwA10ClockCtlState *s = AW_A10_CCM(opaque);
270
+ const uint32_t idx = REG_INDEX(offset);
271
+
272
+ switch (offset) {
273
+ case REG_PLL1_CFG:
274
+ case REG_PLL1_TUN:
275
+ case REG_PLL2_CFG:
276
+ case REG_PLL2_TUN:
277
+ case REG_PLL3_CFG:
278
+ case REG_PLL4_CFG:
279
+ case REG_PLL5_CFG:
280
+ case REG_PLL5_TUN:
281
+ case REG_PLL6_CFG:
282
+ case REG_PLL6_TUN:
283
+ case REG_PLL7_CFG:
284
+ case REG_PLL1_TUN2:
285
+ case REG_PLL5_TUN2:
286
+ case REG_PLL8_CFG:
287
+ case REG_OSC24M_CFG:
288
+ case REG_CPU_AHB_APB0_CFG:
289
+ break;
290
+ case 0x158 ... AW_A10_CCM_IOSIZE:
291
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
292
+ __func__, (uint32_t)offset);
293
+ break;
294
+ default:
295
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
296
+ __func__, (uint32_t)offset);
297
+ break;
298
+ }
299
+
300
+ s->regs[idx] = (uint32_t) val;
301
+}
302
+
303
+static const MemoryRegionOps allwinner_a10_ccm_ops = {
304
+ .read = allwinner_a10_ccm_read,
305
+ .write = allwinner_a10_ccm_write,
306
+ .endianness = DEVICE_NATIVE_ENDIAN,
307
+ .valid = {
308
+ .min_access_size = 4,
309
+ .max_access_size = 4,
310
+ },
311
+ .impl.min_access_size = 4,
312
+};
313
+
314
+static void allwinner_a10_ccm_reset_enter(Object *obj, ResetType type)
315
+{
316
+ AwA10ClockCtlState *s = AW_A10_CCM(obj);
317
+
318
+ /* Set default values for registers */
319
+ s->regs[REG_INDEX(REG_PLL1_CFG)] = REG_PLL1_CFG_RST;
320
+ s->regs[REG_INDEX(REG_PLL1_TUN)] = REG_PLL1_TUN_RST;
321
+ s->regs[REG_INDEX(REG_PLL2_CFG)] = REG_PLL2_CFG_RST;
322
+ s->regs[REG_INDEX(REG_PLL2_TUN)] = REG_PLL2_TUN_RST;
323
+ s->regs[REG_INDEX(REG_PLL3_CFG)] = REG_PLL3_CFG_RST;
324
+ s->regs[REG_INDEX(REG_PLL4_CFG)] = REG_PLL4_CFG_RST;
325
+ s->regs[REG_INDEX(REG_PLL5_CFG)] = REG_PLL5_CFG_RST;
326
+ s->regs[REG_INDEX(REG_PLL5_TUN)] = REG_PLL5_TUN_RST;
327
+ s->regs[REG_INDEX(REG_PLL6_CFG)] = REG_PLL6_CFG_RST;
328
+ s->regs[REG_INDEX(REG_PLL6_TUN)] = REG_PLL6_TUN_RST;
329
+ s->regs[REG_INDEX(REG_PLL7_CFG)] = REG_PLL7_CFG_RST;
330
+ s->regs[REG_INDEX(REG_PLL1_TUN2)] = REG_PLL1_TUN2_RST;
331
+ s->regs[REG_INDEX(REG_PLL5_TUN2)] = REG_PLL5_TUN2_RST;
332
+ s->regs[REG_INDEX(REG_PLL8_CFG)] = REG_PLL8_CFG_RST;
333
+ s->regs[REG_INDEX(REG_OSC24M_CFG)] = REG_OSC24M_CFG_RST;
334
+ s->regs[REG_INDEX(REG_CPU_AHB_APB0_CFG)] = REG_CPU_AHB_APB0_CFG_RST;
335
+}
336
+
337
+static void allwinner_a10_ccm_init(Object *obj)
338
+{
339
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
340
+ AwA10ClockCtlState *s = AW_A10_CCM(obj);
341
+
342
+ /* Memory mapping */
343
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_ccm_ops, s,
344
+ TYPE_AW_A10_CCM, AW_A10_CCM_IOSIZE);
345
+ sysbus_init_mmio(sbd, &s->iomem);
346
+}
347
+
348
+static const VMStateDescription allwinner_a10_ccm_vmstate = {
349
+ .name = "allwinner-a10-ccm",
350
+ .version_id = 1,
351
+ .minimum_version_id = 1,
352
+ .fields = (VMStateField[]) {
353
+ VMSTATE_UINT32_ARRAY(regs, AwA10ClockCtlState, AW_A10_CCM_REGS_NUM),
354
+ VMSTATE_END_OF_LIST()
355
+ }
356
+};
357
+
358
+static void allwinner_a10_ccm_class_init(ObjectClass *klass, void *data)
359
+{
360
+ DeviceClass *dc = DEVICE_CLASS(klass);
361
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
362
+
363
+ rc->phases.enter = allwinner_a10_ccm_reset_enter;
364
+ dc->vmsd = &allwinner_a10_ccm_vmstate;
365
+}
366
+
367
+static const TypeInfo allwinner_a10_ccm_info = {
368
+ .name = TYPE_AW_A10_CCM,
369
+ .parent = TYPE_SYS_BUS_DEVICE,
370
+ .instance_init = allwinner_a10_ccm_init,
371
+ .instance_size = sizeof(AwA10ClockCtlState),
372
+ .class_init = allwinner_a10_ccm_class_init,
373
+};
374
+
375
+static void allwinner_a10_ccm_register(void)
376
+{
377
+ type_register_static(&allwinner_a10_ccm_info);
378
+}
379
+
380
+type_init(allwinner_a10_ccm_register)
381
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
382
index XXXXXXX..XXXXXXX 100644
383
--- a/hw/arm/Kconfig
384
+++ b/hw/arm/Kconfig
385
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
386
select AHCI
387
select ALLWINNER_A10_PIT
388
select ALLWINNER_A10_PIC
389
+ select ALLWINNER_A10_CCM
390
select ALLWINNER_EMAC
391
select SERIAL
392
select UNIMP
393
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
394
index XXXXXXX..XXXXXXX 100644
395
--- a/hw/misc/Kconfig
396
+++ b/hw/misc/Kconfig
397
@@ -XXX,XX +XXX,XX @@ config VIRT_CTRL
398
config LASI
399
bool
400
401
+config ALLWINNER_A10_CCM
402
+ bool
403
+
404
source macio/Kconfig
405
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
406
index XXXXXXX..XXXXXXX 100644
407
--- a/hw/misc/meson.build
408
+++ b/hw/misc/meson.build
409
@@ -XXX,XX +XXX,XX @@ subdir('macio')
410
411
softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
412
413
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
414
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
415
specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
416
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
417
--
418
2.34.1
diff view generated by jsdifflib
New patch
1
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
2
3
During SPL boot several DRAM Controller registers are used. Most
4
important registers are those related to DRAM initialization and
5
calibration, where SPL initiates process and waits until certain bit is
6
set/cleared.
7
8
This patch adds these registers, initializes reset values from user's
9
guide and updates state of registers as SPL expects it.
10
11
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
12
13
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Message-id: 20221226220303.14420-3-strahinja.p.jankovic@gmail.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
include/hw/arm/allwinner-a10.h | 2 +
18
include/hw/misc/allwinner-a10-dramc.h | 68 ++++++++++
19
hw/arm/allwinner-a10.c | 7 +
20
hw/misc/allwinner-a10-dramc.c | 179 ++++++++++++++++++++++++++
21
hw/arm/Kconfig | 1 +
22
hw/misc/Kconfig | 3 +
23
hw/misc/meson.build | 1 +
24
7 files changed, 261 insertions(+)
25
create mode 100644 include/hw/misc/allwinner-a10-dramc.h
26
create mode 100644 hw/misc/allwinner-a10-dramc.c
27
28
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/arm/allwinner-a10.h
31
+++ b/include/hw/arm/allwinner-a10.h
32
@@ -XXX,XX +XXX,XX @@
33
#include "hw/usb/hcd-ehci.h"
34
#include "hw/rtc/allwinner-rtc.h"
35
#include "hw/misc/allwinner-a10-ccm.h"
36
+#include "hw/misc/allwinner-a10-dramc.h"
37
38
#include "target/arm/cpu.h"
39
#include "qom/object.h"
40
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
41
42
ARMCPU cpu;
43
AwA10ClockCtlState ccm;
44
+ AwA10DramControllerState dramc;
45
AwA10PITState timer;
46
AwA10PICState intc;
47
AwEmacState emac;
48
diff --git a/include/hw/misc/allwinner-a10-dramc.h b/include/hw/misc/allwinner-a10-dramc.h
49
new file mode 100644
50
index XXXXXXX..XXXXXXX
51
--- /dev/null
52
+++ b/include/hw/misc/allwinner-a10-dramc.h
53
@@ -XXX,XX +XXX,XX @@
54
+/*
55
+ * Allwinner A10 DRAM Controller emulation
56
+ *
57
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
58
+ *
59
+ * This file is derived from Allwinner H3 DRAMC,
60
+ * by Niek Linnenbank.
61
+ *
62
+ * This program is free software: you can redistribute it and/or modify
63
+ * it under the terms of the GNU General Public License as published by
64
+ * the Free Software Foundation, either version 2 of the License, or
65
+ * (at your option) any later version.
66
+ *
67
+ * This program is distributed in the hope that it will be useful,
68
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
69
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
70
+ * GNU General Public License for more details.
71
+ *
72
+ * You should have received a copy of the GNU General Public License
73
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
74
+ */
75
+
76
+#ifndef HW_MISC_ALLWINNER_A10_DRAMC_H
77
+#define HW_MISC_ALLWINNER_A10_DRAMC_H
78
+
79
+#include "qom/object.h"
80
+#include "hw/sysbus.h"
81
+#include "hw/register.h"
82
+
83
+/**
84
+ * @name Constants
85
+ * @{
86
+ */
87
+
88
+/** Size of register I/O address space used by DRAMC device */
89
+#define AW_A10_DRAMC_IOSIZE (0x1000)
90
+
91
+/** Total number of known registers */
92
+#define AW_A10_DRAMC_REGS_NUM (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t))
93
+
94
+/** @} */
95
+
96
+/**
97
+ * @name Object model
98
+ * @{
99
+ */
100
+
101
+#define TYPE_AW_A10_DRAMC "allwinner-a10-dramc"
102
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC)
103
+
104
+/** @} */
105
+
106
+/**
107
+ * Allwinner A10 DRAMC object instance state.
108
+ */
109
+struct AwA10DramControllerState {
110
+ /*< private >*/
111
+ SysBusDevice parent_obj;
112
+ /*< public >*/
113
+
114
+ /** Maps I/O registers in physical memory */
115
+ MemoryRegion iomem;
116
+
117
+ /** Array of hardware registers */
118
+ uint32_t regs[AW_A10_DRAMC_REGS_NUM];
119
+};
120
+
121
+#endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */
122
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
123
index XXXXXXX..XXXXXXX 100644
124
--- a/hw/arm/allwinner-a10.c
125
+++ b/hw/arm/allwinner-a10.c
126
@@ -XXX,XX +XXX,XX @@
127
#include "hw/boards.h"
128
#include "hw/usb/hcd-ohci.h"
129
130
+#define AW_A10_DRAMC_BASE 0x01c01000
131
#define AW_A10_MMC0_BASE 0x01c0f000
132
#define AW_A10_CCM_BASE 0x01c20000
133
#define AW_A10_PIC_REG_BASE 0x01c20400
134
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
135
136
object_initialize_child(obj, "ccm", &s->ccm, TYPE_AW_A10_CCM);
137
138
+ object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_A10_DRAMC);
139
+
140
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
141
142
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
143
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
144
sysbus_realize(SYS_BUS_DEVICE(&s->ccm), &error_fatal);
145
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, AW_A10_CCM_BASE);
146
147
+ /* DRAM Control Module */
148
+ sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
149
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, AW_A10_DRAMC_BASE);
150
+
151
/* FIXME use qdev NIC properties instead of nd_table[] */
152
if (nd_table[0].used) {
153
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
154
diff --git a/hw/misc/allwinner-a10-dramc.c b/hw/misc/allwinner-a10-dramc.c
155
new file mode 100644
156
index XXXXXXX..XXXXXXX
157
--- /dev/null
158
+++ b/hw/misc/allwinner-a10-dramc.c
159
@@ -XXX,XX +XXX,XX @@
160
+/*
161
+ * Allwinner A10 DRAM Controller emulation
162
+ *
163
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
164
+ *
165
+ * This file is derived from Allwinner H3 DRAMC,
166
+ * by Niek Linnenbank.
167
+ *
168
+ * This program is free software: you can redistribute it and/or modify
169
+ * it under the terms of the GNU General Public License as published by
170
+ * the Free Software Foundation, either version 2 of the License, or
171
+ * (at your option) any later version.
172
+ *
173
+ * This program is distributed in the hope that it will be useful,
174
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
175
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
176
+ * GNU General Public License for more details.
177
+ *
178
+ * You should have received a copy of the GNU General Public License
179
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
180
+ */
181
+
182
+#include "qemu/osdep.h"
183
+#include "qemu/units.h"
184
+#include "hw/sysbus.h"
185
+#include "migration/vmstate.h"
186
+#include "qemu/log.h"
187
+#include "qemu/module.h"
188
+#include "hw/misc/allwinner-a10-dramc.h"
189
+
190
+/* DRAMC register offsets */
191
+enum {
192
+ REG_SDR_CCR = 0x0000,
193
+ REG_SDR_ZQCR0 = 0x00a8,
194
+ REG_SDR_ZQSR = 0x00b0
195
+};
196
+
197
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
198
+
199
+/* DRAMC register flags */
200
+enum {
201
+ REG_SDR_CCR_DATA_TRAINING = (1 << 30),
202
+ REG_SDR_CCR_DRAM_INIT = (1 << 31),
203
+};
204
+enum {
205
+ REG_SDR_ZQSR_ZCAL = (1 << 31),
206
+};
207
+
208
+/* DRAMC register reset values */
209
+enum {
210
+ REG_SDR_CCR_RESET = 0x80020000,
211
+ REG_SDR_ZQCR0_RESET = 0x07b00000,
212
+ REG_SDR_ZQSR_RESET = 0x80000000
213
+};
214
+
215
+static uint64_t allwinner_a10_dramc_read(void *opaque, hwaddr offset,
216
+ unsigned size)
217
+{
218
+ const AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
219
+ const uint32_t idx = REG_INDEX(offset);
220
+
221
+ switch (offset) {
222
+ case REG_SDR_CCR:
223
+ case REG_SDR_ZQCR0:
224
+ case REG_SDR_ZQSR:
225
+ break;
226
+ case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
227
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
228
+ __func__, (uint32_t)offset);
229
+ return 0;
230
+ default:
231
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented read offset 0x%04x\n",
232
+ __func__, (uint32_t)offset);
233
+ return 0;
234
+ }
235
+
236
+ return s->regs[idx];
237
+}
238
+
239
+static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
240
+ uint64_t val, unsigned size)
241
+{
242
+ AwA10DramControllerState *s = AW_A10_DRAMC(opaque);
243
+ const uint32_t idx = REG_INDEX(offset);
244
+
245
+ switch (offset) {
246
+ case REG_SDR_CCR:
247
+ if (val & REG_SDR_CCR_DRAM_INIT) {
248
+ /* Clear DRAM_INIT to indicate process is done. */
249
+ val &= ~REG_SDR_CCR_DRAM_INIT;
250
+ }
251
+ if (val & REG_SDR_CCR_DATA_TRAINING) {
252
+ /* Clear DATA_TRAINING to indicate process is done. */
253
+ val &= ~REG_SDR_CCR_DATA_TRAINING;
254
+ }
255
+ break;
256
+ case REG_SDR_ZQCR0:
257
+ /* Set ZCAL in ZQSR to indicate calibration is done. */
258
+ s->regs[REG_INDEX(REG_SDR_ZQSR)] |= REG_SDR_ZQSR_ZCAL;
259
+ break;
260
+ case 0x2e4 ... AW_A10_DRAMC_IOSIZE:
261
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
262
+ __func__, (uint32_t)offset);
263
+ break;
264
+ default:
265
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
266
+ __func__, (uint32_t)offset);
267
+ break;
268
+ }
269
+
270
+ s->regs[idx] = (uint32_t) val;
271
+}
272
+
273
+static const MemoryRegionOps allwinner_a10_dramc_ops = {
274
+ .read = allwinner_a10_dramc_read,
275
+ .write = allwinner_a10_dramc_write,
276
+ .endianness = DEVICE_NATIVE_ENDIAN,
277
+ .valid = {
278
+ .min_access_size = 4,
279
+ .max_access_size = 4,
280
+ },
281
+ .impl.min_access_size = 4,
282
+};
283
+
284
+static void allwinner_a10_dramc_reset_enter(Object *obj, ResetType type)
285
+{
286
+ AwA10DramControllerState *s = AW_A10_DRAMC(obj);
287
+
288
+ /* Set default values for registers */
289
+ s->regs[REG_INDEX(REG_SDR_CCR)] = REG_SDR_CCR_RESET;
290
+ s->regs[REG_INDEX(REG_SDR_ZQCR0)] = REG_SDR_ZQCR0_RESET;
291
+ s->regs[REG_INDEX(REG_SDR_ZQSR)] = REG_SDR_ZQSR_RESET;
292
+}
293
+
294
+static void allwinner_a10_dramc_init(Object *obj)
295
+{
296
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
297
+ AwA10DramControllerState *s = AW_A10_DRAMC(obj);
298
+
299
+ /* Memory mapping */
300
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_dramc_ops, s,
301
+ TYPE_AW_A10_DRAMC, AW_A10_DRAMC_IOSIZE);
302
+ sysbus_init_mmio(sbd, &s->iomem);
303
+}
304
+
305
+static const VMStateDescription allwinner_a10_dramc_vmstate = {
306
+ .name = "allwinner-a10-dramc",
307
+ .version_id = 1,
308
+ .minimum_version_id = 1,
309
+ .fields = (VMStateField[]) {
310
+ VMSTATE_UINT32_ARRAY(regs, AwA10DramControllerState,
311
+ AW_A10_DRAMC_REGS_NUM),
312
+ VMSTATE_END_OF_LIST()
313
+ }
314
+};
315
+
316
+static void allwinner_a10_dramc_class_init(ObjectClass *klass, void *data)
317
+{
318
+ DeviceClass *dc = DEVICE_CLASS(klass);
319
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
320
+
321
+ rc->phases.enter = allwinner_a10_dramc_reset_enter;
322
+ dc->vmsd = &allwinner_a10_dramc_vmstate;
323
+}
324
+
325
+static const TypeInfo allwinner_a10_dramc_info = {
326
+ .name = TYPE_AW_A10_DRAMC,
327
+ .parent = TYPE_SYS_BUS_DEVICE,
328
+ .instance_init = allwinner_a10_dramc_init,
329
+ .instance_size = sizeof(AwA10DramControllerState),
330
+ .class_init = allwinner_a10_dramc_class_init,
331
+};
332
+
333
+static void allwinner_a10_dramc_register(void)
334
+{
335
+ type_register_static(&allwinner_a10_dramc_info);
336
+}
337
+
338
+type_init(allwinner_a10_dramc_register)
339
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
340
index XXXXXXX..XXXXXXX 100644
341
--- a/hw/arm/Kconfig
342
+++ b/hw/arm/Kconfig
343
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
344
select ALLWINNER_A10_PIT
345
select ALLWINNER_A10_PIC
346
select ALLWINNER_A10_CCM
347
+ select ALLWINNER_A10_DRAMC
348
select ALLWINNER_EMAC
349
select SERIAL
350
select UNIMP
351
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
352
index XXXXXXX..XXXXXXX 100644
353
--- a/hw/misc/Kconfig
354
+++ b/hw/misc/Kconfig
355
@@ -XXX,XX +XXX,XX @@ config LASI
356
config ALLWINNER_A10_CCM
357
bool
358
359
+config ALLWINNER_A10_DRAMC
360
+ bool
361
+
362
source macio/Kconfig
363
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
364
index XXXXXXX..XXXXXXX 100644
365
--- a/hw/misc/meson.build
366
+++ b/hw/misc/meson.build
367
@@ -XXX,XX +XXX,XX @@ subdir('macio')
368
softmmu_ss.add(when: 'CONFIG_IVSHMEM_DEVICE', if_true: files('ivshmem.c'))
369
370
softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_CCM', if_true: files('allwinner-a10-ccm.c'))
371
+softmmu_ss.add(when: 'CONFIG_ALLWINNER_A10_DRAMC', if_true: files('allwinner-a10-dramc.c'))
372
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-ccu.c'))
373
specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'))
374
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
375
--
376
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
This patch implements Allwinner TWI/I2C controller emulation. Only
4
master-mode functionality is implemented.
5
6
The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
7
first part enabling the TWI/I2C bus operation.
8
9
Since both Allwinner A10 and H3 use the same module, it is added for
10
both boards.
11
12
Docs are also updated for Cubieboard and Orangepi-PC board to indicate
13
I2C availability.
14
15
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
16
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
17
Message-id: 20221226220303.14420-4-strahinja.p.jankovic@gmail.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
docs/system/arm/cubieboard.rst | 1 +
21
docs/system/arm/orangepi.rst | 1 +
22
include/hw/arm/allwinner-a10.h | 2 +
23
include/hw/arm/allwinner-h3.h | 3 +
24
include/hw/i2c/allwinner-i2c.h | 55 ++++
25
hw/arm/allwinner-a10.c | 8 +
26
hw/arm/allwinner-h3.c | 11 +-
27
hw/i2c/allwinner-i2c.c | 459 +++++++++++++++++++++++++++++++++
28
hw/arm/Kconfig | 2 +
29
hw/i2c/Kconfig | 4 +
30
hw/i2c/meson.build | 1 +
31
hw/i2c/trace-events | 5 +
32
12 files changed, 551 insertions(+), 1 deletion(-)
33
create mode 100644 include/hw/i2c/allwinner-i2c.h
34
create mode 100644 hw/i2c/allwinner-i2c.c
35
36
diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst
37
index XXXXXXX..XXXXXXX 100644
38
--- a/docs/system/arm/cubieboard.rst
39
+++ b/docs/system/arm/cubieboard.rst
40
@@ -XXX,XX +XXX,XX @@ Emulated devices:
41
- SDHCI
42
- USB controller
43
- SATA controller
44
+- TWI (I2C) controller
45
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
46
index XXXXXXX..XXXXXXX 100644
47
--- a/docs/system/arm/orangepi.rst
48
+++ b/docs/system/arm/orangepi.rst
49
@@ -XXX,XX +XXX,XX @@ The Orange Pi PC machine supports the following devices:
50
* Clock Control Unit
51
* System Control module
52
* Security Identifier device
53
+ * TWI (I2C)
54
55
Limitations
56
"""""""""""
57
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
58
index XXXXXXX..XXXXXXX 100644
59
--- a/include/hw/arm/allwinner-a10.h
60
+++ b/include/hw/arm/allwinner-a10.h
61
@@ -XXX,XX +XXX,XX @@
62
#include "hw/rtc/allwinner-rtc.h"
63
#include "hw/misc/allwinner-a10-ccm.h"
64
#include "hw/misc/allwinner-a10-dramc.h"
65
+#include "hw/i2c/allwinner-i2c.h"
66
67
#include "target/arm/cpu.h"
68
#include "qom/object.h"
69
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
70
AwEmacState emac;
71
AllwinnerAHCIState sata;
72
AwSdHostState mmc0;
73
+ AWI2CState i2c0;
74
AwRtcState rtc;
75
MemoryRegion sram_a;
76
EHCISysBusState ehci[AW_A10_NUM_USB];
77
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
78
index XXXXXXX..XXXXXXX 100644
79
--- a/include/hw/arm/allwinner-h3.h
80
+++ b/include/hw/arm/allwinner-h3.h
81
@@ -XXX,XX +XXX,XX @@
82
#include "hw/sd/allwinner-sdhost.h"
83
#include "hw/net/allwinner-sun8i-emac.h"
84
#include "hw/rtc/allwinner-rtc.h"
85
+#include "hw/i2c/allwinner-i2c.h"
86
#include "target/arm/cpu.h"
87
#include "sysemu/block-backend.h"
88
89
@@ -XXX,XX +XXX,XX @@ enum {
90
AW_H3_DEV_UART2,
91
AW_H3_DEV_UART3,
92
AW_H3_DEV_EMAC,
93
+ AW_H3_DEV_TWI0,
94
AW_H3_DEV_DRAMCOM,
95
AW_H3_DEV_DRAMCTL,
96
AW_H3_DEV_DRAMPHY,
97
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
98
AwH3SysCtrlState sysctrl;
99
AwSidState sid;
100
AwSdHostState mmc0;
101
+ AWI2CState i2c0;
102
AwSun8iEmacState emac;
103
AwRtcState rtc;
104
GICState gic;
105
diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
106
new file mode 100644
107
index XXXXXXX..XXXXXXX
108
--- /dev/null
109
+++ b/include/hw/i2c/allwinner-i2c.h
110
@@ -XXX,XX +XXX,XX @@
111
+/*
112
+ * Allwinner I2C Bus Serial Interface registers definition
113
+ *
114
+ * Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
115
+ *
116
+ * This file is derived from IMX I2C controller,
117
+ * by Jean-Christophe DUBOIS .
118
+ *
119
+ * This program is free software; you can redistribute it and/or modify it
120
+ * under the terms of the GNU General Public License as published by the
121
+ * Free Software Foundation; either version 2 of the License, or
122
+ * (at your option) any later version.
123
+ *
124
+ * This program is distributed in the hope that it will be useful, but WITHOUT
125
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
126
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
127
+ * for more details.
128
+ *
129
+ * You should have received a copy of the GNU General Public License along
130
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
131
+ *
132
+ */
133
+
134
+#ifndef ALLWINNER_I2C_H
135
+#define ALLWINNER_I2C_H
136
+
137
+#include "hw/sysbus.h"
138
+#include "qom/object.h"
139
+
140
+#define TYPE_AW_I2C "allwinner.i2c"
141
+OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
142
+
143
+#define AW_I2C_MEM_SIZE 0x24
144
+
145
+struct AWI2CState {
146
+ /*< private >*/
147
+ SysBusDevice parent_obj;
148
+
149
+ /*< public >*/
150
+ MemoryRegion iomem;
151
+ I2CBus *bus;
152
+ qemu_irq irq;
153
+
154
+ uint8_t addr;
155
+ uint8_t xaddr;
156
+ uint8_t data;
157
+ uint8_t cntr;
158
+ uint8_t stat;
159
+ uint8_t ccr;
160
+ uint8_t srst;
161
+ uint8_t efr;
162
+ uint8_t lcr;
163
+};
164
+
165
+#endif /* ALLWINNER_I2C_H */
166
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
167
index XXXXXXX..XXXXXXX 100644
168
--- a/hw/arm/allwinner-a10.c
169
+++ b/hw/arm/allwinner-a10.c
170
@@ -XXX,XX +XXX,XX @@
171
#define AW_A10_OHCI_BASE 0x01c14400
172
#define AW_A10_SATA_BASE 0x01c18000
173
#define AW_A10_RTC_BASE 0x01c20d00
174
+#define AW_A10_I2C0_BASE 0x01c2ac00
175
176
static void aw_a10_init(Object *obj)
177
{
178
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
179
180
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
181
182
+ object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
183
+
184
if (machine_usb(current_machine)) {
185
int i;
186
187
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
188
/* RTC */
189
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
190
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 10);
191
+
192
+ /* I2C */
193
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
194
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, AW_A10_I2C0_BASE);
195
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0, qdev_get_gpio_in(dev, 7));
196
}
197
198
static void aw_a10_class_init(ObjectClass *oc, void *data)
199
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
200
index XXXXXXX..XXXXXXX 100644
201
--- a/hw/arm/allwinner-h3.c
202
+++ b/hw/arm/allwinner-h3.c
203
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
204
[AW_H3_DEV_UART1] = 0x01c28400,
205
[AW_H3_DEV_UART2] = 0x01c28800,
206
[AW_H3_DEV_UART3] = 0x01c28c00,
207
+ [AW_H3_DEV_TWI0] = 0x01c2ac00,
208
[AW_H3_DEV_EMAC] = 0x01c30000,
209
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
210
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
211
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
212
{ "uart1", 0x01c28400, 1 * KiB },
213
{ "uart2", 0x01c28800, 1 * KiB },
214
{ "uart3", 0x01c28c00, 1 * KiB },
215
- { "twi0", 0x01c2ac00, 1 * KiB },
216
{ "twi1", 0x01c2b000, 1 * KiB },
217
{ "twi2", 0x01c2b400, 1 * KiB },
218
{ "scr", 0x01c2c400, 1 * KiB },
219
@@ -XXX,XX +XXX,XX @@ enum {
220
AW_H3_GIC_SPI_UART1 = 1,
221
AW_H3_GIC_SPI_UART2 = 2,
222
AW_H3_GIC_SPI_UART3 = 3,
223
+ AW_H3_GIC_SPI_TWI0 = 6,
224
AW_H3_GIC_SPI_TIMER0 = 18,
225
AW_H3_GIC_SPI_TIMER1 = 19,
226
AW_H3_GIC_SPI_MMC0 = 60,
227
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
228
"ram-size");
229
230
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
231
+
232
+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
233
}
234
235
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
236
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
237
sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
238
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
239
240
+ /* I2C */
241
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c0), &error_fatal);
242
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c0), 0, s->memmap[AW_H3_DEV_TWI0]);
243
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
244
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
245
+
246
/* Unimplemented devices */
247
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
248
create_unimplemented_device(unimplemented[i].device_name,
249
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
250
new file mode 100644
251
index XXXXXXX..XXXXXXX
252
--- /dev/null
253
+++ b/hw/i2c/allwinner-i2c.c
254
@@ -XXX,XX +XXX,XX @@
255
+/*
256
+ * Allwinner I2C Bus Serial Interface Emulation
257
+ *
258
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
259
+ *
260
+ * This file is derived from IMX I2C controller,
261
+ * by Jean-Christophe DUBOIS .
262
+ *
263
+ * This program is free software; you can redistribute it and/or modify it
264
+ * under the terms of the GNU General Public License as published by the
265
+ * Free Software Foundation; either version 2 of the License, or
266
+ * (at your option) any later version.
267
+ *
268
+ * This program is distributed in the hope that it will be useful, but WITHOUT
269
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
270
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
271
+ * for more details.
272
+ *
273
+ * You should have received a copy of the GNU General Public License along
274
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
275
+ *
276
+ * SPDX-License-Identifier: MIT
277
+ */
278
+
279
+#include "qemu/osdep.h"
280
+#include "hw/i2c/allwinner-i2c.h"
281
+#include "hw/irq.h"
282
+#include "migration/vmstate.h"
283
+#include "hw/i2c/i2c.h"
284
+#include "qemu/log.h"
285
+#include "trace.h"
286
+#include "qemu/module.h"
287
+
288
+/* Allwinner I2C memory map */
289
+#define TWI_ADDR_REG 0x00 /* slave address register */
290
+#define TWI_XADDR_REG 0x04 /* extended slave address register */
291
+#define TWI_DATA_REG 0x08 /* data register */
292
+#define TWI_CNTR_REG 0x0c /* control register */
293
+#define TWI_STAT_REG 0x10 /* status register */
294
+#define TWI_CCR_REG 0x14 /* clock control register */
295
+#define TWI_SRST_REG 0x18 /* software reset register */
296
+#define TWI_EFR_REG 0x1c /* enhance feature register */
297
+#define TWI_LCR_REG 0x20 /* line control register */
298
+
299
+/* Used only in slave mode, do not set */
300
+#define TWI_ADDR_RESET 0
301
+#define TWI_XADDR_RESET 0
302
+
303
+/* Data register */
304
+#define TWI_DATA_MASK 0xFF
305
+#define TWI_DATA_RESET 0
306
+
307
+/* Control register */
308
+#define TWI_CNTR_INT_EN (1 << 7)
309
+#define TWI_CNTR_BUS_EN (1 << 6)
310
+#define TWI_CNTR_M_STA (1 << 5)
311
+#define TWI_CNTR_M_STP (1 << 4)
312
+#define TWI_CNTR_INT_FLAG (1 << 3)
313
+#define TWI_CNTR_A_ACK (1 << 2)
314
+#define TWI_CNTR_MASK 0xFC
315
+#define TWI_CNTR_RESET 0
316
+
317
+/* Status register */
318
+#define TWI_STAT_MASK 0xF8
319
+#define TWI_STAT_RESET 0xF8
320
+
321
+/* Clock register */
322
+#define TWI_CCR_CLK_M_MASK 0x78
323
+#define TWI_CCR_CLK_N_MASK 0x07
324
+#define TWI_CCR_MASK 0x7F
325
+#define TWI_CCR_RESET 0
326
+
327
+/* Soft reset */
328
+#define TWI_SRST_MASK 0x01
329
+#define TWI_SRST_RESET 0
330
+
331
+/* Enhance feature */
332
+#define TWI_EFR_MASK 0x03
333
+#define TWI_EFR_RESET 0
334
+
335
+/* Line control */
336
+#define TWI_LCR_SCL_STATE (1 << 5)
337
+#define TWI_LCR_SDA_STATE (1 << 4)
338
+#define TWI_LCR_SCL_CTL (1 << 3)
339
+#define TWI_LCR_SCL_CTL_EN (1 << 2)
340
+#define TWI_LCR_SDA_CTL (1 << 1)
341
+#define TWI_LCR_SDA_CTL_EN (1 << 0)
342
+#define TWI_LCR_MASK 0x3F
343
+#define TWI_LCR_RESET 0x3A
344
+
345
+/* Status value in STAT register is shifted by 3 bits */
346
+#define TWI_STAT_SHIFT 3
347
+#define STAT_FROM_STA(x) ((x) << TWI_STAT_SHIFT)
348
+#define STAT_TO_STA(x) ((x) >> TWI_STAT_SHIFT)
349
+
350
+enum {
351
+ STAT_BUS_ERROR = 0,
352
+ /* Master mode */
353
+ STAT_M_STA_TX,
354
+ STAT_M_RSTA_TX,
355
+ STAT_M_ADDR_WR_ACK,
356
+ STAT_M_ADDR_WR_NACK,
357
+ STAT_M_DATA_TX_ACK,
358
+ STAT_M_DATA_TX_NACK,
359
+ STAT_M_ARB_LOST,
360
+ STAT_M_ADDR_RD_ACK,
361
+ STAT_M_ADDR_RD_NACK,
362
+ STAT_M_DATA_RX_ACK,
363
+ STAT_M_DATA_RX_NACK,
364
+ /* Slave mode */
365
+ STAT_S_ADDR_WR_ACK,
366
+ STAT_S_ARB_LOST_AW_ACK,
367
+ STAT_S_GCA_ACK,
368
+ STAT_S_ARB_LOST_GCA_ACK,
369
+ STAT_S_DATA_RX_SA_ACK,
370
+ STAT_S_DATA_RX_SA_NACK,
371
+ STAT_S_DATA_RX_GCA_ACK,
372
+ STAT_S_DATA_RX_GCA_NACK,
373
+ STAT_S_STP_RSTA,
374
+ STAT_S_ADDR_RD_ACK,
375
+ STAT_S_ARB_LOST_AR_ACK,
376
+ STAT_S_DATA_TX_ACK,
377
+ STAT_S_DATA_TX_NACK,
378
+ STAT_S_LB_TX_ACK,
379
+ /* Master mode, 10-bit */
380
+ STAT_M_2ND_ADDR_WR_ACK,
381
+ STAT_M_2ND_ADDR_WR_NACK,
382
+ /* Idle */
383
+ STAT_IDLE = 0x1f
384
+} TWI_STAT_STA;
385
+
386
+static const char *allwinner_i2c_get_regname(unsigned offset)
387
+{
388
+ switch (offset) {
389
+ case TWI_ADDR_REG:
390
+ return "ADDR";
391
+ case TWI_XADDR_REG:
392
+ return "XADDR";
393
+ case TWI_DATA_REG:
394
+ return "DATA";
395
+ case TWI_CNTR_REG:
396
+ return "CNTR";
397
+ case TWI_STAT_REG:
398
+ return "STAT";
399
+ case TWI_CCR_REG:
400
+ return "CCR";
401
+ case TWI_SRST_REG:
402
+ return "SRST";
403
+ case TWI_EFR_REG:
404
+ return "EFR";
405
+ case TWI_LCR_REG:
406
+ return "LCR";
407
+ default:
408
+ return "[?]";
409
+ }
410
+}
411
+
412
+static inline bool allwinner_i2c_is_reset(AWI2CState *s)
413
+{
414
+ return s->srst & TWI_SRST_MASK;
415
+}
416
+
417
+static inline bool allwinner_i2c_bus_is_enabled(AWI2CState *s)
418
+{
419
+ return s->cntr & TWI_CNTR_BUS_EN;
420
+}
421
+
422
+static inline bool allwinner_i2c_interrupt_is_enabled(AWI2CState *s)
423
+{
424
+ return s->cntr & TWI_CNTR_INT_EN;
425
+}
426
+
427
+static void allwinner_i2c_reset_hold(Object *obj)
428
+{
429
+ AWI2CState *s = AW_I2C(obj);
430
+
431
+ if (STAT_TO_STA(s->stat) != STAT_IDLE) {
432
+ i2c_end_transfer(s->bus);
433
+ }
434
+
435
+ s->addr = TWI_ADDR_RESET;
436
+ s->xaddr = TWI_XADDR_RESET;
437
+ s->data = TWI_DATA_RESET;
438
+ s->cntr = TWI_CNTR_RESET;
439
+ s->stat = TWI_STAT_RESET;
440
+ s->ccr = TWI_CCR_RESET;
441
+ s->srst = TWI_SRST_RESET;
442
+ s->efr = TWI_EFR_RESET;
443
+ s->lcr = TWI_LCR_RESET;
444
+}
445
+
446
+static inline void allwinner_i2c_raise_interrupt(AWI2CState *s)
447
+{
448
+ /*
449
+ * Raise an interrupt if the device is not reset and it is configured
450
+ * to generate some interrupts.
451
+ */
452
+ if (!allwinner_i2c_is_reset(s) && allwinner_i2c_bus_is_enabled(s)) {
453
+ if (STAT_TO_STA(s->stat) != STAT_IDLE) {
454
+ s->cntr |= TWI_CNTR_INT_FLAG;
455
+ if (allwinner_i2c_interrupt_is_enabled(s)) {
456
+ qemu_irq_raise(s->irq);
457
+ }
458
+ }
459
+ }
460
+}
461
+
462
+static uint64_t allwinner_i2c_read(void *opaque, hwaddr offset,
463
+ unsigned size)
464
+{
465
+ uint16_t value;
466
+ AWI2CState *s = AW_I2C(opaque);
467
+
468
+ switch (offset) {
469
+ case TWI_ADDR_REG:
470
+ value = s->addr;
471
+ break;
472
+ case TWI_XADDR_REG:
473
+ value = s->xaddr;
474
+ break;
475
+ case TWI_DATA_REG:
476
+ if ((STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) ||
477
+ (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) ||
478
+ (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK)) {
479
+ /* Get the next byte */
480
+ s->data = i2c_recv(s->bus);
481
+
482
+ if (s->cntr & TWI_CNTR_A_ACK) {
483
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
484
+ } else {
485
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
486
+ }
487
+ allwinner_i2c_raise_interrupt(s);
488
+ }
489
+ value = s->data;
490
+ break;
491
+ case TWI_CNTR_REG:
492
+ value = s->cntr;
493
+ break;
494
+ case TWI_STAT_REG:
495
+ value = s->stat;
496
+ /*
497
+ * If polling when reading then change state to indicate data
498
+ * is available
499
+ */
500
+ if (STAT_TO_STA(s->stat) == STAT_M_ADDR_RD_ACK) {
501
+ if (s->cntr & TWI_CNTR_A_ACK) {
502
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
503
+ } else {
504
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
505
+ }
506
+ allwinner_i2c_raise_interrupt(s);
507
+ }
508
+ break;
509
+ case TWI_CCR_REG:
510
+ value = s->ccr;
511
+ break;
512
+ case TWI_SRST_REG:
513
+ value = s->srst;
514
+ break;
515
+ case TWI_EFR_REG:
516
+ value = s->efr;
517
+ break;
518
+ case TWI_LCR_REG:
519
+ value = s->lcr;
520
+ break;
521
+ default:
522
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
523
+ HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
524
+ value = 0;
525
+ break;
526
+ }
527
+
528
+ trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, value);
529
+
530
+ return (uint64_t)value;
531
+}
532
+
533
+static void allwinner_i2c_write(void *opaque, hwaddr offset,
534
+ uint64_t value, unsigned size)
535
+{
536
+ AWI2CState *s = AW_I2C(opaque);
537
+
538
+ value &= 0xff;
539
+
540
+ trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, value);
541
+
542
+ switch (offset) {
543
+ case TWI_ADDR_REG:
544
+ s->addr = (uint8_t)value;
545
+ break;
546
+ case TWI_XADDR_REG:
547
+ s->xaddr = (uint8_t)value;
548
+ break;
549
+ case TWI_DATA_REG:
550
+ /* If the device is in reset or not enabled, nothing to do */
551
+ if (allwinner_i2c_is_reset(s) || (!allwinner_i2c_bus_is_enabled(s))) {
552
+ break;
553
+ }
554
+
555
+ s->data = value & TWI_DATA_MASK;
556
+
557
+ switch (STAT_TO_STA(s->stat)) {
558
+ case STAT_M_STA_TX:
559
+ case STAT_M_RSTA_TX:
560
+ /* Send address */
561
+ if (i2c_start_transfer(s->bus, extract32(s->data, 1, 7),
562
+ extract32(s->data, 0, 1))) {
563
+ /* If non zero is returned, the address is not valid */
564
+ s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_NACK);
565
+ } else {
566
+ /* Determine if read of write */
567
+ if (extract32(s->data, 0, 1)) {
568
+ s->stat = STAT_FROM_STA(STAT_M_ADDR_RD_ACK);
569
+ } else {
570
+ s->stat = STAT_FROM_STA(STAT_M_ADDR_WR_ACK);
571
+ }
572
+ allwinner_i2c_raise_interrupt(s);
573
+ }
574
+ break;
575
+ case STAT_M_ADDR_WR_ACK:
576
+ case STAT_M_DATA_TX_ACK:
577
+ if (i2c_send(s->bus, s->data)) {
578
+ /* If the target return non zero then end the transfer */
579
+ s->stat = STAT_FROM_STA(STAT_M_DATA_TX_NACK);
580
+ i2c_end_transfer(s->bus);
581
+ } else {
582
+ s->stat = STAT_FROM_STA(STAT_M_DATA_TX_ACK);
583
+ allwinner_i2c_raise_interrupt(s);
584
+ }
585
+ break;
586
+ default:
587
+ break;
588
+ }
589
+ break;
590
+ case TWI_CNTR_REG:
591
+ if (!allwinner_i2c_is_reset(s)) {
592
+ /* Do something only if not in software reset */
593
+ s->cntr = value & TWI_CNTR_MASK;
594
+
595
+ /* Check if start condition should be sent */
596
+ if (s->cntr & TWI_CNTR_M_STA) {
597
+ /* Update status */
598
+ if (STAT_TO_STA(s->stat) == STAT_IDLE) {
599
+ /* Send start condition */
600
+ s->stat = STAT_FROM_STA(STAT_M_STA_TX);
601
+ } else {
602
+ /* Send repeated start condition */
603
+ s->stat = STAT_FROM_STA(STAT_M_RSTA_TX);
604
+ }
605
+ /* Clear start condition */
606
+ s->cntr &= ~TWI_CNTR_M_STA;
607
+ }
608
+ if (s->cntr & TWI_CNTR_M_STP) {
609
+ /* Update status */
610
+ i2c_end_transfer(s->bus);
611
+ s->stat = STAT_FROM_STA(STAT_IDLE);
612
+ s->cntr &= ~TWI_CNTR_M_STP;
613
+ }
614
+ if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
615
+ /* Interrupt flag cleared */
616
+ qemu_irq_lower(s->irq);
617
+ }
618
+ if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
619
+ if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
620
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
621
+ }
622
+ } else {
623
+ if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_NACK) {
624
+ s->stat = STAT_FROM_STA(STAT_M_DATA_RX_ACK);
625
+ }
626
+ }
627
+ allwinner_i2c_raise_interrupt(s);
628
+
629
+ }
630
+ break;
631
+ case TWI_CCR_REG:
632
+ s->ccr = value & TWI_CCR_MASK;
633
+ break;
634
+ case TWI_SRST_REG:
635
+ if (((value & TWI_SRST_MASK) == 0) && (s->srst & TWI_SRST_MASK)) {
636
+ /* Perform reset */
637
+ allwinner_i2c_reset_hold(OBJECT(s));
638
+ }
639
+ s->srst = value & TWI_SRST_MASK;
640
+ break;
641
+ case TWI_EFR_REG:
642
+ s->efr = value & TWI_EFR_MASK;
643
+ break;
644
+ case TWI_LCR_REG:
645
+ s->lcr = value & TWI_LCR_MASK;
646
+ break;
647
+ default:
648
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
649
+ HWADDR_PRIx "\n", TYPE_AW_I2C, __func__, offset);
650
+ break;
651
+ }
652
+}
653
+
654
+static const MemoryRegionOps allwinner_i2c_ops = {
655
+ .read = allwinner_i2c_read,
656
+ .write = allwinner_i2c_write,
657
+ .valid.min_access_size = 1,
658
+ .valid.max_access_size = 4,
659
+ .endianness = DEVICE_NATIVE_ENDIAN,
660
+};
661
+
662
+static const VMStateDescription allwinner_i2c_vmstate = {
663
+ .name = TYPE_AW_I2C,
664
+ .version_id = 1,
665
+ .minimum_version_id = 1,
666
+ .fields = (VMStateField[]) {
667
+ VMSTATE_UINT8(addr, AWI2CState),
668
+ VMSTATE_UINT8(xaddr, AWI2CState),
669
+ VMSTATE_UINT8(data, AWI2CState),
670
+ VMSTATE_UINT8(cntr, AWI2CState),
671
+ VMSTATE_UINT8(ccr, AWI2CState),
672
+ VMSTATE_UINT8(srst, AWI2CState),
673
+ VMSTATE_UINT8(efr, AWI2CState),
674
+ VMSTATE_UINT8(lcr, AWI2CState),
675
+ VMSTATE_END_OF_LIST()
676
+ }
677
+};
678
+
679
+static void allwinner_i2c_realize(DeviceState *dev, Error **errp)
680
+{
681
+ AWI2CState *s = AW_I2C(dev);
682
+
683
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_i2c_ops, s,
684
+ TYPE_AW_I2C, AW_I2C_MEM_SIZE);
685
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
686
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
687
+ s->bus = i2c_init_bus(dev, "i2c");
688
+}
689
+
690
+static void allwinner_i2c_class_init(ObjectClass *klass, void *data)
691
+{
692
+ DeviceClass *dc = DEVICE_CLASS(klass);
693
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
694
+
695
+ rc->phases.hold = allwinner_i2c_reset_hold;
696
+ dc->vmsd = &allwinner_i2c_vmstate;
697
+ dc->realize = allwinner_i2c_realize;
698
+ dc->desc = "Allwinner I2C Controller";
699
+}
700
+
701
+static const TypeInfo allwinner_i2c_type_info = {
702
+ .name = TYPE_AW_I2C,
703
+ .parent = TYPE_SYS_BUS_DEVICE,
704
+ .instance_size = sizeof(AWI2CState),
705
+ .class_init = allwinner_i2c_class_init,
706
+};
707
+
708
+static void allwinner_i2c_register_types(void)
709
+{
710
+ type_register_static(&allwinner_i2c_type_info);
711
+}
712
+
713
+type_init(allwinner_i2c_register_types)
714
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
715
index XXXXXXX..XXXXXXX 100644
716
--- a/hw/arm/Kconfig
717
+++ b/hw/arm/Kconfig
718
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
719
select ALLWINNER_A10_CCM
720
select ALLWINNER_A10_DRAMC
721
select ALLWINNER_EMAC
722
+ select ALLWINNER_I2C
723
select SERIAL
724
select UNIMP
725
726
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_H3
727
bool
728
select ALLWINNER_A10_PIT
729
select ALLWINNER_SUN8I_EMAC
730
+ select ALLWINNER_I2C
731
select SERIAL
732
select ARM_TIMER
733
select ARM_GIC
734
diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
735
index XXXXXXX..XXXXXXX 100644
736
--- a/hw/i2c/Kconfig
737
+++ b/hw/i2c/Kconfig
738
@@ -XXX,XX +XXX,XX @@ config MPC_I2C
739
bool
740
select I2C
741
742
+config ALLWINNER_I2C
743
+ bool
744
+ select I2C
745
+
746
config PCA954X
747
bool
748
select I2C
749
diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build
750
index XXXXXXX..XXXXXXX 100644
751
--- a/hw/i2c/meson.build
752
+++ b/hw/i2c/meson.build
753
@@ -XXX,XX +XXX,XX @@ i2c_ss.add(when: 'CONFIG_BITBANG_I2C', if_true: files('bitbang_i2c.c'))
754
i2c_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_i2c.c'))
755
i2c_ss.add(when: 'CONFIG_IMX_I2C', if_true: files('imx_i2c.c'))
756
i2c_ss.add(when: 'CONFIG_MPC_I2C', if_true: files('mpc_i2c.c'))
757
+i2c_ss.add(when: 'CONFIG_ALLWINNER_I2C', if_true: files('allwinner-i2c.c'))
758
i2c_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('microbit_i2c.c'))
759
i2c_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_smbus.c'))
760
i2c_ss.add(when: 'CONFIG_SMBUS_EEPROM', if_true: files('smbus_eeprom.c'))
761
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
762
index XXXXXXX..XXXXXXX 100644
763
--- a/hw/i2c/trace-events
764
+++ b/hw/i2c/trace-events
765
@@ -XXX,XX +XXX,XX @@ i2c_send_async(uint8_t address, uint8_t data) "send_async(addr:0x%02x) data:0x%0
766
i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
767
i2c_ack(void) ""
768
769
+# allwinner_i2c.c
770
+
771
+allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64
772
+allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value) "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64
773
+
774
# aspeed_i2c.c
775
776
aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x"
777
--
778
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
This patch adds minimal support for AXP-209 PMU.
4
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
5
the chip ID register, reset values for two more registers used by A10
6
U-Boot SPL are covered.
7
8
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
9
Message-id: 20221226220303.14420-5-strahinja.p.jankovic@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/misc/axp209.c | 238 +++++++++++++++++++++++++++++++++++++++++++
14
MAINTAINERS | 2 +
15
hw/misc/Kconfig | 4 +
16
hw/misc/meson.build | 1 +
17
hw/misc/trace-events | 5 +
18
5 files changed, 250 insertions(+)
19
create mode 100644 hw/misc/axp209.c
20
21
diff --git a/hw/misc/axp209.c b/hw/misc/axp209.c
22
new file mode 100644
23
index XXXXXXX..XXXXXXX
24
--- /dev/null
25
+++ b/hw/misc/axp209.c
26
@@ -XXX,XX +XXX,XX @@
27
+/*
28
+ * AXP-209 PMU Emulation
29
+ *
30
+ * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
31
+ *
32
+ * Permission is hereby granted, free of charge, to any person obtaining a
33
+ * copy of this software and associated documentation files (the "Software"),
34
+ * to deal in the Software without restriction, including without limitation
35
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
36
+ * and/or sell copies of the Software, and to permit persons to whom the
37
+ * Software is furnished to do so, subject to the following conditions:
38
+ *
39
+ * The above copyright notice and this permission notice shall be included in
40
+ * all copies or substantial portions of the Software.
41
+ *
42
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
44
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
45
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
46
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
47
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
48
+ * DEALINGS IN THE SOFTWARE.
49
+ *
50
+ * SPDX-License-Identifier: MIT
51
+ */
52
+
53
+#include "qemu/osdep.h"
54
+#include "qemu/log.h"
55
+#include "trace.h"
56
+#include "hw/i2c/i2c.h"
57
+#include "migration/vmstate.h"
58
+
59
+#define TYPE_AXP209_PMU "axp209_pmu"
60
+
61
+#define AXP209(obj) \
62
+ OBJECT_CHECK(AXP209I2CState, (obj), TYPE_AXP209_PMU)
63
+
64
+/* registers */
65
+enum {
66
+ REG_POWER_STATUS = 0x0u,
67
+ REG_OPERATING_MODE,
68
+ REG_OTG_VBUS_STATUS,
69
+ REG_CHIP_VERSION,
70
+ REG_DATA_CACHE_0,
71
+ REG_DATA_CACHE_1,
72
+ REG_DATA_CACHE_2,
73
+ REG_DATA_CACHE_3,
74
+ REG_DATA_CACHE_4,
75
+ REG_DATA_CACHE_5,
76
+ REG_DATA_CACHE_6,
77
+ REG_DATA_CACHE_7,
78
+ REG_DATA_CACHE_8,
79
+ REG_DATA_CACHE_9,
80
+ REG_DATA_CACHE_A,
81
+ REG_DATA_CACHE_B,
82
+ REG_POWER_OUTPUT_CTRL = 0x12u,
83
+ REG_DC_DC2_OUT_V_CTRL = 0x23u,
84
+ REG_DC_DC2_DVS_CTRL = 0x25u,
85
+ REG_DC_DC3_OUT_V_CTRL = 0x27u,
86
+ REG_LDO2_4_OUT_V_CTRL,
87
+ REG_LDO3_OUT_V_CTRL,
88
+ REG_VBUS_CH_MGMT = 0x30u,
89
+ REG_SHUTDOWN_V_CTRL,
90
+ REG_SHUTDOWN_CTRL,
91
+ REG_CHARGE_CTRL_1,
92
+ REG_CHARGE_CTRL_2,
93
+ REG_SPARE_CHARGE_CTRL,
94
+ REG_PEK_KEY_CTRL,
95
+ REG_DC_DC_FREQ_SET,
96
+ REG_CHR_TEMP_TH_SET,
97
+ REG_CHR_HIGH_TEMP_TH_CTRL,
98
+ REG_IPSOUT_WARN_L1,
99
+ REG_IPSOUT_WARN_L2,
100
+ REG_DISCHR_TEMP_TH_SET,
101
+ REG_DISCHR_HIGH_TEMP_TH_CTRL,
102
+ REG_IRQ_BANK_1_CTRL = 0x40u,
103
+ REG_IRQ_BANK_2_CTRL,
104
+ REG_IRQ_BANK_3_CTRL,
105
+ REG_IRQ_BANK_4_CTRL,
106
+ REG_IRQ_BANK_5_CTRL,
107
+ REG_IRQ_BANK_1_STAT = 0x48u,
108
+ REG_IRQ_BANK_2_STAT,
109
+ REG_IRQ_BANK_3_STAT,
110
+ REG_IRQ_BANK_4_STAT,
111
+ REG_IRQ_BANK_5_STAT,
112
+ REG_ADC_ACIN_V_H = 0x56u,
113
+ REG_ADC_ACIN_V_L,
114
+ REG_ADC_ACIN_CURR_H,
115
+ REG_ADC_ACIN_CURR_L,
116
+ REG_ADC_VBUS_V_H,
117
+ REG_ADC_VBUS_V_L,
118
+ REG_ADC_VBUS_CURR_H,
119
+ REG_ADC_VBUS_CURR_L,
120
+ REG_ADC_INT_TEMP_H,
121
+ REG_ADC_INT_TEMP_L,
122
+ REG_ADC_TEMP_SENS_V_H = 0x62u,
123
+ REG_ADC_TEMP_SENS_V_L,
124
+ REG_ADC_BAT_V_H = 0x78u,
125
+ REG_ADC_BAT_V_L,
126
+ REG_ADC_BAT_DISCHR_CURR_H,
127
+ REG_ADC_BAT_DISCHR_CURR_L,
128
+ REG_ADC_BAT_CHR_CURR_H,
129
+ REG_ADC_BAT_CHR_CURR_L,
130
+ REG_ADC_IPSOUT_V_H,
131
+ REG_ADC_IPSOUT_V_L,
132
+ REG_DC_DC_MOD_SEL = 0x80u,
133
+ REG_ADC_EN_1,
134
+ REG_ADC_EN_2,
135
+ REG_ADC_SR_CTRL,
136
+ REG_ADC_IN_RANGE,
137
+ REG_GPIO1_ADC_IRQ_RISING_TH,
138
+ REG_GPIO1_ADC_IRQ_FALLING_TH,
139
+ REG_TIMER_CTRL = 0x8au,
140
+ REG_VBUS_CTRL_MON_SRP,
141
+ REG_OVER_TEMP_SHUTDOWN = 0x8fu,
142
+ REG_GPIO0_FEAT_SET,
143
+ REG_GPIO_OUT_HIGH_SET,
144
+ REG_GPIO1_FEAT_SET,
145
+ REG_GPIO2_FEAT_SET,
146
+ REG_GPIO_SIG_STATE_SET_MON,
147
+ REG_GPIO3_SET,
148
+ REG_COULOMB_CNTR_CTRL = 0xb8u,
149
+ REG_POWER_MEAS_RES,
150
+ NR_REGS
151
+};
152
+
153
+#define AXP209_CHIP_VERSION_ID (0x01)
154
+#define AXP209_DC_DC2_OUT_V_CTRL_RESET (0x16)
155
+#define AXP209_IRQ_BANK_1_CTRL_RESET (0xd8)
156
+
157
+/* A simple I2C slave which returns values of ID or CNT register. */
158
+typedef struct AXP209I2CState {
159
+ /*< private >*/
160
+ I2CSlave i2c;
161
+ /*< public >*/
162
+ uint8_t regs[NR_REGS]; /* peripheral registers */
163
+ uint8_t ptr; /* current register index */
164
+ uint8_t count; /* counter used for tx/rx */
165
+} AXP209I2CState;
166
+
167
+/* Reset all counters and load ID register */
168
+static void axp209_reset_enter(Object *obj, ResetType type)
169
+{
170
+ AXP209I2CState *s = AXP209(obj);
171
+
172
+ memset(s->regs, 0, NR_REGS);
173
+ s->ptr = 0;
174
+ s->count = 0;
175
+ s->regs[REG_CHIP_VERSION] = AXP209_CHIP_VERSION_ID;
176
+ s->regs[REG_DC_DC2_OUT_V_CTRL] = AXP209_DC_DC2_OUT_V_CTRL_RESET;
177
+ s->regs[REG_IRQ_BANK_1_CTRL] = AXP209_IRQ_BANK_1_CTRL_RESET;
178
+}
179
+
180
+/* Handle events from master. */
181
+static int axp209_event(I2CSlave *i2c, enum i2c_event event)
182
+{
183
+ AXP209I2CState *s = AXP209(i2c);
184
+
185
+ s->count = 0;
186
+
187
+ return 0;
188
+}
189
+
190
+/* Called when master requests read */
191
+static uint8_t axp209_rx(I2CSlave *i2c)
192
+{
193
+ AXP209I2CState *s = AXP209(i2c);
194
+ uint8_t ret = 0xff;
195
+
196
+ if (s->ptr < NR_REGS) {
197
+ ret = s->regs[s->ptr++];
198
+ }
199
+
200
+ trace_axp209_rx(s->ptr - 1, ret);
201
+
202
+ return ret;
203
+}
204
+
205
+/*
206
+ * Called when master sends write.
207
+ * Update ptr with byte 0, then perform write with second byte.
208
+ */
209
+static int axp209_tx(I2CSlave *i2c, uint8_t data)
210
+{
211
+ AXP209I2CState *s = AXP209(i2c);
212
+
213
+ if (s->count == 0) {
214
+ /* Store register address */
215
+ s->ptr = data;
216
+ s->count++;
217
+ trace_axp209_select(data);
218
+ } else {
219
+ trace_axp209_tx(s->ptr, data);
220
+ if (s->ptr == REG_DC_DC2_OUT_V_CTRL) {
221
+ s->regs[s->ptr++] = data;
222
+ }
223
+ }
224
+
225
+ return 0;
226
+}
227
+
228
+static const VMStateDescription vmstate_axp209 = {
229
+ .name = TYPE_AXP209_PMU,
230
+ .version_id = 1,
231
+ .fields = (VMStateField[]) {
232
+ VMSTATE_UINT8_ARRAY(regs, AXP209I2CState, NR_REGS),
233
+ VMSTATE_UINT8(count, AXP209I2CState),
234
+ VMSTATE_UINT8(ptr, AXP209I2CState),
235
+ VMSTATE_END_OF_LIST()
236
+ }
237
+};
238
+
239
+static void axp209_class_init(ObjectClass *oc, void *data)
240
+{
241
+ DeviceClass *dc = DEVICE_CLASS(oc);
242
+ I2CSlaveClass *isc = I2C_SLAVE_CLASS(oc);
243
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
244
+
245
+ rc->phases.enter = axp209_reset_enter;
246
+ dc->vmsd = &vmstate_axp209;
247
+ isc->event = axp209_event;
248
+ isc->recv = axp209_rx;
249
+ isc->send = axp209_tx;
250
+}
251
+
252
+static const TypeInfo axp209_info = {
253
+ .name = TYPE_AXP209_PMU,
254
+ .parent = TYPE_I2C_SLAVE,
255
+ .instance_size = sizeof(AXP209I2CState),
256
+ .class_init = axp209_class_init
257
+};
258
+
259
+static void axp209_register_devices(void)
260
+{
261
+ type_register_static(&axp209_info);
262
+}
263
+
264
+type_init(axp209_register_devices);
265
diff --git a/MAINTAINERS b/MAINTAINERS
266
index XXXXXXX..XXXXXXX 100644
267
--- a/MAINTAINERS
268
+++ b/MAINTAINERS
269
@@ -XXX,XX +XXX,XX @@ ARM Machines
270
Allwinner-a10
271
M: Beniamino Galvani <b.galvani@gmail.com>
272
M: Peter Maydell <peter.maydell@linaro.org>
273
+R: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
274
L: qemu-arm@nongnu.org
275
S: Odd Fixes
276
F: hw/*/allwinner*
277
F: include/hw/*/allwinner*
278
F: hw/arm/cubieboard.c
279
F: docs/system/arm/cubieboard.rst
280
+F: hw/misc/axp209.c
281
282
Allwinner-h3
283
M: Niek Linnenbank <nieklinnenbank@gmail.com>
284
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
285
index XXXXXXX..XXXXXXX 100644
286
--- a/hw/misc/Kconfig
287
+++ b/hw/misc/Kconfig
288
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10_CCM
289
config ALLWINNER_A10_DRAMC
290
bool
291
292
+config AXP209_PMU
293
+ bool
294
+ depends on I2C
295
+
296
source macio/Kconfig
297
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
298
index XXXXXXX..XXXXXXX 100644
299
--- a/hw/misc/meson.build
300
+++ b/hw/misc/meson.build
301
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-cpucfg.c'
302
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-dramc.c'))
303
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3-sysctrl.c'))
304
softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sid.c'))
305
+softmmu_ss.add(when: 'CONFIG_AXP209_PMU', if_true: files('axp209.c'))
306
softmmu_ss.add(when: 'CONFIG_REALVIEW', if_true: files('arm_sysctl.c'))
307
softmmu_ss.add(when: 'CONFIG_NSERIES', if_true: files('cbus.c'))
308
softmmu_ss.add(when: 'CONFIG_ECCMEMCTL', if_true: files('eccmemctl.c'))
309
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
310
index XXXXXXX..XXXXXXX 100644
311
--- a/hw/misc/trace-events
312
+++ b/hw/misc/trace-events
313
@@ -XXX,XX +XXX,XX @@ allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%"
314
avr_power_read(uint8_t value) "power_reduc read value:%u"
315
avr_power_write(uint8_t value) "power_reduc write value:%u"
316
317
+# axp209.c
318
+axp209_rx(uint8_t reg, uint8_t data) "Read reg 0x%" PRIx8 " : 0x%" PRIx8
319
+axp209_select(uint8_t reg) "Accessing reg 0x%" PRIx8
320
+axp209_tx(uint8_t reg, uint8_t data) "Write reg 0x%" PRIx8 " : 0x%" PRIx8
321
+
322
# eccmemctl.c
323
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
324
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
325
--
326
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus.
4
5
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20221226220303.14420-6-strahinja.p.jankovic@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/cubieboard.c | 6 ++++++
12
hw/arm/Kconfig | 1 +
13
2 files changed, 7 insertions(+)
14
15
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/cubieboard.c
18
+++ b/hw/arm/cubieboard.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "hw/boards.h"
21
#include "hw/qdev-properties.h"
22
#include "hw/arm/allwinner-a10.h"
23
+#include "hw/i2c/i2c.h"
24
25
static struct arm_boot_info cubieboard_binfo = {
26
.loader_start = AW_A10_SDRAM_BASE,
27
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
28
BlockBackend *blk;
29
BusState *bus;
30
DeviceState *carddev;
31
+ I2CBus *i2c;
32
33
/* BIOS is not supported by this board */
34
if (machine->firmware) {
35
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
36
exit(1);
37
}
38
39
+ /* Connect AXP 209 */
40
+ i2c = I2C_BUS(qdev_get_child_bus(DEVICE(&a10->i2c0), "i2c"));
41
+ i2c_slave_create_simple(i2c, "axp209_pmu", 0x34);
42
+
43
/* Retrieve SD bus */
44
di = drive_get(IF_SD, 0, 0);
45
blk = di ? blk_by_legacy_dinfo(di) : NULL;
46
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/Kconfig
49
+++ b/hw/arm/Kconfig
50
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_A10
51
select ALLWINNER_A10_DRAMC
52
select ALLWINNER_EMAC
53
select ALLWINNER_I2C
54
+ select AXP209_PMU
55
select SERIAL
56
select UNIMP
57
58
--
59
2.34.1
60
61
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
This patch enables copying of SPL from MMC if `-kernel` parameter is not
4
passed when starting QEMU. SPL is copied to SRAM_A.
5
6
The approach is reused from Allwinner H3 implementation.
7
8
Tested with Armbian and custom Yocto image.
9
10
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
11
12
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
13
Message-id: 20221226220303.14420-7-strahinja.p.jankovic@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/allwinner-a10.h | 21 +++++++++++++++++++++
17
hw/arm/allwinner-a10.c | 18 ++++++++++++++++++
18
hw/arm/cubieboard.c | 5 +++++
19
3 files changed, 44 insertions(+)
20
21
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/arm/allwinner-a10.h
24
+++ b/include/hw/arm/allwinner-a10.h
25
@@ -XXX,XX +XXX,XX @@
26
#include "hw/misc/allwinner-a10-ccm.h"
27
#include "hw/misc/allwinner-a10-dramc.h"
28
#include "hw/i2c/allwinner-i2c.h"
29
+#include "sysemu/block-backend.h"
30
31
#include "target/arm/cpu.h"
32
#include "qom/object.h"
33
@@ -XXX,XX +XXX,XX @@ struct AwA10State {
34
OHCISysBusState ohci[AW_A10_NUM_USB];
35
};
36
37
+/**
38
+ * Emulate Boot ROM firmware setup functionality.
39
+ *
40
+ * A real Allwinner A10 SoC contains a Boot ROM
41
+ * which is the first code that runs right after
42
+ * the SoC is powered on. The Boot ROM is responsible
43
+ * for loading user code (e.g. a bootloader) from any
44
+ * of the supported external devices and writing the
45
+ * downloaded code to internal SRAM. After loading the SoC
46
+ * begins executing the code written to SRAM.
47
+ *
48
+ * This function emulates the Boot ROM by copying 32 KiB
49
+ * of data at offset 8 KiB from the given block device and writes it to
50
+ * the start of the first internal SRAM memory.
51
+ *
52
+ * @s: Allwinner A10 state object pointer
53
+ * @blk: Block backend device object pointer
54
+ */
55
+void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk);
56
+
57
#endif
58
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/allwinner-a10.c
61
+++ b/hw/arm/allwinner-a10.c
62
@@ -XXX,XX +XXX,XX @@
63
#include "sysemu/sysemu.h"
64
#include "hw/boards.h"
65
#include "hw/usb/hcd-ohci.h"
66
+#include "hw/loader.h"
67
68
+#define AW_A10_SRAM_A_BASE 0x00000000
69
#define AW_A10_DRAMC_BASE 0x01c01000
70
#define AW_A10_MMC0_BASE 0x01c0f000
71
#define AW_A10_CCM_BASE 0x01c20000
72
@@ -XXX,XX +XXX,XX @@
73
#define AW_A10_RTC_BASE 0x01c20d00
74
#define AW_A10_I2C0_BASE 0x01c2ac00
75
76
+void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
77
+{
78
+ const int64_t rom_size = 32 * KiB;
79
+ g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
80
+
81
+ if (blk_pread(blk, 8 * KiB, rom_size, buffer, 0) < 0) {
82
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
83
+ __func__);
84
+ return;
85
+ }
86
+
87
+ rom_add_blob("allwinner-a10.bootrom", buffer, rom_size,
88
+ rom_size, AW_A10_SRAM_A_BASE,
89
+ NULL, NULL, NULL, NULL, false);
90
+}
91
+
92
static void aw_a10_init(Object *obj)
93
{
94
AwA10State *s = AW_A10(obj);
95
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/hw/arm/cubieboard.c
98
+++ b/hw/arm/cubieboard.c
99
@@ -XXX,XX +XXX,XX @@ static void cubieboard_init(MachineState *machine)
100
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
101
machine->ram);
102
103
+ /* Load target kernel or start using BootROM */
104
+ if (!machine->kernel_filename && blk && blk_is_available(blk)) {
105
+ /* Use Boot ROM to copy data from SD card to SRAM */
106
+ allwinner_a10_bootrom_setup(a10, blk);
107
+ }
108
/* TODO create and connect IDE devices for ide_drive_get() */
109
110
cubieboard_binfo.ram_size = machine->ram_size;
111
--
112
2.34.1
diff view generated by jsdifflib
New patch
1
From: Strahinja Jankovic <strahinjapjankovic@gmail.com>
1
2
3
Cubieboard now can boot directly from SD card, without the need to pass
4
`-kernel` parameter. Update Avocado tests to cover this functionality.
5
6
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
7
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
8
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
9
Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
tests/avocado/boot_linux_console.py | 47 +++++++++++++++++++++++++++++
13
1 file changed, 47 insertions(+)
14
15
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
16
index XXXXXXX..XXXXXXX 100644
17
--- a/tests/avocado/boot_linux_console.py
18
+++ b/tests/avocado/boot_linux_console.py
19
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
20
'sda')
21
# cubieboard's reboot is not functioning; omit reboot test.
22
23
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited')
24
+ def test_arm_cubieboard_openwrt_22_03_2(self):
25
+ """
26
+ :avocado: tags=arch:arm
27
+ :avocado: tags=machine:cubieboard
28
+ :avocado: tags=device:sd
29
+ """
30
+
31
+ # This test download a 7.5 MiB compressed image and expand it
32
+ # to 126 MiB.
33
+ image_url = ('https://downloads.openwrt.org/releases/22.03.2/targets/'
34
+ 'sunxi/cortexa8/openwrt-22.03.2-sunxi-cortexa8-'
35
+ 'cubietech_a10-cubieboard-ext4-sdcard.img.gz')
36
+ image_hash = ('94b5ecbfbc0b3b56276e5146b899eafa'
37
+ '2ac5dc2d08733d6705af9f144f39f554')
38
+ image_path_gz = self.fetch_asset(image_url, asset_hash=image_hash,
39
+ algorithm='sha256')
40
+ image_path = archive.extract(image_path_gz, self.workdir)
41
+ image_pow2ceil_expand(image_path)
42
+
43
+ self.vm.set_console()
44
+ self.vm.add_args('-drive', 'file=' + image_path + ',if=sd,format=raw',
45
+ '-nic', 'user',
46
+ '-no-reboot')
47
+ self.vm.launch()
48
+
49
+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +
50
+ 'usbcore.nousb '
51
+ 'noreboot')
52
+
53
+ self.wait_for_console_pattern('U-Boot SPL')
54
+
55
+ interrupt_interactive_console_until_pattern(
56
+ self, 'Hit any key to stop autoboot:', '=>')
57
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
58
+ kernel_command_line + "'", '=>')
59
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel ...');
60
+
61
+ self.wait_for_console_pattern(
62
+ 'Please press Enter to activate this console.')
63
+
64
+ exec_command_and_wait_for_pattern(self, ' ', 'root@')
65
+
66
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
67
+ 'Allwinner sun4i/sun5i')
68
+ # cubieboard's reboot is not functioning; omit reboot test.
69
+
70
@skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
71
def test_arm_quanta_gsj(self):
72
"""
73
--
74
2.34.1
diff view generated by jsdifflib
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Coverity found that the string return by 'object_get_canonical_path' was not
3
Don't dereference CPUTLBEntryFull until we verify that
4
being freed at two locations in the model (CID 1391294 and CID 1391293) and
4
the page is valid. Move the other user-only info field
5
also that a memset was being called with a value greater than the max of a byte
5
updates after the valid check to match.
6
on the second argument (CID 1391286). This patch corrects this by adding the
7
freeing of the strings and also changing to memset to zero instead on
8
descriptor unaligned errors.
9
6
10
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
7
Cc: qemu-stable@nongnu.org
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1412
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20230104190056.305143-1-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
hw/dma/xlnx-zdma.c | 10 +++++++---
14
target/arm/sve_helper.c | 14 +++++++++-----
18
1 file changed, 7 insertions(+), 3 deletions(-)
15
1 file changed, 9 insertions(+), 5 deletions(-)
19
16
20
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
17
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/dma/xlnx-zdma.c
19
--- a/target/arm/sve_helper.c
23
+++ b/hw/dma/xlnx-zdma.c
20
+++ b/target/arm/sve_helper.c
24
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
21
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
25
qemu_log_mask(LOG_GUEST_ERROR,
22
#ifdef CONFIG_USER_ONLY
26
"zdma: unaligned descriptor at %" PRIx64,
23
flags = probe_access_flags(env, addr, access_type, mmu_idx, nofault,
27
addr);
24
&info->host, retaddr);
28
- memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
25
- memset(&info->attrs, 0, sizeof(info->attrs));
29
+ memset(buf, 0x0, sizeof(XlnxZDMADescr));
26
- /* Require both ANON and MTE; see allocation_tag_mem(). */
30
s->error = true;
27
- info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
28
#else
29
CPUTLBEntryFull *full;
30
flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
31
&info->host, &full, retaddr);
32
- info->attrs = full->attrs;
33
- info->tagged = full->pte_attrs == 0xf0;
34
#endif
35
info->flags = flags;
36
37
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
31
return false;
38
return false;
32
}
39
}
33
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
40
34
RegisterInfo *r = &s->regs_info[addr / 4];
41
+#ifdef CONFIG_USER_ONLY
35
42
+ memset(&info->attrs, 0, sizeof(info->attrs));
36
if (!r->data) {
43
+ /* Require both ANON and MTE; see allocation_tag_mem(). */
37
+ gchar *path = object_get_canonical_path(OBJECT(s));
44
+ info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE);
38
qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
45
+#else
39
- object_get_canonical_path(OBJECT(s)),
46
+ info->attrs = full->attrs;
40
+ path,
47
+ info->tagged = full->pte_attrs == 0xf0;
41
addr);
48
+#endif
42
+ g_free(path);
49
+
43
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
50
/* Ensure that info->host[] is relative to addr, not addr + mem_off. */
44
zdma_ch_imr_update_irq(s);
51
info->host -= mem_off;
45
return 0;
52
return true;
46
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
47
RegisterInfo *r = &s->regs_info[addr / 4];
48
49
if (!r->data) {
50
+ gchar *path = object_get_canonical_path(OBJECT(s));
51
qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
52
- object_get_canonical_path(OBJECT(s)),
53
+ path,
54
addr, value);
55
+ g_free(path);
56
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
57
zdma_ch_imr_update_irq(s);
58
return;
59
--
53
--
60
2.17.1
54
2.34.1
61
55
62
56
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
Since pxa255_init() must map the device in the system memory,
4
there is no point in passing get_system_memory() by argument.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109115316.2235-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/pxa.h | 2 +-
12
hw/arm/gumstix.c | 3 +--
13
hw/arm/pxa2xx.c | 4 +++-
14
hw/arm/tosa.c | 2 +-
15
4 files changed, 6 insertions(+), 5 deletions(-)
16
17
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/pxa.h
20
+++ b/include/hw/arm/pxa.h
21
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
22
23
PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
24
const char *revision);
25
-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
26
+PXA2xxState *pxa255_init(unsigned int sdram_size);
27
28
#endif /* PXA_H */
29
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/gumstix.c
32
+++ b/hw/arm/gumstix.c
33
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
34
{
35
PXA2xxState *cpu;
36
DriveInfo *dinfo;
37
- MemoryRegion *address_space_mem = get_system_memory();
38
39
uint32_t connex_rom = 0x01000000;
40
uint32_t connex_ram = 0x04000000;
41
42
- cpu = pxa255_init(address_space_mem, connex_ram);
43
+ cpu = pxa255_init(connex_ram);
44
45
dinfo = drive_get(IF_PFLASH, 0, 0);
46
if (!dinfo && !qtest_enabled()) {
47
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/pxa2xx.c
50
+++ b/hw/arm/pxa2xx.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "qemu/error-report.h"
53
#include "qemu/module.h"
54
#include "qapi/error.h"
55
+#include "exec/address-spaces.h"
56
#include "cpu.h"
57
#include "hw/sysbus.h"
58
#include "migration/vmstate.h"
59
@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
60
}
61
62
/* Initialise a PXA255 integrated chip (ARM based core). */
63
-PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
64
+PXA2xxState *pxa255_init(unsigned int sdram_size)
65
{
66
+ MemoryRegion *address_space = get_system_memory();
67
PXA2xxState *s;
68
int i;
69
DriveInfo *dinfo;
70
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
71
index XXXXXXX..XXXXXXX 100644
72
--- a/hw/arm/tosa.c
73
+++ b/hw/arm/tosa.c
74
@@ -XXX,XX +XXX,XX @@ static void tosa_init(MachineState *machine)
75
TC6393xbState *tmio;
76
DeviceState *scp0, *scp1;
77
78
- mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);
79
+ mpu = pxa255_init(tosa_binfo.ram_size);
80
81
memory_region_init_rom(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal);
82
memory_region_add_subregion(address_space_mem, 0, rom);
83
--
84
2.34.1
85
86
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to flatview_translate(); all its
3
callers now have attrs available.
4
2
3
Since pxa270_init() must map the device in the system memory,
4
there is no point in passing get_system_memory() by argument.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109115316.2235-3-philmd@linaro.org
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
9
---
10
---
10
include/exec/memory.h | 7 ++++---
11
include/hw/arm/pxa.h | 3 +--
11
exec.c | 17 +++++++++--------
12
hw/arm/gumstix.c | 3 +--
12
2 files changed, 13 insertions(+), 11 deletions(-)
13
hw/arm/mainstone.c | 10 ++++------
14
hw/arm/pxa2xx.c | 4 ++--
15
hw/arm/spitz.c | 6 ++----
16
hw/arm/z2.c | 3 +--
17
6 files changed, 11 insertions(+), 18 deletions(-)
13
18
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
19
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
21
--- a/include/hw/arm/pxa.h
17
+++ b/include/exec/memory.h
22
+++ b/include/hw/arm/pxa.h
18
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
23
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
19
*/
24
20
MemoryRegion *flatview_translate(FlatView *fv,
25
# define PA_FMT            "0x%08lx"
21
hwaddr addr, hwaddr *xlat,
26
22
- hwaddr *len, bool is_write);
27
-PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
23
+ hwaddr *len, bool is_write,
28
- const char *revision);
24
+ MemTxAttrs attrs);
29
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision);
25
30
PXA2xxState *pxa255_init(unsigned int sdram_size);
26
static inline MemoryRegion *address_space_translate(AddressSpace *as,
31
27
hwaddr addr, hwaddr *xlat,
32
#endif /* PXA_H */
28
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
33
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
29
MemTxAttrs attrs)
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/gumstix.c
36
+++ b/hw/arm/gumstix.c
37
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
30
{
38
{
31
return flatview_translate(address_space_to_flatview(as),
39
PXA2xxState *cpu;
32
- addr, xlat, len, is_write);
40
DriveInfo *dinfo;
33
+ addr, xlat, len, is_write, attrs);
41
- MemoryRegion *address_space_mem = get_system_memory();
42
43
uint32_t verdex_rom = 0x02000000;
44
uint32_t verdex_ram = 0x10000000;
45
46
- cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);
47
+ cpu = pxa270_init(verdex_ram, machine->cpu_type);
48
49
dinfo = drive_get(IF_PFLASH, 0, 0);
50
if (!dinfo && !qtest_enabled()) {
51
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/mainstone.c
54
+++ b/hw/arm/mainstone.c
55
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info mainstone_binfo = {
56
.ram_size = 0x04000000,
57
};
58
59
-static void mainstone_common_init(MemoryRegion *address_space_mem,
60
- MachineState *machine,
61
+static void mainstone_common_init(MachineState *machine,
62
enum mainstone_model_e model, int arm_id)
63
{
64
uint32_t sector_len = 256 * 1024;
65
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
66
MemoryRegion *rom = g_new(MemoryRegion, 1);
67
68
/* Setup CPU & memory */
69
- mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,
70
- machine->cpu_type);
71
+ mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
72
memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
73
&error_fatal);
74
- memory_region_add_subregion(address_space_mem, 0, rom);
75
+ memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
76
77
/* There are two 32MiB flash devices on the board */
78
for (i = 0; i < 2; i ++) {
79
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MemoryRegion *address_space_mem,
80
81
static void mainstone_init(MachineState *machine)
82
{
83
- mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
84
+ mainstone_common_init(machine, mainstone, 0x196);
34
}
85
}
35
86
36
/* address_space_access_valid: check for validity of accessing an address
87
static void mainstone2_machine_init(MachineClass *mc)
37
@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
88
diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
38
rcu_read_lock();
39
fv = address_space_to_flatview(as);
40
l = len;
41
- mr = flatview_translate(fv, addr, &addr1, &l, false);
42
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
43
if (len == l && memory_access_is_direct(mr, false)) {
44
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
45
memcpy(buf, ptr, len);
46
diff --git a/exec.c b/exec.c
47
index XXXXXXX..XXXXXXX 100644
89
index XXXXXXX..XXXXXXX 100644
48
--- a/exec.c
90
--- a/hw/arm/pxa2xx.c
49
+++ b/exec.c
91
+++ b/hw/arm/pxa2xx.c
50
@@ -XXX,XX +XXX,XX @@ iotlb_fail:
92
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_reset(void *opaque, int line, int level)
51
93
}
52
/* Called from RCU critical section */
94
53
MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
95
/* Initialise a PXA270 integrated chip (ARM based core). */
54
- hwaddr *plen, bool is_write)
96
-PXA2xxState *pxa270_init(MemoryRegion *address_space,
55
+ hwaddr *plen, bool is_write,
97
- unsigned int sdram_size, const char *cpu_type)
56
+ MemTxAttrs attrs)
98
+PXA2xxState *pxa270_init(unsigned int sdram_size, const char *cpu_type)
57
{
99
{
58
MemoryRegion *mr;
100
+ MemoryRegion *address_space = get_system_memory();
59
MemoryRegionSection section;
101
PXA2xxState *s;
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
102
int i;
61
}
103
DriveInfo *dinfo;
62
104
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
63
l = len;
105
index XXXXXXX..XXXXXXX 100644
64
- mr = flatview_translate(fv, addr, &addr1, &l, true);
106
--- a/hw/arm/spitz.c
65
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
107
+++ b/hw/arm/spitz.c
66
}
108
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
67
109
SpitzMachineState *sms = SPITZ_MACHINE(machine);
68
return result;
110
enum spitz_model_e model = smc->model;
69
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
111
PXA2xxState *mpu;
70
MemTxResult result = MEMTX_OK;
112
- MemoryRegion *address_space_mem = get_system_memory();
71
113
MemoryRegion *rom = g_new(MemoryRegion, 1);
72
l = len;
114
73
- mr = flatview_translate(fv, addr, &addr1, &l, true);
115
/* Setup CPU & memory */
74
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
116
- mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
75
result = flatview_write_continue(fv, addr, attrs, buf, len,
117
- machine->cpu_type);
76
addr1, l, mr);
118
+ mpu = pxa270_init(spitz_binfo.ram_size, machine->cpu_type);
77
119
sms->mpu = mpu;
78
@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
120
79
}
121
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
80
122
81
l = len;
123
memory_region_init_rom(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal);
82
- mr = flatview_translate(fv, addr, &addr1, &l, false);
124
- memory_region_add_subregion(address_space_mem, 0, rom);
83
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
125
+ memory_region_add_subregion(get_system_memory(), 0, rom);
84
}
126
85
127
/* Setup peripherals */
86
return result;
128
spitz_keyboard_register(mpu);
87
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
129
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
88
MemoryRegion *mr;
130
index XXXXXXX..XXXXXXX 100644
89
131
--- a/hw/arm/z2.c
90
l = len;
132
+++ b/hw/arm/z2.c
91
- mr = flatview_translate(fv, addr, &addr1, &l, false);
133
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
92
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
134
93
return flatview_read_continue(fv, addr, attrs, buf, len,
135
static void z2_init(MachineState *machine)
94
addr1, l, mr);
136
{
95
}
137
- MemoryRegion *address_space_mem = get_system_memory();
96
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
138
uint32_t sector_len = 0x10000;
97
139
PXA2xxState *mpu;
98
while (len > 0) {
140
DriveInfo *dinfo;
99
l = len;
141
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
100
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
142
DeviceState *wm;
101
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
143
102
if (!memory_access_is_direct(mr, is_write)) {
144
/* Setup CPU & memory */
103
l = memory_access_size(mr, l, addr);
145
- mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);
104
if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
146
+ mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
105
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
147
106
148
dinfo = drive_get(IF_PFLASH, 0, 0);
107
len = target_len;
149
if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
108
this_mr = flatview_translate(fv, addr, &xlat,
109
- &len, is_write);
110
+ &len, is_write, attrs);
111
if (this_mr != mr || xlat != base + done) {
112
return done;
113
}
114
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
115
l = len;
116
rcu_read_lock();
117
fv = address_space_to_flatview(as);
118
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
119
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
120
121
if (!memory_access_is_direct(mr, is_write)) {
122
if (atomic_xchg(&bounce.in_use, true)) {
123
--
150
--
124
2.17.1
151
2.34.1
125
152
126
153
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to address_space_translate_iommu().
3
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add definitions for RAM / Flash / Flash blocksize.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-4-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
8
---
11
---
9
exec.c | 8 +++++---
12
hw/arm/collie.c | 16 ++++++++++------
10
1 file changed, 5 insertions(+), 3 deletions(-)
13
1 file changed, 10 insertions(+), 6 deletions(-)
11
14
12
diff --git a/exec.c b/exec.c
15
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/exec.c
17
--- a/hw/arm/collie.c
15
+++ b/exec.c
18
+++ b/hw/arm/collie.c
16
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
19
@@ -XXX,XX +XXX,XX @@
17
* @is_write: whether the translation operation is for write
20
#include "cpu.h"
18
* @is_mmio: whether this can be MMIO, set true if it can
21
#include "qom/object.h"
19
* @target_as: the address space targeted by the IOMMU
22
20
+ * @attrs: transaction attributes
23
+#define RAM_SIZE (512 * MiB)
21
*
24
+#define FLASH_SIZE (32 * MiB)
22
* This function is called from RCU critical section. It is the common
25
+#define FLASH_SECTOR_SIZE (64 * KiB)
23
* part of flatview_do_translate and address_space_translate_cached.
26
+
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
27
struct CollieMachineState {
25
hwaddr *page_mask_out,
28
MachineState parent;
26
bool is_write,
29
27
bool is_mmio,
30
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(CollieMachineState, COLLIE_MACHINE)
28
- AddressSpace **target_as)
31
29
+ AddressSpace **target_as,
32
static struct arm_boot_info collie_binfo = {
30
+ MemTxAttrs attrs)
33
.loader_start = SA_SDCS0,
31
{
34
- .ram_size = 0x20000000,
32
MemoryRegionSection *section;
35
+ .ram_size = RAM_SIZE,
33
hwaddr page_mask = (hwaddr)-1;
36
};
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
37
35
return address_space_translate_iommu(iommu_mr, xlat,
38
static void collie_init(MachineState *machine)
36
plen_out, page_mask_out,
39
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
37
is_write, is_mmio,
40
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
38
- target_as);
41
39
+ target_as, attrs);
42
dinfo = drive_get(IF_PFLASH, 0, 0);
40
}
43
- pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000,
41
if (page_mask_out) {
44
+ pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
42
/* Not behind an IOMMU, use default page size. */
45
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
43
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
46
- 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
44
47
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
45
section = address_space_translate_iommu(iommu_mr, xlat, plen,
48
46
NULL, is_write, true,
49
dinfo = drive_get(IF_PFLASH, 0, 1);
47
- &target_as);
50
- pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000,
48
+ &target_as, attrs);
51
+ pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
49
return section.mr;
52
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
53
- 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0);
54
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
55
56
sysbus_create_simple("scoop", 0x40800000, NULL);
57
58
@@ -XXX,XX +XXX,XX @@ static void collie_machine_class_init(ObjectClass *oc, void *data)
59
mc->init = collie_init;
60
mc->ignore_memory_transaction_failures = true;
61
mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110");
62
- mc->default_ram_size = 0x20000000;
63
+ mc->default_ram_size = RAM_SIZE;
64
mc->default_ram_id = "strongarm.sdram";
50
}
65
}
51
66
52
--
67
--
53
2.17.1
68
2.34.1
54
69
55
70
diff view generated by jsdifflib
1
Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
and friends.
3
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230109115316.2235-5-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
7
---
7
---
8
include/migration/vmstate.h | 3 +++
8
hw/arm/collie.c | 17 +++++++----------
9
1 file changed, 3 insertions(+)
9
1 file changed, 7 insertions(+), 10 deletions(-)
10
10
11
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
11
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/migration/vmstate.h
13
--- a/hw/arm/collie.c
14
+++ b/include/migration/vmstate.h
14
+++ b/hw/arm/collie.c
15
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
15
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info collie_binfo = {
16
#define VMSTATE_BOOL_ARRAY(_f, _s, _n) \
16
17
VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
17
static void collie_init(MachineState *machine)
18
18
{
19
+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num) \
19
- DriveInfo *dinfo;
20
+ VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
20
MachineClass *mc = MACHINE_GET_CLASS(machine);
21
+
21
CollieMachineState *cms = COLLIE_MACHINE(machine);
22
#define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v) \
22
23
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
23
@@ -XXX,XX +XXX,XX @@ static void collie_init(MachineState *machine)
24
25
memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram);
26
27
- dinfo = drive_get(IF_PFLASH, 0, 0);
28
- pflash_cfi01_register(SA_CS0, "collie.fl1", FLASH_SIZE,
29
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
30
- FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
31
-
32
- dinfo = drive_get(IF_PFLASH, 0, 1);
33
- pflash_cfi01_register(SA_CS1, "collie.fl2", FLASH_SIZE,
34
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
35
- FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
36
+ for (unsigned i = 0; i < 2; i++) {
37
+ DriveInfo *dinfo = drive_get(IF_PFLASH, 0, i);
38
+ pflash_cfi01_register(i ? SA_CS1 : SA_CS0,
39
+ i ? "collie.fl2" : "collie.fl1", FLASH_SIZE,
40
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
41
+ FLASH_SECTOR_SIZE, 4, 0x00, 0x00, 0x00, 0x00, 0);
42
+ }
43
44
sysbus_create_simple("scoop", 0x40800000, NULL);
24
45
25
--
46
--
26
2.17.1
47
2.34.1
27
48
28
49
diff view generated by jsdifflib
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
acpi_data_push uses g_array_set_size to resize the memory size. If there
3
Add a comment describing the Connex uses a Numonyx RC28F128J3F75
4
is no enough contiguous memory, the address will be changed. So previous
4
flash, and the Verdex uses a Micron RC28F256P30TFA.
5
pointer could not be used any more. It must update the pointer and use
6
the new one.
7
5
8
Also, previous codes wrongly use le32 conversion of iort->node_offset
6
Correct the Verdex machine description (we model the 'Pro' board).
9
for subsequent computations that will result incorrect value if host is
10
not litlle endian. So use the non-converted one instead.
11
7
12
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
10
Message-id: 20230109115316.2235-6-philmd@linaro.org
11
Message-Id: <20200223231044.8003-3-philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
13
---
17
hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
14
hw/arm/gumstix.c | 6 ++++--
18
1 file changed, 15 insertions(+), 5 deletions(-)
15
1 file changed, 4 insertions(+), 2 deletions(-)
19
16
20
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
17
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt-acpi-build.c
19
--- a/hw/arm/gumstix.c
23
+++ b/hw/arm/virt-acpi-build.c
20
+++ b/hw/arm/gumstix.c
24
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
21
@@ -XXX,XX +XXX,XX @@
25
AcpiIortItsGroup *its;
22
* Contributions after 2012-01-13 are licensed under the terms of the
26
AcpiIortTable *iort;
23
* GNU GPL, version 2 or (at your option) any later version.
27
AcpiIortSmmu3 *smmu;
24
*/
28
- size_t node_size, iort_length, smmu_offset = 0;
25
-
29
+ size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
26
+
30
AcpiIortRC *rc;
27
/*
31
28
* Example usage:
32
iort = acpi_data_push(table_data, sizeof(*iort));
29
*
33
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
30
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
34
31
exit(1);
35
iort_length = sizeof(*iort);
36
iort->node_count = cpu_to_le32(nb_nodes);
37
- iort->node_offset = cpu_to_le32(sizeof(*iort));
38
+ /*
39
+ * Use a copy in case table_data->data moves during acpi_data_push
40
+ * operations.
41
+ */
42
+ iort_node_offset = sizeof(*iort);
43
+ iort->node_offset = cpu_to_le32(iort_node_offset);
44
45
/* ITS group node */
46
node_size = sizeof(*its) + sizeof(uint32_t);
47
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
48
int irq = vms->irqmap[VIRT_SMMU];
49
50
/* SMMUv3 node */
51
- smmu_offset = iort->node_offset + node_size;
52
+ smmu_offset = iort_node_offset + node_size;
53
node_size = sizeof(*smmu) + sizeof(*idmap);
54
iort_length += node_size;
55
smmu = acpi_data_push(table_data, node_size);
56
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
57
idmap->id_count = cpu_to_le32(0xFFFF);
58
idmap->output_base = 0;
59
/* output IORT node is the ITS group node (the first node) */
60
- idmap->output_reference = cpu_to_le32(iort->node_offset);
61
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
62
}
32
}
63
33
64
/* Root Complex Node */
34
+ /* Numonyx RC28F128J3F75 */
65
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
35
if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
66
idmap->output_reference = cpu_to_le32(smmu_offset);
36
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
67
} else {
37
sector_len, 2, 0, 0, 0, 0, 0)) {
68
/* output IORT node is the ITS group node (the first node) */
38
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
69
- idmap->output_reference = cpu_to_le32(iort->node_offset);
39
exit(1);
70
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
71
}
40
}
72
41
73
+ /*
42
+ /* Micron RC28F256P30TFA */
74
+ * Update the pointer address in case table_data->data moves during above
43
if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
75
+ * acpi_data_push operations.
44
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
76
+ */
45
sector_len, 2, 0, 0, 0, 0, 0)) {
77
+ iort = (AcpiIortTable *)(table_data->data + iort_start);
46
@@ -XXX,XX +XXX,XX @@ static void verdex_class_init(ObjectClass *oc, void *data)
78
iort->length = cpu_to_le32(iort_length);
47
{
79
48
MachineClass *mc = MACHINE_CLASS(oc);
80
build_header(linker, table_data, (void *)(table_data->data + iort_start),
49
50
- mc->desc = "Gumstix Verdex (PXA270)";
51
+ mc->desc = "Gumstix Verdex Pro XL6P COMs (PXA270)";
52
mc->init = verdex_init;
53
mc->ignore_memory_transaction_failures = true;
54
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
81
--
55
--
82
2.17.1
56
2.34.1
83
57
84
58
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
add MemTxAttrs as an argument to address_space_map().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add definitions for RAM / Flash / Flash blocksize.
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-7-philmd@linaro.org
10
Message-Id: <20200223231044.8003-3-philmd@redhat.com>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
10
---
12
---
11
include/exec/memory.h | 3 ++-
13
hw/arm/gumstix.c | 27 ++++++++++++++-------------
12
include/sysemu/dma.h | 3 ++-
14
1 file changed, 14 insertions(+), 13 deletions(-)
13
exec.c | 6 ++++--
14
target/ppc/mmu-hash64.c | 3 ++-
15
4 files changed, 10 insertions(+), 5 deletions(-)
16
15
17
diff --git a/include/exec/memory.h b/include/exec/memory.h
16
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/memory.h
18
--- a/hw/arm/gumstix.c
20
+++ b/include/exec/memory.h
19
+++ b/hw/arm/gumstix.c
21
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
20
@@ -XXX,XX +XXX,XX @@
22
* @addr: address within that address space
23
* @plen: pointer to length of buffer; updated on return
24
* @is_write: indicates the transfer direction
25
+ * @attrs: memory attributes
26
*/
21
*/
27
void *address_space_map(AddressSpace *as, hwaddr addr,
22
28
- hwaddr *plen, bool is_write);
23
#include "qemu/osdep.h"
29
+ hwaddr *plen, bool is_write, MemTxAttrs attrs);
24
+#include "qemu/units.h"
30
25
#include "qemu/error-report.h"
31
/* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
26
#include "hw/arm/pxa.h"
32
*
27
#include "net/net.h"
33
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
28
@@ -XXX,XX +XXX,XX @@
34
index XXXXXXX..XXXXXXX 100644
29
#include "sysemu/qtest.h"
35
--- a/include/sysemu/dma.h
30
#include "cpu.h"
36
+++ b/include/sysemu/dma.h
31
37
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
32
-static const int sector_len = 128 * 1024;
38
hwaddr xlen = *len;
33
+#define CONNEX_FLASH_SIZE (16 * MiB)
39
void *p;
34
+#define CONNEX_RAM_SIZE (64 * MiB)
40
35
+
41
- p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
36
+#define VERDEX_FLASH_SIZE (32 * MiB)
42
+ p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
37
+#define VERDEX_RAM_SIZE (256 * MiB)
43
+ MEMTXATTRS_UNSPECIFIED);
38
+
44
*len = xlen;
39
+#define FLASH_SECTOR_SIZE (128 * KiB)
45
return p;
40
46
}
41
static void connex_init(MachineState *machine)
47
diff --git a/exec.c b/exec.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/exec.c
50
+++ b/exec.c
51
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
52
void *address_space_map(AddressSpace *as,
53
hwaddr addr,
54
hwaddr *plen,
55
- bool is_write)
56
+ bool is_write,
57
+ MemTxAttrs attrs)
58
{
42
{
59
hwaddr len = *plen;
43
PXA2xxState *cpu;
60
hwaddr l, xlat;
44
DriveInfo *dinfo;
61
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
45
62
hwaddr *plen,
46
- uint32_t connex_rom = 0x01000000;
63
int is_write)
47
- uint32_t connex_ram = 0x04000000;
64
{
48
-
65
- return address_space_map(&address_space_memory, addr, plen, is_write);
49
- cpu = pxa255_init(connex_ram);
66
+ return address_space_map(&address_space_memory, addr, plen, is_write,
50
+ cpu = pxa255_init(CONNEX_RAM_SIZE);
67
+ MEMTXATTRS_UNSPECIFIED);
51
68
}
52
dinfo = drive_get(IF_PFLASH, 0, 0);
69
53
if (!dinfo && !qtest_enabled()) {
70
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
54
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
71
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/ppc/mmu-hash64.c
74
+++ b/target/ppc/mmu-hash64.c
75
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
76
return NULL;
77
}
55
}
78
56
79
- hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
57
/* Numonyx RC28F128J3F75 */
80
+ hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
58
- if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom,
81
+ MEMTXATTRS_UNSPECIFIED);
59
+ if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
82
if (plen < (n * HASH_PTE_SIZE_64)) {
60
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
83
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
61
- sector_len, 2, 0, 0, 0, 0, 0)) {
62
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
63
error_report("Error registering flash memory");
64
exit(1);
65
}
66
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
67
PXA2xxState *cpu;
68
DriveInfo *dinfo;
69
70
- uint32_t verdex_rom = 0x02000000;
71
- uint32_t verdex_ram = 0x10000000;
72
-
73
- cpu = pxa270_init(verdex_ram, machine->cpu_type);
74
+ cpu = pxa270_init(VERDEX_RAM_SIZE, machine->cpu_type);
75
76
dinfo = drive_get(IF_PFLASH, 0, 0);
77
if (!dinfo && !qtest_enabled()) {
78
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
79
}
80
81
/* Micron RC28F256P30TFA */
82
- if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom,
83
+ if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
84
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
85
- sector_len, 2, 0, 0, 0, 0, 0)) {
86
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
87
error_report("Error registering flash memory");
88
exit(1);
84
}
89
}
85
--
90
--
86
2.17.1
91
2.34.1
87
92
88
93
diff view generated by jsdifflib
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
3
IEC binary prefixes ease code review: the unit is explicit.
4
initialize global capability variables. If we call kvm_init_irq_routing in
5
GIC realize function, previous allocated memory will leak.
6
4
7
Fix this by deleting the unnecessary call.
5
Add the FLASH_SECTOR_SIZE definition.
8
6
9
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
9
Message-id: 20230109115316.2235-8-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
hw/intc/arm_gic_kvm.c | 1 -
12
hw/arm/mainstone.c | 18 ++++++++++--------
15
hw/intc/arm_gicv3_kvm.c | 1 -
13
1 file changed, 10 insertions(+), 8 deletions(-)
16
2 files changed, 2 deletions(-)
17
14
18
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
15
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/arm_gic_kvm.c
17
--- a/hw/arm/mainstone.c
21
+++ b/hw/intc/arm_gic_kvm.c
18
+++ b/hw/arm/mainstone.c
22
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
19
@@ -XXX,XX +XXX,XX @@
23
20
* GNU GPL, version 2 or (at your option) any later version.
24
if (kvm_has_gsi_routing()) {
21
*/
25
/* set up irq routing */
22
#include "qemu/osdep.h"
26
- kvm_init_irq_routing(kvm_state);
23
+#include "qemu/units.h"
27
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
24
#include "qemu/error-report.h"
28
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
25
#include "qapi/error.h"
29
}
26
#include "hw/arm/pxa.h"
30
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
27
@@ -XXX,XX +XXX,XX @@ static const struct keymap map[0xE0] = {
31
index XXXXXXX..XXXXXXX 100644
28
32
--- a/hw/intc/arm_gicv3_kvm.c
29
enum mainstone_model_e { mainstone };
33
+++ b/hw/intc/arm_gicv3_kvm.c
30
34
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
31
-#define MAINSTONE_RAM    0x04000000
35
32
-#define MAINSTONE_ROM    0x00800000
36
if (kvm_has_gsi_routing()) {
33
-#define MAINSTONE_FLASH    0x02000000
37
/* set up irq routing */
34
+#define MAINSTONE_RAM_SIZE (64 * MiB)
38
- kvm_init_irq_routing(kvm_state);
35
+#define MAINSTONE_ROM_SIZE (8 * MiB)
39
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
36
+#define MAINSTONE_FLASH_SIZE (32 * MiB)
40
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
37
38
static struct arm_boot_info mainstone_binfo = {
39
.loader_start = PXA2XX_SDRAM_BASE,
40
- .ram_size = 0x04000000,
41
+ .ram_size = MAINSTONE_RAM_SIZE,
42
};
43
44
+#define FLASH_SECTOR_SIZE (256 * KiB)
45
+
46
static void mainstone_common_init(MachineState *machine,
47
enum mainstone_model_e model, int arm_id)
48
{
49
- uint32_t sector_len = 256 * 1024;
50
hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
51
PXA2xxState *mpu;
52
DeviceState *mst_irq;
53
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
54
55
/* Setup CPU & memory */
56
mpu = pxa270_init(mainstone_binfo.ram_size, machine->cpu_type);
57
- memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
58
+ memory_region_init_rom(rom, NULL, "mainstone.rom", MAINSTONE_ROM_SIZE,
59
&error_fatal);
60
memory_region_add_subregion(get_system_memory(), 0x00000000, rom);
61
62
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
63
dinfo = drive_get(IF_PFLASH, 0, i);
64
if (!pflash_cfi01_register(mainstone_flash_base[i],
65
i ? "mainstone.flash1" : "mainstone.flash0",
66
- MAINSTONE_FLASH,
67
+ MAINSTONE_FLASH_SIZE,
68
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
69
- sector_len, 4, 0, 0, 0, 0, 0)) {
70
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
71
error_report("Error registering flash memory");
72
exit(1);
41
}
73
}
42
--
74
--
43
2.17.1
75
2.34.1
44
76
45
77
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to flatview_do_translate().
3
2
3
IEC binary prefixes ease code review: the unit is explicit.
4
5
Add the FLASH_SECTOR_SIZE definition.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-9-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
8
---
11
---
9
exec.c | 9 ++++++---
12
hw/arm/musicpal.c | 9 ++++++---
10
1 file changed, 6 insertions(+), 3 deletions(-)
13
1 file changed, 6 insertions(+), 3 deletions(-)
11
14
12
diff --git a/exec.c b/exec.c
15
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/exec.c
17
--- a/hw/arm/musicpal.c
15
+++ b/exec.c
18
+++ b/hw/arm/musicpal.c
16
@@ -XXX,XX +XXX,XX @@ unassigned:
19
@@ -XXX,XX +XXX,XX @@
17
* @is_write: whether the translation operation is for write
18
* @is_mmio: whether this can be MMIO, set true if it can
19
* @target_as: the address space targeted by the IOMMU
20
+ * @attrs: memory transaction attributes
21
*
22
* This function is called from RCU critical section
23
*/
20
*/
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
21
25
hwaddr *page_mask_out,
22
#include "qemu/osdep.h"
26
bool is_write,
23
+#include "qemu/units.h"
27
bool is_mmio,
24
#include "qapi/error.h"
28
- AddressSpace **target_as)
25
#include "cpu.h"
29
+ AddressSpace **target_as,
26
#include "hw/sysbus.h"
30
+ MemTxAttrs attrs)
27
@@ -XXX,XX +XXX,XX @@ static const TypeInfo musicpal_key_info = {
31
{
28
.class_init = musicpal_key_class_init,
32
MemoryRegionSection *section;
29
};
33
IOMMUMemoryRegion *iommu_mr;
30
34
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
31
+#define FLASH_SECTOR_SIZE (64 * KiB)
35
* but page mask.
32
+
36
*/
33
static struct arm_boot_info musicpal_binfo = {
37
section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
34
.loader_start = 0x0,
38
- NULL, &page_mask, is_write, false, &as);
35
.board_id = 0x20e,
39
+ NULL, &page_mask, is_write, false, &as,
36
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
40
+ attrs);
37
BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
41
38
42
/* Illegal translation */
39
flash_size = blk_getlength(blk);
43
if (section.mr == &io_mem_unassigned) {
40
- if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
44
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
41
- flash_size != 32*1024*1024) {
45
42
+ if (flash_size != 8 * MiB && flash_size != 16 * MiB &&
46
/* This can be MMIO, so setup MMIO bit. */
43
+ flash_size != 32 * MiB) {
47
section = flatview_do_translate(fv, addr, xlat, plen, NULL,
44
error_report("Invalid flash image size");
48
- is_write, true, &as);
45
exit(1);
49
+ is_write, true, &as, attrs);
46
}
50
mr = section.mr;
47
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
51
48
*/
52
if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
49
pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX,
50
"musicpal.flash", flash_size,
51
- blk, 0x10000,
52
+ blk, FLASH_SECTOR_SIZE,
53
MP_FLASH_SIZE_MAX / flash_size,
54
2, 0x00BF, 0x236D, 0x0000, 0x0000,
55
0x5555, 0x2AAA, 0);
53
--
56
--
54
2.17.1
57
2.34.1
55
58
56
59
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
The total_ram_v1/total_ram_v2 definitions were never used.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20230109115316.2235-10-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/omap_sx1.c | 2 --
11
1 file changed, 2 deletions(-)
12
13
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/omap_sx1.c
16
+++ b/hw/arm/omap_sx1.c
17
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
18
#define flash0_size    (16 * 1024 * 1024)
19
#define flash1_size    ( 8 * 1024 * 1024)
20
#define flash2_size    (32 * 1024 * 1024)
21
-#define total_ram_v1    (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
22
-#define total_ram_v2    (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
23
24
static struct arm_boot_info sx1_binfo = {
25
.loader_start = OMAP_EMIFF_BASE,
26
--
27
2.34.1
28
29
diff view generated by jsdifflib
1
From: Jan Kiszka <jan.kiszka@siemens.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
There was a nasty flip in identifying which register group an access is
3
IEC binary prefixes ease code review: the unit is explicit.
4
targeting. The issue caused spuriously raised priorities of the guest
5
when handing CPUs over in the Jailhouse hypervisor.
6
4
7
Cc: qemu-stable@nongnu.org
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
7
Message-id: 20230109115316.2235-11-philmd@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
10
hw/arm/omap_sx1.c | 33 +++++++++++++++++----------------
14
1 file changed, 6 insertions(+), 6 deletions(-)
11
1 file changed, 17 insertions(+), 16 deletions(-)
15
12
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
13
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_cpuif.c
15
--- a/hw/arm/omap_sx1.c
19
+++ b/hw/intc/arm_gicv3_cpuif.c
16
+++ b/hw/arm/omap_sx1.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
17
@@ -XXX,XX +XXX,XX @@
21
{
18
* with this program; if not, see <http://www.gnu.org/licenses/>.
22
GICv3CPUState *cs = icc_cs_from_env(env);
19
*/
23
int regno = ri->opc2 & 3;
20
#include "qemu/osdep.h"
24
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
21
+#include "qemu/units.h"
25
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
22
#include "qapi/error.h"
26
uint64_t value = cs->ich_apr[grp][regno];
23
#include "ui/console.h"
27
24
#include "hw/arm/omap.h"
28
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
25
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps static_ops = {
29
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
26
.endianness = DEVICE_NATIVE_ENDIAN,
30
{
27
};
31
GICv3CPUState *cs = icc_cs_from_env(env);
28
32
int regno = ri->opc2 & 3;
29
-#define sdram_size    0x02000000
33
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
30
-#define sector_size    (128 * 1024)
34
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
31
-#define flash0_size    (16 * 1024 * 1024)
35
32
-#define flash1_size    ( 8 * 1024 * 1024)
36
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
33
-#define flash2_size    (32 * 1024 * 1024)
37
34
+#define SDRAM_SIZE (32 * MiB)
38
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
35
+#define SECTOR_SIZE (128 * KiB)
39
uint64_t value;
36
+#define FLASH0_SIZE (16 * MiB)
40
37
+#define FLASH1_SIZE (8 * MiB)
41
int regno = ri->opc2 & 3;
38
+#define FLASH2_SIZE (32 * MiB)
42
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
39
43
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
40
static struct arm_boot_info sx1_binfo = {
44
41
.loader_start = OMAP_EMIFF_BASE,
45
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
42
- .ram_size = sdram_size,
46
return icv_ap_read(env, ri);
43
+ .ram_size = SDRAM_SIZE,
47
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
44
.board_id = 0x265,
48
GICv3CPUState *cs = icc_cs_from_env(env);
45
};
49
46
50
int regno = ri->opc2 & 3;
47
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
51
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
48
static uint32_t cs3val = 0x00001139;
52
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
49
DriveInfo *dinfo;
53
50
int fl_idx;
54
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
51
- uint32_t flash_size = flash0_size;
55
icv_ap_write(env, ri, value);
52
+ uint32_t flash_size = FLASH0_SIZE;
56
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
53
57
{
54
if (machine->ram_size != mc->default_ram_size) {
58
GICv3CPUState *cs = icc_cs_from_env(env);
55
char *sz = size_to_str(mc->default_ram_size);
59
int regno = ri->opc2 & 3;
56
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
60
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
57
}
61
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
58
62
uint64_t value;
59
if (version == 2) {
63
60
- flash_size = flash2_size;
64
value = cs->ich_apr[grp][regno];
61
+ flash_size = FLASH2_SIZE;
65
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
62
}
66
{
63
67
GICv3CPUState *cs = icc_cs_from_env(env);
64
memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
68
int regno = ri->opc2 & 3;
65
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
69
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
66
if (!pflash_cfi01_register(OMAP_CS0_BASE,
70
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
67
"omap_sx1.flash0-1", flash_size,
71
68
blk_by_legacy_dinfo(dinfo),
72
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
69
- sector_size, 4, 0, 0, 0, 0, 0)) {
70
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
71
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
72
fl_idx);
73
}
74
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
75
(dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
76
MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
77
memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
78
- flash1_size, &error_fatal);
79
+ FLASH1_SIZE, &error_fatal);
80
memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
81
82
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
83
- "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
84
+ "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
85
memory_region_add_subregion(address_space,
86
- OMAP_CS1_BASE + flash1_size, &cs[1]);
87
+ OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
88
89
if (!pflash_cfi01_register(OMAP_CS1_BASE,
90
- "omap_sx1.flash1-1", flash1_size,
91
+ "omap_sx1.flash1-1", FLASH1_SIZE,
92
blk_by_legacy_dinfo(dinfo),
93
- sector_size, 4, 0, 0, 0, 0, 0)) {
94
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
95
fprintf(stderr, "qemu: Error registering flash memory %d.\n",
96
fl_idx);
97
}
98
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
99
mc->init = sx1_init_v2;
100
mc->ignore_memory_transaction_failures = true;
101
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
102
- mc->default_ram_size = sdram_size;
103
+ mc->default_ram_size = SDRAM_SIZE;
104
mc->default_ram_id = "omap1.dram";
105
}
106
107
@@ -XXX,XX +XXX,XX @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
108
mc->init = sx1_init_v1;
109
mc->ignore_memory_transaction_failures = true;
110
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
111
- mc->default_ram_size = sdram_size;
112
+ mc->default_ram_size = SDRAM_SIZE;
113
mc->default_ram_id = "omap1.dram";
114
}
73
115
74
--
116
--
75
2.17.1
117
2.34.1
76
118
77
119
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to memory_region_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
2
6
The callsite in flatview_access_valid() is part of a recursive
3
IEC binary prefixes ease code review: the unit is explicit.
7
loop flatview_access_valid() -> memory_region_access_valid() ->
8
subpage_accepts() -> flatview_access_valid(); we make it pass
9
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
10
have plumbed an attrs parameter through the rest of the loop
11
and we can add an attrs parameter to flatview_access_valid().
12
4
5
Add the FLASH_SECTOR_SIZE definition.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109115316.2235-12-philmd@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
17
---
11
---
18
include/exec/memory-internal.h | 3 ++-
12
hw/arm/z2.c | 6 ++++--
19
exec.c | 4 +++-
13
1 file changed, 4 insertions(+), 2 deletions(-)
20
hw/s390x/s390-pci-inst.c | 3 ++-
21
memory.c | 7 ++++---
22
4 files changed, 11 insertions(+), 6 deletions(-)
23
14
24
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
15
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/include/exec/memory-internal.h
17
--- a/hw/arm/z2.c
27
+++ b/include/exec/memory-internal.h
18
+++ b/hw/arm/z2.c
28
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
19
@@ -XXX,XX +XXX,XX @@
29
extern const MemoryRegionOps unassigned_mem_ops;
20
*/
30
21
31
bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
22
#include "qemu/osdep.h"
32
- unsigned size, bool is_write);
23
+#include "qemu/units.h"
33
+ unsigned size, bool is_write,
24
#include "hw/arm/pxa.h"
34
+ MemTxAttrs attrs);
25
#include "hw/arm/boot.h"
35
26
#include "hw/i2c/i2c.h"
36
void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
27
@@ -XXX,XX +XXX,XX @@ static const TypeInfo aer915_info = {
37
AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
28
.class_init = aer915_class_init,
38
diff --git a/exec.c b/exec.c
29
};
39
index XXXXXXX..XXXXXXX 100644
30
40
--- a/exec.c
31
+#define FLASH_SECTOR_SIZE (64 * KiB)
41
+++ b/exec.c
32
+
42
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
33
static void z2_init(MachineState *machine)
43
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
44
if (!memory_access_is_direct(mr, is_write)) {
45
l = memory_access_size(mr, l, addr);
46
- if (!memory_region_access_valid(mr, xlat, l, is_write)) {
47
+ /* When our callers all have attrs we'll pass them through here */
48
+ if (!memory_region_access_valid(mr, xlat, l, is_write,
49
+ MEMTXATTRS_UNSPECIFIED)) {
50
return false;
51
}
52
}
53
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/s390x/s390-pci-inst.c
56
+++ b/hw/s390x/s390-pci-inst.c
57
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
58
mr = s390_get_subregion(mr, offset, len);
59
offset -= mr->addr;
60
61
- if (!memory_region_access_valid(mr, offset, len, true)) {
62
+ if (!memory_region_access_valid(mr, offset, len, true,
63
+ MEMTXATTRS_UNSPECIFIED)) {
64
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
65
return 0;
66
}
67
diff --git a/memory.c b/memory.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/memory.c
70
+++ b/memory.c
71
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
72
bool memory_region_access_valid(MemoryRegion *mr,
73
hwaddr addr,
74
unsigned size,
75
- bool is_write)
76
+ bool is_write,
77
+ MemTxAttrs attrs)
78
{
34
{
79
int access_size_min, access_size_max;
35
- uint32_t sector_len = 0x10000;
80
int access_size, i;
36
PXA2xxState *mpu;
81
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
37
DriveInfo *dinfo;
82
{
38
void *z2_lcd;
83
MemTxResult r;
39
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
84
40
dinfo = drive_get(IF_PFLASH, 0, 0);
85
- if (!memory_region_access_valid(mr, addr, size, false)) {
41
if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
86
+ if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
42
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
87
*pval = unassigned_mem_read(mr, addr, size);
43
- sector_len, 4, 0, 0, 0, 0, 0)) {
88
return MEMTX_DECODE_ERROR;
44
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
89
}
45
error_report("Error registering flash memory");
90
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
46
exit(1);
91
unsigned size,
92
MemTxAttrs attrs)
93
{
94
- if (!memory_region_access_valid(mr, addr, size, true)) {
95
+ if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
96
unassigned_mem_write(mr, addr, data, size);
97
return MEMTX_DECODE_ERROR;
98
}
47
}
99
--
48
--
100
2.17.1
49
2.34.1
101
50
102
51
diff view generated by jsdifflib
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
When QEMU is started with following CLI
3
Upon introduction in commit b8433303fb ("Set proper device-width
4
-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
4
for vexpress flash"), ve_pflash_cfi01_register() was calling
5
it crashes with abort at
5
qdev_init_nofail() which can not fail. This call was later
6
accel/kvm/kvm-all.c:2164:
6
converted with a script to use &error_fatal, still unable to
7
KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
7
fail. Remove the unreachable code.
8
8
9
Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
arm_gicv3_icc_reset() where the later is called by CPU reset
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
reset callback.
11
Message-id: 20230109115316.2235-13-philmd@linaro.org
12
13
However commit:
14
3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
15
broke CPU reset callback registration in case
16
17
arm_load_kernel()
18
...
19
if (!info->kernel_filename || info->firmware_loaded)
20
21
branch is taken, i.e. it's sufficient to provide a firmware
22
or do not provide kernel on CLI to skip cpu reset callback
23
registration, where before offending commit the callback
24
has been registered unconditionally.
25
26
Fix it by registering the callback right at the beginning of
27
arm_load_kernel() unconditionally instead of doing it at the end.
28
29
NOTE:
30
we probably should eliminate that dependency anyways as well as
31
separate arch CPU reset parts from arm_load_kernel() into CPU
32
itself, but that refactoring that I probably would have to do
33
anyways later for CPU hotplug to work.
34
35
Reported-by: Auger Eric <eric.auger@redhat.com>
36
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Tested-by: Eric Auger <eric.auger@redhat.com>
39
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
13
---
43
hw/arm/boot.c | 18 +++++++++---------
14
hw/arm/vexpress.c | 10 +---------
44
1 file changed, 9 insertions(+), 9 deletions(-)
15
1 file changed, 1 insertion(+), 9 deletions(-)
45
16
46
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
47
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/boot.c
19
--- a/hw/arm/vexpress.c
49
+++ b/hw/arm/boot.c
20
+++ b/hw/arm/vexpress.c
50
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
21
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
51
static const ARMInsnFixup *primary_loader;
22
dinfo = drive_get(IF_PFLASH, 0, 0);
52
AddressSpace *as = arm_boot_address_space(cpu, info);
23
pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0",
53
24
dinfo);
54
+ /* CPU objects (unlike devices) are not automatically reset on system
25
- if (!pflash0) {
55
+ * reset, so we must always register a handler to do so. If we're
26
- error_report("vexpress: error registering flash 0");
56
+ * actually loading a kernel, the handler is also responsible for
27
- exit(1);
57
+ * arranging that we start it correctly.
28
- }
58
+ */
29
59
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
30
if (map[VE_NORFLASHALIAS] != -1) {
60
+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
31
/* Map flash 0 as an alias into low memory */
61
+ }
32
@@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine)
62
+
63
/* The board code is not supposed to set secure_board_setup unless
64
* running its code in secure mode is actually possible, and KVM
65
* doesn't support secure.
66
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
67
ARM_CPU(cs)->env.boot_info = info;
68
}
33
}
69
34
70
- /* CPU objects (unlike devices) are not automatically reset on system
35
dinfo = drive_get(IF_PFLASH, 0, 1);
71
- * reset, so we must always register a handler to do so. If we're
36
- if (!ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1",
72
- * actually loading a kernel, the handler is also responsible for
37
- dinfo)) {
73
- * arranging that we start it correctly.
38
- error_report("vexpress: error registering flash 1");
74
- */
39
- exit(1);
75
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
76
- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
77
- }
40
- }
78
-
41
+ ve_pflash_cfi01_register(map[VE_NORFLASH1], "vexpress.flash1", dinfo);
79
if (!info->skip_dtb_autoload && have_dtb(info)) {
42
80
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
43
sram_size = 0x2000000;
81
exit(1);
44
memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size,
82
--
45
--
83
2.17.1
46
2.34.1
84
47
85
48
diff view generated by jsdifflib
1
The FRECPX instructions should (like most other floating point operations)
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
honour the FPCR.FZ bit which specifies whether input denormals should
3
be flushed to zero (or FZ16 for the half-precision version).
4
We forgot to implement this, which doesn't affect the results (since
5
the calculation doesn't actually care about the mantissa bits) but did
6
mean we were failing to set the FPSR.IDC bit.
7
2
3
Since its QOM'ification in commit 368a354f02 ("pflash_cfi0x:
4
QOMified") the pflash_cfi01_register() function does not fail.
5
6
This call was later converted with a script to use &error_fatal,
7
still unable to fail. Remove the unreachable code.
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230109115316.2235-14-philmd@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
11
---
13
---
12
target/arm/helper-a64.c | 6 ++++++
14
hw/arm/gumstix.c | 18 ++++++------------
13
1 file changed, 6 insertions(+)
15
hw/arm/mainstone.c | 13 +++++--------
16
hw/arm/omap_sx1.c | 22 ++++++++--------------
17
hw/arm/versatilepb.c | 6 ++----
18
hw/arm/z2.c | 9 +++------
19
5 files changed, 24 insertions(+), 44 deletions(-)
14
20
15
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
21
diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c
16
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.c
23
--- a/hw/arm/gumstix.c
18
+++ b/target/arm/helper-a64.c
24
+++ b/hw/arm/gumstix.c
19
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
25
@@ -XXX,XX +XXX,XX @@ static void connex_init(MachineState *machine)
20
return nan;
21
}
26
}
22
27
23
+ a = float16_squash_input_denormal(a, fpst);
28
/* Numonyx RC28F128J3F75 */
24
+
29
- if (!pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
25
val16 = float16_val(a);
30
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
26
sbit = 0x8000 & val16;
31
- FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
27
exp = extract32(val16, 10, 5);
32
- error_report("Error registering flash memory");
28
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
33
- exit(1);
29
return nan;
34
- }
35
+ pflash_cfi01_register(0x00000000, "connext.rom", CONNEX_FLASH_SIZE,
36
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
37
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
38
39
/* Interrupt line of NIC is connected to GPIO line 36 */
40
smc91c111_init(&nd_table[0], 0x04000300,
41
@@ -XXX,XX +XXX,XX @@ static void verdex_init(MachineState *machine)
30
}
42
}
31
43
32
+ a = float32_squash_input_denormal(a, fpst);
44
/* Micron RC28F256P30TFA */
33
+
45
- if (!pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
34
val32 = float32_val(a);
46
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
35
sbit = 0x80000000ULL & val32;
47
- FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0)) {
36
exp = extract32(val32, 23, 8);
48
- error_report("Error registering flash memory");
37
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
49
- exit(1);
38
return nan;
50
- }
51
+ pflash_cfi01_register(0x00000000, "verdex.rom", VERDEX_FLASH_SIZE,
52
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
53
+ FLASH_SECTOR_SIZE, 2, 0, 0, 0, 0, 0);
54
55
/* Interrupt line of NIC is connected to GPIO line 99 */
56
smc91c111_init(&nd_table[0], 0x04000300,
57
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
58
index XXXXXXX..XXXXXXX 100644
59
--- a/hw/arm/mainstone.c
60
+++ b/hw/arm/mainstone.c
61
@@ -XXX,XX +XXX,XX @@ static void mainstone_common_init(MachineState *machine,
62
/* There are two 32MiB flash devices on the board */
63
for (i = 0; i < 2; i ++) {
64
dinfo = drive_get(IF_PFLASH, 0, i);
65
- if (!pflash_cfi01_register(mainstone_flash_base[i],
66
- i ? "mainstone.flash1" : "mainstone.flash0",
67
- MAINSTONE_FLASH_SIZE,
68
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
69
- FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
70
- error_report("Error registering flash memory");
71
- exit(1);
72
- }
73
+ pflash_cfi01_register(mainstone_flash_base[i],
74
+ i ? "mainstone.flash1" : "mainstone.flash0",
75
+ MAINSTONE_FLASH_SIZE,
76
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
77
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
39
}
78
}
40
79
41
+ a = float64_squash_input_denormal(a, fpst);
80
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
42
+
81
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
43
val64 = float64_val(a);
82
index XXXXXXX..XXXXXXX 100644
44
sbit = 0x8000000000000000ULL & val64;
83
--- a/hw/arm/omap_sx1.c
45
exp = extract64(float64_val(a), 52, 11);
84
+++ b/hw/arm/omap_sx1.c
85
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
86
87
fl_idx = 0;
88
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
89
- if (!pflash_cfi01_register(OMAP_CS0_BASE,
90
- "omap_sx1.flash0-1", flash_size,
91
- blk_by_legacy_dinfo(dinfo),
92
- SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
93
- fprintf(stderr, "qemu: Error registering flash memory %d.\n",
94
- fl_idx);
95
- }
96
+ pflash_cfi01_register(OMAP_CS0_BASE,
97
+ "omap_sx1.flash0-1", flash_size,
98
+ blk_by_legacy_dinfo(dinfo),
99
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
100
fl_idx++;
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static void sx1_init(MachineState *machine, const int version)
104
memory_region_add_subregion(address_space,
105
OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
106
107
- if (!pflash_cfi01_register(OMAP_CS1_BASE,
108
- "omap_sx1.flash1-1", FLASH1_SIZE,
109
- blk_by_legacy_dinfo(dinfo),
110
- SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
111
- fprintf(stderr, "qemu: Error registering flash memory %d.\n",
112
- fl_idx);
113
- }
114
+ pflash_cfi01_register(OMAP_CS1_BASE,
115
+ "omap_sx1.flash1-1", FLASH1_SIZE,
116
+ blk_by_legacy_dinfo(dinfo),
117
+ SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
118
fl_idx++;
119
} else {
120
memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
121
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/hw/arm/versatilepb.c
124
+++ b/hw/arm/versatilepb.c
125
@@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id)
126
/* 0x34000000 NOR Flash */
127
128
dinfo = drive_get(IF_PFLASH, 0, 0);
129
- if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
130
+ pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash",
131
VERSATILE_FLASH_SIZE,
132
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
133
VERSATILE_FLASH_SECT_SIZE,
134
- 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
135
- fprintf(stderr, "qemu: Error registering flash memory.\n");
136
- }
137
+ 4, 0x0089, 0x0018, 0x0000, 0x0, 0);
138
139
versatile_binfo.ram_size = machine->ram_size;
140
versatile_binfo.board_id = board_id;
141
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
142
index XXXXXXX..XXXXXXX 100644
143
--- a/hw/arm/z2.c
144
+++ b/hw/arm/z2.c
145
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
146
mpu = pxa270_init(z2_binfo.ram_size, machine->cpu_type);
147
148
dinfo = drive_get(IF_PFLASH, 0, 0);
149
- if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
150
- dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
151
- FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0)) {
152
- error_report("Error registering flash memory");
153
- exit(1);
154
- }
155
+ pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE,
156
+ dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
157
+ FLASH_SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
158
159
/* setup keypad */
160
pxa27x_register_keypad(mpu->kp, map, 0x100);
46
--
161
--
47
2.17.1
162
2.34.1
48
163
49
164
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
1
2
3
To avoid forward-declaring PXA2xxI2CState, declare
4
PXA2XX_I2C before its use in pxa2xx_i2c_init() prototype.
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109140306.23161-2-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/pxa.h | 6 +++---
12
1 file changed, 3 insertions(+), 3 deletions(-)
13
14
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/arm/pxa.h
17
+++ b/include/hw/arm/pxa.h
18
@@ -XXX,XX +XXX,XX @@ void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
19
const struct keymap *map, int size);
20
21
/* pxa2xx.c */
22
-typedef struct PXA2xxI2CState PXA2xxI2CState;
23
+#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
24
+OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
25
+
26
PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
27
qemu_irq irq, uint32_t page_size);
28
I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
29
30
-#define TYPE_PXA2XX_I2C "pxa2xx_i2c"
31
typedef struct PXA2xxI2SState PXA2xxI2SState;
32
-OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C)
33
34
#define TYPE_PXA2XX_FIR "pxa2xx-fir"
35
OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR)
36
--
37
2.34.1
38
39
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to address_space_get_iotlb_entry().
3
2
3
Add a local 'struct omap_gpif_s *' variable to improve readability.
4
(This also eases next commit conversion).
5
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230109140306.23161-3-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
8
---
10
---
9
include/exec/memory.h | 2 +-
11
hw/gpio/omap_gpio.c | 3 ++-
10
exec.c | 2 +-
12
1 file changed, 2 insertions(+), 1 deletion(-)
11
hw/virtio/vhost.c | 3 ++-
12
3 files changed, 4 insertions(+), 3 deletions(-)
13
13
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
14
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
16
--- a/hw/gpio/omap_gpio.c
17
+++ b/include/exec/memory.h
17
+++ b/hw/gpio/omap_gpio.c
18
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
18
@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
19
* entry. Should be called from an RCU critical section.
19
/* General-Purpose I/O of OMAP1 */
20
*/
20
static void omap_gpio_set(void *opaque, int line, int level)
21
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
22
- bool is_write);
23
+ bool is_write, MemTxAttrs attrs);
24
25
/* address_space_translate: translate an address range into an address space
26
* into a MemoryRegion and an address range into that section. Should be
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
32
33
/* Called from RCU critical section */
34
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
35
- bool is_write)
36
+ bool is_write, MemTxAttrs attrs)
37
{
21
{
38
MemoryRegionSection section;
22
- struct omap_gpio_s *s = &((struct omap_gpif_s *) opaque)->omap1;
39
hwaddr xlat, page_mask;
23
+ struct omap_gpif_s *p = opaque;
40
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
24
+ struct omap_gpio_s *s = &p->omap1;
41
index XXXXXXX..XXXXXXX 100644
25
uint16_t prev = s->inputs;
42
--- a/hw/virtio/vhost.c
26
43
+++ b/hw/virtio/vhost.c
27
if (level)
44
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
45
trace_vhost_iotlb_miss(dev, 1);
46
47
iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
48
- iova, write);
49
+ iova, write,
50
+ MEMTXATTRS_UNSPECIFIED);
51
if (iotlb.target_as != NULL) {
52
ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
53
&uaddr, &len);
54
--
28
--
55
2.17.1
29
2.34.1
56
30
57
31
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230109140306.23161-4-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
10
---
7
---
11
include/exec/exec-all.h | 5 +++--
8
hw/arm/omap1.c | 115 ++++++++++++++++++--------------------
12
accel/tcg/translate-all.c | 2 +-
9
hw/arm/omap2.c | 40 ++++++-------
13
exec.c | 2 +-
10
hw/arm/omap_sx1.c | 2 +-
14
target/xtensa/op_helper.c | 3 ++-
11
hw/arm/palm.c | 2 +-
15
4 files changed, 7 insertions(+), 5 deletions(-)
12
hw/char/omap_uart.c | 7 +--
13
hw/display/omap_dss.c | 15 +++--
14
hw/display/omap_lcdc.c | 9 ++-
15
hw/dma/omap_dma.c | 15 +++--
16
hw/gpio/omap_gpio.c | 15 +++--
17
hw/intc/omap_intc.c | 12 ++--
18
hw/misc/omap_gpmc.c | 12 ++--
19
hw/misc/omap_l4.c | 7 +--
20
hw/misc/omap_sdrc.c | 7 +--
21
hw/misc/omap_tap.c | 5 +-
22
hw/sd/omap_mmc.c | 9 ++-
23
hw/ssi/omap_spi.c | 7 +--
24
hw/timer/omap_gptimer.c | 22 ++++----
25
hw/timer/omap_synctimer.c | 4 +-
26
18 files changed, 142 insertions(+), 163 deletions(-)
16
27
17
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
28
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
18
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/exec-all.h
30
--- a/hw/arm/omap1.c
20
+++ b/include/exec/exec-all.h
31
+++ b/hw/arm/omap1.c
21
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
32
@@ -XXX,XX +XXX,XX @@ static void omap_timer_fire(void *opaque)
22
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
33
23
hwaddr paddr, int prot,
34
static void omap_timer_tick(void *opaque)
24
int mmu_idx, target_ulong size);
35
{
25
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
36
- struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
26
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
37
+ struct omap_mpu_timer_s *timer = opaque;
27
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
38
28
uintptr_t retaddr);
39
omap_timer_sync(timer);
29
#else
40
omap_timer_fire(timer);
30
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
41
@@ -XXX,XX +XXX,XX @@ static void omap_timer_tick(void *opaque)
31
uint16_t idxmap)
42
32
{
43
static void omap_timer_clk_update(void *opaque, int line, int on)
33
}
44
{
34
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
45
- struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
35
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
46
+ struct omap_mpu_timer_s *timer = opaque;
36
+ MemTxAttrs attrs)
47
37
{
48
omap_timer_sync(timer);
38
}
49
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
39
#endif
50
@@ -XXX,XX +XXX,XX @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
40
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
51
static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
41
index XXXXXXX..XXXXXXX 100644
52
unsigned size)
42
--- a/accel/tcg/translate-all.c
53
{
43
+++ b/accel/tcg/translate-all.c
54
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
44
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
55
+ struct omap_mpu_timer_s *s = opaque;
45
}
56
46
57
if (size != 4) {
47
#if !defined(CONFIG_USER_ONLY)
58
return omap_badwidth_read32(opaque, addr);
48
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
59
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
49
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
60
static void omap_mpu_timer_write(void *opaque, hwaddr addr,
50
{
61
uint64_t value, unsigned size)
51
ram_addr_t ram_addr;
62
{
52
MemoryRegion *mr;
63
- struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
53
diff --git a/exec.c b/exec.c
64
+ struct omap_mpu_timer_s *s = opaque;
54
index XXXXXXX..XXXXXXX 100644
65
55
--- a/exec.c
66
if (size != 4) {
56
+++ b/exec.c
67
omap_badwidth_write32(opaque, addr, value);
57
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
68
@@ -XXX,XX +XXX,XX @@ struct omap_watchdog_timer_s {
58
if (phys != -1) {
69
static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
59
/* Locks grabbed by tb_invalidate_phys_addr */
70
unsigned size)
60
tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
71
{
61
- phys | (pc & ~TARGET_PAGE_MASK));
72
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
62
+ phys | (pc & ~TARGET_PAGE_MASK), attrs);
73
+ struct omap_watchdog_timer_s *s = opaque;
74
75
if (size != 2) {
76
return omap_badwidth_read16(opaque, addr);
77
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
78
static void omap_wd_timer_write(void *opaque, hwaddr addr,
79
uint64_t value, unsigned size)
80
{
81
- struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
82
+ struct omap_watchdog_timer_s *s = opaque;
83
84
if (size != 2) {
85
omap_badwidth_write16(opaque, addr, value);
86
@@ -XXX,XX +XXX,XX @@ struct omap_32khz_timer_s {
87
static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
88
unsigned size)
89
{
90
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
91
+ struct omap_32khz_timer_s *s = opaque;
92
int offset = addr & OMAP_MPUI_REG_MASK;
93
94
if (size != 4) {
95
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
96
static void omap_os_timer_write(void *opaque, hwaddr addr,
97
uint64_t value, unsigned size)
98
{
99
- struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
100
+ struct omap_32khz_timer_s *s = opaque;
101
int offset = addr & OMAP_MPUI_REG_MASK;
102
103
if (size != 4) {
104
@@ -XXX,XX +XXX,XX @@ static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
105
static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
106
unsigned size)
107
{
108
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
109
+ struct omap_mpu_state_s *s = opaque;
110
uint16_t ret;
111
112
if (size != 2) {
113
@@ -XXX,XX +XXX,XX @@ static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
114
static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
115
uint64_t value, unsigned size)
116
{
117
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
118
+ struct omap_mpu_state_s *s = opaque;
119
int64_t now, ticks;
120
int div, mult;
121
static const int bypass_div[4] = { 1, 2, 4, 4 };
122
@@ -XXX,XX +XXX,XX @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
123
static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
124
unsigned size)
125
{
126
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
127
+ struct omap_mpu_state_s *s = opaque;
128
129
if (size != 4) {
130
return omap_badwidth_read32(opaque, addr);
131
@@ -XXX,XX +XXX,XX @@ static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
132
static void omap_pin_cfg_write(void *opaque, hwaddr addr,
133
uint64_t value, unsigned size)
134
{
135
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
136
+ struct omap_mpu_state_s *s = opaque;
137
uint32_t diff;
138
139
if (size != 4) {
140
@@ -XXX,XX +XXX,XX @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
141
static uint64_t omap_id_read(void *opaque, hwaddr addr,
142
unsigned size)
143
{
144
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
145
+ struct omap_mpu_state_s *s = opaque;
146
147
if (size != 4) {
148
return omap_badwidth_read32(opaque, addr);
149
@@ -XXX,XX +XXX,XX @@ static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mpu)
150
static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
151
unsigned size)
152
{
153
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
154
+ struct omap_mpu_state_s *s = opaque;
155
156
if (size != 4) {
157
return omap_badwidth_read32(opaque, addr);
158
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
159
static void omap_mpui_write(void *opaque, hwaddr addr,
160
uint64_t value, unsigned size)
161
{
162
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
163
+ struct omap_mpu_state_s *s = opaque;
164
165
if (size != 4) {
166
omap_badwidth_write32(opaque, addr, value);
167
@@ -XXX,XX +XXX,XX @@ struct omap_tipb_bridge_s {
168
static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
169
unsigned size)
170
{
171
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
172
+ struct omap_tipb_bridge_s *s = opaque;
173
174
if (size < 2) {
175
return omap_badwidth_read16(opaque, addr);
176
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
177
static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
178
uint64_t value, unsigned size)
179
{
180
- struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
181
+ struct omap_tipb_bridge_s *s = opaque;
182
183
if (size < 2) {
184
omap_badwidth_write16(opaque, addr, value);
185
@@ -XXX,XX +XXX,XX @@ static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
186
static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
187
unsigned size)
188
{
189
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
190
+ struct omap_mpu_state_s *s = opaque;
191
uint32_t ret;
192
193
if (size != 4) {
194
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
195
static void omap_tcmi_write(void *opaque, hwaddr addr,
196
uint64_t value, unsigned size)
197
{
198
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
199
+ struct omap_mpu_state_s *s = opaque;
200
201
if (size != 4) {
202
omap_badwidth_write32(opaque, addr, value);
203
@@ -XXX,XX +XXX,XX @@ struct dpll_ctl_s {
204
static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
205
unsigned size)
206
{
207
- struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
208
+ struct dpll_ctl_s *s = opaque;
209
210
if (size != 2) {
211
return omap_badwidth_read16(opaque, addr);
212
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
213
static void omap_dpll_write(void *opaque, hwaddr addr,
214
uint64_t value, unsigned size)
215
{
216
- struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
217
+ struct dpll_ctl_s *s = opaque;
218
uint16_t diff;
219
static const int bypass_div[4] = { 1, 2, 4, 4 };
220
int div, mult;
221
@@ -XXX,XX +XXX,XX @@ static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
222
static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
223
unsigned size)
224
{
225
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
226
+ struct omap_mpu_state_s *s = opaque;
227
228
if (size != 2) {
229
return omap_badwidth_read16(opaque, addr);
230
@@ -XXX,XX +XXX,XX @@ static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
231
static void omap_clkm_write(void *opaque, hwaddr addr,
232
uint64_t value, unsigned size)
233
{
234
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
235
+ struct omap_mpu_state_s *s = opaque;
236
uint16_t diff;
237
omap_clk clk;
238
static const char *clkschemename[8] = {
239
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_clkm_ops = {
240
static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
241
unsigned size)
242
{
243
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
244
+ struct omap_mpu_state_s *s = opaque;
245
CPUState *cpu = CPU(s->cpu);
246
247
if (size != 2) {
248
@@ -XXX,XX +XXX,XX @@ static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
249
static void omap_clkdsp_write(void *opaque, hwaddr addr,
250
uint64_t value, unsigned size)
251
{
252
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
253
+ struct omap_mpu_state_s *s = opaque;
254
uint16_t diff;
255
256
if (size != 2) {
257
@@ -XXX,XX +XXX,XX @@ struct omap_mpuio_s {
258
259
static void omap_mpuio_set(void *opaque, int line, int level)
260
{
261
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
262
+ struct omap_mpuio_s *s = opaque;
263
uint16_t prev = s->inputs;
264
265
if (level)
266
@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
267
static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
268
unsigned size)
269
{
270
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
271
+ struct omap_mpuio_s *s = opaque;
272
int offset = addr & OMAP_MPUI_REG_MASK;
273
uint16_t ret;
274
275
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
276
static void omap_mpuio_write(void *opaque, hwaddr addr,
277
uint64_t value, unsigned size)
278
{
279
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
280
+ struct omap_mpuio_s *s = opaque;
281
int offset = addr & OMAP_MPUI_REG_MASK;
282
uint16_t diff;
283
int ln;
284
@@ -XXX,XX +XXX,XX @@ static void omap_mpuio_reset(struct omap_mpuio_s *s)
285
286
static void omap_mpuio_onoff(void *opaque, int line, int on)
287
{
288
- struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
289
+ struct omap_mpuio_s *s = opaque;
290
291
s->clk = on;
292
if (on)
293
@@ -XXX,XX +XXX,XX @@ static void omap_uwire_transfer_start(struct omap_uwire_s *s)
63
}
294
}
64
}
295
}
65
#endif
296
66
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
297
-static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
67
index XXXXXXX..XXXXXXX 100644
298
- unsigned size)
68
--- a/target/xtensa/op_helper.c
299
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr, unsigned size)
69
+++ b/target/xtensa/op_helper.c
300
{
70
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
301
- struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
71
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
302
+ struct omap_uwire_s *s = opaque;
72
&paddr, &page_size, &access);
303
int offset = addr & OMAP_MPUI_REG_MASK;
73
if (ret == 0) {
304
74
- tb_invalidate_phys_addr(&address_space_memory, paddr);
305
if (size != 2) {
75
+ tb_invalidate_phys_addr(&address_space_memory, paddr,
306
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
76
+ MEMTXATTRS_UNSPECIFIED);
307
static void omap_uwire_write(void *opaque, hwaddr addr,
308
uint64_t value, unsigned size)
309
{
310
- struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
311
+ struct omap_uwire_s *s = opaque;
312
int offset = addr & OMAP_MPUI_REG_MASK;
313
314
if (size != 2) {
315
@@ -XXX,XX +XXX,XX @@ static void omap_pwl_update(struct omap_pwl_s *s)
77
}
316
}
78
}
317
}
79
318
319
-static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
320
- unsigned size)
321
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr, unsigned size)
322
{
323
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
324
+ struct omap_pwl_s *s = opaque;
325
int offset = addr & OMAP_MPUI_REG_MASK;
326
327
if (size != 1) {
328
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
329
static void omap_pwl_write(void *opaque, hwaddr addr,
330
uint64_t value, unsigned size)
331
{
332
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
333
+ struct omap_pwl_s *s = opaque;
334
int offset = addr & OMAP_MPUI_REG_MASK;
335
336
if (size != 1) {
337
@@ -XXX,XX +XXX,XX @@ static void omap_pwl_reset(struct omap_pwl_s *s)
338
339
static void omap_pwl_clk_update(void *opaque, int line, int on)
340
{
341
- struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
342
+ struct omap_pwl_s *s = opaque;
343
344
s->clk = on;
345
omap_pwl_update(s);
346
@@ -XXX,XX +XXX,XX @@ struct omap_pwt_s {
347
omap_clk clk;
348
};
349
350
-static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
351
- unsigned size)
352
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr, unsigned size)
353
{
354
- struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
355
+ struct omap_pwt_s *s = opaque;
356
int offset = addr & OMAP_MPUI_REG_MASK;
357
358
if (size != 1) {
359
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
360
static void omap_pwt_write(void *opaque, hwaddr addr,
361
uint64_t value, unsigned size)
362
{
363
- struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
364
+ struct omap_pwt_s *s = opaque;
365
int offset = addr & OMAP_MPUI_REG_MASK;
366
367
if (size != 1) {
368
@@ -XXX,XX +XXX,XX @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
369
printf("%s: conversion failed\n", __func__);
370
}
371
372
-static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
373
- unsigned size)
374
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr, unsigned size)
375
{
376
- struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
377
+ struct omap_rtc_s *s = opaque;
378
int offset = addr & OMAP_MPUI_REG_MASK;
379
uint8_t i;
380
381
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
382
static void omap_rtc_write(void *opaque, hwaddr addr,
383
uint64_t value, unsigned size)
384
{
385
- struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
386
+ struct omap_rtc_s *s = opaque;
387
int offset = addr & OMAP_MPUI_REG_MASK;
388
struct tm new_tm;
389
time_t ti[2];
390
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s)
391
392
static void omap_mcbsp_source_tick(void *opaque)
393
{
394
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
395
+ struct omap_mcbsp_s *s = opaque;
396
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
397
398
if (!s->rx_rate)
399
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s)
400
401
static void omap_mcbsp_sink_tick(void *opaque)
402
{
403
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
404
+ struct omap_mcbsp_s *s = opaque;
405
static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 };
406
407
if (!s->tx_rate)
408
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
409
static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
410
unsigned size)
411
{
412
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
413
+ struct omap_mcbsp_s *s = opaque;
414
int offset = addr & OMAP_MPUI_REG_MASK;
415
uint16_t ret;
416
417
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
418
static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
419
uint32_t value)
420
{
421
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
422
+ struct omap_mcbsp_s *s = opaque;
423
int offset = addr & OMAP_MPUI_REG_MASK;
424
425
switch (offset) {
426
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
427
static void omap_mcbsp_writew(void *opaque, hwaddr addr,
428
uint32_t value)
429
{
430
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
431
+ struct omap_mcbsp_s *s = opaque;
432
int offset = addr & OMAP_MPUI_REG_MASK;
433
434
if (offset == 0x04) {                /* DXR */
435
@@ -XXX,XX +XXX,XX @@ static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
436
437
static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
438
{
439
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
440
+ struct omap_mcbsp_s *s = opaque;
441
442
if (s->rx_rate) {
443
s->rx_req = s->codec->in.len;
444
@@ -XXX,XX +XXX,XX @@ static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
445
446
static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
447
{
448
- struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
449
+ struct omap_mcbsp_s *s = opaque;
450
451
if (s->tx_rate) {
452
s->tx_req = s->codec->out.size;
453
@@ -XXX,XX +XXX,XX @@ static void omap_lpg_reset(struct omap_lpg_s *s)
454
omap_lpg_update(s);
455
}
456
457
-static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
458
- unsigned size)
459
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr, unsigned size)
460
{
461
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
462
+ struct omap_lpg_s *s = opaque;
463
int offset = addr & OMAP_MPUI_REG_MASK;
464
465
if (size != 1) {
466
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
467
static void omap_lpg_write(void *opaque, hwaddr addr,
468
uint64_t value, unsigned size)
469
{
470
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
471
+ struct omap_lpg_s *s = opaque;
472
int offset = addr & OMAP_MPUI_REG_MASK;
473
474
if (size != 1) {
475
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_lpg_ops = {
476
477
static void omap_lpg_clk_update(void *opaque, int line, int on)
478
{
479
- struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
480
+ struct omap_lpg_s *s = opaque;
481
482
s->clk = on;
483
omap_lpg_update(s);
484
@@ -XXX,XX +XXX,XX @@ static void omap_setup_mpui_io(MemoryRegion *system_memory,
485
/* General chip reset */
486
static void omap1_mpu_reset(void *opaque)
487
{
488
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
489
+ struct omap_mpu_state_s *mpu = opaque;
490
491
omap_dma_reset(mpu->dma);
492
omap_mpu_timer_reset(mpu->timer[0]);
493
@@ -XXX,XX +XXX,XX @@ static void omap_setup_dsp_mapping(MemoryRegion *system_memory,
494
495
void omap_mpu_wakeup(void *opaque, int irq, int req)
496
{
497
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
498
+ struct omap_mpu_state_s *mpu = opaque;
499
CPUState *cpu = CPU(mpu->cpu);
500
501
if (cpu->halted) {
502
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
503
index XXXXXXX..XXXXXXX 100644
504
--- a/hw/arm/omap2.c
505
+++ b/hw/arm/omap2.c
506
@@ -XXX,XX +XXX,XX @@ static inline void omap_eac_out_empty(struct omap_eac_s *s)
507
508
static void omap_eac_in_cb(void *opaque, int avail_b)
509
{
510
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
511
+ struct omap_eac_s *s = opaque;
512
513
s->codec.rxavail = avail_b >> 2;
514
omap_eac_in_refill(s);
515
@@ -XXX,XX +XXX,XX @@ static void omap_eac_in_cb(void *opaque, int avail_b)
516
517
static void omap_eac_out_cb(void *opaque, int free_b)
518
{
519
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
520
+ struct omap_eac_s *s = opaque;
521
522
s->codec.txavail = free_b >> 2;
523
if (s->codec.txlen)
524
@@ -XXX,XX +XXX,XX @@ static void omap_eac_reset(struct omap_eac_s *s)
525
omap_eac_interrupt_update(s);
526
}
527
528
-static uint64_t omap_eac_read(void *opaque, hwaddr addr,
529
- unsigned size)
530
+static uint64_t omap_eac_read(void *opaque, hwaddr addr, unsigned size)
531
{
532
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
533
+ struct omap_eac_s *s = opaque;
534
uint32_t ret;
535
536
if (size != 2) {
537
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_eac_read(void *opaque, hwaddr addr,
538
static void omap_eac_write(void *opaque, hwaddr addr,
539
uint64_t value, unsigned size)
540
{
541
- struct omap_eac_s *s = (struct omap_eac_s *) opaque;
542
+ struct omap_eac_s *s = opaque;
543
544
if (size != 2) {
545
omap_badwidth_write16(opaque, addr, value);
546
@@ -XXX,XX +XXX,XX @@ static void omap_sti_reset(struct omap_sti_s *s)
547
static uint64_t omap_sti_read(void *opaque, hwaddr addr,
548
unsigned size)
549
{
550
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
551
+ struct omap_sti_s *s = opaque;
552
553
if (size != 4) {
554
return omap_badwidth_read32(opaque, addr);
555
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_read(void *opaque, hwaddr addr,
556
static void omap_sti_write(void *opaque, hwaddr addr,
557
uint64_t value, unsigned size)
558
{
559
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
560
+ struct omap_sti_s *s = opaque;
561
562
if (size != 4) {
563
omap_badwidth_write32(opaque, addr, value);
564
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_sti_ops = {
565
.endianness = DEVICE_NATIVE_ENDIAN,
566
};
567
568
-static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
569
- unsigned size)
570
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, unsigned size)
571
{
572
OMAP_BAD_REG(addr);
573
return 0;
574
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
575
static void omap_sti_fifo_write(void *opaque, hwaddr addr,
576
uint64_t value, unsigned size)
577
{
578
- struct omap_sti_s *s = (struct omap_sti_s *) opaque;
579
+ struct omap_sti_s *s = opaque;
580
int ch = addr >> 6;
581
uint8_t byte = value;
582
583
@@ -XXX,XX +XXX,XX @@ static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
584
static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
585
unsigned size)
586
{
587
- struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
588
+ struct omap_prcm_s *s = opaque;
589
uint32_t ret;
590
591
if (size != 4) {
592
@@ -XXX,XX +XXX,XX @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
593
static void omap_prcm_write(void *opaque, hwaddr addr,
594
uint64_t value, unsigned size)
595
{
596
- struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
597
+ struct omap_prcm_s *s = opaque;
598
599
if (size != 4) {
600
omap_badwidth_write32(opaque, addr, value);
601
@@ -XXX,XX +XXX,XX @@ struct omap_sysctl_s {
602
static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
603
{
604
605
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
606
+ struct omap_sysctl_s *s = opaque;
607
int pad_offset, byte_offset;
608
int value;
609
610
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
611
612
static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
613
{
614
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
615
+ struct omap_sysctl_s *s = opaque;
616
617
switch (addr) {
618
case 0x000:    /* CONTROL_REVISION */
619
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
620
return 0;
621
}
622
623
-static void omap_sysctl_write8(void *opaque, hwaddr addr,
624
- uint32_t value)
625
+static void omap_sysctl_write8(void *opaque, hwaddr addr, uint32_t value)
626
{
627
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
628
+ struct omap_sysctl_s *s = opaque;
629
int pad_offset, byte_offset;
630
int prev_value;
631
632
@@ -XXX,XX +XXX,XX @@ static void omap_sysctl_write8(void *opaque, hwaddr addr,
633
}
634
}
635
636
-static void omap_sysctl_write(void *opaque, hwaddr addr,
637
- uint32_t value)
638
+static void omap_sysctl_write(void *opaque, hwaddr addr, uint32_t value)
639
{
640
- struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
641
+ struct omap_sysctl_s *s = opaque;
642
643
switch (addr) {
644
case 0x000:    /* CONTROL_REVISION */
645
@@ -XXX,XX +XXX,XX @@ static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
646
/* General chip reset */
647
static void omap2_mpu_reset(void *opaque)
648
{
649
- struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
650
+ struct omap_mpu_state_s *mpu = opaque;
651
652
omap_dma_reset(mpu->dma);
653
omap_prcm_reset(mpu->prcm);
654
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
655
index XXXXXXX..XXXXXXX 100644
656
--- a/hw/arm/omap_sx1.c
657
+++ b/hw/arm/omap_sx1.c
658
@@ -XXX,XX +XXX,XX @@
659
static uint64_t static_read(void *opaque, hwaddr offset,
660
unsigned size)
661
{
662
- uint32_t *val = (uint32_t *) opaque;
663
+ uint32_t *val = opaque;
664
uint32_t mask = (4 / size) - 1;
665
666
return *val >> ((offset & mask) << 3);
667
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
668
index XXXXXXX..XXXXXXX 100644
669
--- a/hw/arm/palm.c
670
+++ b/hw/arm/palm.c
671
@@ -XXX,XX +XXX,XX @@ static struct {
672
673
static void palmte_button_event(void *opaque, int keycode)
674
{
675
- struct omap_mpu_state_s *cpu = (struct omap_mpu_state_s *) opaque;
676
+ struct omap_mpu_state_s *cpu = opaque;
677
678
if (palmte_keymap[keycode & 0x7f].row != -1)
679
omap_mpuio_key(cpu->mpuio,
680
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
681
index XXXXXXX..XXXXXXX 100644
682
--- a/hw/char/omap_uart.c
683
+++ b/hw/char/omap_uart.c
684
@@ -XXX,XX +XXX,XX @@ struct omap_uart_s *omap_uart_init(hwaddr base,
685
return s;
686
}
687
688
-static uint64_t omap_uart_read(void *opaque, hwaddr addr,
689
- unsigned size)
690
+static uint64_t omap_uart_read(void *opaque, hwaddr addr, unsigned size)
691
{
692
- struct omap_uart_s *s = (struct omap_uart_s *) opaque;
693
+ struct omap_uart_s *s = opaque;
694
695
if (size == 4) {
696
return omap_badwidth_read8(opaque, addr);
697
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_uart_read(void *opaque, hwaddr addr,
698
static void omap_uart_write(void *opaque, hwaddr addr,
699
uint64_t value, unsigned size)
700
{
701
- struct omap_uart_s *s = (struct omap_uart_s *) opaque;
702
+ struct omap_uart_s *s = opaque;
703
704
if (size == 4) {
705
omap_badwidth_write8(opaque, addr, value);
706
diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c
707
index XXXXXXX..XXXXXXX 100644
708
--- a/hw/display/omap_dss.c
709
+++ b/hw/display/omap_dss.c
710
@@ -XXX,XX +XXX,XX @@ void omap_dss_reset(struct omap_dss_s *s)
711
static uint64_t omap_diss_read(void *opaque, hwaddr addr,
712
unsigned size)
713
{
714
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
715
+ struct omap_dss_s *s = opaque;
716
717
if (size != 4) {
718
return omap_badwidth_read32(opaque, addr);
719
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_diss_read(void *opaque, hwaddr addr,
720
static void omap_diss_write(void *opaque, hwaddr addr,
721
uint64_t value, unsigned size)
722
{
723
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
724
+ struct omap_dss_s *s = opaque;
725
726
if (size != 4) {
727
omap_badwidth_write32(opaque, addr, value);
728
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_diss_ops = {
729
static uint64_t omap_disc_read(void *opaque, hwaddr addr,
730
unsigned size)
731
{
732
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
733
+ struct omap_dss_s *s = opaque;
734
735
if (size != 4) {
736
return omap_badwidth_read32(opaque, addr);
737
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_disc_read(void *opaque, hwaddr addr,
738
static void omap_disc_write(void *opaque, hwaddr addr,
739
uint64_t value, unsigned size)
740
{
741
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
742
+ struct omap_dss_s *s = opaque;
743
744
if (size != 4) {
745
omap_badwidth_write32(opaque, addr, value);
746
@@ -XXX,XX +XXX,XX @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
747
omap_dispc_interrupt_update(s);
748
}
749
750
-static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
751
- unsigned size)
752
+static uint64_t omap_rfbi_read(void *opaque, hwaddr addr, unsigned size)
753
{
754
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
755
+ struct omap_dss_s *s = opaque;
756
757
if (size != 4) {
758
return omap_badwidth_read32(opaque, addr);
759
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
760
static void omap_rfbi_write(void *opaque, hwaddr addr,
761
uint64_t value, unsigned size)
762
{
763
- struct omap_dss_s *s = (struct omap_dss_s *) opaque;
764
+ struct omap_dss_s *s = opaque;
765
766
if (size != 4) {
767
omap_badwidth_write32(opaque, addr, value);
768
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
769
index XXXXXXX..XXXXXXX 100644
770
--- a/hw/display/omap_lcdc.c
771
+++ b/hw/display/omap_lcdc.c
772
@@ -XXX,XX +XXX,XX @@ static void draw_line16_32(void *opaque, uint8_t *d, const uint8_t *s,
773
774
static void omap_update_display(void *opaque)
775
{
776
- struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
777
+ struct omap_lcd_panel_s *omap_lcd = opaque;
778
DisplaySurface *surface;
779
drawfn draw_line;
780
int size, height, first, last;
781
@@ -XXX,XX +XXX,XX @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
782
}
783
}
784
785
-static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
786
- unsigned size)
787
+static uint64_t omap_lcdc_read(void *opaque, hwaddr addr, unsigned size)
788
{
789
- struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
790
+ struct omap_lcd_panel_s *s = opaque;
791
792
switch (addr) {
793
case 0x00:    /* LCD_CONTROL */
794
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_lcdc_read(void *opaque, hwaddr addr,
795
static void omap_lcdc_write(void *opaque, hwaddr addr,
796
uint64_t value, unsigned size)
797
{
798
- struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
799
+ struct omap_lcd_panel_s *s = opaque;
800
801
switch (addr) {
802
case 0x00:    /* LCD_CONTROL */
803
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c
804
index XXXXXXX..XXXXXXX 100644
805
--- a/hw/dma/omap_dma.c
806
+++ b/hw/dma/omap_dma.c
807
@@ -XXX,XX +XXX,XX @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
808
return 0;
809
}
810
811
-static uint64_t omap_dma_read(void *opaque, hwaddr addr,
812
- unsigned size)
813
+static uint64_t omap_dma_read(void *opaque, hwaddr addr, unsigned size)
814
{
815
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
816
+ struct omap_dma_s *s = opaque;
817
int reg, ch;
818
uint16_t ret;
819
820
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma_read(void *opaque, hwaddr addr,
821
static void omap_dma_write(void *opaque, hwaddr addr,
822
uint64_t value, unsigned size)
823
{
824
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
825
+ struct omap_dma_s *s = opaque;
826
int reg, ch;
827
828
if (size != 2) {
829
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_dma_ops = {
830
831
static void omap_dma_request(void *opaque, int drq, int req)
832
{
833
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
834
+ struct omap_dma_s *s = opaque;
835
/* The request pins are level triggered in QEMU. */
836
if (req) {
837
if (~s->dma->drqbmp & (1ULL << drq)) {
838
@@ -XXX,XX +XXX,XX @@ static void omap_dma_request(void *opaque, int drq, int req)
839
/* XXX: this won't be needed once soc_dma knows about clocks. */
840
static void omap_dma_clk_update(void *opaque, int line, int on)
841
{
842
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
843
+ struct omap_dma_s *s = opaque;
844
int i;
845
846
s->dma->freq = omap_clk_getrate(s->clk);
847
@@ -XXX,XX +XXX,XX @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
848
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
849
unsigned size)
850
{
851
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
852
+ struct omap_dma_s *s = opaque;
853
int irqn = 0, chnum;
854
struct omap_dma_channel_s *ch;
855
856
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
857
static void omap_dma4_write(void *opaque, hwaddr addr,
858
uint64_t value, unsigned size)
859
{
860
- struct omap_dma_s *s = (struct omap_dma_s *) opaque;
861
+ struct omap_dma_s *s = opaque;
862
int chnum, irqn = 0;
863
struct omap_dma_channel_s *ch;
864
865
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
866
index XXXXXXX..XXXXXXX 100644
867
--- a/hw/gpio/omap_gpio.c
868
+++ b/hw/gpio/omap_gpio.c
869
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_set(void *opaque, int line, int level)
870
static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
871
unsigned size)
872
{
873
- struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
874
+ struct omap_gpio_s *s = opaque;
875
int offset = addr & OMAP_MPUI_REG_MASK;
876
877
if (size != 2) {
878
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpio_read(void *opaque, hwaddr addr,
879
static void omap_gpio_write(void *opaque, hwaddr addr,
880
uint64_t value, unsigned size)
881
{
882
- struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
883
+ struct omap_gpio_s *s = opaque;
884
int offset = addr & OMAP_MPUI_REG_MASK;
885
uint16_t diff;
886
int ln;
887
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
888
889
static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
890
{
891
- struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
892
+ struct omap2_gpio_s *s = opaque;
893
894
switch (addr) {
895
case 0x00:    /* GPIO_REVISION */
896
@@ -XXX,XX +XXX,XX @@ static uint32_t omap2_gpio_module_read(void *opaque, hwaddr addr)
897
static void omap2_gpio_module_write(void *opaque, hwaddr addr,
898
uint32_t value)
899
{
900
- struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
901
+ struct omap2_gpio_s *s = opaque;
902
uint32_t diff;
903
int ln;
904
905
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
906
s->gpo = 0;
907
}
908
909
-static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
910
- unsigned size)
911
+static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
912
{
913
- struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
914
+ struct omap2_gpif_s *s = opaque;
915
916
switch (addr) {
917
case 0x00:    /* IPGENERICOCPSPL_REVISION */
918
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr,
919
static void omap2_gpif_top_write(void *opaque, hwaddr addr,
920
uint64_t value, unsigned size)
921
{
922
- struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
923
+ struct omap2_gpif_s *s = opaque;
924
925
switch (addr) {
926
case 0x00:    /* IPGENERICOCPSPL_REVISION */
927
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
928
index XXXXXXX..XXXXXXX 100644
929
--- a/hw/intc/omap_intc.c
930
+++ b/hw/intc/omap_intc.c
931
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
932
933
static void omap_set_intr(void *opaque, int irq, int req)
934
{
935
- struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
936
+ struct omap_intr_handler_s *ih = opaque;
937
uint32_t rise;
938
939
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
940
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
941
/* Simplified version with no edge detection */
942
static void omap_set_intr_noedge(void *opaque, int irq, int req)
943
{
944
- struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
945
+ struct omap_intr_handler_s *ih = opaque;
946
uint32_t rise;
947
948
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
949
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
950
static uint64_t omap_inth_read(void *opaque, hwaddr addr,
951
unsigned size)
952
{
953
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
954
+ struct omap_intr_handler_s *s = opaque;
955
int i, offset = addr;
956
int bank_no = offset >> 8;
957
int line_no;
958
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
959
static void omap_inth_write(void *opaque, hwaddr addr,
960
uint64_t value, unsigned size)
961
{
962
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
963
+ struct omap_intr_handler_s *s = opaque;
964
int i, offset = addr;
965
int bank_no = offset >> 8;
966
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
967
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
968
static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
969
unsigned size)
970
{
971
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
972
+ struct omap_intr_handler_s *s = opaque;
973
int offset = addr;
974
int bank_no, line_no;
975
struct omap_intr_handler_bank_s *bank = NULL;
976
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
977
static void omap2_inth_write(void *opaque, hwaddr addr,
978
uint64_t value, unsigned size)
979
{
980
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
981
+ struct omap_intr_handler_s *s = opaque;
982
int offset = addr;
983
int bank_no, line_no;
984
struct omap_intr_handler_bank_s *bank = NULL;
985
diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c
986
index XXXXXXX..XXXXXXX 100644
987
--- a/hw/misc/omap_gpmc.c
988
+++ b/hw/misc/omap_gpmc.c
989
@@ -XXX,XX +XXX,XX @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
990
static uint64_t omap_nand_read(void *opaque, hwaddr addr,
991
unsigned size)
992
{
993
- struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
994
+ struct omap_gpmc_cs_file_s *f = opaque;
995
uint64_t v;
996
nand_setpins(f->dev, 0, 0, 0, 1, 0);
997
switch (omap_gpmc_devsize(f)) {
998
@@ -XXX,XX +XXX,XX @@ static void omap_nand_setio(DeviceState *dev, uint64_t value,
999
static void omap_nand_write(void *opaque, hwaddr addr,
1000
uint64_t value, unsigned size)
1001
{
1002
- struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
1003
+ struct omap_gpmc_cs_file_s *f = opaque;
1004
nand_setpins(f->dev, 0, 0, 0, 1, 0);
1005
omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
1006
}
1007
@@ -XXX,XX +XXX,XX @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
1008
static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
1009
unsigned size)
1010
{
1011
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1012
+ struct omap_gpmc_s *s = opaque;
1013
uint32_t data;
1014
if (s->prefetch.config1 & 1) {
1015
/* The TRM doesn't define the behaviour if you read from the
1016
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
1017
static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
1018
uint64_t value, unsigned size)
1019
{
1020
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1021
+ struct omap_gpmc_s *s = opaque;
1022
int cs = prefetch_cs(s->prefetch.config1);
1023
if ((s->prefetch.config1 & 1) == 0) {
1024
/* The TRM doesn't define the behaviour of writing to the
1025
@@ -XXX,XX +XXX,XX @@ static int gpmc_wordaccess_only(hwaddr addr)
1026
static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
1027
unsigned size)
1028
{
1029
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1030
+ struct omap_gpmc_s *s = opaque;
1031
int cs;
1032
struct omap_gpmc_cs_file_s *f;
1033
1034
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
1035
static void omap_gpmc_write(void *opaque, hwaddr addr,
1036
uint64_t value, unsigned size)
1037
{
1038
- struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
1039
+ struct omap_gpmc_s *s = opaque;
1040
int cs;
1041
struct omap_gpmc_cs_file_s *f;
1042
1043
diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c
1044
index XXXXXXX..XXXXXXX 100644
1045
--- a/hw/misc/omap_l4.c
1046
+++ b/hw/misc/omap_l4.c
1047
@@ -XXX,XX +XXX,XX @@ hwaddr omap_l4_region_size(struct omap_target_agent_s *ta,
1048
return ta->start[region].size;
1049
}
1050
1051
-static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
1052
- unsigned size)
1053
+static uint64_t omap_l4ta_read(void *opaque, hwaddr addr, unsigned size)
1054
{
1055
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1056
+ struct omap_target_agent_s *s = opaque;
1057
1058
if (size != 2) {
1059
return omap_badwidth_read16(opaque, addr);
1060
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_l4ta_read(void *opaque, hwaddr addr,
1061
static void omap_l4ta_write(void *opaque, hwaddr addr,
1062
uint64_t value, unsigned size)
1063
{
1064
- struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1065
+ struct omap_target_agent_s *s = opaque;
1066
1067
if (size != 4) {
1068
omap_badwidth_write32(opaque, addr, value);
1069
diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c
1070
index XXXXXXX..XXXXXXX 100644
1071
--- a/hw/misc/omap_sdrc.c
1072
+++ b/hw/misc/omap_sdrc.c
1073
@@ -XXX,XX +XXX,XX @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
1074
s->config = 0x10;
1075
}
1076
1077
-static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
1078
- unsigned size)
1079
+static uint64_t omap_sdrc_read(void *opaque, hwaddr addr, unsigned size)
1080
{
1081
- struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
1082
+ struct omap_sdrc_s *s = opaque;
1083
1084
if (size != 4) {
1085
return omap_badwidth_read32(opaque, addr);
1086
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_sdrc_read(void *opaque, hwaddr addr,
1087
static void omap_sdrc_write(void *opaque, hwaddr addr,
1088
uint64_t value, unsigned size)
1089
{
1090
- struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
1091
+ struct omap_sdrc_s *s = opaque;
1092
1093
if (size != 4) {
1094
omap_badwidth_write32(opaque, addr, value);
1095
diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c
1096
index XXXXXXX..XXXXXXX 100644
1097
--- a/hw/misc/omap_tap.c
1098
+++ b/hw/misc/omap_tap.c
1099
@@ -XXX,XX +XXX,XX @@
1100
#include "hw/arm/omap.h"
1101
1102
/* TEST-Chip-level TAP */
1103
-static uint64_t omap_tap_read(void *opaque, hwaddr addr,
1104
- unsigned size)
1105
+static uint64_t omap_tap_read(void *opaque, hwaddr addr, unsigned size)
1106
{
1107
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1108
+ struct omap_mpu_state_s *s = opaque;
1109
1110
if (size != 4) {
1111
return omap_badwidth_read32(opaque, addr);
1112
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
1113
index XXXXXXX..XXXXXXX 100644
1114
--- a/hw/sd/omap_mmc.c
1115
+++ b/hw/sd/omap_mmc.c
1116
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
1117
device_cold_reset(DEVICE(host->card));
1118
}
1119
1120
-static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
1121
- unsigned size)
1122
+static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size)
1123
{
1124
uint16_t i;
1125
- struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
1126
+ struct omap_mmc_s *s = opaque;
1127
1128
if (size != 2) {
1129
return omap_badwidth_read16(opaque, offset);
1130
@@ -XXX,XX +XXX,XX @@ static void omap_mmc_write(void *opaque, hwaddr offset,
1131
uint64_t value, unsigned size)
1132
{
1133
int i;
1134
- struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
1135
+ struct omap_mmc_s *s = opaque;
1136
1137
if (size != 2) {
1138
omap_badwidth_write16(opaque, offset, value);
1139
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_mmc_ops = {
1140
1141
static void omap_mmc_cover_cb(void *opaque, int line, int level)
1142
{
1143
- struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
1144
+ struct omap_mmc_s *host = opaque;
1145
1146
if (!host->cdet_state && level) {
1147
host->status |= 0x0002;
1148
diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
1149
index XXXXXXX..XXXXXXX 100644
1150
--- a/hw/ssi/omap_spi.c
1151
+++ b/hw/ssi/omap_spi.c
1152
@@ -XXX,XX +XXX,XX @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
1153
omap_mcspi_interrupt_update(s);
1154
}
1155
1156
-static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1157
- unsigned size)
1158
+static uint64_t omap_mcspi_read(void *opaque, hwaddr addr, unsigned size)
1159
{
1160
- struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1161
+ struct omap_mcspi_s *s = opaque;
1162
int ch = 0;
1163
uint32_t ret;
1164
1165
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1166
static void omap_mcspi_write(void *opaque, hwaddr addr,
1167
uint64_t value, unsigned size)
1168
{
1169
- struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1170
+ struct omap_mcspi_s *s = opaque;
1171
int ch = 0;
1172
1173
if (size != 4) {
1174
diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c
1175
index XXXXXXX..XXXXXXX 100644
1176
--- a/hw/timer/omap_gptimer.c
1177
+++ b/hw/timer/omap_gptimer.c
1178
@@ -XXX,XX +XXX,XX @@ static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
1179
1180
static void omap_gp_timer_tick(void *opaque)
1181
{
1182
- struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
1183
+ struct omap_gp_timer_s *timer = opaque;
1184
1185
if (!timer->ar) {
1186
timer->st = 0;
1187
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_tick(void *opaque)
1188
1189
static void omap_gp_timer_match(void *opaque)
1190
{
1191
- struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
1192
+ struct omap_gp_timer_s *timer = opaque;
1193
1194
if (timer->trigger == gpt_trigger_both)
1195
omap_gp_timer_trigger(timer);
1196
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_match(void *opaque)
1197
1198
static void omap_gp_timer_input(void *opaque, int line, int on)
1199
{
1200
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1201
+ struct omap_gp_timer_s *s = opaque;
1202
int trigger;
1203
1204
switch (s->capture) {
1205
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_input(void *opaque, int line, int on)
1206
1207
static void omap_gp_timer_clk_update(void *opaque, int line, int on)
1208
{
1209
- struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
1210
+ struct omap_gp_timer_s *timer = opaque;
1211
1212
omap_gp_timer_sync(timer);
1213
timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
1214
@@ -XXX,XX +XXX,XX @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
1215
1216
static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
1217
{
1218
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1219
+ struct omap_gp_timer_s *s = opaque;
1220
1221
switch (addr) {
1222
case 0x00:    /* TIDR */
1223
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readw(void *opaque, hwaddr addr)
1224
1225
static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
1226
{
1227
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1228
+ struct omap_gp_timer_s *s = opaque;
1229
uint32_t ret;
1230
1231
if (addr & 2)
1232
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_gp_timer_readh(void *opaque, hwaddr addr)
1233
}
1234
}
1235
1236
-static void omap_gp_timer_write(void *opaque, hwaddr addr,
1237
- uint32_t value)
1238
+static void omap_gp_timer_write(void *opaque, hwaddr addr, uint32_t value)
1239
{
1240
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1241
+ struct omap_gp_timer_s *s = opaque;
1242
1243
switch (addr) {
1244
case 0x00:    /* TIDR */
1245
@@ -XXX,XX +XXX,XX @@ static void omap_gp_timer_write(void *opaque, hwaddr addr,
1246
}
1247
}
1248
1249
-static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
1250
- uint32_t value)
1251
+static void omap_gp_timer_writeh(void *opaque, hwaddr addr, uint32_t value)
1252
{
1253
- struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
1254
+ struct omap_gp_timer_s *s = opaque;
1255
1256
if (addr & 2)
1257
omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
1258
diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c
1259
index XXXXXXX..XXXXXXX 100644
1260
--- a/hw/timer/omap_synctimer.c
1261
+++ b/hw/timer/omap_synctimer.c
1262
@@ -XXX,XX +XXX,XX @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
1263
1264
static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
1265
{
1266
- struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
1267
+ struct omap_synctimer_s *s = opaque;
1268
1269
switch (addr) {
1270
case 0x00:    /* 32KSYNCNT_REV */
1271
@@ -XXX,XX +XXX,XX @@ static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr)
1272
1273
static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr)
1274
{
1275
- struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
1276
+ struct omap_synctimer_s *s = opaque;
1277
uint32_t ret;
1278
1279
if (addr & 2)
80
--
1280
--
81
2.17.1
1281
2.34.1
82
1282
83
1283
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to flatview_extend_translation().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
2
3
Following docs/devel/style.rst guidelines, rename omap_gpif_s ->
4
Omap1GpioState. This also remove a use of 'struct' in the
5
DECLARE_INSTANCE_CHECKER() macro call.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-5-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
10
---
11
---
11
exec.c | 15 ++++++++++-----
12
include/hw/arm/omap.h | 6 +++---
12
1 file changed, 10 insertions(+), 5 deletions(-)
13
hw/gpio/omap_gpio.c | 16 ++++++++--------
14
2 files changed, 11 insertions(+), 11 deletions(-)
13
15
14
diff --git a/exec.c b/exec.c
16
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
18
--- a/include/hw/arm/omap.h
17
+++ b/exec.c
19
+++ b/include/hw/arm/omap.h
18
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
20
@@ -XXX,XX +XXX,XX @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk);
19
21
20
static hwaddr
22
/* omap_gpio.c */
21
flatview_extend_translation(FlatView *fv, hwaddr addr,
23
#define TYPE_OMAP1_GPIO "omap-gpio"
22
- hwaddr target_len,
24
-DECLARE_INSTANCE_CHECKER(struct omap_gpif_s, OMAP1_GPIO,
23
- MemoryRegion *mr, hwaddr base, hwaddr len,
25
+typedef struct Omap1GpioState Omap1GpioState;
24
- bool is_write)
26
+DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
25
+ hwaddr target_len,
27
TYPE_OMAP1_GPIO)
26
+ MemoryRegion *mr, hwaddr base, hwaddr len,
28
27
+ bool is_write, MemTxAttrs attrs)
29
#define TYPE_OMAP2_GPIO "omap2-gpio"
30
DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
31
TYPE_OMAP2_GPIO)
32
33
-typedef struct omap_gpif_s omap_gpif;
34
typedef struct omap2_gpif_s omap2_gpif;
35
36
/* TODO: clock framework (see above) */
37
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk);
38
+void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
39
40
void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
41
void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
42
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/gpio/omap_gpio.c
45
+++ b/hw/gpio/omap_gpio.c
46
@@ -XXX,XX +XXX,XX @@ struct omap_gpio_s {
47
uint16_t pins;
48
};
49
50
-struct omap_gpif_s {
51
+struct Omap1GpioState {
52
SysBusDevice parent_obj;
53
54
MemoryRegion iomem;
55
@@ -XXX,XX +XXX,XX @@ struct omap_gpif_s {
56
/* General-Purpose I/O of OMAP1 */
57
static void omap_gpio_set(void *opaque, int line, int level)
28
{
58
{
29
hwaddr done = 0;
59
- struct omap_gpif_s *p = opaque;
30
hwaddr xlat;
60
+ Omap1GpioState *p = opaque;
31
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
61
struct omap_gpio_s *s = &p->omap1;
32
62
uint16_t prev = s->inputs;
33
memory_region_ref(mr);
63
34
*plen = flatview_extend_translation(fv, addr, len, mr, xlat,
64
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpio_module_ops = {
35
- l, is_write);
65
36
+ l, is_write, attrs);
66
static void omap_gpif_reset(DeviceState *dev)
37
ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
67
{
38
rcu_read_unlock();
68
- struct omap_gpif_s *s = OMAP1_GPIO(dev);
39
69
+ Omap1GpioState *s = OMAP1_GPIO(dev);
40
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
70
41
mr = cache->mrs.mr;
71
omap_gpio_reset(&s->omap1);
42
memory_region_ref(mr);
72
}
43
if (memory_access_is_direct(mr, is_write)) {
73
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_gpif_top_ops = {
44
+ /* We don't care about the memory attributes here as we're only
74
static void omap_gpio_init(Object *obj)
45
+ * doing this if we found actual RAM, which behaves the same
75
{
46
+ * regardless of attributes; so UNSPECIFIED is fine.
76
DeviceState *dev = DEVICE(obj);
47
+ */
77
- struct omap_gpif_s *s = OMAP1_GPIO(obj);
48
l = flatview_extend_translation(cache->fv, addr, len, mr,
78
+ Omap1GpioState *s = OMAP1_GPIO(obj);
49
- cache->xlat, l, is_write);
79
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
50
+ cache->xlat, l, is_write,
80
51
+ MEMTXATTRS_UNSPECIFIED);
81
qdev_init_gpio_in(dev, omap_gpio_set, 16);
52
cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
82
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_init(Object *obj)
53
} else {
83
54
cache->ptr = NULL;
84
static void omap_gpio_realize(DeviceState *dev, Error **errp)
85
{
86
- struct omap_gpif_s *s = OMAP1_GPIO(dev);
87
+ Omap1GpioState *s = OMAP1_GPIO(dev);
88
89
if (!s->clk) {
90
error_setg(errp, "omap-gpio: clk not connected");
91
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp)
92
}
93
}
94
95
-void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk)
96
+void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk)
97
{
98
gpio->clk = clk;
99
}
100
101
static Property omap_gpio_properties[] = {
102
- DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0),
103
+ DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0),
104
DEFINE_PROP_END_OF_LIST(),
105
};
106
107
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_class_init(ObjectClass *klass, void *data)
108
static const TypeInfo omap_gpio_info = {
109
.name = TYPE_OMAP1_GPIO,
110
.parent = TYPE_SYS_BUS_DEVICE,
111
- .instance_size = sizeof(struct omap_gpif_s),
112
+ .instance_size = sizeof(Omap1GpioState),
113
.instance_init = omap_gpio_init,
114
.class_init = omap_gpio_class_init,
115
};
55
--
116
--
56
2.17.1
117
2.34.1
57
118
58
119
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to address_space_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
2
3
Following docs/devel/style.rst guidelines, rename omap2_gpif_s ->
4
Omap2GpioState. This also remove a use of 'struct' in the
5
DECLARE_INSTANCE_CHECKER() macro call.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-6-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
10
---
11
---
11
include/exec/memory.h | 4 +++-
12
include/hw/arm/omap.h | 9 ++++-----
12
include/sysemu/dma.h | 3 ++-
13
hw/gpio/omap_gpio.c | 20 ++++++++++----------
13
exec.c | 3 ++-
14
2 files changed, 14 insertions(+), 15 deletions(-)
14
target/s390x/diag.c | 6 ++++--
15
target/s390x/excp_helper.c | 3 ++-
16
target/s390x/mmu_helper.c | 3 ++-
17
target/s390x/sigp.c | 3 ++-
18
7 files changed, 17 insertions(+), 8 deletions(-)
19
15
20
diff --git a/include/exec/memory.h b/include/exec/memory.h
16
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/memory.h
18
--- a/include/hw/arm/omap.h
23
+++ b/include/exec/memory.h
19
+++ b/include/hw/arm/omap.h
24
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
20
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO,
25
* @addr: address within that address space
21
TYPE_OMAP1_GPIO)
26
* @len: length of the area to be checked
22
27
* @is_write: indicates the transfer direction
23
#define TYPE_OMAP2_GPIO "omap2-gpio"
28
+ * @attrs: memory attributes
24
-DECLARE_INSTANCE_CHECKER(struct omap2_gpif_s, OMAP2_GPIO,
29
*/
25
+typedef struct Omap2GpioState Omap2GpioState;
30
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
26
+DECLARE_INSTANCE_CHECKER(Omap2GpioState, OMAP2_GPIO,
31
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
27
TYPE_OMAP2_GPIO)
32
+ bool is_write, MemTxAttrs attrs);
28
33
29
-typedef struct omap2_gpif_s omap2_gpif;
34
/* address_space_map: map a physical memory region into a host virtual address
30
-
35
*
31
/* TODO: clock framework (see above) */
36
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
32
void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk);
33
34
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk);
35
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk);
36
+void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk);
37
+void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk);
38
39
/* OMAP2 l4 Interconnect */
40
struct omap_l4_s;
41
diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c
37
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
38
--- a/include/sysemu/dma.h
43
--- a/hw/gpio/omap_gpio.c
39
+++ b/include/sysemu/dma.h
44
+++ b/hw/gpio/omap_gpio.c
40
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
45
@@ -XXX,XX +XXX,XX @@ struct omap2_gpio_s {
41
DMADirection dir)
46
uint8_t delay;
47
};
48
49
-struct omap2_gpif_s {
50
+struct Omap2GpioState {
51
SysBusDevice parent_obj;
52
53
MemoryRegion iomem;
54
@@ -XXX,XX +XXX,XX @@ static inline void omap2_gpio_module_int(struct omap2_gpio_s *s, int line)
55
56
static void omap2_gpio_set(void *opaque, int line, int level)
42
{
57
{
43
return address_space_access_valid(as, addr, len,
58
- struct omap2_gpif_s *p = opaque;
44
- dir == DMA_DIRECTION_FROM_DEVICE);
59
+ Omap2GpioState *p = opaque;
45
+ dir == DMA_DIRECTION_FROM_DEVICE,
60
struct omap2_gpio_s *s = &p->modules[line >> 5];
46
+ MEMTXATTRS_UNSPECIFIED);
61
62
line &= 31;
63
@@ -XXX,XX +XXX,XX @@ static void omap_gpif_reset(DeviceState *dev)
64
65
static void omap2_gpif_reset(DeviceState *dev)
66
{
67
- struct omap2_gpif_s *s = OMAP2_GPIO(dev);
68
+ Omap2GpioState *s = OMAP2_GPIO(dev);
69
int i;
70
71
for (i = 0; i < s->modulecount; i++) {
72
@@ -XXX,XX +XXX,XX @@ static void omap2_gpif_reset(DeviceState *dev)
73
74
static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
75
{
76
- struct omap2_gpif_s *s = opaque;
77
+ Omap2GpioState *s = opaque;
78
79
switch (addr) {
80
case 0x00:    /* IPGENERICOCPSPL_REVISION */
81
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_gpif_top_read(void *opaque, hwaddr addr, unsigned size)
82
static void omap2_gpif_top_write(void *opaque, hwaddr addr,
83
uint64_t value, unsigned size)
84
{
85
- struct omap2_gpif_s *s = opaque;
86
+ Omap2GpioState *s = opaque;
87
88
switch (addr) {
89
case 0x00:    /* IPGENERICOCPSPL_REVISION */
90
@@ -XXX,XX +XXX,XX @@ static void omap_gpio_realize(DeviceState *dev, Error **errp)
91
92
static void omap2_gpio_realize(DeviceState *dev, Error **errp)
93
{
94
- struct omap2_gpif_s *s = OMAP2_GPIO(dev);
95
+ Omap2GpioState *s = OMAP2_GPIO(dev);
96
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
97
int i;
98
99
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_gpio_info = {
100
.class_init = omap_gpio_class_init,
101
};
102
103
-void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk)
104
+void omap2_gpio_set_iclk(Omap2GpioState *gpio, omap_clk clk)
105
{
106
gpio->iclk = clk;
47
}
107
}
48
108
49
static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
109
-void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk)
50
diff --git a/exec.c b/exec.c
110
+void omap2_gpio_set_fclk(Omap2GpioState *gpio, uint8_t i, omap_clk clk)
51
index XXXXXXX..XXXXXXX 100644
111
{
52
--- a/exec.c
112
assert(i <= 5);
53
+++ b/exec.c
113
gpio->fclk[i] = clk;
54
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
55
}
114
}
56
115
57
bool address_space_access_valid(AddressSpace *as, hwaddr addr,
116
static Property omap2_gpio_properties[] = {
58
- int len, bool is_write)
117
- DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0),
59
+ int len, bool is_write,
118
+ DEFINE_PROP_INT32("mpu_model", Omap2GpioState, mpu_model, 0),
60
+ MemTxAttrs attrs)
119
DEFINE_PROP_END_OF_LIST(),
61
{
120
};
62
FlatView *fv;
121
63
bool result;
122
@@ -XXX,XX +XXX,XX @@ static void omap2_gpio_class_init(ObjectClass *klass, void *data)
64
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
123
static const TypeInfo omap2_gpio_info = {
65
index XXXXXXX..XXXXXXX 100644
124
.name = TYPE_OMAP2_GPIO,
66
--- a/target/s390x/diag.c
125
.parent = TYPE_SYS_BUS_DEVICE,
67
+++ b/target/s390x/diag.c
126
- .instance_size = sizeof(struct omap2_gpif_s),
68
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
127
+ .instance_size = sizeof(Omap2GpioState),
69
return;
128
.class_init = omap2_gpio_class_init,
70
}
129
};
71
if (!address_space_access_valid(&address_space_memory, addr,
130
72
- sizeof(IplParameterBlock), false)) {
73
+ sizeof(IplParameterBlock), false,
74
+ MEMTXATTRS_UNSPECIFIED)) {
75
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
76
return;
77
}
78
@@ -XXX,XX +XXX,XX @@ out:
79
return;
80
}
81
if (!address_space_access_valid(&address_space_memory, addr,
82
- sizeof(IplParameterBlock), true)) {
83
+ sizeof(IplParameterBlock), true,
84
+ MEMTXATTRS_UNSPECIFIED)) {
85
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
86
return;
87
}
88
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/s390x/excp_helper.c
91
+++ b/target/s390x/excp_helper.c
92
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
93
94
/* check out of RAM access */
95
if (!address_space_access_valid(&address_space_memory, raddr,
96
- TARGET_PAGE_SIZE, rw)) {
97
+ TARGET_PAGE_SIZE, rw,
98
+ MEMTXATTRS_UNSPECIFIED)) {
99
DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
100
(uint64_t)raddr, (uint64_t)ram_size);
101
trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
102
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/s390x/mmu_helper.c
105
+++ b/target/s390x/mmu_helper.c
106
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
107
return ret;
108
}
109
if (!address_space_access_valid(&address_space_memory, pages[i],
110
- TARGET_PAGE_SIZE, is_write)) {
111
+ TARGET_PAGE_SIZE, is_write,
112
+ MEMTXATTRS_UNSPECIFIED)) {
113
trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
114
return -EFAULT;
115
}
116
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/s390x/sigp.c
119
+++ b/target/s390x/sigp.c
120
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
121
cpu_synchronize_state(cs);
122
123
if (!address_space_access_valid(&address_space_memory, addr,
124
- sizeof(struct LowCore), false)) {
125
+ sizeof(struct LowCore), false,
126
+ MEMTXATTRS_UNSPECIFIED)) {
127
set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
128
return;
129
}
130
--
131
--
131
2.17.1
132
2.34.1
132
133
133
134
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
Following docs/devel/style.rst guidelines, rename
4
omap_intr_handler_s -> OMAPIntcState. This also remove a
5
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-7-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/omap.h | 9 ++++-----
13
hw/intc/omap_intc.c | 38 +++++++++++++++++++-------------------
14
2 files changed, 23 insertions(+), 24 deletions(-)
15
16
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/omap.h
19
+++ b/include/hw/arm/omap.h
20
@@ -XXX,XX +XXX,XX @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
21
22
/* omap_intc.c */
23
#define TYPE_OMAP_INTC "common-omap-intc"
24
-typedef struct omap_intr_handler_s omap_intr_handler;
25
-DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
26
- TYPE_OMAP_INTC)
27
+typedef struct OMAPIntcState OMAPIntcState;
28
+DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC)
29
30
31
/*
32
@@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(omap_intr_handler, OMAP_INTC,
33
* (ie the struct omap_mpu_state_s*) to do the clockname to pointer
34
* translation.)
35
*/
36
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk);
37
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
38
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk);
39
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk);
40
41
/* omap_i2c.c */
42
#define TYPE_OMAP_I2C "omap_i2c"
43
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/intc/omap_intc.c
46
+++ b/hw/intc/omap_intc.c
47
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_bank_s {
48
unsigned char priority[32];
49
};
50
51
-struct omap_intr_handler_s {
52
+struct OMAPIntcState {
53
SysBusDevice parent_obj;
54
55
qemu_irq *pins;
56
@@ -XXX,XX +XXX,XX @@ struct omap_intr_handler_s {
57
struct omap_intr_handler_bank_s bank[3];
58
};
59
60
-static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
61
+static void omap_inth_sir_update(OMAPIntcState *s, int is_fiq)
62
{
63
int i, j, sir_intr, p_intr, p;
64
uint32_t level;
65
@@ -XXX,XX +XXX,XX @@ static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
66
s->sir_intr[is_fiq] = sir_intr;
67
}
68
69
-static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
70
+static inline void omap_inth_update(OMAPIntcState *s, int is_fiq)
71
{
72
int i;
73
uint32_t has_intr = 0;
74
@@ -XXX,XX +XXX,XX @@ static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
75
76
static void omap_set_intr(void *opaque, int irq, int req)
77
{
78
- struct omap_intr_handler_s *ih = opaque;
79
+ OMAPIntcState *ih = opaque;
80
uint32_t rise;
81
82
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
83
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr(void *opaque, int irq, int req)
84
/* Simplified version with no edge detection */
85
static void omap_set_intr_noedge(void *opaque, int irq, int req)
86
{
87
- struct omap_intr_handler_s *ih = opaque;
88
+ OMAPIntcState *ih = opaque;
89
uint32_t rise;
90
91
struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
92
@@ -XXX,XX +XXX,XX @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
93
static uint64_t omap_inth_read(void *opaque, hwaddr addr,
94
unsigned size)
95
{
96
- struct omap_intr_handler_s *s = opaque;
97
+ OMAPIntcState *s = opaque;
98
int i, offset = addr;
99
int bank_no = offset >> 8;
100
int line_no;
101
@@ -XXX,XX +XXX,XX @@ static uint64_t omap_inth_read(void *opaque, hwaddr addr,
102
static void omap_inth_write(void *opaque, hwaddr addr,
103
uint64_t value, unsigned size)
104
{
105
- struct omap_intr_handler_s *s = opaque;
106
+ OMAPIntcState *s = opaque;
107
int i, offset = addr;
108
int bank_no = offset >> 8;
109
struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
110
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap_inth_mem_ops = {
111
112
static void omap_inth_reset(DeviceState *dev)
113
{
114
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
115
+ OMAPIntcState *s = OMAP_INTC(dev);
116
int i;
117
118
for (i = 0; i < s->nbanks; ++i){
119
@@ -XXX,XX +XXX,XX @@ static void omap_inth_reset(DeviceState *dev)
120
static void omap_intc_init(Object *obj)
121
{
122
DeviceState *dev = DEVICE(obj);
123
- struct omap_intr_handler_s *s = OMAP_INTC(obj);
124
+ OMAPIntcState *s = OMAP_INTC(obj);
125
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
126
127
s->nbanks = 1;
128
@@ -XXX,XX +XXX,XX @@ static void omap_intc_init(Object *obj)
129
130
static void omap_intc_realize(DeviceState *dev, Error **errp)
131
{
132
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
133
+ OMAPIntcState *s = OMAP_INTC(dev);
134
135
if (!s->iclk) {
136
error_setg(errp, "omap-intc: clk not connected");
137
}
138
}
139
140
-void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk)
141
+void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk)
142
{
143
intc->iclk = clk;
144
}
145
146
-void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk)
147
+void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk)
148
{
149
intc->fclk = clk;
150
}
151
152
static Property omap_intc_properties[] = {
153
- DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
154
+ DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100),
155
DEFINE_PROP_END_OF_LIST(),
156
};
157
158
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap_intc_info = {
159
static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
160
unsigned size)
161
{
162
- struct omap_intr_handler_s *s = opaque;
163
+ OMAPIntcState *s = opaque;
164
int offset = addr;
165
int bank_no, line_no;
166
struct omap_intr_handler_bank_s *bank = NULL;
167
@@ -XXX,XX +XXX,XX @@ static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
168
static void omap2_inth_write(void *opaque, hwaddr addr,
169
uint64_t value, unsigned size)
170
{
171
- struct omap_intr_handler_s *s = opaque;
172
+ OMAPIntcState *s = opaque;
173
int offset = addr;
174
int bank_no, line_no;
175
struct omap_intr_handler_bank_s *bank = NULL;
176
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps omap2_inth_mem_ops = {
177
static void omap2_intc_init(Object *obj)
178
{
179
DeviceState *dev = DEVICE(obj);
180
- struct omap_intr_handler_s *s = OMAP_INTC(obj);
181
+ OMAPIntcState *s = OMAP_INTC(obj);
182
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
183
184
s->level_only = 1;
185
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_init(Object *obj)
186
187
static void omap2_intc_realize(DeviceState *dev, Error **errp)
188
{
189
- struct omap_intr_handler_s *s = OMAP_INTC(dev);
190
+ OMAPIntcState *s = OMAP_INTC(dev);
191
192
if (!s->iclk) {
193
error_setg(errp, "omap2-intc: iclk not connected");
194
@@ -XXX,XX +XXX,XX @@ static void omap2_intc_realize(DeviceState *dev, Error **errp)
195
}
196
197
static Property omap2_intc_properties[] = {
198
- DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
199
+ DEFINE_PROP_UINT8("revision", OMAPIntcState,
200
revision, 0x21),
201
DEFINE_PROP_END_OF_LIST(),
202
};
203
@@ -XXX,XX +XXX,XX @@ static const TypeInfo omap2_intc_info = {
204
static const TypeInfo omap_intc_type_info = {
205
.name = TYPE_OMAP_INTC,
206
.parent = TYPE_SYS_BUS_DEVICE,
207
- .instance_size = sizeof(omap_intr_handler),
208
+ .instance_size = sizeof(OMAPIntcState),
209
.abstract = true,
210
};
211
212
--
213
2.34.1
214
215
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to address_space_translate()
3
and address_space_translate_cached(). Callers either have an
4
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
5
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20230109140306.23161-8-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
10
---
7
---
11
include/exec/memory.h | 4 +++-
8
hw/arm/stellaris.c | 6 +++---
12
accel/tcg/translate-all.c | 2 +-
9
1 file changed, 3 insertions(+), 3 deletions(-)
13
exec.c | 14 +++++++++-----
14
hw/vfio/common.c | 3 ++-
15
memory_ldst.inc.c | 18 +++++++++---------
16
target/riscv/helper.c | 2 +-
17
6 files changed, 25 insertions(+), 18 deletions(-)
18
10
19
diff --git a/include/exec/memory.h b/include/exec/memory.h
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/memory.h
13
--- a/hw/arm/stellaris.c
22
+++ b/include/exec/memory.h
14
+++ b/hw/arm/stellaris.c
23
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
15
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
24
* #MemoryRegion.
16
25
* @len: pointer to length
17
static void stellaris_adc_trigger(void *opaque, int irq, int level)
26
* @is_write: indicates the transfer direction
27
+ * @attrs: memory attributes
28
*/
29
MemoryRegion *flatview_translate(FlatView *fv,
30
hwaddr addr, hwaddr *xlat,
31
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
32
33
static inline MemoryRegion *address_space_translate(AddressSpace *as,
34
hwaddr addr, hwaddr *xlat,
35
- hwaddr *len, bool is_write)
36
+ hwaddr *len, bool is_write,
37
+ MemTxAttrs attrs)
38
{
18
{
39
return flatview_translate(address_space_to_flatview(as),
19
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
40
addr, xlat, len, is_write);
20
+ stellaris_adc_state *s = opaque;
41
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
21
int n;
42
index XXXXXXX..XXXXXXX 100644
22
43
--- a/accel/tcg/translate-all.c
23
for (n = 0; n < 4; n++) {
44
+++ b/accel/tcg/translate-all.c
24
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
45
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
25
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
46
hwaddr l = 1;
26
unsigned size)
47
48
rcu_read_lock();
49
- mr = address_space_translate(as, addr, &addr, &l, false);
50
+ mr = address_space_translate(as, addr, &addr, &l, false, attrs);
51
if (!(memory_region_is_ram(mr)
52
|| memory_region_is_romd(mr))) {
53
rcu_read_unlock();
54
diff --git a/exec.c b/exec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/exec.c
57
+++ b/exec.c
58
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
59
rcu_read_lock();
60
while (len > 0) {
61
l = len;
62
- mr = address_space_translate(as, addr, &addr1, &l, true);
63
+ mr = address_space_translate(as, addr, &addr1, &l, true,
64
+ MEMTXATTRS_UNSPECIFIED);
65
66
if (!(memory_region_is_ram(mr) ||
67
memory_region_is_romd(mr))) {
68
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
69
*/
70
static inline MemoryRegion *address_space_translate_cached(
71
MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
72
- hwaddr *plen, bool is_write)
73
+ hwaddr *plen, bool is_write, MemTxAttrs attrs)
74
{
27
{
75
MemoryRegionSection section;
28
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
76
MemoryRegion *mr;
29
+ stellaris_adc_state *s = opaque;
77
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
30
78
MemoryRegion *mr;
31
/* TODO: Implement this. */
79
32
if (offset >= 0x40 && offset < 0xc0) {
80
l = len;
33
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
81
- mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
34
static void stellaris_adc_write(void *opaque, hwaddr offset,
82
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
35
uint64_t value, unsigned size)
83
+ MEMTXATTRS_UNSPECIFIED);
36
{
84
flatview_read_continue(cache->fv,
37
- stellaris_adc_state *s = (stellaris_adc_state *)opaque;
85
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
38
+ stellaris_adc_state *s = opaque;
86
addr1, l, mr);
39
87
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
40
/* TODO: Implement this. */
88
MemoryRegion *mr;
41
if (offset >= 0x40 && offset < 0xc0) {
89
90
l = len;
91
- mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
92
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
93
+ MEMTXATTRS_UNSPECIFIED);
94
flatview_write_continue(cache->fv,
95
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
96
addr1, l, mr);
97
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
98
99
rcu_read_lock();
100
mr = address_space_translate(&address_space_memory,
101
- phys_addr, &phys_addr, &l, false);
102
+ phys_addr, &phys_addr, &l, false,
103
+ MEMTXATTRS_UNSPECIFIED);
104
105
res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
106
rcu_read_unlock();
107
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/vfio/common.c
110
+++ b/hw/vfio/common.c
111
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
112
*/
113
mr = address_space_translate(&address_space_memory,
114
iotlb->translated_addr,
115
- &xlat, &len, writable);
116
+ &xlat, &len, writable,
117
+ MEMTXATTRS_UNSPECIFIED);
118
if (!memory_region_is_ram(mr)) {
119
error_report("iommu map to non memory area %"HWADDR_PRIx"",
120
xlat);
121
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/memory_ldst.inc.c
124
+++ b/memory_ldst.inc.c
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
126
bool release_lock = false;
127
128
RCU_READ_LOCK();
129
- mr = TRANSLATE(addr, &addr1, &l, false);
130
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
131
if (l < 4 || !IS_DIRECT(mr, false)) {
132
release_lock |= prepare_mmio_access(mr);
133
134
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
135
bool release_lock = false;
136
137
RCU_READ_LOCK();
138
- mr = TRANSLATE(addr, &addr1, &l, false);
139
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
140
if (l < 8 || !IS_DIRECT(mr, false)) {
141
release_lock |= prepare_mmio_access(mr);
142
143
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
144
bool release_lock = false;
145
146
RCU_READ_LOCK();
147
- mr = TRANSLATE(addr, &addr1, &l, false);
148
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
149
if (!IS_DIRECT(mr, false)) {
150
release_lock |= prepare_mmio_access(mr);
151
152
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
153
bool release_lock = false;
154
155
RCU_READ_LOCK();
156
- mr = TRANSLATE(addr, &addr1, &l, false);
157
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
158
if (l < 2 || !IS_DIRECT(mr, false)) {
159
release_lock |= prepare_mmio_access(mr);
160
161
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
162
bool release_lock = false;
163
164
RCU_READ_LOCK();
165
- mr = TRANSLATE(addr, &addr1, &l, true);
166
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
167
if (l < 4 || !IS_DIRECT(mr, true)) {
168
release_lock |= prepare_mmio_access(mr);
169
170
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
171
bool release_lock = false;
172
173
RCU_READ_LOCK();
174
- mr = TRANSLATE(addr, &addr1, &l, true);
175
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
176
if (l < 4 || !IS_DIRECT(mr, true)) {
177
release_lock |= prepare_mmio_access(mr);
178
179
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
180
bool release_lock = false;
181
182
RCU_READ_LOCK();
183
- mr = TRANSLATE(addr, &addr1, &l, true);
184
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
185
if (!IS_DIRECT(mr, true)) {
186
release_lock |= prepare_mmio_access(mr);
187
r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
188
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
189
bool release_lock = false;
190
191
RCU_READ_LOCK();
192
- mr = TRANSLATE(addr, &addr1, &l, true);
193
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
194
if (l < 2 || !IS_DIRECT(mr, true)) {
195
release_lock |= prepare_mmio_access(mr);
196
197
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
198
bool release_lock = false;
199
200
RCU_READ_LOCK();
201
- mr = TRANSLATE(addr, &addr1, &l, true);
202
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
203
if (l < 8 || !IS_DIRECT(mr, true)) {
204
release_lock |= prepare_mmio_access(mr);
205
206
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
207
index XXXXXXX..XXXXXXX 100644
208
--- a/target/riscv/helper.c
209
+++ b/target/riscv/helper.c
210
@@ -XXX,XX +XXX,XX @@ restart:
211
MemoryRegion *mr;
212
hwaddr l = sizeof(target_ulong), addr1;
213
mr = address_space_translate(cs->as, pte_addr,
214
- &addr1, &l, false);
215
+ &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
216
if (memory_access_is_direct(mr, true)) {
217
target_ulong *pte_pa =
218
qemu_map_ram_ptr(mr->ram_block, addr1);
219
--
42
--
220
2.17.1
43
2.34.1
221
44
222
45
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
3
callback. We'll need this for subpage_accepts().
4
2
5
We could take the approach we used with the read and write
3
Following docs/devel/style.rst guidelines, rename
6
callbacks and add new a new _with_attrs version, but since there
4
stellaris_adc_state -> StellarisADCState. This also remove a
7
are so few implementations of the accepts hook we just change
5
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
8
them all.
9
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-9-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
14
---
11
---
15
include/exec/memory.h | 3 ++-
12
hw/arm/stellaris.c | 73 +++++++++++++++++++++++-----------------------
16
exec.c | 9 ++++++---
13
1 file changed, 36 insertions(+), 37 deletions(-)
17
hw/hppa/dino.c | 3 ++-
18
hw/nvram/fw_cfg.c | 12 ++++++++----
19
hw/scsi/esp.c | 3 ++-
20
hw/xen/xen_pt_msi.c | 3 ++-
21
memory.c | 5 +++--
22
7 files changed, 25 insertions(+), 13 deletions(-)
23
14
24
diff --git a/include/exec/memory.h b/include/exec/memory.h
15
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
25
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
26
--- a/include/exec/memory.h
17
--- a/hw/arm/stellaris.c
27
+++ b/include/exec/memory.h
18
+++ b/hw/arm/stellaris.c
28
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
19
@@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj)
29
* as a machine check exception).
20
#define STELLARIS_ADC_FIFO_FULL 0x1000
30
*/
21
31
bool (*accepts)(void *opaque, hwaddr addr,
22
#define TYPE_STELLARIS_ADC "stellaris-adc"
32
- unsigned size, bool is_write);
23
-typedef struct StellarisADCState stellaris_adc_state;
33
+ unsigned size, bool is_write,
24
-DECLARE_INSTANCE_CHECKER(stellaris_adc_state, STELLARIS_ADC,
34
+ MemTxAttrs attrs);
25
- TYPE_STELLARIS_ADC)
35
} valid;
26
+typedef struct StellarisADCState StellarisADCState;
36
/* Internal implementation constraints: */
27
+DECLARE_INSTANCE_CHECKER(StellarisADCState, STELLARIS_ADC, TYPE_STELLARIS_ADC)
37
struct {
28
38
diff --git a/exec.c b/exec.c
29
struct StellarisADCState {
39
index XXXXXXX..XXXXXXX 100644
30
SysBusDevice parent_obj;
40
--- a/exec.c
31
@@ -XXX,XX +XXX,XX @@ struct StellarisADCState {
41
+++ b/exec.c
32
qemu_irq irq[4];
42
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
33
};
34
35
-static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
36
+static uint32_t stellaris_adc_fifo_read(StellarisADCState *s, int n)
37
{
38
int tail;
39
40
@@ -XXX,XX +XXX,XX @@ static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
41
return s->fifo[n].data[tail];
43
}
42
}
44
43
45
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
44
-static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
46
- unsigned size, bool is_write)
45
+static void stellaris_adc_fifo_write(StellarisADCState *s, int n,
47
+ unsigned size, bool is_write,
46
uint32_t value)
48
+ MemTxAttrs attrs)
49
{
47
{
50
return is_write;
48
int head;
49
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
50
s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
51
}
51
}
52
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
52
53
-static void stellaris_adc_update(stellaris_adc_state *s)
54
+static void stellaris_adc_update(StellarisADCState *s)
55
{
56
int level;
57
int n;
58
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_update(stellaris_adc_state *s)
59
60
static void stellaris_adc_trigger(void *opaque, int irq, int level)
61
{
62
- stellaris_adc_state *s = opaque;
63
+ StellarisADCState *s = opaque;
64
int n;
65
66
for (n = 0; n < 4; n++) {
67
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level)
68
}
53
}
69
}
54
70
55
static bool subpage_accepts(void *opaque, hwaddr addr,
71
-static void stellaris_adc_reset(stellaris_adc_state *s)
56
- unsigned len, bool is_write)
72
+static void stellaris_adc_reset(StellarisADCState *s)
57
+ unsigned len, bool is_write,
58
+ MemTxAttrs attrs)
59
{
73
{
60
subpage_t *subpage = opaque;
74
int n;
61
#if defined(DEBUG_SUBPAGE)
75
62
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
76
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_reset(stellaris_adc_state *s)
63
}
77
static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
64
78
unsigned size)
65
static bool readonly_mem_accepts(void *opaque, hwaddr addr,
66
- unsigned size, bool is_write)
67
+ unsigned size, bool is_write,
68
+ MemTxAttrs attrs)
69
{
79
{
70
return is_write;
80
- stellaris_adc_state *s = opaque;
71
}
81
+ StellarisADCState *s = opaque;
72
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
82
73
index XXXXXXX..XXXXXXX 100644
83
/* TODO: Implement this. */
74
--- a/hw/hppa/dino.c
84
if (offset >= 0x40 && offset < 0xc0) {
75
+++ b/hw/hppa/dino.c
85
@@ -XXX,XX +XXX,XX @@ static uint64_t stellaris_adc_read(void *opaque, hwaddr offset,
76
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
86
static void stellaris_adc_write(void *opaque, hwaddr offset,
77
}
87
uint64_t value, unsigned size)
78
79
static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
80
- unsigned size, bool is_write)
81
+ unsigned size, bool is_write,
82
+ MemTxAttrs attrs)
83
{
88
{
84
switch (addr) {
89
- stellaris_adc_state *s = opaque;
85
case DINO_IAR0:
90
+ StellarisADCState *s = opaque;
86
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
91
87
index XXXXXXX..XXXXXXX 100644
92
/* TODO: Implement this. */
88
--- a/hw/nvram/fw_cfg.c
93
if (offset >= 0x40 && offset < 0xc0) {
89
+++ b/hw/nvram/fw_cfg.c
94
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
90
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
95
.version_id = 1,
91
}
96
.minimum_version_id = 1,
92
97
.fields = (VMStateField[]) {
93
static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
98
- VMSTATE_UINT32(actss, stellaris_adc_state),
94
- unsigned size, bool is_write)
99
- VMSTATE_UINT32(ris, stellaris_adc_state),
95
+ unsigned size, bool is_write,
100
- VMSTATE_UINT32(im, stellaris_adc_state),
96
+ MemTxAttrs attrs)
101
- VMSTATE_UINT32(emux, stellaris_adc_state),
102
- VMSTATE_UINT32(ostat, stellaris_adc_state),
103
- VMSTATE_UINT32(ustat, stellaris_adc_state),
104
- VMSTATE_UINT32(sspri, stellaris_adc_state),
105
- VMSTATE_UINT32(sac, stellaris_adc_state),
106
- VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
107
- VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
108
- VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
109
- VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
110
- VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
111
- VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
112
- VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
113
- VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
114
- VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
115
- VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
116
- VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
117
- VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
118
- VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
119
- VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
120
- VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
121
- VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
122
- VMSTATE_UINT32(noise, stellaris_adc_state),
123
+ VMSTATE_UINT32(actss, StellarisADCState),
124
+ VMSTATE_UINT32(ris, StellarisADCState),
125
+ VMSTATE_UINT32(im, StellarisADCState),
126
+ VMSTATE_UINT32(emux, StellarisADCState),
127
+ VMSTATE_UINT32(ostat, StellarisADCState),
128
+ VMSTATE_UINT32(ustat, StellarisADCState),
129
+ VMSTATE_UINT32(sspri, StellarisADCState),
130
+ VMSTATE_UINT32(sac, StellarisADCState),
131
+ VMSTATE_UINT32(fifo[0].state, StellarisADCState),
132
+ VMSTATE_UINT32_ARRAY(fifo[0].data, StellarisADCState, 16),
133
+ VMSTATE_UINT32(ssmux[0], StellarisADCState),
134
+ VMSTATE_UINT32(ssctl[0], StellarisADCState),
135
+ VMSTATE_UINT32(fifo[1].state, StellarisADCState),
136
+ VMSTATE_UINT32_ARRAY(fifo[1].data, StellarisADCState, 16),
137
+ VMSTATE_UINT32(ssmux[1], StellarisADCState),
138
+ VMSTATE_UINT32(ssctl[1], StellarisADCState),
139
+ VMSTATE_UINT32(fifo[2].state, StellarisADCState),
140
+ VMSTATE_UINT32_ARRAY(fifo[2].data, StellarisADCState, 16),
141
+ VMSTATE_UINT32(ssmux[2], StellarisADCState),
142
+ VMSTATE_UINT32(ssctl[2], StellarisADCState),
143
+ VMSTATE_UINT32(fifo[3].state, StellarisADCState),
144
+ VMSTATE_UINT32_ARRAY(fifo[3].data, StellarisADCState, 16),
145
+ VMSTATE_UINT32(ssmux[3], StellarisADCState),
146
+ VMSTATE_UINT32(ssctl[3], StellarisADCState),
147
+ VMSTATE_UINT32(noise, StellarisADCState),
148
VMSTATE_END_OF_LIST()
149
}
150
};
151
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_stellaris_adc = {
152
static void stellaris_adc_init(Object *obj)
97
{
153
{
98
return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
154
DeviceState *dev = DEVICE(obj);
99
(size == 8 && addr == 0));
155
- stellaris_adc_state *s = STELLARIS_ADC(obj);
100
}
156
+ StellarisADCState *s = STELLARIS_ADC(obj);
101
157
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
102
static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
158
int n;
103
- unsigned size, bool is_write)
159
104
+ unsigned size, bool is_write,
160
@@ -XXX,XX +XXX,XX @@ static void stellaris_adc_class_init(ObjectClass *klass, void *data)
105
+ MemTxAttrs attrs)
161
static const TypeInfo stellaris_adc_info = {
106
{
162
.name = TYPE_STELLARIS_ADC,
107
return addr == 0;
163
.parent = TYPE_SYS_BUS_DEVICE,
108
}
164
- .instance_size = sizeof(stellaris_adc_state),
109
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
165
+ .instance_size = sizeof(StellarisADCState),
110
}
166
.instance_init = stellaris_adc_init,
111
167
.class_init = stellaris_adc_class_init,
112
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
168
};
113
- unsigned size, bool is_write)
114
+ unsigned size, bool is_write,
115
+ MemTxAttrs attrs)
116
{
117
return is_write && size == 2;
118
}
119
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
120
}
121
122
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
123
- unsigned size, bool is_write)
124
+ unsigned size, bool is_write,
125
+ MemTxAttrs attrs)
126
{
127
return (size == 1) || (is_write && size == 2);
128
}
129
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/scsi/esp.c
132
+++ b/hw/scsi/esp.c
133
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
134
}
135
136
static bool esp_mem_accepts(void *opaque, hwaddr addr,
137
- unsigned size, bool is_write)
138
+ unsigned size, bool is_write,
139
+ MemTxAttrs attrs)
140
{
141
return (size == 1) || (is_write && size == 4);
142
}
143
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/xen/xen_pt_msi.c
146
+++ b/hw/xen/xen_pt_msi.c
147
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
148
}
149
150
static bool pci_msix_accepts(void *opaque, hwaddr addr,
151
- unsigned size, bool is_write)
152
+ unsigned size, bool is_write,
153
+ MemTxAttrs attrs)
154
{
155
return !(addr & (size - 1));
156
}
157
diff --git a/memory.c b/memory.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/memory.c
160
+++ b/memory.c
161
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
162
}
163
164
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
165
- unsigned size, bool is_write)
166
+ unsigned size, bool is_write,
167
+ MemTxAttrs attrs)
168
{
169
return false;
170
}
171
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
172
access_size = MAX(MIN(size, access_size_max), access_size_min);
173
for (i = 0; i < size; i += access_size) {
174
if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
175
- is_write)) {
176
+ is_write, attrs)) {
177
return false;
178
}
179
}
180
--
169
--
181
2.17.1
170
2.34.1
182
171
183
172
diff view generated by jsdifflib
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
It forgot to increase clroffset during the loop. So it only clear the
3
The typedef and definitions are generated by the OBJECT_DECLARE_TYPE
4
first 4 bytes.
4
macro in "hw/arm/bcm2836.h":
5
5
6
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
6
20 #define TYPE_BCM283X "bcm283x"
7
Cc: qemu-stable@nongnu.org
7
21 OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X)
8
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
8
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
The script ran in commit a489d1951c ("Use OBJECT_DECLARE_TYPE when
10
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
10
possible") missed them because they are declared in a different
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
file unit. Remove them.
12
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20230109140306.23161-10-philmd@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
17
---
14
hw/intc/arm_gicv3_kvm.c | 1 +
18
hw/arm/bcm2836.c | 9 ++-------
15
1 file changed, 1 insertion(+)
19
1 file changed, 2 insertions(+), 7 deletions(-)
16
20
17
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
21
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
18
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/arm_gicv3_kvm.c
23
--- a/hw/arm/bcm2836.c
20
+++ b/hw/intc/arm_gicv3_kvm.c
24
+++ b/hw/arm/bcm2836.c
21
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
25
@@ -XXX,XX +XXX,XX @@
22
if (clroffset != 0) {
26
#include "hw/arm/raspi_platform.h"
23
reg = 0;
27
#include "hw/sysbus.h"
24
kvm_gicd_access(s, clroffset, &reg, true);
28
25
+ clroffset += 4;
29
-typedef struct BCM283XClass {
26
}
30
+struct BCM283XClass {
27
reg = *gic_bmp_ptr32(bmp, irq);
31
/*< private >*/
28
kvm_gicd_access(s, offset, &reg, true);
32
DeviceClass parent_class;
33
/*< public >*/
34
@@ -XXX,XX +XXX,XX @@ typedef struct BCM283XClass {
35
hwaddr peri_base; /* Peripheral base address seen by the CPU */
36
hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */
37
int clusterid;
38
-} BCM283XClass;
39
-
40
-#define BCM283X_CLASS(klass) \
41
- OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
42
-#define BCM283X_GET_CLASS(obj) \
43
- OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X)
44
+};
45
46
static Property bcm2836_enabled_cores_property =
47
DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0);
29
--
48
--
30
2.17.1
49
2.34.1
31
50
32
51
diff view generated by jsdifflib
New patch
1
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
3
NPCM7XX models have been commited after the conversion from
4
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
5
Manually convert them.
6
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230109140306.23161-11-philmd@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/adc/npcm7xx_adc.h | 7 +++----
13
include/hw/arm/npcm7xx.h | 18 ++++++------------
14
include/hw/i2c/npcm7xx_smbus.h | 7 +++----
15
include/hw/misc/npcm7xx_clk.h | 2 +-
16
include/hw/misc/npcm7xx_gcr.h | 6 +++---
17
include/hw/misc/npcm7xx_mft.h | 7 +++----
18
include/hw/misc/npcm7xx_pwm.h | 3 +--
19
include/hw/misc/npcm7xx_rng.h | 6 +++---
20
include/hw/net/npcm7xx_emc.h | 5 +----
21
include/hw/sd/npcm7xx_sdhci.h | 4 ++--
22
10 files changed, 26 insertions(+), 39 deletions(-)
23
24
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/adc/npcm7xx_adc.h
27
+++ b/include/hw/adc/npcm7xx_adc.h
28
@@ -XXX,XX +XXX,XX @@
29
* @iref: The internal reference voltage, initialized at launch time.
30
* @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
31
*/
32
-typedef struct {
33
+struct NPCM7xxADCState {
34
SysBusDevice parent;
35
36
MemoryRegion iomem;
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
uint32_t iref;
39
40
uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
41
-} NPCM7xxADCState;
42
+};
43
44
#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
45
-#define NPCM7XX_ADC(obj) \
46
- OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
47
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
48
49
#endif /* NPCM7XX_ADC_H */
50
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
51
index XXXXXXX..XXXXXXX 100644
52
--- a/include/hw/arm/npcm7xx.h
53
+++ b/include/hw/arm/npcm7xx.h
54
@@ -XXX,XX +XXX,XX @@
55
56
#define NPCM7XX_NR_PWM_MODULES 2
57
58
-typedef struct NPCM7xxMachine {
59
+struct NPCM7xxMachine {
60
MachineState parent;
61
/*
62
* PWM fan splitter. each splitter connects to one PWM output and
63
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachine {
64
*/
65
SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES *
66
NPCM7XX_PWM_PER_MODULE];
67
-} NPCM7xxMachine;
68
+};
69
70
#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
71
-#define NPCM7XX_MACHINE(obj) \
72
- OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
73
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
74
75
typedef struct NPCM7xxMachineClass {
76
MachineClass parent;
77
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMachineClass {
78
#define NPCM7XX_MACHINE_GET_CLASS(obj) \
79
OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
80
81
-typedef struct NPCM7xxState {
82
+struct NPCM7xxState {
83
DeviceState parent;
84
85
ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
86
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
87
NPCM7xxFIUState fiu[2];
88
NPCM7xxEMCState emc[2];
89
NPCM7xxSDHCIState mmc;
90
-} NPCM7xxState;
91
+};
92
93
#define TYPE_NPCM7XX "npcm7xx"
94
-#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
95
+OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
96
97
#define TYPE_NPCM730 "npcm730"
98
#define TYPE_NPCM750 "npcm750"
99
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxClass {
100
uint32_t num_cpus;
101
} NPCM7xxClass;
102
103
-#define NPCM7XX_CLASS(klass) \
104
- OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
105
-#define NPCM7XX_GET_CLASS(obj) \
106
- OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
107
-
108
/**
109
* npcm7xx_load_kernel - Loads memory with everything needed to boot
110
* @machine - The machine containing the SoC to be booted.
111
diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h
112
index XXXXXXX..XXXXXXX 100644
113
--- a/include/hw/i2c/npcm7xx_smbus.h
114
+++ b/include/hw/i2c/npcm7xx_smbus.h
115
@@ -XXX,XX +XXX,XX @@ typedef enum NPCM7xxSMBusStatus {
116
* @rx_cur: The current position of rx_fifo.
117
* @status: The current status of the SMBus.
118
*/
119
-typedef struct NPCM7xxSMBusState {
120
+struct NPCM7xxSMBusState {
121
SysBusDevice parent;
122
123
MemoryRegion iomem;
124
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSMBusState {
125
uint8_t rx_cur;
126
127
NPCM7xxSMBusStatus status;
128
-} NPCM7xxSMBusState;
129
+};
130
131
#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
132
-#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
133
- TYPE_NPCM7XX_SMBUS)
134
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
135
136
#endif /* NPCM7XX_SMBUS_H */
137
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/misc/npcm7xx_clk.h
140
+++ b/include/hw/misc/npcm7xx_clk.h
141
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxCLKState {
142
};
143
144
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
145
-#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
146
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
147
148
#endif /* NPCM7XX_CLK_H */
149
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
150
index XXXXXXX..XXXXXXX 100644
151
--- a/include/hw/misc/npcm7xx_gcr.h
152
+++ b/include/hw/misc/npcm7xx_gcr.h
153
@@ -XXX,XX +XXX,XX @@
154
*/
155
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
156
157
-typedef struct NPCM7xxGCRState {
158
+struct NPCM7xxGCRState {
159
SysBusDevice parent;
160
161
MemoryRegion iomem;
162
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxGCRState {
163
uint32_t reset_pwron;
164
uint32_t reset_mdlr;
165
uint32_t reset_intcr3;
166
-} NPCM7xxGCRState;
167
+};
168
169
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
170
-#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
171
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
172
173
#endif /* NPCM7XX_GCR_H */
174
diff --git a/include/hw/misc/npcm7xx_mft.h b/include/hw/misc/npcm7xx_mft.h
175
index XXXXXXX..XXXXXXX 100644
176
--- a/include/hw/misc/npcm7xx_mft.h
177
+++ b/include/hw/misc/npcm7xx_mft.h
178
@@ -XXX,XX +XXX,XX @@
179
* @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
180
* @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
181
*/
182
-typedef struct NPCM7xxMFTState {
183
+struct NPCM7xxMFTState {
184
SysBusDevice parent;
185
186
MemoryRegion iomem;
187
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxMFTState {
188
189
uint32_t max_rpm[NPCM7XX_MFT_FANIN_COUNT];
190
uint32_t duty[NPCM7XX_MFT_FANIN_COUNT];
191
-} NPCM7xxMFTState;
192
+};
193
194
#define TYPE_NPCM7XX_MFT "npcm7xx-mft"
195
-#define NPCM7XX_MFT(obj) \
196
- OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
197
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT)
198
199
#endif /* NPCM7XX_MFT_H */
200
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
201
index XXXXXXX..XXXXXXX 100644
202
--- a/include/hw/misc/npcm7xx_pwm.h
203
+++ b/include/hw/misc/npcm7xx_pwm.h
204
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxPWMState {
205
};
206
207
#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
208
-#define NPCM7XX_PWM(obj) \
209
- OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
210
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
211
212
#endif /* NPCM7XX_PWM_H */
213
diff --git a/include/hw/misc/npcm7xx_rng.h b/include/hw/misc/npcm7xx_rng.h
214
index XXXXXXX..XXXXXXX 100644
215
--- a/include/hw/misc/npcm7xx_rng.h
216
+++ b/include/hw/misc/npcm7xx_rng.h
217
@@ -XXX,XX +XXX,XX @@
218
219
#include "hw/sysbus.h"
220
221
-typedef struct NPCM7xxRNGState {
222
+struct NPCM7xxRNGState {
223
SysBusDevice parent;
224
225
MemoryRegion iomem;
226
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRNGState {
227
uint8_t rngcs;
228
uint8_t rngd;
229
uint8_t rngmode;
230
-} NPCM7xxRNGState;
231
+};
232
233
#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
234
-#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
235
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG)
236
237
#endif /* NPCM7XX_RNG_H */
238
diff --git a/include/hw/net/npcm7xx_emc.h b/include/hw/net/npcm7xx_emc.h
239
index XXXXXXX..XXXXXXX 100644
240
--- a/include/hw/net/npcm7xx_emc.h
241
+++ b/include/hw/net/npcm7xx_emc.h
242
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxEMCState {
243
bool rx_active;
244
};
245
246
-typedef struct NPCM7xxEMCState NPCM7xxEMCState;
247
-
248
#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
249
-#define NPCM7XX_EMC(obj) \
250
- OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
251
+OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
252
253
#endif /* NPCM7XX_EMC_H */
254
diff --git a/include/hw/sd/npcm7xx_sdhci.h b/include/hw/sd/npcm7xx_sdhci.h
255
index XXXXXXX..XXXXXXX 100644
256
--- a/include/hw/sd/npcm7xx_sdhci.h
257
+++ b/include/hw/sd/npcm7xx_sdhci.h
258
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxRegs {
259
uint32_t boottoctrl;
260
} NPCM7xxRegisters;
261
262
-typedef struct NPCM7xxSDHCIState {
263
+struct NPCM7xxSDHCIState {
264
SysBusDevice parent;
265
266
MemoryRegion container;
267
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxSDHCIState {
268
NPCM7xxRegisters regs;
269
270
SDHCIState sdhci;
271
-} NPCM7xxSDHCIState;
272
+};
273
274
#endif /* NPCM7XX_SDHCI_H */
275
--
276
2.34.1
277
278
diff view generated by jsdifflib
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
add MemTxAttrs as an argument to flatview_access_valid().
3
Its callers now all have an attrs value to hand, so we can
4
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
5
2
3
The structure is named SECUREECState. Rename the type accordingly.
4
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20230109140306.23161-12-philmd@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
10
---
9
---
11
exec.c | 12 +++++-------
10
hw/misc/sbsa_ec.c | 13 +++++++------
12
1 file changed, 5 insertions(+), 7 deletions(-)
11
1 file changed, 7 insertions(+), 6 deletions(-)
13
12
14
diff --git a/exec.c b/exec.c
13
diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
15
--- a/hw/misc/sbsa_ec.c
17
+++ b/exec.c
16
+++ b/hw/misc/sbsa_ec.c
18
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
17
@@ -XXX,XX +XXX,XX @@
19
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
18
#include "hw/sysbus.h"
20
const uint8_t *buf, int len);
19
#include "sysemu/runstate.h"
21
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
20
22
- bool is_write);
21
-typedef struct {
23
+ bool is_write, MemTxAttrs attrs);
22
+typedef struct SECUREECState {
24
23
SysBusDevice parent_obj;
25
static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
24
MemoryRegion iomem;
26
unsigned len, MemTxAttrs attrs)
25
} SECUREECState;
27
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
26
28
#endif
27
-#define TYPE_SBSA_EC "sbsa-ec"
29
28
-#define SECURE_EC(obj) OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_EC)
30
return flatview_access_valid(subpage->fv, addr + subpage->base,
29
+#define TYPE_SBSA_SECURE_EC "sbsa-ec"
31
- len, is_write);
30
+#define SBSA_SECURE_EC(obj) \
32
+ len, is_write, attrs);
31
+ OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
32
33
enum sbsa_ec_powerstates {
34
SBSA_EC_CMD_POWEROFF = 0x01,
35
@@ -XXX,XX +XXX,XX @@ static uint64_t sbsa_ec_read(void *opaque, hwaddr offset, unsigned size)
33
}
36
}
34
37
35
static const MemoryRegionOps subpage_ops = {
38
static void sbsa_ec_write(void *opaque, hwaddr offset,
36
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
39
- uint64_t value, unsigned size)
40
+ uint64_t value, unsigned size)
41
{
42
if (offset == 0) { /* PSCI machine power command register */
43
switch (value) {
44
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sbsa_ec_ops = {
45
46
static void sbsa_ec_init(Object *obj)
47
{
48
- SECUREECState *s = SECURE_EC(obj);
49
+ SECUREECState *s = SBSA_SECURE_EC(obj);
50
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
51
52
memory_region_init_io(&s->iomem, obj, &sbsa_ec_ops, s, "sbsa-ec",
53
@@ -XXX,XX +XXX,XX @@ static void sbsa_ec_class_init(ObjectClass *klass, void *data)
37
}
54
}
38
55
39
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
56
static const TypeInfo sbsa_ec_info = {
40
- bool is_write)
57
- .name = TYPE_SBSA_EC,
41
+ bool is_write, MemTxAttrs attrs)
58
+ .name = TYPE_SBSA_SECURE_EC,
42
{
59
.parent = TYPE_SYS_BUS_DEVICE,
43
MemoryRegion *mr;
60
.instance_size = sizeof(SECUREECState),
44
hwaddr l, xlat;
61
.instance_init = sbsa_ec_init,
45
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
46
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
47
if (!memory_access_is_direct(mr, is_write)) {
48
l = memory_access_size(mr, l, addr);
49
- /* When our callers all have attrs we'll pass them through here */
50
- if (!memory_region_access_valid(mr, xlat, l, is_write,
51
- MEMTXATTRS_UNSPECIFIED)) {
52
+ if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
53
return false;
54
}
55
}
56
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
57
58
rcu_read_lock();
59
fv = address_space_to_flatview(as);
60
- result = flatview_access_valid(fv, addr, len, is_write);
61
+ result = flatview_access_valid(fv, addr, len, is_write, attrs);
62
rcu_read_unlock();
63
return result;
64
}
65
--
62
--
66
2.17.1
63
2.34.1
67
64
68
65
diff view generated by jsdifflib
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
cpregs_keys is an uint32_t* so the allocation should use uint32_t.
3
This model was merged few days before the QOM cleanup from
4
g_new is even better because it is type-safe.
4
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible")
5
was pulled and merged. Manually adapt.
5
6
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20230109140306.23161-13-philmd@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/gdbstub.c | 3 +--
12
hw/misc/sbsa_ec.c | 3 +--
12
1 file changed, 1 insertion(+), 2 deletions(-)
13
1 file changed, 1 insertion(+), 2 deletions(-)
13
14
14
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
15
diff --git a/hw/misc/sbsa_ec.c b/hw/misc/sbsa_ec.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/gdbstub.c
17
--- a/hw/misc/sbsa_ec.c
17
+++ b/target/arm/gdbstub.c
18
+++ b/hw/misc/sbsa_ec.c
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
19
@@ -XXX,XX +XXX,XX @@ typedef struct SECUREECState {
19
RegisterSysregXmlParam param = {cs, s};
20
} SECUREECState;
20
21
21
cpu->dyn_xml.num_cpregs = 0;
22
#define TYPE_SBSA_SECURE_EC "sbsa-ec"
22
- cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
23
-#define SBSA_SECURE_EC(obj) \
23
- g_hash_table_size(cpu->cp_regs));
24
- OBJECT_CHECK(SECUREECState, (obj), TYPE_SBSA_SECURE_EC)
24
+ cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
25
+OBJECT_DECLARE_SIMPLE_TYPE(SECUREECState, SBSA_SECURE_EC)
25
g_string_printf(s, "<?xml version=\"1.0\"?>");
26
26
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
27
enum sbsa_ec_powerstates {
27
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
28
SBSA_EC_CMD_POWEROFF = 0x01,
28
--
29
--
29
2.17.1
30
2.34.1
30
31
31
32
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
Depending on the host abi, float16, aka uint16_t, values are
3
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
4
passed and returned either zero-extended in the host register
4
macro call, to avoid after a QOM refactor:
5
or with garbage at the top of the host register.
6
5
7
The tcg code generator has so far been assuming garbage, as that
6
hw/intc/xilinx_intc.c:45:1: error: declaration of anonymous struct must be a definition
8
matches the x86 abi, but this is incorrect for other host abis.
7
DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
9
Further, target/arm has so far been assuming zero-extended results,
8
^
10
so that it may store the 16-bit value into a 32-bit slot with the
11
high 16-bits already clear.
12
9
13
Rectify both problems by mapping "f16" in the helper definition
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
to uint32_t instead of (a typedef for) uint16_t. This forces
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
the host compiler to assume garbage in the upper 16 bits on input
12
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
16
and to zero-extend the result on output.
13
Message-id: 20230109140306.23161-14-philmd@linaro.org
17
18
Cc: qemu-stable@nongnu.org
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
22
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
15
---
26
include/exec/helper-head.h | 2 +-
16
hw/intc/xilinx_intc.c | 28 +++++++++++++---------------
27
target/arm/helper-a64.c | 35 +++++++++--------
17
1 file changed, 13 insertions(+), 15 deletions(-)
28
target/arm/helper.c | 80 +++++++++++++++++++-------------------
29
3 files changed, 59 insertions(+), 58 deletions(-)
30
18
31
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
19
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
32
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
33
--- a/include/exec/helper-head.h
21
--- a/hw/intc/xilinx_intc.c
34
+++ b/include/exec/helper-head.h
22
+++ b/hw/intc/xilinx_intc.c
35
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
36
#define dh_ctype_int int
24
#define R_MAX 8
37
#define dh_ctype_i64 uint64_t
25
38
#define dh_ctype_s64 int64_t
26
#define TYPE_XILINX_INTC "xlnx.xps-intc"
39
-#define dh_ctype_f16 float16
27
-DECLARE_INSTANCE_CHECKER(struct xlx_pic, XILINX_INTC,
40
+#define dh_ctype_f16 uint32_t
28
- TYPE_XILINX_INTC)
41
#define dh_ctype_f32 float32
29
+typedef struct XpsIntc XpsIntc;
42
#define dh_ctype_f64 float64
30
+DECLARE_INSTANCE_CHECKER(XpsIntc, XILINX_INTC, TYPE_XILINX_INTC)
43
#define dh_ctype_ptr void *
31
44
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
32
-struct xlx_pic
45
index XXXXXXX..XXXXXXX 100644
33
+struct XpsIntc
46
--- a/target/arm/helper-a64.c
34
{
47
+++ b/target/arm/helper-a64.c
35
SysBusDevice parent_obj;
48
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
36
49
return flags;
37
@@ -XXX,XX +XXX,XX @@ struct xlx_pic
38
uint32_t irq_pin_state;
39
};
40
41
-static void update_irq(struct xlx_pic *p)
42
+static void update_irq(XpsIntc *p)
43
{
44
uint32_t i;
45
46
@@ -XXX,XX +XXX,XX @@ static void update_irq(struct xlx_pic *p)
47
qemu_set_irq(p->parent_irq, (p->regs[R_MER] & 1) && p->regs[R_IPR]);
50
}
48
}
51
49
52
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
50
-static uint64_t
53
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
51
-pic_read(void *opaque, hwaddr addr, unsigned int size)
52
+static uint64_t pic_read(void *opaque, hwaddr addr, unsigned int size)
54
{
53
{
55
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
54
- struct xlx_pic *p = opaque;
56
}
55
+ XpsIntc *p = opaque;
57
56
uint32_t r = 0;
58
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
57
59
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
58
addr >>= 2;
60
{
59
@@ -XXX,XX +XXX,XX @@ pic_read(void *opaque, hwaddr addr, unsigned int size)
61
return float_rel_to_flags(float16_compare(x, y, fp_status));
62
}
63
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
64
#define float64_three make_float64(0x4008000000000000ULL)
65
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
66
67
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
68
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
69
{
70
float_status *fpst = fpstp;
71
72
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
73
return float64_muladd(a, b, float64_two, 0, fpst);
74
}
75
76
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
77
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
78
{
79
float_status *fpst = fpstp;
80
81
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
82
}
83
84
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
85
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
86
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
87
{
88
float_status *fpst = fpstp;
89
uint16_t val16, sbit;
90
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
91
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
92
93
#define ADVSIMD_HALFOP(name) \
94
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
95
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
96
{ \
97
float_status *fpst = fpstp; \
98
return float16_ ## name(a, b, fpst); \
99
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
100
ADVSIMD_TWOHALFOP(mulx)
101
102
/* fused multiply-accumulate */
103
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
104
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
105
+ void *fpstp)
106
{
107
float_status *fpst = fpstp;
108
return float16_muladd(a, b, c, 0, fpst);
109
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
110
111
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
112
113
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
114
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
115
{
116
float_status *fpst = fpstp;
117
int compare = float16_compare_quiet(a, b, fpst);
118
return ADVSIMD_CMPRES(compare == float_relation_equal);
119
}
120
121
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
122
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
123
{
124
float_status *fpst = fpstp;
125
int compare = float16_compare(a, b, fpst);
126
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
127
compare == float_relation_equal);
128
}
129
130
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
131
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
132
{
133
float_status *fpst = fpstp;
134
int compare = float16_compare(a, b, fpst);
135
return ADVSIMD_CMPRES(compare == float_relation_greater);
136
}
137
138
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
139
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
140
{
141
float_status *fpst = fpstp;
142
float16 f0 = float16_abs(a);
143
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
144
compare == float_relation_equal);
145
}
146
147
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
148
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
149
{
150
float_status *fpst = fpstp;
151
float16 f0 = float16_abs(a);
152
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
153
}
154
155
/* round to integral */
156
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
157
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
158
{
159
return float16_round_to_int(x, fp_status);
160
}
161
162
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
163
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
164
{
165
int old_flags = get_float_exception_flags(fp_status), new_flags;
166
float16 ret;
167
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
168
* setting the mode appropriately before calling the helper.
169
*/
170
171
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
172
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
173
{
174
float_status *fpst = fpstp;
175
176
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
177
return float16_to_int16(a, fpst);
178
}
179
180
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
181
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
182
{
183
float_status *fpst = fpstp;
184
185
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
186
* Square Root and Reciprocal square root
187
*/
188
189
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
190
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
191
{
192
float_status *s = fpstp;
193
194
diff --git a/target/arm/helper.c b/target/arm/helper.c
195
index XXXXXXX..XXXXXXX 100644
196
--- a/target/arm/helper.c
197
+++ b/target/arm/helper.c
198
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
199
200
/* Integer to float and float to integer conversions */
201
202
-#define CONV_ITOF(name, fsz, sign) \
203
- float##fsz HELPER(name)(uint32_t x, void *fpstp) \
204
-{ \
205
- float_status *fpst = fpstp; \
206
- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
207
+#define CONV_ITOF(name, ftype, fsz, sign) \
208
+ftype HELPER(name)(uint32_t x, void *fpstp) \
209
+{ \
210
+ float_status *fpst = fpstp; \
211
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
212
}
213
214
-#define CONV_FTOI(name, fsz, sign, round) \
215
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
216
-{ \
217
- float_status *fpst = fpstp; \
218
- if (float##fsz##_is_any_nan(x)) { \
219
- float_raise(float_flag_invalid, fpst); \
220
- return 0; \
221
- } \
222
- return float##fsz##_to_##sign##int32##round(x, fpst); \
223
+#define CONV_FTOI(name, ftype, fsz, sign, round) \
224
+uint32_t HELPER(name)(ftype x, void *fpstp) \
225
+{ \
226
+ float_status *fpst = fpstp; \
227
+ if (float##fsz##_is_any_nan(x)) { \
228
+ float_raise(float_flag_invalid, fpst); \
229
+ return 0; \
230
+ } \
231
+ return float##fsz##_to_##sign##int32##round(x, fpst); \
232
}
233
234
-#define FLOAT_CONVS(name, p, fsz, sign) \
235
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
236
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
237
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
238
+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
239
+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
240
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
241
+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
242
243
-FLOAT_CONVS(si, h, 16, )
244
-FLOAT_CONVS(si, s, 32, )
245
-FLOAT_CONVS(si, d, 64, )
246
-FLOAT_CONVS(ui, h, 16, u)
247
-FLOAT_CONVS(ui, s, 32, u)
248
-FLOAT_CONVS(ui, d, 64, u)
249
+FLOAT_CONVS(si, h, uint32_t, 16, )
250
+FLOAT_CONVS(si, s, float32, 32, )
251
+FLOAT_CONVS(si, d, float64, 64, )
252
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
253
+FLOAT_CONVS(ui, s, float32, 32, u)
254
+FLOAT_CONVS(ui, d, float64, 64, u)
255
256
#undef CONV_ITOF
257
#undef CONV_FTOI
258
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
259
return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
260
}
261
262
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
263
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
264
{
265
return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
266
}
267
268
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
269
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
270
{
271
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
272
}
273
274
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
275
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
276
{
277
return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
278
}
279
280
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
281
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
282
{
283
return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
284
}
285
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
286
}
287
}
288
289
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
290
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
291
{
292
return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
293
}
294
295
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
296
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
297
{
298
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
299
}
300
301
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
302
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
303
{
304
return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
305
}
306
307
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
308
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
309
{
310
return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
311
}
312
313
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
314
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
315
{
316
return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
317
}
318
319
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
320
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
321
{
322
return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
323
}
324
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
325
}
326
327
/* Half precision conversions. */
328
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
329
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
330
{
331
/* Squash FZ16 to 0 for the duration of conversion. In this case,
332
* it would affect flushing input denormals.
333
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
334
return r;
60
return r;
335
}
61
}
336
62
337
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
63
-static void
338
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
64
-pic_write(void *opaque, hwaddr addr,
65
- uint64_t val64, unsigned int size)
66
+static void pic_write(void *opaque, hwaddr addr,
67
+ uint64_t val64, unsigned int size)
339
{
68
{
340
/* Squash FZ16 to 0 for the duration of conversion. In this case,
69
- struct xlx_pic *p = opaque;
341
* it would affect flushing output denormals.
70
+ XpsIntc *p = opaque;
342
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
71
uint32_t value = val64;
343
return r;
72
73
addr >>= 2;
74
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pic_ops = {
75
76
static void irq_handler(void *opaque, int irq, int level)
77
{
78
- struct xlx_pic *p = opaque;
79
+ XpsIntc *p = opaque;
80
81
/* edge triggered interrupt */
82
if (p->c_kind_of_intr & (1 << irq) && p->regs[R_MER] & 2) {
83
@@ -XXX,XX +XXX,XX @@ static void irq_handler(void *opaque, int irq, int level)
84
85
static void xilinx_intc_init(Object *obj)
86
{
87
- struct xlx_pic *p = XILINX_INTC(obj);
88
+ XpsIntc *p = XILINX_INTC(obj);
89
90
qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
91
sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
92
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_init(Object *obj)
344
}
93
}
345
94
346
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
95
static Property xilinx_intc_properties[] = {
347
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
96
- DEFINE_PROP_UINT32("kind-of-intr", struct xlx_pic, c_kind_of_intr, 0),
348
{
97
+ DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
349
/* Squash FZ16 to 0 for the duration of conversion. In this case,
98
DEFINE_PROP_END_OF_LIST(),
350
* it would affect flushing input denormals.
99
};
351
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
100
352
return r;
101
@@ -XXX,XX +XXX,XX @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
353
}
102
static const TypeInfo xilinx_intc_info = {
354
103
.name = TYPE_XILINX_INTC,
355
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
104
.parent = TYPE_SYS_BUS_DEVICE,
356
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
105
- .instance_size = sizeof(struct xlx_pic),
357
{
106
+ .instance_size = sizeof(XpsIntc),
358
/* Squash FZ16 to 0 for the duration of conversion. In this case,
107
.instance_init = xilinx_intc_init,
359
* it would affect flushing output denormals.
108
.class_init = xilinx_intc_class_init,
360
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
109
};
361
g_assert_not_reached();
362
}
363
364
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
365
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
366
{
367
float_status *fpst = fpstp;
368
float16 f16 = float16_squash_input_denormal(input, fpst);
369
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
370
return extract64(estimate, 0, 8) << 44;
371
}
372
373
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
374
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
375
{
376
float_status *s = fpstp;
377
float16 f16 = float16_squash_input_denormal(input, s);
378
--
110
--
379
2.17.1
111
2.34.1
380
112
381
113
diff view generated by jsdifflib
1
Add more detail to the documentation for memory_region_init_iommu()
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
and other IOMMU-related functions and data structures.
3
2
3
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
4
macro call, to avoid after a QOM refactor:
5
6
hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be a definition
7
DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
8
^
9
10
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
13
Message-id: 20230109140306.23161-15-philmd@linaro.org
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
9
---
15
---
10
include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
16
hw/timer/xilinx_timer.c | 27 +++++++++++++--------------
11
1 file changed, 95 insertions(+), 10 deletions(-)
17
1 file changed, 13 insertions(+), 14 deletions(-)
12
18
13
diff --git a/include/exec/memory.h b/include/exec/memory.h
19
diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
14
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/memory.h
21
--- a/hw/timer/xilinx_timer.c
16
+++ b/include/exec/memory.h
22
+++ b/hw/timer/xilinx_timer.c
17
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
23
@@ -XXX,XX +XXX,XX @@ struct xlx_timer
18
IOMMU_ATTR_SPAPR_TCE_FD
19
};
24
};
20
25
21
+/**
26
#define TYPE_XILINX_TIMER "xlnx.xps-timer"
22
+ * IOMMUMemoryRegionClass:
27
-DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
23
+ *
28
- TYPE_XILINX_TIMER)
24
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
29
+typedef struct XpsTimerState XpsTimerState;
25
+ * and provide an implementation of at least the @translate method here
30
+DECLARE_INSTANCE_CHECKER(XpsTimerState, XILINX_TIMER, TYPE_XILINX_TIMER)
26
+ * to handle requests to the memory region. Other methods are optional.
31
27
+ *
32
-struct timerblock
28
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
33
+struct XpsTimerState
29
+ * to report whenever mappings are changed, by calling
34
{
30
+ * memory_region_notify_iommu() (or, if necessary, by calling
35
SysBusDevice parent_obj;
31
+ * memory_region_notify_one() for each registered notifier).
36
32
+ */
37
@@ -XXX,XX +XXX,XX @@ struct timerblock
33
typedef struct IOMMUMemoryRegionClass {
38
struct xlx_timer *timers;
34
/* private */
39
};
35
struct DeviceClass parent_class;
40
36
41
-static inline unsigned int num_timers(struct timerblock *t)
37
/*
42
+static inline unsigned int num_timers(XpsTimerState *t)
38
- * Return a TLB entry that contains a given address. Flag should
43
{
39
- * be the access permission of this translation operation. We can
44
return 2 - t->one_timer_only;
40
- * set flag to IOMMU_NONE to mean that we don't need any
45
}
41
- * read/write permission checks, like, when for region replay.
46
@@ -XXX,XX +XXX,XX @@ static inline unsigned int timer_from_addr(hwaddr addr)
42
+ * Return a TLB entry that contains a given address.
47
return addr >> 2;
43
+ *
48
}
44
+ * The IOMMUAccessFlags indicated via @flag are optional and may
49
45
+ * be specified as IOMMU_NONE to indicate that the caller needs
50
-static void timer_update_irq(struct timerblock *t)
46
+ * the full translation information for both reads and writes. If
51
+static void timer_update_irq(XpsTimerState *t)
47
+ * the access flags are specified then the IOMMU implementation
52
{
48
+ * may use this as an optimization, to stop doing a page table
53
unsigned int i, irq = 0;
49
+ * walk as soon as it knows that the requested permissions are not
54
uint32_t csr;
50
+ * allowed. If IOMMU_NONE is passed then the IOMMU must do the
55
@@ -XXX,XX +XXX,XX @@ static void timer_update_irq(struct timerblock *t)
51
+ * full page table walk and report the permissions in the returned
56
static uint64_t
52
+ * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
57
timer_read(void *opaque, hwaddr addr, unsigned int size)
53
+ * return different mappings for reads and writes.)
58
{
54
+ *
59
- struct timerblock *t = opaque;
55
+ * The returned information remains valid while the caller is
60
+ XpsTimerState *t = opaque;
56
+ * holding the big QEMU lock or is inside an RCU critical section;
61
struct xlx_timer *xt;
57
+ * if the caller wishes to cache the mapping beyond that it must
62
uint32_t r = 0;
58
+ * register an IOMMU notifier so it can invalidate its cached
63
unsigned int timer;
59
+ * information when the IOMMU mapping changes.
64
@@ -XXX,XX +XXX,XX @@ static void
60
+ *
65
timer_write(void *opaque, hwaddr addr,
61
+ * @iommu: the IOMMUMemoryRegion
66
uint64_t val64, unsigned int size)
62
+ * @hwaddr: address to be translated within the memory region
67
{
63
+ * @flag: requested access permissions
68
- struct timerblock *t = opaque;
64
*/
69
+ XpsTimerState *t = opaque;
65
IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
70
struct xlx_timer *xt;
66
IOMMUAccessFlags flag);
71
unsigned int timer;
67
- /* Returns minimum supported page size */
72
uint32_t value = val64;
68
+ /* Returns minimum supported page size in bytes.
73
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps timer_ops = {
69
+ * If this method is not provided then the minimum is assumed to
74
static void timer_hit(void *opaque)
70
+ * be TARGET_PAGE_SIZE.
75
{
71
+ *
76
struct xlx_timer *xt = opaque;
72
+ * @iommu: the IOMMUMemoryRegion
77
- struct timerblock *t = xt->parent;
73
+ */
78
+ XpsTimerState *t = xt->parent;
74
uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
79
D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
75
- /* Called when IOMMU Notifier flag changed */
80
xt->regs[R_TCSR] |= TCSR_TINT;
76
+ /* Called when IOMMU Notifier flag changes (ie when the set of
81
77
+ * events which IOMMU users are requesting notification for changes).
82
@@ -XXX,XX +XXX,XX @@ static void timer_hit(void *opaque)
78
+ * Optional method -- need not be provided if the IOMMU does not
83
79
+ * need to know exactly which events must be notified.
84
static void xilinx_timer_realize(DeviceState *dev, Error **errp)
80
+ *
85
{
81
+ * @iommu: the IOMMUMemoryRegion
86
- struct timerblock *t = XILINX_TIMER(dev);
82
+ * @old_flags: events which previously needed to be notified
87
+ XpsTimerState *t = XILINX_TIMER(dev);
83
+ * @new_flags: events which now need to be notified
88
unsigned int i;
84
+ */
89
85
void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
90
/* Init all the ptimers. */
86
IOMMUNotifierFlag old_flags,
91
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
87
IOMMUNotifierFlag new_flags);
92
88
- /* Set this up to provide customized IOMMU replay function */
93
static void xilinx_timer_init(Object *obj)
89
+ /* Called to handle memory_region_iommu_replay().
94
{
90
+ *
95
- struct timerblock *t = XILINX_TIMER(obj);
91
+ * The default implementation of memory_region_iommu_replay() is to
96
+ XpsTimerState *t = XILINX_TIMER(obj);
92
+ * call the IOMMU translate method for every page in the address space
97
93
+ * with flag == IOMMU_NONE and then call the notifier if translate
98
/* All timers share a single irq line. */
94
+ * returns a valid mapping. If this method is implemented then it
99
sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
95
+ * overrides the default behaviour, and must provide the full semantics
100
}
96
+ * of memory_region_iommu_replay(), by calling @notifier for every
101
97
+ * translation present in the IOMMU.
102
static Property xilinx_timer_properties[] = {
98
+ *
103
- DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
99
+ * Optional method -- an IOMMU only needs to provide this method
104
- 62 * 1000000),
100
+ * if the default is inefficient or produces undesirable side effects.
105
- DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
101
+ *
106
+ DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
102
+ * Note: this is not related to record-and-replay functionality.
107
+ DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
103
+ */
108
DEFINE_PROP_END_OF_LIST(),
104
void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
109
};
105
110
106
- /* Get IOMMU misc attributes */
111
@@ -XXX,XX +XXX,XX @@ static void xilinx_timer_class_init(ObjectClass *klass, void *data)
107
- int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
112
static const TypeInfo xilinx_timer_info = {
108
+ /* Get IOMMU misc attributes. This is an optional method that
113
.name = TYPE_XILINX_TIMER,
109
+ * can be used to allow users of the IOMMU to get implementation-specific
114
.parent = TYPE_SYS_BUS_DEVICE,
110
+ * information. The IOMMU implements this method to handle calls
115
- .instance_size = sizeof(struct timerblock),
111
+ * by IOMMU users to memory_region_iommu_get_attr() by filling in
116
+ .instance_size = sizeof(XpsTimerState),
112
+ * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
117
.instance_init = xilinx_timer_init,
113
+ * the IOMMU supports. If the method is unimplemented then
118
.class_init = xilinx_timer_class_init,
114
+ * memory_region_iommu_get_attr() will always return -EINVAL.
119
};
115
+ *
116
+ * @iommu: the IOMMUMemoryRegion
117
+ * @attr: attribute being queried
118
+ * @data: memory to fill in with the attribute data
119
+ *
120
+ * Returns 0 on success, or a negative errno; in particular
121
+ * returns -EINVAL for unrecognized or unimplemented attribute types.
122
+ */
123
+ int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
124
void *data);
125
} IOMMUMemoryRegionClass;
126
127
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
128
* An IOMMU region translates addresses and forwards accesses to a target
129
* memory region.
130
*
131
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
132
+ * @_iommu_mr should be a pointer to enough memory for an instance of
133
+ * that subclass, @instance_size is the size of that subclass, and
134
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
135
+ * instance of the subclass, and its methods will then be called to handle
136
+ * accesses to the memory region. See the documentation of
137
+ * #IOMMUMemoryRegionClass for further details.
138
+ *
139
* @_iommu_mr: the #IOMMUMemoryRegion to be initialized
140
* @instance_size: the IOMMUMemoryRegion subclass instance size
141
* @mrtypename: the type name of the #IOMMUMemoryRegion
142
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
143
* a notifier with the minimum page granularity returned by
144
* mr->iommu_ops->get_page_size().
145
*
146
+ * Note: this is not related to record-and-replay functionality.
147
+ *
148
* @iommu_mr: the memory region to observe
149
* @n: the notifier to which to replay iommu mappings
150
*/
151
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
152
* memory_region_iommu_replay_all: replay existing IOMMU translations
153
* to all the notifiers registered.
154
*
155
+ * Note: this is not related to record-and-replay functionality.
156
+ *
157
* @iommu_mr: the memory region to observe
158
*/
159
void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
160
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
161
* memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
162
* defined on the IOMMU.
163
*
164
- * Returns 0 if succeded, error code otherwise.
165
+ * Returns 0 on success, or a negative errno otherwise. In particular,
166
+ * -EINVAL indicates that the IOMMU does not support the requested
167
+ * attribute.
168
*
169
* @iommu_mr: the memory region
170
* @attr: the requested attribute
171
--
120
--
172
2.17.1
121
2.34.1
173
122
174
123
diff view generated by jsdifflib
1
In commit f0aff255700 we made cpacr_write() enforce that some CPACR
1
From: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
2
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
3
we forgot to also update the register's reset value. The effect
4
was that (a) a guest that read CPACR on reset would not see ones in
5
the RAO bits, and (b) if you did a migration before the guest did
6
a write to the CPACR then the migration would fail because the
7
destination would enforce the RAO bits and then complain that they
8
didn't match the zero value from the source.
9
2
10
Implement reset for the CPACR using a custom reset function
3
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
11
that just calls cpacr_write(), to avoid having to duplicate
4
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
12
the logic for which bits are RAO.
5
uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
6
write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is
7
enabled and exposed to the guest. As a result EL3 writes of that bit are
8
ignored.
13
9
14
This bug would affect migration for TCG CPUs which are ARMv7
10
Cc: qemu-stable@nongnu.org
15
with VFP but without one of Neon or VFPv3.
11
Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
16
12
Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com
17
Reported-by: Cédric Le Goater <clg@kaod.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Tested-by: Cédric Le Goater <clg@kaod.org>
20
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
21
---
15
---
22
target/arm/helper.c | 10 +++++++++-
16
target/arm/helper.c | 3 +++
23
1 file changed, 9 insertions(+), 1 deletion(-)
17
1 file changed, 3 insertions(+)
24
18
25
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper.c
21
--- a/target/arm/helper.c
28
+++ b/target/arm/helper.c
22
+++ b/target/arm/helper.c
29
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
23
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
30
env->cp15.cpacr_el1 = value;
24
if (cpu_isar_feature(aa64_sme, cpu)) {
31
}
25
valid_mask |= SCR_ENTP2;
32
26
}
33
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
27
+ if (cpu_isar_feature(aa64_hcx, cpu)) {
34
+{
28
+ valid_mask |= SCR_HXEN;
35
+ /* Call cpacr_write() so that we reset with the correct RAO bits set
29
+ }
36
+ * for our CPU features.
30
} else {
37
+ */
31
valid_mask &= ~(SCR_RW | SCR_ST);
38
+ cpacr_write(env, ri, 0);
32
if (cpu_isar_feature(aa32_ras, cpu)) {
39
+}
40
+
41
static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
42
bool isread)
43
{
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
45
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
46
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
47
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
48
- .resetvalue = 0, .writefn = cpacr_write },
49
+ .resetfn = cpacr_reset, .writefn = cpacr_write },
50
REGINFO_SENTINEL
51
};
52
53
--
33
--
54
2.17.1
34
2.34.1
55
56
diff view generated by jsdifflib