target-arm queue. This has the "plumb txattrs through various

bits of exec.c" patches, and a collection of bug fixes from

various people.

The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:

Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531

for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)

* target/arm: Honour FPCR.FZ in FRECPX

* MAINTAINERS: Add entries for newer MPS2 boards and devices

* hw/intc/arm_gicv3: Fix APxR<n> register dispatching

* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel

GIC state

* tcg: Fix helper function vs host abi for float16

* arm: fix qemu crash on startup with -bios option

* arm: fix malloc type mismatch

* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

* Correct CPACR reset value for v7 cores

* memory.h: Improve IOMMU related documentation

* exec: Plumb transaction attributes through various functions in

preparation for allowing IOMMUs to see them

* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

* ARM: ACPI: Fix use-after-free due to memory realloc

* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

Francisco Iglesias (1):

xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

Igor Mammedov (1):

arm: fix qemu crash on startup with -bios option

Jan Kiszka (1):

hw/intc/arm_gicv3: Fix APxR<n> register dispatching

Paolo Bonzini (1):

arm: fix malloc type mismatch

Peter Maydell (17):

target/arm: Honour FPCR.FZ in FRECPX

MAINTAINERS: Add entries for newer MPS2 boards and devices

Correct CPACR reset value for v7 cores

memory.h: Improve IOMMU related documentation

Make tb_invalidate_phys_addr() take a MemTxAttrs argument

Make address_space_translate{, _cached}() take a MemTxAttrs argument

Make address_space_map() take a MemTxAttrs argument

Make address_space_access_valid() take a MemTxAttrs argument

Make flatview_extend_translation() take a MemTxAttrs argument

Make memory_region_access_valid() take a MemTxAttrs argument

Make MemoryRegion valid.accepts callback take a MemTxAttrs argument

Make flatview_access_valid() take a MemTxAttrs argument

Make flatview_translate() take a MemTxAttrs argument

Make address_space_get_iotlb_entry() take a MemTxAttrs argument

Make flatview_do_translate() take a MemTxAttrs argument

Make address_space_translate_iommu take a MemTxAttrs argument

vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

Richard Henderson (1):

tcg: Fix helper function vs host abi for float16

Shannon Zhao (3):

arm_gicv3_kvm: increase clroffset accordingly

ARM: ACPI: Fix use-after-free due to memory realloc

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

include/exec/exec-all.h | 5 +-

include/exec/helper-head.h | 2 +-

include/exec/memory-internal.h | 3 +-

include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------

include/migration/vmstate.h | 3 +

include/sysemu/dma.h | 6 +-

accel/tcg/translate-all.c | 4 +-

exec.c | 95 ++++++++++++++++++------------

hw/arm/boot.c | 18 +++---

hw/arm/virt-acpi-build.c | 20 +++++--

hw/dma/xlnx-zdma.c | 10 +++-

hw/hppa/dino.c | 3 +-

hw/intc/arm_gic_kvm.c | 1 -

hw/intc/arm_gicv3_cpuif.c | 12 ++--

hw/intc/arm_gicv3_kvm.c | 2 +-

hw/nvram/fw_cfg.c | 12 ++--

hw/s390x/s390-pci-inst.c | 3 +-

hw/scsi/esp.c | 3 +-

hw/vfio/common.c | 3 +-

hw/virtio/vhost.c | 3 +-

hw/xen/xen_pt_msi.c | 3 +-

memory.c | 12 ++--

memory_ldst.inc.c | 18 +++---

target/arm/gdbstub.c | 3 +-

target/arm/helper-a64.c | 41 +++++++------

target/arm/helper.c | 90 ++++++++++++++++-------------

target/ppc/mmu-hash64.c | 3 +-

target/riscv/helper.c | 2 +-

target/s390x/diag.c | 6 +-

target/s390x/excp_helper.c | 3 +-

target/s390x/mmu_helper.c | 3 +-

target/s390x/sigp.c | 3 +-

target/xtensa/op_helper.c | 3 +-

MAINTAINERS | 9 ++-

34 files changed, 353 insertions(+), 182 deletions(-)

As part of plumbing MemTxAttrs down to the IOMMU translate method,

add MemTxAttrs as an argument to flatview_access_valid().

Its callers now all have an attrs value to hand, so we can

correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.

Message-id: 20180521140402.23318-10-peter.maydell@linaro.org

exec.c | 12 +++++-------

1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/exec.c b/exec.c

--- a/exec.c

+++ b/exec.c

@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,

static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,

const uint8_t *buf, int len);

static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,

- bool is_write);

+ bool is_write, MemTxAttrs attrs);

static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,

unsigned len, MemTxAttrs attrs)

@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,

return flatview_access_valid(subpage->fv, addr + subpage->base,

- len, is_write);

+ len, is_write, attrs);

static const MemoryRegionOps subpage_ops = {

@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)

}

static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,

- bool is_write)

+ bool is_write, MemTxAttrs attrs)

MemoryRegion *mr;

hwaddr l, xlat;

@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,

mr = flatview_translate(fv, addr, &xlat, &l, is_write);

if (!memory_access_is_direct(mr, is_write)) {

l = memory_access_size(mr, l, addr);

- /* When our callers all have attrs we'll pass them through here */

- if (!memory_region_access_valid(mr, xlat, l, is_write,

- MEMTXATTRS_UNSPECIFIED)) {

+ if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {

return false;

}

}

@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,

rcu_read_lock();

fv = address_space_to_flatview(as);

- result = flatview_access_valid(fv, addr, len, is_write);

+ result = flatview_access_valid(fv, addr, len, is_write, attrs);

rcu_read_unlock();

return result;

}

2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,

add MemTxAttrs as an argument to address_space_translate_iommu().

Message-id: 20180521140402.23318-14-peter.maydell@linaro.org

exec.c | 8 +++++---

1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/exec.c b/exec.c

--- a/exec.c

+++ b/exec.c

@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x

* @is_write: whether the translation operation is for write

* @is_mmio: whether this can be MMIO, set true if it can

* @target_as: the address space targeted by the IOMMU

+ * @attrs: transaction attributes

*

* This function is called from RCU critical section. It is the common

* part of flatview_do_translate and address_space_translate_cached.

@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm

hwaddr *page_mask_out,

bool is_write,

bool is_mmio,

- AddressSpace **target_as)

+ AddressSpace **target_as,

+ MemTxAttrs attrs)

MemoryRegionSection *section;

hwaddr page_mask = (hwaddr)-1;

@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,

return address_space_translate_iommu(iommu_mr, xlat,

plen_out, page_mask_out,

is_write, is_mmio,

- target_as);

+ target_as, attrs);

}

if (page_mask_out) {

/* Not behind an IOMMU, use default page size. */

@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(

section = address_space_translate_iommu(iommu_mr, xlat, plen,

NULL, is_write, true,

- &target_as);

+ &target_as, attrs);

return section.mr;

2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

acpi_data_push uses g_array_set_size to resize the memory size. If there

is no enough contiguous memory, the address will be changed. So previous

pointer could not be used any more. It must update the pointer and use

the new one.

Also, previous codes wrongly use le32 conversion of iort->node_offset

for subsequent computations that will result incorrect value if host is

not litlle endian. So use the non-converted one instead.

hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----

1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c

--- a/hw/arm/virt-acpi-build.c

+++ b/hw/arm/virt-acpi-build.c

@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

AcpiIortItsGroup *its;

AcpiIortTable *iort;

AcpiIortSmmu3 *smmu;

- size_t node_size, iort_length, smmu_offset = 0;

+ size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;

AcpiIortRC *rc;

iort = acpi_data_push(table_data, sizeof(*iort));

@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

iort_length = sizeof(*iort);

iort->node_count = cpu_to_le32(nb_nodes);

- iort->node_offset = cpu_to_le32(sizeof(*iort));

+ /*

+ * Use a copy in case table_data->data moves during acpi_data_push

+ * operations.

+ */

+ iort_node_offset = sizeof(*iort);

+ iort->node_offset = cpu_to_le32(iort_node_offset);

/* ITS group node */

node_size = sizeof(*its) + sizeof(uint32_t);

@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

int irq = vms->irqmap[VIRT_SMMU];

/* SMMUv3 node */

- smmu_offset = iort->node_offset + node_size;

+ smmu_offset = iort_node_offset + node_size;

node_size = sizeof(*smmu) + sizeof(*idmap);

iort_length += node_size;

smmu = acpi_data_push(table_data, node_size);

@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

idmap->id_count = cpu_to_le32(0xFFFF);

idmap->output_base = 0;

/* output IORT node is the ITS group node (the first node) */

- idmap->output_reference = cpu_to_le32(iort->node_offset);

+ idmap->output_reference = cpu_to_le32(iort_node_offset);

/* Root Complex Node */

@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)

idmap->output_reference = cpu_to_le32(smmu_offset);

/* output IORT node is the ITS group node (the first node) */

- idmap->output_reference = cpu_to_le32(iort->node_offset);

+ idmap->output_reference = cpu_to_le32(iort_node_offset);

+ /*

+ * Update the pointer address in case table_data->data moves during above

+ * acpi_data_push operations.

+ */

+ iort = (AcpiIortTable *)(table_data->data + iort_start);

iort->length = cpu_to_le32(iort_length);

build_header(linker, table_data, (void *)(table_data->data + iort_start),

2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,

add MemTxAttrs as an argument to flatview_do_translate().

Message-id: 20180521140402.23318-13-peter.maydell@linaro.org

exec.c | 9 ++++++---

1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/exec.c b/exec.c

--- a/exec.c

+++ b/exec.c

@@ -XXX,XX +XXX,XX @@ unassigned:

* @is_write: whether the translation operation is for write

* @is_mmio: whether this can be MMIO, set true if it can

* @target_as: the address space targeted by the IOMMU

+ * @attrs: memory transaction attributes

*

* This function is called from RCU critical section

*/

@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,

hwaddr *page_mask_out,

bool is_write,

bool is_mmio,

- AddressSpace **target_as)

+ AddressSpace **target_as,

+ MemTxAttrs attrs)

{

MemoryRegionSection *section;

IOMMUMemoryRegion *iommu_mr;

@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,

* but page mask.

*/

section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,

- NULL, &page_mask, is_write, false, &as);

+ NULL, &page_mask, is_write, false, &as,

+ attrs);

/* Illegal translation */

if (section.mr == &io_mem_unassigned) {

@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,

/* This can be MMIO, so setup MMIO bit. */

section = flatview_do_translate(fv, addr, xlat, plen, NULL,

- is_write, true, &as);

+ is_write, true, &as, attrs);

mr = section.mr;

if (xen_enabled() && memory_access_is_direct(mr, is_write)) {

2.17.1

From: Igor Mammedov <imammedo@redhat.com>

When QEMU is started with following CLI

-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd

it crashes with abort at

accel/kvm/kvm-all.c:2164:

KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument

Which is caused by implicit dependency of kvm_arm_gicv3_reset() on

arm_gicv3_icc_reset() where the later is called by CPU reset

reset callback.

However commit:

3b77f6c arm/boot: split load_dtb() from arm_load_kernel()

broke CPU reset callback registration in case

arm_load_kernel()

...

if (!info->kernel_filename || info->firmware_loaded)

branch is taken, i.e. it's sufficient to provide a firmware

or do not provide kernel on CLI to skip cpu reset callback

registration, where before offending commit the callback

has been registered unconditionally.

Fix it by registering the callback right at the beginning of

arm_load_kernel() unconditionally instead of doing it at the end.

NOTE:

we probably should eliminate that dependency anyways as well as

separate arch CPU reset parts from arm_load_kernel() into CPU

itself, but that refactoring that I probably would have to do

anyways later for CPU hotplug to work.

Reported-by: Auger Eric <eric.auger@redhat.com>

Signed-off-by: Igor Mammedov <imammedo@redhat.com>

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Tested-by: Eric Auger <eric.auger@redhat.com>

Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/boot.c | 18 +++++++++---------

1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c

--- a/hw/arm/boot.c

+++ b/hw/arm/boot.c

@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)

static const ARMInsnFixup *primary_loader;

AddressSpace *as = arm_boot_address_space(cpu, info);

+ /* CPU objects (unlike devices) are not automatically reset on system

+ * reset, so we must always register a handler to do so. If we're

+ * actually loading a kernel, the handler is also responsible for

+ * arranging that we start it correctly.

+ */

+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {

+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));

/* The board code is not supposed to set secure_board_setup unless

* running its code in secure mode is actually possible, and KVM

* doesn't support secure.

@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)

ARM_CPU(cs)->env.boot_info = info;

}

- /* CPU objects (unlike devices) are not automatically reset on system

- * reset, so we must always register a handler to do so. If we're

- * actually loading a kernel, the handler is also responsible for

- * arranging that we start it correctly.

- */

- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {

- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));

if (!info->skip_dtb_autoload && have_dtb(info)) {

if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {

exit(1);

2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,

add MemTxAttrs as an argument to address_space_get_iotlb_entry().

Message-id: 20180521140402.23318-12-peter.maydell@linaro.org

include/exec/memory.h | 2 +-

exec.c | 2 +-

hw/virtio/vhost.c | 3 ++-

3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h

--- a/include/exec/memory.h

+++ b/include/exec/memory.h

@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);

* entry. Should be called from an RCU critical section.

*/

IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,

- bool is_write);

+ bool is_write, MemTxAttrs attrs);

/* address_space_translate: translate an address range into an address space

* into a MemoryRegion and an address range into that section. Should be

diff --git a/exec.c b/exec.c

--- a/exec.c

+++ b/exec.c

@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,

/* Called from RCU critical section */

IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,

- bool is_write)

+ bool is_write, MemTxAttrs attrs)

{

MemoryRegionSection section;

hwaddr xlat, page_mask;

diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/virtio/vhost.c

+++ b/hw/virtio/vhost.c

@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)

trace_vhost_iotlb_miss(dev, 1);

iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,

- iova, write);

+ iova, write,

+ MEMTXATTRS_UNSPECIFIED);

if (iotlb.target_as != NULL) {

ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,

&uaddr, &len);

2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,

add MemTxAttrs as an argument to address_space_access_valid().

Its callers either have an attrs value to hand, or don't care

and can use MEMTXATTRS_UNSPECIFIED.

Message-id: 20180521140402.23318-6-peter.maydell@linaro.org

include/exec/memory.h | 4 +++-

include/sysemu/dma.h | 3 ++-

exec.c | 3 ++-

target/s390x/diag.c | 6 ++++--

target/s390x/excp_helper.c | 3 ++-

target/s390x/mmu_helper.c | 3 ++-

target/s390x/sigp.c | 3 ++-

7 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h

--- a/include/exec/memory.h

+++ b/include/exec/memory.h

@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,

* @addr: address within that address space

* @len: length of the area to be checked

* @is_write: indicates the transfer direction

+ * @attrs: memory attributes

*/

-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);

+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,

+ bool is_write, MemTxAttrs attrs);

/* address_space_map: map a physical memory region into a host virtual address

*

diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h

--- a/include/sysemu/dma.h

+++ b/include/sysemu/dma.h

@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,

DMADirection dir)

return address_space_access_valid(as, addr, len,

- dir == DMA_DIRECTION_FROM_DEVICE);

+ dir == DMA_DIRECTION_FROM_DEVICE,

+ MEMTXATTRS_UNSPECIFIED);

static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,

diff --git a/exec.c b/exec.c

index XXXXXXX..XXXXXXX 100644

--- a/exec.c

+++ b/exec.c

@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,

}

bool address_space_access_valid(AddressSpace *as, hwaddr addr,

- int len, bool is_write)

+ int len, bool is_write,

+ MemTxAttrs attrs)

FlatView *fv;

bool result;

diff --git a/target/s390x/diag.c b/target/s390x/diag.c

index XXXXXXX..XXXXXXX 100644

--- a/target/s390x/diag.c

+++ b/target/s390x/diag.c

@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)

return;

}

if (!address_space_access_valid(&address_space_memory, addr,

- sizeof(IplParameterBlock), false)) {

+ sizeof(IplParameterBlock), false,

+ MEMTXATTRS_UNSPECIFIED)) {

s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);

return;

}

@@ -XXX,XX +XXX,XX @@ out:

return;

}

if (!address_space_access_valid(&address_space_memory, addr,

- sizeof(IplParameterBlock), true)) {

+ sizeof(IplParameterBlock), true,

+ MEMTXATTRS_UNSPECIFIED)) {

s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);

return;

}

diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/s390x/excp_helper.c

+++ b/target/s390x/excp_helper.c

@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,

/* check out of RAM access */

if (!address_space_access_valid(&address_space_memory, raddr,

- TARGET_PAGE_SIZE, rw)) {

+ TARGET_PAGE_SIZE, rw,

+ MEMTXATTRS_UNSPECIFIED)) {

DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,

(uint64_t)raddr, (uint64_t)ram_size);

trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);

diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/s390x/mmu_helper.c

+++ b/target/s390x/mmu_helper.c

@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,

return ret;

}

if (!address_space_access_valid(&address_space_memory, pages[i],

- TARGET_PAGE_SIZE, is_write)) {

+ TARGET_PAGE_SIZE, is_write,

+ MEMTXATTRS_UNSPECIFIED)) {

trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);

return -EFAULT;

}

diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c

index XXXXXXX..XXXXXXX 100644

--- a/target/s390x/sigp.c

+++ b/target/s390x/sigp.c

@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)

cpu_synchronize_state(cs);

if (!address_space_access_valid(&address_space_memory, addr,

- sizeof(struct LowCore), false)) {

+ sizeof(struct LowCore), false,

+ MEMTXATTRS_UNSPECIFIED)) {

set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);

return;

}

2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,

add MemTxAttrs as an argument to tb_invalidate_phys_addr().

Its callers either have an attrs value to hand, or don't care

and can use MEMTXATTRS_UNSPECIFIED.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180521140402.23318-3-peter.maydell@linaro.org

include/exec/exec-all.h | 5 +++--

accel/tcg/translate-all.c | 2 +-

exec.c | 2 +-

target/xtensa/op_helper.c | 3 ++-

4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h

index XXXXXXX..XXXXXXX 100644

--- a/include/exec/exec-all.h

+++ b/include/exec/exec-all.h

@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,

void tlb_set_page(CPUState *cpu, target_ulong vaddr,

hwaddr paddr, int prot,

int mmu_idx, target_ulong size);

-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);

+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);

void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,

uintptr_t retaddr);

#else

@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,

uint16_t idxmap)