1 | target-arm queue. This has the "plumb txattrs through various | 1 | Last few changes before rc0: a few bug fixes, but mostly |
---|---|---|---|
2 | bits of exec.c" patches, and a collection of bug fixes from | 2 | docs stuff. |
3 | various people. | ||
4 | 3 | ||
5 | thanks | ||
6 | -- PMM | 4 | -- PMM |
7 | 5 | ||
6 | The following changes since commit a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf: | ||
8 | 7 | ||
9 | 8 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream3' into staging (2021-07-16 16:34:42 +0100) | |
10 | The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022: | ||
11 | |||
12 | Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100) | ||
13 | 9 | ||
14 | are available in the Git repository at: | 10 | are available in the Git repository at: |
15 | 11 | ||
16 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210718 |
17 | 13 | ||
18 | for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b: | 14 | for you to fetch changes up to 8fe612a183dec4c63afdc57537079bc742d024ca: |
19 | 15 | ||
20 | KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100) | 16 | target/arm: Remove duplicate 'plus1' function from Neon and SVE decode (2021-07-18 10:59:47 +0100) |
21 | 17 | ||
22 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
23 | target-arm queue: | 19 | target-arm queue: |
24 | * target/arm: Honour FPCR.FZ in FRECPX | 20 | * Remove duplicate 'plus1' function from Neon and SVE decode |
25 | * MAINTAINERS: Add entries for newer MPS2 boards and devices | 21 | * Fix offsets for TTBCR for big-endian hosts |
26 | * hw/intc/arm_gicv3: Fix APxR<n> register dispatching | 22 | * docs: fix copyright date |
27 | * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel | 23 | * docs: add license/version info to HTML footers |
28 | GIC state | 24 | * docs: add an About section |
29 | * tcg: Fix helper function vs host abi for float16 | 25 | * docs: document some more arm boards |
30 | * arm: fix qemu crash on startup with -bios option | ||
31 | * arm: fix malloc type mismatch | ||
32 | * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors | ||
33 | * Correct CPACR reset value for v7 cores | ||
34 | * memory.h: Improve IOMMU related documentation | ||
35 | * exec: Plumb transaction attributes through various functions in | ||
36 | preparation for allowing IOMMUs to see them | ||
37 | * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY | ||
38 | * ARM: ACPI: Fix use-after-free due to memory realloc | ||
39 | * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice | ||
40 | 26 | ||
41 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
42 | Francisco Iglesias (1): | 28 | Peter Maydell (11): |
43 | xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors | 29 | docs: Fix documentation Copyright date |
44 | 30 | docs: Stop calling the top level subsections of our manual 'manuals' | |
45 | Igor Mammedov (1): | 31 | docs: Remove "Contents:" lines from top-level subsections |
46 | arm: fix qemu crash on startup with -bios option | 32 | docs: Move deprecation, build and license info out of system/ |
47 | 33 | docs: Add some actual About text to about/index.rst | |
48 | Jan Kiszka (1): | 34 | docs: Add license note to the HTML page footer |
49 | hw/intc/arm_gicv3: Fix APxR<n> register dispatching | 35 | docs: Add QEMU version information to HTML footer |
50 | 36 | docs: Add skeletal documentation of cubieboard | |
51 | Paolo Bonzini (1): | 37 | docs: Add skeletal documentation of the emcraft-sf2 |
52 | arm: fix malloc type mismatch | 38 | docs: Add skeletal documentation of highbank and midway |
53 | 39 | target/arm: Remove duplicate 'plus1' function from Neon and SVE decode | |
54 | Peter Maydell (17): | ||
55 | target/arm: Honour FPCR.FZ in FRECPX | ||
56 | MAINTAINERS: Add entries for newer MPS2 boards and devices | ||
57 | Correct CPACR reset value for v7 cores | ||
58 | memory.h: Improve IOMMU related documentation | ||
59 | Make tb_invalidate_phys_addr() take a MemTxAttrs argument | ||
60 | Make address_space_translate{, _cached}() take a MemTxAttrs argument | ||
61 | Make address_space_map() take a MemTxAttrs argument | ||
62 | Make address_space_access_valid() take a MemTxAttrs argument | ||
63 | Make flatview_extend_translation() take a MemTxAttrs argument | ||
64 | Make memory_region_access_valid() take a MemTxAttrs argument | ||
65 | Make MemoryRegion valid.accepts callback take a MemTxAttrs argument | ||
66 | Make flatview_access_valid() take a MemTxAttrs argument | ||
67 | Make flatview_translate() take a MemTxAttrs argument | ||
68 | Make address_space_get_iotlb_entry() take a MemTxAttrs argument | ||
69 | Make flatview_do_translate() take a MemTxAttrs argument | ||
70 | Make address_space_translate_iommu take a MemTxAttrs argument | ||
71 | vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY | ||
72 | 40 | ||
73 | Richard Henderson (1): | 41 | Richard Henderson (1): |
74 | tcg: Fix helper function vs host abi for float16 | 42 | target/arm: Fix offsets for TTBCR |
75 | 43 | ||
76 | Shannon Zhao (3): | 44 | docs/_templates/footer.html | 14 ++++++++++++++ |
77 | arm_gicv3_kvm: increase clroffset accordingly | 45 | docs/{system => about}/build-platforms.rst | 0 |
78 | ARM: ACPI: Fix use-after-free due to memory realloc | 46 | docs/{system => about}/deprecated.rst | 0 |
79 | KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice | 47 | docs/about/index.rst | 27 +++++++++++++++++++++++++++ |
48 | docs/{system => about}/license.rst | 0 | ||
49 | docs/{system => about}/removed-features.rst | 0 | ||
50 | docs/conf.py | 2 +- | ||
51 | docs/devel/index.rst | 7 +------ | ||
52 | docs/index.rst | 1 + | ||
53 | docs/interop/index.rst | 9 ++------- | ||
54 | docs/meson.build | 3 ++- | ||
55 | docs/specs/index.rst | 7 ++----- | ||
56 | docs/system/arm/cubieboard.rst | 16 ++++++++++++++++ | ||
57 | docs/system/arm/emcraft-sf2.rst | 15 +++++++++++++++ | ||
58 | docs/system/arm/highbank.rst | 19 +++++++++++++++++++ | ||
59 | docs/system/index.rst | 11 +---------- | ||
60 | docs/system/target-arm.rst | 3 +++ | ||
61 | docs/tools/index.rst | 7 ++----- | ||
62 | docs/user/index.rst | 7 +------ | ||
63 | target/arm/neon-ls.decode | 4 ++-- | ||
64 | target/arm/neon-shared.decode | 2 +- | ||
65 | target/arm/sve.decode | 2 +- | ||
66 | target/arm/helper.c | 11 +++++++---- | ||
67 | target/arm/translate-neon.c | 5 ----- | ||
68 | target/arm/translate-sve.c | 5 ----- | ||
69 | MAINTAINERS | 4 ++++ | ||
70 | 26 files changed, 122 insertions(+), 59 deletions(-) | ||
71 | create mode 100644 docs/_templates/footer.html | ||
72 | rename docs/{system => about}/build-platforms.rst (100%) | ||
73 | rename docs/{system => about}/deprecated.rst (100%) | ||
74 | create mode 100644 docs/about/index.rst | ||
75 | rename docs/{system => about}/license.rst (100%) | ||
76 | rename docs/{system => about}/removed-features.rst (100%) | ||
77 | create mode 100644 docs/system/arm/cubieboard.rst | ||
78 | create mode 100644 docs/system/arm/emcraft-sf2.rst | ||
79 | create mode 100644 docs/system/arm/highbank.rst | ||
80 | 80 | ||
81 | include/exec/exec-all.h | 5 +- | ||
82 | include/exec/helper-head.h | 2 +- | ||
83 | include/exec/memory-internal.h | 3 +- | ||
84 | include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------ | ||
85 | include/migration/vmstate.h | 3 + | ||
86 | include/sysemu/dma.h | 6 +- | ||
87 | accel/tcg/translate-all.c | 4 +- | ||
88 | exec.c | 95 ++++++++++++++++++------------ | ||
89 | hw/arm/boot.c | 18 +++--- | ||
90 | hw/arm/virt-acpi-build.c | 20 +++++-- | ||
91 | hw/dma/xlnx-zdma.c | 10 +++- | ||
92 | hw/hppa/dino.c | 3 +- | ||
93 | hw/intc/arm_gic_kvm.c | 1 - | ||
94 | hw/intc/arm_gicv3_cpuif.c | 12 ++-- | ||
95 | hw/intc/arm_gicv3_kvm.c | 2 +- | ||
96 | hw/nvram/fw_cfg.c | 12 ++-- | ||
97 | hw/s390x/s390-pci-inst.c | 3 +- | ||
98 | hw/scsi/esp.c | 3 +- | ||
99 | hw/vfio/common.c | 3 +- | ||
100 | hw/virtio/vhost.c | 3 +- | ||
101 | hw/xen/xen_pt_msi.c | 3 +- | ||
102 | memory.c | 12 ++-- | ||
103 | memory_ldst.inc.c | 18 +++--- | ||
104 | target/arm/gdbstub.c | 3 +- | ||
105 | target/arm/helper-a64.c | 41 +++++++------ | ||
106 | target/arm/helper.c | 90 ++++++++++++++++------------- | ||
107 | target/ppc/mmu-hash64.c | 3 +- | ||
108 | target/riscv/helper.c | 2 +- | ||
109 | target/s390x/diag.c | 6 +- | ||
110 | target/s390x/excp_helper.c | 3 +- | ||
111 | target/s390x/mmu_helper.c | 3 +- | ||
112 | target/s390x/sigp.c | 3 +- | ||
113 | target/xtensa/op_helper.c | 3 +- | ||
114 | MAINTAINERS | 9 ++- | ||
115 | 34 files changed, 353 insertions(+), 182 deletions(-) | ||
116 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Depending on the host abi, float16, aka uint16_t, values are | 3 | The functions vmsa_ttbcr_write and vmsa_ttbcr_raw_write expect |
4 | passed and returned either zero-extended in the host register | 4 | the offset to be for the complete TCR structure, not the offset |
5 | or with garbage at the top of the host register. | 5 | to the low 32-bits of a uint64_t. Using offsetoflow32 in this |
6 | case breaks big-endian hosts. | ||
6 | 7 | ||
7 | The tcg code generator has so far been assuming garbage, as that | 8 | For TTBCR2, we do want the high 32-bits of a uint64_t. |
8 | matches the x86 abi, but this is incorrect for other host abis. | 9 | Use cp15.tcr_el[*].raw_tcr as the offsetofhigh32 argument to |
9 | Further, target/arm has so far been assuming zero-extended results, | 10 | clarify this. |
10 | so that it may store the 16-bit value into a 32-bit slot with the | ||
11 | high 16-bits already clear. | ||
12 | 11 | ||
13 | Rectify both problems by mapping "f16" in the helper definition | 12 | Buglink: https://gitlab.com/qemu-project/qemu/-/issues/187 |
14 | to uint32_t instead of (a typedef for) uint16_t. This forces | ||
15 | the host compiler to assume garbage in the upper 16 bits on input | ||
16 | and to zero-extend the result on output. | ||
17 | |||
18 | Cc: qemu-stable@nongnu.org | ||
19 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
20 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 14 | Message-id: 20210709230621.938821-2-richard.henderson@linaro.org |
21 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
22 | Message-id: 20180522175629.24932-1-richard.henderson@linaro.org | ||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | --- | 17 | --- |
26 | include/exec/helper-head.h | 2 +- | 18 | target/arm/helper.c | 11 +++++++---- |
27 | target/arm/helper-a64.c | 35 +++++++++-------- | 19 | 1 file changed, 7 insertions(+), 4 deletions(-) |
28 | target/arm/helper.c | 80 +++++++++++++++++++------------------- | ||
29 | 3 files changed, 59 insertions(+), 58 deletions(-) | ||
30 | 20 | ||
31 | diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/include/exec/helper-head.h | ||
34 | +++ b/include/exec/helper-head.h | ||
35 | @@ -XXX,XX +XXX,XX @@ | ||
36 | #define dh_ctype_int int | ||
37 | #define dh_ctype_i64 uint64_t | ||
38 | #define dh_ctype_s64 int64_t | ||
39 | -#define dh_ctype_f16 float16 | ||
40 | +#define dh_ctype_f16 uint32_t | ||
41 | #define dh_ctype_f32 float32 | ||
42 | #define dh_ctype_f64 float64 | ||
43 | #define dh_ctype_ptr void * | ||
44 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/helper-a64.c | ||
47 | +++ b/target/arm/helper-a64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res) | ||
49 | return flags; | ||
50 | } | ||
51 | |||
52 | -uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status) | ||
53 | +uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status) | ||
54 | { | ||
55 | return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); | ||
56 | } | ||
57 | |||
58 | -uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status) | ||
59 | +uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status) | ||
60 | { | ||
61 | return float_rel_to_flags(float16_compare(x, y, fp_status)); | ||
62 | } | ||
63 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) | ||
64 | #define float64_three make_float64(0x4008000000000000ULL) | ||
65 | #define float64_one_point_five make_float64(0x3FF8000000000000ULL) | ||
66 | |||
67 | -float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp) | ||
68 | +uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
69 | { | ||
70 | float_status *fpst = fpstp; | ||
71 | |||
72 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp) | ||
73 | return float64_muladd(a, b, float64_two, 0, fpst); | ||
74 | } | ||
75 | |||
76 | -float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp) | ||
77 | +uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
78 | { | ||
79 | float_status *fpst = fpstp; | ||
80 | |||
81 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a) | ||
82 | } | ||
83 | |||
84 | /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ | ||
85 | -float16 HELPER(frecpx_f16)(float16 a, void *fpstp) | ||
86 | +uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) | ||
87 | { | ||
88 | float_status *fpst = fpstp; | ||
89 | uint16_t val16, sbit; | ||
90 | @@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, | ||
91 | #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) | ||
92 | |||
93 | #define ADVSIMD_HALFOP(name) \ | ||
94 | -float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ | ||
95 | +uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \ | ||
96 | { \ | ||
97 | float_status *fpst = fpstp; \ | ||
98 | return float16_ ## name(a, b, fpst); \ | ||
99 | @@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx) | ||
100 | ADVSIMD_TWOHALFOP(mulx) | ||
101 | |||
102 | /* fused multiply-accumulate */ | ||
103 | -float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) | ||
104 | +uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c, | ||
105 | + void *fpstp) | ||
106 | { | ||
107 | float_status *fpst = fpstp; | ||
108 | return float16_muladd(a, b, c, 0, fpst); | ||
109 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b, | ||
110 | |||
111 | #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 | ||
112 | |||
113 | -uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) | ||
114 | +uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
115 | { | ||
116 | float_status *fpst = fpstp; | ||
117 | int compare = float16_compare_quiet(a, b, fpst); | ||
118 | return ADVSIMD_CMPRES(compare == float_relation_equal); | ||
119 | } | ||
120 | |||
121 | -uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) | ||
122 | +uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
123 | { | ||
124 | float_status *fpst = fpstp; | ||
125 | int compare = float16_compare(a, b, fpst); | ||
126 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) | ||
127 | compare == float_relation_equal); | ||
128 | } | ||
129 | |||
130 | -uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) | ||
131 | +uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
132 | { | ||
133 | float_status *fpst = fpstp; | ||
134 | int compare = float16_compare(a, b, fpst); | ||
135 | return ADVSIMD_CMPRES(compare == float_relation_greater); | ||
136 | } | ||
137 | |||
138 | -uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) | ||
139 | +uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
140 | { | ||
141 | float_status *fpst = fpstp; | ||
142 | float16 f0 = float16_abs(a); | ||
143 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) | ||
144 | compare == float_relation_equal); | ||
145 | } | ||
146 | |||
147 | -uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) | ||
148 | +uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp) | ||
149 | { | ||
150 | float_status *fpst = fpstp; | ||
151 | float16 f0 = float16_abs(a); | ||
152 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) | ||
153 | } | ||
154 | |||
155 | /* round to integral */ | ||
156 | -float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status) | ||
157 | +uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status) | ||
158 | { | ||
159 | return float16_round_to_int(x, fp_status); | ||
160 | } | ||
161 | |||
162 | -float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) | ||
163 | +uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status) | ||
164 | { | ||
165 | int old_flags = get_float_exception_flags(fp_status), new_flags; | ||
166 | float16 ret; | ||
167 | @@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) | ||
168 | * setting the mode appropriately before calling the helper. | ||
169 | */ | ||
170 | |||
171 | -uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) | ||
172 | +uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp) | ||
173 | { | ||
174 | float_status *fpst = fpstp; | ||
175 | |||
176 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) | ||
177 | return float16_to_int16(a, fpst); | ||
178 | } | ||
179 | |||
180 | -uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) | ||
181 | +uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp) | ||
182 | { | ||
183 | float_status *fpst = fpstp; | ||
184 | |||
185 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) | ||
186 | * Square Root and Reciprocal square root | ||
187 | */ | ||
188 | |||
189 | -float16 HELPER(sqrt_f16)(float16 a, void *fpstp) | ||
190 | +uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp) | ||
191 | { | ||
192 | float_status *s = fpstp; | ||
193 | |||
194 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 21 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
195 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
196 | --- a/target/arm/helper.c | 23 | --- a/target/arm/helper.c |
197 | +++ b/target/arm/helper.c | 24 | +++ b/target/arm/helper.c |
198 | @@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64) | 25 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { |
199 | 26 | .access = PL1_RW, .accessfn = access_tvm_trvm, | |
200 | /* Integer to float and float to integer conversions */ | 27 | .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write, |
201 | 28 | .raw_writefn = vmsa_ttbcr_raw_write, | |
202 | -#define CONV_ITOF(name, fsz, sign) \ | 29 | - .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]), |
203 | - float##fsz HELPER(name)(uint32_t x, void *fpstp) \ | 30 | - offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, |
204 | -{ \ | 31 | + /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ |
205 | - float_status *fpst = fpstp; \ | 32 | + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.tcr_el[3]), |
206 | - return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ | 33 | + offsetof(CPUARMState, cp15.tcr_el[1])} }, |
207 | +#define CONV_ITOF(name, ftype, fsz, sign) \ | 34 | REGINFO_SENTINEL |
208 | +ftype HELPER(name)(uint32_t x, void *fpstp) \ | 35 | }; |
209 | +{ \ | 36 | |
210 | + float_status *fpst = fpstp; \ | 37 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ttbcr2_reginfo = { |
211 | + return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ | 38 | .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3, |
212 | } | 39 | .access = PL1_RW, .accessfn = access_tvm_trvm, |
213 | 40 | .type = ARM_CP_ALIAS, | |
214 | -#define CONV_FTOI(name, fsz, sign, round) \ | 41 | - .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), |
215 | -uint32_t HELPER(name)(float##fsz x, void *fpstp) \ | 42 | - offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, |
216 | -{ \ | 43 | + .bank_fieldoffsets = { |
217 | - float_status *fpst = fpstp; \ | 44 | + offsetofhigh32(CPUARMState, cp15.tcr_el[3].raw_tcr), |
218 | - if (float##fsz##_is_any_nan(x)) { \ | 45 | + offsetofhigh32(CPUARMState, cp15.tcr_el[1].raw_tcr), |
219 | - float_raise(float_flag_invalid, fpst); \ | 46 | + }, |
220 | - return 0; \ | 47 | }; |
221 | - } \ | 48 | |
222 | - return float##fsz##_to_##sign##int32##round(x, fpst); \ | 49 | static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, |
223 | +#define CONV_FTOI(name, ftype, fsz, sign, round) \ | ||
224 | +uint32_t HELPER(name)(ftype x, void *fpstp) \ | ||
225 | +{ \ | ||
226 | + float_status *fpst = fpstp; \ | ||
227 | + if (float##fsz##_is_any_nan(x)) { \ | ||
228 | + float_raise(float_flag_invalid, fpst); \ | ||
229 | + return 0; \ | ||
230 | + } \ | ||
231 | + return float##fsz##_to_##sign##int32##round(x, fpst); \ | ||
232 | } | ||
233 | |||
234 | -#define FLOAT_CONVS(name, p, fsz, sign) \ | ||
235 | -CONV_ITOF(vfp_##name##to##p, fsz, sign) \ | ||
236 | -CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ | ||
237 | -CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) | ||
238 | +#define FLOAT_CONVS(name, p, ftype, fsz, sign) \ | ||
239 | + CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ | ||
240 | + CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ | ||
241 | + CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) | ||
242 | |||
243 | -FLOAT_CONVS(si, h, 16, ) | ||
244 | -FLOAT_CONVS(si, s, 32, ) | ||
245 | -FLOAT_CONVS(si, d, 64, ) | ||
246 | -FLOAT_CONVS(ui, h, 16, u) | ||
247 | -FLOAT_CONVS(ui, s, 32, u) | ||
248 | -FLOAT_CONVS(ui, d, 64, u) | ||
249 | +FLOAT_CONVS(si, h, uint32_t, 16, ) | ||
250 | +FLOAT_CONVS(si, s, float32, 32, ) | ||
251 | +FLOAT_CONVS(si, d, float64, 64, ) | ||
252 | +FLOAT_CONVS(ui, h, uint32_t, 16, u) | ||
253 | +FLOAT_CONVS(ui, s, float32, 32, u) | ||
254 | +FLOAT_CONVS(ui, d, float64, 64, u) | ||
255 | |||
256 | #undef CONV_ITOF | ||
257 | #undef CONV_FTOI | ||
258 | @@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst) | ||
259 | return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst); | ||
260 | } | ||
261 | |||
262 | -float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst) | ||
263 | +uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst) | ||
264 | { | ||
265 | return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst); | ||
266 | } | ||
267 | |||
268 | -float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) | ||
269 | +uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) | ||
270 | { | ||
271 | return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst); | ||
272 | } | ||
273 | |||
274 | -float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) | ||
275 | +uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) | ||
276 | { | ||
277 | return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst); | ||
278 | } | ||
279 | |||
280 | -float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) | ||
281 | +uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) | ||
282 | { | ||
283 | return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst); | ||
284 | } | ||
285 | @@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst) | ||
286 | } | ||
287 | } | ||
288 | |||
289 | -uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst) | ||
290 | +uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst) | ||
291 | { | ||
292 | return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst); | ||
293 | } | ||
294 | |||
295 | -uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst) | ||
296 | +uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst) | ||
297 | { | ||
298 | return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst); | ||
299 | } | ||
300 | |||
301 | -uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst) | ||
302 | +uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst) | ||
303 | { | ||
304 | return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst); | ||
305 | } | ||
306 | |||
307 | -uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst) | ||
308 | +uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst) | ||
309 | { | ||
310 | return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst); | ||
311 | } | ||
312 | |||
313 | -uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst) | ||
314 | +uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst) | ||
315 | { | ||
316 | return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst); | ||
317 | } | ||
318 | |||
319 | -uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst) | ||
320 | +uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst) | ||
321 | { | ||
322 | return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst); | ||
323 | } | ||
324 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) | ||
325 | } | ||
326 | |||
327 | /* Half precision conversions. */ | ||
328 | -float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) | ||
329 | +float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode) | ||
330 | { | ||
331 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | ||
332 | * it would affect flushing input denormals. | ||
333 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) | ||
334 | return r; | ||
335 | } | ||
336 | |||
337 | -float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) | ||
338 | +uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) | ||
339 | { | ||
340 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | ||
341 | * it would affect flushing output denormals. | ||
342 | @@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) | ||
343 | return r; | ||
344 | } | ||
345 | |||
346 | -float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) | ||
347 | +float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode) | ||
348 | { | ||
349 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | ||
350 | * it would affect flushing input denormals. | ||
351 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) | ||
352 | return r; | ||
353 | } | ||
354 | |||
355 | -float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) | ||
356 | +uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) | ||
357 | { | ||
358 | /* Squash FZ16 to 0 for the duration of conversion. In this case, | ||
359 | * it would affect flushing output denormals. | ||
360 | @@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit) | ||
361 | g_assert_not_reached(); | ||
362 | } | ||
363 | |||
364 | -float16 HELPER(recpe_f16)(float16 input, void *fpstp) | ||
365 | +uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp) | ||
366 | { | ||
367 | float_status *fpst = fpstp; | ||
368 | float16 f16 = float16_squash_input_denormal(input, fpst); | ||
369 | @@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) | ||
370 | return extract64(estimate, 0, 8) << 44; | ||
371 | } | ||
372 | |||
373 | -float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) | ||
374 | +uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp) | ||
375 | { | ||
376 | float_status *s = fpstp; | ||
377 | float16 f16 = float16_squash_input_denormal(input, s); | ||
378 | -- | 50 | -- |
379 | 2.17.1 | 51 | 2.20.1 |
380 | 52 | ||
381 | 53 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | In commit 6d8980a38fa we updated the copyright string we present to |
---|---|---|---|
2 | add MemTxAttrs as an argument to the MemoryRegion valid.accepts | 2 | the user in -version output, About dialogs, etc, but we forgot that |
3 | callback. We'll need this for subpage_accepts(). | 3 | the Sphinx manuals have a separate copyright string setting. Update |
4 | 4 | that one too. | |
5 | We could take the approach we used with the read and write | ||
6 | callbacks and add new a new _with_attrs version, but since there | ||
7 | are so few implementations of the accepts hook we just change | ||
8 | them all. | ||
9 | 5 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Acked-by: Markus Armbruster <armbru@redhat.com> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
13 | Message-id: 20180521140402.23318-9-peter.maydell@linaro.org | 9 | Message-id: 20210705095547.15790-2-peter.maydell@linaro.org |
14 | --- | 10 | --- |
15 | include/exec/memory.h | 3 ++- | 11 | docs/conf.py | 2 +- |
16 | exec.c | 9 ++++++--- | 12 | 1 file changed, 1 insertion(+), 1 deletion(-) |
17 | hw/hppa/dino.c | 3 ++- | ||
18 | hw/nvram/fw_cfg.c | 12 ++++++++---- | ||
19 | hw/scsi/esp.c | 3 ++- | ||
20 | hw/xen/xen_pt_msi.c | 3 ++- | ||
21 | memory.c | 5 +++-- | ||
22 | 7 files changed, 25 insertions(+), 13 deletions(-) | ||
23 | 13 | ||
24 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 14 | diff --git a/docs/conf.py b/docs/conf.py |
25 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/include/exec/memory.h | 16 | --- a/docs/conf.py |
27 | +++ b/include/exec/memory.h | 17 | +++ b/docs/conf.py |
28 | @@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps { | 18 | @@ -XXX,XX +XXX,XX @@ |
29 | * as a machine check exception). | 19 | |
30 | */ | 20 | # General information about the project. |
31 | bool (*accepts)(void *opaque, hwaddr addr, | 21 | project = u'QEMU' |
32 | - unsigned size, bool is_write); | 22 | -copyright = u'2020, The QEMU Project Developers' |
33 | + unsigned size, bool is_write, | 23 | +copyright = u'2021, The QEMU Project Developers' |
34 | + MemTxAttrs attrs); | 24 | author = u'The QEMU Project Developers' |
35 | } valid; | 25 | |
36 | /* Internal implementation constraints: */ | 26 | # The version info for the project you're documenting, acts as replacement for |
37 | struct { | ||
38 | diff --git a/exec.c b/exec.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/exec.c | ||
41 | +++ b/exec.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr, | ||
43 | } | ||
44 | |||
45 | static bool notdirty_mem_accepts(void *opaque, hwaddr addr, | ||
46 | - unsigned size, bool is_write) | ||
47 | + unsigned size, bool is_write, | ||
48 | + MemTxAttrs attrs) | ||
49 | { | ||
50 | return is_write; | ||
51 | } | ||
52 | @@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, | ||
53 | } | ||
54 | |||
55 | static bool subpage_accepts(void *opaque, hwaddr addr, | ||
56 | - unsigned len, bool is_write) | ||
57 | + unsigned len, bool is_write, | ||
58 | + MemTxAttrs attrs) | ||
59 | { | ||
60 | subpage_t *subpage = opaque; | ||
61 | #if defined(DEBUG_SUBPAGE) | ||
62 | @@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr, | ||
63 | } | ||
64 | |||
65 | static bool readonly_mem_accepts(void *opaque, hwaddr addr, | ||
66 | - unsigned size, bool is_write) | ||
67 | + unsigned size, bool is_write, | ||
68 | + MemTxAttrs attrs) | ||
69 | { | ||
70 | return is_write; | ||
71 | } | ||
72 | diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/hw/hppa/dino.c | ||
75 | +++ b/hw/hppa/dino.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s) | ||
77 | } | ||
78 | |||
79 | static bool dino_chip_mem_valid(void *opaque, hwaddr addr, | ||
80 | - unsigned size, bool is_write) | ||
81 | + unsigned size, bool is_write, | ||
82 | + MemTxAttrs attrs) | ||
83 | { | ||
84 | switch (addr) { | ||
85 | case DINO_IAR0: | ||
86 | diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | ||
88 | --- a/hw/nvram/fw_cfg.c | ||
89 | +++ b/hw/nvram/fw_cfg.c | ||
90 | @@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, | ||
91 | } | ||
92 | |||
93 | static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, | ||
94 | - unsigned size, bool is_write) | ||
95 | + unsigned size, bool is_write, | ||
96 | + MemTxAttrs attrs) | ||
97 | { | ||
98 | return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || | ||
99 | (size == 8 && addr == 0)); | ||
100 | } | ||
101 | |||
102 | static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, | ||
103 | - unsigned size, bool is_write) | ||
104 | + unsigned size, bool is_write, | ||
105 | + MemTxAttrs attrs) | ||
106 | { | ||
107 | return addr == 0; | ||
108 | } | ||
109 | @@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, | ||
110 | } | ||
111 | |||
112 | static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, | ||
113 | - unsigned size, bool is_write) | ||
114 | + unsigned size, bool is_write, | ||
115 | + MemTxAttrs attrs) | ||
116 | { | ||
117 | return is_write && size == 2; | ||
118 | } | ||
119 | @@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr, | ||
120 | } | ||
121 | |||
122 | static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, | ||
123 | - unsigned size, bool is_write) | ||
124 | + unsigned size, bool is_write, | ||
125 | + MemTxAttrs attrs) | ||
126 | { | ||
127 | return (size == 1) || (is_write && size == 2); | ||
128 | } | ||
129 | diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c | ||
130 | index XXXXXXX..XXXXXXX 100644 | ||
131 | --- a/hw/scsi/esp.c | ||
132 | +++ b/hw/scsi/esp.c | ||
133 | @@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) | ||
134 | } | ||
135 | |||
136 | static bool esp_mem_accepts(void *opaque, hwaddr addr, | ||
137 | - unsigned size, bool is_write) | ||
138 | + unsigned size, bool is_write, | ||
139 | + MemTxAttrs attrs) | ||
140 | { | ||
141 | return (size == 1) || (is_write && size == 4); | ||
142 | } | ||
143 | diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c | ||
144 | index XXXXXXX..XXXXXXX 100644 | ||
145 | --- a/hw/xen/xen_pt_msi.c | ||
146 | +++ b/hw/xen/xen_pt_msi.c | ||
147 | @@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr, | ||
148 | } | ||
149 | |||
150 | static bool pci_msix_accepts(void *opaque, hwaddr addr, | ||
151 | - unsigned size, bool is_write) | ||
152 | + unsigned size, bool is_write, | ||
153 | + MemTxAttrs attrs) | ||
154 | { | ||
155 | return !(addr & (size - 1)); | ||
156 | } | ||
157 | diff --git a/memory.c b/memory.c | ||
158 | index XXXXXXX..XXXXXXX 100644 | ||
159 | --- a/memory.c | ||
160 | +++ b/memory.c | ||
161 | @@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr, | ||
162 | } | ||
163 | |||
164 | static bool unassigned_mem_accepts(void *opaque, hwaddr addr, | ||
165 | - unsigned size, bool is_write) | ||
166 | + unsigned size, bool is_write, | ||
167 | + MemTxAttrs attrs) | ||
168 | { | ||
169 | return false; | ||
170 | } | ||
171 | @@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr, | ||
172 | access_size = MAX(MIN(size, access_size_max), access_size_min); | ||
173 | for (i = 0; i < size; i += access_size) { | ||
174 | if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size, | ||
175 | - is_write)) { | ||
176 | + is_write, attrs)) { | ||
177 | return false; | ||
178 | } | ||
179 | } | ||
180 | -- | 27 | -- |
181 | 2.17.1 | 28 | 2.20.1 |
182 | 29 | ||
183 | 30 | diff view generated by jsdifflib |
1 | Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY | 1 | We merged our previous multiple-manual setup into a single Sphinx |
---|---|---|---|
2 | and friends. | 2 | manual, but we left some text in the various index.rst lines that |
3 | still calls the top level subsections separate 'manuals'. Update | ||
4 | them to talk about "this section of the manual" instead, and remove | ||
5 | now-obsolete comments about how the index.rst files are the "top | ||
6 | level page for the 'foo' manual". | ||
3 | 7 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 9 | Acked-by: Markus Armbruster <armbru@redhat.com> |
6 | Message-id: 20180521140402.23318-23-peter.maydell@linaro.org | 10 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
11 | Message-id: 20210705095547.15790-3-peter.maydell@linaro.org | ||
7 | --- | 12 | --- |
8 | include/migration/vmstate.h | 3 +++ | 13 | docs/devel/index.rst | 5 +---- |
9 | 1 file changed, 3 insertions(+) | 14 | docs/interop/index.rst | 7 ++----- |
15 | docs/specs/index.rst | 5 ++--- | ||
16 | docs/system/index.rst | 5 +---- | ||
17 | docs/tools/index.rst | 5 ++--- | ||
18 | docs/user/index.rst | 5 +---- | ||
19 | 6 files changed, 9 insertions(+), 23 deletions(-) | ||
10 | 20 | ||
11 | diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h | 21 | diff --git a/docs/devel/index.rst b/docs/devel/index.rst |
12 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/include/migration/vmstate.h | 23 | --- a/docs/devel/index.rst |
14 | +++ b/include/migration/vmstate.h | 24 | +++ b/docs/devel/index.rst |
15 | @@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq; | 25 | @@ -XXX,XX +XXX,XX @@ |
16 | #define VMSTATE_BOOL_ARRAY(_f, _s, _n) \ | 26 | -.. This is the top level page for the 'devel' manual. |
17 | VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0) | 27 | - |
18 | 28 | - | |
19 | +#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num) \ | 29 | Developer Information |
20 | + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool) | 30 | ===================== |
21 | + | 31 | |
22 | #define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v) \ | 32 | -This manual documents various parts of the internals of QEMU. |
23 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t) | 33 | +This section of the manual documents various parts of the internals of QEMU. |
34 | You only need to read it if you are interested in reading or | ||
35 | modifying QEMU's source code. | ||
36 | |||
37 | diff --git a/docs/interop/index.rst b/docs/interop/index.rst | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/docs/interop/index.rst | ||
40 | +++ b/docs/interop/index.rst | ||
41 | @@ -XXX,XX +XXX,XX @@ | ||
42 | -.. This is the top level page for the 'interop' manual. | ||
43 | - | ||
44 | - | ||
45 | System Emulation Management and Interoperability | ||
46 | ================================================ | ||
47 | |||
48 | -This manual contains documents and specifications that are useful | ||
49 | -for making QEMU interoperate with other software. | ||
50 | +This section of the manual contains documents and specifications that | ||
51 | +are useful for making QEMU interoperate with other software. | ||
52 | |||
53 | Contents: | ||
54 | |||
55 | diff --git a/docs/specs/index.rst b/docs/specs/index.rst | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/docs/specs/index.rst | ||
58 | +++ b/docs/specs/index.rst | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | -.. This is the top level page for the 'specs' manual | ||
61 | - | ||
62 | - | ||
63 | System Emulation Guest Hardware Specifications | ||
64 | ============================================== | ||
65 | |||
66 | +This section of the manual contains specifications of | ||
67 | +guest hardware that is specific to QEMU. | ||
68 | |||
69 | Contents: | ||
70 | |||
71 | diff --git a/docs/system/index.rst b/docs/system/index.rst | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/docs/system/index.rst | ||
74 | +++ b/docs/system/index.rst | ||
75 | @@ -XXX,XX +XXX,XX @@ | ||
76 | -.. This is the top level page for the 'system' manual. | ||
77 | - | ||
78 | - | ||
79 | System Emulation | ||
80 | ================ | ||
81 | |||
82 | -This manual is the overall guide for users using QEMU | ||
83 | +This section of the manual is the overall guide for users using QEMU | ||
84 | for full system emulation (as opposed to user-mode emulation). | ||
85 | This includes working with hypervisors such as KVM, Xen, Hax | ||
86 | or Hypervisor.Framework. | ||
87 | diff --git a/docs/tools/index.rst b/docs/tools/index.rst | ||
88 | index XXXXXXX..XXXXXXX 100644 | ||
89 | --- a/docs/tools/index.rst | ||
90 | +++ b/docs/tools/index.rst | ||
91 | @@ -XXX,XX +XXX,XX @@ | ||
92 | -.. This is the top level page for the 'tools' manual | ||
93 | - | ||
94 | - | ||
95 | Tools | ||
96 | ===== | ||
97 | |||
98 | +This section of the manual documents QEMU's "tools": its | ||
99 | +command line utilities and other standalone programs. | ||
100 | |||
101 | Contents: | ||
102 | |||
103 | diff --git a/docs/user/index.rst b/docs/user/index.rst | ||
104 | index XXXXXXX..XXXXXXX 100644 | ||
105 | --- a/docs/user/index.rst | ||
106 | +++ b/docs/user/index.rst | ||
107 | @@ -XXX,XX +XXX,XX @@ | ||
108 | -.. This is the top level page for the 'user' manual. | ||
109 | - | ||
110 | - | ||
111 | User Mode Emulation | ||
112 | =================== | ||
113 | |||
114 | -This manual is the overall guide for users using QEMU | ||
115 | +This section of the manual is the overall guide for users using QEMU | ||
116 | for user-mode emulation. In this mode, QEMU can launch | ||
117 | processes compiled for one CPU on another CPU. | ||
24 | 118 | ||
25 | -- | 119 | -- |
26 | 2.17.1 | 120 | 2.20.1 |
27 | 121 | ||
28 | 122 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | Since the top-level subsections aren't self-contained manuals |
---|---|---|---|
2 | add MemTxAttrs as an argument to address_space_translate_iommu(). | 2 | any more, the "Contents:" lines at the top of each of their |
3 | index pages look a bit odd; remove them. | ||
3 | 4 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Acked-by: Markus Armbruster <armbru@redhat.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
7 | Message-id: 20180521140402.23318-14-peter.maydell@linaro.org | 8 | Message-id: 20210705095547.15790-4-peter.maydell@linaro.org |
8 | --- | 9 | --- |
9 | exec.c | 8 +++++--- | 10 | docs/devel/index.rst | 2 -- |
10 | 1 file changed, 5 insertions(+), 3 deletions(-) | 11 | docs/interop/index.rst | 2 -- |
12 | docs/specs/index.rst | 2 -- | ||
13 | docs/system/index.rst | 2 -- | ||
14 | docs/tools/index.rst | 2 -- | ||
15 | docs/user/index.rst | 2 -- | ||
16 | 6 files changed, 12 deletions(-) | ||
11 | 17 | ||
12 | diff --git a/exec.c b/exec.c | 18 | diff --git a/docs/devel/index.rst b/docs/devel/index.rst |
13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/exec.c | 20 | --- a/docs/devel/index.rst |
15 | +++ b/exec.c | 21 | +++ b/docs/devel/index.rst |
16 | @@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x | 22 | @@ -XXX,XX +XXX,XX @@ This section of the manual documents various parts of the internals of QEMU. |
17 | * @is_write: whether the translation operation is for write | 23 | You only need to read it if you are interested in reading or |
18 | * @is_mmio: whether this can be MMIO, set true if it can | 24 | modifying QEMU's source code. |
19 | * @target_as: the address space targeted by the IOMMU | 25 | |
20 | + * @attrs: transaction attributes | 26 | -Contents: |
21 | * | 27 | - |
22 | * This function is called from RCU critical section. It is the common | 28 | .. toctree:: |
23 | * part of flatview_do_translate and address_space_translate_cached. | 29 | :maxdepth: 2 |
24 | @@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm | 30 | :includehidden: |
25 | hwaddr *page_mask_out, | 31 | diff --git a/docs/interop/index.rst b/docs/interop/index.rst |
26 | bool is_write, | 32 | index XXXXXXX..XXXXXXX 100644 |
27 | bool is_mmio, | 33 | --- a/docs/interop/index.rst |
28 | - AddressSpace **target_as) | 34 | +++ b/docs/interop/index.rst |
29 | + AddressSpace **target_as, | 35 | @@ -XXX,XX +XXX,XX @@ System Emulation Management and Interoperability |
30 | + MemTxAttrs attrs) | 36 | This section of the manual contains documents and specifications that |
31 | { | 37 | are useful for making QEMU interoperate with other software. |
32 | MemoryRegionSection *section; | 38 | |
33 | hwaddr page_mask = (hwaddr)-1; | 39 | -Contents: |
34 | @@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv, | 40 | - |
35 | return address_space_translate_iommu(iommu_mr, xlat, | 41 | .. toctree:: |
36 | plen_out, page_mask_out, | 42 | :maxdepth: 2 |
37 | is_write, is_mmio, | 43 | |
38 | - target_as); | 44 | diff --git a/docs/specs/index.rst b/docs/specs/index.rst |
39 | + target_as, attrs); | 45 | index XXXXXXX..XXXXXXX 100644 |
40 | } | 46 | --- a/docs/specs/index.rst |
41 | if (page_mask_out) { | 47 | +++ b/docs/specs/index.rst |
42 | /* Not behind an IOMMU, use default page size. */ | 48 | @@ -XXX,XX +XXX,XX @@ System Emulation Guest Hardware Specifications |
43 | @@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached( | 49 | This section of the manual contains specifications of |
44 | 50 | guest hardware that is specific to QEMU. | |
45 | section = address_space_translate_iommu(iommu_mr, xlat, plen, | 51 | |
46 | NULL, is_write, true, | 52 | -Contents: |
47 | - &target_as); | 53 | - |
48 | + &target_as, attrs); | 54 | .. toctree:: |
49 | return section.mr; | 55 | :maxdepth: 2 |
50 | } | 56 | |
57 | diff --git a/docs/system/index.rst b/docs/system/index.rst | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/docs/system/index.rst | ||
60 | +++ b/docs/system/index.rst | ||
61 | @@ -XXX,XX +XXX,XX @@ for full system emulation (as opposed to user-mode emulation). | ||
62 | This includes working with hypervisors such as KVM, Xen, Hax | ||
63 | or Hypervisor.Framework. | ||
64 | |||
65 | -Contents: | ||
66 | - | ||
67 | .. toctree:: | ||
68 | :maxdepth: 3 | ||
69 | |||
70 | diff --git a/docs/tools/index.rst b/docs/tools/index.rst | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/docs/tools/index.rst | ||
73 | +++ b/docs/tools/index.rst | ||
74 | @@ -XXX,XX +XXX,XX @@ Tools | ||
75 | This section of the manual documents QEMU's "tools": its | ||
76 | command line utilities and other standalone programs. | ||
77 | |||
78 | -Contents: | ||
79 | - | ||
80 | .. toctree:: | ||
81 | :maxdepth: 2 | ||
82 | |||
83 | diff --git a/docs/user/index.rst b/docs/user/index.rst | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/docs/user/index.rst | ||
86 | +++ b/docs/user/index.rst | ||
87 | @@ -XXX,XX +XXX,XX @@ This section of the manual is the overall guide for users using QEMU | ||
88 | for user-mode emulation. In this mode, QEMU can launch | ||
89 | processes compiled for one CPU on another CPU. | ||
90 | |||
91 | -Contents: | ||
92 | - | ||
93 | .. toctree:: | ||
94 | :maxdepth: 2 | ||
51 | 95 | ||
52 | -- | 96 | -- |
53 | 2.17.1 | 97 | 2.20.1 |
54 | 98 | ||
55 | 99 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | Now that we have a single Sphinx manual rather than multiple manuals, |
---|---|---|---|
2 | add MemTxAttrs as an argument to flatview_access_valid(). | 2 | we can provide a better place for "common to all of QEMU" information |
3 | Its callers now all have an attrs value to hand, so we can | 3 | like the deprecation notices, build platforms, license information, |
4 | correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED. | 4 | which we currently have in the system/ manual even though it applies |
5 | to all of QEMU. | ||
6 | |||
7 | Create a new directory about/ on the same level as system/, user/, | ||
8 | etc, and move these documents there. | ||
5 | 9 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 11 | Acked-by: Markus Armbruster <armbru@redhat.com> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
9 | Message-id: 20180521140402.23318-10-peter.maydell@linaro.org | 13 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
14 | Message-id: 20210705095547.15790-5-peter.maydell@linaro.org | ||
10 | --- | 15 | --- |
11 | exec.c | 12 +++++------- | 16 | docs/{system => about}/build-platforms.rst | 0 |
12 | 1 file changed, 5 insertions(+), 7 deletions(-) | 17 | docs/{system => about}/deprecated.rst | 0 |
18 | docs/about/index.rst | 10 ++++++++++ | ||
19 | docs/{system => about}/license.rst | 0 | ||
20 | docs/{system => about}/removed-features.rst | 0 | ||
21 | docs/index.rst | 1 + | ||
22 | docs/system/index.rst | 4 ---- | ||
23 | 7 files changed, 11 insertions(+), 4 deletions(-) | ||
24 | rename docs/{system => about}/build-platforms.rst (100%) | ||
25 | rename docs/{system => about}/deprecated.rst (100%) | ||
26 | create mode 100644 docs/about/index.rst | ||
27 | rename docs/{system => about}/license.rst (100%) | ||
28 | rename docs/{system => about}/removed-features.rst (100%) | ||
13 | 29 | ||
14 | diff --git a/exec.c b/exec.c | 30 | diff --git a/docs/system/build-platforms.rst b/docs/about/build-platforms.rst |
31 | similarity index 100% | ||
32 | rename from docs/system/build-platforms.rst | ||
33 | rename to docs/about/build-platforms.rst | ||
34 | diff --git a/docs/system/deprecated.rst b/docs/about/deprecated.rst | ||
35 | similarity index 100% | ||
36 | rename from docs/system/deprecated.rst | ||
37 | rename to docs/about/deprecated.rst | ||
38 | diff --git a/docs/about/index.rst b/docs/about/index.rst | ||
39 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | ||
41 | --- /dev/null | ||
42 | +++ b/docs/about/index.rst | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +About QEMU | ||
45 | +========== | ||
46 | + | ||
47 | +.. toctree:: | ||
48 | + :maxdepth: 2 | ||
49 | + | ||
50 | + build-platforms | ||
51 | + deprecated | ||
52 | + removed-features | ||
53 | + license | ||
54 | diff --git a/docs/system/license.rst b/docs/about/license.rst | ||
55 | similarity index 100% | ||
56 | rename from docs/system/license.rst | ||
57 | rename to docs/about/license.rst | ||
58 | diff --git a/docs/system/removed-features.rst b/docs/about/removed-features.rst | ||
59 | similarity index 100% | ||
60 | rename from docs/system/removed-features.rst | ||
61 | rename to docs/about/removed-features.rst | ||
62 | diff --git a/docs/index.rst b/docs/index.rst | ||
15 | index XXXXXXX..XXXXXXX 100644 | 63 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/exec.c | 64 | --- a/docs/index.rst |
17 | +++ b/exec.c | 65 | +++ b/docs/index.rst |
18 | @@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | 66 | @@ -XXX,XX +XXX,XX @@ Welcome to QEMU's documentation! |
19 | static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | 67 | :maxdepth: 2 |
20 | const uint8_t *buf, int len); | 68 | :caption: Contents: |
21 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | 69 | |
22 | - bool is_write); | 70 | + about/index |
23 | + bool is_write, MemTxAttrs attrs); | 71 | system/index |
24 | 72 | user/index | |
25 | static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, | 73 | tools/index |
26 | unsigned len, MemTxAttrs attrs) | 74 | diff --git a/docs/system/index.rst b/docs/system/index.rst |
27 | @@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr, | 75 | index XXXXXXX..XXXXXXX 100644 |
28 | #endif | 76 | --- a/docs/system/index.rst |
29 | 77 | +++ b/docs/system/index.rst | |
30 | return flatview_access_valid(subpage->fv, addr + subpage->base, | 78 | @@ -XXX,XX +XXX,XX @@ or Hypervisor.Framework. |
31 | - len, is_write); | 79 | targets |
32 | + len, is_write, attrs); | 80 | security |
33 | } | 81 | multi-process |
34 | 82 | - deprecated | |
35 | static const MemoryRegionOps subpage_ops = { | 83 | - removed-features |
36 | @@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void) | 84 | - build-platforms |
37 | } | 85 | - license |
38 | |||
39 | static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | ||
40 | - bool is_write) | ||
41 | + bool is_write, MemTxAttrs attrs) | ||
42 | { | ||
43 | MemoryRegion *mr; | ||
44 | hwaddr l, xlat; | ||
45 | @@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | ||
46 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); | ||
47 | if (!memory_access_is_direct(mr, is_write)) { | ||
48 | l = memory_access_size(mr, l, addr); | ||
49 | - /* When our callers all have attrs we'll pass them through here */ | ||
50 | - if (!memory_region_access_valid(mr, xlat, l, is_write, | ||
51 | - MEMTXATTRS_UNSPECIFIED)) { | ||
52 | + if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { | ||
53 | return false; | ||
54 | } | ||
55 | } | ||
56 | @@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, | ||
57 | |||
58 | rcu_read_lock(); | ||
59 | fv = address_space_to_flatview(as); | ||
60 | - result = flatview_access_valid(fv, addr, len, is_write); | ||
61 | + result = flatview_access_valid(fv, addr, len, is_write, attrs); | ||
62 | rcu_read_unlock(); | ||
63 | return result; | ||
64 | } | ||
65 | -- | 86 | -- |
66 | 2.17.1 | 87 | 2.20.1 |
67 | 88 | ||
68 | 89 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | Add some text to About to act as a brief introduction to the QEMU |
---|---|---|---|
2 | add MemTxAttrs as an argument to tb_invalidate_phys_addr(). | 2 | manual and to make the about page a bit less of an abrupt start to |
3 | Its callers either have an attrs value to hand, or don't care | 3 | it. |
4 | and can use MEMTXATTRS_UNSPECIFIED. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Acked-by: Markus Armbruster <armbru@redhat.com> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
9 | Message-id: 20180521140402.23318-3-peter.maydell@linaro.org | 8 | Message-id: 20210705095547.15790-6-peter.maydell@linaro.org |
10 | --- | 9 | --- |
11 | include/exec/exec-all.h | 5 +++-- | 10 | docs/about/index.rst | 17 +++++++++++++++++ |
12 | accel/tcg/translate-all.c | 2 +- | 11 | 1 file changed, 17 insertions(+) |
13 | exec.c | 2 +- | ||
14 | target/xtensa/op_helper.c | 3 ++- | ||
15 | 4 files changed, 7 insertions(+), 5 deletions(-) | ||
16 | 12 | ||
17 | diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h | 13 | diff --git a/docs/about/index.rst b/docs/about/index.rst |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/exec/exec-all.h | 15 | --- a/docs/about/index.rst |
20 | +++ b/include/exec/exec-all.h | 16 | +++ b/docs/about/index.rst |
21 | @@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, | 17 | @@ -XXX,XX +XXX,XX @@ |
22 | void tlb_set_page(CPUState *cpu, target_ulong vaddr, | 18 | About QEMU |
23 | hwaddr paddr, int prot, | 19 | ========== |
24 | int mmu_idx, target_ulong size); | 20 | |
25 | -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); | 21 | +QEMU is a generic and open source machine emulator and virtualizer. |
26 | +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); | 22 | + |
27 | void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, | 23 | +QEMU can be used in several different ways. The most common is for |
28 | uintptr_t retaddr); | 24 | +"system emulation", where it provides a virtual model of an |
29 | #else | 25 | +entire machine (CPU, memory and emulated devices) to run a guest OS. |
30 | @@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, | 26 | +In this mode the CPU may be fully emulated, or it may work with |
31 | uint16_t idxmap) | 27 | +a hypervisor such as KVM, Xen, Hax or Hypervisor.Framework to |
32 | { | 28 | +allow the guest to run directly on the host CPU. |
33 | } | 29 | + |
34 | -static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) | 30 | +The second supported way to use QEMU is "user mode emulation", |
35 | +static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, | 31 | +where QEMU can launch processes compiled for one CPU on another CPU. |
36 | + MemTxAttrs attrs) | 32 | +In this mode the CPU is always emulated. |
37 | { | 33 | + |
38 | } | 34 | +QEMU also provides a number of standalone commandline utilities, |
39 | #endif | 35 | +such as the `qemu-img` disk image utility that allows you to create, |
40 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | 36 | +convert and modify disk images. |
41 | index XXXXXXX..XXXXXXX 100644 | 37 | + |
42 | --- a/accel/tcg/translate-all.c | 38 | .. toctree:: |
43 | +++ b/accel/tcg/translate-all.c | 39 | :maxdepth: 2 |
44 | @@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) | ||
45 | } | ||
46 | |||
47 | #if !defined(CONFIG_USER_ONLY) | ||
48 | -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) | ||
49 | +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) | ||
50 | { | ||
51 | ram_addr_t ram_addr; | ||
52 | MemoryRegion *mr; | ||
53 | diff --git a/exec.c b/exec.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/exec.c | ||
56 | +++ b/exec.c | ||
57 | @@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) | ||
58 | if (phys != -1) { | ||
59 | /* Locks grabbed by tb_invalidate_phys_addr */ | ||
60 | tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, | ||
61 | - phys | (pc & ~TARGET_PAGE_MASK)); | ||
62 | + phys | (pc & ~TARGET_PAGE_MASK), attrs); | ||
63 | } | ||
64 | } | ||
65 | #endif | ||
66 | diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/xtensa/op_helper.c | ||
69 | +++ b/target/xtensa/op_helper.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) | ||
71 | int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, | ||
72 | &paddr, &page_size, &access); | ||
73 | if (ret == 0) { | ||
74 | - tb_invalidate_phys_addr(&address_space_memory, paddr); | ||
75 | + tb_invalidate_phys_addr(&address_space_memory, paddr, | ||
76 | + MEMTXATTRS_UNSPECIFIED); | ||
77 | } | ||
78 | } | ||
79 | 40 | ||
80 | -- | 41 | -- |
81 | 2.17.1 | 42 | 2.20.1 |
82 | 43 | ||
83 | 44 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | The standard Sphinx/RTD HTML page footer gives a copyright line |
---|---|---|---|
2 | add MemTxAttrs as an argument to flatview_do_translate(). | 2 | (based on the 'copyright' variable set in conf.py) and a line "Built |
3 | with Sphinx using a theme provided by Read the Docs" (which can be | ||
4 | disabled via the html_show_sphinx variable, but we leave it enabled). | ||
5 | As a free software project, we'd like to also mention the license | ||
6 | QEMU and its manual are released under. | ||
7 | |||
8 | Add a template footer.html which defines the 'extrafooter' block that | ||
9 | the RtD theme provides for this purpose. The new line of text will | ||
10 | go below the existing copyright and sphinx-acknowledgement lines. | ||
11 | (Unfortunately the RTD footer template does not permit putting it | ||
12 | after the copyright but before the sphinx-acknowledgement.) | ||
13 | |||
14 | We use the templating functionality to make the new text also be a | ||
15 | hyperlink to the about/license.html page of the manual. | ||
16 | |||
17 | Unlike rst files, HTML template files are not reported to our depfile | ||
18 | plugin, so we maintain a manual list in meson.build. New template | ||
19 | files should be rare, so not being able to auto-generate the | ||
20 | dependency info is not too awkward. | ||
3 | 21 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 23 | Acked-by: Markus Armbruster <armbru@redhat.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 24 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
7 | Message-id: 20180521140402.23318-13-peter.maydell@linaro.org | 25 | Message-id: 20210705095547.15790-7-peter.maydell@linaro.org |
8 | --- | 26 | --- |
9 | exec.c | 9 ++++++--- | 27 | docs/_templates/footer.html | 12 ++++++++++++ |
10 | 1 file changed, 6 insertions(+), 3 deletions(-) | 28 | docs/meson.build | 3 ++- |
29 | MAINTAINERS | 1 + | ||
30 | 3 files changed, 15 insertions(+), 1 deletion(-) | ||
31 | create mode 100644 docs/_templates/footer.html | ||
11 | 32 | ||
12 | diff --git a/exec.c b/exec.c | 33 | diff --git a/docs/_templates/footer.html b/docs/_templates/footer.html |
34 | new file mode 100644 | ||
35 | index XXXXXXX..XXXXXXX | ||
36 | --- /dev/null | ||
37 | +++ b/docs/_templates/footer.html | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | +{% extends "!footer.html" %} | ||
40 | +{% block extrafooter %} | ||
41 | + | ||
42 | +<!-- Empty para to force a blank line after "Built with Sphinx ..." --> | ||
43 | +<p></p> | ||
44 | + | ||
45 | +{% trans path=pathto('about/license') %} | ||
46 | +<p><a href="{{ path }}">QEMU and this manual are released under the | ||
47 | +GNU General Public License, version 2.</a></p> | ||
48 | +{% endtrans %} | ||
49 | +{{ super() }} | ||
50 | +{% endblock %} | ||
51 | diff --git a/docs/meson.build b/docs/meson.build | ||
13 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/exec.c | 53 | --- a/docs/meson.build |
15 | +++ b/exec.c | 54 | +++ b/docs/meson.build |
16 | @@ -XXX,XX +XXX,XX @@ unassigned: | 55 | @@ -XXX,XX +XXX,XX @@ if build_docs |
17 | * @is_write: whether the translation operation is for write | 56 | meson.source_root() / 'docs/sphinx/qapidoc.py', |
18 | * @is_mmio: whether this can be MMIO, set true if it can | 57 | meson.source_root() / 'docs/sphinx/qmp_lexer.py', |
19 | * @target_as: the address space targeted by the IOMMU | 58 | qapi_gen_depends ] |
20 | + * @attrs: memory transaction attributes | 59 | + sphinx_template_files = [ meson.source_root() / 'docs/_templates/footer.html' ] |
21 | * | 60 | |
22 | * This function is called from RCU critical section | 61 | have_ga = have_tools and config_host.has_key('CONFIG_GUEST_AGENT') |
23 | */ | 62 | |
24 | @@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv, | 63 | @@ -XXX,XX +XXX,XX @@ if build_docs |
25 | hwaddr *page_mask_out, | 64 | output: 'docs.stamp', |
26 | bool is_write, | 65 | input: files('conf.py'), |
27 | bool is_mmio, | 66 | depfile: 'docs.d', |
28 | - AddressSpace **target_as) | 67 | - depend_files: sphinx_extn_depends, |
29 | + AddressSpace **target_as, | 68 | + depend_files: [ sphinx_extn_depends, sphinx_template_files ], |
30 | + MemTxAttrs attrs) | 69 | command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@', |
31 | { | 70 | '-Ddepfile_stamp=@OUTPUT0@', |
32 | MemoryRegionSection *section; | 71 | '-b', 'html', '-d', private_dir, |
33 | IOMMUMemoryRegion *iommu_mr; | 72 | diff --git a/MAINTAINERS b/MAINTAINERS |
34 | @@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | 73 | index XXXXXXX..XXXXXXX 100644 |
35 | * but page mask. | 74 | --- a/MAINTAINERS |
36 | */ | 75 | +++ b/MAINTAINERS |
37 | section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, | 76 | @@ -XXX,XX +XXX,XX @@ S: Maintained |
38 | - NULL, &page_mask, is_write, false, &as); | 77 | F: docs/conf.py |
39 | + NULL, &page_mask, is_write, false, &as, | 78 | F: docs/*/conf.py |
40 | + attrs); | 79 | F: docs/sphinx/ |
41 | 80 | +F: docs/_templates/ | |
42 | /* Illegal translation */ | 81 | |
43 | if (section.mr == &io_mem_unassigned) { | 82 | Miscellaneous |
44 | @@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, | 83 | ------------- |
45 | |||
46 | /* This can be MMIO, so setup MMIO bit. */ | ||
47 | section = flatview_do_translate(fv, addr, xlat, plen, NULL, | ||
48 | - is_write, true, &as); | ||
49 | + is_write, true, &as, attrs); | ||
50 | mr = section.mr; | ||
51 | |||
52 | if (xen_enabled() && memory_access_is_direct(mr, is_write)) { | ||
53 | -- | 84 | -- |
54 | 2.17.1 | 85 | 2.20.1 |
55 | 86 | ||
56 | 87 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | Add a line to the HTML document footer mentioning the QEMU version. |
---|---|---|---|
2 | add MemTxAttrs as an argument to address_space_get_iotlb_entry(). | 2 | The version information is already provided in very faint text below |
3 | the QEMU logo in the sidebar, but that is rather inconspicious, so | ||
4 | repeating it in the footer seems useful. | ||
3 | 5 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 7 | Acked-by: Markus Armbruster <armbru@redhat.com> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
7 | Message-id: 20180521140402.23318-12-peter.maydell@linaro.org | 9 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> |
10 | Message-id: 20210705095547.15790-8-peter.maydell@linaro.org | ||
8 | --- | 11 | --- |
9 | include/exec/memory.h | 2 +- | 12 | docs/_templates/footer.html | 2 ++ |
10 | exec.c | 2 +- | 13 | 1 file changed, 2 insertions(+) |
11 | hw/virtio/vhost.c | 3 ++- | ||
12 | 3 files changed, 4 insertions(+), 3 deletions(-) | ||
13 | 14 | ||
14 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 15 | diff --git a/docs/_templates/footer.html b/docs/_templates/footer.html |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/exec/memory.h | 17 | --- a/docs/_templates/footer.html |
17 | +++ b/include/exec/memory.h | 18 | +++ b/docs/_templates/footer.html |
18 | @@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache); | 19 | @@ -XXX,XX +XXX,XX @@ |
19 | * entry. Should be called from an RCU critical section. | 20 | <!-- Empty para to force a blank line after "Built with Sphinx ..." --> |
20 | */ | 21 | <p></p> |
21 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | 22 | |
22 | - bool is_write); | 23 | +<p>This documentation is for QEMU version {{ version }}.</p> |
23 | + bool is_write, MemTxAttrs attrs); | 24 | + |
24 | 25 | {% trans path=pathto('about/license') %} | |
25 | /* address_space_translate: translate an address range into an address space | 26 | <p><a href="{{ path }}">QEMU and this manual are released under the |
26 | * into a MemoryRegion and an address range into that section. Should be | 27 | GNU General Public License, version 2.</a></p> |
27 | diff --git a/exec.c b/exec.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/exec.c | ||
30 | +++ b/exec.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv, | ||
32 | |||
33 | /* Called from RCU critical section */ | ||
34 | IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | ||
35 | - bool is_write) | ||
36 | + bool is_write, MemTxAttrs attrs) | ||
37 | { | ||
38 | MemoryRegionSection section; | ||
39 | hwaddr xlat, page_mask; | ||
40 | diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/virtio/vhost.c | ||
43 | +++ b/hw/virtio/vhost.c | ||
44 | @@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write) | ||
45 | trace_vhost_iotlb_miss(dev, 1); | ||
46 | |||
47 | iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as, | ||
48 | - iova, write); | ||
49 | + iova, write, | ||
50 | + MEMTXATTRS_UNSPECIFIED); | ||
51 | if (iotlb.target_as != NULL) { | ||
52 | ret = vhost_memory_region_lookup(dev, iotlb.translated_addr, | ||
53 | &uaddr, &len); | ||
54 | -- | 28 | -- |
55 | 2.17.1 | 29 | 2.20.1 |
56 | 30 | ||
57 | 31 | diff view generated by jsdifflib |
1 | Add more detail to the documentation for memory_region_init_iommu() | 1 | Add skeletal documentation of the cubieboard machine. |
---|---|---|---|
2 | and other IOMMU-related functions and data structures. | ||
3 | 2 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
7 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | 6 | Message-id: 20210713142226.19155-2-peter.maydell@linaro.org |
8 | Message-id: 20180521140402.23318-2-peter.maydell@linaro.org | ||
9 | --- | 7 | --- |
10 | include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++---- | 8 | docs/system/arm/cubieboard.rst | 16 ++++++++++++++++ |
11 | 1 file changed, 95 insertions(+), 10 deletions(-) | 9 | docs/system/target-arm.rst | 1 + |
10 | MAINTAINERS | 1 + | ||
11 | 3 files changed, 18 insertions(+) | ||
12 | create mode 100644 docs/system/arm/cubieboard.rst | ||
12 | 13 | ||
13 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 14 | diff --git a/docs/system/arm/cubieboard.rst b/docs/system/arm/cubieboard.rst |
15 | new file mode 100644 | ||
16 | index XXXXXXX..XXXXXXX | ||
17 | --- /dev/null | ||
18 | +++ b/docs/system/arm/cubieboard.rst | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | +Cubietech Cubieboard (``cubieboard``) | ||
21 | +===================================== | ||
22 | + | ||
23 | +The ``cubieboard`` model emulates the Cubietech Cubieboard, | ||
24 | +which is a Cortex-A8 based single-board computer using | ||
25 | +the AllWinner A10 SoC. | ||
26 | + | ||
27 | +Emulated devices: | ||
28 | + | ||
29 | +- Timer | ||
30 | +- UART | ||
31 | +- RTC | ||
32 | +- EMAC | ||
33 | +- SDHCI | ||
34 | +- USB controller | ||
35 | +- SATA controller | ||
36 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
14 | index XXXXXXX..XXXXXXX 100644 | 37 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/exec/memory.h | 38 | --- a/docs/system/target-arm.rst |
16 | +++ b/include/exec/memory.h | 39 | +++ b/docs/system/target-arm.rst |
17 | @@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr { | 40 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
18 | IOMMU_ATTR_SPAPR_TCE_FD | 41 | arm/aspeed |
19 | }; | 42 | arm/sabrelite |
20 | 43 | arm/digic | |
21 | +/** | 44 | + arm/cubieboard |
22 | + * IOMMUMemoryRegionClass: | 45 | arm/musicpal |
23 | + * | 46 | arm/gumstix |
24 | + * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION | 47 | arm/nrf |
25 | + * and provide an implementation of at least the @translate method here | 48 | diff --git a/MAINTAINERS b/MAINTAINERS |
26 | + * to handle requests to the memory region. Other methods are optional. | 49 | index XXXXXXX..XXXXXXX 100644 |
27 | + * | 50 | --- a/MAINTAINERS |
28 | + * The IOMMU implementation must use the IOMMU notifier infrastructure | 51 | +++ b/MAINTAINERS |
29 | + * to report whenever mappings are changed, by calling | 52 | @@ -XXX,XX +XXX,XX @@ S: Odd Fixes |
30 | + * memory_region_notify_iommu() (or, if necessary, by calling | 53 | F: hw/*/allwinner* |
31 | + * memory_region_notify_one() for each registered notifier). | 54 | F: include/hw/*/allwinner* |
32 | + */ | 55 | F: hw/arm/cubieboard.c |
33 | typedef struct IOMMUMemoryRegionClass { | 56 | +F: docs/system/arm/cubieboard.rst |
34 | /* private */ | 57 | |
35 | struct DeviceClass parent_class; | 58 | Allwinner-h3 |
36 | 59 | M: Niek Linnenbank <nieklinnenbank@gmail.com> | |
37 | /* | ||
38 | - * Return a TLB entry that contains a given address. Flag should | ||
39 | - * be the access permission of this translation operation. We can | ||
40 | - * set flag to IOMMU_NONE to mean that we don't need any | ||
41 | - * read/write permission checks, like, when for region replay. | ||
42 | + * Return a TLB entry that contains a given address. | ||
43 | + * | ||
44 | + * The IOMMUAccessFlags indicated via @flag are optional and may | ||
45 | + * be specified as IOMMU_NONE to indicate that the caller needs | ||
46 | + * the full translation information for both reads and writes. If | ||
47 | + * the access flags are specified then the IOMMU implementation | ||
48 | + * may use this as an optimization, to stop doing a page table | ||
49 | + * walk as soon as it knows that the requested permissions are not | ||
50 | + * allowed. If IOMMU_NONE is passed then the IOMMU must do the | ||
51 | + * full page table walk and report the permissions in the returned | ||
52 | + * IOMMUTLBEntry. (Note that this implies that an IOMMU may not | ||
53 | + * return different mappings for reads and writes.) | ||
54 | + * | ||
55 | + * The returned information remains valid while the caller is | ||
56 | + * holding the big QEMU lock or is inside an RCU critical section; | ||
57 | + * if the caller wishes to cache the mapping beyond that it must | ||
58 | + * register an IOMMU notifier so it can invalidate its cached | ||
59 | + * information when the IOMMU mapping changes. | ||
60 | + * | ||
61 | + * @iommu: the IOMMUMemoryRegion | ||
62 | + * @hwaddr: address to be translated within the memory region | ||
63 | + * @flag: requested access permissions | ||
64 | */ | ||
65 | IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr, | ||
66 | IOMMUAccessFlags flag); | ||
67 | - /* Returns minimum supported page size */ | ||
68 | + /* Returns minimum supported page size in bytes. | ||
69 | + * If this method is not provided then the minimum is assumed to | ||
70 | + * be TARGET_PAGE_SIZE. | ||
71 | + * | ||
72 | + * @iommu: the IOMMUMemoryRegion | ||
73 | + */ | ||
74 | uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu); | ||
75 | - /* Called when IOMMU Notifier flag changed */ | ||
76 | + /* Called when IOMMU Notifier flag changes (ie when the set of | ||
77 | + * events which IOMMU users are requesting notification for changes). | ||
78 | + * Optional method -- need not be provided if the IOMMU does not | ||
79 | + * need to know exactly which events must be notified. | ||
80 | + * | ||
81 | + * @iommu: the IOMMUMemoryRegion | ||
82 | + * @old_flags: events which previously needed to be notified | ||
83 | + * @new_flags: events which now need to be notified | ||
84 | + */ | ||
85 | void (*notify_flag_changed)(IOMMUMemoryRegion *iommu, | ||
86 | IOMMUNotifierFlag old_flags, | ||
87 | IOMMUNotifierFlag new_flags); | ||
88 | - /* Set this up to provide customized IOMMU replay function */ | ||
89 | + /* Called to handle memory_region_iommu_replay(). | ||
90 | + * | ||
91 | + * The default implementation of memory_region_iommu_replay() is to | ||
92 | + * call the IOMMU translate method for every page in the address space | ||
93 | + * with flag == IOMMU_NONE and then call the notifier if translate | ||
94 | + * returns a valid mapping. If this method is implemented then it | ||
95 | + * overrides the default behaviour, and must provide the full semantics | ||
96 | + * of memory_region_iommu_replay(), by calling @notifier for every | ||
97 | + * translation present in the IOMMU. | ||
98 | + * | ||
99 | + * Optional method -- an IOMMU only needs to provide this method | ||
100 | + * if the default is inefficient or produces undesirable side effects. | ||
101 | + * | ||
102 | + * Note: this is not related to record-and-replay functionality. | ||
103 | + */ | ||
104 | void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier); | ||
105 | |||
106 | - /* Get IOMMU misc attributes */ | ||
107 | - int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr, | ||
108 | + /* Get IOMMU misc attributes. This is an optional method that | ||
109 | + * can be used to allow users of the IOMMU to get implementation-specific | ||
110 | + * information. The IOMMU implements this method to handle calls | ||
111 | + * by IOMMU users to memory_region_iommu_get_attr() by filling in | ||
112 | + * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that | ||
113 | + * the IOMMU supports. If the method is unimplemented then | ||
114 | + * memory_region_iommu_get_attr() will always return -EINVAL. | ||
115 | + * | ||
116 | + * @iommu: the IOMMUMemoryRegion | ||
117 | + * @attr: attribute being queried | ||
118 | + * @data: memory to fill in with the attribute data | ||
119 | + * | ||
120 | + * Returns 0 on success, or a negative errno; in particular | ||
121 | + * returns -EINVAL for unrecognized or unimplemented attribute types. | ||
122 | + */ | ||
123 | + int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr, | ||
124 | void *data); | ||
125 | } IOMMUMemoryRegionClass; | ||
126 | |||
127 | @@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr, | ||
128 | * An IOMMU region translates addresses and forwards accesses to a target | ||
129 | * memory region. | ||
130 | * | ||
131 | + * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION. | ||
132 | + * @_iommu_mr should be a pointer to enough memory for an instance of | ||
133 | + * that subclass, @instance_size is the size of that subclass, and | ||
134 | + * @mrtypename is its name. This function will initialize @_iommu_mr as an | ||
135 | + * instance of the subclass, and its methods will then be called to handle | ||
136 | + * accesses to the memory region. See the documentation of | ||
137 | + * #IOMMUMemoryRegionClass for further details. | ||
138 | + * | ||
139 | * @_iommu_mr: the #IOMMUMemoryRegion to be initialized | ||
140 | * @instance_size: the IOMMUMemoryRegion subclass instance size | ||
141 | * @mrtypename: the type name of the #IOMMUMemoryRegion | ||
142 | @@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr, | ||
143 | * a notifier with the minimum page granularity returned by | ||
144 | * mr->iommu_ops->get_page_size(). | ||
145 | * | ||
146 | + * Note: this is not related to record-and-replay functionality. | ||
147 | + * | ||
148 | * @iommu_mr: the memory region to observe | ||
149 | * @n: the notifier to which to replay iommu mappings | ||
150 | */ | ||
151 | @@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n); | ||
152 | * memory_region_iommu_replay_all: replay existing IOMMU translations | ||
153 | * to all the notifiers registered. | ||
154 | * | ||
155 | + * Note: this is not related to record-and-replay functionality. | ||
156 | + * | ||
157 | * @iommu_mr: the memory region to observe | ||
158 | */ | ||
159 | void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr); | ||
160 | @@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr, | ||
161 | * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is | ||
162 | * defined on the IOMMU. | ||
163 | * | ||
164 | - * Returns 0 if succeded, error code otherwise. | ||
165 | + * Returns 0 on success, or a negative errno otherwise. In particular, | ||
166 | + * -EINVAL indicates that the IOMMU does not support the requested | ||
167 | + * attribute. | ||
168 | * | ||
169 | * @iommu_mr: the memory region | ||
170 | * @attr: the requested attribute | ||
171 | -- | 60 | -- |
172 | 2.17.1 | 61 | 2.20.1 |
173 | 62 | ||
174 | 63 | diff view generated by jsdifflib |
1 | Add entries to MAINTAINERS to cover the newer MPS2 boards and | 1 | Add skeletal documentation of the emcraft-sf2 machine. |
---|---|---|---|
2 | the new devices they use. | ||
3 | 2 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Message-id: 20180518153157.14899-1-peter.maydell@linaro.org | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Message-id: 20210713142226.19155-3-peter.maydell@linaro.org | ||
6 | --- | 7 | --- |
7 | MAINTAINERS | 9 +++++++-- | 8 | docs/system/arm/emcraft-sf2.rst | 15 +++++++++++++++ |
8 | 1 file changed, 7 insertions(+), 2 deletions(-) | 9 | docs/system/target-arm.rst | 1 + |
10 | MAINTAINERS | 1 + | ||
11 | 3 files changed, 17 insertions(+) | ||
12 | create mode 100644 docs/system/arm/emcraft-sf2.rst | ||
9 | 13 | ||
14 | diff --git a/docs/system/arm/emcraft-sf2.rst b/docs/system/arm/emcraft-sf2.rst | ||
15 | new file mode 100644 | ||
16 | index XXXXXXX..XXXXXXX | ||
17 | --- /dev/null | ||
18 | +++ b/docs/system/arm/emcraft-sf2.rst | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | +Emcraft SmartFusion2 SOM kit (``emcraft-sf2``) | ||
21 | +============================================== | ||
22 | + | ||
23 | +The ``emcraft-sf2`` board emulates the SmartFusion2 SOM kit from | ||
24 | +Emcraft (M2S010). This is a System-on-Module from EmCraft systems, | ||
25 | +based on the SmartFusion2 SoC FPGA from Microsemi Corporation. | ||
26 | +The SoC is based on a Cortex-M4 processor. | ||
27 | + | ||
28 | +Emulated devices: | ||
29 | + | ||
30 | +- System timer | ||
31 | +- System registers | ||
32 | +- SPI controller | ||
33 | +- UART | ||
34 | +- EMAC | ||
35 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/docs/system/target-arm.rst | ||
38 | +++ b/docs/system/target-arm.rst | ||
39 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | ||
40 | arm/sabrelite | ||
41 | arm/digic | ||
42 | arm/cubieboard | ||
43 | + arm/emcraft-sf2 | ||
44 | arm/musicpal | ||
45 | arm/gumstix | ||
46 | arm/nrf | ||
10 | diff --git a/MAINTAINERS b/MAINTAINERS | 47 | diff --git a/MAINTAINERS b/MAINTAINERS |
11 | index XXXXXXX..XXXXXXX 100644 | 48 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/MAINTAINERS | 49 | --- a/MAINTAINERS |
13 | +++ b/MAINTAINERS | 50 | +++ b/MAINTAINERS |
14 | @@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c | ||
15 | F: include/hw/timer/cmsdk-apb-timer.h | ||
16 | F: hw/char/cmsdk-apb-uart.c | ||
17 | F: include/hw/char/cmsdk-apb-uart.h | ||
18 | +F: hw/misc/tz-ppc.c | ||
19 | +F: include/hw/misc/tz-ppc.h | ||
20 | |||
21 | ARM cores | ||
22 | M: Peter Maydell <peter.maydell@linaro.org> | ||
23 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | 51 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> |
24 | L: qemu-arm@nongnu.org | 52 | L: qemu-arm@nongnu.org |
25 | S: Maintained | 53 | S: Maintained |
26 | F: hw/arm/mps2.c | 54 | F: hw/arm/msf2-som.c |
27 | -F: hw/misc/mps2-scc.c | 55 | +F: docs/system/arm/emcraft-sf2.rst |
28 | -F: include/hw/misc/mps2-scc.h | 56 | |
29 | +F: hw/arm/mps2-tz.c | 57 | ASPEED BMCs |
30 | +F: hw/misc/mps2-*.c | 58 | M: Cédric Le Goater <clg@kaod.org> |
31 | +F: include/hw/misc/mps2-*.h | ||
32 | +F: hw/arm/iotkit.c | ||
33 | +F: include/hw/arm/iotkit.h | ||
34 | |||
35 | Musicpal | ||
36 | M: Jan Kiszka <jan.kiszka@web.de> | ||
37 | -- | 59 | -- |
38 | 2.17.1 | 60 | 2.20.1 |
39 | 61 | ||
40 | 62 | diff view generated by jsdifflib |
1 | The FRECPX instructions should (like most other floating point operations) | 1 | Add skeletal documentation for the highbank and midway machines. |
---|---|---|---|
2 | honour the FPCR.FZ bit which specifies whether input denormals should | ||
3 | be flushed to zero (or FZ16 for the half-precision version). | ||
4 | We forgot to implement this, which doesn't affect the results (since | ||
5 | the calculation doesn't actually care about the mantissa bits) but did | ||
6 | mean we were failing to set the FPSR.IDC bit. | ||
7 | 2 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20180521172712.19930-1-peter.maydell@linaro.org | 5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
6 | Message-id: 20210713142226.19155-4-peter.maydell@linaro.org | ||
11 | --- | 7 | --- |
12 | target/arm/helper-a64.c | 6 ++++++ | 8 | docs/system/arm/highbank.rst | 19 +++++++++++++++++++ |
13 | 1 file changed, 6 insertions(+) | 9 | docs/system/target-arm.rst | 1 + |
10 | MAINTAINERS | 1 + | ||
11 | 3 files changed, 21 insertions(+) | ||
12 | create mode 100644 docs/system/arm/highbank.rst | ||
14 | 13 | ||
15 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | 14 | diff --git a/docs/system/arm/highbank.rst b/docs/system/arm/highbank.rst |
15 | new file mode 100644 | ||
16 | index XXXXXXX..XXXXXXX | ||
17 | --- /dev/null | ||
18 | +++ b/docs/system/arm/highbank.rst | ||
19 | @@ -XXX,XX +XXX,XX @@ | ||
20 | +Calxeda Highbank and Midway (``highbank``, ``midway``) | ||
21 | +====================================================== | ||
22 | + | ||
23 | +``highbank`` is a model of the Calxeda Highbank (ECX-1000) system, | ||
24 | +which has four Cortex-A9 cores. | ||
25 | + | ||
26 | +``midway`` is a model of the Calxeda Midway (ECX-2000) system, | ||
27 | +which has four Cortex-A15 cores. | ||
28 | + | ||
29 | +Emulated devices: | ||
30 | + | ||
31 | +- L2x0 cache controller | ||
32 | +- SP804 dual timer | ||
33 | +- PL011 UART | ||
34 | +- PL061 GPIOs | ||
35 | +- PL031 RTC | ||
36 | +- PL022 synchronous serial port controller | ||
37 | +- AHCI | ||
38 | +- XGMAC ethernet controllers | ||
39 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
16 | index XXXXXXX..XXXXXXX 100644 | 40 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper-a64.c | 41 | --- a/docs/system/target-arm.rst |
18 | +++ b/target/arm/helper-a64.c | 42 | +++ b/docs/system/target-arm.rst |
19 | @@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) | 43 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
20 | return nan; | 44 | arm/digic |
21 | } | 45 | arm/cubieboard |
22 | 46 | arm/emcraft-sf2 | |
23 | + a = float16_squash_input_denormal(a, fpst); | 47 | + arm/highbank |
24 | + | 48 | arm/musicpal |
25 | val16 = float16_val(a); | 49 | arm/gumstix |
26 | sbit = 0x8000 & val16; | 50 | arm/nrf |
27 | exp = extract32(val16, 10, 5); | 51 | diff --git a/MAINTAINERS b/MAINTAINERS |
28 | @@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) | 52 | index XXXXXXX..XXXXXXX 100644 |
29 | return nan; | 53 | --- a/MAINTAINERS |
30 | } | 54 | +++ b/MAINTAINERS |
31 | 55 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | |
32 | + a = float32_squash_input_denormal(a, fpst); | 56 | S: Odd Fixes |
33 | + | 57 | F: hw/arm/highbank.c |
34 | val32 = float32_val(a); | 58 | F: hw/net/xgmac.c |
35 | sbit = 0x80000000ULL & val32; | 59 | +F: docs/system/arm/highbank.rst |
36 | exp = extract32(val32, 23, 8); | 60 | |
37 | @@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) | 61 | Canon DIGIC |
38 | return nan; | 62 | M: Antony Pavlov <antonynpavlov@gmail.com> |
39 | } | ||
40 | |||
41 | + a = float64_squash_input_denormal(a, fpst); | ||
42 | + | ||
43 | val64 = float64_val(a); | ||
44 | sbit = 0x8000000000000000ULL & val64; | ||
45 | exp = extract64(float64_val(a), 52, 11); | ||
46 | -- | 63 | -- |
47 | 2.17.1 | 64 | 2.20.1 |
48 | 65 | ||
49 | 66 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Jan Kiszka <jan.kiszka@siemens.com> | ||
2 | 1 | ||
3 | There was a nasty flip in identifying which register group an access is | ||
4 | targeting. The issue caused spuriously raised priorities of the guest | ||
5 | when handing CPUs over in the Jailhouse hypervisor. | ||
6 | |||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> | ||
9 | Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | hw/intc/arm_gicv3_cpuif.c | 12 ++++++------ | ||
14 | 1 file changed, 6 insertions(+), 6 deletions(-) | ||
15 | |||
16 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
19 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
21 | { | ||
22 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
23 | int regno = ri->opc2 & 3; | ||
24 | - int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; | ||
25 | + int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; | ||
26 | uint64_t value = cs->ich_apr[grp][regno]; | ||
27 | |||
28 | trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | ||
29 | @@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
30 | { | ||
31 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
32 | int regno = ri->opc2 & 3; | ||
33 | - int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; | ||
34 | + int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; | ||
35 | |||
36 | trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
39 | uint64_t value; | ||
40 | |||
41 | int regno = ri->opc2 & 3; | ||
42 | - int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1; | ||
43 | + int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; | ||
44 | |||
45 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { | ||
46 | return icv_ap_read(env, ri); | ||
47 | @@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
48 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
49 | |||
50 | int regno = ri->opc2 & 3; | ||
51 | - int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1; | ||
52 | + int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; | ||
53 | |||
54 | if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) { | ||
55 | icv_ap_write(env, ri, value); | ||
56 | @@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) | ||
57 | { | ||
58 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
59 | int regno = ri->opc2 & 3; | ||
60 | - int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; | ||
61 | + int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; | ||
62 | uint64_t value; | ||
63 | |||
64 | value = cs->ich_apr[grp][regno]; | ||
65 | @@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
66 | { | ||
67 | GICv3CPUState *cs = icc_cs_from_env(env); | ||
68 | int regno = ri->opc2 & 3; | ||
69 | - int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS; | ||
70 | + int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; | ||
71 | |||
72 | trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); | ||
73 | |||
74 | -- | ||
75 | 2.17.1 | ||
76 | |||
77 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Shannon Zhao <zhaoshenglong@huawei.com> | ||
2 | 1 | ||
3 | It forgot to increase clroffset during the loop. So it only clear the | ||
4 | first 4 bytes. | ||
5 | |||
6 | Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 | ||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> | ||
9 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
10 | Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/intc/arm_gicv3_kvm.c | 1 + | ||
15 | 1 file changed, 1 insertion(+) | ||
16 | |||
17 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/intc/arm_gicv3_kvm.c | ||
20 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset, | ||
22 | if (clroffset != 0) { | ||
23 | reg = 0; | ||
24 | kvm_gicd_access(s, clroffset, ®, true); | ||
25 | + clroffset += 4; | ||
26 | } | ||
27 | reg = *gic_bmp_ptr32(bmp, irq); | ||
28 | kvm_gicd_access(s, offset, ®, true); | ||
29 | -- | ||
30 | 2.17.1 | ||
31 | |||
32 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Igor Mammedov <imammedo@redhat.com> | ||
2 | 1 | ||
3 | When QEMU is started with following CLI | ||
4 | -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd | ||
5 | it crashes with abort at | ||
6 | accel/kvm/kvm-all.c:2164: | ||
7 | KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument | ||
8 | |||
9 | Which is caused by implicit dependency of kvm_arm_gicv3_reset() on | ||
10 | arm_gicv3_icc_reset() where the later is called by CPU reset | ||
11 | reset callback. | ||
12 | |||
13 | However commit: | ||
14 | 3b77f6c arm/boot: split load_dtb() from arm_load_kernel() | ||
15 | broke CPU reset callback registration in case | ||
16 | |||
17 | arm_load_kernel() | ||
18 | ... | ||
19 | if (!info->kernel_filename || info->firmware_loaded) | ||
20 | |||
21 | branch is taken, i.e. it's sufficient to provide a firmware | ||
22 | or do not provide kernel on CLI to skip cpu reset callback | ||
23 | registration, where before offending commit the callback | ||
24 | has been registered unconditionally. | ||
25 | |||
26 | Fix it by registering the callback right at the beginning of | ||
27 | arm_load_kernel() unconditionally instead of doing it at the end. | ||
28 | |||
29 | NOTE: | ||
30 | we probably should eliminate that dependency anyways as well as | ||
31 | separate arch CPU reset parts from arm_load_kernel() into CPU | ||
32 | itself, but that refactoring that I probably would have to do | ||
33 | anyways later for CPU hotplug to work. | ||
34 | |||
35 | Reported-by: Auger Eric <eric.auger@redhat.com> | ||
36 | Signed-off-by: Igor Mammedov <imammedo@redhat.com> | ||
37 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
38 | Tested-by: Eric Auger <eric.auger@redhat.com> | ||
39 | Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com | ||
40 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
41 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
42 | --- | ||
43 | hw/arm/boot.c | 18 +++++++++--------- | ||
44 | 1 file changed, 9 insertions(+), 9 deletions(-) | ||
45 | |||
46 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/boot.c | ||
49 | +++ b/hw/arm/boot.c | ||
50 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
51 | static const ARMInsnFixup *primary_loader; | ||
52 | AddressSpace *as = arm_boot_address_space(cpu, info); | ||
53 | |||
54 | + /* CPU objects (unlike devices) are not automatically reset on system | ||
55 | + * reset, so we must always register a handler to do so. If we're | ||
56 | + * actually loading a kernel, the handler is also responsible for | ||
57 | + * arranging that we start it correctly. | ||
58 | + */ | ||
59 | + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | ||
60 | + qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); | ||
61 | + } | ||
62 | + | ||
63 | /* The board code is not supposed to set secure_board_setup unless | ||
64 | * running its code in secure mode is actually possible, and KVM | ||
65 | * doesn't support secure. | ||
66 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
67 | ARM_CPU(cs)->env.boot_info = info; | ||
68 | } | ||
69 | |||
70 | - /* CPU objects (unlike devices) are not automatically reset on system | ||
71 | - * reset, so we must always register a handler to do so. If we're | ||
72 | - * actually loading a kernel, the handler is also responsible for | ||
73 | - * arranging that we start it correctly. | ||
74 | - */ | ||
75 | - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | ||
76 | - qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); | ||
77 | - } | ||
78 | - | ||
79 | if (!info->skip_dtb_autoload && have_dtb(info)) { | ||
80 | if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { | ||
81 | exit(1); | ||
82 | -- | ||
83 | 2.17.1 | ||
84 | |||
85 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Paolo Bonzini <pbonzini@redhat.com> | ||
2 | 1 | ||
3 | cpregs_keys is an uint32_t* so the allocation should use uint32_t. | ||
4 | g_new is even better because it is type-safe. | ||
5 | |||
6 | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/gdbstub.c | 3 +-- | ||
12 | 1 file changed, 1 insertion(+), 2 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/gdbstub.c | ||
17 | +++ b/target/arm/gdbstub.c | ||
18 | @@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs) | ||
19 | RegisterSysregXmlParam param = {cs, s}; | ||
20 | |||
21 | cpu->dyn_xml.num_cpregs = 0; | ||
22 | - cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) * | ||
23 | - g_hash_table_size(cpu->cp_regs)); | ||
24 | + cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs)); | ||
25 | g_string_printf(s, "<?xml version=\"1.0\"?>"); | ||
26 | g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); | ||
27 | g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">"); | ||
28 | -- | ||
29 | 2.17.1 | ||
30 | |||
31 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
2 | 1 | ||
3 | Coverity found that the string return by 'object_get_canonical_path' was not | ||
4 | being freed at two locations in the model (CID 1391294 and CID 1391293) and | ||
5 | also that a memset was being called with a value greater than the max of a byte | ||
6 | on the second argument (CID 1391286). This patch corrects this by adding the | ||
7 | freeing of the strings and also changing to memset to zero instead on | ||
8 | descriptor unaligned errors. | ||
9 | |||
10 | Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> | ||
11 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/dma/xlnx-zdma.c | 10 +++++++--- | ||
18 | 1 file changed, 7 insertions(+), 3 deletions(-) | ||
19 | |||
20 | diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/dma/xlnx-zdma.c | ||
23 | +++ b/hw/dma/xlnx-zdma.c | ||
24 | @@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf) | ||
25 | qemu_log_mask(LOG_GUEST_ERROR, | ||
26 | "zdma: unaligned descriptor at %" PRIx64, | ||
27 | addr); | ||
28 | - memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr)); | ||
29 | + memset(buf, 0x0, sizeof(XlnxZDMADescr)); | ||
30 | s->error = true; | ||
31 | return false; | ||
32 | } | ||
33 | @@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size) | ||
34 | RegisterInfo *r = &s->regs_info[addr / 4]; | ||
35 | |||
36 | if (!r->data) { | ||
37 | + gchar *path = object_get_canonical_path(OBJECT(s)); | ||
38 | qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n", | ||
39 | - object_get_canonical_path(OBJECT(s)), | ||
40 | + path, | ||
41 | addr); | ||
42 | + g_free(path); | ||
43 | ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); | ||
44 | zdma_ch_imr_update_irq(s); | ||
45 | return 0; | ||
46 | @@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value, | ||
47 | RegisterInfo *r = &s->regs_info[addr / 4]; | ||
48 | |||
49 | if (!r->data) { | ||
50 | + gchar *path = object_get_canonical_path(OBJECT(s)); | ||
51 | qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n", | ||
52 | - object_get_canonical_path(OBJECT(s)), | ||
53 | + path, | ||
54 | addr, value); | ||
55 | + g_free(path); | ||
56 | ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true); | ||
57 | zdma_ch_imr_update_irq(s); | ||
58 | return; | ||
59 | -- | ||
60 | 2.17.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In commit f0aff255700 we made cpacr_write() enforce that some CPACR | ||
2 | bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately | ||
3 | we forgot to also update the register's reset value. The effect | ||
4 | was that (a) a guest that read CPACR on reset would not see ones in | ||
5 | the RAO bits, and (b) if you did a migration before the guest did | ||
6 | a write to the CPACR then the migration would fail because the | ||
7 | destination would enforce the RAO bits and then complain that they | ||
8 | didn't match the zero value from the source. | ||
9 | 1 | ||
10 | Implement reset for the CPACR using a custom reset function | ||
11 | that just calls cpacr_write(), to avoid having to duplicate | ||
12 | the logic for which bits are RAO. | ||
13 | |||
14 | This bug would affect migration for TCG CPUs which are ARMv7 | ||
15 | with VFP but without one of Neon or VFPv3. | ||
16 | |||
17 | Reported-by: Cédric Le Goater <clg@kaod.org> | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Tested-by: Cédric Le Goater <clg@kaod.org> | ||
20 | Message-id: 20180522173713.26282-1-peter.maydell@linaro.org | ||
21 | --- | ||
22 | target/arm/helper.c | 10 +++++++++- | ||
23 | 1 file changed, 9 insertions(+), 1 deletion(-) | ||
24 | |||
25 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/helper.c | ||
28 | +++ b/target/arm/helper.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
30 | env->cp15.cpacr_el1 = value; | ||
31 | } | ||
32 | |||
33 | +static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) | ||
34 | +{ | ||
35 | + /* Call cpacr_write() so that we reset with the correct RAO bits set | ||
36 | + * for our CPU features. | ||
37 | + */ | ||
38 | + cpacr_write(env, ri, 0); | ||
39 | +} | ||
40 | + | ||
41 | static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
42 | bool isread) | ||
43 | { | ||
44 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = { | ||
45 | { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, | ||
46 | .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, | ||
47 | .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), | ||
48 | - .resetvalue = 0, .writefn = cpacr_write }, | ||
49 | + .resetfn = cpacr_reset, .writefn = cpacr_write }, | ||
50 | REGINFO_SENTINEL | ||
51 | }; | ||
52 | |||
53 | -- | ||
54 | 2.17.1 | ||
55 | |||
56 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | ||
2 | add MemTxAttrs as an argument to address_space_translate() | ||
3 | and address_space_translate_cached(). Callers either have an | ||
4 | attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180521140402.23318-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/exec/memory.h | 4 +++- | ||
12 | accel/tcg/translate-all.c | 2 +- | ||
13 | exec.c | 14 +++++++++----- | ||
14 | hw/vfio/common.c | 3 ++- | ||
15 | memory_ldst.inc.c | 18 +++++++++--------- | ||
16 | target/riscv/helper.c | 2 +- | ||
17 | 6 files changed, 25 insertions(+), 18 deletions(-) | ||
18 | |||
19 | diff --git a/include/exec/memory.h b/include/exec/memory.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/include/exec/memory.h | ||
22 | +++ b/include/exec/memory.h | ||
23 | @@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | ||
24 | * #MemoryRegion. | ||
25 | * @len: pointer to length | ||
26 | * @is_write: indicates the transfer direction | ||
27 | + * @attrs: memory attributes | ||
28 | */ | ||
29 | MemoryRegion *flatview_translate(FlatView *fv, | ||
30 | hwaddr addr, hwaddr *xlat, | ||
31 | @@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, | ||
32 | |||
33 | static inline MemoryRegion *address_space_translate(AddressSpace *as, | ||
34 | hwaddr addr, hwaddr *xlat, | ||
35 | - hwaddr *len, bool is_write) | ||
36 | + hwaddr *len, bool is_write, | ||
37 | + MemTxAttrs attrs) | ||
38 | { | ||
39 | return flatview_translate(address_space_to_flatview(as), | ||
40 | addr, xlat, len, is_write); | ||
41 | diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/accel/tcg/translate-all.c | ||
44 | +++ b/accel/tcg/translate-all.c | ||
45 | @@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) | ||
46 | hwaddr l = 1; | ||
47 | |||
48 | rcu_read_lock(); | ||
49 | - mr = address_space_translate(as, addr, &addr, &l, false); | ||
50 | + mr = address_space_translate(as, addr, &addr, &l, false, attrs); | ||
51 | if (!(memory_region_is_ram(mr) | ||
52 | || memory_region_is_romd(mr))) { | ||
53 | rcu_read_unlock(); | ||
54 | diff --git a/exec.c b/exec.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/exec.c | ||
57 | +++ b/exec.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, | ||
59 | rcu_read_lock(); | ||
60 | while (len > 0) { | ||
61 | l = len; | ||
62 | - mr = address_space_translate(as, addr, &addr1, &l, true); | ||
63 | + mr = address_space_translate(as, addr, &addr1, &l, true, | ||
64 | + MEMTXATTRS_UNSPECIFIED); | ||
65 | |||
66 | if (!(memory_region_is_ram(mr) || | ||
67 | memory_region_is_romd(mr))) { | ||
68 | @@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache) | ||
69 | */ | ||
70 | static inline MemoryRegion *address_space_translate_cached( | ||
71 | MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat, | ||
72 | - hwaddr *plen, bool is_write) | ||
73 | + hwaddr *plen, bool is_write, MemTxAttrs attrs) | ||
74 | { | ||
75 | MemoryRegionSection section; | ||
76 | MemoryRegion *mr; | ||
77 | @@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr, | ||
78 | MemoryRegion *mr; | ||
79 | |||
80 | l = len; | ||
81 | - mr = address_space_translate_cached(cache, addr, &addr1, &l, false); | ||
82 | + mr = address_space_translate_cached(cache, addr, &addr1, &l, false, | ||
83 | + MEMTXATTRS_UNSPECIFIED); | ||
84 | flatview_read_continue(cache->fv, | ||
85 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | ||
86 | addr1, l, mr); | ||
87 | @@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, | ||
88 | MemoryRegion *mr; | ||
89 | |||
90 | l = len; | ||
91 | - mr = address_space_translate_cached(cache, addr, &addr1, &l, true); | ||
92 | + mr = address_space_translate_cached(cache, addr, &addr1, &l, true, | ||
93 | + MEMTXATTRS_UNSPECIFIED); | ||
94 | flatview_write_continue(cache->fv, | ||
95 | addr, MEMTXATTRS_UNSPECIFIED, buf, len, | ||
96 | addr1, l, mr); | ||
97 | @@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr) | ||
98 | |||
99 | rcu_read_lock(); | ||
100 | mr = address_space_translate(&address_space_memory, | ||
101 | - phys_addr, &phys_addr, &l, false); | ||
102 | + phys_addr, &phys_addr, &l, false, | ||
103 | + MEMTXATTRS_UNSPECIFIED); | ||
104 | |||
105 | res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); | ||
106 | rcu_read_unlock(); | ||
107 | diff --git a/hw/vfio/common.c b/hw/vfio/common.c | ||
108 | index XXXXXXX..XXXXXXX 100644 | ||
109 | --- a/hw/vfio/common.c | ||
110 | +++ b/hw/vfio/common.c | ||
111 | @@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr, | ||
112 | */ | ||
113 | mr = address_space_translate(&address_space_memory, | ||
114 | iotlb->translated_addr, | ||
115 | - &xlat, &len, writable); | ||
116 | + &xlat, &len, writable, | ||
117 | + MEMTXATTRS_UNSPECIFIED); | ||
118 | if (!memory_region_is_ram(mr)) { | ||
119 | error_report("iommu map to non memory area %"HWADDR_PRIx"", | ||
120 | xlat); | ||
121 | diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/memory_ldst.inc.c | ||
124 | +++ b/memory_ldst.inc.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, | ||
126 | bool release_lock = false; | ||
127 | |||
128 | RCU_READ_LOCK(); | ||
129 | - mr = TRANSLATE(addr, &addr1, &l, false); | ||
130 | + mr = TRANSLATE(addr, &addr1, &l, false, attrs); | ||
131 | if (l < 4 || !IS_DIRECT(mr, false)) { | ||
132 | release_lock |= prepare_mmio_access(mr); | ||
133 | |||
134 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, | ||
135 | bool release_lock = false; | ||
136 | |||
137 | RCU_READ_LOCK(); | ||
138 | - mr = TRANSLATE(addr, &addr1, &l, false); | ||
139 | + mr = TRANSLATE(addr, &addr1, &l, false, attrs); | ||
140 | if (l < 8 || !IS_DIRECT(mr, false)) { | ||
141 | release_lock |= prepare_mmio_access(mr); | ||
142 | |||
143 | @@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, | ||
144 | bool release_lock = false; | ||
145 | |||
146 | RCU_READ_LOCK(); | ||
147 | - mr = TRANSLATE(addr, &addr1, &l, false); | ||
148 | + mr = TRANSLATE(addr, &addr1, &l, false, attrs); | ||
149 | if (!IS_DIRECT(mr, false)) { | ||
150 | release_lock |= prepare_mmio_access(mr); | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL, | ||
153 | bool release_lock = false; | ||
154 | |||
155 | RCU_READ_LOCK(); | ||
156 | - mr = TRANSLATE(addr, &addr1, &l, false); | ||
157 | + mr = TRANSLATE(addr, &addr1, &l, false, attrs); | ||
158 | if (l < 2 || !IS_DIRECT(mr, false)) { | ||
159 | release_lock |= prepare_mmio_access(mr); | ||
160 | |||
161 | @@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, | ||
162 | bool release_lock = false; | ||
163 | |||
164 | RCU_READ_LOCK(); | ||
165 | - mr = TRANSLATE(addr, &addr1, &l, true); | ||
166 | + mr = TRANSLATE(addr, &addr1, &l, true, attrs); | ||
167 | if (l < 4 || !IS_DIRECT(mr, true)) { | ||
168 | release_lock |= prepare_mmio_access(mr); | ||
169 | |||
170 | @@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, | ||
171 | bool release_lock = false; | ||
172 | |||
173 | RCU_READ_LOCK(); | ||
174 | - mr = TRANSLATE(addr, &addr1, &l, true); | ||
175 | + mr = TRANSLATE(addr, &addr1, &l, true, attrs); | ||
176 | if (l < 4 || !IS_DIRECT(mr, true)) { | ||
177 | release_lock |= prepare_mmio_access(mr); | ||
178 | |||
179 | @@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, | ||
180 | bool release_lock = false; | ||
181 | |||
182 | RCU_READ_LOCK(); | ||
183 | - mr = TRANSLATE(addr, &addr1, &l, true); | ||
184 | + mr = TRANSLATE(addr, &addr1, &l, true, attrs); | ||
185 | if (!IS_DIRECT(mr, true)) { | ||
186 | release_lock |= prepare_mmio_access(mr); | ||
187 | r = memory_region_dispatch_write(mr, addr1, val, 1, attrs); | ||
188 | @@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL, | ||
189 | bool release_lock = false; | ||
190 | |||
191 | RCU_READ_LOCK(); | ||
192 | - mr = TRANSLATE(addr, &addr1, &l, true); | ||
193 | + mr = TRANSLATE(addr, &addr1, &l, true, attrs); | ||
194 | if (l < 2 || !IS_DIRECT(mr, true)) { | ||
195 | release_lock |= prepare_mmio_access(mr); | ||
196 | |||
197 | @@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, | ||
198 | bool release_lock = false; | ||
199 | |||
200 | RCU_READ_LOCK(); | ||
201 | - mr = TRANSLATE(addr, &addr1, &l, true); | ||
202 | + mr = TRANSLATE(addr, &addr1, &l, true, attrs); | ||
203 | if (l < 8 || !IS_DIRECT(mr, true)) { | ||
204 | release_lock |= prepare_mmio_access(mr); | ||
205 | |||
206 | diff --git a/target/riscv/helper.c b/target/riscv/helper.c | ||
207 | index XXXXXXX..XXXXXXX 100644 | ||
208 | --- a/target/riscv/helper.c | ||
209 | +++ b/target/riscv/helper.c | ||
210 | @@ -XXX,XX +XXX,XX @@ restart: | ||
211 | MemoryRegion *mr; | ||
212 | hwaddr l = sizeof(target_ulong), addr1; | ||
213 | mr = address_space_translate(cs->as, pte_addr, | ||
214 | - &addr1, &l, false); | ||
215 | + &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); | ||
216 | if (memory_access_is_direct(mr, true)) { | ||
217 | target_ulong *pte_pa = | ||
218 | qemu_map_ram_ptr(mr->ram_block, addr1); | ||
219 | -- | ||
220 | 2.17.1 | ||
221 | |||
222 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | ||
2 | add MemTxAttrs as an argument to address_space_map(). | ||
3 | Its callers either have an attrs value to hand, or don't care | ||
4 | and can use MEMTXATTRS_UNSPECIFIED. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180521140402.23318-5-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/exec/memory.h | 3 ++- | ||
12 | include/sysemu/dma.h | 3 ++- | ||
13 | exec.c | 6 ++++-- | ||
14 | target/ppc/mmu-hash64.c | 3 ++- | ||
15 | 4 files changed, 10 insertions(+), 5 deletions(-) | ||
16 | |||
17 | diff --git a/include/exec/memory.h b/include/exec/memory.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/include/exec/memory.h | ||
20 | +++ b/include/exec/memory.h | ||
21 | @@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_ | ||
22 | * @addr: address within that address space | ||
23 | * @plen: pointer to length of buffer; updated on return | ||
24 | * @is_write: indicates the transfer direction | ||
25 | + * @attrs: memory attributes | ||
26 | */ | ||
27 | void *address_space_map(AddressSpace *as, hwaddr addr, | ||
28 | - hwaddr *plen, bool is_write); | ||
29 | + hwaddr *plen, bool is_write, MemTxAttrs attrs); | ||
30 | |||
31 | /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map() | ||
32 | * | ||
33 | diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/include/sysemu/dma.h | ||
36 | +++ b/include/sysemu/dma.h | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as, | ||
38 | hwaddr xlen = *len; | ||
39 | void *p; | ||
40 | |||
41 | - p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE); | ||
42 | + p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE, | ||
43 | + MEMTXATTRS_UNSPECIFIED); | ||
44 | *len = xlen; | ||
45 | return p; | ||
46 | } | ||
47 | diff --git a/exec.c b/exec.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/exec.c | ||
50 | +++ b/exec.c | ||
51 | @@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr, | ||
52 | void *address_space_map(AddressSpace *as, | ||
53 | hwaddr addr, | ||
54 | hwaddr *plen, | ||
55 | - bool is_write) | ||
56 | + bool is_write, | ||
57 | + MemTxAttrs attrs) | ||
58 | { | ||
59 | hwaddr len = *plen; | ||
60 | hwaddr l, xlat; | ||
61 | @@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr, | ||
62 | hwaddr *plen, | ||
63 | int is_write) | ||
64 | { | ||
65 | - return address_space_map(&address_space_memory, addr, plen, is_write); | ||
66 | + return address_space_map(&address_space_memory, addr, plen, is_write, | ||
67 | + MEMTXATTRS_UNSPECIFIED); | ||
68 | } | ||
69 | |||
70 | void cpu_physical_memory_unmap(void *buffer, hwaddr len, | ||
71 | diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/ppc/mmu-hash64.c | ||
74 | +++ b/target/ppc/mmu-hash64.c | ||
75 | @@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, | ||
76 | return NULL; | ||
77 | } | ||
78 | |||
79 | - hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false); | ||
80 | + hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false, | ||
81 | + MEMTXATTRS_UNSPECIFIED); | ||
82 | if (plen < (n * HASH_PTE_SIZE_64)) { | ||
83 | hw_error("%s: Unable to map all requested HPTEs\n", __func__); | ||
84 | } | ||
85 | -- | ||
86 | 2.17.1 | ||
87 | |||
88 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | ||
2 | add MemTxAttrs as an argument to address_space_access_valid(). | ||
3 | Its callers either have an attrs value to hand, or don't care | ||
4 | and can use MEMTXATTRS_UNSPECIFIED. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180521140402.23318-6-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/exec/memory.h | 4 +++- | ||
12 | include/sysemu/dma.h | 3 ++- | ||
13 | exec.c | 3 ++- | ||
14 | target/s390x/diag.c | 6 ++++-- | ||
15 | target/s390x/excp_helper.c | 3 ++- | ||
16 | target/s390x/mmu_helper.c | 3 ++- | ||
17 | target/s390x/sigp.c | 3 ++- | ||
18 | 7 files changed, 17 insertions(+), 8 deletions(-) | ||
19 | |||
20 | diff --git a/include/exec/memory.h b/include/exec/memory.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/exec/memory.h | ||
23 | +++ b/include/exec/memory.h | ||
24 | @@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as, | ||
25 | * @addr: address within that address space | ||
26 | * @len: length of the area to be checked | ||
27 | * @is_write: indicates the transfer direction | ||
28 | + * @attrs: memory attributes | ||
29 | */ | ||
30 | -bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write); | ||
31 | +bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, | ||
32 | + bool is_write, MemTxAttrs attrs); | ||
33 | |||
34 | /* address_space_map: map a physical memory region into a host virtual address | ||
35 | * | ||
36 | diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/include/sysemu/dma.h | ||
39 | +++ b/include/sysemu/dma.h | ||
40 | @@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as, | ||
41 | DMADirection dir) | ||
42 | { | ||
43 | return address_space_access_valid(as, addr, len, | ||
44 | - dir == DMA_DIRECTION_FROM_DEVICE); | ||
45 | + dir == DMA_DIRECTION_FROM_DEVICE, | ||
46 | + MEMTXATTRS_UNSPECIFIED); | ||
47 | } | ||
48 | |||
49 | static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, | ||
50 | diff --git a/exec.c b/exec.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | ||
52 | --- a/exec.c | ||
53 | +++ b/exec.c | ||
54 | @@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | ||
55 | } | ||
56 | |||
57 | bool address_space_access_valid(AddressSpace *as, hwaddr addr, | ||
58 | - int len, bool is_write) | ||
59 | + int len, bool is_write, | ||
60 | + MemTxAttrs attrs) | ||
61 | { | ||
62 | FlatView *fv; | ||
63 | bool result; | ||
64 | diff --git a/target/s390x/diag.c b/target/s390x/diag.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/s390x/diag.c | ||
67 | +++ b/target/s390x/diag.c | ||
68 | @@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) | ||
69 | return; | ||
70 | } | ||
71 | if (!address_space_access_valid(&address_space_memory, addr, | ||
72 | - sizeof(IplParameterBlock), false)) { | ||
73 | + sizeof(IplParameterBlock), false, | ||
74 | + MEMTXATTRS_UNSPECIFIED)) { | ||
75 | s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); | ||
76 | return; | ||
77 | } | ||
78 | @@ -XXX,XX +XXX,XX @@ out: | ||
79 | return; | ||
80 | } | ||
81 | if (!address_space_access_valid(&address_space_memory, addr, | ||
82 | - sizeof(IplParameterBlock), true)) { | ||
83 | + sizeof(IplParameterBlock), true, | ||
84 | + MEMTXATTRS_UNSPECIFIED)) { | ||
85 | s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); | ||
86 | return; | ||
87 | } | ||
88 | diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/s390x/excp_helper.c | ||
91 | +++ b/target/s390x/excp_helper.c | ||
92 | @@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, | ||
93 | |||
94 | /* check out of RAM access */ | ||
95 | if (!address_space_access_valid(&address_space_memory, raddr, | ||
96 | - TARGET_PAGE_SIZE, rw)) { | ||
97 | + TARGET_PAGE_SIZE, rw, | ||
98 | + MEMTXATTRS_UNSPECIFIED)) { | ||
99 | DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, | ||
100 | (uint64_t)raddr, (uint64_t)ram_size); | ||
101 | trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); | ||
102 | diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/target/s390x/mmu_helper.c | ||
105 | +++ b/target/s390x/mmu_helper.c | ||
106 | @@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages, | ||
107 | return ret; | ||
108 | } | ||
109 | if (!address_space_access_valid(&address_space_memory, pages[i], | ||
110 | - TARGET_PAGE_SIZE, is_write)) { | ||
111 | + TARGET_PAGE_SIZE, is_write, | ||
112 | + MEMTXATTRS_UNSPECIFIED)) { | ||
113 | trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0); | ||
114 | return -EFAULT; | ||
115 | } | ||
116 | diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c | ||
117 | index XXXXXXX..XXXXXXX 100644 | ||
118 | --- a/target/s390x/sigp.c | ||
119 | +++ b/target/s390x/sigp.c | ||
120 | @@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg) | ||
121 | cpu_synchronize_state(cs); | ||
122 | |||
123 | if (!address_space_access_valid(&address_space_memory, addr, | ||
124 | - sizeof(struct LowCore), false)) { | ||
125 | + sizeof(struct LowCore), false, | ||
126 | + MEMTXATTRS_UNSPECIFIED)) { | ||
127 | set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER); | ||
128 | return; | ||
129 | } | ||
130 | -- | ||
131 | 2.17.1 | ||
132 | |||
133 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | ||
2 | add MemTxAttrs as an argument to flatview_extend_translation(). | ||
3 | Its callers either have an attrs value to hand, or don't care | ||
4 | and can use MEMTXATTRS_UNSPECIFIED. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20180521140402.23318-7-peter.maydell@linaro.org | ||
10 | --- | ||
11 | exec.c | 15 ++++++++++----- | ||
12 | 1 file changed, 10 insertions(+), 5 deletions(-) | ||
13 | |||
14 | diff --git a/exec.c b/exec.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/exec.c | ||
17 | +++ b/exec.c | ||
18 | @@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, | ||
19 | |||
20 | static hwaddr | ||
21 | flatview_extend_translation(FlatView *fv, hwaddr addr, | ||
22 | - hwaddr target_len, | ||
23 | - MemoryRegion *mr, hwaddr base, hwaddr len, | ||
24 | - bool is_write) | ||
25 | + hwaddr target_len, | ||
26 | + MemoryRegion *mr, hwaddr base, hwaddr len, | ||
27 | + bool is_write, MemTxAttrs attrs) | ||
28 | { | ||
29 | hwaddr done = 0; | ||
30 | hwaddr xlat; | ||
31 | @@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as, | ||
32 | |||
33 | memory_region_ref(mr); | ||
34 | *plen = flatview_extend_translation(fv, addr, len, mr, xlat, | ||
35 | - l, is_write); | ||
36 | + l, is_write, attrs); | ||
37 | ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); | ||
38 | rcu_read_unlock(); | ||
39 | |||
40 | @@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache, | ||
41 | mr = cache->mrs.mr; | ||
42 | memory_region_ref(mr); | ||
43 | if (memory_access_is_direct(mr, is_write)) { | ||
44 | + /* We don't care about the memory attributes here as we're only | ||
45 | + * doing this if we found actual RAM, which behaves the same | ||
46 | + * regardless of attributes; so UNSPECIFIED is fine. | ||
47 | + */ | ||
48 | l = flatview_extend_translation(cache->fv, addr, len, mr, | ||
49 | - cache->xlat, l, is_write); | ||
50 | + cache->xlat, l, is_write, | ||
51 | + MEMTXATTRS_UNSPECIFIED); | ||
52 | cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true); | ||
53 | } else { | ||
54 | cache->ptr = NULL; | ||
55 | -- | ||
56 | 2.17.1 | ||
57 | |||
58 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | ||
2 | add MemTxAttrs as an argument to memory_region_access_valid(). | ||
3 | Its callers either have an attrs value to hand, or don't care | ||
4 | and can use MEMTXATTRS_UNSPECIFIED. | ||
5 | 1 | ||
6 | The callsite in flatview_access_valid() is part of a recursive | ||
7 | loop flatview_access_valid() -> memory_region_access_valid() -> | ||
8 | subpage_accepts() -> flatview_access_valid(); we make it pass | ||
9 | MEMTXATTRS_UNSPECIFIED for now, until the next several commits | ||
10 | have plumbed an attrs parameter through the rest of the loop | ||
11 | and we can add an attrs parameter to flatview_access_valid(). | ||
12 | |||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
15 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
16 | Message-id: 20180521140402.23318-8-peter.maydell@linaro.org | ||
17 | --- | ||
18 | include/exec/memory-internal.h | 3 ++- | ||
19 | exec.c | 4 +++- | ||
20 | hw/s390x/s390-pci-inst.c | 3 ++- | ||
21 | memory.c | 7 ++++--- | ||
22 | 4 files changed, 11 insertions(+), 6 deletions(-) | ||
23 | |||
24 | diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/include/exec/memory-internal.h | ||
27 | +++ b/include/exec/memory-internal.h | ||
28 | @@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view); | ||
29 | extern const MemoryRegionOps unassigned_mem_ops; | ||
30 | |||
31 | bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr, | ||
32 | - unsigned size, bool is_write); | ||
33 | + unsigned size, bool is_write, | ||
34 | + MemTxAttrs attrs); | ||
35 | |||
36 | void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section); | ||
37 | AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv); | ||
38 | diff --git a/exec.c b/exec.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/exec.c | ||
41 | +++ b/exec.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | ||
43 | mr = flatview_translate(fv, addr, &xlat, &l, is_write); | ||
44 | if (!memory_access_is_direct(mr, is_write)) { | ||
45 | l = memory_access_size(mr, l, addr); | ||
46 | - if (!memory_region_access_valid(mr, xlat, l, is_write)) { | ||
47 | + /* When our callers all have attrs we'll pass them through here */ | ||
48 | + if (!memory_region_access_valid(mr, xlat, l, is_write, | ||
49 | + MEMTXATTRS_UNSPECIFIED)) { | ||
50 | return false; | ||
51 | } | ||
52 | } | ||
53 | diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/hw/s390x/s390-pci-inst.c | ||
56 | +++ b/hw/s390x/s390-pci-inst.c | ||
57 | @@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, | ||
58 | mr = s390_get_subregion(mr, offset, len); | ||
59 | offset -= mr->addr; | ||
60 | |||
61 | - if (!memory_region_access_valid(mr, offset, len, true)) { | ||
62 | + if (!memory_region_access_valid(mr, offset, len, true, | ||
63 | + MEMTXATTRS_UNSPECIFIED)) { | ||
64 | s390_program_interrupt(env, PGM_OPERAND, 6, ra); | ||
65 | return 0; | ||
66 | } | ||
67 | diff --git a/memory.c b/memory.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/memory.c | ||
70 | +++ b/memory.c | ||
71 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = { | ||
72 | bool memory_region_access_valid(MemoryRegion *mr, | ||
73 | hwaddr addr, | ||
74 | unsigned size, | ||
75 | - bool is_write) | ||
76 | + bool is_write, | ||
77 | + MemTxAttrs attrs) | ||
78 | { | ||
79 | int access_size_min, access_size_max; | ||
80 | int access_size, i; | ||
81 | @@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr, | ||
82 | { | ||
83 | MemTxResult r; | ||
84 | |||
85 | - if (!memory_region_access_valid(mr, addr, size, false)) { | ||
86 | + if (!memory_region_access_valid(mr, addr, size, false, attrs)) { | ||
87 | *pval = unassigned_mem_read(mr, addr, size); | ||
88 | return MEMTX_DECODE_ERROR; | ||
89 | } | ||
90 | @@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr, | ||
91 | unsigned size, | ||
92 | MemTxAttrs attrs) | ||
93 | { | ||
94 | - if (!memory_region_access_valid(mr, addr, size, true)) { | ||
95 | + if (!memory_region_access_valid(mr, addr, size, true, attrs)) { | ||
96 | unassigned_mem_write(mr, addr, data, size); | ||
97 | return MEMTX_DECODE_ERROR; | ||
98 | } | ||
99 | -- | ||
100 | 2.17.1 | ||
101 | |||
102 | diff view generated by jsdifflib |
1 | As part of plumbing MemTxAttrs down to the IOMMU translate method, | 1 | The Neon and SVE decoders use private 'plus1' functions to implement |
---|---|---|---|
2 | add MemTxAttrs as an argument to flatview_translate(); all its | 2 | "add one" for the !function decoder syntax. We have a generic |
3 | callers now have attrs available. | 3 | "plus_1" function in translate.h, so use that instead. |
4 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20180521140402.23318-11-peter.maydell@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
8 | Message-id: 20210715095341.701-1-peter.maydell@linaro.org | ||
9 | --- | 9 | --- |
10 | include/exec/memory.h | 7 ++++--- | 10 | target/arm/neon-ls.decode | 4 ++-- |
11 | exec.c | 17 +++++++++-------- | 11 | target/arm/neon-shared.decode | 2 +- |
12 | 2 files changed, 13 insertions(+), 11 deletions(-) | 12 | target/arm/sve.decode | 2 +- |
13 | target/arm/translate-neon.c | 5 ----- | ||
14 | target/arm/translate-sve.c | 5 ----- | ||
15 | 5 files changed, 4 insertions(+), 14 deletions(-) | ||
13 | 16 | ||
14 | diff --git a/include/exec/memory.h b/include/exec/memory.h | 17 | diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/exec/memory.h | 19 | --- a/target/arm/neon-ls.decode |
17 | +++ b/include/exec/memory.h | 20 | +++ b/target/arm/neon-ls.decode |
18 | @@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, | 21 | @@ -XXX,XX +XXX,XX @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ |
19 | */ | 22 | vd=%vd_dp |
20 | MemoryRegion *flatview_translate(FlatView *fv, | 23 | |
21 | hwaddr addr, hwaddr *xlat, | 24 | # Neon load/store single structure to one lane |
22 | - hwaddr *len, bool is_write); | 25 | -%imm1_5_p1 5:1 !function=plus1 |
23 | + hwaddr *len, bool is_write, | 26 | -%imm1_6_p1 6:1 !function=plus1 |
24 | + MemTxAttrs attrs); | 27 | +%imm1_5_p1 5:1 !function=plus_1 |
25 | 28 | +%imm1_6_p1 6:1 !function=plus_1 | |
26 | static inline MemoryRegion *address_space_translate(AddressSpace *as, | 29 | |
27 | hwaddr addr, hwaddr *xlat, | 30 | VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ |
28 | @@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as, | 31 | vd=%vd_dp size=0 stride=1 |
29 | MemTxAttrs attrs) | 32 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode |
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/neon-shared.decode | ||
35 | +++ b/target/arm/neon-shared.decode | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | # which is 0 for fp16 and 1 for fp32 into a MO_* constant. | ||
38 | # (Note that this is the reverse of the sense of the 1-bit size | ||
39 | # field in the 3same_fp Neon insns.) | ||
40 | -%vcadd_size 20:1 !function=plus1 | ||
41 | +%vcadd_size 20:1 !function=plus_1 | ||
42 | |||
43 | VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \ | ||
44 | vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%vcadd_size | ||
45 | diff --git a/target/arm/sve.decode b/target/arm/sve.decode | ||
46 | index XXXXXXX..XXXXXXX 100644 | ||
47 | --- a/target/arm/sve.decode | ||
48 | +++ b/target/arm/sve.decode | ||
49 | @@ -XXX,XX +XXX,XX @@ | ||
50 | ########################################################################### | ||
51 | # Named fields. These are primarily for disjoint fields. | ||
52 | |||
53 | -%imm4_16_p1 16:4 !function=plus1 | ||
54 | +%imm4_16_p1 16:4 !function=plus_1 | ||
55 | %imm6_22_5 22:1 5:5 | ||
56 | %imm7_22_16 22:2 16:5 | ||
57 | %imm8_16_10 16:5 10:3 | ||
58 | diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/translate-neon.c | ||
61 | +++ b/target/arm/translate-neon.c | ||
62 | @@ -XXX,XX +XXX,XX @@ | ||
63 | #include "translate.h" | ||
64 | #include "translate-a32.h" | ||
65 | |||
66 | -static inline int plus1(DisasContext *s, int x) | ||
67 | -{ | ||
68 | - return x + 1; | ||
69 | -} | ||
70 | - | ||
71 | static inline int neon_3same_fp_size(DisasContext *s, int x) | ||
30 | { | 72 | { |
31 | return flatview_translate(address_space_to_flatview(as), | 73 | /* Convert 0==fp32, 1==fp16 into a MO_* value */ |
32 | - addr, xlat, len, is_write); | 74 | diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c |
33 | + addr, xlat, len, is_write, attrs); | 75 | index XXXXXXX..XXXXXXX 100644 |
76 | --- a/target/arm/translate-sve.c | ||
77 | +++ b/target/arm/translate-sve.c | ||
78 | @@ -XXX,XX +XXX,XX @@ static int tszimm_shl(DisasContext *s, int x) | ||
79 | return x - (8 << tszimm_esz(s, x)); | ||
34 | } | 80 | } |
35 | 81 | ||
36 | /* address_space_access_valid: check for validity of accessing an address | 82 | -static inline int plus1(DisasContext *s, int x) |
37 | @@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr, | 83 | -{ |
38 | rcu_read_lock(); | 84 | - return x + 1; |
39 | fv = address_space_to_flatview(as); | 85 | -} |
40 | l = len; | 86 | - |
41 | - mr = flatview_translate(fv, addr, &addr1, &l, false); | 87 | /* The SH bit is in bit 8. Extract the low 8 and shift. */ |
42 | + mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); | 88 | static inline int expand_imm_sh8s(DisasContext *s, int x) |
43 | if (len == l && memory_access_is_direct(mr, false)) { | ||
44 | ptr = qemu_map_ram_ptr(mr->ram_block, addr1); | ||
45 | memcpy(buf, ptr, len); | ||
46 | diff --git a/exec.c b/exec.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/exec.c | ||
49 | +++ b/exec.c | ||
50 | @@ -XXX,XX +XXX,XX @@ iotlb_fail: | ||
51 | |||
52 | /* Called from RCU critical section */ | ||
53 | MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, | ||
54 | - hwaddr *plen, bool is_write) | ||
55 | + hwaddr *plen, bool is_write, | ||
56 | + MemTxAttrs attrs) | ||
57 | { | 89 | { |
58 | MemoryRegion *mr; | ||
59 | MemoryRegionSection section; | ||
60 | @@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, | ||
61 | } | ||
62 | |||
63 | l = len; | ||
64 | - mr = flatview_translate(fv, addr, &addr1, &l, true); | ||
65 | + mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); | ||
66 | } | ||
67 | |||
68 | return result; | ||
69 | @@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, | ||
70 | MemTxResult result = MEMTX_OK; | ||
71 | |||
72 | l = len; | ||
73 | - mr = flatview_translate(fv, addr, &addr1, &l, true); | ||
74 | + mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); | ||
75 | result = flatview_write_continue(fv, addr, attrs, buf, len, | ||
76 | addr1, l, mr); | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, | ||
79 | } | ||
80 | |||
81 | l = len; | ||
82 | - mr = flatview_translate(fv, addr, &addr1, &l, false); | ||
83 | + mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); | ||
84 | } | ||
85 | |||
86 | return result; | ||
87 | @@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, | ||
88 | MemoryRegion *mr; | ||
89 | |||
90 | l = len; | ||
91 | - mr = flatview_translate(fv, addr, &addr1, &l, false); | ||
92 | + mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); | ||
93 | return flatview_read_continue(fv, addr, attrs, buf, len, | ||
94 | addr1, l, mr); | ||
95 | } | ||
96 | @@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, | ||
97 | |||
98 | while (len > 0) { | ||
99 | l = len; | ||
100 | - mr = flatview_translate(fv, addr, &xlat, &l, is_write); | ||
101 | + mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); | ||
102 | if (!memory_access_is_direct(mr, is_write)) { | ||
103 | l = memory_access_size(mr, l, addr); | ||
104 | if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { | ||
105 | @@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr, | ||
106 | |||
107 | len = target_len; | ||
108 | this_mr = flatview_translate(fv, addr, &xlat, | ||
109 | - &len, is_write); | ||
110 | + &len, is_write, attrs); | ||
111 | if (this_mr != mr || xlat != base + done) { | ||
112 | return done; | ||
113 | } | ||
114 | @@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as, | ||
115 | l = len; | ||
116 | rcu_read_lock(); | ||
117 | fv = address_space_to_flatview(as); | ||
118 | - mr = flatview_translate(fv, addr, &xlat, &l, is_write); | ||
119 | + mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); | ||
120 | |||
121 | if (!memory_access_is_direct(mr, is_write)) { | ||
122 | if (atomic_xchg(&bounce.in_use, true)) { | ||
123 | -- | 90 | -- |
124 | 2.17.1 | 91 | 2.20.1 |
125 | 92 | ||
126 | 93 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Shannon Zhao <zhaoshenglong@huawei.com> | ||
2 | 1 | ||
3 | acpi_data_push uses g_array_set_size to resize the memory size. If there | ||
4 | is no enough contiguous memory, the address will be changed. So previous | ||
5 | pointer could not be used any more. It must update the pointer and use | ||
6 | the new one. | ||
7 | |||
8 | Also, previous codes wrongly use le32 conversion of iort->node_offset | ||
9 | for subsequent computations that will result incorrect value if host is | ||
10 | not litlle endian. So use the non-converted one instead. | ||
11 | |||
12 | Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> | ||
13 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
14 | Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
16 | --- | ||
17 | hw/arm/virt-acpi-build.c | 20 +++++++++++++++----- | ||
18 | 1 file changed, 15 insertions(+), 5 deletions(-) | ||
19 | |||
20 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/arm/virt-acpi-build.c | ||
23 | +++ b/hw/arm/virt-acpi-build.c | ||
24 | @@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
25 | AcpiIortItsGroup *its; | ||
26 | AcpiIortTable *iort; | ||
27 | AcpiIortSmmu3 *smmu; | ||
28 | - size_t node_size, iort_length, smmu_offset = 0; | ||
29 | + size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; | ||
30 | AcpiIortRC *rc; | ||
31 | |||
32 | iort = acpi_data_push(table_data, sizeof(*iort)); | ||
33 | @@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
34 | |||
35 | iort_length = sizeof(*iort); | ||
36 | iort->node_count = cpu_to_le32(nb_nodes); | ||
37 | - iort->node_offset = cpu_to_le32(sizeof(*iort)); | ||
38 | + /* | ||
39 | + * Use a copy in case table_data->data moves during acpi_data_push | ||
40 | + * operations. | ||
41 | + */ | ||
42 | + iort_node_offset = sizeof(*iort); | ||
43 | + iort->node_offset = cpu_to_le32(iort_node_offset); | ||
44 | |||
45 | /* ITS group node */ | ||
46 | node_size = sizeof(*its) + sizeof(uint32_t); | ||
47 | @@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
48 | int irq = vms->irqmap[VIRT_SMMU]; | ||
49 | |||
50 | /* SMMUv3 node */ | ||
51 | - smmu_offset = iort->node_offset + node_size; | ||
52 | + smmu_offset = iort_node_offset + node_size; | ||
53 | node_size = sizeof(*smmu) + sizeof(*idmap); | ||
54 | iort_length += node_size; | ||
55 | smmu = acpi_data_push(table_data, node_size); | ||
56 | @@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
57 | idmap->id_count = cpu_to_le32(0xFFFF); | ||
58 | idmap->output_base = 0; | ||
59 | /* output IORT node is the ITS group node (the first node) */ | ||
60 | - idmap->output_reference = cpu_to_le32(iort->node_offset); | ||
61 | + idmap->output_reference = cpu_to_le32(iort_node_offset); | ||
62 | } | ||
63 | |||
64 | /* Root Complex Node */ | ||
65 | @@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
66 | idmap->output_reference = cpu_to_le32(smmu_offset); | ||
67 | } else { | ||
68 | /* output IORT node is the ITS group node (the first node) */ | ||
69 | - idmap->output_reference = cpu_to_le32(iort->node_offset); | ||
70 | + idmap->output_reference = cpu_to_le32(iort_node_offset); | ||
71 | } | ||
72 | |||
73 | + /* | ||
74 | + * Update the pointer address in case table_data->data moves during above | ||
75 | + * acpi_data_push operations. | ||
76 | + */ | ||
77 | + iort = (AcpiIortTable *)(table_data->data + iort_start); | ||
78 | iort->length = cpu_to_le32(iort_length); | ||
79 | |||
80 | build_header(linker, table_data, (void *)(table_data->data + iort_start), | ||
81 | -- | ||
82 | 2.17.1 | ||
83 | |||
84 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Shannon Zhao <zhaoshenglong@huawei.com> | ||
2 | 1 | ||
3 | kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to | ||
4 | initialize global capability variables. If we call kvm_init_irq_routing in | ||
5 | GIC realize function, previous allocated memory will leak. | ||
6 | |||
7 | Fix this by deleting the unnecessary call. | ||
8 | |||
9 | Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> | ||
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
11 | Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/intc/arm_gic_kvm.c | 1 - | ||
15 | hw/intc/arm_gicv3_kvm.c | 1 - | ||
16 | 2 files changed, 2 deletions(-) | ||
17 | |||
18 | diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/hw/intc/arm_gic_kvm.c | ||
21 | +++ b/hw/intc/arm_gic_kvm.c | ||
22 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) | ||
23 | |||
24 | if (kvm_has_gsi_routing()) { | ||
25 | /* set up irq routing */ | ||
26 | - kvm_init_irq_routing(kvm_state); | ||
27 | for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { | ||
28 | kvm_irqchip_add_irq_route(kvm_state, i, 0, i); | ||
29 | } | ||
30 | diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/hw/intc/arm_gicv3_kvm.c | ||
33 | +++ b/hw/intc/arm_gicv3_kvm.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp) | ||
35 | |||
36 | if (kvm_has_gsi_routing()) { | ||
37 | /* set up irq routing */ | ||
38 | - kvm_init_irq_routing(kvm_state); | ||
39 | for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) { | ||
40 | kvm_irqchip_add_irq_route(kvm_state, i, 0, i); | ||
41 | } | ||
42 | -- | ||
43 | 2.17.1 | ||
44 | |||
45 | diff view generated by jsdifflib |