The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:

This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20210617165647.2575955-4-erdnaxe@crans.org

diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/docs/system/arm/stm32.rst

@@ -XXX,XX +XXX,XX @@

+STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)

+========================================================================================

+

+The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by

+STMicroelectronics.

+

+.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html

+

+The STM32F1 series is based on ARM Cortex-M3 core. The following machines are

+based on this chip :

+

+- ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller

+

+The STM32F2 series is based on ARM Cortex-M3 core. The following machines are

+based on this chip :

+

+- ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller

+

+The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin

+compatible with STM32F2 series. The following machines are based on this chip :

+

+- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcontroller

+

+There are many other STM32 series that are currently not supported by QEMU.

+

+Supported devices

+-----------------

+

+ * ARM Cortex-M3, Cortex M4F

+ * Analog to Digital Converter (ADC)

+ * EXTI interrupt

+ * Serial ports (USART)

+ * SPI controller

+ * System configuration (SYSCFG)

+ * Timer controller (TIMER)

+

+Missing devices

+---------------

+

+ * Camera interface (DCMI)

+ * Controller Area Network (CAN)

+ * Cycle Redundancy Check (CRC) calculation unit

+ * Digital to Analog Converter (DAC)

+ * DMA controller

+ * Ethernet controller

+ * Flash Interface Unit

+ * GPIO controller

+ * I2C controller

+ * Inter-Integrated Sound (I2S) controller

+ * Power supply configuration (PWR)

+ * Random Number Generator (RNG)

+ * Real-Time Clock (RTC) controller

+ * Reset and Clock Controller (RCC)

+ * Secure Digital Input/Output (SDIO) interface

+ * USB OTG

+ * Watchdog controller (IWDG, WWDG)

+

+Boot options

+------------

+

+The STM32 machines can be started using the ``-kernel`` option to load a

+firmware. Example:

+

+.. code-block:: bash

+

+ $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin

diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/target-arm.rst

+++ b/docs/system/target-arm.rst

@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running

arm/collie

arm/sx1

arm/stellaris

+ arm/stm32

arm/virt

arm/xlnx-versal-virt

@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)

for (i = 0; i < N_GPIOS; i++) {

mask = 1 << i;

if (changed & mask) {

- DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);

+ trace_pl061_input_change(DEVICE(s)->canonical_path, i,

+ (s->data & mask) != 0);

if (!(s->isense & mask)) {

/* Edge interrupt */

@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)

/* Level interrupt */

s->istate |= ~(s->data ^ s->iev) & s->isense;

- DPRINTF("istate = %02X\n", s->istate);

+ trace_pl061_update_istate(DEVICE(s)->canonical_path,

+ s->istate, s->im, (s->istate & s->im) != 0);

qemu_set_irq(s->irq, (s->istate & s->im) != 0);

}

diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events

index XXXXXXX..XXXXXXX 100644

--- a/hw/gpio/trace-events

+++ b/hw/gpio/trace-events

@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x

nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64

+# pl061.c

+pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"

+pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"

+pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"

+pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"

+

# sifive_gpio.c

sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64

sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64

PL061State *s = (PL061State *)opaque;

- if (offset < 0x400) {

- return s->data & (offset >> 2);

- }

- if (offset >= s->rsvd_start && offset <= 0xfcc) {

- goto err_out;

- }

- if (offset >= 0xfd0 && offset < 0x1000) {

- return s->id[(offset - 0xfd0) >> 2];

- }

switch (offset) {

+ case 0x0 ... 0x3ff: /* Data */

+ return s->data & (offset >> 2);

case 0x400: /* Direction */

return s->dir;

case 0x404: /* Interrupt sense */

@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,

case 0x420: /* Alternate function select */

return s->afsel;

case 0x500: /* 2mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->dr2r;

case 0x504: /* 4mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->dr4r;

case 0x508: /* 8mA drive */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }

return s->dr8r;

case 0x50c: /* Open drain */

+ if (s->id != pl061_id_luminary) {

+ goto bad_offset;

+ }