Series comparison

-[Qemu-devel] [PULL 00/25] target-arm queue
+[PULL 00/12] target-arm queue
-target-arm queue. This has the "plumb txattrs through various
+The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:
 bits of exec.c" patches, and a collection of bug fixes from
 various people.
-thanks
+  Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)
 -- PMM
 The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
   Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008
-for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
+for you to fetch changes up to ba118c26e16a97e6ff6de8184057d3420ce16a23:
-  KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
+  target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 15:24:32 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * target/arm: Honour FPCR.FZ in FRECPX
+ * hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
- * MAINTAINERS: Add entries for newer MPS2 boards and devices
+ * hw/arm/fsl-imx25: Fix a typo
- * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+ * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
- * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
+ * hw/arm/sbsa-ref : allocate IRQs for SMMUv3
-   GIC state
+ * hw/char/bcm2835_aux: Allow less than 32-bit accesses
- * tcg: Fix helper function vs host abi for float16
+ * hw/arm/virt: Implement kvm-steal-time
- * arm: fix qemu crash on startup with -bios option
+ * target/arm: Make '-cpu max' have a 48-bit PA
  * arm: fix malloc type mismatch
  * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
  * Correct CPACR reset value for v7 cores
  * memory.h: Improve IOMMU related documentation
  * exec: Plumb transaction attributes through various functions in
    preparation for allowing IOMMUs to see them
  * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
  * ARM: ACPI: Fix use-after-free due to memory realloc
  * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
 ----------------------------------------------------------------
-Francisco Iglesias (1):
+Andrew Jones (6):
-      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+      linux headers: sync to 5.9-rc7
       target/arm/kvm: Make uncalled stubs explicitly unreachable
       hw/arm/virt: Move post cpu realize check into its own function
       hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
       tests/qtest: Restore aarch64 arm-cpu-features test
       hw/arm/virt: Implement kvm-steal-time
-Igor Mammedov (1):
+Graeme Gregory (2):
-      arm: fix qemu crash on startup with -bios option
+      hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
       hw/arm/sbsa-ref : allocate IRQs for SMMUv3
-Jan Kiszka (1):
+Peter Maydell (1):
-      hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+      target/arm: Make '-cpu max' have a 48-bit PA
-Paolo Bonzini (1):
+Philippe Mathieu-Daudé (3):
-      arm: fix malloc type mismatch
+      hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
       hw/arm/fsl-imx25: Fix a typo
       hw/char/bcm2835_aux: Allow less than 32-bit accesses
-Peter Maydell (17):
+ docs/system/arm/cpu-features.rst |  11 ++++
-      target/arm: Honour FPCR.FZ in FRECPX
+ include/hw/arm/fsl-imx25.h       |   2 +-
-      MAINTAINERS: Add entries for newer MPS2 boards and devices
+ include/hw/arm/virt.h            |   5 ++
-      Correct CPACR reset value for v7 cores
+ linux-headers/linux/kvm.h        |   6 ++-
-      memory.h: Improve IOMMU related documentation
+ target/arm/cpu.h                 |   4 ++
-      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
+ target/arm/kvm_arm.h             |  94 ++++++++++++++++++++++++++-------
-      Make address_space_translate{, _cached}() take a MemTxAttrs argument
+ hw/arm/sbsa-ref.c                |   3 +-
-      Make address_space_map() take a MemTxAttrs argument
+ hw/arm/virt.c                    | 110 ++++++++++++++++++++++++++++-----------
-      Make address_space_access_valid() take a MemTxAttrs argument
+ hw/char/bcm2835_aux.c            |   4 +-
-      Make flatview_extend_translation() take a MemTxAttrs argument
+ hw/ssi/npcm7xx_fiu.c             |  12 ++---
-      Make memory_region_access_valid() take a MemTxAttrs argument
+ target/arm/cpu.c                 |   8 +++
-      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
+ target/arm/cpu64.c               |   4 ++
-      Make flatview_access_valid() take a MemTxAttrs argument
+ target/arm/kvm.c                 |  16 ++++++
-      Make flatview_translate() take a MemTxAttrs argument
+ target/arm/kvm64.c               |  64 +++++++++++++++++++++--
-      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
+ target/arm/monitor.c             |   2 +-
-      Make flatview_do_translate() take a MemTxAttrs argument
+ tests/qtest/arm-cpu-features.c   |  25 +++++++--
-      Make address_space_translate_iommu take a MemTxAttrs argument
+ hw/ssi/trace-events              |   2 +-
-      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
+ tests/qtest/meson.build          |   3 +-
 files changed, 303 insertions(+), 72 deletions(-)
-Richard Henderson (1):
-      tcg: Fix helper function vs host abi for float16
-Shannon Zhao (3):
-      arm_gicv3_kvm: increase clroffset accordingly
-      ARM: ACPI: Fix use-after-free due to memory realloc
-      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
- include/exec/exec-all.h        |   5 +-
- include/exec/helper-head.h     |   2 +-
- include/exec/memory-internal.h |   3 +-
- include/exec/memory.h          | 128 +++++++++++++++++++++++++++++++++++------
- include/migration/vmstate.h    |   3 +
- include/sysemu/dma.h           |   6 +-
- accel/tcg/translate-all.c      |   4 +-
- exec.c                         |  95 ++++++++++++++++++------------
- hw/arm/boot.c                  |  18 +++---
- hw/arm/virt-acpi-build.c       |  20 +++++--
- hw/dma/xlnx-zdma.c             |  10 +++-
- hw/hppa/dino.c                 |   3 +-
- hw/intc/arm_gic_kvm.c          |   1 -
- hw/intc/arm_gicv3_cpuif.c      |  12 ++--
- hw/intc/arm_gicv3_kvm.c        |   2 +-
- hw/nvram/fw_cfg.c              |  12 ++--
- hw/s390x/s390-pci-inst.c       |   3 +-
- hw/scsi/esp.c                  |   3 +-
- hw/vfio/common.c               |   3 +-
- hw/virtio/vhost.c              |   3 +-
- hw/xen/xen_pt_msi.c            |   3 +-
- memory.c                       |  12 ++--
- memory_ldst.inc.c              |  18 +++---
- target/arm/gdbstub.c           |   3 +-
- target/arm/helper-a64.c        |  41 +++++++------
- target/arm/helper.c            |  90 ++++++++++++++++-------------
- target/ppc/mmu-hash64.c        |   3 +-
- target/riscv/helper.c          |   2 +-
- target/s390x/diag.c            |   6 +-
- target/s390x/excp_helper.c     |   3 +-
- target/s390x/mmu_helper.c      |   3 +-
- target/s390x/sigp.c            |   3 +-
- target/xtensa/op_helper.c      |   3 +-
- MAINTAINERS                    |   9 ++-
-files changed, 353 insertions(+), 182 deletions(-)

-[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
+[PULL 01/12] hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 add MemTxAttrs as an argument to flatview_access_valid().
 Its callers now all have an attrs value to hand, so we can
 correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
+Fix integer handling issues handling issue reported by Coverity:
+  hw/ssi/npcm7xx_fiu.c: 162 in npcm7xx_fiu_flash_read()
+  >>>     CID 1432730:  Integer handling issues  (NEGATIVE_RETURNS)
+  >>>     "npcm7xx_fiu_cs_index(fiu, f)" is passed to a parameter that cannot be negative.
+npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));
+  hw/ssi/npcm7xx_fiu.c: 221 in npcm7xx_fiu_flash_write()
+cs_id = npcm7xx_fiu_cs_index(fiu, f);
+trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
+size, v);
+  >>>     CID 1432729:  Integer handling issues  (NEGATIVE_RETURNS)
+  >>>     "cs_id" is passed to a parameter that cannot be negative.
+npcm7xx_fiu_select(fiu, cs_id);
+Since the index of the flash can not be negative, return an
+unsigned type.
+Reported-by: Coverity (CID 1432729 & 1432730: NEGATIVE_RETURNS)
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
+Message-id: 20200919132435.310527-1-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
 ---
- exec.c | 12 +++++-------
+ hw/ssi/npcm7xx_fiu.c | 12 ++++++------
-file changed, 5 insertions(+), 7 deletions(-)
+ hw/ssi/trace-events  |  2 +-
 files changed, 7 insertions(+), 7 deletions(-)
-diff --git a/exec.c b/exec.c
+diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
 index XXXXXXX..XXXXXXX 100644
---- a/exec.c
+--- a/hw/ssi/npcm7xx_fiu.c
-+++ b/exec.c
++++ b/hw/ssi/npcm7xx_fiu.c
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@ enum NPCM7xxFIURegister {
- static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
+  * Returns the index of flash in the fiu->flash array. This corresponds to the
-                                   const uint8_t *buf, int len);
+  * chip select ID of the flash.
- static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
+  */
--                                  bool is_write);
+-static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
-+                                  bool is_write, MemTxAttrs attrs);
++static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu,
++                                     NPCM7xxFIUFlash *flash)
- static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
+ {
-                                 unsigned len, MemTxAttrs attrs)
+     int index = flash - fiu->flash;
-@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
- #endif
+@@ -XXX,XX +XXX,XX @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
      return flatview_access_valid(subpage->fv, addr + subpage->base,
 -                                 len, is_write);
 +                                 len, is_write, attrs);
  }
- static const MemoryRegionOps subpage_ops = {
+ /* Assert the chip select specified in the UMA Control/Status Register. */
-@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
+-static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
 +static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id)
  {
      trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
      if (cs_id < s->cs_count) {
          qemu_irq_lower(s->cs_lines[cs_id]);
 +        s->active_cs = cs_id;
      } else {
          qemu_log_mask(LOG_GUEST_ERROR,
                        "%s: UMA to CS%d; this module has only %d chip selects",
                        DEVICE(s)->canonical_path, cs_id, s->cs_count);
 -        cs_id = -1;
 +        s->active_cs = -1;
      }
 -
 -    s->active_cs = cs_id;
  }
- static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
+ /* Deassert the currently active chip select. */
--                                  bool is_write)
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
-+                                  bool is_write, MemTxAttrs attrs)
+     NPCM7xxFIUFlash *f = opaque;
- {
+     NPCM7xxFIUState *fiu = f->fiu;
-     MemoryRegion *mr;
+     uint32_t dwr_cfg;
-     hwaddr l, xlat;
+-    int cs_id;
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
++    unsigned cs_id;
-         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
+     int i;
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
+     if (fiu->active_cs != -1) {
--            /* When our callers all have attrs we'll pass them through here */
+diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
--            if (!memory_region_access_valid(mr, xlat, l, is_write,
+index XXXXXXX..XXXXXXX 100644
--                                            MEMTXATTRS_UNSPECIFIED)) {
+--- a/hw/ssi/trace-events
-+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
++++ b/hw/ssi/trace-events
-                 return false;
+@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
-             }
+ npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-         }
+ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
+ npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+-npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
-     rcu_read_lock();
++npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
      fv = address_space_to_flatview(as);
 -    result = flatview_access_valid(fv, addr, len, is_write);
 +    result = flatview_access_valid(fv, addr, len, is_write, attrs);
      rcu_read_unlock();
      return result;
  }
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+[PULL 02/12] hw/arm/fsl-imx25: Fix a typo
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Coverity found that the string return by 'object_get_canonical_path' was not
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-being freed at two locations in the model (CID 1391294 and CID 1391293) and
+Message-id: 20201002080935.1660005-1-f4bug@amsat.org
 also that a memset was being called with a value greater than the max of a byte
 on the second argument (CID 1391286). This patch corrects this by adding the
 freeing of the strings and also changing to memset to zero instead on
 descriptor unaligned errors.
 Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/dma/xlnx-zdma.c | 10 +++++++---
+ include/hw/arm/fsl-imx25.h | 2 +-
-file changed, 7 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
+diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/dma/xlnx-zdma.c
+--- a/include/hw/arm/fsl-imx25.h
-+++ b/hw/dma/xlnx-zdma.c
++++ b/include/hw/arm/fsl-imx25.h
-@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
+@@ -XXX,XX +XXX,XX @@ struct FslIMX25State {
-         qemu_log_mask(LOG_GUEST_ERROR,
+  * 0xBB00_0000 0xBB00_0FFF 4 Kbytes     NAND flash main area buffer
-                       "zdma: unaligned descriptor at %" PRIx64,
+  * 0xBB00_1000 0xBB00_11FF 512 B        NAND flash spare area buffer
-                       addr);
+  * 0xBB00_1200 0xBB00_1DFF 3 Kbytes     Reserved
--        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+- * 0xBB00_1E00 0xBB00_1FFF 512 B        NAND flash control regisers
-+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
++ * 0xBB00_1E00 0xBB00_1FFF 512 B        NAND flash control registers
-         s->error = true;
+  * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
-         return false;
+  * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes  Reserved
-     }
+  */
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
      RegisterInfo *r = &s->regs_info[addr / 4];
      if (!r->data) {
 +        gchar *path = object_get_canonical_path(OBJECT(s));
          qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
 -                 object_get_canonical_path(OBJECT(s)),
 +                 path,
                   addr);
 +        g_free(path);
          ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
          zdma_ch_imr_update_irq(s);
          return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
      RegisterInfo *r = &s->regs_info[addr / 4];
      if (!r->data) {
 +        gchar *path = object_get_canonical_path(OBJECT(s));
          qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
 -                 object_get_canonical_path(OBJECT(s)),
 +                 path,
                   addr, value);
 +        g_free(path);
          ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
          zdma_ch_imr_update_irq(s);
          return;
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
+[PULL 03/12] hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
+From: Graeme Gregory <graeme@nuviainc.com>
 add MemTxAttrs as an argument to address_space_translate_iommu().
+SMMUv3 has an error in a previous patch where an i was transposed to a 1
+meaning interrupts would not have been correctly assigned to the SMMUv3
+instance.
+Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
+Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20201007100732.4103790-2-graeme@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
 ---
- exec.c | 8 +++++---
+ hw/arm/sbsa-ref.c | 2 +-
-file changed, 5 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/exec.c b/exec.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/exec.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/exec.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
+@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
-  * @is_write: whether the translation operation is for write
+     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
-  * @is_mmio: whether this can be MMIO, set true if it can
+     for (i = 0; i < NUM_SMMU_IRQS; i++) {
-  * @target_as: the address space targeted by the IOMMU
+         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
-+ * @attrs: transaction attributes
+-                           qdev_get_gpio_in(sms->gic, irq + 1));
-  *
++                           qdev_get_gpio_in(sms->gic, irq + i));
   * This function is called from RCU critical section.  It is the common
   * part of flatview_do_translate and address_space_translate_cached.
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
                                                           hwaddr *page_mask_out,
                                                           bool is_write,
                                                           bool is_mmio,
 -                                                         AddressSpace **target_as)
 +                                                         AddressSpace **target_as,
 +                                                         MemTxAttrs attrs)
  {
      MemoryRegionSection *section;
      hwaddr page_mask = (hwaddr)-1;
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
          return address_space_translate_iommu(iommu_mr, xlat,
                                               plen_out, page_mask_out,
                                               is_write, is_mmio,
 -                                             target_as);
 +                                             target_as, attrs);
      }
-     if (page_mask_out) {
-         /* Not behind an IOMMU, use default page size. */
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
-     section = address_space_translate_iommu(iommu_mr, xlat, plen,
-                                             NULL, is_write, true,
--                                            &target_as);
-+                                            &target_as, attrs);
-     return section.mr;
  }
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
+[PULL 04/12] hw/arm/sbsa-ref : allocate IRQs for SMMUv3
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Graeme Gregory <graeme@nuviainc.com>
-It forgot to increase clroffset during the loop. So it only clear the
+Original commit did not allocate IRQs for the SMMUv3 in the irqmap
-first 4 bytes.
+effectively using irq 0->3 (shared with other devices). Assuming
 original intent was to allocate unique IRQs then add an allocation
 to the irqmap.
-Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
+Fixes: e9fdf453240 ("hw/arm: Add arm SBSA reference machine, devices part")
-Cc: qemu-stable@nongnu.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
+Message-id: 20201007100732.4103790-3-graeme@nuviainc.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_kvm.c | 1 +
+ hw/arm/sbsa-ref.c | 1 +
 file changed, 1 insertion(+)
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/hw/intc/arm_gicv3_kvm.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
+@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
-         if (clroffset != 0) {
+     [SBSA_SECURE_UART_MM] = 9,
-             reg = 0;
+     [SBSA_AHCI] = 10,
-             kvm_gicd_access(s, clroffset, &reg, true);
+     [SBSA_EHCI] = 11,
-+            clroffset += 4;
++    [SBSA_SMMU] = 12, /* ... to 15 */
-         }
+ };
-         reg = *gic_bmp_ptr32(bmp, irq);
-         kvm_gicd_access(s, offset, &reg, true);
+ static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
+[PULL 05/12] hw/char/bcm2835_aux: Allow less than 32-bit accesses
-In commit f0aff255700 we made cpacr_write() enforce that some CPACR
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
 we forgot to also update the register's reset value. The effect
 was that (a) a guest that read CPACR on reset would not see ones in
 the RAO bits, and (b) if you did a migration before the guest did
 a write to the CPACR then the migration would fail because the
 destination would enforce the RAO bits and then complain that they
 didn't match the zero value from the source.
-Implement reset for the CPACR using a custom reset function
+The "BCM2835 ARM Peripherals" datasheet [*] chapter 2
-that just calls cpacr_write(), to avoid having to duplicate
+("Auxiliaries: UART1 & SPI1, SPI2"), list the register
-the logic for which bits are RAO.
+sizes as 3/8/16/32 bits. We assume this means this
 peripheral allows 8-bit accesses.
-This bug would affect migration for TCG CPUs which are ARMv7
+This was not an issue until commit 5d971f9e67 which reverted
-with VFP but without one of Neon or VFPv3.
+("memory: accept mismatching sizes in memory_region_access_valid").
-Reported-by: Cédric Le Goater <clg@kaod.org>
+The model is implemented as 32-bit accesses (see commit 97398d900c,
 all registers are 32-bit) so replace MemoryRegionOps.valid as
 MemoryRegionOps.impl, and re-introduce MemoryRegionOps.valid
 with a 8/32-bit range.
 [*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
 Fixes: 97398d900c ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block")
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20201002181032.1899463-1-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Tested-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 10 +++++++++-
+ hw/char/bcm2835_aux.c | 4 +++-
-file changed, 9 insertions(+), 1 deletion(-)
+file changed, 3 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/char/bcm2835_aux.c
-+++ b/target/arm/helper.c
++++ b/hw/char/bcm2835_aux.c
-@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bcm2835_aux_ops = {
-     env->cp15.cpacr_el1 = value;
+     .read = bcm2835_aux_read,
- }
+     .write = bcm2835_aux_write,
+     .endianness = DEVICE_NATIVE_ENDIAN,
-+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+-    .valid.min_access_size = 4,
-+{
++    .impl.min_access_size = 4,
-+    /* Call cpacr_write() so that we reset with the correct RAO bits set
++    .impl.max_access_size = 4,
-+     * for our CPU features.
++    .valid.min_access_size = 1,
-+     */
+     .valid.max_access_size = 4,
 +    cpacr_write(env, ri, 0);
 +}
 +
  static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                     bool isread)
  {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
      { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
        .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 -      .resetvalue = 0, .writefn = cpacr_write },
 +      .resetfn = cpacr_reset, .writefn = cpacr_write },
      REGINFO_SENTINEL
  };
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
+[PULL 06/12] linux headers: sync to 5.9-rc7
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Andrew Jones <drjones@redhat.com>
-kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
+Update against Linux 5.9-rc7.
 initialize global capability variables. If we call kvm_init_irq_routing in
 GIC realize function, previous allocated memory will leak.
-Fix this by deleting the unnecessary call.
+Cc: Paolo Bonzini <pbonzini@redhat.com>
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Message-id: 20201001061718.101915-2-drjones@redhat.com
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gic_kvm.c   | 1 -
+ linux-headers/linux/kvm.h | 6 ++++--
- hw/intc/arm_gicv3_kvm.c | 1 -
+file changed, 4 insertions(+), 2 deletions(-)
 files changed, 2 deletions(-)
-diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
+diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic_kvm.c
+--- a/linux-headers/linux/kvm.h
-+++ b/hw/intc/arm_gic_kvm.c
++++ b/linux-headers/linux/kvm.h
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
+ #define KVM_VM_PPC_HV 1
-     if (kvm_has_gsi_routing()) {
+ #define KVM_VM_PPC_PR 2
-         /* set up irq routing */
--        kvm_init_irq_routing(kvm_state);
+-/* on MIPS, 0 forces trap & emulate, 1 forces VZ ASE */
-         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
+-#define KVM_VM_MIPS_TE        0
-             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
++/* on MIPS, 0 indicates auto, 1 forces VZ ASE, 2 forces trap & emulate */
-         }
++#define KVM_VM_MIPS_AUTO    0
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+ #define KVM_VM_MIPS_VZ        1
-index XXXXXXX..XXXXXXX 100644
++#define KVM_VM_MIPS_TE        2
---- a/hw/intc/arm_gicv3_kvm.c
-+++ b/hw/intc/arm_gicv3_kvm.c
+ #define KVM_S390_SIE_PAGE_OFFSET 1
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
-     if (kvm_has_gsi_routing()) {
+ #define KVM_CAP_LAST_CPU 184
-         /* set up irq routing */
+ #define KVM_CAP_SMALLER_MAXPHYADDR 185
--        kvm_init_irq_routing(kvm_state);
+ #define KVM_CAP_S390_DIAG318 186
-         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
++#define KVM_CAP_STEAL_TIME 187
-             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
-         }
+ #ifdef KVM_CAP_IRQ_ROUTING
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
+[PULL 07/12] target/arm/kvm: Make uncalled stubs explicitly unreachable
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
+From: Andrew Jones <drjones@redhat.com>
 add MemTxAttrs as an argument to address_space_access_valid().
 Its callers either have an attrs value to hand, or don't care
 and can use MEMTXATTRS_UNSPECIFIED.
+When we compile without KVM support !defined(CONFIG_KVM) we generate
+stubs for functions that the linker will still encounter. Sometimes
+these stubs can be executed safely and are placed in paths where they
+get executed with or without KVM. Other functions should never be
+called without KVM. Those functions should be guarded by kvm_enabled(),
+but should also be robust to refactoring mistakes. Putting a
+g_assert_not_reached() in the function should help. Additionally,
+the g_assert_not_reached() calls may actually help the linker remove
+some code.
+We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't
+necessary at all - the only caller is in kvm.c
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Signed-off-by: Andrew Jones <drjones@redhat.com>
+Message-id: 20201001061718.101915-3-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
 ---
- include/exec/memory.h      | 4 +++-
+ target/arm/kvm_arm.h | 51 +++++++++++++++++++++++++++-----------------
- include/sysemu/dma.h       | 3 ++-
+file changed, 32 insertions(+), 19 deletions(-)
  exec.c                     | 3 ++-
  target/s390x/diag.c        | 6 ++++--
  target/s390x/excp_helper.c | 3 ++-
  target/s390x/mmu_helper.c  | 3 ++-
  target/s390x/sigp.c        | 3 ++-
 files changed, 17 insertions(+), 8 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
+--- a/target/arm/kvm_arm.h
-+++ b/include/exec/memory.h
++++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
+@@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
-  * @addr: address within that address space
-  * @len: length of the area to be checked
+ #else
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
+-static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
-  */
+-{
--bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
+-    /*
-+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
+-     * This should never actually be called in the "not KVM" case,
-+                                bool is_write, MemTxAttrs attrs);
+-     * but set up the fields to indicate an error anyway.
+-     */
- /* address_space_map: map a physical memory region into a host virtual address
+-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
-  *
+-    cpu->host_cpu_probe_failed = true;
-diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
+-}
-index XXXXXXX..XXXXXXX 100644
+-
---- a/include/sysemu/dma.h
+-static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
-+++ b/include/sysemu/dma.h
+-
-@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
++/*
-                                     DMADirection dir)
++ * It's safe to call these functions without KVM support.
 + * They should either do nothing or return "not supported".
 + */
  static inline bool kvm_arm_aarch32_supported(void)
  {
-     return address_space_access_valid(as, addr, len,
+     return false;
--                                      dir == DMA_DIRECTION_FROM_DEVICE);
+@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
-+                                      dir == DMA_DIRECTION_FROM_DEVICE,
+     return false;
 +                                      MEMTXATTRS_UNSPECIFIED);
  }
- static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
++/*
-diff --git a/exec.c b/exec.c
++ * These functions should never actually be called without KVM support.
-index XXXXXXX..XXXXXXX 100644
++ */
---- a/exec.c
++static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
-+++ b/exec.c
++{
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
++    g_assert_not_reached();
 +}
 +
 +static inline void kvm_arm_add_vcpu_properties(Object *obj)
 +{
 +    g_assert_not_reached();
 +}
 +
  static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
  {
 -    return -ENOENT;
 +    g_assert_not_reached();
  }
- bool address_space_access_valid(AddressSpace *as, hwaddr addr,
+ static inline int kvm_arm_vgic_probe(void)
 -                                int len, bool is_write)
 +                                int len, bool is_write,
 +                                MemTxAttrs attrs)
  {
-     FlatView *fv;
+-    return 0;
-     bool result;
++    g_assert_not_reached();
-diff --git a/target/s390x/diag.c b/target/s390x/diag.c
+ }
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/diag.c
+-static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
-+++ b/target/s390x/diag.c
+-static inline void kvm_arm_pmu_init(CPUState *cs) {}
-@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
++static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
-             return;
++{
-         }
++    g_assert_not_reached();
-         if (!address_space_access_valid(&address_space_memory, addr,
++}
--                                        sizeof(IplParameterBlock), false)) {
-+                                        sizeof(IplParameterBlock), false,
+-static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
-+                                        MEMTXATTRS_UNSPECIFIED)) {
++static inline void kvm_arm_pmu_init(CPUState *cs)
-             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
++{
-             return;
++    g_assert_not_reached();
-         }
++}
-@@ -XXX,XX +XXX,XX @@ out:
++
-             return;
++static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
-         }
++{
-         if (!address_space_access_valid(&address_space_memory, addr,
++    g_assert_not_reached();
--                                        sizeof(IplParameterBlock), true)) {
++}
-+                                        sizeof(IplParameterBlock), true,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
+-static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
-             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
+-static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
-             return;
+ #endif
-         }
-diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
+ static inline const char *gic_class_name(void)
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/excp_helper.c
 +++ b/target/s390x/excp_helper.c
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
      /* check out of RAM access */
      if (!address_space_access_valid(&address_space_memory, raddr,
 -                                    TARGET_PAGE_SIZE, rw)) {
 +                                    TARGET_PAGE_SIZE, rw,
 +                                    MEMTXATTRS_UNSPECIFIED)) {
          DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                  (uint64_t)raddr, (uint64_t)ram_size);
          trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
 diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/mmu_helper.c
 +++ b/target/s390x/mmu_helper.c
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
              return ret;
          }
          if (!address_space_access_valid(&address_space_memory, pages[i],
 -                                        TARGET_PAGE_SIZE, is_write)) {
 +                                        TARGET_PAGE_SIZE, is_write,
 +                                        MEMTXATTRS_UNSPECIFIED)) {
              trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
              return -EFAULT;
          }
 diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/s390x/sigp.c
 +++ b/target/s390x/sigp.c
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
      cpu_synchronize_state(cs);
      if (!address_space_access_valid(&address_space_memory, addr,
 -                                    sizeof(struct LowCore), false)) {
 +                                    sizeof(struct LowCore), false,
 +                                    MEMTXATTRS_UNSPECIFIED)) {
          set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
          return;
      }
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
+[PULL 08/12] hw/arm/virt: Move post cpu realize check into its own function
-From: Igor Mammedov <imammedo@redhat.com>
+From: Andrew Jones <drjones@redhat.com>
-When QEMU is started with following CLI
+We'll add more to this new function in coming patches so we also
- -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
+state the gic must be created and call it below create_gic().
 it crashes with abort at
  accel/kvm/kvm-all.c:2164:
  KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
-Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
+No functional change intended.
 arm_gicv3_icc_reset() where the later is called by CPU reset
 reset callback.
-However commit:
-b77f6c arm/boot: split load_dtb() from arm_load_kernel()
-broke CPU reset callback registration in case
-  arm_load_kernel()
-      ...
-      if (!info->kernel_filename || info->firmware_loaded)
-branch is taken, i.e. it's sufficient to provide a firmware
-or do not provide kernel on CLI to skip cpu reset callback
-registration, where before offending commit the callback
-has been registered unconditionally.
-Fix it by registering the callback right at the beginning of
-arm_load_kernel() unconditionally instead of doing it at the end.
-NOTE:
- we probably should eliminate that dependency anyways as well as
- separate arch CPU reset parts from arm_load_kernel() into CPU
- itself, but that refactoring that I probably would have to do
- anyways later for CPU hotplug to work.
-Reported-by: Auger Eric <eric.auger@redhat.com>
-Signed-off-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Tested-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Andrew Jones <drjones@redhat.com>
+Message-id: 20201001061718.101915-4-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/boot.c | 18 +++++++++---------
+ hw/arm/virt.c | 43 +++++++++++++++++++++++++++----------------
-file changed, 9 insertions(+), 9 deletions(-)
+file changed, 27 insertions(+), 16 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/arm/virt.c
-+++ b/hw/arm/boot.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
-     static const ARMInsnFixup *primary_loader;
+     }
-     AddressSpace *as = arm_boot_address_space(cpu, info);
+ }
-+    /* CPU objects (unlike devices) are not automatically reset on system
++/*
-+     * reset, so we must always register a handler to do so. If we're
++ * virt_cpu_post_init() must be called after the CPUs have
-+     * actually loading a kernel, the handler is also responsible for
++ * been realized and the GIC has been created.
-+     * arranging that we start it correctly.
++ */
-+     */
++static void virt_cpu_post_init(VirtMachineState *vms)
-+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
++{
-+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
++    bool aarch64;
 +
 +    aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
 +
 +    if (!kvm_enabled()) {
 +        if (aarch64 && vms->highmem) {
 +            int requested_pa_size = 64 - clz64(vms->highest_gpa);
 +            int pamax = arm_pamax(ARM_CPU(first_cpu));
 +
 +            if (pamax < requested_pa_size) {
 +                error_report("VCPU supports less PA bits (%d) than "
 +                             "requested by the memory map (%d)",
 +                             pamax, requested_pa_size);
 +                exit(1);
 +            }
 +        }
 +    }
++}
 +
-     /* The board code is not supposed to set secure_board_setup unless
+ static void machvirt_init(MachineState *machine)
-      * running its code in secure mode is actually possible, and KVM
+ {
-      * doesn't support secure.
+     VirtMachineState *vms = VIRT_MACHINE(machine);
-@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
-         ARM_CPU(cs)->env.boot_info = info;
+     fdt_add_timer_nodes(vms);
-     }
+     fdt_add_cpu_nodes(vms);
--    /* CPU objects (unlike devices) are not automatically reset on system
+-   if (!kvm_enabled()) {
--     * reset, so we must always register a handler to do so. If we're
+-        ARMCPU *cpu = ARM_CPU(first_cpu);
--     * actually loading a kernel, the handler is also responsible for
+-        bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
--     * arranging that we start it correctly.
+-
--     */
+-        if (aarch64 && vms->highmem) {
--    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+-            int requested_pa_size, pamax = arm_pamax(cpu);
--        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+-
 -            requested_pa_size = 64 - clz64(vms->highest_gpa);
 -            if (pamax < requested_pa_size) {
 -                error_report("VCPU supports less PA bits (%d) than requested "
 -                            "by the memory map (%d)", pamax, requested_pa_size);
 -                exit(1);
 -            }
 -        }
 -    }
 -
-     if (!info->skip_dtb_autoload && have_dtb(info)) {
+     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
-         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
+                                 machine->ram);
-             exit(1);
+     if (machine->device_memory) {
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
      create_gic(vms);
 +    virt_cpu_post_init(vms);
 +
      fdt_add_pmu_nodes(vms);
      create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
+[PULL 09/12] hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Andrew Jones <drjones@redhat.com>
-acpi_data_push uses g_array_set_size to resize the memory size. If there
+Move the KVM PMU setup part of fdt_add_pmu_nodes() to
-is no enough contiguous memory, the address will be changed. So previous
+virt_cpu_post_init(), which is a more appropriate location. Now
-pointer could not be used any more. It must update the pointer and use
+fdt_add_pmu_nodes() is also named more appropriately, because it
-the new one.
+no longer does anything but fdt node creation.
-Also, previous codes wrongly use le32 conversion of iort->node_offset
+No functional change intended.
 for subsequent computations that will result incorrect value if host is
 not litlle endian. So use the non-converted one instead.
-Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
+Signed-off-by: Andrew Jones <drjones@redhat.com>
 Message-id: 20201001061718.101915-5-drjones@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
+ hw/arm/virt.c | 34 ++++++++++++++++++----------------
-file changed, 15 insertions(+), 5 deletions(-)
+file changed, 18 insertions(+), 16 deletions(-)
-diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt-acpi-build.c
+--- a/hw/arm/virt.c
-+++ b/hw/arm/virt-acpi-build.c
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
-     AcpiIortItsGroup *its;
-     AcpiIortTable *iort;
+ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
-     AcpiIortSmmu3 *smmu;
+ {
--    size_t node_size, iort_length, smmu_offset = 0;
+-    CPUState *cpu;
-+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
+-    ARMCPU *armcpu;
-     AcpiIortRC *rc;
++    ARMCPU *armcpu = ARM_CPU(first_cpu);
+     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
-     iort = acpi_data_push(table_data, sizeof(*iort));
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+-    CPU_FOREACH(cpu) {
+-        armcpu = ARM_CPU(cpu);
-     iort_length = sizeof(*iort);
+-        if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
-     iort->node_count = cpu_to_le32(nb_nodes);
+-            return;
--    iort->node_offset = cpu_to_le32(sizeof(*iort));
+-        }
-+    /*
+-        if (kvm_enabled()) {
-+     * Use a copy in case table_data->data moves during acpi_data_push
+-            if (kvm_irqchip_in_kernel()) {
-+     * operations.
+-                kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
-+     */
+-            }
-+    iort_node_offset = sizeof(*iort);
+-            kvm_arm_pmu_init(cpu);
-+    iort->node_offset = cpu_to_le32(iort_node_offset);
+-        }
++    if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
-     /* ITS group node */
++        assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
-     node_size =  sizeof(*its) + sizeof(uint32_t);
++        return;
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          int irq =  vms->irqmap[VIRT_SMMU];
          /* SMMUv3 node */
 -        smmu_offset = iort->node_offset + node_size;
 +        smmu_offset = iort_node_offset + node_size;
          node_size = sizeof(*smmu) + sizeof(*idmap);
          iort_length += node_size;
          smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          idmap->id_count = cpu_to_le32(0xFFFF);
          idmap->output_base = 0;
          /* output IORT node is the ITS group node (the first node) */
 -        idmap->output_reference = cpu_to_le32(iort->node_offset);
 +        idmap->output_reference = cpu_to_le32(iort_node_offset);
      }
-     /* Root Complex Node */
+     if (vms->gic_version == VIRT_GIC_VERSION_2) {
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
-         idmap->output_reference = cpu_to_le32(smmu_offset);
+                              (1 << vms->smp_cpus) - 1);
      } else {
          /* output IORT node is the ITS group node (the first node) */
 -        idmap->output_reference = cpu_to_le32(iort->node_offset);
 +        idmap->output_reference = cpu_to_le32(iort_node_offset);
      }
-+    /*
+-    armcpu = ARM_CPU(qemu_get_cpu(0));
-+     * Update the pointer address in case table_data->data moves during above
+     qemu_fdt_add_subnode(vms->fdt, "/pmu");
-+     * acpi_data_push operations.
+     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
-+     */
+         const char compat[] = "arm,armv8-pmuv3";
-+    iort = (AcpiIortTable *)(table_data->data + iort_start);
+@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
-     iort->length = cpu_to_le32(iort_length);
+  */
+ static void virt_cpu_post_init(VirtMachineState *vms)
-     build_header(linker, table_data, (void *)(table_data->data + iort_start),
+ {
 -    bool aarch64;
 +    bool aarch64, pmu;
 +    CPUState *cpu;
      aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
 +    pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
 -    if (!kvm_enabled()) {
 +    if (kvm_enabled()) {
 +        CPU_FOREACH(cpu) {
 +            if (pmu) {
 +                assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
 +                if (kvm_irqchip_in_kernel()) {
 +                    kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
 +                }
 +                kvm_arm_pmu_init(cpu);
 +            }
 +        }
 +    } else {
          if (aarch64 && vms->highmem) {
              int requested_pa_size = 64 - clz64(vms->highest_gpa);
              int pamax = arm_pamax(ARM_CPU(first_cpu));
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+[PULL 10/12] tests/qtest: Restore aarch64 arm-cpu-features test
-From: Jan Kiszka <jan.kiszka@siemens.com>
+From: Andrew Jones <drjones@redhat.com>
-There was a nasty flip in identifying which register group an access is
+arm-cpu-features got dropped from the AArch64 tests during the meson
-targeting. The issue caused spuriously raised priorities of the guest
+conversion shuffle.
 when handing CPUs over in the Jailhouse hypervisor.
-Cc: qemu-stable@nongnu.org
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Message-id: 20201001061718.101915-6-drjones@redhat.com
 Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
+ tests/qtest/meson.build | 3 ++-
-file changed, 6 insertions(+), 6 deletions(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/tests/qtest/meson.build
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/tests/qtest/meson.build
-@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
- {
+   (cpu != 'arm' ? ['bios-tables-test'] : []) +                                                  \
-     GICv3CPUState *cs = icc_cs_from_env(env);
+   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
-     int regno = ri->opc2 & 3;
+   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
--    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+-  ['numa-test',
-+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
++  ['arm-cpu-features',
-     uint64_t value = cs->ich_apr[grp][regno];
++   'numa-test',
+    'boot-serial-test',
-     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
+    'migration-test']
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
      uint64_t value;
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
 +    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
      if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
          return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
 +    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
      if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
          icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      uint64_t value;
      value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
+[PULL 11/12] hw/arm/virt: Implement kvm-steal-time
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Andrew Jones <drjones@redhat.com>
-Depending on the host abi, float16, aka uint16_t, values are
+We add the kvm-steal-time CPU property and implement it for machvirt.
-passed and returned either zero-extended in the host register
+A tiny bit of refactoring was also done to allow pmu and pvtime to
-or with garbage at the top of the host register.
+use the same vcpu device helper functions.
-The tcg code generator has so far been assuming garbage, as that
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
-matches the x86 abi, but this is incorrect for other host abis.
+Signed-off-by: Andrew Jones <drjones@redhat.com>
-Further, target/arm has so far been assuming zero-extended results,
+Message-id: 20201001061718.101915-7-drjones@redhat.com
 so that it may store the 16-bit value into a 32-bit slot with the
 high 16-bits already clear.
 Rectify both problems by mapping "f16" in the helper definition
 to uint32_t instead of (a typedef for) uint16_t.  This forces
 the host compiler to assume garbage in the upper 16 bits on input
 and to zero-extend the result on output.
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/exec/helper-head.h |  2 +-
+ docs/system/arm/cpu-features.rst | 11 ++++++
- target/arm/helper-a64.c    | 35 +++++++++--------
+ include/hw/arm/virt.h            |  5 +++
- target/arm/helper.c        | 80 +++++++++++++++++++-------------------
+ target/arm/cpu.h                 |  4 ++
-files changed, 59 insertions(+), 58 deletions(-)
+ target/arm/kvm_arm.h             | 43 +++++++++++++++++++++
  hw/arm/virt.c                    | 43 +++++++++++++++++++--
  target/arm/cpu.c                 |  8 ++++
  target/arm/kvm.c                 | 16 ++++++++
  target/arm/kvm64.c               | 64 +++++++++++++++++++++++++++++---
  target/arm/monitor.c             |  2 +-
  tests/qtest/arm-cpu-features.c   | 25 +++++++++++--
 files changed, 208 insertions(+), 13 deletions(-)
-diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
+diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/helper-head.h
+--- a/docs/system/arm/cpu-features.rst
-+++ b/include/exec/helper-head.h
++++ b/docs/system/arm/cpu-features.rst
@@ -XXX,XX +XXX,XX @@ the list of KVM VCPU features and their descriptions.
                             adjustment, also restoring the legacy (pre-5.0)
                             behavior.
 +  kvm-steal-time           Since v5.2, kvm-steal-time is enabled by
 +                           default when KVM is enabled, the feature is
 +                           supported, and the guest is 64-bit.
 +
 +                           When kvm-steal-time is enabled a 64-bit guest
 +                           can account for time its CPUs were not running
 +                           due to the host not scheduling the corresponding
 +                           VCPU threads.  The accounting statistics may
 +                           influence the guest scheduler behavior and/or be
 +                           exposed to the guest userspace.
 +
  SVE CPU Properties
  ==================
 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/virt.h
 +++ b/include/hw/arm/virt.h
 @@ -XXX,XX +XXX,XX @@
- #define dh_ctype_int int
- #define dh_ctype_i64 uint64_t
+ #define PPI(irq) ((irq) + 16)
- #define dh_ctype_s64 int64_t
--#define dh_ctype_f16 float16
++/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
-+#define dh_ctype_f16 uint32_t
++#define PVTIME_SIZE_PER_CPU 64
- #define dh_ctype_f32 float32
++
- #define dh_ctype_f64 float64
+ enum {
- #define dh_ctype_ptr void *
+     VIRT_FLASH,
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+     VIRT_MEM,
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ enum {
---- a/target/arm/helper-a64.c
+     VIRT_PCDIMM_ACPI,
-+++ b/target/arm/helper-a64.c
+     VIRT_ACPI_GED,
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
+     VIRT_NVDIMM_ACPI,
-     return flags;
++    VIRT_PVTIME,
- }
+     VIRT_LOWMEMMAP_LAST,
+ };
--uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
-+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
+@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
- {
+     bool no_highmem_ecam;
-     return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
+     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
- }
+     bool kvm_no_adjvtime;
++    bool no_kvm_steal_time;
--uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+     bool acpi_expose_flash;
-+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
+ };
- {
-     return float_rel_to_flags(float16_compare(x, y, fp_status));
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
- }
+index XXXXXXX..XXXXXXX 100644
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
+--- a/target/arm/cpu.h
- #define float64_three make_float64(0x4008000000000000ULL)
++++ b/target/arm/cpu.h
- #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/registerfields.h"
--float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+ #include "cpu-qom.h"
-+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
+ #include "exec/cpu-defs.h"
- {
++#include "qapi/qapi-types-common.h"
-     float_status *fpst = fpstp;
+ /* ARM processors have a weak memory model */
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
+ #define TCG_GUEST_DEFAULT_MO      (0)
-     return float64_muladd(a, b, float64_two, 0, fpst);
+@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
- }
+     bool kvm_vtime_dirty;
+     uint64_t kvm_vtime;
--float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
-+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
++    /* KVM steal time */
- {
++    OnOffAuto kvm_steal_time;
-     float_status *fpst = fpstp;
++
+     /* Uniprocessor system with MP extensions */
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
+     bool mp_is_up;
- }
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
- /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
+index XXXXXXX..XXXXXXX 100644
--float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+--- a/target/arm/kvm_arm.h
-+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
++++ b/target/arm/kvm_arm.h
- {
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
      float_status *fpst = fpstp;
      uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
  #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
  #define ADVSIMD_HALFOP(name) \
 -float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
 +uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
  { \
      float_status *fpst = fpstp; \
      return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
  ADVSIMD_TWOHALFOP(mulx)
  /* fused multiply-accumulate */
 -float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
 +uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
 +                                 void *fpstp)
  {
      float_status *fpst = fpstp;
      return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
  #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 -uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare_quiet(a, b, fpst);
      return ADVSIMD_CMPRES(compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare(a, b, fpst);
      return ADVSIMD_CMPRES(compare == float_relation_greater);
  }
 -uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
  }
  /* round to integral */
 -float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
  {
      return float16_round_to_int(x, fp_status);
  }
 -float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
  {
      int old_flags = get_float_exception_flags(fp_status), new_flags;
      float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
   * setting the mode appropriately before calling the helper.
   */
+ void kvm_arm_add_vcpu_properties(Object *obj);
--uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
-+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
++/**
- {
++ * kvm_arm_steal_time_finalize:
-     float_status *fpst = fpstp;
++ * @cpu: ARMCPU for which to finalize kvm-steal-time
++ * @errp: Pointer to Error* for error propagation
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
++ *
-     return float16_to_int16(a, fpst);
++ * Validate the kvm-steal-time property selection and set its default
- }
++ * based on KVM support and guest configuration.
++ */
--uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
++void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp);
-+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
++
- {
++/**
-     float_status *fpst = fpstp;
++ * kvm_arm_steal_time_supported:
++ *
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
++ * Returns: true if KVM can enable steal time reporting
-  * Square Root and Reciprocal square root
++ * and false otherwise.
 + */
 +bool kvm_arm_steal_time_supported(void);
 +
  /**
   * kvm_arm_aarch32_supported:
   *
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void);
  void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
  void kvm_arm_pmu_init(CPUState *cs);
 +
 +/**
 + * kvm_arm_pvtime_init:
 + * @cs: CPUState
 + * @ipa: Per-vcpu guest physical base address of the pvtime structures
 + *
 + * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa.
 + */
 +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa);
 +
  int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
  #else
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
      return false;
  }
 +static inline bool kvm_arm_steal_time_supported(void)
 +{
 +    return false;
 +}
 +
  /*
   * These functions should never actually be called without KVM support.
   */
+@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_init(CPUState *cs)
 -float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
 +uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
  {
      float_status *s = fpstp;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
  /* Integer to float and float to integer conversions */
 -#define CONV_ITOF(name, fsz, sign) \
 -    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
 +#define CONV_ITOF(name, ftype, fsz, sign)                           \
 +ftype HELPER(name)(uint32_t x, void *fpstp)                         \
 +{                                                                   \
 +    float_status *fpst = fpstp;                                     \
 +    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
  }
 -#define CONV_FTOI(name, fsz, sign, round) \
 -uint32_t HELPER(name)(float##fsz x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    if (float##fsz##_is_any_nan(x)) { \
 -        float_raise(float_flag_invalid, fpst); \
 -        return 0; \
 -    } \
 -    return float##fsz##_to_##sign##int32##round(x, fpst); \
 +#define CONV_FTOI(name, ftype, fsz, sign, round)                \
 +uint32_t HELPER(name)(ftype x, void *fpstp)                     \
 +{                                                               \
 +    float_status *fpst = fpstp;                                 \
 +    if (float##fsz##_is_any_nan(x)) {                           \
 +        float_raise(float_flag_invalid, fpst);                  \
 +        return 0;                                               \
 +    }                                                           \
 +    return float##fsz##_to_##sign##int32##round(x, fpst);       \
  }
 -#define FLOAT_CONVS(name, p, fsz, sign) \
 -CONV_ITOF(vfp_##name##to##p, fsz, sign) \
 -CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
 -CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
 +#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
 +    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
 +    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
 +    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 -FLOAT_CONVS(si, h, 16, )
 -FLOAT_CONVS(si, s, 32, )
 -FLOAT_CONVS(si, d, 64, )
 -FLOAT_CONVS(ui, h, 16, u)
 -FLOAT_CONVS(ui, s, 32, u)
 -FLOAT_CONVS(ui, d, 64, u)
 +FLOAT_CONVS(si, h, uint32_t, 16, )
 +FLOAT_CONVS(si, s, float32, 32, )
 +FLOAT_CONVS(si, d, float64, 64, )
 +FLOAT_CONVS(ui, h, uint32_t, 16, u)
 +FLOAT_CONVS(ui, s, float32, 32, u)
 +FLOAT_CONVS(ui, d, float64, 64, u)
  #undef CONV_ITOF
  #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
      return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
  }
 -float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
  }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
      }
  }
 -uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
  }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
  }
  /* Half precision conversions.  */
 -float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
      g_assert_not_reached();
  }
--float16 HELPER(recpe_f16)(float16 input, void *fpstp)
++static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
-+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
++{
- {
++    g_assert_not_reached();
-     float_status *fpst = fpstp;
++}
-     float16 f16 = float16_squash_input_denormal(input, fpst);
++
-@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
++static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
-     return extract64(estimate, 0, 8) << 44;
++{
- }
++    g_assert_not_reached();
++}
--float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
++
-+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
+ static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
  {
-     float_status *s = fpstp;
+     g_assert_not_reached();
-     float16 f16 = float16_squash_input_denormal(input, s);
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
      [VIRT_PCDIMM_ACPI] =        { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
      [VIRT_ACPI_GED] =           { 0x09080000, ACPI_GED_EVT_SEL_LEN },
      [VIRT_NVDIMM_ACPI] =        { 0x09090000, NVDIMM_ACPI_IO_LEN},
 +    [VIRT_PVTIME] =             { 0x090a0000, 0x00010000 },
      [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
      /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
      [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
   * virt_cpu_post_init() must be called after the CPUs have
   * been realized and the GIC has been created.
   */
 -static void virt_cpu_post_init(VirtMachineState *vms)
 +static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
 +                               MemoryRegion *sysmem)
  {
 -    bool aarch64, pmu;
 +    bool aarch64, pmu, steal_time;
      CPUState *cpu;
      aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
      pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
 +    steal_time = object_property_get_bool(OBJECT(first_cpu),
 +                                          "kvm-steal-time", NULL);
      if (kvm_enabled()) {
 +        hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
 +        hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
 +
 +        if (steal_time) {
 +            MemoryRegion *pvtime = g_new(MemoryRegion, 1);
 +            hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
 +
 +            /* The memory region size must be a multiple of host page size. */
 +            pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
 +
 +            if (pvtime_size > pvtime_reg_size) {
 +                error_report("pvtime requires a %ld byte memory region for "
 +                             "%d CPUs, but only %ld has been reserved",
 +                             pvtime_size, max_cpus, pvtime_reg_size);
 +                exit(1);
 +            }
 +
 +            memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
 +            memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
 +        }
 +
          CPU_FOREACH(cpu) {
              if (pmu) {
                  assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms)
                  }
                  kvm_arm_pmu_init(cpu);
              }
 +            if (steal_time) {
 +                kvm_arm_pvtime_init(cpu, pvtime_reg_base +
 +                                         cpu->cpu_index * PVTIME_SIZE_PER_CPU);
 +            }
          }
      } else {
          if (aarch64 && vms->highmem) {
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
              object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
          }
 +        if (vmc->no_kvm_steal_time &&
 +            object_property_find(cpuobj, "kvm-steal-time")) {
 +            object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
 +        }
 +
          if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
              object_property_set_bool(cpuobj, "pmu", false, NULL);
          }
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
      create_gic(vms);
 -    virt_cpu_post_init(vms);
 +    virt_cpu_post_init(vms, possible_cpus->len, sysmem);
      fdt_add_pmu_nodes(vms);
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
  static void virt_machine_5_1_options(MachineClass *mc)
  {
 +    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
 +
      virt_machine_5_2_options(mc);
      compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
 +    vmc->no_kvm_steal_time = true;
  }
  DEFINE_VIRT_MACHINE(5, 1)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
              return;
          }
      }
 +
 +    if (kvm_enabled()) {
 +        kvm_arm_steal_time_finalize(cpu, &local_err);
 +        if (local_err != NULL) {
 +            error_propagate(errp, local_err);
 +            return;
 +        }
 +    }
  }
  static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
      ARM_CPU(obj)->kvm_adjvtime = !value;
  }
 +static bool kvm_steal_time_get(Object *obj, Error **errp)
 +{
 +    return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF;
 +}
 +
 +static void kvm_steal_time_set(Object *obj, bool value, Error **errp)
 +{
 +    ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
 +}
 +
  /* KVM VCPU properties should be prefixed with "kvm-". */
  void kvm_arm_add_vcpu_properties(Object *obj)
  {
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
                                          "the virtual counter. VM stopped time "
                                          "will be counted.");
      }
 +
 +    cpu->kvm_steal_time = ON_OFF_AUTO_AUTO;
 +    object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get,
 +                             kvm_steal_time_set);
 +    object_property_set_description(obj, "kvm-steal-time",
 +                                    "Set off to disable KVM steal time.");
  }
  bool kvm_arm_pmu_supported(void)
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
  #include <linux/kvm.h>
  #include "qemu-common.h"
 +#include "qapi/error.h"
  #include "cpu.h"
  #include "qemu/timer.h"
  #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
      return NULL;
  }
 -static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr)
 +static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr,
 +                                    const char *name)
  {
      int err;
      err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
      if (err != 0) {
 -        error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err));
 +        error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err));
          return false;
      }
      err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
      if (err != 0) {
 -        error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err));
 +        error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err));
          return false;
      }
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
      if (!ARM_CPU(cs)->has_pmu) {
          return;
      }
 -    if (!kvm_arm_pmu_set_attr(cs, &attr)) {
 +    if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
          error_report("failed to init PMU");
          abort();
      }
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
      if (!ARM_CPU(cs)->has_pmu) {
          return;
      }
 -    if (!kvm_arm_pmu_set_attr(cs, &attr)) {
 +    if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
          error_report("failed to set irq for PMU");
          abort();
      }
  }
 +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
 +{
 +    struct kvm_device_attr attr = {
 +        .group = KVM_ARM_VCPU_PVTIME_CTRL,
 +        .attr = KVM_ARM_VCPU_PVTIME_IPA,
 +        .addr = (uint64_t)&ipa,
 +    };
 +
 +    if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) {
 +        return;
 +    }
 +    if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) {
 +        error_report("failed to init PVTIME IPA");
 +        abort();
 +    }
 +}
 +
  static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
  {
      uint64_t ret;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      return true;
  }
 +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
 +{
 +    bool has_steal_time = kvm_arm_steal_time_supported();
 +
 +    if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) {
 +        if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +            cpu->kvm_steal_time = ON_OFF_AUTO_OFF;
 +        } else {
 +            cpu->kvm_steal_time = ON_OFF_AUTO_ON;
 +        }
 +    } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) {
 +        if (!has_steal_time) {
 +            error_setg(errp, "'kvm-steal-time' cannot be enabled "
 +                             "on this host");
 +            return;
 +        } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +            /*
 +             * DEN0057A chapter 2 says "This specification only covers
 +             * systems in which the Execution state of the hypervisor
 +             * as well as EL1 of virtual machines is AArch64.". And,
 +             * to ensure that, the smc/hvc calls are only specified as
 +             * smc64/hvc64.
 +             */
 +            error_setg(errp, "'kvm-steal-time' cannot be enabled "
 +                             "for AArch32 guests");
 +            return;
 +        }
 +    }
 +}
 +
  bool kvm_arm_aarch32_supported(void)
  {
      return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(void)
      return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
  }
 +bool kvm_arm_steal_time_supported(void)
 +{
 +    return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
 +}
 +
  QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
  void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
 diff --git a/target/arm/monitor.c b/target/arm/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/monitor.c
 +++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
      "sve128", "sve256", "sve384", "sve512",
      "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
      "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
 -    "kvm-no-adjvtime",
 +    "kvm-no-adjvtime", "kvm-steal-time",
      NULL
  };
 diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/qtest/arm-cpu-features.c
 +++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
      assert_set_feature(qts, "max", "pmu", true);
      assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
 +    assert_has_not_feature(qts, "max", "kvm-steal-time");
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
          assert_has_feature_enabled(qts, "max", "aarch64");
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
      assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
      if (g_str_equal(qtest_get_arch(), "aarch64")) {
 +        bool kvm_supports_steal_time;
          bool kvm_supports_sve;
          char max_name[8], name[8];
          uint32_t max_vq, vq;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
          QDict *resp;
          char *error;
 +        assert_error(qts, "cortex-a15",
 +            "We cannot guarantee the CPU type 'cortex-a15' works "
 +            "with KVM on this host", NULL);
 +
          assert_has_feature_enabled(qts, "host", "aarch64");
          /* Enabling and disabling pmu should always work. */
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
          assert_set_feature(qts, "host", "pmu", false);
          assert_set_feature(qts, "host", "pmu", true);
 -        assert_error(qts, "cortex-a15",
 -            "We cannot guarantee the CPU type 'cortex-a15' works "
 -            "with KVM on this host", NULL);
 -
 +        /*
 +         * Some features would be enabled by default, but they're disabled
 +         * because this instance of KVM doesn't support them. Test that the
 +         * features are present, and, when enabled, issue further tests.
 +         */
 +        assert_has_feature(qts, "host", "kvm-steal-time");
          assert_has_feature(qts, "host", "sve");
 +
          resp = do_query_no_props(qts, "host");
 +        kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time");
          kvm_supports_sve = resp_get_feature(resp, "sve");
          vls = resp_get_sve_vls(resp);
          qobject_unref(resp);
 +        if (kvm_supports_steal_time) {
 +            /* If we have steal-time then we should be able to toggle it. */
 +            assert_set_feature(qts, "host", "kvm-steal-time", false);
 +            assert_set_feature(qts, "host", "kvm-steal-time", true);
 +        }
 +
          if (kvm_supports_sve) {
              g_assert(vls != 0);
              max_vq = 64 - __builtin_clzll(vls);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
          assert_has_not_feature(qts, "host", "aarch64");
          assert_has_not_feature(qts, "host", "pmu");
          assert_has_not_feature(qts, "host", "sve");
 +        assert_has_not_feature(qts, "host", "kvm-steal-time");
      }
      qtest_quit(qts);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
+[PULL 12/12] target/arm: Make '-cpu max' have a 48-bit PA
-The FRECPX instructions should (like most other floating point operations)
+QEMU supports a 48-bit physical address range, but we don't currently
-honour the FPCR.FZ bit which specifies whether input denormals should
+expose it in the '-cpu max' ID registers (you get the same range as
-be flushed to zero (or FZ16 for the half-precision version).
+Cortex-A57, which is 44 bits).
-We forgot to implement this, which doesn't affect the results (since
-the calculation doesn't actually care about the mantissa bits) but did
+Set the ID_AA64MMFR0.PARange field to indicate 48 bits.
 mean we were failing to set the FPSR.IDC bit.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
+Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
 ---
- target/arm/helper-a64.c | 6 ++++++
+ target/arm/cpu64.c | 4 ++++
-file changed, 6 insertions(+)
+file changed, 4 insertions(+)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/target/arm/cpu64.c
-+++ b/target/arm/helper-a64.c
++++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-         return nan;
+         t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
-     }
+         cpu->isar.id_aa64pfr1 = t;
-+    a = float16_squash_input_denormal(a, fpst);
++        t = cpu->isar.id_aa64mmfr0;
 +        t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
 +        cpu->isar.id_aa64mmfr0 = t;
 +
-     val16 = float16_val(a);
+         t = cpu->isar.id_aa64mmfr1;
-     sbit = 0x8000 & val16;
+         t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
-     exp = extract32(val16, 10, 5);
+         t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
          return nan;
      }
 +    a = float32_squash_input_denormal(a, fpst);
 +
      val32 = float32_val(a);
      sbit = 0x80000000ULL & val32;
      exp = extract32(val32, 23, 8);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
          return nan;
      }
 +    a = float64_squash_input_denormal(a, fpst);
 +
      val64 = float64_val(a);
      sbit = 0x8000000000000000ULL & val64;
      exp = extract64(float64_val(a), 52, 11);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
+Deleted patch
-Add entries to MAINTAINERS to cover the newer MPS2 boards and
-the new devices they use.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
----
- MAINTAINERS | 9 +++++++--
-file changed, 7 insertions(+), 2 deletions(-)
-diff --git a/MAINTAINERS b/MAINTAINERS
-index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
- F: include/hw/timer/cmsdk-apb-timer.h
- F: hw/char/cmsdk-apb-uart.c
- F: include/hw/char/cmsdk-apb-uart.h
-+F: hw/misc/tz-ppc.c
-+F: include/hw/misc/tz-ppc.h
- ARM cores
- M: Peter Maydell <peter.maydell@linaro.org>
-@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
- L: qemu-arm@nongnu.org
- S: Maintained
- F: hw/arm/mps2.c
--F: hw/misc/mps2-scc.c
--F: include/hw/misc/mps2-scc.h
-+F: hw/arm/mps2-tz.c
-+F: hw/misc/mps2-*.c
-+F: include/hw/misc/mps2-*.h
-+F: hw/arm/iotkit.c
-+F: include/hw/arm/iotkit.h
- Musicpal
- M: Jan Kiszka <jan.kiszka@web.de>
---
-.17.1

-[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
+Deleted patch
-From: Paolo Bonzini <pbonzini@redhat.com>
-cpregs_keys is an uint32_t* so the allocation should use uint32_t.
-g_new is even better because it is type-safe.
-Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/gdbstub.c | 3 +--
-file changed, 1 insertion(+), 2 deletions(-)
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/gdbstub.c
-+++ b/target/arm/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
-     RegisterSysregXmlParam param = {cs, s};
-     cpu->dyn_xml.num_cpregs = 0;
--    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
--                                        g_hash_table_size(cpu->cp_regs));
-+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
-     g_string_printf(s, "<?xml version=\"1.0\"?>");
-     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
-     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
---
-.17.1

-[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
+Deleted patch
-Add more detail to the documentation for memory_region_init_iommu()
-and other IOMMU-related functions and data structures.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
----
- include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
-file changed, 95 insertions(+), 10 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
-     IOMMU_ATTR_SPAPR_TCE_FD
- };
-+/**
-+ * IOMMUMemoryRegionClass:
-+ *
-+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
-+ * and provide an implementation of at least the @translate method here
-+ * to handle requests to the memory region. Other methods are optional.
-+ *
-+ * The IOMMU implementation must use the IOMMU notifier infrastructure
-+ * to report whenever mappings are changed, by calling
-+ * memory_region_notify_iommu() (or, if necessary, by calling
-+ * memory_region_notify_one() for each registered notifier).
-+ */
- typedef struct IOMMUMemoryRegionClass {
-     /* private */
-     struct DeviceClass parent_class;
-     /*
--     * Return a TLB entry that contains a given address. Flag should
--     * be the access permission of this translation operation. We can
--     * set flag to IOMMU_NONE to mean that we don't need any
--     * read/write permission checks, like, when for region replay.
-+     * Return a TLB entry that contains a given address.
-+     *
-+     * The IOMMUAccessFlags indicated via @flag are optional and may
-+     * be specified as IOMMU_NONE to indicate that the caller needs
-+     * the full translation information for both reads and writes. If
-+     * the access flags are specified then the IOMMU implementation
-+     * may use this as an optimization, to stop doing a page table
-+     * walk as soon as it knows that the requested permissions are not
-+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
-+     * full page table walk and report the permissions in the returned
-+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
-+     * return different mappings for reads and writes.)
-+     *
-+     * The returned information remains valid while the caller is
-+     * holding the big QEMU lock or is inside an RCU critical section;
-+     * if the caller wishes to cache the mapping beyond that it must
-+     * register an IOMMU notifier so it can invalidate its cached
-+     * information when the IOMMU mapping changes.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @hwaddr: address to be translated within the memory region
-+     * @flag: requested access permissions
-      */
-     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
-                                IOMMUAccessFlags flag);
--    /* Returns minimum supported page size */
-+    /* Returns minimum supported page size in bytes.
-+     * If this method is not provided then the minimum is assumed to
-+     * be TARGET_PAGE_SIZE.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     */
-     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
--    /* Called when IOMMU Notifier flag changed */
-+    /* Called when IOMMU Notifier flag changes (ie when the set of
-+     * events which IOMMU users are requesting notification for changes).
-+     * Optional method -- need not be provided if the IOMMU does not
-+     * need to know exactly which events must be notified.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @old_flags: events which previously needed to be notified
-+     * @new_flags: events which now need to be notified
-+     */
-     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
-                                 IOMMUNotifierFlag old_flags,
-                                 IOMMUNotifierFlag new_flags);
--    /* Set this up to provide customized IOMMU replay function */
-+    /* Called to handle memory_region_iommu_replay().
-+     *
-+     * The default implementation of memory_region_iommu_replay() is to
-+     * call the IOMMU translate method for every page in the address space
-+     * with flag == IOMMU_NONE and then call the notifier if translate
-+     * returns a valid mapping. If this method is implemented then it
-+     * overrides the default behaviour, and must provide the full semantics
-+     * of memory_region_iommu_replay(), by calling @notifier for every
-+     * translation present in the IOMMU.
-+     *
-+     * Optional method -- an IOMMU only needs to provide this method
-+     * if the default is inefficient or produces undesirable side effects.
-+     *
-+     * Note: this is not related to record-and-replay functionality.
-+     */
-     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
--    /* Get IOMMU misc attributes */
--    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
-+    /* Get IOMMU misc attributes. This is an optional method that
-+     * can be used to allow users of the IOMMU to get implementation-specific
-+     * information. The IOMMU implements this method to handle calls
-+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
-+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
-+     * the IOMMU supports. If the method is unimplemented then
-+     * memory_region_iommu_get_attr() will always return -EINVAL.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @attr: attribute being queried
-+     * @data: memory to fill in with the attribute data
-+     *
-+     * Returns 0 on success, or a negative errno; in particular
-+     * returns -EINVAL for unrecognized or unimplemented attribute types.
-+     */
-+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
-                     void *data);
- } IOMMUMemoryRegionClass;
-@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
-  * An IOMMU region translates addresses and forwards accesses to a target
-  * memory region.
-  *
-+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
-+ * @_iommu_mr should be a pointer to enough memory for an instance of
-+ * that subclass, @instance_size is the size of that subclass, and
-+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
-+ * instance of the subclass, and its methods will then be called to handle
-+ * accesses to the memory region. See the documentation of
-+ * #IOMMUMemoryRegionClass for further details.
-+ *
-  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
-  * @instance_size: the IOMMUMemoryRegion subclass instance size
-  * @mrtypename: the type name of the #IOMMUMemoryRegion
-@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
-  * a notifier with the minimum page granularity returned by
-  * mr->iommu_ops->get_page_size().
-  *
-+ * Note: this is not related to record-and-replay functionality.
-+ *
-  * @iommu_mr: the memory region to observe
-  * @n: the notifier to which to replay iommu mappings
-  */
-@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
-  * memory_region_iommu_replay_all: replay existing IOMMU translations
-  * to all the notifiers registered.
-  *
-+ * Note: this is not related to record-and-replay functionality.
-+ *
-  * @iommu_mr: the memory region to observe
-  */
- void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
-@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
-  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
-  * defined on the IOMMU.
-  *
-- * Returns 0 if succeded, error code otherwise.
-+ * Returns 0 on success, or a negative errno otherwise. In particular,
-+ * -EINVAL indicates that the IOMMU does not support the requested
-+ * attribute.
-  *
-  * @iommu_mr: the memory region
-  * @attr: the requested attribute
---
-.17.1

-[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to tb_invalidate_phys_addr().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
----
- include/exec/exec-all.h   | 5 +++--
- accel/tcg/translate-all.c | 2 +-
- exec.c                    | 2 +-
- target/xtensa/op_helper.c | 3 ++-
-files changed, 7 insertions(+), 5 deletions(-)
-diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/exec-all.h
-+++ b/include/exec/exec-all.h
-@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
- void tlb_set_page(CPUState *cpu, target_ulong vaddr,
-                   hwaddr paddr, int prot,
-                   int mmu_idx, target_ulong size);
--void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
-+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
- void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
-                  uintptr_t retaddr);
- #else
-@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
-                                                        uint16_t idxmap)
- {
- }
--static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
-+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
-+                                           MemTxAttrs attrs)
- {
- }
- #endif
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
- }
- #if !defined(CONFIG_USER_ONLY)
--void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
-+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
- {
-     ram_addr_t ram_addr;
-     MemoryRegion *mr;
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
-     if (phys != -1) {
-         /* Locks grabbed by tb_invalidate_phys_addr */
-         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
--                                phys | (pc & ~TARGET_PAGE_MASK));
-+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
-     }
- }
- #endif
-diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/xtensa/op_helper.c
-+++ b/target/xtensa/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
-     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
-             &paddr, &page_size, &access);
-     if (ret == 0) {
--        tb_invalidate_phys_addr(&address_space_memory, paddr);
-+        tb_invalidate_phys_addr(&address_space_memory, paddr,
-+                                MEMTXATTRS_UNSPECIFIED);
-     }
- }
---
-.17.1

-[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_translate()
-and address_space_translate_cached(). Callers either have an
-attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
----
- include/exec/memory.h     |  4 +++-
- accel/tcg/translate-all.c |  2 +-
- exec.c                    | 14 +++++++++-----
- hw/vfio/common.c          |  3 ++-
- memory_ldst.inc.c         | 18 +++++++++---------
- target/riscv/helper.c     |  2 +-
-files changed, 25 insertions(+), 18 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-  * #MemoryRegion.
-  * @len: pointer to length
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
- MemoryRegion *flatview_translate(FlatView *fv,
-                                  hwaddr addr, hwaddr *xlat,
-@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
- static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     hwaddr addr, hwaddr *xlat,
--                                                    hwaddr *len, bool is_write)
-+                                                    hwaddr *len, bool is_write,
-+                                                    MemTxAttrs attrs)
- {
-     return flatview_translate(address_space_to_flatview(as),
-                               addr, xlat, len, is_write);
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
-     hwaddr l = 1;
-     rcu_read_lock();
--    mr = address_space_translate(as, addr, &addr, &l, false);
-+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
-     if (!(memory_region_is_ram(mr)
-           || memory_region_is_romd(mr))) {
-         rcu_read_unlock();
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
-     rcu_read_lock();
-     while (len > 0) {
-         l = len;
--        mr = address_space_translate(as, addr, &addr1, &l, true);
-+        mr = address_space_translate(as, addr, &addr1, &l, true,
-+                                     MEMTXATTRS_UNSPECIFIED);
-         if (!(memory_region_is_ram(mr) ||
-               memory_region_is_romd(mr))) {
-@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
-  */
- static inline MemoryRegion *address_space_translate_cached(
-     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
--    hwaddr *plen, bool is_write)
-+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegionSection section;
-     MemoryRegion *mr;
-@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
-+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
-+                                        MEMTXATTRS_UNSPECIFIED);
-     flatview_read_continue(cache->fv,
-                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
-                            addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
-+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
-+                                        MEMTXATTRS_UNSPECIFIED);
-     flatview_write_continue(cache->fv,
-                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
-                             addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
-     rcu_read_lock();
-     mr = address_space_translate(&address_space_memory,
--                                 phys_addr, &phys_addr, &l, false);
-+                                 phys_addr, &phys_addr, &l, false,
-+                                 MEMTXATTRS_UNSPECIFIED);
-     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
-     rcu_read_unlock();
-diff --git a/hw/vfio/common.c b/hw/vfio/common.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/vfio/common.c
-+++ b/hw/vfio/common.c
-@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
-      */
-     mr = address_space_translate(&address_space_memory,
-                                  iotlb->translated_addr,
--                                 &xlat, &len, writable);
-+                                 &xlat, &len, writable,
-+                                 MEMTXATTRS_UNSPECIFIED);
-     if (!memory_region_is_ram(mr)) {
-         error_report("iommu map to non memory area %"HWADDR_PRIx"",
-                      xlat);
-diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory_ldst.inc.c
-+++ b/memory_ldst.inc.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 4 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 8 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (!IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 2 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 4 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 4 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (!IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
-@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 2 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 8 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-diff --git a/target/riscv/helper.c b/target/riscv/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.c
-+++ b/target/riscv/helper.c
-@@ -XXX,XX +XXX,XX @@ restart:
-                 MemoryRegion *mr;
-                 hwaddr l = sizeof(target_ulong), addr1;
-                 mr = address_space_translate(cs->as, pte_addr,
--                    &addr1, &l, false);
-+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
-                 if (memory_access_is_direct(mr, true)) {
-                     target_ulong *pte_pa =
-                         qemu_map_ram_ptr(mr->ram_block, addr1);
---
-.17.1

-[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_map().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
----
- include/exec/memory.h   | 3 ++-
- include/sysemu/dma.h    | 3 ++-
- exec.c                  | 6 ++++--
- target/ppc/mmu-hash64.c | 3 ++-
-files changed, 10 insertions(+), 5 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
-  * @addr: address within that address space
-  * @plen: pointer to length of buffer; updated on return
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
- void *address_space_map(AddressSpace *as, hwaddr addr,
--                        hwaddr *plen, bool is_write);
-+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
- /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
-  *
-diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/dma.h
-+++ b/include/sysemu/dma.h
-@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
-     hwaddr xlen = *len;
-     void *p;
--    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
-+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
-+                          MEMTXATTRS_UNSPECIFIED);
-     *len = xlen;
-     return p;
- }
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
- void *address_space_map(AddressSpace *as,
-                         hwaddr addr,
-                         hwaddr *plen,
--                        bool is_write)
-+                        bool is_write,
-+                        MemTxAttrs attrs)
- {
-     hwaddr len = *plen;
-     hwaddr l, xlat;
-@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
-                               hwaddr *plen,
-                               int is_write)
- {
--    return address_space_map(&address_space_memory, addr, plen, is_write);
-+    return address_space_map(&address_space_memory, addr, plen, is_write,
-+                             MEMTXATTRS_UNSPECIFIED);
- }
- void cpu_physical_memory_unmap(void *buffer, hwaddr len,
-diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/ppc/mmu-hash64.c
-+++ b/target/ppc/mmu-hash64.c
-@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
-         return NULL;
-     }
--    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
-+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
-+                              MEMTXATTRS_UNSPECIFIED);
-     if (plen < (n * HASH_PTE_SIZE_64)) {
-         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
-     }
---
-.17.1

-[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_extend_translation().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
----
- exec.c | 15 ++++++++++-----
-file changed, 10 insertions(+), 5 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
- static hwaddr
- flatview_extend_translation(FlatView *fv, hwaddr addr,
--                                 hwaddr target_len,
--                                 MemoryRegion *mr, hwaddr base, hwaddr len,
--                                 bool is_write)
-+                            hwaddr target_len,
-+                            MemoryRegion *mr, hwaddr base, hwaddr len,
-+                            bool is_write, MemTxAttrs attrs)
- {
-     hwaddr done = 0;
-     hwaddr xlat;
-@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
-     memory_region_ref(mr);
-     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
--                                             l, is_write);
-+                                        l, is_write, attrs);
-     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
-     rcu_read_unlock();
-@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
-     mr = cache->mrs.mr;
-     memory_region_ref(mr);
-     if (memory_access_is_direct(mr, is_write)) {
-+        /* We don't care about the memory attributes here as we're only
-+         * doing this if we found actual RAM, which behaves the same
-+         * regardless of attributes; so UNSPECIFIED is fine.
-+         */
-         l = flatview_extend_translation(cache->fv, addr, len, mr,
--                                        cache->xlat, l, is_write);
-+                                        cache->xlat, l, is_write,
-+                                        MEMTXATTRS_UNSPECIFIED);
-         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
-     } else {
-         cache->ptr = NULL;
---
-.17.1

-[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to memory_region_access_valid().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-The callsite in flatview_access_valid() is part of a recursive
-loop flatview_access_valid() -> memory_region_access_valid() ->
- subpage_accepts() -> flatview_access_valid(); we make it pass
-MEMTXATTRS_UNSPECIFIED for now, until the next several commits
-have plumbed an attrs parameter through the rest of the loop
-and we can add an attrs parameter to flatview_access_valid().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
----
- include/exec/memory-internal.h | 3 ++-
- exec.c                         | 4 +++-
- hw/s390x/s390-pci-inst.c       | 3 ++-
- memory.c                       | 7 ++++---
-files changed, 11 insertions(+), 6 deletions(-)
-diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory-internal.h
-+++ b/include/exec/memory-internal.h
-@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
- extern const MemoryRegionOps unassigned_mem_ops;
- bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
--                                unsigned size, bool is_write);
-+                                unsigned size, bool is_write,
-+                                MemTxAttrs attrs);
- void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
- AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
--            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
-+            /* When our callers all have attrs we'll pass them through here */
-+            if (!memory_region_access_valid(mr, xlat, l, is_write,
-+                                            MEMTXATTRS_UNSPECIFIED)) {
-                 return false;
-             }
-         }
-diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/s390x/s390-pci-inst.c
-+++ b/hw/s390x/s390-pci-inst.c
-@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
-     mr = s390_get_subregion(mr, offset, len);
-     offset -= mr->addr;
--    if (!memory_region_access_valid(mr, offset, len, true)) {
-+    if (!memory_region_access_valid(mr, offset, len, true,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
-         return 0;
-     }
-diff --git a/memory.c b/memory.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory.c
-+++ b/memory.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
- bool memory_region_access_valid(MemoryRegion *mr,
-                                 hwaddr addr,
-                                 unsigned size,
--                                bool is_write)
-+                                bool is_write,
-+                                MemTxAttrs attrs)
- {
-     int access_size_min, access_size_max;
-     int access_size, i;
-@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
- {
-     MemTxResult r;
--    if (!memory_region_access_valid(mr, addr, size, false)) {
-+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
-         *pval = unassigned_mem_read(mr, addr, size);
-         return MEMTX_DECODE_ERROR;
-     }
-@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
-                                          unsigned size,
-                                          MemTxAttrs attrs)
- {
--    if (!memory_region_access_valid(mr, addr, size, true)) {
-+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
-         unassigned_mem_write(mr, addr, data, size);
-         return MEMTX_DECODE_ERROR;
-     }
---
-.17.1

-[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to the MemoryRegion valid.accepts
-callback. We'll need this for subpage_accepts().
-We could take the approach we used with the read and write
-callbacks and add new a new _with_attrs version, but since there
-are so few implementations of the accepts hook we just change
-them all.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
----
- include/exec/memory.h |  3 ++-
- exec.c                |  9 ++++++---
- hw/hppa/dino.c        |  3 ++-
- hw/nvram/fw_cfg.c     | 12 ++++++++----
- hw/scsi/esp.c         |  3 ++-
- hw/xen/xen_pt_msi.c   |  3 ++-
- memory.c              |  5 +++--
-files changed, 25 insertions(+), 13 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
-          * as a machine check exception).
-          */
-         bool (*accepts)(void *opaque, hwaddr addr,
--                        unsigned size, bool is_write);
-+                        unsigned size, bool is_write,
-+                        MemTxAttrs attrs);
-     } valid;
-     /* Internal implementation constraints: */
-     struct {
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
- }
- static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
--                                 unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return is_write;
- }
-@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
- }
- static bool subpage_accepts(void *opaque, hwaddr addr,
--                            unsigned len, bool is_write)
-+                            unsigned len, bool is_write,
-+                            MemTxAttrs attrs)
- {
-     subpage_t *subpage = opaque;
- #if defined(DEBUG_SUBPAGE)
-@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
- }
- static bool readonly_mem_accepts(void *opaque, hwaddr addr,
--                                 unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return is_write;
- }
-diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/hppa/dino.c
-+++ b/hw/hppa/dino.c
-@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
- }
- static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
--                                unsigned size, bool is_write)
-+                                unsigned size, bool is_write,
-+                                MemTxAttrs attrs)
- {
-     switch (addr) {
-     case DINO_IAR0:
-diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/nvram/fw_cfg.c
-+++ b/hw/nvram/fw_cfg.c
-@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
- }
- static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
--                                  unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
-                          (size == 8 && addr == 0));
- }
- static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
--                                  unsigned size, bool is_write)
-+                                  unsigned size, bool is_write,
-+                                  MemTxAttrs attrs)
- {
-     return addr == 0;
- }
-@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
- }
- static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
--                                 unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return is_write && size == 2;
- }
-@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
- }
- static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
--                                  unsigned size, bool is_write)
-+                              unsigned size, bool is_write,
-+                              MemTxAttrs attrs)
- {
-     return (size == 1) || (is_write && size == 2);
- }
-diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/scsi/esp.c
-+++ b/hw/scsi/esp.c
-@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
- }
- static bool esp_mem_accepts(void *opaque, hwaddr addr,
--                            unsigned size, bool is_write)
-+                            unsigned size, bool is_write,
-+                            MemTxAttrs attrs)
- {
-     return (size == 1) || (is_write && size == 4);
- }
-diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/xen/xen_pt_msi.c
-+++ b/hw/xen/xen_pt_msi.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
- }
- static bool pci_msix_accepts(void *opaque, hwaddr addr,
--                             unsigned size, bool is_write)
-+                             unsigned size, bool is_write,
-+                             MemTxAttrs attrs)
- {
-     return !(addr & (size - 1));
- }
-diff --git a/memory.c b/memory.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory.c
-+++ b/memory.c
-@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
- }
- static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
--                                   unsigned size, bool is_write)
-+                                   unsigned size, bool is_write,
-+                                   MemTxAttrs attrs)
- {
-     return false;
- }
-@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
-     access_size = MAX(MIN(size, access_size_max), access_size_min);
-     for (i = 0; i < size; i += access_size) {
-         if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
--                                    is_write)) {
-+                                    is_write, attrs)) {
-             return false;
-         }
-     }
---
-.17.1

-[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_translate(); all its
-callers now have attrs available.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
----
- include/exec/memory.h |  7 ++++---
- exec.c                | 17 +++++++++--------
-files changed, 13 insertions(+), 11 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-  */
- MemoryRegion *flatview_translate(FlatView *fv,
-                                  hwaddr addr, hwaddr *xlat,
--                                 hwaddr *len, bool is_write);
-+                                 hwaddr *len, bool is_write,
-+                                 MemTxAttrs attrs);
- static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     hwaddr addr, hwaddr *xlat,
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     MemTxAttrs attrs)
- {
-     return flatview_translate(address_space_to_flatview(as),
--                              addr, xlat, len, is_write);
-+                              addr, xlat, len, is_write, attrs);
- }
- /* address_space_access_valid: check for validity of accessing an address
-@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
-             rcu_read_lock();
-             fv = address_space_to_flatview(as);
-             l = len;
--            mr = flatview_translate(fv, addr, &addr1, &l, false);
-+            mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-             if (len == l && memory_access_is_direct(mr, false)) {
-                 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
-                 memcpy(buf, ptr, len);
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ iotlb_fail:
- /* Called from RCU critical section */
- MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
--                                 hwaddr *plen, bool is_write)
-+                                 hwaddr *plen, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     MemoryRegion *mr;
-     MemoryRegionSection section;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
-         }
-         l = len;
--        mr = flatview_translate(fv, addr, &addr1, &l, true);
-+        mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
-     }
-     return result;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
-     MemTxResult result = MEMTX_OK;
-     l = len;
--    mr = flatview_translate(fv, addr, &addr1, &l, true);
-+    mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
-     result = flatview_write_continue(fv, addr, attrs, buf, len,
-                                      addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
-         }
-         l = len;
--        mr = flatview_translate(fv, addr, &addr1, &l, false);
-+        mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-     }
-     return result;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = flatview_translate(fv, addr, &addr1, &l, false);
-+    mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-     return flatview_read_continue(fv, addr, attrs, buf, len,
-                                   addr1, l, mr);
- }
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-     while (len > 0) {
-         l = len;
--        mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-+        mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
-             if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
-@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
-         len = target_len;
-         this_mr = flatview_translate(fv, addr, &xlat,
--                                                   &len, is_write);
-+                                     &len, is_write, attrs);
-         if (this_mr != mr || xlat != base + done) {
-             return done;
-         }
-@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
-     l = len;
-     rcu_read_lock();
-     fv = address_space_to_flatview(as);
--    mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-+    mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
-     if (!memory_access_is_direct(mr, is_write)) {
-         if (atomic_xchg(&bounce.in_use, true)) {
---
-.17.1

-[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_get_iotlb_entry().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
----
- include/exec/memory.h | 2 +-
- exec.c                | 2 +-
- hw/virtio/vhost.c     | 3 ++-
-files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
-  * entry. Should be called from an RCU critical section.
-  */
- IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
--                                            bool is_write);
-+                                            bool is_write, MemTxAttrs attrs);
- /* address_space_translate: translate an address range into an address space
-  * into a MemoryRegion and an address range into that section.  Should be
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
- /* Called from RCU critical section */
- IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
--                                            bool is_write)
-+                                            bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegionSection section;
-     hwaddr xlat, page_mask;
-diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/virtio/vhost.c
-+++ b/hw/virtio/vhost.c
-@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
-     trace_vhost_iotlb_miss(dev, 1);
-     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
--                                          iova, write);
-+                                          iova, write,
-+                                          MEMTXATTRS_UNSPECIFIED);
-     if (iotlb.target_as != NULL) {
-         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
-                                          &uaddr, &len);
---
-.17.1

-[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_do_translate().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
----
- exec.c | 9 ++++++---
-file changed, 6 insertions(+), 3 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ unassigned:
-  * @is_write: whether the translation operation is for write
-  * @is_mmio: whether this can be MMIO, set true if it can
-  * @target_as: the address space targeted by the IOMMU
-+ * @attrs: memory transaction attributes
-  *
-  * This function is called from RCU critical section
-  */
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-                                                  hwaddr *page_mask_out,
-                                                  bool is_write,
-                                                  bool is_mmio,
--                                                 AddressSpace **target_as)
-+                                                 AddressSpace **target_as,
-+                                                 MemTxAttrs attrs)
- {
-     MemoryRegionSection *section;
-     IOMMUMemoryRegion *iommu_mr;
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-      * but page mask.
-      */
-     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
--                                    NULL, &page_mask, is_write, false, &as);
-+                                    NULL, &page_mask, is_write, false, &as,
-+                                    attrs);
-     /* Illegal translation */
-     if (section.mr == &io_mem_unassigned) {
-@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
-     /* This can be MMIO, so setup MMIO bit. */
-     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
--                                    is_write, true, &as);
-+                                    is_write, true, &as, attrs);
-     mr = section.mr;
-     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
---
-.17.1

-[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
+Deleted patch
-Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
-and friends.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
----
- include/migration/vmstate.h | 3 +++
-file changed, 3 insertions(+)
-diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/migration/vmstate.h
-+++ b/include/migration/vmstate.h
-@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
- #define VMSTATE_BOOL_ARRAY(_f, _s, _n)                               \
-     VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
-+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num)                \
-+    VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
-+
- #define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v)                         \
-     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
---
-.17.1

target-arm queue. This has the "plumb txattrs through various
bits of exec.c" patches, and a collection of bug fixes from
various people.

thanks
-- PMM

The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:

Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531

for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm: Honour FPCR.FZ in FRECPX
 * MAINTAINERS: Add entries for newer MPS2 boards and devices
 * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
 * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
   GIC state
 * tcg: Fix helper function vs host abi for float16
 * arm: fix qemu crash on startup with -bios option
 * arm: fix malloc type mismatch
 * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
 * Correct CPACR reset value for v7 cores
 * memory.h: Improve IOMMU related documentation
 * exec: Plumb transaction attributes through various functions in
   preparation for allowing IOMMUs to see them
 * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
 * ARM: ACPI: Fix use-after-free due to memory realloc
 * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

----------------------------------------------------------------
Francisco Iglesias (1):
      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

Igor Mammedov (1):
      arm: fix qemu crash on startup with -bios option

Jan Kiszka (1):
      hw/intc/arm_gicv3: Fix APxR<n> register dispatching

Paolo Bonzini (1):
      arm: fix malloc type mismatch

Peter Maydell (17):
      target/arm: Honour FPCR.FZ in FRECPX
      MAINTAINERS: Add entries for newer MPS2 boards and devices
      Correct CPACR reset value for v7 cores
      memory.h: Improve IOMMU related documentation
      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
      Make address_space_translate{, _cached}() take a MemTxAttrs argument
      Make address_space_map() take a MemTxAttrs argument
      Make address_space_access_valid() take a MemTxAttrs argument
      Make flatview_extend_translation() take a MemTxAttrs argument
      Make memory_region_access_valid() take a MemTxAttrs argument
      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
      Make flatview_access_valid() take a MemTxAttrs argument
      Make flatview_translate() take a MemTxAttrs argument
      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
      Make flatview_do_translate() take a MemTxAttrs argument
      Make address_space_translate_iommu take a MemTxAttrs argument
      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

Richard Henderson (1):
      tcg: Fix helper function vs host abi for float16

Shannon Zhao (3):
      arm_gicv3_kvm: increase clroffset accordingly
      ARM: ACPI: Fix use-after-free due to memory realloc
      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
---
 target/arm/helper-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
         return nan;
     }
 
+    a = float16_squash_input_denormal(a, fpst);
+
     val16 = float16_val(a);
     sbit = 0x8000 & val16;
     exp = extract32(val16, 10, 5);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         return nan;
     }
 
+    a = float32_squash_input_denormal(a, fpst);
+
     val32 = float32_val(a);
     sbit = 0x80000000ULL & val32;
     exp = extract32(val32, 23, 8);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         return nan;
     }
 
+    a = float64_squash_input_denormal(a, fpst);
+
     val64 = float64_val(a);
     sbit = 0x8000000000000000ULL & val64;
     exp = extract64(float64_val(a), 52, 11);
-- 
2.17.1

Add entries to MAINTAINERS to cover the newer MPS2 boards and
the new devices they use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
---
 MAINTAINERS | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
 F: include/hw/timer/cmsdk-apb-timer.h
 F: hw/char/cmsdk-apb-uart.c
 F: include/hw/char/cmsdk-apb-uart.h
+F: hw/misc/tz-ppc.c
+F: include/hw/misc/tz-ppc.h
 
 ARM cores
 M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/mps2.c
-F: hw/misc/mps2-scc.c
-F: include/hw/misc/mps2-scc.h
+F: hw/arm/mps2-tz.c
+F: hw/misc/mps2-*.c
+F: include/hw/misc/mps2-*.h
+F: hw/arm/iotkit.c
+F: include/hw/arm/iotkit.h
 
 Musicpal
 M: Jan Kiszka <jan.kiszka@web.de>
-- 
2.17.1

From: Jan Kiszka <jan.kiszka@siemens.com>

There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.

Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value = cs->ich_apr[grp][regno];
 
     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
     uint64_t value;
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
     GICv3CPUState *cs = icc_cs_from_env(env);
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value;
 
     value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.

Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-stable@nongnu.org
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_kvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
         if (clroffset != 0) {
             reg = 0;
             kvm_gicd_access(s, clroffset, &reg, true);
+            clroffset += 4;
         }
         reg = *gic_bmp_ptr32(bmp, irq);
         kvm_gicd_access(s, offset, &reg, true);
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Depending on the host abi, float16, aka uint16_t, values are
passed and returned either zero-extended in the host register
or with garbage at the top of the host register.

The tcg code generator has so far been assuming garbage, as that
matches the x86 abi, but this is incorrect for other host abis.
Further, target/arm has so far been assuming zero-extended results,
so that it may store the 16-bit value into a 32-bit slot with the
high 16-bits already clear.

Rectify both problems by mapping "f16" in the helper definition
to uint32_t instead of (a typedef for) uint16_t.  This forces
the host compiler to assume garbage in the upper 16 bits on input
and to zero-extend the result on output.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/helper-head.h |  2 +-
 target/arm/helper-a64.c    | 35 +++++++++--------
 target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 3 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_int int
 #define dh_ctype_i64 uint64_t
 #define dh_ctype_s64 int64_t
-#define dh_ctype_f16 float16
+#define dh_ctype_f16 uint32_t
 #define dh_ctype_f32 float32
 #define dh_ctype_f64 float64
 #define dh_ctype_ptr void *
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
     return flags;
 }
 
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
 }
 
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare(x, y, fp_status));
 }
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 #define float64_three make_float64(0x4008000000000000ULL)
 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
     return float64_muladd(a, b, float64_two, 0, fpst);
 }
 
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 }
 
 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
     uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
 #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
 
 #define ADVSIMD_HALFOP(name) \
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
 { \
     float_status *fpst = fpstp; \
     return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
 ADVSIMD_TWOHALFOP(mulx)
 
 /* fused multiply-accumulate */
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
+                                 void *fpstp)
 {
     float_status *fpst = fpstp;
     return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
 
 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare_quiet(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_greater);
 }
 
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 }
 
 /* round to integral */
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
 {
     return float16_round_to_int(x, fp_status);
 }
 
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
 {
     int old_flags = get_float_exception_flags(fp_status), new_flags;
     float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
  * setting the mode appropriately before calling the helper.
  */
 
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
     return float16_to_int16(a, fpst);
 }
 
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
  * Square Root and Reciprocal square root
  */
 
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
 {
     float_status *s = fpstp;
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
 
 /* Integer to float and float to integer conversions */
 
-#define CONV_ITOF(name, fsz, sign) \
-    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
+#define CONV_ITOF(name, ftype, fsz, sign)                           \
+ftype HELPER(name)(uint32_t x, void *fpstp)                         \
+{                                                                   \
+    float_status *fpst = fpstp;                                     \
+    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
 }
 
-#define CONV_FTOI(name, fsz, sign, round) \
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    if (float##fsz##_is_any_nan(x)) { \
-        float_raise(float_flag_invalid, fpst); \
-        return 0; \
-    } \
-    return float##fsz##_to_##sign##int32##round(x, fpst); \
+#define CONV_FTOI(name, ftype, fsz, sign, round)                \
+uint32_t HELPER(name)(ftype x, void *fpstp)                     \
+{                                                               \
+    float_status *fpst = fpstp;                                 \
+    if (float##fsz##_is_any_nan(x)) {                           \
+        float_raise(float_flag_invalid, fpst);                  \
+        return 0;                                               \
+    }                                                           \
+    return float##fsz##_to_##sign##int32##round(x, fpst);       \
 }
 
-#define FLOAT_CONVS(name, p, fsz, sign) \
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
+#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
+    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
+    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
+    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 
-FLOAT_CONVS(si, h, 16, )
-FLOAT_CONVS(si, s, 32, )
-FLOAT_CONVS(si, d, 64, )
-FLOAT_CONVS(ui, h, 16, u)
-FLOAT_CONVS(ui, s, 32, u)
-FLOAT_CONVS(ui, d, 64, u)
+FLOAT_CONVS(si, h, uint32_t, 16, )
+FLOAT_CONVS(si, s, float32, 32, )
+FLOAT_CONVS(si, d, float64, 64, )
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
+FLOAT_CONVS(ui, s, float32, 32, u)
+FLOAT_CONVS(ui, d, float64, 64, u)
 
 #undef CONV_ITOF
 #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
     return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
 }
 
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
 }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
     }
 }
 
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
 }
 
 /* Half precision conversions.  */
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
     g_assert_not_reached();
 }
 
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
     return extract64(estimate, 0, 8) << 44;
 }
 
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
 {
     float_status *s = fpstp;
     float16 f16 = float16_squash_input_denormal(input, s);
-- 
2.17.1

From: Igor Mammedov <imammedo@redhat.com>

When QEMU is started with following CLI
 -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
it crashes with abort at
 accel/kvm/kvm-all.c:2164:
 KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument

Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
arm_gicv3_icc_reset() where the later is called by CPU reset
reset callback.

However commit:
 3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
broke CPU reset callback registration in case

arm_load_kernel()
      ...
      if (!info->kernel_filename || info->firmware_loaded)

branch is taken, i.e. it's sufficient to provide a firmware
or do not provide kernel on CLI to skip cpu reset callback
registration, where before offending commit the callback
has been registered unconditionally.

Fix it by registering the callback right at the beginning of
arm_load_kernel() unconditionally instead of doing it at the end.

NOTE:
 we probably should eliminate that dependency anyways as well as
 separate arch CPU reset parts from arm_load_kernel() into CPU
 itself, but that refactoring that I probably would have to do
 anyways later for CPU hotplug to work.

Reported-by: Auger Eric <eric.auger@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
     static const ARMInsnFixup *primary_loader;
     AddressSpace *as = arm_boot_address_space(cpu, info);
 
+    /* CPU objects (unlike devices) are not automatically reset on system
+     * reset, so we must always register a handler to do so. If we're
+     * actually loading a kernel, the handler is also responsible for
+     * arranging that we start it correctly.
+     */
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+    }
+
     /* The board code is not supposed to set secure_board_setup unless
      * running its code in secure mode is actually possible, and KVM
      * doesn't support secure.
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
         ARM_CPU(cs)->env.boot_info = info;
     }
 
-    /* CPU objects (unlike devices) are not automatically reset on system
-     * reset, so we must always register a handler to do so. If we're
-     * actually loading a kernel, the handler is also responsible for
-     * arranging that we start it correctly.
-     */
-    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
-        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
-    }
-
     if (!info->skip_dtb_autoload && have_dtb(info)) {
         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
             exit(1);
-- 
2.17.1

From: Paolo Bonzini <pbonzini@redhat.com>

cpregs_keys is an uint32_t* so the allocation should use uint32_t.
g_new is even better because it is type-safe.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
     RegisterSysregXmlParam param = {cs, s};
 
     cpu->dyn_xml.num_cpregs = 0;
-    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
-                                        g_hash_table_size(cpu->cp_regs));
+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
-- 
2.17.1

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Coverity found that the string return by 'object_get_canonical_path' was not
being freed at two locations in the model (CID 1391294 and CID 1391293) and
also that a memset was being called with a value greater than the max of a byte
on the second argument (CID 1391286). This patch corrects this by adding the
freeing of the strings and also changing to memset to zero instead on
descriptor unaligned errors.

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx-zdma.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/xlnx-zdma.c
+++ b/hw/dma/xlnx-zdma.c
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
         qemu_log_mask(LOG_GUEST_ERROR,
                       "zdma: unaligned descriptor at %" PRIx64,
                       addr);
-        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
         s->error = true;
         return false;
     }
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr, value);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return;
-- 
2.17.1

In commit f0aff255700 we made cpacr_write() enforce that some CPACR
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
we forgot to also update the register's reset value. The effect
was that (a) a guest that read CPACR on reset would not see ones in
the RAO bits, and (b) if you did a migration before the guest did
a write to the CPACR then the migration would fail because the
destination would enforce the RAO bits and then complain that they
didn't match the zero value from the source.

Implement reset for the CPACR using a custom reset function
that just calls cpacr_write(), to avoid having to duplicate
the logic for which bits are RAO.

This bug would affect migration for TCG CPUs which are ARMv7
with VFP but without one of Neon or VFPv3.

Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     env->cp15.cpacr_el1 = value;
 }
 
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /* Call cpacr_write() so that we reset with the correct RAO bits set
+     * for our CPU features.
+     */
+    cpacr_write(env, ri, 0);
+}
+
 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
-      .resetvalue = 0, .writefn = cpacr_write },
+      .resetfn = cpacr_reset, .writefn = cpacr_write },
     REGINFO_SENTINEL
 };
 
-- 
2.17.1

Add more detail to the documentation for memory_region_init_iommu()
and other IOMMU-related functions and data structures.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
---
 include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 95 insertions(+), 10 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
     IOMMU_ATTR_SPAPR_TCE_FD
 };
 
+/**
+ * IOMMUMemoryRegionClass:
+ *
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
+ * and provide an implementation of at least the @translate method here
+ * to handle requests to the memory region. Other methods are optional.
+ *
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
+ * to report whenever mappings are changed, by calling
+ * memory_region_notify_iommu() (or, if necessary, by calling
+ * memory_region_notify_one() for each registered notifier).
+ */
 typedef struct IOMMUMemoryRegionClass {
     /* private */
     struct DeviceClass parent_class;
 
     /*
-     * Return a TLB entry that contains a given address. Flag should
-     * be the access permission of this translation operation. We can
-     * set flag to IOMMU_NONE to mean that we don't need any
-     * read/write permission checks, like, when for region replay.
+     * Return a TLB entry that contains a given address.
+     *
+     * The IOMMUAccessFlags indicated via @flag are optional and may
+     * be specified as IOMMU_NONE to indicate that the caller needs
+     * the full translation information for both reads and writes. If
+     * the access flags are specified then the IOMMU implementation
+     * may use this as an optimization, to stop doing a page table
+     * walk as soon as it knows that the requested permissions are not
+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
+     * full page table walk and report the permissions in the returned
+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
+     * return different mappings for reads and writes.)
+     *
+     * The returned information remains valid while the caller is
+     * holding the big QEMU lock or is inside an RCU critical section;
+     * if the caller wishes to cache the mapping beyond that it must
+     * register an IOMMU notifier so it can invalidate its cached
+     * information when the IOMMU mapping changes.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @hwaddr: address to be translated within the memory region
+     * @flag: requested access permissions
      */
     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
                                IOMMUAccessFlags flag);
-    /* Returns minimum supported page size */
+    /* Returns minimum supported page size in bytes.
+     * If this method is not provided then the minimum is assumed to
+     * be TARGET_PAGE_SIZE.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     */
     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
-    /* Called when IOMMU Notifier flag changed */
+    /* Called when IOMMU Notifier flag changes (ie when the set of
+     * events which IOMMU users are requesting notification for changes).
+     * Optional method -- need not be provided if the IOMMU does not
+     * need to know exactly which events must be notified.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @old_flags: events which previously needed to be notified
+     * @new_flags: events which now need to be notified
+     */
     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
                                 IOMMUNotifierFlag old_flags,
                                 IOMMUNotifierFlag new_flags);
-    /* Set this up to provide customized IOMMU replay function */
+    /* Called to handle memory_region_iommu_replay().
+     *
+     * The default implementation of memory_region_iommu_replay() is to
+     * call the IOMMU translate method for every page in the address space
+     * with flag == IOMMU_NONE and then call the notifier if translate
+     * returns a valid mapping. If this method is implemented then it
+     * overrides the default behaviour, and must provide the full semantics
+     * of memory_region_iommu_replay(), by calling @notifier for every
+     * translation present in the IOMMU.
+     *
+     * Optional method -- an IOMMU only needs to provide this method
+     * if the default is inefficient or produces undesirable side effects.
+     *
+     * Note: this is not related to record-and-replay functionality.
+     */
     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
 
-    /* Get IOMMU misc attributes */
-    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
+    /* Get IOMMU misc attributes. This is an optional method that
+     * can be used to allow users of the IOMMU to get implementation-specific
+     * information. The IOMMU implements this method to handle calls
+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
+     * the IOMMU supports. If the method is unimplemented then
+     * memory_region_iommu_get_attr() will always return -EINVAL.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @attr: attribute being queried
+     * @data: memory to fill in with the attribute data
+     *
+     * Returns 0 on success, or a negative errno; in particular
+     * returns -EINVAL for unrecognized or unimplemented attribute types.
+     */
+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
                     void *data);
 } IOMMUMemoryRegionClass;
 
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
  * An IOMMU region translates addresses and forwards accesses to a target
  * memory region.
  *
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
+ * @_iommu_mr should be a pointer to enough memory for an instance of
+ * that subclass, @instance_size is the size of that subclass, and
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
+ * instance of the subclass, and its methods will then be called to handle
+ * accesses to the memory region. See the documentation of
+ * #IOMMUMemoryRegionClass for further details.
+ *
  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
  * @instance_size: the IOMMUMemoryRegion subclass instance size
  * @mrtypename: the type name of the #IOMMUMemoryRegion
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
  * a notifier with the minimum page granularity returned by
  * mr->iommu_ops->get_page_size().
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  * @n: the notifier to which to replay iommu mappings
  */
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
  * memory_region_iommu_replay_all: replay existing IOMMU translations
  * to all the notifiers registered.
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  */
 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
  * defined on the IOMMU.
  *
- * Returns 0 if succeded, error code otherwise.
+ * Returns 0 on success, or a negative errno otherwise. In particular,
+ * -EINVAL indicates that the IOMMU does not support the requested
+ * attribute.
  *
  * @iommu_mr: the memory region
  * @attr: the requested attribute
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
---
 include/exec/exec-all.h   | 5 +++--
 accel/tcg/translate-all.c | 2 +-
 exec.c                    | 2 +-
 target/xtensa/op_helper.c | 3 ++-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                   hwaddr paddr, int prot,
                   int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
                  uintptr_t retaddr);
 #else
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                        uint16_t idxmap)
 {
 }
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
+                                           MemTxAttrs attrs)
 {
 }
 #endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 {
     ram_addr_t ram_addr;
     MemoryRegion *mr;
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
     if (phys != -1) {
         /* Locks grabbed by tb_invalidate_phys_addr */
         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
-                                phys | (pc & ~TARGET_PAGE_MASK));
+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
     }
 }
 #endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
             &paddr, &page_size, &access);
     if (ret == 0) {
-        tb_invalidate_phys_addr(&address_space_memory, paddr);
+        tb_invalidate_phys_addr(&address_space_memory, paddr,
+                                MEMTXATTRS_UNSPECIFIED);
     }
 }
 
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate()
and address_space_translate_cached(). Callers either have an
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
---
 include/exec/memory.h     |  4 +++-
 accel/tcg/translate-all.c |  2 +-
 exec.c                    | 14 +++++++++-----
 hw/vfio/common.c          |  3 ++-
 memory_ldst.inc.c         | 18 +++++++++---------
 target/riscv/helper.c     |  2 +-
 6 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
  * #MemoryRegion.
  * @len: pointer to length
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 MemoryRegion *flatview_translate(FlatView *fv,
                                  hwaddr addr, hwaddr *xlat,
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
 
 static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                     hwaddr addr, hwaddr *xlat,
-                                                    hwaddr *len, bool is_write)
+                                                    hwaddr *len, bool is_write,
+                                                    MemTxAttrs attrs)
 {
     return flatview_translate(address_space_to_flatview(as),
                               addr, xlat, len, is_write);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
     hwaddr l = 1;
 
     rcu_read_lock();
-    mr = address_space_translate(as, addr, &addr, &l, false);
+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
     if (!(memory_region_is_ram(mr)
           || memory_region_is_romd(mr))) {
         rcu_read_unlock();
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
     rcu_read_lock();
     while (len > 0) {
         l = len;
-        mr = address_space_translate(as, addr, &addr1, &l, true);
+        mr = address_space_translate(as, addr, &addr1, &l, true,
+                                     MEMTXATTRS_UNSPECIFIED);
 
         if (!(memory_region_is_ram(mr) ||
               memory_region_is_romd(mr))) {
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
  */
 static inline MemoryRegion *address_space_translate_cached(
     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
-    hwaddr *plen, bool is_write)
+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     MemoryRegion *mr;
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_read_continue(cache->fv,
                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                            addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_write_continue(cache->fv,
                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                             addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
 
     rcu_read_lock();
     mr = address_space_translate(&address_space_memory,
-                                 phys_addr, &phys_addr, &l, false);
+                                 phys_addr, &phys_addr, &l, false,
+                                 MEMTXATTRS_UNSPECIFIED);
 
     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
     rcu_read_unlock();
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
      */
     mr = address_space_translate(&address_space_memory,
                                  iotlb->translated_addr,
-                                 &xlat, &len, writable);
+                                 &xlat, &len, writable,
+                                 MEMTXATTRS_UNSPECIFIED);
     if (!memory_region_is_ram(mr)) {
         error_report("iommu map to non memory area %"HWADDR_PRIx"",
                      xlat);
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 4 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 8 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (!IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 2 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (!IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 2 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 8 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -XXX,XX +XXX,XX @@ restart:
                 MemoryRegion *mr;
                 hwaddr l = sizeof(target_ulong), addr1;
                 mr = address_space_translate(cs->as, pte_addr,
-                    &addr1, &l, false);
+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
                 if (memory_access_is_direct(mr, true)) {
                     target_ulong *pte_pa =
                         qemu_map_ram_ptr(mr->ram_block, addr1);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_map().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
---
 include/exec/memory.h   | 3 ++-
 include/sysemu/dma.h    | 3 ++-
 exec.c                  | 6 ++++--
 target/ppc/mmu-hash64.c | 3 ++-
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
  * @addr: address within that address space
  * @plen: pointer to length of buffer; updated on return
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 void *address_space_map(AddressSpace *as, hwaddr addr,
-                        hwaddr *plen, bool is_write);
+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
 
 /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
     hwaddr xlen = *len;
     void *p;
 
-    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
+                          MEMTXATTRS_UNSPECIFIED);
     *len = xlen;
     return p;
 }
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
 void *address_space_map(AddressSpace *as,
                         hwaddr addr,
                         hwaddr *plen,
-                        bool is_write)
+                        bool is_write,
+                        MemTxAttrs attrs)
 {
     hwaddr len = *plen;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
                               hwaddr *plen,
                               int is_write)
 {
-    return address_space_map(&address_space_memory, addr, plen, is_write);
+    return address_space_map(&address_space_memory, addr, plen, is_write,
+                             MEMTXATTRS_UNSPECIFIED);
 }
 
 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
         return NULL;
     }
 
-    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
+                              MEMTXATTRS_UNSPECIFIED);
     if (plen < (n * HASH_PTE_SIZE_64)) {
         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
---
 include/exec/memory.h      | 4 +++-
 include/sysemu/dma.h       | 3 ++-
 exec.c                     | 3 ++-
 target/s390x/diag.c        | 6 ++++--
 target/s390x/excp_helper.c | 3 ++-
 target/s390x/mmu_helper.c  | 3 ++-
 target/s390x/sigp.c        | 3 ++-
 7 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
  * @addr: address within that address space
  * @len: length of the area to be checked
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
+                                bool is_write, MemTxAttrs attrs);
 
 /* address_space_map: map a physical memory region into a host virtual address
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
                                     DMADirection dir)
 {
     return address_space_access_valid(as, addr, len,
-                                      dir == DMA_DIRECTION_FROM_DEVICE);
+                                      dir == DMA_DIRECTION_FROM_DEVICE,
+                                      MEMTXATTRS_UNSPECIFIED);
 }
 
 static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
 }
 
 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-                                int len, bool is_write)
+                                int len, bool is_write,
+                                MemTxAttrs attrs)
 {
     FlatView *fv;
     bool result;
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/diag.c
+++ b/target/s390x/diag.c
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), false)) {
+                                        sizeof(IplParameterBlock), false,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
@@ -XXX,XX +XXX,XX @@ out:
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), true)) {
+                                        sizeof(IplParameterBlock), true,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
 
     /* check out of RAM access */
     if (!address_space_access_valid(&address_space_memory, raddr,
-                                    TARGET_PAGE_SIZE, rw)) {
+                                    TARGET_PAGE_SIZE, rw,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                 (uint64_t)raddr, (uint64_t)ram_size);
         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
             return ret;
         }
         if (!address_space_access_valid(&address_space_memory, pages[i],
-                                        TARGET_PAGE_SIZE, is_write)) {
+                                        TARGET_PAGE_SIZE, is_write,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
             return -EFAULT;
         }
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
     cpu_synchronize_state(cs);
 
     if (!address_space_access_valid(&address_space_memory, addr,
-                                    sizeof(struct LowCore), false)) {
+                                    sizeof(struct LowCore), false,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
         return;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_extend_translation().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
 static hwaddr
 flatview_extend_translation(FlatView *fv, hwaddr addr,
-                                 hwaddr target_len,
-                                 MemoryRegion *mr, hwaddr base, hwaddr len,
-                                 bool is_write)
+                            hwaddr target_len,
+                            MemoryRegion *mr, hwaddr base, hwaddr len,
+                            bool is_write, MemTxAttrs attrs)
 {
     hwaddr done = 0;
     hwaddr xlat;
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
 
     memory_region_ref(mr);
     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
-                                             l, is_write);
+                                        l, is_write, attrs);
     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
     rcu_read_unlock();
 
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
     mr = cache->mrs.mr;
     memory_region_ref(mr);
     if (memory_access_is_direct(mr, is_write)) {
+        /* We don't care about the memory attributes here as we're only
+         * doing this if we found actual RAM, which behaves the same
+         * regardless of attributes; so UNSPECIFIED is fine.
+         */
         l = flatview_extend_translation(cache->fv, addr, len, mr,
-                                        cache->xlat, l, is_write);
+                                        cache->xlat, l, is_write,
+                                        MEMTXATTRS_UNSPECIFIED);
         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
     } else {
         cache->ptr = NULL;
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to memory_region_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

The callsite in flatview_access_valid() is part of a recursive
loop flatview_access_valid() -> memory_region_access_valid() ->
 subpage_accepts() -> flatview_access_valid(); we make it pass
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
have plumbed an attrs parameter through the rest of the loop
and we can add an attrs parameter to flatview_access_valid().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
---
 include/exec/memory-internal.h | 3 ++-
 exec.c                         | 4 +++-
 hw/s390x/s390-pci-inst.c       | 3 ++-
 memory.c                       | 7 ++++---
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
 extern const MemoryRegionOps unassigned_mem_ops;
 
 bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
-                                unsigned size, bool is_write);
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs);
 
 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
+            /* When our callers all have attrs we'll pass them through here */
+            if (!memory_region_access_valid(mr, xlat, l, is_write,
+                                            MEMTXATTRS_UNSPECIFIED)) {
                 return false;
             }
         }
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
     mr = s390_get_subregion(mr, offset, len);
     offset -= mr->addr;
 
-    if (!memory_region_access_valid(mr, offset, len, true)) {
+    if (!memory_region_access_valid(mr, offset, len, true,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
         return 0;
     }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
 bool memory_region_access_valid(MemoryRegion *mr,
                                 hwaddr addr,
                                 unsigned size,
-                                bool is_write)
+                                bool is_write,
+                                MemTxAttrs attrs)
 {
     int access_size_min, access_size_max;
     int access_size, i;
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
 {
     MemTxResult r;
 
-    if (!memory_region_access_valid(mr, addr, size, false)) {
+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
         *pval = unassigned_mem_read(mr, addr, size);
         return MEMTX_DECODE_ERROR;
     }
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
                                          unsigned size,
                                          MemTxAttrs attrs)
 {
-    if (!memory_region_access_valid(mr, addr, size, true)) {
+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
         unassigned_mem_write(mr, addr, data, size);
         return MEMTX_DECODE_ERROR;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
callback. We'll need this for subpage_accepts().

We could take the approach we used with the read and write
callbacks and add new a new _with_attrs version, but since there
are so few implementations of the accepts hook we just change
them all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
---
 include/exec/memory.h |  3 ++-
 exec.c                |  9 ++++++---
 hw/hppa/dino.c        |  3 ++-
 hw/nvram/fw_cfg.c     | 12 ++++++++----
 hw/scsi/esp.c         |  3 ++-
 hw/xen/xen_pt_msi.c   |  3 ++-
 memory.c              |  5 +++--
 7 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
          * as a machine check exception).
          */
         bool (*accepts)(void *opaque, hwaddr addr,
-                        unsigned size, bool is_write);
+                        unsigned size, bool is_write,
+                        MemTxAttrs attrs);
     } valid;
     /* Internal implementation constraints: */
     struct {
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
 }
 
 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
 }
 
 static bool subpage_accepts(void *opaque, hwaddr addr,
-                            unsigned len, bool is_write)
+                            unsigned len, bool is_write,
+                            MemTxAttrs attrs)
 {
     subpage_t *subpage = opaque;
 #if defined(DEBUG_SUBPAGE)
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/hppa/dino.c
+++ b/hw/hppa/dino.c
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
 }
 
 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
-                                unsigned size, bool is_write)
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs)
 {
     switch (addr) {
     case DINO_IAR0:
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
                          (size == 8 && addr == 0));
 }
 
 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                  unsigned size, bool is_write,
+                                  MemTxAttrs attrs)
 {
     return addr == 0;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write && size == 2;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                              unsigned size, bool is_write,
+                              MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 2);
 }
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 }
 
 static bool esp_mem_accepts(void *opaque, hwaddr addr,
-                            unsigned size, bool is_write)
+                            unsigned size, bool is_write,
+                            MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 4);
 }
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/xen/xen_pt_msi.c
+++ b/hw/xen/xen_pt_msi.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
 }
 
 static bool pci_msix_accepts(void *opaque, hwaddr addr,
-                             unsigned size, bool is_write)
+                             unsigned size, bool is_write,
+                             MemTxAttrs attrs)
 {
     return !(addr & (size - 1));
 }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
-                                   unsigned size, bool is_write)
+                                   unsigned size, bool is_write,
+                                   MemTxAttrs attrs)
 {
     return false;
 }
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
     access_size = MAX(MIN(size, access_size_max), access_size_min);
     for (i = 0; i < size; i += access_size) {
         if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
-                                    is_write)) {
+                                    is_write, attrs)) {
             return false;
         }
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_access_valid().
Its callers now all have an attrs value to hand, so we can
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
                                   const uint8_t *buf, int len);
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write);
+                                  bool is_write, MemTxAttrs attrs);
 
 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
                                 unsigned len, MemTxAttrs attrs)
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
 #endif
 
     return flatview_access_valid(subpage->fv, addr + subpage->base,
-                                 len, is_write);
+                                 len, is_write, attrs);
 }
 
 static const MemoryRegionOps subpage_ops = {
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
 }
 
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write)
+                                  bool is_write, MemTxAttrs attrs)
 {
     MemoryRegion *mr;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            /* When our callers all have attrs we'll pass them through here */
-            if (!memory_region_access_valid(mr, xlat, l, is_write,
-                                            MEMTXATTRS_UNSPECIFIED)) {
+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
                 return false;
             }
         }
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
     rcu_read_lock();
     fv = address_space_to_flatview(as);
-    result = flatview_access_valid(fv, addr, len, is_write);
+    result = flatview_access_valid(fv, addr, len, is_write, attrs);
     rcu_read_unlock();
     return result;
 }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_translate(); all its
callers now have attrs available.

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_get_iotlb_entry().

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
  * entry. Should be called from an RCU critical section.
  */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write);
+                                            bool is_write, MemTxAttrs attrs);
 
 /* address_space_translate: translate an address range into an address space
  * into a MemoryRegion and an address range into that section.  Should be
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
 
 /* Called from RCU critical section */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write)
+                                            bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     hwaddr xlat, page_mask;
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
     trace_vhost_iotlb_miss(dev, 1);
 
     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
-                                          iova, write);
+                                          iova, write,
+                                          MEMTXATTRS_UNSPECIFIED);
     if (iotlb.target_as != NULL) {
         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
                                          &uaddr, &len);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_do_translate().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ unassigned:
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: memory transaction attributes
  *
  * This function is called from RCU critical section
  */
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
                                                  hwaddr *page_mask_out,
                                                  bool is_write,
                                                  bool is_mmio,
-                                                 AddressSpace **target_as)
+                                                 AddressSpace **target_as,
+                                                 MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     IOMMUMemoryRegion *iommu_mr;
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
      * but page mask.
      */
     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
-                                    NULL, &page_mask, is_write, false, &as);
+                                    NULL, &page_mask, is_write, false, &as,
+                                    attrs);
 
     /* Illegal translation */
     if (section.mr == &io_mem_unassigned) {
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
 
     /* This can be MMIO, so setup MMIO bit. */
     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
-                                    is_write, true, &as);
+                                    is_write, true, &as, attrs);
     mr = section.mr;
 
     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate_iommu().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: transaction attributes
  *
  * This function is called from RCU critical section.  It is the common
  * part of flatview_do_translate and address_space_translate_cached.
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
                                                          hwaddr *page_mask_out,
                                                          bool is_write,
                                                          bool is_mmio,
-                                                         AddressSpace **target_as)
+                                                         AddressSpace **target_as,
+                                                         MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     hwaddr page_mask = (hwaddr)-1;
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
         return address_space_translate_iommu(iommu_mr, xlat,
                                              plen_out, page_mask_out,
                                              is_write, is_mmio,
-                                             target_as);
+                                             target_as, attrs);
     }
     if (page_mask_out) {
         /* Not behind an IOMMU, use default page size. */
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
 
     section = address_space_translate_iommu(iommu_mr, xlat, plen,
                                             NULL, is_write, true,
-                                            &target_as);
+                                            &target_as, attrs);
     return section.mr;
 }
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. So previous
pointer could not be used any more. It must update the pointer and use
the new one.

Also, previous codes wrongly use le32 conversion of iort->node_offset
for subsequent computations that will result incorrect value if host is
not litlle endian. So use the non-converted one instead.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     AcpiIortItsGroup *its;
     AcpiIortTable *iort;
     AcpiIortSmmu3 *smmu;
-    size_t node_size, iort_length, smmu_offset = 0;
+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
     AcpiIortRC *rc;
 
     iort = acpi_data_push(table_data, sizeof(*iort));
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 
     iort_length = sizeof(*iort);
     iort->node_count = cpu_to_le32(nb_nodes);
-    iort->node_offset = cpu_to_le32(sizeof(*iort));
+    /*
+     * Use a copy in case table_data->data moves during acpi_data_push
+     * operations.
+     */
+    iort_node_offset = sizeof(*iort);
+    iort->node_offset = cpu_to_le32(iort_node_offset);
 
     /* ITS group node */
     node_size =  sizeof(*its) + sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         int irq =  vms->irqmap[VIRT_SMMU];
 
         /* SMMUv3 node */
-        smmu_offset = iort->node_offset + node_size;
+        smmu_offset = iort_node_offset + node_size;
         node_size = sizeof(*smmu) + sizeof(*idmap);
         iort_length += node_size;
         smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->id_count = cpu_to_le32(0xFFFF);
         idmap->output_base = 0;
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
     /* Root Complex Node */
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->output_reference = cpu_to_le32(smmu_offset);
     } else {
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
+    /*
+     * Update the pointer address in case table_data->data moves during above
+     * acpi_data_push operations.
+     */
+    iort = (AcpiIortTable *)(table_data->data + iort_start);
     iort->length = cpu_to_le32(iort_length);
 
     build_header(linker, table_data, (void *)(table_data->data + iort_start),
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
initialize global capability variables. If we call kvm_init_irq_routing in
GIC realize function, previous allocated memory will leak.

Fix this by deleting the unnecessary call.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic_kvm.c   | 1 -
 hw/intc/arm_gicv3_kvm.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
-- 
2.17.1

The following changes since commit 6eeea6725a70e6fcb5abba0764496bdab07ddfb3:

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-10-06' into staging (2020-10-06 21:13:34 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201008

for you to fetch changes up to ba118c26e16a97e6ff6de8184057d3420ce16a23:

target/arm: Make '-cpu max' have a 48-bit PA (2020-10-08 15:24:32 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
 * hw/arm/fsl-imx25: Fix a typo
 * hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
 * hw/arm/sbsa-ref : allocate IRQs for SMMUv3
 * hw/char/bcm2835_aux: Allow less than 32-bit accesses
 * hw/arm/virt: Implement kvm-steal-time
 * target/arm: Make '-cpu max' have a 48-bit PA

----------------------------------------------------------------
Andrew Jones (6):
      linux headers: sync to 5.9-rc7
      target/arm/kvm: Make uncalled stubs explicitly unreachable
      hw/arm/virt: Move post cpu realize check into its own function
      hw/arm/virt: Move kvm pmu setup to virt_cpu_post_init
      tests/qtest: Restore aarch64 arm-cpu-features test
      hw/arm/virt: Implement kvm-steal-time

Graeme Gregory (2):
      hw/arm/sbsa-ref : Fix SMMUv3 Initialisation
      hw/arm/sbsa-ref : allocate IRQs for SMMUv3

Peter Maydell (1):
      target/arm: Make '-cpu max' have a 48-bit PA

Philippe Mathieu-Daudé (3):
      hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer
      hw/arm/fsl-imx25: Fix a typo
      hw/char/bcm2835_aux: Allow less than 32-bit accesses

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Fix integer handling issues handling issue reported by Coverity:

hw/ssi/npcm7xx_fiu.c: 162 in npcm7xx_fiu_flash_read()
  >>>     CID 1432730:  Integer handling issues  (NEGATIVE_RETURNS)
  >>>     "npcm7xx_fiu_cs_index(fiu, f)" is passed to a parameter that cannot be negative.
  162         npcm7xx_fiu_select(fiu, npcm7xx_fiu_cs_index(fiu, f));

hw/ssi/npcm7xx_fiu.c: 221 in npcm7xx_fiu_flash_write()
  218         cs_id = npcm7xx_fiu_cs_index(fiu, f);
  219         trace_npcm7xx_fiu_flash_write(DEVICE(fiu)->canonical_path, cs_id, addr,
  220                                       size, v);
  >>>     CID 1432729:  Integer handling issues  (NEGATIVE_RETURNS)
  >>>     "cs_id" is passed to a parameter that cannot be negative.
  221         npcm7xx_fiu_select(fiu, cs_id);

Since the index of the flash can not be negative, return an
unsigned type.

Reported-by: Coverity (CID 1432729 & 1432730: NEGATIVE_RETURNS)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20200919132435.310527-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/npcm7xx_fiu.c | 12 ++++++------
 hw/ssi/trace-events  |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/npcm7xx_fiu.c
+++ b/hw/ssi/npcm7xx_fiu.c
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxFIURegister {
  * Returns the index of flash in the fiu->flash array. This corresponds to the
  * chip select ID of the flash.
  */
-static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
+static unsigned npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu,
+                                     NPCM7xxFIUFlash *flash)
 {
     int index = flash - fiu->flash;
 
@@ -XXX,XX +XXX,XX @@ static int npcm7xx_fiu_cs_index(NPCM7xxFIUState *fiu, NPCM7xxFIUFlash *flash)
 }
 
 /* Assert the chip select specified in the UMA Control/Status Register. */
-static void npcm7xx_fiu_select(NPCM7xxFIUState *s, int cs_id)
+static void npcm7xx_fiu_select(NPCM7xxFIUState *s, unsigned cs_id)
 {
     trace_npcm7xx_fiu_select(DEVICE(s)->canonical_path, cs_id);
 
     if (cs_id < s->cs_count) {
         qemu_irq_lower(s->cs_lines[cs_id]);
+        s->active_cs = cs_id;
     } else {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: UMA to CS%d; this module has only %d chip selects",
                       DEVICE(s)->canonical_path, cs_id, s->cs_count);
-        cs_id = -1;
+        s->active_cs = -1;
     }
-
-    s->active_cs = cs_id;
 }
 
 /* Deassert the currently active chip select. */
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_flash_write(void *opaque, hwaddr addr, uint64_t v,
     NPCM7xxFIUFlash *f = opaque;
     NPCM7xxFIUState *fiu = f->fiu;
     uint32_t dwr_cfg;
-    int cs_id;
+    unsigned cs_id;
     int i;
 
     if (fiu->active_cs != -1) {
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_deselect(const char *id, int cs) "%s deselect CS%d"
 npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
 npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
-npcm7xx_fiu_flash_write(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
+npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201002080935.1660005-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx25.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX25State {
  * 0xBB00_0000 0xBB00_0FFF 4 Kbytes     NAND flash main area buffer
  * 0xBB00_1000 0xBB00_11FF 512 B        NAND flash spare area buffer
  * 0xBB00_1200 0xBB00_1DFF 3 Kbytes     Reserved
- * 0xBB00_1E00 0xBB00_1FFF 512 B        NAND flash control regisers
+ * 0xBB00_1E00 0xBB00_1FFF 512 B        NAND flash control registers
  * 0xBB01_2000 0xBFFF_FFFF 96 Mbytes (minus 8 Kbytes) Reserved
  * 0xC000_0000 0xFFFF_FFFF 1024 Mbytes  Reserved
  */
-- 
2.20.1

From: Graeme Gregory <graeme@nuviainc.com>

SMMUv3 has an error in a previous patch where an i was transposed to a 1
meaning interrupts would not have been correctly assigned to the SMMUv3
instance.

Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state")
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20201007100732.4103790-2-graeme@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const SBSAMachineState *sms, PCIBus *bus)
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
     for (i = 0; i < NUM_SMMU_IRQS; i++) {
         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
-                           qdev_get_gpio_in(sms->gic, irq + 1));
+                           qdev_get_gpio_in(sms->gic, irq + i));
     }
 }
 
-- 
2.20.1

From: Graeme Gregory <graeme@nuviainc.com>

Original commit did not allocate IRQs for the SMMUv3 in the irqmap
effectively using irq 0->3 (shared with other devices). Assuming
original intent was to allocate unique IRQs then add an allocation
to the irqmap.

Fixes: e9fdf453240 ("hw/arm: Add arm SBSA reference machine, devices part")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20201007100732.4103790-3-graeme@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
     [SBSA_SECURE_UART_MM] = 9,
     [SBSA_AHCI] = 10,
     [SBSA_EHCI] = 11,
+    [SBSA_SMMU] = 12, /* ... to 15 */
 };
 
 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The "BCM2835 ARM Peripherals" datasheet [*] chapter 2
("Auxiliaries: UART1 & SPI1, SPI2"), list the register
sizes as 3/8/16/32 bits. We assume this means this
peripheral allows 8-bit accesses.

This was not an issue until commit 5d971f9e67 which reverted
("memory: accept mismatching sizes in memory_region_access_valid").

The model is implemented as 32-bit accesses (see commit 97398d900c,
all registers are 32-bit) so replace MemoryRegionOps.valid as
MemoryRegionOps.impl, and re-introduce MemoryRegionOps.valid
with a 8/32-bit range.

[*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf

Fixes: 97398d900c ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201002181032.1899463-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/bcm2835_aux.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/bcm2835_aux.c
+++ b/hw/char/bcm2835_aux.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps bcm2835_aux_ops = {
     .read = bcm2835_aux_read,
     .write = bcm2835_aux_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid.min_access_size = 4,
+    .impl.min_access_size = 4,
+    .impl.max_access_size = 4,
+    .valid.min_access_size = 1,
     .valid.max_access_size = 4,
 };
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Update against Linux 5.9-rc7.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20201001061718.101915-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-headers/linux/kvm.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
 #define KVM_VM_PPC_HV 1
 #define KVM_VM_PPC_PR 2
 
-/* on MIPS, 0 forces trap & emulate, 1 forces VZ ASE */
-#define KVM_VM_MIPS_TE		0
+/* on MIPS, 0 indicates auto, 1 forces VZ ASE, 2 forces trap & emulate */
+#define KVM_VM_MIPS_AUTO	0
 #define KVM_VM_MIPS_VZ		1
+#define KVM_VM_MIPS_TE		2
 
 #define KVM_S390_SIE_PAGE_OFFSET 1
 
@@ -XXX,XX +XXX,XX @@ struct kvm_ppc_resize_hpt {
 #define KVM_CAP_LAST_CPU 184
 #define KVM_CAP_SMALLER_MAXPHYADDR 185
 #define KVM_CAP_S390_DIAG318 186
+#define KVM_CAP_STEAL_TIME 187
 
 #ifdef KVM_CAP_IRQ_ROUTING
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

When we compile without KVM support !defined(CONFIG_KVM) we generate
stubs for functions that the linker will still encounter. Sometimes
these stubs can be executed safely and are placed in paths where they
get executed with or without KVM. Other functions should never be
called without KVM. Those functions should be guarded by kvm_enabled(),
but should also be robust to refactoring mistakes. Putting a
g_assert_not_reached() in the function should help. Additionally,
the g_assert_not_reached() calls may actually help the linker remove
some code.

We remove the stubs for kvm_arm_get/put_virtual_time(), as they aren't
necessary at all - the only caller is in kvm.c

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20201001061718.101915-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h | 51 +++++++++++++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 19 deletions(-)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
 
 #else
 
-static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
-{
-    /*
-     * This should never actually be called in the "not KVM" case,
-     * but set up the fields to indicate an error anyway.
-     */
-    cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
-    cpu->host_cpu_probe_failed = true;
-}
-
-static inline void kvm_arm_add_vcpu_properties(Object *obj) {}
-
+/*
+ * It's safe to call these functions without KVM support.
+ * They should either do nothing or return "not supported".
+ */
 static inline bool kvm_arm_aarch32_supported(void)
 {
     return false;
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
     return false;
 }
 
+/*
+ * These functions should never actually be called without KVM support.
+ */
+static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
+{
+    g_assert_not_reached();
+}
+
+static inline void kvm_arm_add_vcpu_properties(Object *obj)
+{
+    g_assert_not_reached();
+}
+
 static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
 {
-    return -ENOENT;
+    g_assert_not_reached();
 }
 
 static inline int kvm_arm_vgic_probe(void)
 {
-    return 0;
+    g_assert_not_reached();
 }
 
-static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {}
-static inline void kvm_arm_pmu_init(CPUState *cs) {}
+static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
+{
+    g_assert_not_reached();
+}
 
-static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {}
+static inline void kvm_arm_pmu_init(CPUState *cs)
+{
+    g_assert_not_reached();
+}
+
+static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
+{
+    g_assert_not_reached();
+}
 
-static inline void kvm_arm_get_virtual_time(CPUState *cs) {}
-static inline void kvm_arm_put_virtual_time(CPUState *cs) {}
 #endif
 
 static inline const char *gic_class_name(void)
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

We'll add more to this new function in coming patches so we also
state the gic must be created and call it below create_gic().

No functional change intended.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20201001061718.101915-4-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 43 +++++++++++++++++++++++++++----------------
 1 file changed, 27 insertions(+), 16 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
     }
 }
 
+/*
+ * virt_cpu_post_init() must be called after the CPUs have
+ * been realized and the GIC has been created.
+ */
+static void virt_cpu_post_init(VirtMachineState *vms)
+{
+    bool aarch64;
+
+    aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
+
+    if (!kvm_enabled()) {
+        if (aarch64 && vms->highmem) {
+            int requested_pa_size = 64 - clz64(vms->highest_gpa);
+            int pamax = arm_pamax(ARM_CPU(first_cpu));
+
+            if (pamax < requested_pa_size) {
+                error_report("VCPU supports less PA bits (%d) than "
+                             "requested by the memory map (%d)",
+                             pamax, requested_pa_size);
+                exit(1);
+            }
+        }
+    }
+}
+
 static void machvirt_init(MachineState *machine)
 {
     VirtMachineState *vms = VIRT_MACHINE(machine);
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
     fdt_add_timer_nodes(vms);
     fdt_add_cpu_nodes(vms);
 
-   if (!kvm_enabled()) {
-        ARMCPU *cpu = ARM_CPU(first_cpu);
-        bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
-
-        if (aarch64 && vms->highmem) {
-            int requested_pa_size, pamax = arm_pamax(cpu);
-
-            requested_pa_size = 64 - clz64(vms->highest_gpa);
-            if (pamax < requested_pa_size) {
-                error_report("VCPU supports less PA bits (%d) than requested "
-                            "by the memory map (%d)", pamax, requested_pa_size);
-                exit(1);
-            }
-        }
-    }
-
     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
                                 machine->ram);
     if (machine->device_memory) {
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
 
     create_gic(vms);
 
+    virt_cpu_post_init(vms);
+
     fdt_add_pmu_nodes(vms);
 
     create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

Move the KVM PMU setup part of fdt_add_pmu_nodes() to
virt_cpu_post_init(), which is a more appropriate location. Now
fdt_add_pmu_nodes() is also named more appropriately, because it
no longer does anything but fdt node creation.

No functional change intended.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20201001061718.101915-5-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 34 ++++++++++++++++++----------------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
 
 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
 {
-    CPUState *cpu;
-    ARMCPU *armcpu;
+    ARMCPU *armcpu = ARM_CPU(first_cpu);
     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
 
-    CPU_FOREACH(cpu) {
-        armcpu = ARM_CPU(cpu);
-        if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
-            return;
-        }
-        if (kvm_enabled()) {
-            if (kvm_irqchip_in_kernel()) {
-                kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
-            }
-            kvm_arm_pmu_init(cpu);
-        }
+    if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
+        assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
+        return;
     }
 
     if (vms->gic_version == VIRT_GIC_VERSION_2) {
@@ -XXX,XX +XXX,XX @@ static void fdt_add_pmu_nodes(const VirtMachineState *vms)
                              (1 << vms->smp_cpus) - 1);
     }
 
-    armcpu = ARM_CPU(qemu_get_cpu(0));
     qemu_fdt_add_subnode(vms->fdt, "/pmu");
     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
         const char compat[] = "arm,armv8-pmuv3";
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
  */
 static void virt_cpu_post_init(VirtMachineState *vms)
 {
-    bool aarch64;
+    bool aarch64, pmu;
+    CPUState *cpu;
 
     aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
+    pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
 
-    if (!kvm_enabled()) {
+    if (kvm_enabled()) {
+        CPU_FOREACH(cpu) {
+            if (pmu) {
+                assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
+                if (kvm_irqchip_in_kernel()) {
+                    kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
+                }
+                kvm_arm_pmu_init(cpu);
+            }
+        }
+    } else {
         if (aarch64 && vms->highmem) {
             int requested_pa_size = 64 - clz64(vms->highest_gpa);
             int pamax = arm_pamax(ARM_CPU(first_cpu));
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

arm-cpu-features got dropped from the AArch64 tests during the meson
conversion shuffle.

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20201001061718.101915-6-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
   (cpu != 'arm' ? ['bios-tables-test'] : []) +                                                  \
   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) +        \
   (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) +  \
-  ['numa-test',
+  ['arm-cpu-features',
+   'numa-test',
    'boot-serial-test',
    'migration-test']
 
-- 
2.20.1

From: Andrew Jones <drjones@redhat.com>

We add the kvm-steal-time CPU property and implement it for machvirt.
A tiny bit of refactoring was also done to allow pmu and pvtime to
use the same vcpu device helper functions.

Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 20201001061718.101915-7-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/cpu-features.rst | 11 ++++++
 include/hw/arm/virt.h            |  5 +++
 target/arm/cpu.h                 |  4 ++
 target/arm/kvm_arm.h             | 43 +++++++++++++++++++++
 hw/arm/virt.c                    | 43 +++++++++++++++++++--
 target/arm/cpu.c                 |  8 ++++
 target/arm/kvm.c                 | 16 ++++++++
 target/arm/kvm64.c               | 64 +++++++++++++++++++++++++++++---
 target/arm/monitor.c             |  2 +-
 tests/qtest/arm-cpu-features.c   | 25 +++++++++++--
 10 files changed, 208 insertions(+), 13 deletions(-)

diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/cpu-features.rst
+++ b/docs/system/arm/cpu-features.rst
@@ -XXX,XX +XXX,XX @@ the list of KVM VCPU features and their descriptions.
                            adjustment, also restoring the legacy (pre-5.0)
                            behavior.
 
+  kvm-steal-time           Since v5.2, kvm-steal-time is enabled by
+                           default when KVM is enabled, the feature is
+                           supported, and the guest is 64-bit.
+
+                           When kvm-steal-time is enabled a 64-bit guest
+                           can account for time its CPUs were not running
+                           due to the host not scheduling the corresponding
+                           VCPU threads.  The accounting statistics may
+                           influence the guest scheduler behavior and/or be
+                           exposed to the guest userspace.
+
 SVE CPU Properties
 ==================
 
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 
 #define PPI(irq) ((irq) + 16)
 
+/* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */
+#define PVTIME_SIZE_PER_CPU 64
+
 enum {
     VIRT_FLASH,
     VIRT_MEM,
@@ -XXX,XX +XXX,XX @@ enum {
     VIRT_PCDIMM_ACPI,
     VIRT_ACPI_GED,
     VIRT_NVDIMM_ACPI,
+    VIRT_PVTIME,
     VIRT_LOWMEMMAP_LAST,
 };
 
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
     bool no_highmem_ecam;
     bool no_ged;   /* Machines < 4.2 has no support for ACPI GED device */
     bool kvm_no_adjvtime;
+    bool no_kvm_steal_time;
     bool acpi_expose_flash;
 };
 
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/registerfields.h"
 #include "cpu-qom.h"
 #include "exec/cpu-defs.h"
+#include "qapi/qapi-types-common.h"
 
 /* ARM processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     bool kvm_vtime_dirty;
     uint64_t kvm_vtime;
 
+    /* KVM steal time */
+    OnOffAuto kvm_steal_time;
+
     /* Uniprocessor system with MP extensions */
     bool mp_is_up;
 
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
  */
 void kvm_arm_add_vcpu_properties(Object *obj);
 
+/**
+ * kvm_arm_steal_time_finalize:
+ * @cpu: ARMCPU for which to finalize kvm-steal-time
+ * @errp: Pointer to Error* for error propagation
+ *
+ * Validate the kvm-steal-time property selection and set its default
+ * based on KVM support and guest configuration.
+ */
+void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp);
+
+/**
+ * kvm_arm_steal_time_supported:
+ *
+ * Returns: true if KVM can enable steal time reporting
+ * and false otherwise.
+ */
+bool kvm_arm_steal_time_supported(void);
+
 /**
  * kvm_arm_aarch32_supported:
  *
@@ -XXX,XX +XXX,XX @@ int kvm_arm_vgic_probe(void);
 
 void kvm_arm_pmu_set_irq(CPUState *cs, int irq);
 void kvm_arm_pmu_init(CPUState *cs);
+
+/**
+ * kvm_arm_pvtime_init:
+ * @cs: CPUState
+ * @ipa: Per-vcpu guest physical base address of the pvtime structures
+ *
+ * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa.
+ */
+void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa);
+
 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level);
 
 #else
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_sve_supported(void)
     return false;
 }
 
+static inline bool kvm_arm_steal_time_supported(void)
+{
+    return false;
+}
+
 /*
  * These functions should never actually be called without KVM support.
  */
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_pmu_init(CPUState *cs)
     g_assert_not_reached();
 }
 
+static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
+{
+    g_assert_not_reached();
+}
+
+static inline void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
+{
+    g_assert_not_reached();
+}
+
 static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
 {
     g_assert_not_reached();
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
     [VIRT_PCDIMM_ACPI] =        { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
     [VIRT_ACPI_GED] =           { 0x09080000, ACPI_GED_EVT_SEL_LEN },
     [VIRT_NVDIMM_ACPI] =        { 0x09090000, NVDIMM_ACPI_IO_LEN},
+    [VIRT_PVTIME] =             { 0x090a0000, 0x00010000 },
     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
  * virt_cpu_post_init() must be called after the CPUs have
  * been realized and the GIC has been created.
  */
-static void virt_cpu_post_init(VirtMachineState *vms)
+static void virt_cpu_post_init(VirtMachineState *vms, int max_cpus,
+                               MemoryRegion *sysmem)
 {
-    bool aarch64, pmu;
+    bool aarch64, pmu, steal_time;
     CPUState *cpu;
 
     aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
     pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
+    steal_time = object_property_get_bool(OBJECT(first_cpu),
+                                          "kvm-steal-time", NULL);
 
     if (kvm_enabled()) {
+        hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
+        hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
+
+        if (steal_time) {
+            MemoryRegion *pvtime = g_new(MemoryRegion, 1);
+            hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
+
+            /* The memory region size must be a multiple of host page size. */
+            pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
+
+            if (pvtime_size > pvtime_reg_size) {
+                error_report("pvtime requires a %ld byte memory region for "
+                             "%d CPUs, but only %ld has been reserved",
+                             pvtime_size, max_cpus, pvtime_reg_size);
+                exit(1);
+            }
+
+            memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
+            memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
+        }
+
         CPU_FOREACH(cpu) {
             if (pmu) {
                 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
@@ -XXX,XX +XXX,XX @@ static void virt_cpu_post_init(VirtMachineState *vms)
                 }
                 kvm_arm_pmu_init(cpu);
             }
+            if (steal_time) {
+                kvm_arm_pvtime_init(cpu, pvtime_reg_base +
+                                         cpu->cpu_index * PVTIME_SIZE_PER_CPU);
+            }
         }
     } else {
         if (aarch64 && vms->highmem) {
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
             object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
         }
 
+        if (vmc->no_kvm_steal_time &&
+            object_property_find(cpuobj, "kvm-steal-time")) {
+            object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
+        }
+
         if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
             object_property_set_bool(cpuobj, "pmu", false, NULL);
         }
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
 
     create_gic(vms);
 
-    virt_cpu_post_init(vms);
+    virt_cpu_post_init(vms, possible_cpus->len, sysmem);
 
     fdt_add_pmu_nodes(vms);
 
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2)
 
 static void virt_machine_5_1_options(MachineClass *mc)
 {
+    VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
     virt_machine_5_2_options(mc);
     compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
+    vmc->no_kvm_steal_time = true;
 }
 DEFINE_VIRT_MACHINE(5, 1)
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
             return;
         }
     }
+
+    if (kvm_enabled()) {
+        kvm_arm_steal_time_finalize(cpu, &local_err);
+        if (local_err != NULL) {
+            error_propagate(errp, local_err);
+            return;
+        }
+    }
 }
 
 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_no_adjvtime_set(Object *obj, bool value, Error **errp)
     ARM_CPU(obj)->kvm_adjvtime = !value;
 }
 
+static bool kvm_steal_time_get(Object *obj, Error **errp)
+{
+    return ARM_CPU(obj)->kvm_steal_time != ON_OFF_AUTO_OFF;
+}
+
+static void kvm_steal_time_set(Object *obj, bool value, Error **errp)
+{
+    ARM_CPU(obj)->kvm_steal_time = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
+}
+
 /* KVM VCPU properties should be prefixed with "kvm-". */
 void kvm_arm_add_vcpu_properties(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj)
                                         "the virtual counter. VM stopped time "
                                         "will be counted.");
     }
+
+    cpu->kvm_steal_time = ON_OFF_AUTO_AUTO;
+    object_property_add_bool(obj, "kvm-steal-time", kvm_steal_time_get,
+                             kvm_steal_time_set);
+    object_property_set_description(obj, "kvm-steal-time",
+                                    "Set off to disable KVM steal time.");
 }
 
 bool kvm_arm_pmu_supported(void)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
 #include <linux/kvm.h>
 
 #include "qemu-common.h"
+#include "qapi/error.h"
 #include "cpu.h"
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
     return NULL;
 }
 
-static bool kvm_arm_pmu_set_attr(CPUState *cs, struct kvm_device_attr *attr)
+static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *attr,
+                                    const char *name)
 {
     int err;
 
     err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr);
     if (err != 0) {
-        error_report("PMU: KVM_HAS_DEVICE_ATTR: %s", strerror(-err));
+        error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err));
         return false;
     }
 
     err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr);
     if (err != 0) {
-        error_report("PMU: KVM_SET_DEVICE_ATTR: %s", strerror(-err));
+        error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err));
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
     if (!ARM_CPU(cs)->has_pmu) {
         return;
     }
-    if (!kvm_arm_pmu_set_attr(cs, &attr)) {
+    if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
         error_report("failed to init PMU");
         abort();
     }
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
     if (!ARM_CPU(cs)->has_pmu) {
         return;
     }
-    if (!kvm_arm_pmu_set_attr(cs, &attr)) {
+    if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) {
         error_report("failed to set irq for PMU");
         abort();
     }
 }
 
+void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
+{
+    struct kvm_device_attr attr = {
+        .group = KVM_ARM_VCPU_PVTIME_CTRL,
+        .attr = KVM_ARM_VCPU_PVTIME_IPA,
+        .addr = (uint64_t)&ipa,
+    };
+
+    if (ARM_CPU(cs)->kvm_steal_time == ON_OFF_AUTO_OFF) {
+        return;
+    }
+    if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) {
+        error_report("failed to init PVTIME IPA");
+        abort();
+    }
+}
+
 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
 {
     uint64_t ret;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     return true;
 }
 
+void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
+{
+    bool has_steal_time = kvm_arm_steal_time_supported();
+
+    if (cpu->kvm_steal_time == ON_OFF_AUTO_AUTO) {
+        if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+            cpu->kvm_steal_time = ON_OFF_AUTO_OFF;
+        } else {
+            cpu->kvm_steal_time = ON_OFF_AUTO_ON;
+        }
+    } else if (cpu->kvm_steal_time == ON_OFF_AUTO_ON) {
+        if (!has_steal_time) {
+            error_setg(errp, "'kvm-steal-time' cannot be enabled "
+                             "on this host");
+            return;
+        } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+            /*
+             * DEN0057A chapter 2 says "This specification only covers
+             * systems in which the Execution state of the hypervisor
+             * as well as EL1 of virtual machines is AArch64.". And,
+             * to ensure that, the smc/hvc calls are only specified as
+             * smc64/hvc64.
+             */
+            error_setg(errp, "'kvm-steal-time' cannot be enabled "
+                             "for AArch32 guests");
+            return;
+        }
+    }
+}
+
 bool kvm_arm_aarch32_supported(void)
 {
     return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT);
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_sve_supported(void)
     return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE);
 }
 
+bool kvm_arm_steal_time_supported(void)
+{
+    return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
+}
+
 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1);
 
 void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map)
diff --git a/target/arm/monitor.c b/target/arm/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/monitor.c
+++ b/target/arm/monitor.c
@@ -XXX,XX +XXX,XX @@ static const char *cpu_model_advertised_features[] = {
     "sve128", "sve256", "sve384", "sve512",
     "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280",
     "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048",
-    "kvm-no-adjvtime",
+    "kvm-no-adjvtime", "kvm-steal-time",
     NULL
 };
 
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data)
     assert_set_feature(qts, "max", "pmu", true);
 
     assert_has_not_feature(qts, "max", "kvm-no-adjvtime");
+    assert_has_not_feature(qts, "max", "kvm-steal-time");
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
         assert_has_feature_enabled(qts, "max", "aarch64");
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
     assert_set_feature(qts, "host", "kvm-no-adjvtime", false);
 
     if (g_str_equal(qtest_get_arch(), "aarch64")) {
+        bool kvm_supports_steal_time;
         bool kvm_supports_sve;
         char max_name[8], name[8];
         uint32_t max_vq, vq;
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         QDict *resp;
         char *error;
 
+        assert_error(qts, "cortex-a15",
+            "We cannot guarantee the CPU type 'cortex-a15' works "
+            "with KVM on this host", NULL);
+
         assert_has_feature_enabled(qts, "host", "aarch64");
 
         /* Enabling and disabling pmu should always work. */
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         assert_set_feature(qts, "host", "pmu", false);
         assert_set_feature(qts, "host", "pmu", true);
 
-        assert_error(qts, "cortex-a15",
-            "We cannot guarantee the CPU type 'cortex-a15' works "
-            "with KVM on this host", NULL);
-
+        /*
+         * Some features would be enabled by default, but they're disabled
+         * because this instance of KVM doesn't support them. Test that the
+         * features are present, and, when enabled, issue further tests.
+         */
+        assert_has_feature(qts, "host", "kvm-steal-time");
         assert_has_feature(qts, "host", "sve");
+
         resp = do_query_no_props(qts, "host");
+        kvm_supports_steal_time = resp_get_feature(resp, "kvm-steal-time");
         kvm_supports_sve = resp_get_feature(resp, "sve");
         vls = resp_get_sve_vls(resp);
         qobject_unref(resp);
 
+        if (kvm_supports_steal_time) {
+            /* If we have steal-time then we should be able to toggle it. */
+            assert_set_feature(qts, "host", "kvm-steal-time", false);
+            assert_set_feature(qts, "host", "kvm-steal-time", true);
+        }
+
         if (kvm_supports_sve) {
             g_assert(vls != 0);
             max_vq = 64 - __builtin_clzll(vls);
@@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data)
         assert_has_not_feature(qts, "host", "aarch64");
         assert_has_not_feature(qts, "host", "pmu");
         assert_has_not_feature(qts, "host", "sve");
+        assert_has_not_feature(qts, "host", "kvm-steal-time");
     }
 
     qtest_quit(qts);
-- 
2.20.1

QEMU supports a 48-bit physical address range, but we don't currently
expose it in the '-cpu max' ID registers (you get the same range as
Cortex-A57, which is 44 bits).

Set the ID_AA64MMFR0.PARange field to indicate 48 bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201001160116.18095-1-peter.maydell@linaro.org
---
 target/arm/cpu64.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
         cpu->isar.id_aa64pfr1 = t;
 
+        t = cpu->isar.id_aa64mmfr0;
+        t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
+        cpu->isar.id_aa64mmfr0 = t;
+
         t = cpu->isar.id_aa64mmfr1;
         t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
         t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
-- 
2.20.1