Series comparison

-[Qemu-devel] [PULL 00/25] target-arm queue
+[PULL 00/11] target-arm queue
-target-arm queue. This has the "plumb txattrs through various
+Last handful of arm patches before softfreeze...
 bits of exec.c" patches, and a collection of bug fixes from
 various people.
-thanks
+The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
 -- PMM
+  Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +0000)
 The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
   Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200317
-for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
+for you to fetch changes up to e88d3671e3bbd59d385838a4101ea19cdcf47309:
-  KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
+  hw/arm/pxa2xx: Do not wire up OHCI for PXA255 (2020-03-17 11:36:48 +0000)
 ----------------------------------------------------------------
-target-arm queue:
+target-arm:
- * target/arm: Honour FPCR.FZ in FRECPX
+ * hw/arm/pxa2xx: Do not wire up OHCI for PXA255
- * MAINTAINERS: Add entries for newer MPS2 boards and devices
+ * aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
- * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+ * m25p80: Improve command handling for Jedec and unsupported commands
- * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
+ * hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
-   GIC state
+ * hw/arm/fsl-imx6, imx6ul: Wire up USB controllers
- * tcg: Fix helper function vs host abi for float16
+ * hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
  * arm: fix qemu crash on startup with -bios option
  * arm: fix malloc type mismatch
  * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
  * Correct CPACR reset value for v7 cores
  * memory.h: Improve IOMMU related documentation
  * exec: Plumb transaction attributes through various functions in
    preparation for allowing IOMMUs to see them
  * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
  * ARM: ACPI: Fix use-after-free due to memory realloc
  * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
 ----------------------------------------------------------------
-Francisco Iglesias (1):
+Chen Qun (1):
-      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+      hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
-Igor Mammedov (1):
+Guenter Roeck (10):
-      arm: fix qemu crash on startup with -bios option
+      hw/usb: Add basic i.MX USB Phy support
       hw/arm/fsl-imx6ul: Fix USB interrupt numbers
       hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
       hw/arm/fsl-imx6ul: Wire up USB controllers
       hw/arm/fsl-imx6: Wire up USB controllers
       m25p80: Convert to support tracing
       m25p80: Improve command handling for Jedec commands
       m25p80: Improve command handling for unsupported commands
       aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
       hw/arm/pxa2xx: Do not wire up OHCI for PXA255
-Jan Kiszka (1):
+ hw/usb/Makefile.objs         |   2 +
-      hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+ include/hw/arm/fsl-imx6.h    |   6 ++
  include/hw/arm/fsl-imx6ul.h  |  16 ++-
  include/hw/usb/imx-usb-phy.h |  53 ++++++++++
  hw/arm/fsl-imx6.c            |  36 +++++++
  hw/arm/fsl-imx6ul.c          |  49 ++++++++++
  hw/arm/pxa2xx.c              |   3 -
  hw/block/m25p80.c            |  58 +++++------
  hw/net/imx_fec.c             |   6 +-
  hw/ssi/aspeed_smc.c          |   2 +-
  hw/usb/imx-usb-phy.c         | 225 +++++++++++++++++++++++++++++++++++++++++++
  MAINTAINERS                  |   2 +
  hw/arm/Kconfig               |   1 +
  hw/block/trace-events        |  16 +++
  hw/usb/Kconfig               |   5 +
 files changed, 444 insertions(+), 36 deletions(-)
  create mode 100644 include/hw/usb/imx-usb-phy.h
  create mode 100644 hw/usb/imx-usb-phy.c
-Paolo Bonzini (1):
-      arm: fix malloc type mismatch
-Peter Maydell (17):
-      target/arm: Honour FPCR.FZ in FRECPX
-      MAINTAINERS: Add entries for newer MPS2 boards and devices
-      Correct CPACR reset value for v7 cores
-      memory.h: Improve IOMMU related documentation
-      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
-      Make address_space_translate{, _cached}() take a MemTxAttrs argument
-      Make address_space_map() take a MemTxAttrs argument
-      Make address_space_access_valid() take a MemTxAttrs argument
-      Make flatview_extend_translation() take a MemTxAttrs argument
-      Make memory_region_access_valid() take a MemTxAttrs argument
-      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
-      Make flatview_access_valid() take a MemTxAttrs argument
-      Make flatview_translate() take a MemTxAttrs argument
-      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
-      Make flatview_do_translate() take a MemTxAttrs argument
-      Make address_space_translate_iommu take a MemTxAttrs argument
-      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
-Richard Henderson (1):
-      tcg: Fix helper function vs host abi for float16
-Shannon Zhao (3):
-      arm_gicv3_kvm: increase clroffset accordingly
-      ARM: ACPI: Fix use-after-free due to memory realloc
-      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
- include/exec/exec-all.h        |   5 +-
- include/exec/helper-head.h     |   2 +-
- include/exec/memory-internal.h |   3 +-
- include/exec/memory.h          | 128 +++++++++++++++++++++++++++++++++++------
- include/migration/vmstate.h    |   3 +
- include/sysemu/dma.h           |   6 +-
- accel/tcg/translate-all.c      |   4 +-
- exec.c                         |  95 ++++++++++++++++++------------
- hw/arm/boot.c                  |  18 +++---
- hw/arm/virt-acpi-build.c       |  20 +++++--
- hw/dma/xlnx-zdma.c             |  10 +++-
- hw/hppa/dino.c                 |   3 +-
- hw/intc/arm_gic_kvm.c          |   1 -
- hw/intc/arm_gicv3_cpuif.c      |  12 ++--
- hw/intc/arm_gicv3_kvm.c        |   2 +-
- hw/nvram/fw_cfg.c              |  12 ++--
- hw/s390x/s390-pci-inst.c       |   3 +-
- hw/scsi/esp.c                  |   3 +-
- hw/vfio/common.c               |   3 +-
- hw/virtio/vhost.c              |   3 +-
- hw/xen/xen_pt_msi.c            |   3 +-
- memory.c                       |  12 ++--
- memory_ldst.inc.c              |  18 +++---
- target/arm/gdbstub.c           |   3 +-
- target/arm/helper-a64.c        |  41 +++++++------
- target/arm/helper.c            |  90 ++++++++++++++++-------------
- target/ppc/mmu-hash64.c        |   3 +-
- target/riscv/helper.c          |   2 +-
- target/s390x/diag.c            |   6 +-
- target/s390x/excp_helper.c     |   3 +-
- target/s390x/mmu_helper.c      |   3 +-
- target/s390x/sigp.c            |   3 +-
- target/xtensa/op_helper.c      |   3 +-
- MAINTAINERS                    |   9 ++-
-files changed, 353 insertions(+), 182 deletions(-)

-[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
+[PULL 01/11] hw/usb: Add basic i.MX USB Phy support
-Add entries to MAINTAINERS to cover the newer MPS2 boards and
+From: Guenter Roeck <linux@roeck-us.net>
-the new devices they use.
+Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
 and i.MX7 SoCs.
 The only support really needed - at least to boot Linux - is support
 for soft reset, which needs to reset various registers to their initial
 value. Otherwise, just record register values.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 20200313014551.12554-2-linux@roeck-us.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
 ---
- MAINTAINERS | 9 +++++++--
+ hw/usb/Makefile.objs         |   2 +
-file changed, 7 insertions(+), 2 deletions(-)
+ include/hw/usb/imx-usb-phy.h |  53 +++++++++
+ hw/usb/imx-usb-phy.c         | 225 +++++++++++++++++++++++++++++++++++
  MAINTAINERS                  |   2 +
  hw/arm/Kconfig               |   1 +
  hw/usb/Kconfig               |   5 +
 files changed, 288 insertions(+)
  create mode 100644 include/hw/usb/imx-usb-phy.h
  create mode 100644 hw/usb/imx-usb-phy.c
 diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/Makefile.objs
 +++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XEN) += xen-usb.o
  xen-usb.o-cflags := $(LIBUSB_CFLAGS)
  xen-usb.o-libs := $(LIBUSB_LIBS)
  endif
 +
 +common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o
 diff --git a/include/hw/usb/imx-usb-phy.h b/include/hw/usb/imx-usb-phy.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/usb/imx-usb-phy.h
@@ -XXX,XX +XXX,XX @@
 +#ifndef IMX_USB_PHY_H
 +#define IMX_USB_PHY_H
 +
 +#include "hw/sysbus.h"
 +#include "qemu/bitops.h"
 +
 +enum IMXUsbPhyRegisters {
 +    USBPHY_PWD,
 +    USBPHY_PWD_SET,
 +    USBPHY_PWD_CLR,
 +    USBPHY_PWD_TOG,
 +    USBPHY_TX,
 +    USBPHY_TX_SET,
 +    USBPHY_TX_CLR,
 +    USBPHY_TX_TOG,
 +    USBPHY_RX,
 +    USBPHY_RX_SET,
 +    USBPHY_RX_CLR,
 +    USBPHY_RX_TOG,
 +    USBPHY_CTRL,
 +    USBPHY_CTRL_SET,
 +    USBPHY_CTRL_CLR,
 +    USBPHY_CTRL_TOG,
 +    USBPHY_STATUS,
 +    USBPHY_DEBUG = 0x14,
 +    USBPHY_DEBUG_SET,
 +    USBPHY_DEBUG_CLR,
 +    USBPHY_DEBUG_TOG,
 +    USBPHY_DEBUG0_STATUS,
 +    USBPHY_DEBUG1 = 0x1c,
 +    USBPHY_DEBUG1_SET,
 +    USBPHY_DEBUG1_CLR,
 +    USBPHY_DEBUG1_TOG,
 +    USBPHY_VERSION,
 +    USBPHY_MAX
 +};
 +
 +#define USBPHY_CTRL_SFTRST BIT(31)
 +
 +#define TYPE_IMX_USBPHY "imx.usbphy"
 +#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
 +
 +typedef struct IMXUSBPHYState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion iomem;
 +
 +    uint32_t usbphy[USBPHY_MAX];
 +} IMXUSBPHYState;
 +
 +#endif /* IMX_USB_PHY_H */
 diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/usb/imx-usb-phy.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * i.MX USB PHY
 + *
 + * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + * We need to implement basic reset control in the PHY control register.
 + * For everything else, it is sufficient to set whatever is written.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/usb/imx-usb-phy.h"
 +#include "migration/vmstate.h"
 +#include "qemu/log.h"
 +#include "qemu/module.h"
 +
 +static const VMStateDescription vmstate_imx_usbphy = {
 +    .name = TYPE_IMX_USBPHY,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void imx_usbphy_softreset(IMXUSBPHYState *s)
 +{
 +    s->usbphy[USBPHY_PWD] = 0x001e1c00;
 +    s->usbphy[USBPHY_TX] = 0x10060607;
 +    s->usbphy[USBPHY_RX] = 0x00000000;
 +    s->usbphy[USBPHY_CTRL] = 0xc0200000;
 +}
 +
 +static void imx_usbphy_reset(DeviceState *dev)
 +{
 +    IMXUSBPHYState *s = IMX_USBPHY(dev);
 +
 +    s->usbphy[USBPHY_STATUS] = 0x00000000;
 +    s->usbphy[USBPHY_DEBUG] = 0x7f180000;
 +    s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
 +    s->usbphy[USBPHY_DEBUG1] = 0x00001000;
 +    s->usbphy[USBPHY_VERSION] = 0x04020000;
 +
 +    imx_usbphy_softreset(s);
 +}
 +
 +static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
 +    uint32_t index = offset >> 2;
 +    uint32_t value;
 +
 +    switch (index) {
 +    case USBPHY_PWD_SET:
 +    case USBPHY_TX_SET:
 +    case USBPHY_RX_SET:
 +    case USBPHY_CTRL_SET:
 +    case USBPHY_DEBUG_SET:
 +    case USBPHY_DEBUG1_SET:
 +        /*
 +         * All REG_NAME_SET register access are in fact targeting the
 +         * REG_NAME register.
 +         */
 +        value = s->usbphy[index - 1];
 +        break;
 +    case USBPHY_PWD_CLR:
 +    case USBPHY_TX_CLR:
 +    case USBPHY_RX_CLR:
 +    case USBPHY_CTRL_CLR:
 +    case USBPHY_DEBUG_CLR:
 +    case USBPHY_DEBUG1_CLR:
 +        /*
 +         * All REG_NAME_CLR register access are in fact targeting the
 +         * REG_NAME register.
 +         */
 +        value = s->usbphy[index - 2];
 +        break;
 +    case USBPHY_PWD_TOG:
 +    case USBPHY_TX_TOG:
 +    case USBPHY_RX_TOG:
 +    case USBPHY_CTRL_TOG:
 +    case USBPHY_DEBUG_TOG:
 +    case USBPHY_DEBUG1_TOG:
 +        /*
 +         * All REG_NAME_TOG register access are in fact targeting the
 +         * REG_NAME register.
 +         */
 +        value = s->usbphy[index - 3];
 +        break;
 +    default:
 +        value = s->usbphy[index];
 +        break;
 +    }
 +    return (uint64_t)value;
 +}
 +
 +static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
 +                             unsigned size)
 +{
 +    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    switch (index) {
 +    case USBPHY_CTRL:
 +        s->usbphy[index] = value;
 +        if (value & USBPHY_CTRL_SFTRST) {
 +            imx_usbphy_softreset(s);
 +        }
 +        break;
 +    case USBPHY_PWD:
 +    case USBPHY_TX:
 +    case USBPHY_RX:
 +    case USBPHY_STATUS:
 +    case USBPHY_DEBUG:
 +    case USBPHY_DEBUG1:
 +        s->usbphy[index] = value;
 +        break;
 +    case USBPHY_CTRL_SET:
 +        s->usbphy[index - 1] |= value;
 +        if (value & USBPHY_CTRL_SFTRST) {
 +            imx_usbphy_softreset(s);
 +        }
 +        break;
 +    case USBPHY_PWD_SET:
 +    case USBPHY_TX_SET:
 +    case USBPHY_RX_SET:
 +    case USBPHY_DEBUG_SET:
 +    case USBPHY_DEBUG1_SET:
 +        /*
 +         * All REG_NAME_SET register access are in fact targeting the
 +         * REG_NAME register. So we change the value of the REG_NAME
 +         * register, setting bits passed in the value.
 +         */
 +        s->usbphy[index - 1] |= value;
 +        break;
 +    case USBPHY_PWD_CLR:
 +    case USBPHY_TX_CLR:
 +    case USBPHY_RX_CLR:
 +    case USBPHY_CTRL_CLR:
 +    case USBPHY_DEBUG_CLR:
 +    case USBPHY_DEBUG1_CLR:
 +        /*
 +         * All REG_NAME_CLR register access are in fact targeting the
 +         * REG_NAME register. So we change the value of the REG_NAME
 +         * register, unsetting bits passed in the value.
 +         */
 +        s->usbphy[index - 2] &= ~value;
 +        break;
 +    case USBPHY_CTRL_TOG:
 +        s->usbphy[index - 3] ^= value;
 +        if ((value & USBPHY_CTRL_SFTRST) &&
 +            (s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
 +            imx_usbphy_softreset(s);
 +        }
 +        break;
 +    case USBPHY_PWD_TOG:
 +    case USBPHY_TX_TOG:
 +    case USBPHY_RX_TOG:
 +    case USBPHY_DEBUG_TOG:
 +    case USBPHY_DEBUG1_TOG:
 +        /*
 +         * All REG_NAME_TOG register access are in fact targeting the
 +         * REG_NAME register. So we change the value of the REG_NAME
 +         * register, toggling bits passed in the value.
 +         */
 +        s->usbphy[index - 3] ^= value;
 +        break;
 +    default:
 +        /* Other registers are read-only */
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps imx_usbphy_ops = {
 +    .read = imx_usbphy_read,
 +    .write = imx_usbphy_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        /*
 +         * Our device would not work correctly if the guest was doing
 +         * unaligned access. This might not be a limitation on the real
 +         * device but in practice there is no reason for a guest to access
 +         * this device unaligned.
 +         */
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
 +static void imx_usbphy_realize(DeviceState *dev, Error **errp)
 +{
 +    IMXUSBPHYState *s = IMX_USBPHY(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
 +                          "imx-usbphy", 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 +}
 +
 +static void imx_usbphy_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->reset = imx_usbphy_reset;
 +    dc->vmsd = &vmstate_imx_usbphy;
 +    dc->desc = "i.MX USB PHY Module";
 +    dc->realize = imx_usbphy_realize;
 +}
 +
 +static const TypeInfo imx_usbphy_info = {
 +    .name          = TYPE_IMX_USBPHY,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMXUSBPHYState),
 +    .class_init    = imx_usbphy_class_init,
 +};
 +
 +static void imx_usbphy_register_types(void)
 +{
 +    type_register_static(&imx_usbphy_info);
 +}
 +
 +type_init(imx_usbphy_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
+@@ -XXX,XX +XXX,XX @@ F: hw/arm/sabrelite.c
- F: include/hw/timer/cmsdk-apb-timer.h
+ F: hw/arm/fsl-imx6.c
- F: hw/char/cmsdk-apb-uart.c
+ F: hw/misc/imx6_*.c
- F: include/hw/char/cmsdk-apb-uart.h
+ F: hw/ssi/imx_spi.c
-+F: hw/misc/tz-ppc.c
++F: hw/usb/imx-usb-phy.c
-+F: include/hw/misc/tz-ppc.h
++F: include/hw/usb/imx-usb-phy.h
+ F: include/hw/arm/fsl-imx6.h
- ARM cores
+ F: include/hw/misc/imx6_*.h
- M: Peter Maydell <peter.maydell@linaro.org>
+ F: include/hw/ssi/imx_spi.h
-@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
- L: qemu-arm@nongnu.org
+index XXXXXXX..XXXXXXX 100644
- S: Maintained
+--- a/hw/arm/Kconfig
- F: hw/arm/mps2.c
++++ b/hw/arm/Kconfig
--F: hw/misc/mps2-scc.c
+@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
--F: include/hw/misc/mps2-scc.h
+     select IMX
-+F: hw/arm/mps2-tz.c
+     select IMX_FEC
-+F: hw/misc/mps2-*.c
+     select IMX_I2C
-+F: include/hw/misc/mps2-*.h
++    select IMX_USBPHY
-+F: hw/arm/iotkit.c
+     select SDHCI
-+F: include/hw/arm/iotkit.h
+ config ASPEED_SOC
- Musicpal
+diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
- M: Jan Kiszka <jan.kiszka@web.de>
+index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/Kconfig
 +++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_STORAGE_MTP
      bool
      default y
      depends on USB
 +
 +config IMX_USBPHY
 +    bool
 +    default y
 +    depends on USB
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+[PULL 02/11] hw/arm/fsl-imx6ul: Fix USB interrupt numbers
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
+From: Guenter Roeck <linux@roeck-us.net>
-Coverity found that the string return by 'object_get_canonical_path' was not
+USB1 and USB2 interrupt numbers were swapped. USB_PHY2 interrupt number
-being freed at two locations in the model (CID 1391294 and CID 1391293) and
+is 45. That didn't really matter up to now since the interrupts were not
-also that a memset was being called with a value greater than the max of a byte
+used, but it needs to be fixed to be able to wire up the USB controllers.
 on the second argument (CID 1391286). This patch corrects this by adding the
 freeing of the strings and also changing to memset to zero instead on
 descriptor unaligned errors.
-Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Fixes: 31cbf933f0e ("i.MX6UL: Add i.MX6UL SOC")
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200313014551.12554-3-linux@roeck-us.net
 Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/dma/xlnx-zdma.c | 10 +++++++---
+ include/hw/arm/fsl-imx6ul.h | 6 +++---
-file changed, 7 insertions(+), 3 deletions(-)
+file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/dma/xlnx-zdma.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/hw/dma/xlnx-zdma.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULIRQs {
-         qemu_log_mask(LOG_GUEST_ERROR,
+     FSL_IMX6UL_UART7_IRQ    = 39,
-                       "zdma: unaligned descriptor at %" PRIx64,
+     FSL_IMX6UL_UART8_IRQ    = 40,
-                       addr);
--        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+-    FSL_IMX6UL_USB1_IRQ     = 42,
-+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
+-    FSL_IMX6UL_USB2_IRQ     = 43,
-         s->error = true;
++    FSL_IMX6UL_USB1_IRQ     = 43,
-         return false;
++    FSL_IMX6UL_USB2_IRQ     = 42,
-     }
+     FSL_IMX6UL_USB_PHY1_IRQ = 44,
-@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
+-    FSL_IMX6UL_USB_PHY2_IRQ = 44,
-     RegisterInfo *r = &s->regs_info[addr / 4];
++    FSL_IMX6UL_USB_PHY2_IRQ = 45,
-     if (!r->data) {
+     FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
-+        gchar *path = object_get_canonical_path(OBJECT(s));
+     FSL_IMX6UL_CAAM_ERR_IRQ = 47,
          qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
 -                 object_get_canonical_path(OBJECT(s)),
 +                 path,
                   addr);
 +        g_free(path);
          ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
          zdma_ch_imr_update_irq(s);
          return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
      RegisterInfo *r = &s->regs_info[addr / 4];
      if (!r->data) {
 +        gchar *path = object_get_canonical_path(OBJECT(s));
          qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
 -                 object_get_canonical_path(OBJECT(s)),
 +                 path,
                   addr, value);
 +        g_free(path);
          ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
          zdma_ch_imr_update_irq(s);
          return;
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
+[PULL 03/11] hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Guenter Roeck <linux@roeck-us.net>
-It forgot to increase clroffset during the loop. So it only clear the
+Recent Linux kernels (post v4.20) crash due to accesses to flexcan
-first 4 bytes.
+and pwm controllers. Instantiate as unimplemented devices to work
 around the problem.
-Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Cc: qemu-stable@nongnu.org
+Message-id: 20200313014551.12554-4-linux@roeck-us.net
 Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_kvm.c | 1 +
+ hw/arm/fsl-imx6ul.c | 14 ++++++++++++++
-file changed, 1 insertion(+)
+file changed, 14 insertions(+)
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
+--- a/hw/arm/fsl-imx6ul.c
-+++ b/hw/intc/arm_gicv3_kvm.c
++++ b/hw/arm/fsl-imx6ul.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
-         if (clroffset != 0) {
+      */
-             reg = 0;
+     create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
-             kvm_gicd_access(s, clroffset, &reg, true);
-+            clroffset += 4;
++    /*
-         }
++     * PWM
-         reg = *gic_bmp_ptr32(bmp, irq);
++     */
-         kvm_gicd_access(s, offset, &reg, true);
++    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
 +    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
 +    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
 +    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
 +
 +    /*
 +     * CAN
 +     */
 +    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
 +    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
 +
      /*
       * APHB_DMA
       */
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
+[PULL 04/11] hw/arm/fsl-imx6ul: Wire up USB controllers
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Guenter Roeck <linux@roeck-us.net>
-acpi_data_push uses g_array_set_size to resize the memory size. If there
+IMX6UL USB controllers are quite similar to IMX7 USB controllers.
-is no enough contiguous memory, the address will be changed. So previous
+Wire them up the same way.
 pointer could not be used any more. It must update the pointer and use
 the new one.
-Also, previous codes wrongly use le32 conversion of iort->node_offset
+The only real difference is that wiring up phy devices is necessary
-for subsequent computations that will result incorrect value if host is
+to avoid phy reset timeouts in the Linux kernel.
 not litlle endian. So use the non-converted one instead.
-Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20200313014551.12554-5-linux@roeck-us.net
-Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
+ include/hw/arm/fsl-imx6ul.h | 10 ++++++++++
-file changed, 15 insertions(+), 5 deletions(-)
+ hw/arm/fsl-imx6ul.c         | 35 +++++++++++++++++++++++++++++++++++
 files changed, 45 insertions(+)
-diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt-acpi-build.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/hw/arm/virt-acpi-build.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@
-     AcpiIortItsGroup *its;
+ #include "hw/sd/sdhci.h"
-     AcpiIortTable *iort;
+ #include "hw/ssi/imx_spi.h"
-     AcpiIortSmmu3 *smmu;
+ #include "hw/net/imx_fec.h"
--    size_t node_size, iort_length, smmu_offset = 0;
++#include "hw/usb/chipidea.h"
-+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
++#include "hw/usb/imx-usb-phy.h"
-     AcpiIortRC *rc;
+ #include "exec/memory.h"
+ #include "cpu.h"
-     iort = acpi_data_push(table_data, sizeof(*iort));
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_I2CS         = 4,
-     iort_length = sizeof(*iort);
+     FSL_IMX6UL_NUM_ECSPIS       = 4,
-     iort->node_count = cpu_to_le32(nb_nodes);
+     FSL_IMX6UL_NUM_ADCS         = 2,
--    iort->node_offset = cpu_to_le32(sizeof(*iort));
++    FSL_IMX6UL_NUM_USB_PHYS     = 2,
-+    /*
++    FSL_IMX6UL_NUM_USBS         = 2,
-+     * Use a copy in case table_data->data moves during acpi_data_push
+ };
-+     * operations.
-+     */
+ typedef struct FslIMX6ULState {
-+    iort_node_offset = sizeof(*iort);
+@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
-+    iort->node_offset = cpu_to_le32(iort_node_offset);
+     IMXFECState        eth[FSL_IMX6UL_NUM_ETHS];
+     SDHCIState         usdhc[FSL_IMX6UL_NUM_USDHCS];
-     /* ITS group node */
+     IMX2WdtState       wdt[FSL_IMX6UL_NUM_WDTS];
-     node_size =  sizeof(*its) + sizeof(uint32_t);
++    IMXUSBPHYState     usbphy[FSL_IMX6UL_NUM_USB_PHYS];
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
++    ChipideaState      usb[FSL_IMX6UL_NUM_USBS];
-         int irq =  vms->irqmap[VIRT_SMMU];
+     MemoryRegion       rom;
+     MemoryRegion       caam;
-         /* SMMUv3 node */
+     MemoryRegion       ocram;
--        smmu_offset = iort->node_offset + node_size;
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULMemoryMap {
-+        smmu_offset = iort_node_offset + node_size;
+     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
-         node_size = sizeof(*smmu) + sizeof(*idmap);
+     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
-         iort_length += node_size;
+     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
-         smmu = acpi_data_push(table_data, node_size);
++    FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
++    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
-         idmap->id_count = cpu_to_le32(0xFFFF);
++    FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
-         idmap->output_base = 0;
++    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
-         /* output IORT node is the ITS group node (the first node) */
+     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
--        idmap->output_reference = cpu_to_le32(iort->node_offset);
+     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
-+        idmap->output_reference = cpu_to_le32(iort_node_offset);
+     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx6ul.c
 +++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/arm/fsl-imx6ul.h"
  #include "hw/misc/unimp.h"
 +#include "hw/usb/imx-usb-phy.h"
  #include "hw/boards.h"
  #include "sysemu/sysemu.h"
  #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
                                TYPE_IMX_ENET);
      }
-     /* Root Complex Node */
++    /* USB */
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
++    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
-         idmap->output_reference = cpu_to_le32(smmu_offset);
++        snprintf(name, NAME_SIZE, "usbphy%d", i);
-     } else {
++        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
-         /* output IORT node is the ITS group node (the first node) */
++                              TYPE_IMX_USBPHY);
--        idmap->output_reference = cpu_to_le32(iort->node_offset);
++    }
-+        idmap->output_reference = cpu_to_le32(iort_node_offset);
++    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
 +        snprintf(name, NAME_SIZE, "usb%d", i);
 +        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
 +                              TYPE_CHIPIDEA);
 +    }
 +
      /*
       * SDHCI
       */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                              FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
      }
-+    /*
++    /* USB */
-+     * Update the pointer address in case table_data->data moves during above
++    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
-+     * acpi_data_push operations.
++        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
-+     */
++                                 &error_abort);
-+    iort = (AcpiIortTable *)(table_data->data + iort_start);
++        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-     iort->length = cpu_to_le32(iort_length);
++                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
++    }
-     build_header(linker, table_data, (void *)(table_data->data + iort_start),
++
 +    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
 +        static const int FSL_IMX6UL_USBn_IRQ[] = {
 +            FSL_IMX6UL_USB1_IRQ,
 +            FSL_IMX6UL_USB2_IRQ,
 +        };
 +        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
 +                                 &error_abort);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 +                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
 +                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 +                                            FSL_IMX6UL_USBn_IRQ[i]));
 +    }
 +
      /*
       * USDHC
       */
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
+[PULL 05/11] hw/arm/fsl-imx6: Wire up USB controllers
-From: Igor Mammedov <imammedo@redhat.com>
+From: Guenter Roeck <linux@roeck-us.net>
-When QEMU is started with following CLI
+With this patch, the USB controllers on 'sabrelite' are detected
- -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
+and can be used to boot the system.
 it crashes with abort at
  accel/kvm/kvm-all.c:2164:
  KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
-Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-arm_gicv3_icc_reset() where the later is called by CPU reset
+Message-id: 20200313014551.12554-6-linux@roeck-us.net
 reset callback.
 However commit:
 b77f6c arm/boot: split load_dtb() from arm_load_kernel()
 broke CPU reset callback registration in case
   arm_load_kernel()
       ...
       if (!info->kernel_filename || info->firmware_loaded)
 branch is taken, i.e. it's sufficient to provide a firmware
 or do not provide kernel on CLI to skip cpu reset callback
 registration, where before offending commit the callback
 has been registered unconditionally.
 Fix it by registering the callback right at the beginning of
 arm_load_kernel() unconditionally instead of doing it at the end.
 NOTE:
  we probably should eliminate that dependency anyways as well as
  separate arch CPU reset parts from arm_load_kernel() into CPU
  itself, but that refactoring that I probably would have to do
  anyways later for CPU hotplug to work.
 Reported-by: Auger Eric <eric.auger@redhat.com>
 Signed-off-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Tested-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/boot.c | 18 +++++++++---------
+ include/hw/arm/fsl-imx6.h |  6 ++++++
-file changed, 9 insertions(+), 9 deletions(-)
+ hw/arm/fsl-imx6.c         | 36 ++++++++++++++++++++++++++++++++++++
 files changed, 42 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/include/hw/arm/fsl-imx6.h
-+++ b/hw/arm/boot.c
++++ b/include/hw/arm/fsl-imx6.h
-@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+@@ -XXX,XX +XXX,XX @@
-     static const ARMInsnFixup *primary_loader;
+ #include "hw/sd/sdhci.h"
-     AddressSpace *as = arm_boot_address_space(cpu, info);
+ #include "hw/ssi/imx_spi.h"
+ #include "hw/net/imx_fec.h"
-+    /* CPU objects (unlike devices) are not automatically reset on system
++#include "hw/usb/chipidea.h"
-+     * reset, so we must always register a handler to do so. If we're
++#include "hw/usb/imx-usb-phy.h"
-+     * actually loading a kernel, the handler is also responsible for
+ #include "exec/memory.h"
-+     * arranging that we start it correctly.
+ #include "cpu.h"
-+     */
-+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+@@ -XXX,XX +XXX,XX @@
-+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+ #define FSL_IMX6_NUM_ESDHCS 4
  #define FSL_IMX6_NUM_ECSPIS 5
  #define FSL_IMX6_NUM_WDTS 2
 +#define FSL_IMX6_NUM_USB_PHYS 2
 +#define FSL_IMX6_NUM_USBS 4
  typedef struct FslIMX6State {
      /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
      SDHCIState     esdhc[FSL_IMX6_NUM_ESDHCS];
      IMXSPIState    spi[FSL_IMX6_NUM_ECSPIS];
      IMX2WdtState   wdt[FSL_IMX6_NUM_WDTS];
 +    IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
 +    ChipideaState  usb[FSL_IMX6_NUM_USBS];
      IMXFECState    eth;
      MemoryRegion   rom;
      MemoryRegion   caam;
 diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx6.c
 +++ b/hw/arm/fsl-imx6.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qapi/error.h"
  #include "hw/arm/fsl-imx6.h"
 +#include "hw/usb/imx-usb-phy.h"
  #include "hw/boards.h"
  #include "hw/qdev-properties.h"
  #include "sysemu/sysemu.h"
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
                                TYPE_IMX_USDHC);
      }
 +    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
 +        snprintf(name, NAME_SIZE, "usbphy%d", i);
 +        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
 +                              TYPE_IMX_USBPHY);
 +    }
 +    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
 +        snprintf(name, NAME_SIZE, "usb%d", i);
 +        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
 +                              TYPE_CHIPIDEA);
 +    }
 +
-     /* The board code is not supposed to set secure_board_setup unless
+     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
-      * running its code in secure mode is actually possible, and KVM
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
-      * doesn't support secure.
+         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
-@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
-         ARM_CPU(cs)->env.boot_info = info;
+                                             esdhc_table[i].irq));
      }
--    /* CPU objects (unlike devices) are not automatically reset on system
++    /* USB */
--     * reset, so we must always register a handler to do so. If we're
++    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
--     * actually loading a kernel, the handler is also responsible for
++        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
--     * arranging that we start it correctly.
++                                 &error_abort);
--     */
++        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
--    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
++                        FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
--        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
++    }
--    }
++    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
--
++        static const int FSL_IMX6_USBn_IRQ[] = {
-     if (!info->skip_dtb_autoload && have_dtb(info)) {
++            FSL_IMX6_USB_OTG_IRQ,
-         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
++            FSL_IMX6_USB_HOST1_IRQ,
-             exit(1);
++            FSL_IMX6_USB_HOST2_IRQ,
 +            FSL_IMX6_USB_HOST3_IRQ,
 +        };
 +
 +        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
 +                                 &error_abort);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 +                        FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
 +                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 +                                            FSL_IMX6_USBn_IRQ[i]));
 +    }
 +
      /* Initialize all ECSPI */
      for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
          static const struct {
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
+[PULL 06/11] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Chen Qun <kuhn.chenqun@huawei.com>
-Depending on the host abi, float16, aka uint16_t, values are
+The current code causes clang static code analyzer generate warning:
-passed and returned either zero-extended in the host register
+hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
-or with garbage at the top of the host register.
+        value = value & 0x0000000f;
         ^       ~~~~~~~~~~~~~~~~~~
 hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
         value = value & 0x000000fd;
         ^       ~~~~~~~~~~~~~~~~~~
-The tcg code generator has so far been assuming garbage, as that
+According to the definition of the function, the two “value” assignments
-matches the x86 abi, but this is incorrect for other host abis.
+ should be written to registers.
 Further, target/arm has so far been assuming zero-extended results,
 so that it may store the 16-bit value into a 32-bit slot with the
 high 16-bits already clear.
-Rectify both problems by mapping "f16" in the helper definition
+Reported-by: Euler Robot <euler.robot@huawei.com>
-to uint32_t instead of (a typedef for) uint16_t.  This forces
+Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
-the host compiler to assume garbage in the upper 16 bits on input
+Message-id: 20200313123242.13236-1-kuhn.chenqun@huawei.com
 and to zero-extend the result on output.
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/exec/helper-head.h |  2 +-
+ hw/net/imx_fec.c | 6 ++++--
- target/arm/helper-a64.c    | 35 +++++++++--------
+file changed, 4 insertions(+), 2 deletions(-)
  target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 files changed, 59 insertions(+), 58 deletions(-)
-diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
+diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/helper-head.h
+--- a/hw/net/imx_fec.c
-+++ b/include/exec/helper-head.h
++++ b/hw/net/imx_fec.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
- #define dh_ctype_int int
+         break;
- #define dh_ctype_i64 uint64_t
+     case ENET_TGSR:
- #define dh_ctype_s64 int64_t
+         /* implement clear timer flag */
--#define dh_ctype_f16 float16
+-        value = value & 0x0000000f;
-+#define dh_ctype_f16 uint32_t
++        s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
- #define dh_ctype_f32 float32
+         break;
- #define dh_ctype_f64 float64
+     case ENET_TCSR0:
- #define dh_ctype_ptr void *
+     case ENET_TCSR1:
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+     case ENET_TCSR2:
-index XXXXXXX..XXXXXXX 100644
+     case ENET_TCSR3:
---- a/target/arm/helper-a64.c
+-        value = value & 0x000000fd;
-+++ b/target/arm/helper-a64.c
++        s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
++        s->regs[index] &= ~0x0000007d; /* writable fields */
-     return flags;
++        s->regs[index] |= (value & 0x0000007d);
- }
+         break;
+     case ENET_TCCR0:
--uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+     case ENET_TCCR1:
 +uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
  {
      return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
  }
 -uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
 +uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
  {
      return float_rel_to_flags(float16_compare(x, y, fp_status));
  }
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
  #define float64_three make_float64(0x4008000000000000ULL)
  #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 -float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
      return float64_muladd(a, b, float64_two, 0, fpst);
  }
 -float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
  }
  /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
 -float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
 +uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
      uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
  #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
  #define ADVSIMD_HALFOP(name) \
 -float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
 +uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
  { \
      float_status *fpst = fpstp; \
      return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
  ADVSIMD_TWOHALFOP(mulx)
  /* fused multiply-accumulate */
 -float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
 +uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
 +                                 void *fpstp)
  {
      float_status *fpst = fpstp;
      return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
  #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 -uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare_quiet(a, b, fpst);
      return ADVSIMD_CMPRES(compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      int compare = float16_compare(a, b, fpst);
      return ADVSIMD_CMPRES(compare == float_relation_greater);
  }
 -uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
  }
  /* round to integral */
 -float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
  {
      return float16_round_to_int(x, fp_status);
  }
 -float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
  {
      int old_flags = get_float_exception_flags(fp_status), new_flags;
      float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
   * setting the mode appropriately before calling the helper.
   */
 -uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
 +uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
      return float16_to_int16(a, fpst);
  }
 -uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
 +uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
   * Square Root and Reciprocal square root
   */
 -float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
 +uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
  {
      float_status *s = fpstp;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
  /* Integer to float and float to integer conversions */
 -#define CONV_ITOF(name, fsz, sign) \
 -    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
 +#define CONV_ITOF(name, ftype, fsz, sign)                           \
 +ftype HELPER(name)(uint32_t x, void *fpstp)                         \
 +{                                                                   \
 +    float_status *fpst = fpstp;                                     \
 +    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
  }
 -#define CONV_FTOI(name, fsz, sign, round) \
 -uint32_t HELPER(name)(float##fsz x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    if (float##fsz##_is_any_nan(x)) { \
 -        float_raise(float_flag_invalid, fpst); \
 -        return 0; \
 -    } \
 -    return float##fsz##_to_##sign##int32##round(x, fpst); \
 +#define CONV_FTOI(name, ftype, fsz, sign, round)                \
 +uint32_t HELPER(name)(ftype x, void *fpstp)                     \
 +{                                                               \
 +    float_status *fpst = fpstp;                                 \
 +    if (float##fsz##_is_any_nan(x)) {                           \
 +        float_raise(float_flag_invalid, fpst);                  \
 +        return 0;                                               \
 +    }                                                           \
 +    return float##fsz##_to_##sign##int32##round(x, fpst);       \
  }
 -#define FLOAT_CONVS(name, p, fsz, sign) \
 -CONV_ITOF(vfp_##name##to##p, fsz, sign) \
 -CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
 -CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
 +#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
 +    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
 +    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
 +    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 -FLOAT_CONVS(si, h, 16, )
 -FLOAT_CONVS(si, s, 32, )
 -FLOAT_CONVS(si, d, 64, )
 -FLOAT_CONVS(ui, h, 16, u)
 -FLOAT_CONVS(ui, s, 32, u)
 -FLOAT_CONVS(ui, d, 64, u)
 +FLOAT_CONVS(si, h, uint32_t, 16, )
 +FLOAT_CONVS(si, s, float32, 32, )
 +FLOAT_CONVS(si, d, float64, 64, )
 +FLOAT_CONVS(ui, h, uint32_t, 16, u)
 +FLOAT_CONVS(ui, s, float32, 32, u)
 +FLOAT_CONVS(ui, d, float64, 64, u)
  #undef CONV_ITOF
  #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
      return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
  }
 -float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
  }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
      }
  }
 -uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
  }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
  }
  /* Half precision conversions.  */
 -float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
      g_assert_not_reached();
  }
 -float16 HELPER(recpe_f16)(float16 input, void *fpstp)
 +uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
      return extract64(estimate, 0, 8) << 44;
  }
 -float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
 +uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
  {
      float_status *s = fpstp;
      float16 f16 = float16_squash_input_denormal(input, s);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
+[PULL 07/11] m25p80: Convert to support tracing
-The FRECPX instructions should (like most other floating point operations)
+From: Guenter Roeck <linux@roeck-us.net>
 honour the FPCR.FZ bit which specifies whether input denormals should
 be flushed to zero (or FZ16 for the half-precision version).
 We forgot to implement this, which doesn't affect the results (since
 the calculation doesn't actually care about the mantissa bits) but did
 mean we were failing to set the FPSR.IDC bit.
+While at it, add some trace messages to help debug problems
+seen when running the latest Linux kernel.
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
 ---
- target/arm/helper-a64.c | 6 ++++++
+ hw/block/m25p80.c     | 48 ++++++++++++++++++++-----------------------
-file changed, 6 insertions(+)
+ hw/block/trace-events | 16 +++++++++++++++
 files changed, 38 insertions(+), 26 deletions(-)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
+diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
+--- a/hw/block/m25p80.c
-+++ b/target/arm/helper-a64.c
++++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@
-         return nan;
+ #include "qemu/module.h"
  #include "qemu/error-report.h"
  #include "qapi/error.h"
 -
 -#ifndef M25P80_ERR_DEBUG
 -#define M25P80_ERR_DEBUG 0
 -#endif
 -
 -#define DB_PRINT_L(level, ...) do { \
 -    if (M25P80_ERR_DEBUG > (level)) { \
 -        fprintf(stderr,  ": %s: ", __func__); \
 -        fprintf(stderr, ## __VA_ARGS__); \
 -    } \
 -} while (0)
 +#include "trace.h"
  /* Fields for FlashPartInfo->flags */
@@ -XXX,XX +XXX,XX @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
          abort();
      }
-+    a = float16_squash_input_denormal(a, fpst);
+-    DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
 +    trace_m25p80_flash_erase(s, offset, len);
 +
-     val16 = float16_val(a);
+     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
-     sbit = 0x8000 & val16;
+         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
-     exp = extract32(val16, 10, 5);
+                       " device\n", len);
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
          return nan;
      }
-+    a = float32_squash_input_denormal(a, fpst);
+     if ((prev ^ data) & data) {
 -        DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 "  %" PRIx8
 -                   " -> %" PRIx8 "\n", addr, prev, data);
 +        trace_m25p80_programming_zero_to_one(s, addr, prev, data);
      }
      if (s->pi->flags & EEPROM) {
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
      s->state = STATE_IDLE;
 +    trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
 +                                     s->cur_addr);
 +
-     val32 = float32_val(a);
+     switch (s->cmd_in_progress) {
-     sbit = 0x80000000ULL & val32;
+     case DPP:
-     exp = extract32(val32, 23, 8);
+     case QPP:
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
+@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
-         return nan;
+         break;
      }
-+    a = float64_squash_input_denormal(a, fpst);
+-    DB_PRINT_L(0, "Reset done.\n");
 +    trace_m25p80_reset_done(s);
  }
  static void decode_fast_read_cmd(Flash *s)
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
  static void decode_new_cmd(Flash *s, uint32_t value)
  {
 -    s->cmd_in_progress = value;
      int i;
 -    DB_PRINT_L(0, "decoded new command:%x\n", value);
 +
-     val64 = float64_val(a);
++    s->cmd_in_progress = value;
-     sbit = 0x8000000000000000ULL & val64;
++    trace_m25p80_command_decoded(s, value);
-     exp = extract64(float64_val(a), 52, 11);
      if (value != RESET_MEMORY) {
          s->reset_enable = false;
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
          break;
      case JEDEC_READ:
 -        DB_PRINT_L(0, "populated jedec code\n");
 +        trace_m25p80_populated_jedec(s);
          for (i = 0; i < s->pi->id_len; i++) {
              s->data[i] = s->pi->id[i];
          }
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
      case BULK_ERASE_60:
      case BULK_ERASE:
          if (s->write_enable) {
 -            DB_PRINT_L(0, "chip erase\n");
 +            trace_m25p80_chip_erase(s);
              flash_erase(s, 0, BULK_ERASE);
          } else {
              qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
@@ -XXX,XX +XXX,XX @@ static int m25p80_cs(SSISlave *ss, bool select)
          s->data_read_loop = false;
      }
 -    DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
 +    trace_m25p80_select(s, select ? "de" : "");
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
      Flash *s = M25P80(ss);
      uint32_t r = 0;
 +    trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
 +                          s->cur_addr, (uint8_t)tx);
 +
      switch (s->state) {
      case STATE_PAGE_PROGRAM:
 -        DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
 -                   s->cur_addr, (uint8_t)tx);
 +        trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
          flash_write8(s, s->cur_addr, (uint8_t)tx);
          s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
          break;
      case STATE_READ:
          r = s->storage[s->cur_addr];
 -        DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
 -                   (uint8_t)r);
 +        trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
          s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
          break;
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
          }
          r = s->data[s->pos];
 +        trace_m25p80_read_data(s, s->pos, (uint8_t)r);
          s->pos++;
          if (s->pos == s->len) {
              s->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
              return;
          }
 -        DB_PRINT_L(0, "Binding to IF_MTD drive\n");
 +        trace_m25p80_binding(s);
          s->storage = blk_blockalign(s->blk, s->size);
          if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
              return;
          }
      } else {
 -        DB_PRINT_L(0, "No BDRV - binding to RAM\n");
 +        trace_m25p80_binding_no_bdrv(s);
          s->storage = blk_blockalign(NULL, s->size);
          memset(s->storage, 0xFF, s->size);
      }
 diff --git a/hw/block/trace-events b/hw/block/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/trace-events
 +++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ xen_block_blockdev_add(char *str) "%s"
  xen_block_blockdev_del(const char *node_name) "%s"
  xen_block_device_create(unsigned int number) "%u"
  xen_block_device_destroy(unsigned int number) "%u"
 +
 +# m25p80.c
 +m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
 +m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32"  0x%"PRIx8" -> 0x%"PRIx8
 +m25p80_reset_done(void *s) "[%p] Reset done."
 +m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
 +m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
 +m25p80_populated_jedec(void *s) "[%p] populated jedec code"
 +m25p80_chip_erase(void *s) "[%p] chip erase"
 +m25p80_select(void *s, const char *what) "[%p] %sselect"
 +m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_addr=0x%"PRIx32" data=0x%"PRIx8
 +m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
 +m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
 +m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
 +m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
 +m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
+[PULL 08/11] m25p80: Improve command handling for Jedec commands
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Guenter Roeck <linux@roeck-us.net>
-kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
+When requesting JEDEC data using the JEDEC_READ command, the Linux kernel
-initialize global capability variables. If we call kvm_init_irq_routing in
+always requests 6 bytes. The current implementation only returns three
-GIC realize function, previous allocated memory will leak.
+bytes, and interprets the remaining three bytes as new commands.
 While this does not matter most of the time, it is at the very least
 confusing. To avoid the problem, always report up to 6 bytes of JEDEC
 data. Fill remaining data with 0.
-Fix this by deleting the unnecessary call.
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gic_kvm.c   | 1 -
+ hw/block/m25p80.c | 5 ++++-
- hw/intc/arm_gicv3_kvm.c | 1 -
+file changed, 4 insertions(+), 1 deletion(-)
 files changed, 2 deletions(-)
-diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
+diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic_kvm.c
+--- a/hw/block/m25p80.c
-+++ b/hw/intc/arm_gic_kvm.c
++++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
+         for (i = 0; i < s->pi->id_len; i++) {
-     if (kvm_has_gsi_routing()) {
+             s->data[i] = s->pi->id[i];
          /* set up irq routing */
 -        kvm_init_irq_routing(kvm_state);
          for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
              kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
          }
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
++        for (; i < SPI_NOR_MAX_ID_LEN; i++) {
-index XXXXXXX..XXXXXXX 100644
++            s->data[i] = 0;
---- a/hw/intc/arm_gicv3_kvm.c
++        }
-+++ b/hw/intc/arm_gicv3_kvm.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
+-        s->len = s->pi->id_len;
++        s->len = SPI_NOR_MAX_ID_LEN;
-     if (kvm_has_gsi_routing()) {
+         s->pos = 0;
-         /* set up irq routing */
+         s->state = STATE_READING_DATA;
--        kvm_init_irq_routing(kvm_state);
+         break;
          for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
              kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
          }
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
+[PULL 09/11] m25p80: Improve command handling for unsupported commands
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
+From: Guenter Roeck <linux@roeck-us.net>
 add MemTxAttrs as an argument to the MemoryRegion valid.accepts
 callback. We'll need this for subpage_accepts().
-We could take the approach we used with the read and write
+Whenever an unsupported command is encountered, the current code
-callbacks and add new a new _with_attrs version, but since there
+interprets each transferred byte as new command. Most of the time, those
-are so few implementations of the accepts hook we just change
+'commands' are interpreted as new unknown commands. However, in rare
-them all.
+cases, it may be that for example address or length information
 passed with the original command is by itself a valid command.
 If that happens, the state machine may get completely confused and,
 worst case, start writing data into the flash or even erase it.
+To avoid the problem, transition into STATE_READING_DATA and keep
+sending a value of 0 until the chip is deselected after encountering
+an unsupported command.
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
 ---
- include/exec/memory.h |  3 ++-
+ hw/block/m25p80.c | 5 +++++
- exec.c                |  9 ++++++---
+file changed, 5 insertions(+)
  hw/hppa/dino.c        |  3 ++-
  hw/nvram/fw_cfg.c     | 12 ++++++++----
  hw/scsi/esp.c         |  3 ++-
  hw/xen/xen_pt_msi.c   |  3 ++-
  memory.c              |  5 +++--
 files changed, 25 insertions(+), 13 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
+diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
+--- a/hw/block/m25p80.c
-+++ b/include/exec/memory.h
++++ b/hw/block/m25p80.c
-@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
+@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
-          * as a machine check exception).
+         s->quad_enable = false;
-          */
+         break;
-         bool (*accepts)(void *opaque, hwaddr addr,
+     default:
--                        unsigned size, bool is_write);
++        s->pos = 0;
-+                        unsigned size, bool is_write,
++        s->len = 1;
-+                        MemTxAttrs attrs);
++        s->state = STATE_READING_DATA;
-     } valid;
++        s->data_read_loop = true;
-     /* Internal implementation constraints: */
++        s->data[0] = 0;
-     struct {
+         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
-diff --git a/exec.c b/exec.c
+         break;
 index XXXXXXX..XXXXXXX 100644
 --- a/exec.c
 +++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
  }
  static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
 -                                 unsigned size, bool is_write)
 +                                 unsigned size, bool is_write,
 +                                 MemTxAttrs attrs)
  {
      return is_write;
  }
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
  }
  static bool subpage_accepts(void *opaque, hwaddr addr,
 -                            unsigned len, bool is_write)
 +                            unsigned len, bool is_write,
 +                            MemTxAttrs attrs)
  {
      subpage_t *subpage = opaque;
  #if defined(DEBUG_SUBPAGE)
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
  }
  static bool readonly_mem_accepts(void *opaque, hwaddr addr,
 -                                 unsigned size, bool is_write)
 +                                 unsigned size, bool is_write,
 +                                 MemTxAttrs attrs)
  {
      return is_write;
  }
 diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/hppa/dino.c
 +++ b/hw/hppa/dino.c
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
  }
  static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
 -                                unsigned size, bool is_write)
 +                                unsigned size, bool is_write,
 +                                MemTxAttrs attrs)
  {
      switch (addr) {
      case DINO_IAR0:
 diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/nvram/fw_cfg.c
 +++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
  }
  static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
 -                                  unsigned size, bool is_write)
 +                                 unsigned size, bool is_write,
 +                                 MemTxAttrs attrs)
  {
      return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
                           (size == 8 && addr == 0));
  }
  static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
 -                                  unsigned size, bool is_write)
 +                                  unsigned size, bool is_write,
 +                                  MemTxAttrs attrs)
  {
      return addr == 0;
  }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
  }
  static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
 -                                 unsigned size, bool is_write)
 +                                 unsigned size, bool is_write,
 +                                 MemTxAttrs attrs)
  {
      return is_write && size == 2;
  }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
  }
  static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
 -                                  unsigned size, bool is_write)
 +                              unsigned size, bool is_write,
 +                              MemTxAttrs attrs)
  {
      return (size == 1) || (is_write && size == 2);
  }
 diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/scsi/esp.c
 +++ b/hw/scsi/esp.c
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
  }
  static bool esp_mem_accepts(void *opaque, hwaddr addr,
 -                            unsigned size, bool is_write)
 +                            unsigned size, bool is_write,
 +                            MemTxAttrs attrs)
  {
      return (size == 1) || (is_write && size == 4);
  }
 diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/xen/xen_pt_msi.c
 +++ b/hw/xen/xen_pt_msi.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
  }
  static bool pci_msix_accepts(void *opaque, hwaddr addr,
 -                             unsigned size, bool is_write)
 +                             unsigned size, bool is_write,
 +                             MemTxAttrs attrs)
  {
      return !(addr & (size - 1));
  }
 diff --git a/memory.c b/memory.c
 index XXXXXXX..XXXXXXX 100644
 --- a/memory.c
 +++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
  }
  static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
 -                                   unsigned size, bool is_write)
 +                                   unsigned size, bool is_write,
 +                                   MemTxAttrs attrs)
  {
      return false;
  }
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
      access_size = MAX(MIN(size, access_size_max), access_size_min);
      for (i = 0; i < size; i += access_size) {
          if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
 -                                    is_write)) {
 +                                    is_write, attrs)) {
              return false;
          }
      }
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
+[PULL 10/11] aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
-From: Paolo Bonzini <pbonzini@redhat.com>
+From: Guenter Roeck <linux@roeck-us.net>
-cpregs_keys is an uint32_t* so the allocation should use uint32_t.
+The Linux kernel recently started using FAST_READ_4 commands.
-g_new is even better because it is type-safe.
+This results in flash read failures. At the same time, the m25p80
 emulation is seen to read 8 more bytes than expected. Adjusting the
 expected number of dummy cycles to match FAST_READ fixes the problem.
-Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Fixes: f95c4bffdc4c ("aspeed/smc: snoop SPI transfers to fake dummy cycles")
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/gdbstub.c | 3 +--
+ hw/ssi/aspeed_smc.c | 2 +-
-file changed, 1 insertion(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/gdbstub.c
+--- a/hw/ssi/aspeed_smc.c
-+++ b/target/arm/gdbstub.c
++++ b/hw/ssi/aspeed_smc.c
-@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static int aspeed_smc_num_dummies(uint8_t command)
-     RegisterSysregXmlParam param = {cs, s};
+     case FAST_READ:
+     case DOR:
-     cpu->dyn_xml.num_cpregs = 0;
+     case QOR:
--    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
++    case FAST_READ_4:
--                                        g_hash_table_size(cpu->cp_regs));
+     case DOR_4:
-+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
+     case QOR_4:
-     g_string_printf(s, "<?xml version=\"1.0\"?>");
+         return 1;
-     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+     case DIOR:
-     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
+-    case FAST_READ_4:
      case DIOR_4:
          return 2;
      case QIOR:
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+[PULL 11/11] hw/arm/pxa2xx: Do not wire up OHCI for PXA255
-From: Jan Kiszka <jan.kiszka@siemens.com>
+From: Guenter Roeck <linux@roeck-us.net>
-There was a nasty flip in identifying which register group an access is
+PXA255 does not support a USB OHCI controller, so don't wire it up.
 targeting. The issue caused spuriously raised priorities of the guest
 when handing CPUs over in the Jailhouse hypervisor.
-Cc: qemu-stable@nongnu.org
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Message-id: 20200313160215.28155-1-linux@roeck-us.net
 Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
+ hw/arm/pxa2xx.c | 3 ---
-file changed, 6 insertions(+), 6 deletions(-)
+file changed, 3 deletions(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/hw/arm/pxa2xx.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/hw/arm/pxa2xx.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
- {
+         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
-     GICv3CPUState *cs = icc_cs_from_env(env);
+     }
-     int regno = ri->opc2 & 3;
--    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+-    sysbus_create_simple("sysbus-ohci", 0x4c000000,
-+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+-                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
-     uint64_t value = cs->ich_apr[grp][regno];
+-
+     s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
-     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
+     s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
      uint64_t value;
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
 +    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
      if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
          return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
 +    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
      if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
          icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      uint64_t value;
      value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 --
-.17.1
+.20.1

-[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
+Deleted patch
-In commit f0aff255700 we made cpacr_write() enforce that some CPACR
-bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
-we forgot to also update the register's reset value. The effect
-was that (a) a guest that read CPACR on reset would not see ones in
-the RAO bits, and (b) if you did a migration before the guest did
-a write to the CPACR then the migration would fail because the
-destination would enforce the RAO bits and then complain that they
-didn't match the zero value from the source.
-Implement reset for the CPACR using a custom reset function
-that just calls cpacr_write(), to avoid having to duplicate
-the logic for which bits are RAO.
-This bug would affect migration for TCG CPUs which are ARMv7
-with VFP but without one of Neon or VFPv3.
-Reported-by: Cédric Le Goater <clg@kaod.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Tested-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
----
- target/arm/helper.c | 10 +++++++++-
-file changed, 9 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     env->cp15.cpacr_el1 = value;
- }
-+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
-+{
-+    /* Call cpacr_write() so that we reset with the correct RAO bits set
-+     * for our CPU features.
-+     */
-+    cpacr_write(env, ri, 0);
-+}
-+
- static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
-                                    bool isread)
- {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
-     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
-       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
-       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
--      .resetvalue = 0, .writefn = cpacr_write },
-+      .resetfn = cpacr_reset, .writefn = cpacr_write },
-     REGINFO_SENTINEL
- };
---
-.17.1

-[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
+Deleted patch
-Add more detail to the documentation for memory_region_init_iommu()
-and other IOMMU-related functions and data structures.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
----
- include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
-file changed, 95 insertions(+), 10 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
-     IOMMU_ATTR_SPAPR_TCE_FD
- };
-+/**
-+ * IOMMUMemoryRegionClass:
-+ *
-+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
-+ * and provide an implementation of at least the @translate method here
-+ * to handle requests to the memory region. Other methods are optional.
-+ *
-+ * The IOMMU implementation must use the IOMMU notifier infrastructure
-+ * to report whenever mappings are changed, by calling
-+ * memory_region_notify_iommu() (or, if necessary, by calling
-+ * memory_region_notify_one() for each registered notifier).
-+ */
- typedef struct IOMMUMemoryRegionClass {
-     /* private */
-     struct DeviceClass parent_class;
-     /*
--     * Return a TLB entry that contains a given address. Flag should
--     * be the access permission of this translation operation. We can
--     * set flag to IOMMU_NONE to mean that we don't need any
--     * read/write permission checks, like, when for region replay.
-+     * Return a TLB entry that contains a given address.
-+     *
-+     * The IOMMUAccessFlags indicated via @flag are optional and may
-+     * be specified as IOMMU_NONE to indicate that the caller needs
-+     * the full translation information for both reads and writes. If
-+     * the access flags are specified then the IOMMU implementation
-+     * may use this as an optimization, to stop doing a page table
-+     * walk as soon as it knows that the requested permissions are not
-+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
-+     * full page table walk and report the permissions in the returned
-+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
-+     * return different mappings for reads and writes.)
-+     *
-+     * The returned information remains valid while the caller is
-+     * holding the big QEMU lock or is inside an RCU critical section;
-+     * if the caller wishes to cache the mapping beyond that it must
-+     * register an IOMMU notifier so it can invalidate its cached
-+     * information when the IOMMU mapping changes.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @hwaddr: address to be translated within the memory region
-+     * @flag: requested access permissions
-      */
-     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
-                                IOMMUAccessFlags flag);
--    /* Returns minimum supported page size */
-+    /* Returns minimum supported page size in bytes.
-+     * If this method is not provided then the minimum is assumed to
-+     * be TARGET_PAGE_SIZE.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     */
-     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
--    /* Called when IOMMU Notifier flag changed */
-+    /* Called when IOMMU Notifier flag changes (ie when the set of
-+     * events which IOMMU users are requesting notification for changes).
-+     * Optional method -- need not be provided if the IOMMU does not
-+     * need to know exactly which events must be notified.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @old_flags: events which previously needed to be notified
-+     * @new_flags: events which now need to be notified
-+     */
-     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
-                                 IOMMUNotifierFlag old_flags,
-                                 IOMMUNotifierFlag new_flags);
--    /* Set this up to provide customized IOMMU replay function */
-+    /* Called to handle memory_region_iommu_replay().
-+     *
-+     * The default implementation of memory_region_iommu_replay() is to
-+     * call the IOMMU translate method for every page in the address space
-+     * with flag == IOMMU_NONE and then call the notifier if translate
-+     * returns a valid mapping. If this method is implemented then it
-+     * overrides the default behaviour, and must provide the full semantics
-+     * of memory_region_iommu_replay(), by calling @notifier for every
-+     * translation present in the IOMMU.
-+     *
-+     * Optional method -- an IOMMU only needs to provide this method
-+     * if the default is inefficient or produces undesirable side effects.
-+     *
-+     * Note: this is not related to record-and-replay functionality.
-+     */
-     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
--    /* Get IOMMU misc attributes */
--    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
-+    /* Get IOMMU misc attributes. This is an optional method that
-+     * can be used to allow users of the IOMMU to get implementation-specific
-+     * information. The IOMMU implements this method to handle calls
-+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
-+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
-+     * the IOMMU supports. If the method is unimplemented then
-+     * memory_region_iommu_get_attr() will always return -EINVAL.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @attr: attribute being queried
-+     * @data: memory to fill in with the attribute data
-+     *
-+     * Returns 0 on success, or a negative errno; in particular
-+     * returns -EINVAL for unrecognized or unimplemented attribute types.
-+     */
-+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
-                     void *data);
- } IOMMUMemoryRegionClass;
-@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
-  * An IOMMU region translates addresses and forwards accesses to a target
-  * memory region.
-  *
-+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
-+ * @_iommu_mr should be a pointer to enough memory for an instance of
-+ * that subclass, @instance_size is the size of that subclass, and
-+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
-+ * instance of the subclass, and its methods will then be called to handle
-+ * accesses to the memory region. See the documentation of
-+ * #IOMMUMemoryRegionClass for further details.
-+ *
-  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
-  * @instance_size: the IOMMUMemoryRegion subclass instance size
-  * @mrtypename: the type name of the #IOMMUMemoryRegion
-@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
-  * a notifier with the minimum page granularity returned by
-  * mr->iommu_ops->get_page_size().
-  *
-+ * Note: this is not related to record-and-replay functionality.
-+ *
-  * @iommu_mr: the memory region to observe
-  * @n: the notifier to which to replay iommu mappings
-  */
-@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
-  * memory_region_iommu_replay_all: replay existing IOMMU translations
-  * to all the notifiers registered.
-  *
-+ * Note: this is not related to record-and-replay functionality.
-+ *
-  * @iommu_mr: the memory region to observe
-  */
- void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
-@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
-  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
-  * defined on the IOMMU.
-  *
-- * Returns 0 if succeded, error code otherwise.
-+ * Returns 0 on success, or a negative errno otherwise. In particular,
-+ * -EINVAL indicates that the IOMMU does not support the requested
-+ * attribute.
-  *
-  * @iommu_mr: the memory region
-  * @attr: the requested attribute
---
-.17.1

-[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to tb_invalidate_phys_addr().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
----
- include/exec/exec-all.h   | 5 +++--
- accel/tcg/translate-all.c | 2 +-
- exec.c                    | 2 +-
- target/xtensa/op_helper.c | 3 ++-
-files changed, 7 insertions(+), 5 deletions(-)
-diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/exec-all.h
-+++ b/include/exec/exec-all.h
-@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
- void tlb_set_page(CPUState *cpu, target_ulong vaddr,
-                   hwaddr paddr, int prot,
-                   int mmu_idx, target_ulong size);
--void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
-+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
- void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
-                  uintptr_t retaddr);
- #else
-@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
-                                                        uint16_t idxmap)
- {
- }
--static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
-+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
-+                                           MemTxAttrs attrs)
- {
- }
- #endif
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
- }
- #if !defined(CONFIG_USER_ONLY)
--void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
-+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
- {
-     ram_addr_t ram_addr;
-     MemoryRegion *mr;
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
-     if (phys != -1) {
-         /* Locks grabbed by tb_invalidate_phys_addr */
-         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
--                                phys | (pc & ~TARGET_PAGE_MASK));
-+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
-     }
- }
- #endif
-diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/xtensa/op_helper.c
-+++ b/target/xtensa/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
-     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
-             &paddr, &page_size, &access);
-     if (ret == 0) {
--        tb_invalidate_phys_addr(&address_space_memory, paddr);
-+        tb_invalidate_phys_addr(&address_space_memory, paddr,
-+                                MEMTXATTRS_UNSPECIFIED);
-     }
- }
---
-.17.1

-[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_translate()
-and address_space_translate_cached(). Callers either have an
-attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
----
- include/exec/memory.h     |  4 +++-
- accel/tcg/translate-all.c |  2 +-
- exec.c                    | 14 +++++++++-----
- hw/vfio/common.c          |  3 ++-
- memory_ldst.inc.c         | 18 +++++++++---------
- target/riscv/helper.c     |  2 +-
-files changed, 25 insertions(+), 18 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-  * #MemoryRegion.
-  * @len: pointer to length
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
- MemoryRegion *flatview_translate(FlatView *fv,
-                                  hwaddr addr, hwaddr *xlat,
-@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
- static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     hwaddr addr, hwaddr *xlat,
--                                                    hwaddr *len, bool is_write)
-+                                                    hwaddr *len, bool is_write,
-+                                                    MemTxAttrs attrs)
- {
-     return flatview_translate(address_space_to_flatview(as),
-                               addr, xlat, len, is_write);
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
-     hwaddr l = 1;
-     rcu_read_lock();
--    mr = address_space_translate(as, addr, &addr, &l, false);
-+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
-     if (!(memory_region_is_ram(mr)
-           || memory_region_is_romd(mr))) {
-         rcu_read_unlock();
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
-     rcu_read_lock();
-     while (len > 0) {
-         l = len;
--        mr = address_space_translate(as, addr, &addr1, &l, true);
-+        mr = address_space_translate(as, addr, &addr1, &l, true,
-+                                     MEMTXATTRS_UNSPECIFIED);
-         if (!(memory_region_is_ram(mr) ||
-               memory_region_is_romd(mr))) {
-@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
-  */
- static inline MemoryRegion *address_space_translate_cached(
-     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
--    hwaddr *plen, bool is_write)
-+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegionSection section;
-     MemoryRegion *mr;
-@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
-+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
-+                                        MEMTXATTRS_UNSPECIFIED);
-     flatview_read_continue(cache->fv,
-                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
-                            addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
-+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
-+                                        MEMTXATTRS_UNSPECIFIED);
-     flatview_write_continue(cache->fv,
-                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
-                             addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
-     rcu_read_lock();
-     mr = address_space_translate(&address_space_memory,
--                                 phys_addr, &phys_addr, &l, false);
-+                                 phys_addr, &phys_addr, &l, false,
-+                                 MEMTXATTRS_UNSPECIFIED);
-     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
-     rcu_read_unlock();
-diff --git a/hw/vfio/common.c b/hw/vfio/common.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/vfio/common.c
-+++ b/hw/vfio/common.c
-@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
-      */
-     mr = address_space_translate(&address_space_memory,
-                                  iotlb->translated_addr,
--                                 &xlat, &len, writable);
-+                                 &xlat, &len, writable,
-+                                 MEMTXATTRS_UNSPECIFIED);
-     if (!memory_region_is_ram(mr)) {
-         error_report("iommu map to non memory area %"HWADDR_PRIx"",
-                      xlat);
-diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory_ldst.inc.c
-+++ b/memory_ldst.inc.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 4 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 8 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (!IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 2 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 4 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 4 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (!IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
-@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 2 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 8 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-diff --git a/target/riscv/helper.c b/target/riscv/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.c
-+++ b/target/riscv/helper.c
-@@ -XXX,XX +XXX,XX @@ restart:
-                 MemoryRegion *mr;
-                 hwaddr l = sizeof(target_ulong), addr1;
-                 mr = address_space_translate(cs->as, pte_addr,
--                    &addr1, &l, false);
-+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
-                 if (memory_access_is_direct(mr, true)) {
-                     target_ulong *pte_pa =
-                         qemu_map_ram_ptr(mr->ram_block, addr1);
---
-.17.1

-[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_map().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
----
- include/exec/memory.h   | 3 ++-
- include/sysemu/dma.h    | 3 ++-
- exec.c                  | 6 ++++--
- target/ppc/mmu-hash64.c | 3 ++-
-files changed, 10 insertions(+), 5 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
-  * @addr: address within that address space
-  * @plen: pointer to length of buffer; updated on return
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
- void *address_space_map(AddressSpace *as, hwaddr addr,
--                        hwaddr *plen, bool is_write);
-+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
- /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
-  *
-diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/dma.h
-+++ b/include/sysemu/dma.h
-@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
-     hwaddr xlen = *len;
-     void *p;
--    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
-+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
-+                          MEMTXATTRS_UNSPECIFIED);
-     *len = xlen;
-     return p;
- }
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
- void *address_space_map(AddressSpace *as,
-                         hwaddr addr,
-                         hwaddr *plen,
--                        bool is_write)
-+                        bool is_write,
-+                        MemTxAttrs attrs)
- {
-     hwaddr len = *plen;
-     hwaddr l, xlat;
-@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
-                               hwaddr *plen,
-                               int is_write)
- {
--    return address_space_map(&address_space_memory, addr, plen, is_write);
-+    return address_space_map(&address_space_memory, addr, plen, is_write,
-+                             MEMTXATTRS_UNSPECIFIED);
- }
- void cpu_physical_memory_unmap(void *buffer, hwaddr len,
-diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/ppc/mmu-hash64.c
-+++ b/target/ppc/mmu-hash64.c
-@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
-         return NULL;
-     }
--    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
-+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
-+                              MEMTXATTRS_UNSPECIFIED);
-     if (plen < (n * HASH_PTE_SIZE_64)) {
-         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
-     }
---
-.17.1

-[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_access_valid().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
----
- include/exec/memory.h      | 4 +++-
- include/sysemu/dma.h       | 3 ++-
- exec.c                     | 3 ++-
- target/s390x/diag.c        | 6 ++++--
- target/s390x/excp_helper.c | 3 ++-
- target/s390x/mmu_helper.c  | 3 ++-
- target/s390x/sigp.c        | 3 ++-
-files changed, 17 insertions(+), 8 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
-  * @addr: address within that address space
-  * @len: length of the area to be checked
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
--bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
-+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
-+                                bool is_write, MemTxAttrs attrs);
- /* address_space_map: map a physical memory region into a host virtual address
-  *
-diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/dma.h
-+++ b/include/sysemu/dma.h
-@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
-                                     DMADirection dir)
- {
-     return address_space_access_valid(as, addr, len,
--                                      dir == DMA_DIRECTION_FROM_DEVICE);
-+                                      dir == DMA_DIRECTION_FROM_DEVICE,
-+                                      MEMTXATTRS_UNSPECIFIED);
- }
- static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
- }
- bool address_space_access_valid(AddressSpace *as, hwaddr addr,
--                                int len, bool is_write)
-+                                int len, bool is_write,
-+                                MemTxAttrs attrs)
- {
-     FlatView *fv;
-     bool result;
-diff --git a/target/s390x/diag.c b/target/s390x/diag.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/diag.c
-+++ b/target/s390x/diag.c
-@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
-             return;
-         }
-         if (!address_space_access_valid(&address_space_memory, addr,
--                                        sizeof(IplParameterBlock), false)) {
-+                                        sizeof(IplParameterBlock), false,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
-             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
-             return;
-         }
-@@ -XXX,XX +XXX,XX @@ out:
-             return;
-         }
-         if (!address_space_access_valid(&address_space_memory, addr,
--                                        sizeof(IplParameterBlock), true)) {
-+                                        sizeof(IplParameterBlock), true,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
-             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
-             return;
-         }
-diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/excp_helper.c
-+++ b/target/s390x/excp_helper.c
-@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
-     /* check out of RAM access */
-     if (!address_space_access_valid(&address_space_memory, raddr,
--                                    TARGET_PAGE_SIZE, rw)) {
-+                                    TARGET_PAGE_SIZE, rw,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
-                 (uint64_t)raddr, (uint64_t)ram_size);
-         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
-diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/mmu_helper.c
-+++ b/target/s390x/mmu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
-             return ret;
-         }
-         if (!address_space_access_valid(&address_space_memory, pages[i],
--                                        TARGET_PAGE_SIZE, is_write)) {
-+                                        TARGET_PAGE_SIZE, is_write,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
-             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
-             return -EFAULT;
-         }
-diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/sigp.c
-+++ b/target/s390x/sigp.c
-@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
-     cpu_synchronize_state(cs);
-     if (!address_space_access_valid(&address_space_memory, addr,
--                                    sizeof(struct LowCore), false)) {
-+                                    sizeof(struct LowCore), false,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
-         return;
-     }
---
-.17.1

-[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_extend_translation().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
----
- exec.c | 15 ++++++++++-----
-file changed, 10 insertions(+), 5 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
- static hwaddr
- flatview_extend_translation(FlatView *fv, hwaddr addr,
--                                 hwaddr target_len,
--                                 MemoryRegion *mr, hwaddr base, hwaddr len,
--                                 bool is_write)
-+                            hwaddr target_len,
-+                            MemoryRegion *mr, hwaddr base, hwaddr len,
-+                            bool is_write, MemTxAttrs attrs)
- {
-     hwaddr done = 0;
-     hwaddr xlat;
-@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
-     memory_region_ref(mr);
-     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
--                                             l, is_write);
-+                                        l, is_write, attrs);
-     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
-     rcu_read_unlock();
-@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
-     mr = cache->mrs.mr;
-     memory_region_ref(mr);
-     if (memory_access_is_direct(mr, is_write)) {
-+        /* We don't care about the memory attributes here as we're only
-+         * doing this if we found actual RAM, which behaves the same
-+         * regardless of attributes; so UNSPECIFIED is fine.
-+         */
-         l = flatview_extend_translation(cache->fv, addr, len, mr,
--                                        cache->xlat, l, is_write);
-+                                        cache->xlat, l, is_write,
-+                                        MEMTXATTRS_UNSPECIFIED);
-         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
-     } else {
-         cache->ptr = NULL;
---
-.17.1

-[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to memory_region_access_valid().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-The callsite in flatview_access_valid() is part of a recursive
-loop flatview_access_valid() -> memory_region_access_valid() ->
- subpage_accepts() -> flatview_access_valid(); we make it pass
-MEMTXATTRS_UNSPECIFIED for now, until the next several commits
-have plumbed an attrs parameter through the rest of the loop
-and we can add an attrs parameter to flatview_access_valid().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
----
- include/exec/memory-internal.h | 3 ++-
- exec.c                         | 4 +++-
- hw/s390x/s390-pci-inst.c       | 3 ++-
- memory.c                       | 7 ++++---
-files changed, 11 insertions(+), 6 deletions(-)
-diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory-internal.h
-+++ b/include/exec/memory-internal.h
-@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
- extern const MemoryRegionOps unassigned_mem_ops;
- bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
--                                unsigned size, bool is_write);
-+                                unsigned size, bool is_write,
-+                                MemTxAttrs attrs);
- void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
- AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
--            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
-+            /* When our callers all have attrs we'll pass them through here */
-+            if (!memory_region_access_valid(mr, xlat, l, is_write,
-+                                            MEMTXATTRS_UNSPECIFIED)) {
-                 return false;
-             }
-         }
-diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/s390x/s390-pci-inst.c
-+++ b/hw/s390x/s390-pci-inst.c
-@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
-     mr = s390_get_subregion(mr, offset, len);
-     offset -= mr->addr;
--    if (!memory_region_access_valid(mr, offset, len, true)) {
-+    if (!memory_region_access_valid(mr, offset, len, true,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
-         return 0;
-     }
-diff --git a/memory.c b/memory.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory.c
-+++ b/memory.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
- bool memory_region_access_valid(MemoryRegion *mr,
-                                 hwaddr addr,
-                                 unsigned size,
--                                bool is_write)
-+                                bool is_write,
-+                                MemTxAttrs attrs)
- {
-     int access_size_min, access_size_max;
-     int access_size, i;
-@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
- {
-     MemTxResult r;
--    if (!memory_region_access_valid(mr, addr, size, false)) {
-+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
-         *pval = unassigned_mem_read(mr, addr, size);
-         return MEMTX_DECODE_ERROR;
-     }
-@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
-                                          unsigned size,
-                                          MemTxAttrs attrs)
- {
--    if (!memory_region_access_valid(mr, addr, size, true)) {
-+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
-         unassigned_mem_write(mr, addr, data, size);
-         return MEMTX_DECODE_ERROR;
-     }
---
-.17.1

-[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_access_valid().
-Its callers now all have an attrs value to hand, so we can
-correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
----
- exec.c | 12 +++++-------
-file changed, 5 insertions(+), 7 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
- static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
-                                   const uint8_t *buf, int len);
- static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
--                                  bool is_write);
-+                                  bool is_write, MemTxAttrs attrs);
- static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
-                                 unsigned len, MemTxAttrs attrs)
-@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
- #endif
-     return flatview_access_valid(subpage->fv, addr + subpage->base,
--                                 len, is_write);
-+                                 len, is_write, attrs);
- }
- static const MemoryRegionOps subpage_ops = {
-@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
- }
- static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
--                                  bool is_write)
-+                                  bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegion *mr;
-     hwaddr l, xlat;
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
--            /* When our callers all have attrs we'll pass them through here */
--            if (!memory_region_access_valid(mr, xlat, l, is_write,
--                                            MEMTXATTRS_UNSPECIFIED)) {
-+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
-                 return false;
-             }
-         }
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-     rcu_read_lock();
-     fv = address_space_to_flatview(as);
--    result = flatview_access_valid(fv, addr, len, is_write);
-+    result = flatview_access_valid(fv, addr, len, is_write, attrs);
-     rcu_read_unlock();
-     return result;
- }
---
-.17.1

-[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_translate(); all its
-callers now have attrs available.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
----
- include/exec/memory.h |  7 ++++---
- exec.c                | 17 +++++++++--------
-files changed, 13 insertions(+), 11 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-  */
- MemoryRegion *flatview_translate(FlatView *fv,
-                                  hwaddr addr, hwaddr *xlat,
--                                 hwaddr *len, bool is_write);
-+                                 hwaddr *len, bool is_write,
-+                                 MemTxAttrs attrs);
- static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     hwaddr addr, hwaddr *xlat,
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     MemTxAttrs attrs)
- {
-     return flatview_translate(address_space_to_flatview(as),
--                              addr, xlat, len, is_write);
-+                              addr, xlat, len, is_write, attrs);
- }
- /* address_space_access_valid: check for validity of accessing an address
-@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
-             rcu_read_lock();
-             fv = address_space_to_flatview(as);
-             l = len;
--            mr = flatview_translate(fv, addr, &addr1, &l, false);
-+            mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-             if (len == l && memory_access_is_direct(mr, false)) {
-                 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
-                 memcpy(buf, ptr, len);
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ iotlb_fail:
- /* Called from RCU critical section */
- MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
--                                 hwaddr *plen, bool is_write)
-+                                 hwaddr *plen, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     MemoryRegion *mr;
-     MemoryRegionSection section;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
-         }
-         l = len;
--        mr = flatview_translate(fv, addr, &addr1, &l, true);
-+        mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
-     }
-     return result;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
-     MemTxResult result = MEMTX_OK;
-     l = len;
--    mr = flatview_translate(fv, addr, &addr1, &l, true);
-+    mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
-     result = flatview_write_continue(fv, addr, attrs, buf, len,
-                                      addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
-         }
-         l = len;
--        mr = flatview_translate(fv, addr, &addr1, &l, false);
-+        mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-     }
-     return result;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = flatview_translate(fv, addr, &addr1, &l, false);
-+    mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-     return flatview_read_continue(fv, addr, attrs, buf, len,
-                                   addr1, l, mr);
- }
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-     while (len > 0) {
-         l = len;
--        mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-+        mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
-             if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
-@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
-         len = target_len;
-         this_mr = flatview_translate(fv, addr, &xlat,
--                                                   &len, is_write);
-+                                     &len, is_write, attrs);
-         if (this_mr != mr || xlat != base + done) {
-             return done;
-         }
-@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
-     l = len;
-     rcu_read_lock();
-     fv = address_space_to_flatview(as);
--    mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-+    mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
-     if (!memory_access_is_direct(mr, is_write)) {
-         if (atomic_xchg(&bounce.in_use, true)) {
---
-.17.1

-[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_get_iotlb_entry().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
----
- include/exec/memory.h | 2 +-
- exec.c                | 2 +-
- hw/virtio/vhost.c     | 3 ++-
-files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
-  * entry. Should be called from an RCU critical section.
-  */
- IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
--                                            bool is_write);
-+                                            bool is_write, MemTxAttrs attrs);
- /* address_space_translate: translate an address range into an address space
-  * into a MemoryRegion and an address range into that section.  Should be
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
- /* Called from RCU critical section */
- IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
--                                            bool is_write)
-+                                            bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegionSection section;
-     hwaddr xlat, page_mask;
-diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/virtio/vhost.c
-+++ b/hw/virtio/vhost.c
-@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
-     trace_vhost_iotlb_miss(dev, 1);
-     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
--                                          iova, write);
-+                                          iova, write,
-+                                          MEMTXATTRS_UNSPECIFIED);
-     if (iotlb.target_as != NULL) {
-         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
-                                          &uaddr, &len);
---
-.17.1

-[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_do_translate().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
----
- exec.c | 9 ++++++---
-file changed, 6 insertions(+), 3 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ unassigned:
-  * @is_write: whether the translation operation is for write
-  * @is_mmio: whether this can be MMIO, set true if it can
-  * @target_as: the address space targeted by the IOMMU
-+ * @attrs: memory transaction attributes
-  *
-  * This function is called from RCU critical section
-  */
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-                                                  hwaddr *page_mask_out,
-                                                  bool is_write,
-                                                  bool is_mmio,
--                                                 AddressSpace **target_as)
-+                                                 AddressSpace **target_as,
-+                                                 MemTxAttrs attrs)
- {
-     MemoryRegionSection *section;
-     IOMMUMemoryRegion *iommu_mr;
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-      * but page mask.
-      */
-     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
--                                    NULL, &page_mask, is_write, false, &as);
-+                                    NULL, &page_mask, is_write, false, &as,
-+                                    attrs);
-     /* Illegal translation */
-     if (section.mr == &io_mem_unassigned) {
-@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
-     /* This can be MMIO, so setup MMIO bit. */
-     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
--                                    is_write, true, &as);
-+                                    is_write, true, &as, attrs);
-     mr = section.mr;
-     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
---
-.17.1

-[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_translate_iommu().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
----
- exec.c | 8 +++++---
-file changed, 5 insertions(+), 3 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
-  * @is_write: whether the translation operation is for write
-  * @is_mmio: whether this can be MMIO, set true if it can
-  * @target_as: the address space targeted by the IOMMU
-+ * @attrs: transaction attributes
-  *
-  * This function is called from RCU critical section.  It is the common
-  * part of flatview_do_translate and address_space_translate_cached.
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
-                                                          hwaddr *page_mask_out,
-                                                          bool is_write,
-                                                          bool is_mmio,
--                                                         AddressSpace **target_as)
-+                                                         AddressSpace **target_as,
-+                                                         MemTxAttrs attrs)
- {
-     MemoryRegionSection *section;
-     hwaddr page_mask = (hwaddr)-1;
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-         return address_space_translate_iommu(iommu_mr, xlat,
-                                              plen_out, page_mask_out,
-                                              is_write, is_mmio,
--                                             target_as);
-+                                             target_as, attrs);
-     }
-     if (page_mask_out) {
-         /* Not behind an IOMMU, use default page size. */
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
-     section = address_space_translate_iommu(iommu_mr, xlat, plen,
-                                             NULL, is_write, true,
--                                            &target_as);
-+                                            &target_as, attrs);
-     return section.mr;
- }
---
-.17.1

-[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
+Deleted patch
-Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
-and friends.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
----
- include/migration/vmstate.h | 3 +++
-file changed, 3 insertions(+)
-diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/migration/vmstate.h
-+++ b/include/migration/vmstate.h
-@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
- #define VMSTATE_BOOL_ARRAY(_f, _s, _n)                               \
-     VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
-+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num)                \
-+    VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
-+
- #define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v)                         \
-     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
---
-.17.1

target-arm queue. This has the "plumb txattrs through various
bits of exec.c" patches, and a collection of bug fixes from
various people.

thanks
-- PMM

The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:

Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531

for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm: Honour FPCR.FZ in FRECPX
 * MAINTAINERS: Add entries for newer MPS2 boards and devices
 * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
 * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
   GIC state
 * tcg: Fix helper function vs host abi for float16
 * arm: fix qemu crash on startup with -bios option
 * arm: fix malloc type mismatch
 * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
 * Correct CPACR reset value for v7 cores
 * memory.h: Improve IOMMU related documentation
 * exec: Plumb transaction attributes through various functions in
   preparation for allowing IOMMUs to see them
 * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
 * ARM: ACPI: Fix use-after-free due to memory realloc
 * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

----------------------------------------------------------------
Francisco Iglesias (1):
      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

Igor Mammedov (1):
      arm: fix qemu crash on startup with -bios option

Jan Kiszka (1):
      hw/intc/arm_gicv3: Fix APxR<n> register dispatching

Paolo Bonzini (1):
      arm: fix malloc type mismatch

Peter Maydell (17):
      target/arm: Honour FPCR.FZ in FRECPX
      MAINTAINERS: Add entries for newer MPS2 boards and devices
      Correct CPACR reset value for v7 cores
      memory.h: Improve IOMMU related documentation
      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
      Make address_space_translate{, _cached}() take a MemTxAttrs argument
      Make address_space_map() take a MemTxAttrs argument
      Make address_space_access_valid() take a MemTxAttrs argument
      Make flatview_extend_translation() take a MemTxAttrs argument
      Make memory_region_access_valid() take a MemTxAttrs argument
      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
      Make flatview_access_valid() take a MemTxAttrs argument
      Make flatview_translate() take a MemTxAttrs argument
      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
      Make flatview_do_translate() take a MemTxAttrs argument
      Make address_space_translate_iommu take a MemTxAttrs argument
      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

Richard Henderson (1):
      tcg: Fix helper function vs host abi for float16

Shannon Zhao (3):
      arm_gicv3_kvm: increase clroffset accordingly
      ARM: ACPI: Fix use-after-free due to memory realloc
      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
---
 target/arm/helper-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
         return nan;
     }
 
+    a = float16_squash_input_denormal(a, fpst);
+
     val16 = float16_val(a);
     sbit = 0x8000 & val16;
     exp = extract32(val16, 10, 5);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         return nan;
     }
 
+    a = float32_squash_input_denormal(a, fpst);
+
     val32 = float32_val(a);
     sbit = 0x80000000ULL & val32;
     exp = extract32(val32, 23, 8);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         return nan;
     }
 
+    a = float64_squash_input_denormal(a, fpst);
+
     val64 = float64_val(a);
     sbit = 0x8000000000000000ULL & val64;
     exp = extract64(float64_val(a), 52, 11);
-- 
2.17.1

Add entries to MAINTAINERS to cover the newer MPS2 boards and
the new devices they use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
---
 MAINTAINERS | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
 F: include/hw/timer/cmsdk-apb-timer.h
 F: hw/char/cmsdk-apb-uart.c
 F: include/hw/char/cmsdk-apb-uart.h
+F: hw/misc/tz-ppc.c
+F: include/hw/misc/tz-ppc.h
 
 ARM cores
 M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/mps2.c
-F: hw/misc/mps2-scc.c
-F: include/hw/misc/mps2-scc.h
+F: hw/arm/mps2-tz.c
+F: hw/misc/mps2-*.c
+F: include/hw/misc/mps2-*.h
+F: hw/arm/iotkit.c
+F: include/hw/arm/iotkit.h
 
 Musicpal
 M: Jan Kiszka <jan.kiszka@web.de>
-- 
2.17.1

From: Jan Kiszka <jan.kiszka@siemens.com>

There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.

Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value = cs->ich_apr[grp][regno];
 
     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
     uint64_t value;
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
     GICv3CPUState *cs = icc_cs_from_env(env);
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value;
 
     value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.

Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-stable@nongnu.org
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_kvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
         if (clroffset != 0) {
             reg = 0;
             kvm_gicd_access(s, clroffset, &reg, true);
+            clroffset += 4;
         }
         reg = *gic_bmp_ptr32(bmp, irq);
         kvm_gicd_access(s, offset, &reg, true);
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Depending on the host abi, float16, aka uint16_t, values are
passed and returned either zero-extended in the host register
or with garbage at the top of the host register.

The tcg code generator has so far been assuming garbage, as that
matches the x86 abi, but this is incorrect for other host abis.
Further, target/arm has so far been assuming zero-extended results,
so that it may store the 16-bit value into a 32-bit slot with the
high 16-bits already clear.

Rectify both problems by mapping "f16" in the helper definition
to uint32_t instead of (a typedef for) uint16_t.  This forces
the host compiler to assume garbage in the upper 16 bits on input
and to zero-extend the result on output.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/helper-head.h |  2 +-
 target/arm/helper-a64.c    | 35 +++++++++--------
 target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 3 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_int int
 #define dh_ctype_i64 uint64_t
 #define dh_ctype_s64 int64_t
-#define dh_ctype_f16 float16
+#define dh_ctype_f16 uint32_t
 #define dh_ctype_f32 float32
 #define dh_ctype_f64 float64
 #define dh_ctype_ptr void *
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
     return flags;
 }
 
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
 }
 
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare(x, y, fp_status));
 }
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 #define float64_three make_float64(0x4008000000000000ULL)
 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
     return float64_muladd(a, b, float64_two, 0, fpst);
 }
 
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 }
 
 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
     uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
 #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
 
 #define ADVSIMD_HALFOP(name) \
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
 { \
     float_status *fpst = fpstp; \
     return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
 ADVSIMD_TWOHALFOP(mulx)
 
 /* fused multiply-accumulate */
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
+                                 void *fpstp)
 {
     float_status *fpst = fpstp;
     return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
 
 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare_quiet(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_greater);
 }
 
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 }
 
 /* round to integral */
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
 {
     return float16_round_to_int(x, fp_status);
 }
 
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
 {
     int old_flags = get_float_exception_flags(fp_status), new_flags;
     float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
  * setting the mode appropriately before calling the helper.
  */
 
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
     return float16_to_int16(a, fpst);
 }
 
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
  * Square Root and Reciprocal square root
  */
 
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
 {
     float_status *s = fpstp;
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
 
 /* Integer to float and float to integer conversions */
 
-#define CONV_ITOF(name, fsz, sign) \
-    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
+#define CONV_ITOF(name, ftype, fsz, sign)                           \
+ftype HELPER(name)(uint32_t x, void *fpstp)                         \
+{                                                                   \
+    float_status *fpst = fpstp;                                     \
+    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
 }
 
-#define CONV_FTOI(name, fsz, sign, round) \
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    if (float##fsz##_is_any_nan(x)) { \
-        float_raise(float_flag_invalid, fpst); \
-        return 0; \
-    } \
-    return float##fsz##_to_##sign##int32##round(x, fpst); \
+#define CONV_FTOI(name, ftype, fsz, sign, round)                \
+uint32_t HELPER(name)(ftype x, void *fpstp)                     \
+{                                                               \
+    float_status *fpst = fpstp;                                 \
+    if (float##fsz##_is_any_nan(x)) {                           \
+        float_raise(float_flag_invalid, fpst);                  \
+        return 0;                                               \
+    }                                                           \
+    return float##fsz##_to_##sign##int32##round(x, fpst);       \
 }
 
-#define FLOAT_CONVS(name, p, fsz, sign) \
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
+#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
+    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
+    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
+    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 
-FLOAT_CONVS(si, h, 16, )
-FLOAT_CONVS(si, s, 32, )
-FLOAT_CONVS(si, d, 64, )
-FLOAT_CONVS(ui, h, 16, u)
-FLOAT_CONVS(ui, s, 32, u)
-FLOAT_CONVS(ui, d, 64, u)
+FLOAT_CONVS(si, h, uint32_t, 16, )
+FLOAT_CONVS(si, s, float32, 32, )
+FLOAT_CONVS(si, d, float64, 64, )
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
+FLOAT_CONVS(ui, s, float32, 32, u)
+FLOAT_CONVS(ui, d, float64, 64, u)
 
 #undef CONV_ITOF
 #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
     return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
 }
 
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
 }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
     }
 }
 
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
 }
 
 /* Half precision conversions.  */
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
     g_assert_not_reached();
 }
 
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
     return extract64(estimate, 0, 8) << 44;
 }
 
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
 {
     float_status *s = fpstp;
     float16 f16 = float16_squash_input_denormal(input, s);
-- 
2.17.1

From: Igor Mammedov <imammedo@redhat.com>

When QEMU is started with following CLI
 -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
it crashes with abort at
 accel/kvm/kvm-all.c:2164:
 KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument

Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
arm_gicv3_icc_reset() where the later is called by CPU reset
reset callback.

However commit:
 3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
broke CPU reset callback registration in case

arm_load_kernel()
      ...
      if (!info->kernel_filename || info->firmware_loaded)

branch is taken, i.e. it's sufficient to provide a firmware
or do not provide kernel on CLI to skip cpu reset callback
registration, where before offending commit the callback
has been registered unconditionally.

Fix it by registering the callback right at the beginning of
arm_load_kernel() unconditionally instead of doing it at the end.

NOTE:
 we probably should eliminate that dependency anyways as well as
 separate arch CPU reset parts from arm_load_kernel() into CPU
 itself, but that refactoring that I probably would have to do
 anyways later for CPU hotplug to work.

Reported-by: Auger Eric <eric.auger@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
     static const ARMInsnFixup *primary_loader;
     AddressSpace *as = arm_boot_address_space(cpu, info);
 
+    /* CPU objects (unlike devices) are not automatically reset on system
+     * reset, so we must always register a handler to do so. If we're
+     * actually loading a kernel, the handler is also responsible for
+     * arranging that we start it correctly.
+     */
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+    }
+
     /* The board code is not supposed to set secure_board_setup unless
      * running its code in secure mode is actually possible, and KVM
      * doesn't support secure.
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
         ARM_CPU(cs)->env.boot_info = info;
     }
 
-    /* CPU objects (unlike devices) are not automatically reset on system
-     * reset, so we must always register a handler to do so. If we're
-     * actually loading a kernel, the handler is also responsible for
-     * arranging that we start it correctly.
-     */
-    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
-        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
-    }
-
     if (!info->skip_dtb_autoload && have_dtb(info)) {
         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
             exit(1);
-- 
2.17.1

From: Paolo Bonzini <pbonzini@redhat.com>

cpregs_keys is an uint32_t* so the allocation should use uint32_t.
g_new is even better because it is type-safe.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
     RegisterSysregXmlParam param = {cs, s};
 
     cpu->dyn_xml.num_cpregs = 0;
-    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
-                                        g_hash_table_size(cpu->cp_regs));
+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
-- 
2.17.1

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Coverity found that the string return by 'object_get_canonical_path' was not
being freed at two locations in the model (CID 1391294 and CID 1391293) and
also that a memset was being called with a value greater than the max of a byte
on the second argument (CID 1391286). This patch corrects this by adding the
freeing of the strings and also changing to memset to zero instead on
descriptor unaligned errors.

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx-zdma.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/xlnx-zdma.c
+++ b/hw/dma/xlnx-zdma.c
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
         qemu_log_mask(LOG_GUEST_ERROR,
                       "zdma: unaligned descriptor at %" PRIx64,
                       addr);
-        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
         s->error = true;
         return false;
     }
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr, value);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return;
-- 
2.17.1

In commit f0aff255700 we made cpacr_write() enforce that some CPACR
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
we forgot to also update the register's reset value. The effect
was that (a) a guest that read CPACR on reset would not see ones in
the RAO bits, and (b) if you did a migration before the guest did
a write to the CPACR then the migration would fail because the
destination would enforce the RAO bits and then complain that they
didn't match the zero value from the source.

Implement reset for the CPACR using a custom reset function
that just calls cpacr_write(), to avoid having to duplicate
the logic for which bits are RAO.

This bug would affect migration for TCG CPUs which are ARMv7
with VFP but without one of Neon or VFPv3.

Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     env->cp15.cpacr_el1 = value;
 }
 
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /* Call cpacr_write() so that we reset with the correct RAO bits set
+     * for our CPU features.
+     */
+    cpacr_write(env, ri, 0);
+}
+
 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
-      .resetvalue = 0, .writefn = cpacr_write },
+      .resetfn = cpacr_reset, .writefn = cpacr_write },
     REGINFO_SENTINEL
 };
 
-- 
2.17.1

Add more detail to the documentation for memory_region_init_iommu()
and other IOMMU-related functions and data structures.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
---
 include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 95 insertions(+), 10 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
     IOMMU_ATTR_SPAPR_TCE_FD
 };
 
+/**
+ * IOMMUMemoryRegionClass:
+ *
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
+ * and provide an implementation of at least the @translate method here
+ * to handle requests to the memory region. Other methods are optional.
+ *
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
+ * to report whenever mappings are changed, by calling
+ * memory_region_notify_iommu() (or, if necessary, by calling
+ * memory_region_notify_one() for each registered notifier).
+ */
 typedef struct IOMMUMemoryRegionClass {
     /* private */
     struct DeviceClass parent_class;
 
     /*
-     * Return a TLB entry that contains a given address. Flag should
-     * be the access permission of this translation operation. We can
-     * set flag to IOMMU_NONE to mean that we don't need any
-     * read/write permission checks, like, when for region replay.
+     * Return a TLB entry that contains a given address.
+     *
+     * The IOMMUAccessFlags indicated via @flag are optional and may
+     * be specified as IOMMU_NONE to indicate that the caller needs
+     * the full translation information for both reads and writes. If
+     * the access flags are specified then the IOMMU implementation
+     * may use this as an optimization, to stop doing a page table
+     * walk as soon as it knows that the requested permissions are not
+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
+     * full page table walk and report the permissions in the returned
+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
+     * return different mappings for reads and writes.)
+     *
+     * The returned information remains valid while the caller is
+     * holding the big QEMU lock or is inside an RCU critical section;
+     * if the caller wishes to cache the mapping beyond that it must
+     * register an IOMMU notifier so it can invalidate its cached
+     * information when the IOMMU mapping changes.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @hwaddr: address to be translated within the memory region
+     * @flag: requested access permissions
      */
     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
                                IOMMUAccessFlags flag);
-    /* Returns minimum supported page size */
+    /* Returns minimum supported page size in bytes.
+     * If this method is not provided then the minimum is assumed to
+     * be TARGET_PAGE_SIZE.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     */
     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
-    /* Called when IOMMU Notifier flag changed */
+    /* Called when IOMMU Notifier flag changes (ie when the set of
+     * events which IOMMU users are requesting notification for changes).
+     * Optional method -- need not be provided if the IOMMU does not
+     * need to know exactly which events must be notified.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @old_flags: events which previously needed to be notified
+     * @new_flags: events which now need to be notified
+     */
     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
                                 IOMMUNotifierFlag old_flags,
                                 IOMMUNotifierFlag new_flags);
-    /* Set this up to provide customized IOMMU replay function */
+    /* Called to handle memory_region_iommu_replay().
+     *
+     * The default implementation of memory_region_iommu_replay() is to
+     * call the IOMMU translate method for every page in the address space
+     * with flag == IOMMU_NONE and then call the notifier if translate
+     * returns a valid mapping. If this method is implemented then it
+     * overrides the default behaviour, and must provide the full semantics
+     * of memory_region_iommu_replay(), by calling @notifier for every
+     * translation present in the IOMMU.
+     *
+     * Optional method -- an IOMMU only needs to provide this method
+     * if the default is inefficient or produces undesirable side effects.
+     *
+     * Note: this is not related to record-and-replay functionality.
+     */
     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
 
-    /* Get IOMMU misc attributes */
-    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
+    /* Get IOMMU misc attributes. This is an optional method that
+     * can be used to allow users of the IOMMU to get implementation-specific
+     * information. The IOMMU implements this method to handle calls
+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
+     * the IOMMU supports. If the method is unimplemented then
+     * memory_region_iommu_get_attr() will always return -EINVAL.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @attr: attribute being queried
+     * @data: memory to fill in with the attribute data
+     *
+     * Returns 0 on success, or a negative errno; in particular
+     * returns -EINVAL for unrecognized or unimplemented attribute types.
+     */
+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
                     void *data);
 } IOMMUMemoryRegionClass;
 
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
  * An IOMMU region translates addresses and forwards accesses to a target
  * memory region.
  *
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
+ * @_iommu_mr should be a pointer to enough memory for an instance of
+ * that subclass, @instance_size is the size of that subclass, and
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
+ * instance of the subclass, and its methods will then be called to handle
+ * accesses to the memory region. See the documentation of
+ * #IOMMUMemoryRegionClass for further details.
+ *
  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
  * @instance_size: the IOMMUMemoryRegion subclass instance size
  * @mrtypename: the type name of the #IOMMUMemoryRegion
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
  * a notifier with the minimum page granularity returned by
  * mr->iommu_ops->get_page_size().
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  * @n: the notifier to which to replay iommu mappings
  */
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
  * memory_region_iommu_replay_all: replay existing IOMMU translations
  * to all the notifiers registered.
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  */
 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
  * defined on the IOMMU.
  *
- * Returns 0 if succeded, error code otherwise.
+ * Returns 0 on success, or a negative errno otherwise. In particular,
+ * -EINVAL indicates that the IOMMU does not support the requested
+ * attribute.
  *
  * @iommu_mr: the memory region
  * @attr: the requested attribute
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
---
 include/exec/exec-all.h   | 5 +++--
 accel/tcg/translate-all.c | 2 +-
 exec.c                    | 2 +-
 target/xtensa/op_helper.c | 3 ++-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                   hwaddr paddr, int prot,
                   int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
                  uintptr_t retaddr);
 #else
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                        uint16_t idxmap)
 {
 }
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
+                                           MemTxAttrs attrs)
 {
 }
 #endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 {
     ram_addr_t ram_addr;
     MemoryRegion *mr;
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
     if (phys != -1) {
         /* Locks grabbed by tb_invalidate_phys_addr */
         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
-                                phys | (pc & ~TARGET_PAGE_MASK));
+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
     }
 }
 #endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
             &paddr, &page_size, &access);
     if (ret == 0) {
-        tb_invalidate_phys_addr(&address_space_memory, paddr);
+        tb_invalidate_phys_addr(&address_space_memory, paddr,
+                                MEMTXATTRS_UNSPECIFIED);
     }
 }
 
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate()
and address_space_translate_cached(). Callers either have an
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
---
 include/exec/memory.h     |  4 +++-
 accel/tcg/translate-all.c |  2 +-
 exec.c                    | 14 +++++++++-----
 hw/vfio/common.c          |  3 ++-
 memory_ldst.inc.c         | 18 +++++++++---------
 target/riscv/helper.c     |  2 +-
 6 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
  * #MemoryRegion.
  * @len: pointer to length
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 MemoryRegion *flatview_translate(FlatView *fv,
                                  hwaddr addr, hwaddr *xlat,
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
 
 static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                     hwaddr addr, hwaddr *xlat,
-                                                    hwaddr *len, bool is_write)
+                                                    hwaddr *len, bool is_write,
+                                                    MemTxAttrs attrs)
 {
     return flatview_translate(address_space_to_flatview(as),
                               addr, xlat, len, is_write);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
     hwaddr l = 1;
 
     rcu_read_lock();
-    mr = address_space_translate(as, addr, &addr, &l, false);
+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
     if (!(memory_region_is_ram(mr)
           || memory_region_is_romd(mr))) {
         rcu_read_unlock();
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
     rcu_read_lock();
     while (len > 0) {
         l = len;
-        mr = address_space_translate(as, addr, &addr1, &l, true);
+        mr = address_space_translate(as, addr, &addr1, &l, true,
+                                     MEMTXATTRS_UNSPECIFIED);
 
         if (!(memory_region_is_ram(mr) ||
               memory_region_is_romd(mr))) {
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
  */
 static inline MemoryRegion *address_space_translate_cached(
     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
-    hwaddr *plen, bool is_write)
+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     MemoryRegion *mr;
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_read_continue(cache->fv,
                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                            addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_write_continue(cache->fv,
                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                             addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
 
     rcu_read_lock();
     mr = address_space_translate(&address_space_memory,
-                                 phys_addr, &phys_addr, &l, false);
+                                 phys_addr, &phys_addr, &l, false,
+                                 MEMTXATTRS_UNSPECIFIED);
 
     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
     rcu_read_unlock();
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
      */
     mr = address_space_translate(&address_space_memory,
                                  iotlb->translated_addr,
-                                 &xlat, &len, writable);
+                                 &xlat, &len, writable,
+                                 MEMTXATTRS_UNSPECIFIED);
     if (!memory_region_is_ram(mr)) {
         error_report("iommu map to non memory area %"HWADDR_PRIx"",
                      xlat);
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 4 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 8 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (!IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 2 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (!IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 2 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 8 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -XXX,XX +XXX,XX @@ restart:
                 MemoryRegion *mr;
                 hwaddr l = sizeof(target_ulong), addr1;
                 mr = address_space_translate(cs->as, pte_addr,
-                    &addr1, &l, false);
+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
                 if (memory_access_is_direct(mr, true)) {
                     target_ulong *pte_pa =
                         qemu_map_ram_ptr(mr->ram_block, addr1);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_map().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
---
 include/exec/memory.h   | 3 ++-
 include/sysemu/dma.h    | 3 ++-
 exec.c                  | 6 ++++--
 target/ppc/mmu-hash64.c | 3 ++-
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
  * @addr: address within that address space
  * @plen: pointer to length of buffer; updated on return
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 void *address_space_map(AddressSpace *as, hwaddr addr,
-                        hwaddr *plen, bool is_write);
+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
 
 /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
     hwaddr xlen = *len;
     void *p;
 
-    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
+                          MEMTXATTRS_UNSPECIFIED);
     *len = xlen;
     return p;
 }
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
 void *address_space_map(AddressSpace *as,
                         hwaddr addr,
                         hwaddr *plen,
-                        bool is_write)
+                        bool is_write,
+                        MemTxAttrs attrs)
 {
     hwaddr len = *plen;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
                               hwaddr *plen,
                               int is_write)
 {
-    return address_space_map(&address_space_memory, addr, plen, is_write);
+    return address_space_map(&address_space_memory, addr, plen, is_write,
+                             MEMTXATTRS_UNSPECIFIED);
 }
 
 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
         return NULL;
     }
 
-    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
+                              MEMTXATTRS_UNSPECIFIED);
     if (plen < (n * HASH_PTE_SIZE_64)) {
         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
---
 include/exec/memory.h      | 4 +++-
 include/sysemu/dma.h       | 3 ++-
 exec.c                     | 3 ++-
 target/s390x/diag.c        | 6 ++++--
 target/s390x/excp_helper.c | 3 ++-
 target/s390x/mmu_helper.c  | 3 ++-
 target/s390x/sigp.c        | 3 ++-
 7 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
  * @addr: address within that address space
  * @len: length of the area to be checked
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
+                                bool is_write, MemTxAttrs attrs);
 
 /* address_space_map: map a physical memory region into a host virtual address
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
                                     DMADirection dir)
 {
     return address_space_access_valid(as, addr, len,
-                                      dir == DMA_DIRECTION_FROM_DEVICE);
+                                      dir == DMA_DIRECTION_FROM_DEVICE,
+                                      MEMTXATTRS_UNSPECIFIED);
 }
 
 static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
 }
 
 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-                                int len, bool is_write)
+                                int len, bool is_write,
+                                MemTxAttrs attrs)
 {
     FlatView *fv;
     bool result;
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/diag.c
+++ b/target/s390x/diag.c
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), false)) {
+                                        sizeof(IplParameterBlock), false,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
@@ -XXX,XX +XXX,XX @@ out:
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), true)) {
+                                        sizeof(IplParameterBlock), true,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
 
     /* check out of RAM access */
     if (!address_space_access_valid(&address_space_memory, raddr,
-                                    TARGET_PAGE_SIZE, rw)) {
+                                    TARGET_PAGE_SIZE, rw,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                 (uint64_t)raddr, (uint64_t)ram_size);
         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
             return ret;
         }
         if (!address_space_access_valid(&address_space_memory, pages[i],
-                                        TARGET_PAGE_SIZE, is_write)) {
+                                        TARGET_PAGE_SIZE, is_write,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
             return -EFAULT;
         }
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
     cpu_synchronize_state(cs);
 
     if (!address_space_access_valid(&address_space_memory, addr,
-                                    sizeof(struct LowCore), false)) {
+                                    sizeof(struct LowCore), false,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
         return;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_extend_translation().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
 static hwaddr
 flatview_extend_translation(FlatView *fv, hwaddr addr,
-                                 hwaddr target_len,
-                                 MemoryRegion *mr, hwaddr base, hwaddr len,
-                                 bool is_write)
+                            hwaddr target_len,
+                            MemoryRegion *mr, hwaddr base, hwaddr len,
+                            bool is_write, MemTxAttrs attrs)
 {
     hwaddr done = 0;
     hwaddr xlat;
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
 
     memory_region_ref(mr);
     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
-                                             l, is_write);
+                                        l, is_write, attrs);
     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
     rcu_read_unlock();
 
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
     mr = cache->mrs.mr;
     memory_region_ref(mr);
     if (memory_access_is_direct(mr, is_write)) {
+        /* We don't care about the memory attributes here as we're only
+         * doing this if we found actual RAM, which behaves the same
+         * regardless of attributes; so UNSPECIFIED is fine.
+         */
         l = flatview_extend_translation(cache->fv, addr, len, mr,
-                                        cache->xlat, l, is_write);
+                                        cache->xlat, l, is_write,
+                                        MEMTXATTRS_UNSPECIFIED);
         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
     } else {
         cache->ptr = NULL;
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to memory_region_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

The callsite in flatview_access_valid() is part of a recursive
loop flatview_access_valid() -> memory_region_access_valid() ->
 subpage_accepts() -> flatview_access_valid(); we make it pass
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
have plumbed an attrs parameter through the rest of the loop
and we can add an attrs parameter to flatview_access_valid().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
---
 include/exec/memory-internal.h | 3 ++-
 exec.c                         | 4 +++-
 hw/s390x/s390-pci-inst.c       | 3 ++-
 memory.c                       | 7 ++++---
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
 extern const MemoryRegionOps unassigned_mem_ops;
 
 bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
-                                unsigned size, bool is_write);
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs);
 
 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
+            /* When our callers all have attrs we'll pass them through here */
+            if (!memory_region_access_valid(mr, xlat, l, is_write,
+                                            MEMTXATTRS_UNSPECIFIED)) {
                 return false;
             }
         }
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
     mr = s390_get_subregion(mr, offset, len);
     offset -= mr->addr;
 
-    if (!memory_region_access_valid(mr, offset, len, true)) {
+    if (!memory_region_access_valid(mr, offset, len, true,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
         return 0;
     }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
 bool memory_region_access_valid(MemoryRegion *mr,
                                 hwaddr addr,
                                 unsigned size,
-                                bool is_write)
+                                bool is_write,
+                                MemTxAttrs attrs)
 {
     int access_size_min, access_size_max;
     int access_size, i;
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
 {
     MemTxResult r;
 
-    if (!memory_region_access_valid(mr, addr, size, false)) {
+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
         *pval = unassigned_mem_read(mr, addr, size);
         return MEMTX_DECODE_ERROR;
     }
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
                                          unsigned size,
                                          MemTxAttrs attrs)
 {
-    if (!memory_region_access_valid(mr, addr, size, true)) {
+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
         unassigned_mem_write(mr, addr, data, size);
         return MEMTX_DECODE_ERROR;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
callback. We'll need this for subpage_accepts().

We could take the approach we used with the read and write
callbacks and add new a new _with_attrs version, but since there
are so few implementations of the accepts hook we just change
them all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
---
 include/exec/memory.h |  3 ++-
 exec.c                |  9 ++++++---
 hw/hppa/dino.c        |  3 ++-
 hw/nvram/fw_cfg.c     | 12 ++++++++----
 hw/scsi/esp.c         |  3 ++-
 hw/xen/xen_pt_msi.c   |  3 ++-
 memory.c              |  5 +++--
 7 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
          * as a machine check exception).
          */
         bool (*accepts)(void *opaque, hwaddr addr,
-                        unsigned size, bool is_write);
+                        unsigned size, bool is_write,
+                        MemTxAttrs attrs);
     } valid;
     /* Internal implementation constraints: */
     struct {
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
 }
 
 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
 }
 
 static bool subpage_accepts(void *opaque, hwaddr addr,
-                            unsigned len, bool is_write)
+                            unsigned len, bool is_write,
+                            MemTxAttrs attrs)
 {
     subpage_t *subpage = opaque;
 #if defined(DEBUG_SUBPAGE)
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/hppa/dino.c
+++ b/hw/hppa/dino.c
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
 }
 
 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
-                                unsigned size, bool is_write)
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs)
 {
     switch (addr) {
     case DINO_IAR0:
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
                          (size == 8 && addr == 0));
 }
 
 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                  unsigned size, bool is_write,
+                                  MemTxAttrs attrs)
 {
     return addr == 0;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write && size == 2;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                              unsigned size, bool is_write,
+                              MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 2);
 }
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 }
 
 static bool esp_mem_accepts(void *opaque, hwaddr addr,
-                            unsigned size, bool is_write)
+                            unsigned size, bool is_write,
+                            MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 4);
 }
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/xen/xen_pt_msi.c
+++ b/hw/xen/xen_pt_msi.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
 }
 
 static bool pci_msix_accepts(void *opaque, hwaddr addr,
-                             unsigned size, bool is_write)
+                             unsigned size, bool is_write,
+                             MemTxAttrs attrs)
 {
     return !(addr & (size - 1));
 }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
-                                   unsigned size, bool is_write)
+                                   unsigned size, bool is_write,
+                                   MemTxAttrs attrs)
 {
     return false;
 }
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
     access_size = MAX(MIN(size, access_size_max), access_size_min);
     for (i = 0; i < size; i += access_size) {
         if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
-                                    is_write)) {
+                                    is_write, attrs)) {
             return false;
         }
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_access_valid().
Its callers now all have an attrs value to hand, so we can
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
                                   const uint8_t *buf, int len);
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write);
+                                  bool is_write, MemTxAttrs attrs);
 
 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
                                 unsigned len, MemTxAttrs attrs)
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
 #endif
 
     return flatview_access_valid(subpage->fv, addr + subpage->base,
-                                 len, is_write);
+                                 len, is_write, attrs);
 }
 
 static const MemoryRegionOps subpage_ops = {
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
 }
 
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write)
+                                  bool is_write, MemTxAttrs attrs)
 {
     MemoryRegion *mr;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            /* When our callers all have attrs we'll pass them through here */
-            if (!memory_region_access_valid(mr, xlat, l, is_write,
-                                            MEMTXATTRS_UNSPECIFIED)) {
+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
                 return false;
             }
         }
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
     rcu_read_lock();
     fv = address_space_to_flatview(as);
-    result = flatview_access_valid(fv, addr, len, is_write);
+    result = flatview_access_valid(fv, addr, len, is_write, attrs);
     rcu_read_unlock();
     return result;
 }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_translate(); all its
callers now have attrs available.

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_get_iotlb_entry().

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
  * entry. Should be called from an RCU critical section.
  */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write);
+                                            bool is_write, MemTxAttrs attrs);
 
 /* address_space_translate: translate an address range into an address space
  * into a MemoryRegion and an address range into that section.  Should be
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
 
 /* Called from RCU critical section */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write)
+                                            bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     hwaddr xlat, page_mask;
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
     trace_vhost_iotlb_miss(dev, 1);
 
     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
-                                          iova, write);
+                                          iova, write,
+                                          MEMTXATTRS_UNSPECIFIED);
     if (iotlb.target_as != NULL) {
         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
                                          &uaddr, &len);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_do_translate().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ unassigned:
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: memory transaction attributes
  *
  * This function is called from RCU critical section
  */
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
                                                  hwaddr *page_mask_out,
                                                  bool is_write,
                                                  bool is_mmio,
-                                                 AddressSpace **target_as)
+                                                 AddressSpace **target_as,
+                                                 MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     IOMMUMemoryRegion *iommu_mr;
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
      * but page mask.
      */
     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
-                                    NULL, &page_mask, is_write, false, &as);
+                                    NULL, &page_mask, is_write, false, &as,
+                                    attrs);
 
     /* Illegal translation */
     if (section.mr == &io_mem_unassigned) {
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
 
     /* This can be MMIO, so setup MMIO bit. */
     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
-                                    is_write, true, &as);
+                                    is_write, true, &as, attrs);
     mr = section.mr;
 
     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate_iommu().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: transaction attributes
  *
  * This function is called from RCU critical section.  It is the common
  * part of flatview_do_translate and address_space_translate_cached.
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
                                                          hwaddr *page_mask_out,
                                                          bool is_write,
                                                          bool is_mmio,
-                                                         AddressSpace **target_as)
+                                                         AddressSpace **target_as,
+                                                         MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     hwaddr page_mask = (hwaddr)-1;
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
         return address_space_translate_iommu(iommu_mr, xlat,
                                              plen_out, page_mask_out,
                                              is_write, is_mmio,
-                                             target_as);
+                                             target_as, attrs);
     }
     if (page_mask_out) {
         /* Not behind an IOMMU, use default page size. */
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
 
     section = address_space_translate_iommu(iommu_mr, xlat, plen,
                                             NULL, is_write, true,
-                                            &target_as);
+                                            &target_as, attrs);
     return section.mr;
 }
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. So previous
pointer could not be used any more. It must update the pointer and use
the new one.

Also, previous codes wrongly use le32 conversion of iort->node_offset
for subsequent computations that will result incorrect value if host is
not litlle endian. So use the non-converted one instead.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     AcpiIortItsGroup *its;
     AcpiIortTable *iort;
     AcpiIortSmmu3 *smmu;
-    size_t node_size, iort_length, smmu_offset = 0;
+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
     AcpiIortRC *rc;
 
     iort = acpi_data_push(table_data, sizeof(*iort));
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 
     iort_length = sizeof(*iort);
     iort->node_count = cpu_to_le32(nb_nodes);
-    iort->node_offset = cpu_to_le32(sizeof(*iort));
+    /*
+     * Use a copy in case table_data->data moves during acpi_data_push
+     * operations.
+     */
+    iort_node_offset = sizeof(*iort);
+    iort->node_offset = cpu_to_le32(iort_node_offset);
 
     /* ITS group node */
     node_size =  sizeof(*its) + sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         int irq =  vms->irqmap[VIRT_SMMU];
 
         /* SMMUv3 node */
-        smmu_offset = iort->node_offset + node_size;
+        smmu_offset = iort_node_offset + node_size;
         node_size = sizeof(*smmu) + sizeof(*idmap);
         iort_length += node_size;
         smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->id_count = cpu_to_le32(0xFFFF);
         idmap->output_base = 0;
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
     /* Root Complex Node */
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->output_reference = cpu_to_le32(smmu_offset);
     } else {
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
+    /*
+     * Update the pointer address in case table_data->data moves during above
+     * acpi_data_push operations.
+     */
+    iort = (AcpiIortTable *)(table_data->data + iort_start);
     iort->length = cpu_to_le32(iort_length);
 
     build_header(linker, table_data, (void *)(table_data->data + iort_start),
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
initialize global capability variables. If we call kvm_init_irq_routing in
GIC realize function, previous allocated memory will leak.

Fix this by deleting the unnecessary call.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic_kvm.c   | 1 -
 hw/intc/arm_gicv3_kvm.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
-- 
2.17.1

Last handful of arm patches before softfreeze...

The following changes since commit a98135f727595382e200d04c2996e868b7925a01:

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200317

for you to fetch changes up to e88d3671e3bbd59d385838a4101ea19cdcf47309:

hw/arm/pxa2xx: Do not wire up OHCI for PXA255 (2020-03-17 11:36:48 +0000)

----------------------------------------------------------------
target-arm:
 * hw/arm/pxa2xx: Do not wire up OHCI for PXA255
 * aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
 * m25p80: Improve command handling for Jedec and unsupported commands
 * hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
 * hw/arm/fsl-imx6, imx6ul: Wire up USB controllers
 * hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices

----------------------------------------------------------------
Chen Qun (1):
      hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()

Guenter Roeck (10):
      hw/usb: Add basic i.MX USB Phy support
      hw/arm/fsl-imx6ul: Fix USB interrupt numbers
      hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
      hw/arm/fsl-imx6ul: Wire up USB controllers
      hw/arm/fsl-imx6: Wire up USB controllers
      m25p80: Convert to support tracing
      m25p80: Improve command handling for Jedec commands
      m25p80: Improve command handling for unsupported commands
      aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
      hw/arm/pxa2xx: Do not wire up OHCI for PXA255

From: Guenter Roeck <linux@roeck-us.net>

Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
and i.MX7 SoCs.

The only support really needed - at least to boot Linux - is support
for soft reset, which needs to reset various registers to their initial
value. Otherwise, just record register values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/Makefile.objs         |   2 +
 include/hw/usb/imx-usb-phy.h |  53 +++++++++
 hw/usb/imx-usb-phy.c         | 225 +++++++++++++++++++++++++++++++++++
 MAINTAINERS                  |   2 +
 hw/arm/Kconfig               |   1 +
 hw/usb/Kconfig               |   5 +
 6 files changed, 288 insertions(+)
 create mode 100644 include/hw/usb/imx-usb-phy.h
 create mode 100644 hw/usb/imx-usb-phy.c

diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XEN) += xen-usb.o
 xen-usb.o-cflags := $(LIBUSB_CFLAGS)
 xen-usb.o-libs := $(LIBUSB_LIBS)
 endif
+
+common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o
diff --git a/include/hw/usb/imx-usb-phy.h b/include/hw/usb/imx-usb-phy.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/usb/imx-usb-phy.h
@@ -XXX,XX +XXX,XX @@
+#ifndef IMX_USB_PHY_H
+#define IMX_USB_PHY_H
+
+#include "hw/sysbus.h"
+#include "qemu/bitops.h"
+
+enum IMXUsbPhyRegisters {
+    USBPHY_PWD,
+    USBPHY_PWD_SET,
+    USBPHY_PWD_CLR,
+    USBPHY_PWD_TOG,
+    USBPHY_TX,
+    USBPHY_TX_SET,
+    USBPHY_TX_CLR,
+    USBPHY_TX_TOG,
+    USBPHY_RX,
+    USBPHY_RX_SET,
+    USBPHY_RX_CLR,
+    USBPHY_RX_TOG,
+    USBPHY_CTRL,
+    USBPHY_CTRL_SET,
+    USBPHY_CTRL_CLR,
+    USBPHY_CTRL_TOG,
+    USBPHY_STATUS,
+    USBPHY_DEBUG = 0x14,
+    USBPHY_DEBUG_SET,
+    USBPHY_DEBUG_CLR,
+    USBPHY_DEBUG_TOG,
+    USBPHY_DEBUG0_STATUS,
+    USBPHY_DEBUG1 = 0x1c,
+    USBPHY_DEBUG1_SET,
+    USBPHY_DEBUG1_CLR,
+    USBPHY_DEBUG1_TOG,
+    USBPHY_VERSION,
+    USBPHY_MAX
+};
+
+#define USBPHY_CTRL_SFTRST BIT(31)
+
+#define TYPE_IMX_USBPHY "imx.usbphy"
+#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
+
+typedef struct IMXUSBPHYState {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion iomem;
+
+    uint32_t usbphy[USBPHY_MAX];
+} IMXUSBPHYState;
+
+#endif /* IMX_USB_PHY_H */
diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/usb/imx-usb-phy.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * i.MX USB PHY
+ *
+ * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * We need to implement basic reset control in the PHY control register.
+ * For everything else, it is sufficient to set whatever is written.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/usb/imx-usb-phy.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+
+static const VMStateDescription vmstate_imx_usbphy = {
+    .name = TYPE_IMX_USBPHY,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void imx_usbphy_softreset(IMXUSBPHYState *s)
+{
+    s->usbphy[USBPHY_PWD] = 0x001e1c00;
+    s->usbphy[USBPHY_TX] = 0x10060607;
+    s->usbphy[USBPHY_RX] = 0x00000000;
+    s->usbphy[USBPHY_CTRL] = 0xc0200000;
+}
+
+static void imx_usbphy_reset(DeviceState *dev)
+{
+    IMXUSBPHYState *s = IMX_USBPHY(dev);
+
+    s->usbphy[USBPHY_STATUS] = 0x00000000;
+    s->usbphy[USBPHY_DEBUG] = 0x7f180000;
+    s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
+    s->usbphy[USBPHY_DEBUG1] = 0x00001000;
+    s->usbphy[USBPHY_VERSION] = 0x04020000;
+
+    imx_usbphy_softreset(s);
+}
+
+static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
+{
+    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
+    uint32_t index = offset >> 2;
+    uint32_t value;
+
+    switch (index) {
+    case USBPHY_PWD_SET:
+    case USBPHY_TX_SET:
+    case USBPHY_RX_SET:
+    case USBPHY_CTRL_SET:
+    case USBPHY_DEBUG_SET:
+    case USBPHY_DEBUG1_SET:
+        /*
+         * All REG_NAME_SET register access are in fact targeting the
+         * REG_NAME register.
+         */
+        value = s->usbphy[index - 1];
+        break;
+    case USBPHY_PWD_CLR:
+    case USBPHY_TX_CLR:
+    case USBPHY_RX_CLR:
+    case USBPHY_CTRL_CLR:
+    case USBPHY_DEBUG_CLR:
+    case USBPHY_DEBUG1_CLR:
+        /*
+         * All REG_NAME_CLR register access are in fact targeting the
+         * REG_NAME register.
+         */
+        value = s->usbphy[index - 2];
+        break;
+    case USBPHY_PWD_TOG:
+    case USBPHY_TX_TOG:
+    case USBPHY_RX_TOG:
+    case USBPHY_CTRL_TOG:
+    case USBPHY_DEBUG_TOG:
+    case USBPHY_DEBUG1_TOG:
+        /*
+         * All REG_NAME_TOG register access are in fact targeting the
+         * REG_NAME register.
+         */
+        value = s->usbphy[index - 3];
+        break;
+    default:
+        value = s->usbphy[index];
+        break;
+    }
+    return (uint64_t)value;
+}
+
+static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
+                             unsigned size)
+{
+    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
+    uint32_t index = offset >> 2;
+
+    switch (index) {
+    case USBPHY_CTRL:
+        s->usbphy[index] = value;
+        if (value & USBPHY_CTRL_SFTRST) {
+            imx_usbphy_softreset(s);
+        }
+        break;
+    case USBPHY_PWD:
+    case USBPHY_TX:
+    case USBPHY_RX:
+    case USBPHY_STATUS:
+    case USBPHY_DEBUG:
+    case USBPHY_DEBUG1:
+        s->usbphy[index] = value;
+        break;
+    case USBPHY_CTRL_SET:
+        s->usbphy[index - 1] |= value;
+        if (value & USBPHY_CTRL_SFTRST) {
+            imx_usbphy_softreset(s);
+        }
+        break;
+    case USBPHY_PWD_SET:
+    case USBPHY_TX_SET:
+    case USBPHY_RX_SET:
+    case USBPHY_DEBUG_SET:
+    case USBPHY_DEBUG1_SET:
+        /*
+         * All REG_NAME_SET register access are in fact targeting the
+         * REG_NAME register. So we change the value of the REG_NAME
+         * register, setting bits passed in the value.
+         */
+        s->usbphy[index - 1] |= value;
+        break;
+    case USBPHY_PWD_CLR:
+    case USBPHY_TX_CLR:
+    case USBPHY_RX_CLR:
+    case USBPHY_CTRL_CLR:
+    case USBPHY_DEBUG_CLR:
+    case USBPHY_DEBUG1_CLR:
+        /*
+         * All REG_NAME_CLR register access are in fact targeting the
+         * REG_NAME register. So we change the value of the REG_NAME
+         * register, unsetting bits passed in the value.
+         */
+        s->usbphy[index - 2] &= ~value;
+        break;
+    case USBPHY_CTRL_TOG:
+        s->usbphy[index - 3] ^= value;
+        if ((value & USBPHY_CTRL_SFTRST) &&
+            (s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
+            imx_usbphy_softreset(s);
+        }
+        break;
+    case USBPHY_PWD_TOG:
+    case USBPHY_TX_TOG:
+    case USBPHY_RX_TOG:
+    case USBPHY_DEBUG_TOG:
+    case USBPHY_DEBUG1_TOG:
+        /*
+         * All REG_NAME_TOG register access are in fact targeting the
+         * REG_NAME register. So we change the value of the REG_NAME
+         * register, toggling bits passed in the value.
+         */
+        s->usbphy[index - 3] ^= value;
+        break;
+    default:
+        /* Other registers are read-only */
+        break;
+    }
+}
+
+static const struct MemoryRegionOps imx_usbphy_ops = {
+    .read = imx_usbphy_read,
+    .write = imx_usbphy_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        /*
+         * Our device would not work correctly if the guest was doing
+         * unaligned access. This might not be a limitation on the real
+         * device but in practice there is no reason for a guest to access
+         * this device unaligned.
+         */
+        .min_access_size = 4,
+        .max_access_size = 4,
+        .unaligned = false,
+    },
+};
+
+static void imx_usbphy_realize(DeviceState *dev, Error **errp)
+{
+    IMXUSBPHYState *s = IMX_USBPHY(dev);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
+                          "imx-usbphy", 0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void imx_usbphy_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = imx_usbphy_reset;
+    dc->vmsd = &vmstate_imx_usbphy;
+    dc->desc = "i.MX USB PHY Module";
+    dc->realize = imx_usbphy_realize;
+}
+
+static const TypeInfo imx_usbphy_info = {
+    .name          = TYPE_IMX_USBPHY,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IMXUSBPHYState),
+    .class_init    = imx_usbphy_class_init,
+};
+
+static void imx_usbphy_register_types(void)
+{
+    type_register_static(&imx_usbphy_info);
+}
+
+type_init(imx_usbphy_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/arm/sabrelite.c
 F: hw/arm/fsl-imx6.c
 F: hw/misc/imx6_*.c
 F: hw/ssi/imx_spi.c
+F: hw/usb/imx-usb-phy.c
+F: include/hw/usb/imx-usb-phy.h
 F: include/hw/arm/fsl-imx6.h
 F: include/hw/misc/imx6_*.h
 F: include/hw/ssi/imx_spi.h
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
     select IMX
     select IMX_FEC
     select IMX_I2C
+    select IMX_USBPHY
     select SDHCI
 
 config ASPEED_SOC
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_STORAGE_MTP
     bool
     default y
     depends on USB
+
+config IMX_USBPHY
+    bool
+    default y
+    depends on USB
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

USB1 and USB2 interrupt numbers were swapped. USB_PHY2 interrupt number
is 45. That didn't really matter up to now since the interrupts were not
used, but it needs to be fixed to be able to wire up the USB controllers.

Fixes: 31cbf933f0e ("i.MX6UL: Add i.MX6UL SOC")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-3-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULIRQs {
     FSL_IMX6UL_UART7_IRQ    = 39,
     FSL_IMX6UL_UART8_IRQ    = 40,
 
-    FSL_IMX6UL_USB1_IRQ     = 42,
-    FSL_IMX6UL_USB2_IRQ     = 43,
+    FSL_IMX6UL_USB1_IRQ     = 43,
+    FSL_IMX6UL_USB2_IRQ     = 42,
     FSL_IMX6UL_USB_PHY1_IRQ = 44,
-    FSL_IMX6UL_USB_PHY2_IRQ = 44,
+    FSL_IMX6UL_USB_PHY2_IRQ = 45,
 
     FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
     FSL_IMX6UL_CAAM_ERR_IRQ = 47,
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

Recent Linux kernels (post v4.20) crash due to accesses to flexcan
and pwm controllers. Instantiate as unimplemented devices to work
around the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-4-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/fsl-imx6ul.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
 
+    /*
+     * PWM
+     */
+    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+
+    /*
+     * CAN
+     */
+    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+
     /*
      * APHB_DMA
      */
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

IMX6UL USB controllers are quite similar to IMX7 USB controllers.
Wire them up the same way.

The only real difference is that wiring up phy devices is necessary
to avoid phy reset timeouts in the Linux kernel.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-5-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 10 ++++++++++
 hw/arm/fsl-imx6ul.c         | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/imx_spi.h"
 #include "hw/net/imx_fec.h"
+#include "hw/usb/chipidea.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
 #include "cpu.h"
 
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_I2CS         = 4,
     FSL_IMX6UL_NUM_ECSPIS       = 4,
     FSL_IMX6UL_NUM_ADCS         = 2,
+    FSL_IMX6UL_NUM_USB_PHYS     = 2,
+    FSL_IMX6UL_NUM_USBS         = 2,
 };
 
 typedef struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
     IMXFECState        eth[FSL_IMX6UL_NUM_ETHS];
     SDHCIState         usdhc[FSL_IMX6UL_NUM_USDHCS];
     IMX2WdtState       wdt[FSL_IMX6UL_NUM_WDTS];
+    IMXUSBPHYState     usbphy[FSL_IMX6UL_NUM_USB_PHYS];
+    ChipideaState      usb[FSL_IMX6UL_NUM_USBS];
     MemoryRegion       rom;
     MemoryRegion       caam;
     MemoryRegion       ocram;
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+    FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
+    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
+    FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
+    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/arm/fsl-imx6ul.h"
 #include "hw/misc/unimp.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
                               TYPE_IMX_ENET);
     }
 
+    /* USB */
+    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        snprintf(name, NAME_SIZE, "usbphy%d", i);
+        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
+                              TYPE_IMX_USBPHY);
+    }
+    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        snprintf(name, NAME_SIZE, "usb%d", i);
+        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
+                              TYPE_CHIPIDEA);
+    }
+
     /*
      * SDHCI
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
+    /* USB */
+    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+    }
+
+    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const int FSL_IMX6UL_USBn_IRQ[] = {
+            FSL_IMX6UL_USB1_IRQ,
+            FSL_IMX6UL_USB2_IRQ,
+        };
+        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                            FSL_IMX6UL_USBn_IRQ[i]));
+    }
+
     /*
      * USDHC
      */
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

With this patch, the USB controllers on 'sabrelite' are detected
and can be used to boot the system.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-6-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  6 ++++++
 hw/arm/fsl-imx6.c         | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/imx_spi.h"
 #include "hw/net/imx_fec.h"
+#include "hw/usb/chipidea.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
 #include "cpu.h"
 
@@ -XXX,XX +XXX,XX @@
 #define FSL_IMX6_NUM_ESDHCS 4
 #define FSL_IMX6_NUM_ECSPIS 5
 #define FSL_IMX6_NUM_WDTS 2
+#define FSL_IMX6_NUM_USB_PHYS 2
+#define FSL_IMX6_NUM_USBS 4
 
 typedef struct FslIMX6State {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
     SDHCIState     esdhc[FSL_IMX6_NUM_ESDHCS];
     IMXSPIState    spi[FSL_IMX6_NUM_ECSPIS];
     IMX2WdtState   wdt[FSL_IMX6_NUM_WDTS];
+    IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
+    ChipideaState  usb[FSL_IMX6_NUM_USBS];
     IMXFECState    eth;
     MemoryRegion   rom;
     MemoryRegion   caam;
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/arm/fsl-imx6.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
 #include "sysemu/sysemu.h"
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
                               TYPE_IMX_USDHC);
     }
 
+    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+        snprintf(name, NAME_SIZE, "usbphy%d", i);
+        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
+                              TYPE_IMX_USBPHY);
+    }
+    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+        snprintf(name, NAME_SIZE, "usb%d", i);
+        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
+                              TYPE_CHIPIDEA);
+    }
+
     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
                                             esdhc_table[i].irq));
     }
 
+    /* USB */
+    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+                        FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
+    }
+    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+        static const int FSL_IMX6_USBn_IRQ[] = {
+            FSL_IMX6_USB_OTG_IRQ,
+            FSL_IMX6_USB_HOST1_IRQ,
+            FSL_IMX6_USB_HOST2_IRQ,
+            FSL_IMX6_USB_HOST3_IRQ,
+        };
+
+        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                        FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
+                                            FSL_IMX6_USBn_IRQ[i]));
+    }
+
     /* Initialize all ECSPI */
     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
         static const struct {
-- 
2.20.1

From: Chen Qun <kuhn.chenqun@huawei.com>

The current code causes clang static code analyzer generate warning:
hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
        value = value & 0x0000000f;
        ^       ~~~~~~~~~~~~~~~~~~
hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
        value = value & 0x000000fd;
        ^       ~~~~~~~~~~~~~~~~~~

According to the definition of the function, the two “value” assignments
 should be written to registers.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Message-id: 20200313123242.13236-1-kuhn.chenqun@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/imx_fec.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
         break;
     case ENET_TGSR:
         /* implement clear timer flag */
-        value = value & 0x0000000f;
+        s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
         break;
     case ENET_TCSR0:
     case ENET_TCSR1:
     case ENET_TCSR2:
     case ENET_TCSR3:
-        value = value & 0x000000fd;
+        s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
+        s->regs[index] &= ~0x0000007d; /* writable fields */
+        s->regs[index] |= (value & 0x0000007d);
         break;
     case ENET_TCCR0:
     case ENET_TCCR1:
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

While at it, add some trace messages to help debug problems
seen when running the latest Linux kernel.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/m25p80.c     | 48 ++++++++++++++++++++-----------------------
 hw/block/trace-events | 16 +++++++++++++++
 2 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
-
-#ifndef M25P80_ERR_DEBUG
-#define M25P80_ERR_DEBUG 0
-#endif
-
-#define DB_PRINT_L(level, ...) do { \
-    if (M25P80_ERR_DEBUG > (level)) { \
-        fprintf(stderr,  ": %s: ", __func__); \
-        fprintf(stderr, ## __VA_ARGS__); \
-    } \
-} while (0)
+#include "trace.h"
 
 /* Fields for FlashPartInfo->flags */
 
@@ -XXX,XX +XXX,XX @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
         abort();
     }
 
-    DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
+    trace_m25p80_flash_erase(s, offset, len);
+
     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
                       " device\n", len);
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
     }
 
     if ((prev ^ data) & data) {
-        DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 "  %" PRIx8
-                   " -> %" PRIx8 "\n", addr, prev, data);
+        trace_m25p80_programming_zero_to_one(s, addr, prev, data);
     }
 
     if (s->pi->flags & EEPROM) {
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
 
     s->state = STATE_IDLE;
 
+    trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
+                                     s->cur_addr);
+
     switch (s->cmd_in_progress) {
     case DPP:
     case QPP:
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
         break;
     }
 
-    DB_PRINT_L(0, "Reset done.\n");
+    trace_m25p80_reset_done(s);
 }
 
 static void decode_fast_read_cmd(Flash *s)
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
 
 static void decode_new_cmd(Flash *s, uint32_t value)
 {
-    s->cmd_in_progress = value;
     int i;
-    DB_PRINT_L(0, "decoded new command:%x\n", value);
+
+    s->cmd_in_progress = value;
+    trace_m25p80_command_decoded(s, value);
 
     if (value != RESET_MEMORY) {
         s->reset_enable = false;
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
         break;
 
     case JEDEC_READ:
-        DB_PRINT_L(0, "populated jedec code\n");
+        trace_m25p80_populated_jedec(s);
         for (i = 0; i < s->pi->id_len; i++) {
             s->data[i] = s->pi->id[i];
         }
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
     case BULK_ERASE_60:
     case BULK_ERASE:
         if (s->write_enable) {
-            DB_PRINT_L(0, "chip erase\n");
+            trace_m25p80_chip_erase(s);
             flash_erase(s, 0, BULK_ERASE);
         } else {
             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
@@ -XXX,XX +XXX,XX @@ static int m25p80_cs(SSISlave *ss, bool select)
         s->data_read_loop = false;
     }
 
-    DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
+    trace_m25p80_select(s, select ? "de" : "");
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
     Flash *s = M25P80(ss);
     uint32_t r = 0;
 
+    trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
+                          s->cur_addr, (uint8_t)tx);
+
     switch (s->state) {
 
     case STATE_PAGE_PROGRAM:
-        DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
-                   s->cur_addr, (uint8_t)tx);
+        trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
         flash_write8(s, s->cur_addr, (uint8_t)tx);
         s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
         break;
 
     case STATE_READ:
         r = s->storage[s->cur_addr];
-        DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
-                   (uint8_t)r);
+        trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
         s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
         break;
 
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
         }
 
         r = s->data[s->pos];
+        trace_m25p80_read_data(s, s->pos, (uint8_t)r);
         s->pos++;
         if (s->pos == s->len) {
             s->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
             return;
         }
 
-        DB_PRINT_L(0, "Binding to IF_MTD drive\n");
+        trace_m25p80_binding(s);
         s->storage = blk_blockalign(s->blk, s->size);
 
         if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
             return;
         }
     } else {
-        DB_PRINT_L(0, "No BDRV - binding to RAM\n");
+        trace_m25p80_binding_no_bdrv(s);
         s->storage = blk_blockalign(NULL, s->size);
         memset(s->storage, 0xFF, s->size);
     }
diff --git a/hw/block/trace-events b/hw/block/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ xen_block_blockdev_add(char *str) "%s"
 xen_block_blockdev_del(const char *node_name) "%s"
 xen_block_device_create(unsigned int number) "%u"
 xen_block_device_destroy(unsigned int number) "%u"
+
+# m25p80.c
+m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
+m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32"  0x%"PRIx8" -> 0x%"PRIx8
+m25p80_reset_done(void *s) "[%p] Reset done."
+m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
+m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
+m25p80_populated_jedec(void *s) "[%p] populated jedec code"
+m25p80_chip_erase(void *s) "[%p] chip erase"
+m25p80_select(void *s, const char *what) "[%p] %sselect"
+m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_addr=0x%"PRIx32" data=0x%"PRIx8
+m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
+m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
+m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
+m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
+m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

When requesting JEDEC data using the JEDEC_READ command, the Linux kernel
always requests 6 bytes. The current implementation only returns three
bytes, and interprets the remaining three bytes as new commands.
While this does not matter most of the time, it is at the very least
confusing. To avoid the problem, always report up to 6 bytes of JEDEC
data. Fill remaining data with 0.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/m25p80.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
         for (i = 0; i < s->pi->id_len; i++) {
             s->data[i] = s->pi->id[i];
         }
+        for (; i < SPI_NOR_MAX_ID_LEN; i++) {
+            s->data[i] = 0;
+        }
 
-        s->len = s->pi->id_len;
+        s->len = SPI_NOR_MAX_ID_LEN;
         s->pos = 0;
         s->state = STATE_READING_DATA;
         break;
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

Whenever an unsupported command is encountered, the current code
interprets each transferred byte as new command. Most of the time, those
'commands' are interpreted as new unknown commands. However, in rare
cases, it may be that for example address or length information
passed with the original command is by itself a valid command.
If that happens, the state machine may get completely confused and,
worst case, start writing data into the flash or even erase it.

To avoid the problem, transition into STATE_READING_DATA and keep
sending a value of 0 until the chip is deselected after encountering
an unsupported command.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/m25p80.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
         s->quad_enable = false;
         break;
     default:
+        s->pos = 0;
+        s->len = 1;
+        s->state = STATE_READING_DATA;
+        s->data_read_loop = true;
+        s->data[0] = 0;
         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
         break;
     }
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

The Linux kernel recently started using FAST_READ_4 commands.
This results in flash read failures. At the same time, the m25p80
emulation is seen to read 8 more bytes than expected. Adjusting the
expected number of dummy cycles to match FAST_READ fixes the problem.

Fixes: f95c4bffdc4c ("aspeed/smc: snoop SPI transfers to fake dummy cycles")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/aspeed_smc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -XXX,XX +XXX,XX @@ static int aspeed_smc_num_dummies(uint8_t command)
     case FAST_READ:
     case DOR:
     case QOR:
+    case FAST_READ_4:
     case DOR_4:
     case QOR_4:
         return 1;
     case DIOR:
-    case FAST_READ_4:
     case DIOR_4:
         return 2;
     case QIOR:
-- 
2.20.1