[Qemu-devel] [PULL 00/25] target-arm queue
[Qemu-devel] [PULL 00/15] target-arm queue
1
target-arm queue. This has the "plumb txattrs through various
1
A mixed bag, all bug fixes or similar small stuff.
2
bits of exec.c" patches, and a collection of bug fixes from
3
various people.
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2
5
thanks
3
thanks
6
-- PMM
4
-- PMM
7
5
8
6
7
The following changes since commit 19eb2d4e736dc895f31fbd6b520e514f10cc08e0:
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10
The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
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Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging (2019-05-07 10:43:32 +0100)
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12
Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
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10
14
are available in the Git repository at:
11
are available in the Git repository at:
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12
16
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190507
17
14
18
for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
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for you to fetch changes up to 63159601fb3e396b28da14cbb71e50ed3f5a0331:
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16
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KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
17
target/arm: Stop using variable length array in dc_zva (2019-05-07 12:55:04 +0100)
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18
22
----------------------------------------------------------------
19
----------------------------------------------------------------
23
target-arm queue:
20
target-arm queue:
24
* target/arm: Honour FPCR.FZ in FRECPX
21
* Stop using variable length array in dc_zva
25
* MAINTAINERS: Add entries for newer MPS2 boards and devices
22
* Implement M-profile XPSR GE bits
26
* hw/intc/arm_gicv3: Fix APxR<n> register dispatching
23
* Don't enable ARMV7M_EXCP_DEBUG from reset
27
* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
24
* armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
28
GIC state
25
* armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
29
* tcg: Fix helper function vs host abi for float16
26
* fix various minor issues to allow building for Windows-on-ARM64
30
* arm: fix qemu crash on startup with -bios option
27
* aspeed: Set SDRAM size
31
* arm: fix malloc type mismatch
28
* Allow system registers for KVM guests to be changed by QEMU code
32
* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
29
* raspi: Diagnose requests for too much RAM
33
* Correct CPACR reset value for v7 cores
30
* virt: Support firmware configuration with -blockdev
34
* memory.h: Improve IOMMU related documentation
35
* exec: Plumb transaction attributes through various functions in
36
preparation for allowing IOMMUs to see them
37
* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
38
* ARM: ACPI: Fix use-after-free due to memory realloc
39
* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
40
31
41
----------------------------------------------------------------
32
----------------------------------------------------------------
42
Francisco Iglesias (1):
33
Cao Jiaxi (4):
43
xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
34
QEMU_PACKED: Remove gcc_struct attribute in Windows non x86 targets
35
qga: Fix mingw compilation warnings on enum conversion
36
util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64
37
osdep: Fix mingw compilation regarding stdio formats
44
38
45
Igor Mammedov (1):
39
Joel Stanley (1):
46
arm: fix qemu crash on startup with -bios option
40
arm: aspeed: Set SDRAM size
47
41
48
Jan Kiszka (1):
42
Markus Armbruster (3):
49
hw/intc/arm_gicv3: Fix APxR<n> register dispatching
43
pc: Rearrange pc_system_firmware_init()'s legacy -drive loop
44
pflash_cfi01: New pflash_cfi01_legacy_drive()
45
hw/arm/virt: Support firmware configuration with -blockdev
50
46
51
Paolo Bonzini (1):
47
Peter Maydell (7):
52
arm: fix malloc type mismatch
48
hw/arm/raspi: Diagnose requests for too much RAM
49
arm: Allow system registers for KVM guests to be changed by QEMU code
50
hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
51
hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
52
hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset
53
target/arm: Implement XPSR GE bits
54
target/arm: Stop using variable length array in dc_zva
53
55
54
Peter Maydell (17):
56
contrib/libvhost-user/libvhost-user.h | 2 +-
55
target/arm: Honour FPCR.FZ in FRECPX
57
include/hw/arm/aspeed.h | 1 +
56
MAINTAINERS: Add entries for newer MPS2 boards and devices
58
include/hw/arm/virt.h | 2 +
57
Correct CPACR reset value for v7 cores
59
include/hw/block/flash.h | 1 +
58
memory.h: Improve IOMMU related documentation
60
include/qemu/compiler.h | 2 +-
59
Make tb_invalidate_phys_addr() take a MemTxAttrs argument
61
include/qemu/osdep.h | 10 +-
60
Make address_space_translate{, _cached}() take a MemTxAttrs argument
62
scripts/cocci-macro-file.h | 7 +-
61
Make address_space_map() take a MemTxAttrs argument
63
target/arm/cpu.h | 13 ++-
62
Make address_space_access_valid() take a MemTxAttrs argument
64
hw/arm/aspeed.c | 8 ++
63
Make flatview_extend_translation() take a MemTxAttrs argument
65
hw/arm/raspi.c | 7 ++
64
Make memory_region_access_valid() take a MemTxAttrs argument
66
hw/arm/virt.c | 202 ++++++++++++++++++++++------------
65
Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
67
hw/block/pflash_cfi01.c | 28 +++++
66
Make flatview_access_valid() take a MemTxAttrs argument
68
hw/i386/pc_sysfw.c | 18 +--
67
Make flatview_translate() take a MemTxAttrs argument
69
hw/intc/armv7m_nvic.c | 40 ++++++-
68
Make address_space_get_iotlb_entry() take a MemTxAttrs argument
70
qga/commands-win32.c | 2 +-
69
Make flatview_do_translate() take a MemTxAttrs argument
71
target/arm/helper.c | 47 +++++++-
70
Make address_space_translate_iommu take a MemTxAttrs argument
72
target/arm/kvm.c | 8 ++
71
vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
73
target/arm/kvm32.c | 20 +---
74
target/arm/kvm64.c | 2 +
75
target/arm/machine.c | 2 +-
76
util/cacheinfo.c | 2 +-
77
21 files changed, 294 insertions(+), 130 deletions(-)
72
78
73
Richard Henderson (1):
74
tcg: Fix helper function vs host abi for float16
75
76
Shannon Zhao (3):
77
arm_gicv3_kvm: increase clroffset accordingly
78
ARM: ACPI: Fix use-after-free due to memory realloc
79
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
80
81
include/exec/exec-all.h | 5 +-
82
include/exec/helper-head.h | 2 +-
83
include/exec/memory-internal.h | 3 +-
84
include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------
85
include/migration/vmstate.h | 3 +
86
include/sysemu/dma.h | 6 +-
87
accel/tcg/translate-all.c | 4 +-
88
exec.c | 95 ++++++++++++++++++------------
89
hw/arm/boot.c | 18 +++---
90
hw/arm/virt-acpi-build.c | 20 +++++--
91
hw/dma/xlnx-zdma.c | 10 +++-
92
hw/hppa/dino.c | 3 +-
93
hw/intc/arm_gic_kvm.c | 1 -
94
hw/intc/arm_gicv3_cpuif.c | 12 ++--
95
hw/intc/arm_gicv3_kvm.c | 2 +-
96
hw/nvram/fw_cfg.c | 12 ++--
97
hw/s390x/s390-pci-inst.c | 3 +-
98
hw/scsi/esp.c | 3 +-
99
hw/vfio/common.c | 3 +-
100
hw/virtio/vhost.c | 3 +-
101
hw/xen/xen_pt_msi.c | 3 +-
102
memory.c | 12 ++--
103
memory_ldst.inc.c | 18 +++---
104
target/arm/gdbstub.c | 3 +-
105
target/arm/helper-a64.c | 41 +++++++------
106
target/arm/helper.c | 90 ++++++++++++++++-------------
107
target/ppc/mmu-hash64.c | 3 +-
108
target/riscv/helper.c | 2 +-
109
target/s390x/diag.c | 6 +-
110
target/s390x/excp_helper.c | 3 +-
111
target/s390x/mmu_helper.c | 3 +-
112
target/s390x/sigp.c | 3 +-
113
target/xtensa/op_helper.c | 3 +-
114
MAINTAINERS | 9 ++-
115
34 files changed, 353 insertions(+), 182 deletions(-)
116
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
[Qemu-devel] [PULL 01/15] pc: Rearrange pc_system_firmware_init()'s legacy -drive loop
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Markus Armbruster <armbru@redhat.com>
2
2
3
acpi_data_push uses g_array_set_size to resize the memory size. If there
3
The loop does two things: map legacy -drive to properties, and collect
4
is no enough contiguous memory, the address will be changed. So previous
4
all the backends for use after the loop. The next patch will factor
5
pointer could not be used any more. It must update the pointer and use
5
out the former for reuse in hw/arm/virt.c. To make that easier,
6
the new one.
6
rearrange the loop so it does the first thing first, and the second
7
thing second.
7
8
8
Also, previous codes wrongly use le32 conversion of iort->node_offset
9
Signed-off-by: Markus Armbruster <armbru@redhat.com>
9
for subsequent computations that will result incorrect value if host is
10
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
10
not litlle endian. So use the non-converted one instead.
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
12
Message-id: 20190416091348.26075-2-armbru@redhat.com
12
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
14
---
17
hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
15
hw/i386/pc_sysfw.c | 24 +++++++++++-------------
18
1 file changed, 15 insertions(+), 5 deletions(-)
16
1 file changed, 11 insertions(+), 13 deletions(-)
19
17
20
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
18
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt-acpi-build.c
20
--- a/hw/i386/pc_sysfw.c
23
+++ b/hw/arm/virt-acpi-build.c
21
+++ b/hw/i386/pc_sysfw.c
24
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
22
@@ -XXX,XX +XXX,XX @@ void pc_system_firmware_init(PCMachineState *pcms,
25
AcpiIortItsGroup *its;
23
26
AcpiIortTable *iort;
24
/* Map legacy -drive if=pflash to machine properties */
27
AcpiIortSmmu3 *smmu;
25
for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) {
28
- size_t node_size, iort_length, smmu_offset = 0;
26
- pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]);
29
+ size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
27
pflash_drv = drive_get(IF_PFLASH, 0, i);
30
AcpiIortRC *rc;
28
- if (!pflash_drv) {
31
29
- continue;
32
iort = acpi_data_push(table_data, sizeof(*iort));
30
+ if (pflash_drv) {
33
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
31
+ loc_push_none(&loc);
34
32
+ qemu_opts_loc_restore(pflash_drv->opts);
35
iort_length = sizeof(*iort);
33
+ if (pflash_cfi01_get_blk(pcms->flash[i])) {
36
iort->node_count = cpu_to_le32(nb_nodes);
34
+ error_report("clashes with -machine");
37
- iort->node_offset = cpu_to_le32(sizeof(*iort));
35
+ exit(1);
38
+ /*
36
+ }
39
+ * Use a copy in case table_data->data moves during acpi_data_push
37
+ qdev_prop_set_drive(DEVICE(pcms->flash[i]), "drive",
40
+ * operations.
38
+ blk_by_legacy_dinfo(pflash_drv), &error_fatal);
41
+ */
39
+ loc_pop(&loc);
42
+ iort_node_offset = sizeof(*iort);
40
}
43
+ iort->node_offset = cpu_to_le32(iort_node_offset);
41
- loc_push_none(&loc);
44
42
- qemu_opts_loc_restore(pflash_drv->opts);
45
/* ITS group node */
43
- if (pflash_blk[i]) {
46
node_size = sizeof(*its) + sizeof(uint32_t);
44
- error_report("clashes with -machine");
47
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
45
- exit(1);
48
int irq = vms->irqmap[VIRT_SMMU];
46
- }
49
47
- pflash_blk[i] = blk_by_legacy_dinfo(pflash_drv);
50
/* SMMUv3 node */
48
- qdev_prop_set_drive(DEVICE(pcms->flash[i]),
51
- smmu_offset = iort->node_offset + node_size;
49
- "drive", pflash_blk[i], &error_fatal);
52
+ smmu_offset = iort_node_offset + node_size;
50
- loc_pop(&loc);
53
node_size = sizeof(*smmu) + sizeof(*idmap);
51
+ pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]);
54
iort_length += node_size;
55
smmu = acpi_data_push(table_data, node_size);
56
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
57
idmap->id_count = cpu_to_le32(0xFFFF);
58
idmap->output_base = 0;
59
/* output IORT node is the ITS group node (the first node) */
60
- idmap->output_reference = cpu_to_le32(iort->node_offset);
61
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
62
}
52
}
63
53
64
/* Root Complex Node */
54
/* Reject gaps */
65
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
idmap->output_reference = cpu_to_le32(smmu_offset);
67
} else {
68
/* output IORT node is the ITS group node (the first node) */
69
- idmap->output_reference = cpu_to_le32(iort->node_offset);
70
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
71
}
72
73
+ /*
74
+ * Update the pointer address in case table_data->data moves during above
75
+ * acpi_data_push operations.
76
+ */
77
+ iort = (AcpiIortTable *)(table_data->data + iort_start);
78
iort->length = cpu_to_le32(iort_length);
79
80
build_header(linker, table_data, (void *)(table_data->data + iort_start),
81
--
55
--
82
2.17.1
56
2.20.1
83
57
84
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
[Qemu-devel] [PULL 02/15] pflash_cfi01: New pflash_cfi01_legacy_drive()
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Markus Armbruster <armbru@redhat.com>
2
2
3
When QEMU is started with following CLI
3
Factored out of pc_system_firmware_init() so the next commit can reuse
4
-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
4
it in hw/arm/virt.c.
5
it crashes with abort at
6
accel/kvm/kvm-all.c:2164:
7
KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
8
5
9
Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
6
Signed-off-by: Markus Armbruster <armbru@redhat.com>
10
arm_gicv3_icc_reset() where the later is called by CPU reset
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
11
reset callback.
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
9
Message-id: 20190416091348.26075-3-armbru@redhat.com
13
However commit:
14
3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
15
broke CPU reset callback registration in case
16
17
arm_load_kernel()
18
...
19
if (!info->kernel_filename || info->firmware_loaded)
20
21
branch is taken, i.e. it's sufficient to provide a firmware
22
or do not provide kernel on CLI to skip cpu reset callback
23
registration, where before offending commit the callback
24
has been registered unconditionally.
25
26
Fix it by registering the callback right at the beginning of
27
arm_load_kernel() unconditionally instead of doing it at the end.
28
29
NOTE:
30
we probably should eliminate that dependency anyways as well as
31
separate arch CPU reset parts from arm_load_kernel() into CPU
32
itself, but that refactoring that I probably would have to do
33
anyways later for CPU hotplug to work.
34
35
Reported-by: Auger Eric <eric.auger@redhat.com>
36
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Tested-by: Eric Auger <eric.auger@redhat.com>
39
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
11
---
43
hw/arm/boot.c | 18 +++++++++---------
12
include/hw/block/flash.h | 1 +
44
1 file changed, 9 insertions(+), 9 deletions(-)
13
hw/block/pflash_cfi01.c | 28 ++++++++++++++++++++++++++++
14
hw/i386/pc_sysfw.c | 16 ++--------------
15
3 files changed, 31 insertions(+), 14 deletions(-)
45
16
46
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
47
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/boot.c
19
--- a/include/hw/block/flash.h
49
+++ b/hw/arm/boot.c
20
+++ b/include/hw/block/flash.h
50
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
21
@@ -XXX,XX +XXX,XX @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base,
51
static const ARMInsnFixup *primary_loader;
22
int be);
52
AddressSpace *as = arm_boot_address_space(cpu, info);
23
BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
53
24
MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
54
+ /* CPU objects (unlike devices) are not automatically reset on system
25
+void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo);
55
+ * reset, so we must always register a handler to do so. If we're
26
56
+ * actually loading a kernel, the handler is also responsible for
27
/* pflash_cfi02.c */
57
+ * arranging that we start it correctly.
28
58
+ */
29
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
59
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
30
index XXXXXXX..XXXXXXX 100644
60
+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
31
--- a/hw/block/pflash_cfi01.c
32
+++ b/hw/block/pflash_cfi01.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qapi/error.h"
35
#include "qemu/timer.h"
36
#include "qemu/bitops.h"
37
+#include "qemu/error-report.h"
38
#include "qemu/host-utils.h"
39
#include "qemu/log.h"
40
+#include "qemu/option.h"
41
#include "hw/sysbus.h"
42
+#include "sysemu/blockdev.h"
43
#include "sysemu/sysemu.h"
44
#include "trace.h"
45
46
@@ -XXX,XX +XXX,XX @@ MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl)
47
return &fl->mem;
48
}
49
50
+/*
51
+ * Handle -drive if=pflash for machines that use properties.
52
+ * If @dinfo is null, do nothing.
53
+ * Else if @fl's property "drive" is already set, fatal error.
54
+ * Else set it to the BlockBackend with @dinfo.
55
+ */
56
+void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo)
57
+{
58
+ Location loc;
59
+
60
+ if (!dinfo) {
61
+ return;
61
+ }
62
+ }
62
+
63
+
63
/* The board code is not supposed to set secure_board_setup unless
64
+ loc_push_none(&loc);
64
* running its code in secure mode is actually possible, and KVM
65
+ qemu_opts_loc_restore(dinfo->opts);
65
* doesn't support secure.
66
+ if (fl->blk) {
66
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
67
+ error_report("clashes with -machine");
67
ARM_CPU(cs)->env.boot_info = info;
68
+ exit(1);
69
+ }
70
+ qdev_prop_set_drive(DEVICE(fl), "drive",
71
+ blk_by_legacy_dinfo(dinfo), &error_fatal);
72
+ loc_pop(&loc);
73
+}
74
+
75
static void postload_update_cb(void *opaque, int running, RunState state)
76
{
77
PFlashCFI01 *pfl = opaque;
78
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/i386/pc_sysfw.c
81
+++ b/hw/i386/pc_sysfw.c
82
@@ -XXX,XX +XXX,XX @@ void pc_system_firmware_init(PCMachineState *pcms,
83
{
84
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
85
int i;
86
- DriveInfo *pflash_drv;
87
BlockBackend *pflash_blk[ARRAY_SIZE(pcms->flash)];
88
- Location loc;
89
90
if (!pcmc->pci_enabled) {
91
old_pc_system_rom_init(rom_memory, true);
92
@@ -XXX,XX +XXX,XX @@ void pc_system_firmware_init(PCMachineState *pcms,
93
94
/* Map legacy -drive if=pflash to machine properties */
95
for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) {
96
- pflash_drv = drive_get(IF_PFLASH, 0, i);
97
- if (pflash_drv) {
98
- loc_push_none(&loc);
99
- qemu_opts_loc_restore(pflash_drv->opts);
100
- if (pflash_cfi01_get_blk(pcms->flash[i])) {
101
- error_report("clashes with -machine");
102
- exit(1);
103
- }
104
- qdev_prop_set_drive(DEVICE(pcms->flash[i]), "drive",
105
- blk_by_legacy_dinfo(pflash_drv), &error_fatal);
106
- loc_pop(&loc);
107
- }
108
+ pflash_cfi01_legacy_drive(pcms->flash[i],
109
+ drive_get(IF_PFLASH, 0, i));
110
pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]);
68
}
111
}
69
112
70
- /* CPU objects (unlike devices) are not automatically reset on system
71
- * reset, so we must always register a handler to do so. If we're
72
- * actually loading a kernel, the handler is also responsible for
73
- * arranging that we start it correctly.
74
- */
75
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
76
- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
77
- }
78
-
79
if (!info->skip_dtb_autoload && have_dtb(info)) {
80
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
81
exit(1);
82
--
113
--
83
2.17.1
114
2.20.1
84
115
85
116
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
[Qemu-devel] [PULL 03/15] hw/arm/virt: Support firmware configuration with -blockdev
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Markus Armbruster <armbru@redhat.com>
2
2
3
Depending on the host abi, float16, aka uint16_t, values are
3
The ARM virt machines put firmware in flash memory. To configure it,
4
passed and returned either zero-extended in the host register
4
you use -drive if=pflash,unit=0,... and optionally -drive
5
or with garbage at the top of the host register.
5
if=pflash,unit=1,...
6
6
7
The tcg code generator has so far been assuming garbage, as that
7
Why two -drive? This permits setting up one part of the flash memory
8
matches the x86 abi, but this is incorrect for other host abis.
8
read-only, and the other part read/write. It also makes upgrading
9
Further, target/arm has so far been assuming zero-extended results,
9
firmware on the host easier. Below the hood, we get two separate
10
so that it may store the 16-bit value into a 32-bit slot with the
10
flash devices, because we were too lazy to improve our flash device
11
high 16-bits already clear.
11
models to support sector protection.
12
12
13
Rectify both problems by mapping "f16" in the helper definition
13
The problem at hand is to do the same with -blockdev somehow, as one
14
to uint32_t instead of (a typedef for) uint16_t. This forces
14
more step towards deprecating -drive.
15
the host compiler to assume garbage in the upper 16 bits on input
15
16
and to zero-extend the result on output.
16
We recently solved this problem for x86 PC machines, in commit
17
17
ebc29e1beab. See the commit message for design rationale.
18
Cc: qemu-stable@nongnu.org
18
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
This commit solves it for ARM virt basically the same way: new machine
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
properties pflash0, pflash1 forward to the onboard flash devices'
21
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
21
properties. Requires creating the onboard devices in the
22
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
22
.instance_init() method virt_instance_init(). The existing code to
23
pick up drives defined with -drive if=pflash is replaced by code to
24
desugar into the machine properties.
25
26
There are a few behavioral differences, though:
27
28
* The flash devices are always present (x86: only present if
29
configured)
30
31
* Flash base addresses and sizes are fixed (x86: sizes depend on
32
images, mapped back to back below a fixed address)
33
34
* -bios configures contents of first pflash (x86: -bios configures ROM
35
contents)
36
37
* -bios is rejected when first pflash is also configured with -machine
38
pflash0=... (x86: bios is silently ignored then)
39
40
* -machine pflash1=... does not require -machine pflash0=... (x86: it
41
does).
42
43
The actual code is a bit simpler than for x86 mostly due to the first
44
two differences.
45
46
Before the patch, all the action is in create_flash(), called from the
47
machine's .init() method machvirt_init():
48
49
main()
50
machine_run_board_init()
51
machvirt_init()
52
create_flash()
53
create_one_flash() for flash[0]
54
create
55
configure
56
includes obeying -drive if=pflash,unit=0
57
realize
58
map
59
fall back to -bios
60
create_one_flash() for flash[1]
61
create
62
configure
63
includes obeying -drive if=pflash,unit=1
64
realize
65
map
66
update FDT
67
68
To make the machine properties work, we need to move device creation
69
to its .instance_init() method virt_instance_init().
70
71
Another complication is machvirt_init()'s computation of
72
@firmware_loaded: it predicts what create_flash() will do. Instead of
73
predicting what create_flash()'s replacement virt_firmware_init() will
74
do, I decided to have virt_firmware_init() return what it did.
75
Requires calling it a bit earlier.
76
77
Resulting call tree:
78
79
main()
80
current_machine = object_new()
81
...
82
virt_instance_init()
83
virt_flash_create()
84
virt_flash_create1() for flash[0]
85
create
86
configure: set defaults
87
become child of machine [NEW]
88
add machine prop pflash0 as alias for drive [NEW]
89
virt_flash_create1() for flash[1]
90
create
91
configure: set defaults
92
become child of machine [NEW]
93
add machine prop pflash1 as alias for drive [NEW]
94
for all machine props from the command line: machine_set_property()
95
...
96
property_set_alias() for machine props pflash0, pflash1
97
...
98
set_drive() for cfi.pflash01 prop drive
99
this is how -machine pflash0=... etc set
100
machine_run_board_init(current_machine);
101
virt_firmware_init()
102
pflash_cfi01_legacy_drive()
103
legacy -drive if=pflash,unit=0 and =1 [NEW]
104
virt_flash_map()
105
virt_flash_map1() for flash[0]
106
configure: num-blocks
107
realize
108
map
109
virt_flash_map1() for flash[1]
110
configure: num-blocks
111
realize
112
map
113
fall back to -bios
114
virt_flash_fdt()
115
update FDT
116
117
You have László to thank for making me explain this in detail.
118
119
Signed-off-by: Markus Armbruster <armbru@redhat.com>
120
Acked-by: Laszlo Ersek <lersek@redhat.com>
121
Message-id: 20190416091348.26075-4-armbru@redhat.com
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
122
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
123
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
124
---
26
include/exec/helper-head.h | 2 +-
125
include/hw/arm/virt.h | 2 +
27
target/arm/helper-a64.c | 35 +++++++++--------
126
hw/arm/virt.c | 202 +++++++++++++++++++++++++++---------------
28
target/arm/helper.c | 80 +++++++++++++++++++-------------------
127
2 files changed, 132 insertions(+), 72 deletions(-)
29
3 files changed, 59 insertions(+), 58 deletions(-)
128
30
129
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
31
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
32
index XXXXXXX..XXXXXXX 100644
130
index XXXXXXX..XXXXXXX 100644
33
--- a/include/exec/helper-head.h
131
--- a/include/hw/arm/virt.h
34
+++ b/include/exec/helper-head.h
132
+++ b/include/hw/arm/virt.h
35
@@ -XXX,XX +XXX,XX @@
133
@@ -XXX,XX +XXX,XX @@
36
#define dh_ctype_int int
134
#include "qemu/notify.h"
37
#define dh_ctype_i64 uint64_t
135
#include "hw/boards.h"
38
#define dh_ctype_s64 int64_t
136
#include "hw/arm/arm.h"
39
-#define dh_ctype_f16 float16
137
+#include "hw/block/flash.h"
40
+#define dh_ctype_f16 uint32_t
138
#include "sysemu/kvm.h"
41
#define dh_ctype_f32 float32
139
#include "hw/intc/arm_gicv3_common.h"
42
#define dh_ctype_f64 float64
140
43
#define dh_ctype_ptr void *
141
@@ -XXX,XX +XXX,XX @@ typedef struct {
44
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
142
Notifier machine_done;
143
DeviceState *platform_bus_dev;
144
FWCfgState *fw_cfg;
145
+ PFlashCFI01 *flash[2];
146
bool secure;
147
bool highmem;
148
bool highmem_ecam;
149
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
45
index XXXXXXX..XXXXXXX 100644
150
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/helper-a64.c
151
--- a/hw/arm/virt.c
47
+++ b/target/arm/helper-a64.c
152
+++ b/hw/arm/virt.c
48
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
153
@@ -XXX,XX +XXX,XX @@
49
return flags;
154
50
}
155
#include "qemu/osdep.h"
51
156
#include "qemu/units.h"
52
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
157
+#include "qemu/option.h"
53
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
158
#include "qapi/error.h"
54
{
159
#include "hw/sysbus.h"
55
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
160
#include "hw/arm/arm.h"
56
}
161
@@ -XXX,XX +XXX,XX @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
57
58
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
59
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
60
{
61
return float_rel_to_flags(float16_compare(x, y, fp_status));
62
}
63
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
64
#define float64_three make_float64(0x4008000000000000ULL)
65
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
66
67
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
68
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
69
{
70
float_status *fpst = fpstp;
71
72
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
73
return float64_muladd(a, b, float64_two, 0, fpst);
74
}
75
76
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
77
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
78
{
79
float_status *fpst = fpstp;
80
81
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
82
}
83
84
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
85
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
86
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
87
{
88
float_status *fpst = fpstp;
89
uint16_t val16, sbit;
90
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
91
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
92
93
#define ADVSIMD_HALFOP(name) \
94
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
95
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
96
{ \
97
float_status *fpst = fpstp; \
98
return float16_ ## name(a, b, fpst); \
99
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
100
ADVSIMD_TWOHALFOP(mulx)
101
102
/* fused multiply-accumulate */
103
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
104
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
105
+ void *fpstp)
106
{
107
float_status *fpst = fpstp;
108
return float16_muladd(a, b, c, 0, fpst);
109
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
110
111
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
112
113
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
114
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
115
{
116
float_status *fpst = fpstp;
117
int compare = float16_compare_quiet(a, b, fpst);
118
return ADVSIMD_CMPRES(compare == float_relation_equal);
119
}
120
121
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
122
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
123
{
124
float_status *fpst = fpstp;
125
int compare = float16_compare(a, b, fpst);
126
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
127
compare == float_relation_equal);
128
}
129
130
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
131
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
132
{
133
float_status *fpst = fpstp;
134
int compare = float16_compare(a, b, fpst);
135
return ADVSIMD_CMPRES(compare == float_relation_greater);
136
}
137
138
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
139
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
140
{
141
float_status *fpst = fpstp;
142
float16 f0 = float16_abs(a);
143
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
144
compare == float_relation_equal);
145
}
146
147
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
148
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
149
{
150
float_status *fpst = fpstp;
151
float16 f0 = float16_abs(a);
152
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
153
}
154
155
/* round to integral */
156
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
157
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
158
{
159
return float16_round_to_int(x, fp_status);
160
}
161
162
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
163
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
164
{
165
int old_flags = get_float_exception_flags(fp_status), new_flags;
166
float16 ret;
167
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
168
* setting the mode appropriately before calling the helper.
169
*/
170
171
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
172
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
173
{
174
float_status *fpst = fpstp;
175
176
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
177
return float16_to_int16(a, fpst);
178
}
179
180
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
181
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
182
{
183
float_status *fpst = fpstp;
184
185
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
186
* Square Root and Reciprocal square root
187
*/
188
189
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
190
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
191
{
192
float_status *s = fpstp;
193
194
diff --git a/target/arm/helper.c b/target/arm/helper.c
195
index XXXXXXX..XXXXXXX 100644
196
--- a/target/arm/helper.c
197
+++ b/target/arm/helper.c
198
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
199
200
/* Integer to float and float to integer conversions */
201
202
-#define CONV_ITOF(name, fsz, sign) \
203
- float##fsz HELPER(name)(uint32_t x, void *fpstp) \
204
-{ \
205
- float_status *fpst = fpstp; \
206
- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
207
+#define CONV_ITOF(name, ftype, fsz, sign) \
208
+ftype HELPER(name)(uint32_t x, void *fpstp) \
209
+{ \
210
+ float_status *fpst = fpstp; \
211
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
212
}
213
214
-#define CONV_FTOI(name, fsz, sign, round) \
215
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
216
-{ \
217
- float_status *fpst = fpstp; \
218
- if (float##fsz##_is_any_nan(x)) { \
219
- float_raise(float_flag_invalid, fpst); \
220
- return 0; \
221
- } \
222
- return float##fsz##_to_##sign##int32##round(x, fpst); \
223
+#define CONV_FTOI(name, ftype, fsz, sign, round) \
224
+uint32_t HELPER(name)(ftype x, void *fpstp) \
225
+{ \
226
+ float_status *fpst = fpstp; \
227
+ if (float##fsz##_is_any_nan(x)) { \
228
+ float_raise(float_flag_invalid, fpst); \
229
+ return 0; \
230
+ } \
231
+ return float##fsz##_to_##sign##int32##round(x, fpst); \
232
}
233
234
-#define FLOAT_CONVS(name, p, fsz, sign) \
235
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
236
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
237
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
238
+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
239
+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
240
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
241
+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
242
243
-FLOAT_CONVS(si, h, 16, )
244
-FLOAT_CONVS(si, s, 32, )
245
-FLOAT_CONVS(si, d, 64, )
246
-FLOAT_CONVS(ui, h, 16, u)
247
-FLOAT_CONVS(ui, s, 32, u)
248
-FLOAT_CONVS(ui, d, 64, u)
249
+FLOAT_CONVS(si, h, uint32_t, 16, )
250
+FLOAT_CONVS(si, s, float32, 32, )
251
+FLOAT_CONVS(si, d, float64, 64, )
252
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
253
+FLOAT_CONVS(ui, s, float32, 32, u)
254
+FLOAT_CONVS(ui, d, float64, 64, u)
255
256
#undef CONV_ITOF
257
#undef CONV_FTOI
258
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
259
return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
260
}
261
262
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
263
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
264
{
265
return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
266
}
267
268
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
269
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
270
{
271
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
272
}
273
274
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
275
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
276
{
277
return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
278
}
279
280
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
281
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
282
{
283
return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
284
}
285
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
286
}
162
}
287
}
163
}
288
164
289
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
165
-static void create_one_flash(const char *name, hwaddr flashbase,
290
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
166
- hwaddr flashsize, const char *file,
167
- MemoryRegion *sysmem)
168
+#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
169
+
170
+static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
171
+ const char *name,
172
+ const char *alias_prop_name)
291
{
173
{
292
return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
174
- /* Create and map a single flash device. We use the same
175
- * parameters as the flash devices on the Versatile Express board.
176
+ /*
177
+ * Create a single flash device. We use the same parameters as
178
+ * the flash devices on the Versatile Express board.
179
*/
180
- DriveInfo *dinfo = drive_get_next(IF_PFLASH);
181
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
182
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
183
- const uint64_t sectorlength = 256 * 1024;
184
185
- if (dinfo) {
186
- qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
187
- &error_abort);
188
- }
189
-
190
- qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
191
- qdev_prop_set_uint64(dev, "sector-length", sectorlength);
192
+ qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
193
qdev_prop_set_uint8(dev, "width", 4);
194
qdev_prop_set_uint8(dev, "device-width", 2);
195
qdev_prop_set_bit(dev, "big-endian", false);
196
@@ -XXX,XX +XXX,XX @@ static void create_one_flash(const char *name, hwaddr flashbase,
197
qdev_prop_set_uint16(dev, "id2", 0x00);
198
qdev_prop_set_uint16(dev, "id3", 0x00);
199
qdev_prop_set_string(dev, "name", name);
200
- qdev_init_nofail(dev);
201
-
202
- memory_region_add_subregion(sysmem, flashbase,
203
- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
204
-
205
- if (file) {
206
- char *fn;
207
- int image_size;
208
-
209
- if (drive_get(IF_PFLASH, 0, 0)) {
210
- error_report("The contents of the first flash device may be "
211
- "specified with -bios or with -drive if=pflash... "
212
- "but you cannot use both options at once");
213
- exit(1);
214
- }
215
- fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
216
- if (!fn) {
217
- error_report("Could not find ROM image '%s'", file);
218
- exit(1);
219
- }
220
- image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
221
- g_free(fn);
222
- if (image_size < 0) {
223
- error_report("Could not load ROM image '%s'", file);
224
- exit(1);
225
- }
226
- }
227
+ object_property_add_child(OBJECT(vms), name, OBJECT(dev),
228
+ &error_abort);
229
+ object_property_add_alias(OBJECT(vms), alias_prop_name,
230
+ OBJECT(dev), "drive", &error_abort);
231
+ return PFLASH_CFI01(dev);
293
}
232
}
294
233
295
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
234
-static void create_flash(const VirtMachineState *vms,
296
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
235
- MemoryRegion *sysmem,
236
- MemoryRegion *secure_sysmem)
237
+static void virt_flash_create(VirtMachineState *vms)
297
{
238
{
298
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
239
- /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
240
- * Any file passed via -bios goes in the first of these.
241
+ vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
242
+ vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
243
+}
244
+
245
+static void virt_flash_map1(PFlashCFI01 *flash,
246
+ hwaddr base, hwaddr size,
247
+ MemoryRegion *sysmem)
248
+{
249
+ DeviceState *dev = DEVICE(flash);
250
+
251
+ assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
252
+ assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
253
+ qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
254
+ qdev_init_nofail(dev);
255
+
256
+ memory_region_add_subregion(sysmem, base,
257
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
258
+ 0));
259
+}
260
+
261
+static void virt_flash_map(VirtMachineState *vms,
262
+ MemoryRegion *sysmem,
263
+ MemoryRegion *secure_sysmem)
264
+{
265
+ /*
266
+ * Map two flash devices to fill the VIRT_FLASH space in the memmap.
267
* sysmem is the system memory space. secure_sysmem is the secure view
268
* of the system, and the first flash device should be made visible only
269
* there. The second flash device is visible to both secure and nonsecure.
270
@@ -XXX,XX +XXX,XX @@ static void create_flash(const VirtMachineState *vms,
271
*/
272
hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
273
hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
274
- char *nodename;
275
276
- create_one_flash("virt.flash0", flashbase, flashsize,
277
- bios_name, secure_sysmem);
278
- create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
279
- NULL, sysmem);
280
+ virt_flash_map1(vms->flash[0], flashbase, flashsize,
281
+ secure_sysmem);
282
+ virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
283
+ sysmem);
284
+}
285
+
286
+static void virt_flash_fdt(VirtMachineState *vms,
287
+ MemoryRegion *sysmem,
288
+ MemoryRegion *secure_sysmem)
289
+{
290
+ hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
291
+ hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
292
+ char *nodename;
293
294
if (sysmem == secure_sysmem) {
295
/* Report both flash devices as a single node in the DT */
296
@@ -XXX,XX +XXX,XX @@ static void create_flash(const VirtMachineState *vms,
297
qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
298
g_free(nodename);
299
} else {
300
- /* Report the devices as separate nodes so we can mark one as
301
+ /*
302
+ * Report the devices as separate nodes so we can mark one as
303
* only visible to the secure world.
304
*/
305
nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
306
@@ -XXX,XX +XXX,XX @@ static void create_flash(const VirtMachineState *vms,
307
}
299
}
308
}
300
309
301
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
310
+static bool virt_firmware_init(VirtMachineState *vms,
302
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
311
+ MemoryRegion *sysmem,
312
+ MemoryRegion *secure_sysmem)
313
+{
314
+ int i;
315
+ BlockBackend *pflash_blk0;
316
+
317
+ /* Map legacy -drive if=pflash to machine properties */
318
+ for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
319
+ pflash_cfi01_legacy_drive(vms->flash[i],
320
+ drive_get(IF_PFLASH, 0, i));
321
+ }
322
+
323
+ virt_flash_map(vms, sysmem, secure_sysmem);
324
+
325
+ pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
326
+
327
+ if (bios_name) {
328
+ char *fname;
329
+ MemoryRegion *mr;
330
+ int image_size;
331
+
332
+ if (pflash_blk0) {
333
+ error_report("The contents of the first flash device may be "
334
+ "specified with -bios or with -drive if=pflash... "
335
+ "but you cannot use both options at once");
336
+ exit(1);
337
+ }
338
+
339
+ /* Fall back to -bios */
340
+
341
+ fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
342
+ if (!fname) {
343
+ error_report("Could not find ROM image '%s'", bios_name);
344
+ exit(1);
345
+ }
346
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
347
+ image_size = load_image_mr(fname, mr);
348
+ g_free(fname);
349
+ if (image_size < 0) {
350
+ error_report("Could not load ROM image '%s'", bios_name);
351
+ exit(1);
352
+ }
353
+ }
354
+
355
+ return pflash_blk0 || bios_name;
356
+}
357
+
358
static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
303
{
359
{
304
return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
360
hwaddr base = vms->memmap[VIRT_FW_CFG].base;
361
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
362
MemoryRegion *secure_sysmem = NULL;
363
int n, virt_max_cpus;
364
MemoryRegion *ram = g_new(MemoryRegion, 1);
365
- bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
366
+ bool firmware_loaded;
367
bool aarch64 = true;
368
369
/*
370
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
371
exit(1);
372
}
373
374
+ if (vms->secure) {
375
+ if (kvm_enabled()) {
376
+ error_report("mach-virt: KVM does not support Security extensions");
377
+ exit(1);
378
+ }
379
+
380
+ /*
381
+ * The Secure view of the world is the same as the NonSecure,
382
+ * but with a few extra devices. Create it as a container region
383
+ * containing the system memory at low priority; any secure-only
384
+ * devices go in at higher priority and take precedence.
385
+ */
386
+ secure_sysmem = g_new(MemoryRegion, 1);
387
+ memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
388
+ UINT64_MAX);
389
+ memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
390
+ }
391
+
392
+ firmware_loaded = virt_firmware_init(vms, sysmem,
393
+ secure_sysmem ?: sysmem);
394
+
395
/* If we have an EL3 boot ROM then the assumption is that it will
396
* implement PSCI itself, so disable QEMU's internal implementation
397
* so it doesn't get in the way. Instead of starting secondary
398
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
399
exit(1);
400
}
401
402
- if (vms->secure) {
403
- if (kvm_enabled()) {
404
- error_report("mach-virt: KVM does not support Security extensions");
405
- exit(1);
406
- }
407
-
408
- /* The Secure view of the world is the same as the NonSecure,
409
- * but with a few extra devices. Create it as a container region
410
- * containing the system memory at low priority; any secure-only
411
- * devices go in at higher priority and take precedence.
412
- */
413
- secure_sysmem = g_new(MemoryRegion, 1);
414
- memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
415
- UINT64_MAX);
416
- memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
417
- }
418
-
419
create_fdt(vms);
420
421
possible_cpus = mc->possible_cpu_arch_ids(machine);
422
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
423
&machine->device_memory->mr);
424
}
425
426
- create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
427
+ virt_flash_fdt(vms, sysmem, secure_sysmem);
428
429
create_gic(vms, pic);
430
431
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
432
NULL);
433
434
vms->irqmap = a15irqmap;
435
+
436
+ virt_flash_create(vms);
305
}
437
}
306
438
307
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
439
static const TypeInfo virt_machine_info = {
308
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
309
{
310
return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
311
}
312
313
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
314
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
315
{
316
return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
317
}
318
319
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
320
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
321
{
322
return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
323
}
324
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
325
}
326
327
/* Half precision conversions. */
328
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
329
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
330
{
331
/* Squash FZ16 to 0 for the duration of conversion. In this case,
332
* it would affect flushing input denormals.
333
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
334
return r;
335
}
336
337
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
338
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
339
{
340
/* Squash FZ16 to 0 for the duration of conversion. In this case,
341
* it would affect flushing output denormals.
342
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
343
return r;
344
}
345
346
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
347
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
348
{
349
/* Squash FZ16 to 0 for the duration of conversion. In this case,
350
* it would affect flushing input denormals.
351
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
352
return r;
353
}
354
355
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
356
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
357
{
358
/* Squash FZ16 to 0 for the duration of conversion. In this case,
359
* it would affect flushing output denormals.
360
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
361
g_assert_not_reached();
362
}
363
364
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
365
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
366
{
367
float_status *fpst = fpstp;
368
float16 f16 = float16_squash_input_denormal(input, fpst);
369
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
370
return extract64(estimate, 0, 8) << 44;
371
}
372
373
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
374
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
375
{
376
float_status *s = fpstp;
377
float16 f16 = float16_squash_input_denormal(input, s);
378
--
440
--
379
2.17.1
441
2.20.1
380
442
381
443
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
[Qemu-devel] [PULL 04/15] hw/arm/raspi: Diagnose requests for too much RAM
1
Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
1
The Raspberry Pi boards have a physical memory map which does
2
and friends.
2
not allow for more than 1GB of RAM. Currently if the user tries
3
to ask for more then we fail in a confusing way:
3
4
5
$ qemu-system-aarch64 --machine raspi3 -m 8G
6
Unexpected error in visit_type_uintN() at qapi/qapi-visit-core.c:164:
7
qemu-system-aarch64: Parameter 'vcram-base' expects uint32_t
8
Aborted (core dumped)
9
10
Catch this earlier and diagnose it with a more friendly message:
11
$ qemu-system-aarch64 --machine raspi3 -m 8G
12
qemu-system-aarch64: Requested ram size is too large for this machine: maximum is 1GB
13
14
Fixes: https://bugs.launchpad.net/qemu/+bug/1794187
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
7
---
19
---
8
include/migration/vmstate.h | 3 +++
20
hw/arm/raspi.c | 7 +++++++
9
1 file changed, 3 insertions(+)
21
1 file changed, 7 insertions(+)
10
22
11
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
23
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
12
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
13
--- a/include/migration/vmstate.h
25
--- a/hw/arm/raspi.c
14
+++ b/include/migration/vmstate.h
26
+++ b/hw/arm/raspi.c
15
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
27
@@ -XXX,XX +XXX,XX @@
16
#define VMSTATE_BOOL_ARRAY(_f, _s, _n) \
28
*/
17
VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
29
18
30
#include "qemu/osdep.h"
19
+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num) \
31
+#include "qemu/units.h"
20
+ VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
32
#include "qapi/error.h"
33
#include "qemu-common.h"
34
#include "cpu.h"
35
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
36
BusState *bus;
37
DeviceState *carddev;
38
39
+ if (machine->ram_size > 1 * GiB) {
40
+ error_report("Requested ram size is too large for this machine: "
41
+ "maximum is 1GB");
42
+ exit(1);
43
+ }
21
+
44
+
22
#define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v) \
45
object_initialize(&s->soc, sizeof(s->soc),
23
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
46
version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
24
47
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
25
--
48
--
26
2.17.1
49
2.20.1
27
50
28
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
[Qemu-devel] [PULL 05/15] arm: Allow system registers for KVM guests to be changed by QEMU code
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
At the moment the Arm implementations of kvm_arch_{get,put}_registers()
2
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
2
don't support having QEMU change the values of system registers
3
callback. We'll need this for subpage_accepts().
3
(aka coprocessor registers for AArch32). This is because although
4
4
kvm_arch_get_registers() calls write_list_to_cpustate() to
5
We could take the approach we used with the read and write
5
update the CPU state struct fields (so QEMU code can read the
6
callbacks and add new a new _with_attrs version, but since there
6
values in the usual way), kvm_arch_put_registers() does not
7
are so few implementations of the accepts hook we just change
7
call write_cpustate_to_list(), meaning that any changes to
8
them all.
8
the CPU state struct fields will not be passed back to KVM.
9
10
The rationale for this design is documented in a comment in the
11
AArch32 kvm_arch_put_registers() -- writing the values in the
12
cpregs list into the CPU state struct is "lossy" because the
13
write of a register might not succeed, and so if we blindly
14
copy the CPU state values back again we will incorrectly
15
change register values for the guest. The assumption was that
16
no QEMU code would need to write to the registers.
17
18
However, when we implemented debug support for KVM guests, we
19
broke that assumption: the code to handle "set the guest up
20
to take a breakpoint exception" does so by updating various
21
guest registers including ESR_EL1.
22
23
Support this by making kvm_arch_put_registers() synchronize
24
CPU state back into the list. We sync only those registers
25
where the initial write succeeds, which should be sufficient.
26
27
This commit is the same as commit 823e1b3818f9b10b824ddc which we
28
had to revert in commit 942f99c825fc94c8b1a4, except that the bug
29
which was preventing EDK2 guest firmware running has been fixed:
30
kvm_arm_reset_vcpu() now calls write_list_to_cpustate().
9
31
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
34
Tested-by: Eric Auger <eric.auger@redhat.com>
14
---
35
---
15
include/exec/memory.h | 3 ++-
36
target/arm/cpu.h | 9 ++++++++-
16
exec.c | 9 ++++++---
37
target/arm/helper.c | 27 +++++++++++++++++++++++++--
17
hw/hppa/dino.c | 3 ++-
38
target/arm/kvm.c | 8 ++++++++
18
hw/nvram/fw_cfg.c | 12 ++++++++----
39
target/arm/kvm32.c | 20 ++------------------
19
hw/scsi/esp.c | 3 ++-
40
target/arm/kvm64.c | 2 ++
20
hw/xen/xen_pt_msi.c | 3 ++-
41
target/arm/machine.c | 2 +-
21
memory.c | 5 +++--
42
6 files changed, 46 insertions(+), 22 deletions(-)
22
7 files changed, 25 insertions(+), 13 deletions(-)
43
23
44
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/include/exec/memory.h b/include/exec/memory.h
45
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.h
26
--- a/include/exec/memory.h
47
+++ b/target/arm/cpu.h
27
+++ b/include/exec/memory.h
48
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
28
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
49
/**
29
* as a machine check exception).
50
* write_cpustate_to_list:
30
*/
51
* @cpu: ARMCPU
31
bool (*accepts)(void *opaque, hwaddr addr,
52
+ * @kvm_sync: true if this is for syncing back to KVM
32
- unsigned size, bool is_write);
53
*
33
+ unsigned size, bool is_write,
54
* For each register listed in the ARMCPU cpreg_indexes list, write
34
+ MemTxAttrs attrs);
55
* its value from the ARMCPUState structure into the cpreg_values list.
35
} valid;
56
* This is used to copy info from TCG's working data structures into
36
/* Internal implementation constraints: */
57
* KVM or for outbound migration.
37
struct {
58
*
38
diff --git a/exec.c b/exec.c
59
+ * @kvm_sync is true if we are doing this in order to sync the
39
index XXXXXXX..XXXXXXX 100644
60
+ * register state back to KVM. In this case we will only update
40
--- a/exec.c
61
+ * values in the list if the previous list->cpustate sync actually
41
+++ b/exec.c
62
+ * successfully wrote the CPU state. Otherwise we will keep the value
42
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
63
+ * that is in the list.
64
+ *
65
* Returns: true if all register values were read correctly,
66
* false if some register was unknown or could not be read.
67
* Note that we do not stop early on failure -- we will attempt
68
* reading all registers in the list.
69
*/
70
-bool write_cpustate_to_list(ARMCPU *cpu);
71
+bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
72
73
#define ARM_CPUID_TI915T 0x54029152
74
#define ARM_CPUID_TI925T 0x54029252
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/helper.c
78
+++ b/target/arm/helper.c
79
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
80
return true;
43
}
81
}
44
82
45
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
83
-bool write_cpustate_to_list(ARMCPU *cpu)
46
- unsigned size, bool is_write)
84
+bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
47
+ unsigned size, bool is_write,
48
+ MemTxAttrs attrs)
49
{
85
{
50
return is_write;
86
/* Write the coprocessor state from cpu->env to the (index,value) list. */
87
int i;
88
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu)
89
for (i = 0; i < cpu->cpreg_array_len; i++) {
90
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
91
const ARMCPRegInfo *ri;
92
+ uint64_t newval;
93
94
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
95
if (!ri) {
96
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu)
97
if (ri->type & ARM_CP_NO_RAW) {
98
continue;
99
}
100
- cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
101
+
102
+ newval = read_raw_cp_reg(&cpu->env, ri);
103
+ if (kvm_sync) {
104
+ /*
105
+ * Only sync if the previous list->cpustate sync succeeded.
106
+ * Rather than tracking the success/failure state for every
107
+ * item in the list, we just recheck "does the raw write we must
108
+ * have made in write_list_to_cpustate() read back OK" here.
109
+ */
110
+ uint64_t oldval = cpu->cpreg_values[i];
111
+
112
+ if (oldval == newval) {
113
+ continue;
114
+ }
115
+
116
+ write_raw_cp_reg(&cpu->env, ri, oldval);
117
+ if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
118
+ continue;
119
+ }
120
+
121
+ write_raw_cp_reg(&cpu->env, ri, newval);
122
+ }
123
+ cpu->cpreg_values[i] = newval;
124
}
125
return ok;
51
}
126
}
52
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
127
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/kvm.c
130
+++ b/target/arm/kvm.c
131
@@ -XXX,XX +XXX,XX @@ void kvm_arm_reset_vcpu(ARMCPU *cpu)
132
fprintf(stderr, "write_kvmstate_to_list failed\n");
133
abort();
134
}
135
+ /*
136
+ * Sync the reset values also into the CPUState. This is necessary
137
+ * because the next thing we do will be a kvm_arch_put_registers()
138
+ * which will update the list values from the CPUState before copying
139
+ * the list values back to KVM. It's OK to ignore failure returns here
140
+ * for the same reason we do so in kvm_arch_get_registers().
141
+ */
142
+ write_list_to_cpustate(cpu);
53
}
143
}
54
144
55
static bool subpage_accepts(void *opaque, hwaddr addr,
145
/*
56
- unsigned len, bool is_write)
146
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
57
+ unsigned len, bool is_write,
147
index XXXXXXX..XXXXXXX 100644
58
+ MemTxAttrs attrs)
148
--- a/target/arm/kvm32.c
59
{
149
+++ b/target/arm/kvm32.c
60
subpage_t *subpage = opaque;
150
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
61
#if defined(DEBUG_SUBPAGE)
151
return ret;
62
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
152
}
63
}
153
64
154
- /* Note that we do not call write_cpustate_to_list()
65
static bool readonly_mem_accepts(void *opaque, hwaddr addr,
155
- * here, so we are only writing the tuple list back to
66
- unsigned size, bool is_write)
156
- * KVM. This is safe because nothing can change the
67
+ unsigned size, bool is_write,
157
- * CPUARMState cp15 fields (in particular gdb accesses cannot)
68
+ MemTxAttrs attrs)
158
- * and so there are no changes to sync. In fact syncing would
69
{
159
- * be wrong at this point: for a constant register where TCG and
70
return is_write;
160
- * KVM disagree about its value, the preceding write_list_to_cpustate()
71
}
161
- * would not have had any effect on the CPUARMState value (since the
72
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
162
- * register is read-only), and a write_cpustate_to_list() here would
73
index XXXXXXX..XXXXXXX 100644
163
- * then try to write the TCG value back into KVM -- this would either
74
--- a/hw/hppa/dino.c
164
- * fail or incorrectly change the value the guest sees.
75
+++ b/hw/hppa/dino.c
165
- *
76
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
166
- * If we ever want to allow the user to modify cp15 registers via
77
}
167
- * the gdb stub, we would need to be more clever here (for instance
78
168
- * tracking the set of registers kvm_arch_get_registers() successfully
79
static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
169
- * managed to update the CPUARMState with, and only allowing those
80
- unsigned size, bool is_write)
170
- * to be written back up into the kernel).
81
+ unsigned size, bool is_write,
171
- */
82
+ MemTxAttrs attrs)
172
+ write_cpustate_to_list(cpu, true);
83
{
173
+
84
switch (addr) {
174
if (!write_list_to_kvmstate(cpu, level)) {
85
case DINO_IAR0:
175
return EINVAL;
86
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
176
}
87
index XXXXXXX..XXXXXXX 100644
177
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
88
--- a/hw/nvram/fw_cfg.c
178
index XXXXXXX..XXXXXXX 100644
89
+++ b/hw/nvram/fw_cfg.c
179
--- a/target/arm/kvm64.c
90
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
180
+++ b/target/arm/kvm64.c
91
}
181
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
92
182
return ret;
93
static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
183
}
94
- unsigned size, bool is_write)
184
95
+ unsigned size, bool is_write,
185
+ write_cpustate_to_list(cpu, true);
96
+ MemTxAttrs attrs)
186
+
97
{
187
if (!write_list_to_kvmstate(cpu, level)) {
98
return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
188
return EINVAL;
99
(size == 8 && addr == 0));
189
}
100
}
190
diff --git a/target/arm/machine.c b/target/arm/machine.c
101
191
index XXXXXXX..XXXXXXX 100644
102
static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
192
--- a/target/arm/machine.c
103
- unsigned size, bool is_write)
193
+++ b/target/arm/machine.c
104
+ unsigned size, bool is_write,
194
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
105
+ MemTxAttrs attrs)
195
abort();
106
{
107
return addr == 0;
108
}
109
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
110
}
111
112
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
113
- unsigned size, bool is_write)
114
+ unsigned size, bool is_write,
115
+ MemTxAttrs attrs)
116
{
117
return is_write && size == 2;
118
}
119
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
120
}
121
122
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
123
- unsigned size, bool is_write)
124
+ unsigned size, bool is_write,
125
+ MemTxAttrs attrs)
126
{
127
return (size == 1) || (is_write && size == 2);
128
}
129
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/scsi/esp.c
132
+++ b/hw/scsi/esp.c
133
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
134
}
135
136
static bool esp_mem_accepts(void *opaque, hwaddr addr,
137
- unsigned size, bool is_write)
138
+ unsigned size, bool is_write,
139
+ MemTxAttrs attrs)
140
{
141
return (size == 1) || (is_write && size == 4);
142
}
143
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/xen/xen_pt_msi.c
146
+++ b/hw/xen/xen_pt_msi.c
147
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
148
}
149
150
static bool pci_msix_accepts(void *opaque, hwaddr addr,
151
- unsigned size, bool is_write)
152
+ unsigned size, bool is_write,
153
+ MemTxAttrs attrs)
154
{
155
return !(addr & (size - 1));
156
}
157
diff --git a/memory.c b/memory.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/memory.c
160
+++ b/memory.c
161
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
162
}
163
164
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
165
- unsigned size, bool is_write)
166
+ unsigned size, bool is_write,
167
+ MemTxAttrs attrs)
168
{
169
return false;
170
}
171
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
172
access_size = MAX(MIN(size, access_size_max), access_size_min);
173
for (i = 0; i < size; i += access_size) {
174
if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
175
- is_write)) {
176
+ is_write, attrs)) {
177
return false;
178
}
196
}
179
}
197
} else {
198
- if (!write_cpustate_to_list(cpu)) {
199
+ if (!write_cpustate_to_list(cpu, false)) {
200
/* This should never fail. */
201
abort();
202
}
180
--
203
--
181
2.17.1
204
2.20.1
182
205
183
206
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
[Qemu-devel] [PULL 06/15] arm: aspeed: Set SDRAM size
1
From: Jan Kiszka <jan.kiszka@siemens.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
There was a nasty flip in identifying which register group an access is
3
We currently use Qemu's default of 128MB. As we know how much ram each
4
targeting. The issue caused spuriously raised priorities of the guest
4
machine ships with, make it easier on users by setting a default.
5
when handing CPUs over in the Jailhouse hypervisor.
6
5
7
Cc: qemu-stable@nongnu.org
6
It can still be overridden with -m on the command line.
8
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
7
9
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20190503022958.1394-1-joel@jms.id.au
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
14
---
13
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
15
include/hw/arm/aspeed.h | 1 +
14
1 file changed, 6 insertions(+), 6 deletions(-)
16
hw/arm/aspeed.c | 8 ++++++++
17
2 files changed, 9 insertions(+)
15
18
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
19
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_cpuif.c
21
--- a/include/hw/arm/aspeed.h
19
+++ b/hw/intc/arm_gicv3_cpuif.c
22
+++ b/include/hw/arm/aspeed.h
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
23
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig {
21
{
24
const char *spi_model;
22
GICv3CPUState *cs = icc_cs_from_env(env);
25
uint32_t num_cs;
23
int regno = ri->opc2 & 3;
26
void (*i2c_init)(AspeedBoardState *bmc);
24
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
27
+ uint32_t ram;
25
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
28
} AspeedBoardConfig;
26
uint64_t value = cs->ich_apr[grp][regno];
29
27
30
#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
28
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
31
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
29
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
32
index XXXXXXX..XXXXXXX 100644
30
{
33
--- a/hw/arm/aspeed.c
31
GICv3CPUState *cs = icc_cs_from_env(env);
34
+++ b/hw/arm/aspeed.c
32
int regno = ri->opc2 & 3;
35
@@ -XXX,XX +XXX,XX @@
33
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
36
#include "sysemu/block-backend.h"
34
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
37
#include "hw/loader.h"
35
38
#include "qemu/error-report.h"
36
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
39
+#include "qemu/units.h"
37
40
38
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
41
static struct arm_boot_info aspeed_board_binfo = {
39
uint64_t value;
42
.board_id = -1, /* device-tree-only board */
40
43
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
41
int regno = ri->opc2 & 3;
44
mc->no_floppy = 1;
42
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
45
mc->no_cdrom = 1;
43
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
46
mc->no_parallel = 1;
44
47
+ if (board->ram) {
45
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
48
+ mc->default_ram_size = board->ram;
46
return icv_ap_read(env, ri);
49
+ }
47
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
50
amc->board = board;
48
GICv3CPUState *cs = icc_cs_from_env(env);
51
}
49
52
50
int regno = ri->opc2 & 3;
53
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
51
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
54
.spi_model = "mx25l25635e",
52
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
55
.num_cs = 1,
53
56
.i2c_init = palmetto_bmc_i2c_init,
54
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
57
+ .ram = 256 * MiB,
55
icv_ap_write(env, ri, value);
58
}, {
56
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
59
.name = MACHINE_TYPE_NAME("ast2500-evb"),
57
{
60
.desc = "Aspeed AST2500 EVB (ARM1176)",
58
GICv3CPUState *cs = icc_cs_from_env(env);
61
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
59
int regno = ri->opc2 & 3;
62
.spi_model = "mx25l25635e",
60
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
63
.num_cs = 1,
61
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
64
.i2c_init = ast2500_evb_i2c_init,
62
uint64_t value;
65
+ .ram = 512 * MiB,
63
66
}, {
64
value = cs->ich_apr[grp][regno];
67
.name = MACHINE_TYPE_NAME("romulus-bmc"),
65
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
68
.desc = "OpenPOWER Romulus BMC (ARM1176)",
66
{
69
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
67
GICv3CPUState *cs = icc_cs_from_env(env);
70
.spi_model = "mx66l1g45g",
68
int regno = ri->opc2 & 3;
71
.num_cs = 2,
69
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
72
.i2c_init = romulus_bmc_i2c_init,
70
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
73
+ .ram = 512 * MiB,
71
74
}, {
72
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
75
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
76
.desc = "OpenPOWER Witherspoon BMC (ARM1176)",
77
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
78
.spi_model = "mx66l1g45g",
79
.num_cs = 2,
80
.i2c_init = witherspoon_bmc_i2c_init,
81
+ .ram = 512 * MiB,
82
},
83
};
73
84
74
--
85
--
75
2.17.1
86
2.20.1
76
87
77
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
[Qemu-devel] [PULL 07/15] QEMU_PACKED: Remove gcc_struct attribute in Windows non x86 targets
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
2
3
kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
3
gcc_struct is for x86 only, and it generates an warning on ARM64 Clang/MinGW targets.
4
initialize global capability variables. If we call kvm_init_irq_routing in
5
GIC realize function, previous allocated memory will leak.
6
4
7
Fix this by deleting the unnecessary call.
5
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
8
6
Reviewed-by: Thomas Huth <thuth@redhat.com>
9
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
7
Message-id: 20190503003618.10089-1-driver1998@foxmail.com
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
[PMM: dropped the slirp change as slirp is now a submodule]
11
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
hw/intc/arm_gic_kvm.c | 1 -
11
contrib/libvhost-user/libvhost-user.h | 2 +-
15
hw/intc/arm_gicv3_kvm.c | 1 -
12
include/qemu/compiler.h | 2 +-
16
2 files changed, 2 deletions(-)
13
scripts/cocci-macro-file.h | 7 ++++++-
14
3 files changed, 8 insertions(+), 3 deletions(-)
17
15
18
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
16
diff --git a/contrib/libvhost-user/libvhost-user.h b/contrib/libvhost-user/libvhost-user.h
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/arm_gic_kvm.c
18
--- a/contrib/libvhost-user/libvhost-user.h
21
+++ b/hw/intc/arm_gic_kvm.c
19
+++ b/contrib/libvhost-user/libvhost-user.h
22
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
20
@@ -XXX,XX +XXX,XX @@ typedef struct VhostUserInflight {
23
21
uint16_t queue_size;
24
if (kvm_has_gsi_routing()) {
22
} VhostUserInflight;
25
/* set up irq routing */
23
26
- kvm_init_irq_routing(kvm_state);
24
-#if defined(_WIN32)
27
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
25
+#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
28
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
26
# define VU_PACKED __attribute__((gcc_struct, packed))
29
}
27
#else
30
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
28
# define VU_PACKED __attribute__((packed))
29
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
31
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_kvm.c
31
--- a/include/qemu/compiler.h
33
+++ b/hw/intc/arm_gicv3_kvm.c
32
+++ b/include/qemu/compiler.h
34
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
33
@@ -XXX,XX +XXX,XX @@
35
34
36
if (kvm_has_gsi_routing()) {
35
#define QEMU_SENTINEL __attribute__((sentinel))
37
/* set up irq routing */
36
38
- kvm_init_irq_routing(kvm_state);
37
-#if defined(_WIN32)
39
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
38
+#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
40
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
39
# define QEMU_PACKED __attribute__((gcc_struct, packed))
41
}
40
#else
41
# define QEMU_PACKED __attribute__((packed))
42
diff --git a/scripts/cocci-macro-file.h b/scripts/cocci-macro-file.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/scripts/cocci-macro-file.h
45
+++ b/scripts/cocci-macro-file.h
46
@@ -XXX,XX +XXX,XX @@
47
#define QEMU_NORETURN __attribute__ ((__noreturn__))
48
#define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
49
#define QEMU_SENTINEL __attribute__((sentinel))
50
-#define QEMU_PACKED __attribute__((gcc_struct, packed))
51
+
52
+#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
53
+# define QEMU_PACKED __attribute__((gcc_struct, packed))
54
+#else
55
+# define QEMU_PACKED __attribute__((packed))
56
+#endif
57
58
#define cat(x,y) x ## y
59
#define cat2(x,y) cat(x,y)
42
--
60
--
43
2.17.1
61
2.20.1
44
62
45
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
[Qemu-devel] [PULL 08/15] qga: Fix mingw compilation warnings on enum conversion
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
2
3
Coverity found that the string return by 'object_get_canonical_path' was not
3
The win2qemu[] is supposed to be the conversion table to convert between
4
being freed at two locations in the model (CID 1391294 and CID 1391293) and
4
STORAGE_BUS_TYPE in Windows SDK and GuestDiskBusType in qga.
5
also that a memset was being called with a value greater than the max of a byte
6
on the second argument (CID 1391286). This patch corrects this by adding the
7
freeing of the strings and also changing to memset to zero instead on
8
descriptor unaligned errors.
9
5
10
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
6
But it was incorrectly written that it forces to set a GuestDiskBusType
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
value to STORAGE_BUS_TYPE, which generates an enum conversion warning in clang.
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
13
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
9
Suggested-by: Eric Blake <eblake@redhat.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Message-id: 20190503003650.10137-1-driver1998@foxmail.com
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
---
17
hw/dma/xlnx-zdma.c | 10 +++++++---
18
qga/commands-win32.c | 2 +-
18
1 file changed, 7 insertions(+), 3 deletions(-)
19
1 file changed, 1 insertion(+), 1 deletion(-)
19
20
20
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
21
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/dma/xlnx-zdma.c
23
--- a/qga/commands-win32.c
23
+++ b/hw/dma/xlnx-zdma.c
24
+++ b/qga/commands-win32.c
24
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
25
@@ -XXX,XX +XXX,XX @@ void qmp_guest_file_flush(int64_t handle, Error **errp)
25
qemu_log_mask(LOG_GUEST_ERROR,
26
26
"zdma: unaligned descriptor at %" PRIx64,
27
#ifdef CONFIG_QGA_NTDDSCSI
27
addr);
28
28
- memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
29
-static STORAGE_BUS_TYPE win2qemu[] = {
29
+ memset(buf, 0x0, sizeof(XlnxZDMADescr));
30
+static GuestDiskBusType win2qemu[] = {
30
s->error = true;
31
[BusTypeUnknown] = GUEST_DISK_BUS_TYPE_UNKNOWN,
31
return false;
32
[BusTypeScsi] = GUEST_DISK_BUS_TYPE_SCSI,
32
}
33
[BusTypeAtapi] = GUEST_DISK_BUS_TYPE_IDE,
33
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
34
RegisterInfo *r = &s->regs_info[addr / 4];
35
36
if (!r->data) {
37
+ gchar *path = object_get_canonical_path(OBJECT(s));
38
qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
39
- object_get_canonical_path(OBJECT(s)),
40
+ path,
41
addr);
42
+ g_free(path);
43
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
44
zdma_ch_imr_update_irq(s);
45
return 0;
46
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
47
RegisterInfo *r = &s->regs_info[addr / 4];
48
49
if (!r->data) {
50
+ gchar *path = object_get_canonical_path(OBJECT(s));
51
qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
52
- object_get_canonical_path(OBJECT(s)),
53
+ path,
54
addr, value);
55
+ g_free(path);
56
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
57
zdma_ch_imr_update_irq(s);
58
return;
59
--
34
--
60
2.17.1
35
2.20.1
61
36
62
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
[Qemu-devel] [PULL 09/15] util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64
1
From: Paolo Bonzini <pbonzini@redhat.com>
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
2
3
cpregs_keys is an uint32_t* so the allocation should use uint32_t.
3
Windows ARM64 uses LLP64 model, which breaks current assumptions.
4
g_new is even better because it is type-safe.
5
4
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
5
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20190503003707.10185-1-driver1998@foxmail.com
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/gdbstub.c | 3 +--
13
util/cacheinfo.c | 2 +-
12
1 file changed, 1 insertion(+), 2 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
15
14
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
16
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/gdbstub.c
18
--- a/util/cacheinfo.c
17
+++ b/target/arm/gdbstub.c
19
+++ b/util/cacheinfo.c
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
20
@@ -XXX,XX +XXX,XX @@ static void sys_cache_info(int *isize, int *dsize)
19
RegisterSysregXmlParam param = {cs, s};
21
static void arch_cache_info(int *isize, int *dsize)
20
22
{
21
cpu->dyn_xml.num_cpregs = 0;
23
if (*isize == 0 || *dsize == 0) {
22
- cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
24
- unsigned long ctr;
23
- g_hash_table_size(cpu->cp_regs));
25
+ uint64_t ctr;
24
+ cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
26
25
g_string_printf(s, "<?xml version=\"1.0\"?>");
27
/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
26
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
28
but (at least under Linux) these are marked protected by the
27
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
28
--
29
--
29
2.17.1
30
2.20.1
30
31
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
[Qemu-devel] [PULL 10/15] osdep: Fix mingw compilation regarding stdio formats
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
2
3
It forgot to increase clroffset during the loop. So it only clear the
3
I encountered the following compilation error on mingw:
4
first 4 bytes.
5
4
6
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
5
/mnt/d/qemu/include/qemu/osdep.h:97:9: error: '__USE_MINGW_ANSI_STDIO' macro redefined [-Werror,-Wmacro-redefined]
7
Cc: qemu-stable@nongnu.org
6
#define __USE_MINGW_ANSI_STDIO 1
8
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
7
^
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
/mnt/d/llvm-mingw/aarch64-w64-mingw32/include/_mingw.h:433:9: note: previous definition is here
10
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
9
#define __USE_MINGW_ANSI_STDIO 0 /* was not defined so it should be 0 */
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
11
It turns out that __USE_MINGW_ANSI_STDIO must be set before any
12
system headers are included, not just before stdio.h.
13
14
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
15
Reviewed-by: Thomas Huth <thuth@redhat.com>
16
Reviewed-by: Stefan Weil <sw@weilnetz.de>
17
Message-id: 20190503003719.10233-1-driver1998@foxmail.com
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
20
---
14
hw/intc/arm_gicv3_kvm.c | 1 +
21
include/qemu/osdep.h | 10 +++++-----
15
1 file changed, 1 insertion(+)
22
1 file changed, 5 insertions(+), 5 deletions(-)
16
23
17
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
24
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
18
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/arm_gicv3_kvm.c
26
--- a/include/qemu/osdep.h
20
+++ b/hw/intc/arm_gicv3_kvm.c
27
+++ b/include/qemu/osdep.h
21
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
28
@@ -XXX,XX +XXX,XX @@ extern int daemon(int, int);
22
if (clroffset != 0) {
29
#endif
23
reg = 0;
30
#endif
24
kvm_gicd_access(s, clroffset, &reg, true);
31
25
+ clroffset += 4;
32
+/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */
26
}
33
+#ifdef __MINGW32__
27
reg = *gic_bmp_ptr32(bmp, irq);
34
+#define __USE_MINGW_ANSI_STDIO 1
28
kvm_gicd_access(s, offset, &reg, true);
35
+#endif
36
+
37
#include <stdarg.h>
38
#include <stddef.h>
39
#include <stdbool.h>
40
#include <stdint.h>
41
#include <sys/types.h>
42
#include <stdlib.h>
43
-
44
-/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */
45
-#ifdef __MINGW32__
46
-#define __USE_MINGW_ANSI_STDIO 1
47
-#endif
48
#include <stdio.h>
49
50
#include <string.h>
29
--
51
--
30
2.17.1
52
2.20.1
31
53
32
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
[Qemu-devel] [PULL 11/15] hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
1
Add entries to MAINTAINERS to cover the newer MPS2 boards and
1
Rule R_CQRV says that if two pending interrupts have the same
2
the new devices they use.
2
group priority then ties are broken by looking at the subpriority.
3
We had a comment describing this but had forgotten to actually
4
implement the subpriority comparison. Correct the omission.
5
6
(The further tie break rules of "lowest exception number" and
7
"secure before non-secure" are handled implicitly by the order
8
in which we iterate through the exceptions in the loops.)
3
9
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20190430131439.25251-2-peter.maydell@linaro.org
6
---
13
---
7
MAINTAINERS | 9 +++++++--
14
hw/intc/armv7m_nvic.c | 9 +++++++--
8
1 file changed, 7 insertions(+), 2 deletions(-)
15
1 file changed, 7 insertions(+), 2 deletions(-)
9
16
10
diff --git a/MAINTAINERS b/MAINTAINERS
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
11
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
12
--- a/MAINTAINERS
19
--- a/hw/intc/armv7m_nvic.c
13
+++ b/MAINTAINERS
20
+++ b/hw/intc/armv7m_nvic.c
14
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
21
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state_secure(NVICState *s)
15
F: include/hw/timer/cmsdk-apb-timer.h
22
int active_prio = NVIC_NOEXC_PRIO;
16
F: hw/char/cmsdk-apb-uart.c
23
int pend_irq = 0;
17
F: include/hw/char/cmsdk-apb-uart.h
24
bool pending_is_s_banked = false;
18
+F: hw/misc/tz-ppc.c
25
+ int pend_subprio = 0;
19
+F: include/hw/misc/tz-ppc.h
26
20
27
/* R_CQRV: precedence is by:
21
ARM cores
28
* - lowest group priority; if both the same then
22
M: Peter Maydell <peter.maydell@linaro.org>
29
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state_secure(NVICState *s)
23
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
30
for (i = 1; i < s->num_irq; i++) {
24
L: qemu-arm@nongnu.org
31
for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
25
S: Maintained
32
VecInfo *vec;
26
F: hw/arm/mps2.c
33
- int prio;
27
-F: hw/misc/mps2-scc.c
34
+ int prio, subprio;
28
-F: include/hw/misc/mps2-scc.h
35
bool targets_secure;
29
+F: hw/arm/mps2-tz.c
36
30
+F: hw/misc/mps2-*.c
37
if (bank == M_REG_S) {
31
+F: include/hw/misc/mps2-*.h
38
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state_secure(NVICState *s)
32
+F: hw/arm/iotkit.c
39
}
33
+F: include/hw/arm/iotkit.h
40
34
41
prio = exc_group_prio(s, vec->prio, targets_secure);
35
Musicpal
42
- if (vec->enabled && vec->pending && prio < pend_prio) {
36
M: Jan Kiszka <jan.kiszka@web.de>
43
+ subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure);
44
+ if (vec->enabled && vec->pending &&
45
+ ((prio < pend_prio) ||
46
+ (prio == pend_prio && prio >= 0 && subprio < pend_subprio))) {
47
pend_prio = prio;
48
+ pend_subprio = subprio;
49
pend_irq = i;
50
pending_is_s_banked = (bank == M_REG_S);
51
}
37
--
52
--
38
2.17.1
53
2.20.1
39
54
40
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
[Qemu-devel] [PULL 12/15] hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
1
The FRECPX instructions should (like most other floating point operations)
1
The non-secure versions of the BFAR and BFSR registers are
2
honour the FPCR.FZ bit which specifies whether input denormals should
2
supposed to be RAZ/WI if AICR.BFHFNMINS == 0; we were
3
be flushed to zero (or FZ16 for the half-precision version).
3
incorrectly allowing NS code to access the real values.
4
We forgot to implement this, which doesn't affect the results (since
5
the calculation doesn't actually care about the mantissa bits) but did
6
mean we were failing to set the FPSR.IDC bit.
7
4
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
7
Message-id: 20190430131439.25251-3-peter.maydell@linaro.org
11
---
8
---
12
target/arm/helper-a64.c | 6 ++++++
9
hw/intc/armv7m_nvic.c | 27 ++++++++++++++++++++++++---
13
1 file changed, 6 insertions(+)
10
1 file changed, 24 insertions(+), 3 deletions(-)
14
11
15
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
12
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.c
14
--- a/hw/intc/armv7m_nvic.c
18
+++ b/target/arm/helper-a64.c
15
+++ b/hw/intc/armv7m_nvic.c
19
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
16
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
20
return nan;
17
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
21
}
18
goto bad_offset;
22
19
}
23
+ a = float16_squash_input_denormal(a, fpst);
20
+ if (!attrs.secure &&
21
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
22
+ return 0;
23
+ }
24
return cpu->env.v7m.bfar;
25
case 0xd3c: /* Aux Fault Status. */
26
/* TODO: Implement fault status registers. */
27
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
28
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
29
goto bad_offset;
30
}
31
+ if (!attrs.secure &&
32
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
33
+ return;
34
+ }
35
cpu->env.v7m.bfar = value;
36
return;
37
case 0xd3c: /* Aux Fault Status. */
38
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
39
val = 0;
40
break;
41
};
42
- /* The BFSR bits [15:8] are shared between security states
43
- * and we store them in the NS copy
44
+ /*
45
+ * The BFSR bits [15:8] are shared between security states
46
+ * and we store them in the NS copy. They are RAZ/WI for
47
+ * NS code if AIRCR.BFHFNMINS is 0.
48
*/
49
val = s->cpu->env.v7m.cfsr[attrs.secure];
50
- val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
51
+ if (!attrs.secure &&
52
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
53
+ val &= ~R_V7M_CFSR_BFSR_MASK;
54
+ } else {
55
+ val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
56
+ }
57
val = extract32(val, (offset - 0xd28) * 8, size * 8);
58
break;
59
case 0xfe0 ... 0xfff: /* ID. */
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
61
*/
62
value <<= ((offset - 0xd28) * 8);
63
64
+ if (!attrs.secure &&
65
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
66
+ /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */
67
+ value &= ~R_V7M_CFSR_BFSR_MASK;
68
+ }
24
+
69
+
25
val16 = float16_val(a);
70
s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
26
sbit = 0x8000 & val16;
71
if (attrs.secure) {
27
exp = extract32(val16, 10, 5);
72
/* The BFSR bits [15:8] are shared between security states
28
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
29
return nan;
30
}
31
32
+ a = float32_squash_input_denormal(a, fpst);
33
+
34
val32 = float32_val(a);
35
sbit = 0x80000000ULL & val32;
36
exp = extract32(val32, 23, 8);
37
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
38
return nan;
39
}
40
41
+ a = float64_squash_input_denormal(a, fpst);
42
+
43
val64 = float64_val(a);
44
sbit = 0x8000000000000000ULL & val64;
45
exp = extract64(float64_val(a), 52, 11);
46
--
73
--
47
2.17.1
74
2.20.1
48
75
49
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
[Qemu-devel] [PULL 13/15] hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
The M-profile architecture specifies that the DebugMonitor exception
2
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
2
should be initially disabled, not enabled. It should be controlled
3
Its callers either have an attrs value to hand, or don't care
3
by the DEMCR register's MON_EN bit, but we don't implement that
4
and can use MEMTXATTRS_UNSPECIFIED.
4
register yet (like most of the debug architecture for M-profile).
5
6
Note that BKPT instructions will still work, because they
7
will be escalated to HardFault.
5
8
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20190430131439.25251-4-peter.maydell@linaro.org
9
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
10
---
12
---
11
include/exec/exec-all.h | 5 +++--
13
hw/intc/armv7m_nvic.c | 4 +++-
12
accel/tcg/translate-all.c | 2 +-
14
1 file changed, 3 insertions(+), 1 deletion(-)
13
exec.c | 2 +-
14
target/xtensa/op_helper.c | 3 ++-
15
4 files changed, 7 insertions(+), 5 deletions(-)
16
15
17
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
16
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/exec-all.h
18
--- a/hw/intc/armv7m_nvic.c
20
+++ b/include/exec/exec-all.h
19
+++ b/hw/intc/armv7m_nvic.c
21
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
20
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
22
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
21
* the System Handler Control register
23
hwaddr paddr, int prot,
22
*/
24
int mmu_idx, target_ulong size);
23
s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
25
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
24
- s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1;
26
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
25
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
27
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
26
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
28
uintptr_t retaddr);
27
29
#else
28
+ /* DebugMonitor is enabled via DEMCR.MON_EN */
30
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
29
+ s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0;
31
uint16_t idxmap)
30
+
32
{
31
resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
33
}
32
s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
34
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
33
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
35
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
36
+ MemTxAttrs attrs)
37
{
38
}
39
#endif
40
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/accel/tcg/translate-all.c
43
+++ b/accel/tcg/translate-all.c
44
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
45
}
46
47
#if !defined(CONFIG_USER_ONLY)
48
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
49
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
50
{
51
ram_addr_t ram_addr;
52
MemoryRegion *mr;
53
diff --git a/exec.c b/exec.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/exec.c
56
+++ b/exec.c
57
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
58
if (phys != -1) {
59
/* Locks grabbed by tb_invalidate_phys_addr */
60
tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
61
- phys | (pc & ~TARGET_PAGE_MASK));
62
+ phys | (pc & ~TARGET_PAGE_MASK), attrs);
63
}
64
}
65
#endif
66
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/xtensa/op_helper.c
69
+++ b/target/xtensa/op_helper.c
70
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
71
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
72
&paddr, &page_size, &access);
73
if (ret == 0) {
74
- tb_invalidate_phys_addr(&address_space_memory, paddr);
75
+ tb_invalidate_phys_addr(&address_space_memory, paddr,
76
+ MEMTXATTRS_UNSPECIFIED);
77
}
78
}
79
80
--
34
--
81
2.17.1
35
2.20.1
82
36
83
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
[Qemu-devel] [PULL 14/15] target/arm: Implement XPSR GE bits
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
In the M-profile architecture, if the CPU implements the DSP extension
2
add MemTxAttrs as an argument to flatview_access_valid().
2
then the XPSR has GE bits, in the same way as the A-profile CPSR. When
3
Its callers now all have an attrs value to hand, so we can
3
we added DSP extension support we forgot to add support for reading
4
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
4
and writing the GE bits, which are stored in env->GE. We did put in
5
the code to add XPSR_GE to the mask of bits to update in the v7m_msr
6
helper, but forgot it in v7m_mrs. We also must not allow the XPSR we
7
pull off the stack on exception return to set the nonexistent GE bits.
8
Correct these errors:
9
* read and write env->GE in xpsr_read() and xpsr_write()
10
* only set GE bits on exception return if DSP present
11
* read GE bits for MRS if DSP present
5
12
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
15
Message-id: 20190430131439.25251-5-peter.maydell@linaro.org
10
---
16
---
11
exec.c | 12 +++++-------
17
target/arm/cpu.h | 4 ++++
12
1 file changed, 5 insertions(+), 7 deletions(-)
18
target/arm/helper.c | 12 ++++++++++--
19
2 files changed, 14 insertions(+), 2 deletions(-)
13
20
14
diff --git a/exec.c b/exec.c
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
23
--- a/target/arm/cpu.h
17
+++ b/exec.c
24
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
25
@@ -XXX,XX +XXX,XX @@ static inline uint32_t xpsr_read(CPUARMState *env)
19
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
26
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
20
const uint8_t *buf, int len);
27
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
21
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
28
| ((env->condexec_bits & 0xfc) << 8)
22
- bool is_write);
29
+ | (env->GE << 16)
23
+ bool is_write, MemTxAttrs attrs);
30
| env->v7m.exception;
24
25
static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
26
unsigned len, MemTxAttrs attrs)
27
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
28
#endif
29
30
return flatview_access_valid(subpage->fv, addr + subpage->base,
31
- len, is_write);
32
+ len, is_write, attrs);
33
}
31
}
34
32
35
static const MemoryRegionOps subpage_ops = {
33
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
36
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
34
if (mask & XPSR_Q) {
37
}
35
env->QF = ((val & XPSR_Q) != 0);
38
36
}
39
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
37
+ if (mask & XPSR_GE) {
40
- bool is_write)
38
+ env->GE = (val & XPSR_GE) >> 16;
41
+ bool is_write, MemTxAttrs attrs)
39
+ }
40
if (mask & XPSR_T) {
41
env->thumb = ((val & XPSR_T) != 0);
42
}
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/helper.c
46
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
42
{
48
{
43
MemoryRegion *mr;
49
CPUARMState *env = &cpu->env;
44
hwaddr l, xlat;
50
uint32_t excret;
45
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
51
- uint32_t xpsr;
46
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
52
+ uint32_t xpsr, xpsr_mask;
47
if (!memory_access_is_direct(mr, is_write)) {
53
bool ufault = false;
48
l = memory_access_size(mr, l, addr);
54
bool sfault = false;
49
- /* When our callers all have attrs we'll pass them through here */
55
bool return_to_sp_process;
50
- if (!memory_region_access_valid(mr, xlat, l, is_write,
56
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
51
- MEMTXATTRS_UNSPECIFIED)) {
52
+ if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
53
return false;
54
}
55
}
57
}
56
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
58
*frame_sp_p = frameptr;
57
59
}
58
rcu_read_lock();
60
+
59
fv = address_space_to_flatview(as);
61
+ xpsr_mask = ~(XPSR_SPREALIGN | XPSR_SFPA);
60
- result = flatview_access_valid(fv, addr, len, is_write);
62
+ if (!arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
61
+ result = flatview_access_valid(fv, addr, len, is_write, attrs);
63
+ xpsr_mask &= ~XPSR_GE;
62
rcu_read_unlock();
64
+ }
63
return result;
65
/* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
64
}
66
- xpsr_write(env, xpsr, ~(XPSR_SPREALIGN | XPSR_SFPA));
67
+ xpsr_write(env, xpsr, xpsr_mask);
68
69
if (env->v7m.secure) {
70
bool sfpa = xpsr & XPSR_SFPA;
71
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
72
}
73
if (!(reg & 4)) {
74
mask |= XPSR_NZCV | XPSR_Q; /* APSR */
75
+ if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
76
+ mask |= XPSR_GE;
77
+ }
78
}
79
/* EPSR reads as zero */
80
return xpsr_read(env) & mask;
65
--
81
--
66
2.17.1
82
2.20.1
67
83
68
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
[Qemu-devel] [PULL 15/15] target/arm: Stop using variable length array in dc_zva
1
In commit f0aff255700 we made cpacr_write() enforce that some CPACR
1
Currently the dc_zva helper function uses a variable length
2
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
2
array. In fact we know (as the comment above remarks) that
3
we forgot to also update the register's reset value. The effect
3
the length of this array is bounded because the architecture
4
was that (a) a guest that read CPACR on reset would not see ones in
4
limits the block size and QEMU limits the target page size.
5
the RAO bits, and (b) if you did a migration before the guest did
5
Use a fixed array size and assert that we don't run off it.
6
a write to the CPACR then the migration would fail because the
7
destination would enforce the RAO bits and then complain that they
8
didn't match the zero value from the source.
9
6
10
Implement reset for the CPACR using a custom reset function
11
that just calls cpacr_write(), to avoid having to duplicate
12
the logic for which bits are RAO.
13
14
This bug would affect migration for TCG CPUs which are ARMv7
15
with VFP but without one of Neon or VFPv3.
16
17
Reported-by: Cédric Le Goater <clg@kaod.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Tested-by: Cédric Le Goater <clg@kaod.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20190503120448.13385-1-peter.maydell@linaro.org
21
---
12
---
22
target/arm/helper.c | 10 +++++++++-
13
target/arm/helper.c | 8 ++++++--
23
1 file changed, 9 insertions(+), 1 deletion(-)
14
1 file changed, 6 insertions(+), 2 deletions(-)
24
15
25
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
28
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
29
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
@@ -XXX,XX +XXX,XX @@
30
env->cp15.cpacr_el1 = value;
21
#include "qemu/osdep.h"
31
}
22
+#include "qemu/units.h"
32
23
#include "target/arm/idau.h"
33
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
24
#include "trace.h"
34
+{
25
#include "cpu.h"
35
+ /* Call cpacr_write() so that we reset with the correct RAO bits set
26
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
36
+ * for our CPU features.
27
* We know that in fact for any v8 CPU the page size is at least 4K
37
+ */
28
* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
38
+ cpacr_write(env, ri, 0);
29
* 1K as an artefact of legacy v5 subpage support being present in the
39
+}
30
- * same QEMU executable.
31
+ * same QEMU executable. So in practice the hostaddr[] array has
32
+ * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
33
*/
34
int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
35
- void *hostaddr[maxidx];
36
+ void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
37
int try, i;
38
unsigned mmu_idx = cpu_mmu_index(env, false);
39
TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
40
41
+ assert(maxidx <= ARRAY_SIZE(hostaddr));
40
+
42
+
41
static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
43
for (try = 0; try < 2; try++) {
42
bool isread)
44
43
{
45
for (i = 0; i < maxidx; i++) {
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
45
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
46
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
47
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
48
- .resetvalue = 0, .writefn = cpacr_write },
49
+ .resetfn = cpacr_reset, .writefn = cpacr_write },
50
REGINFO_SENTINEL
51
};
52
53
--
46
--
54
2.17.1
47
2.20.1
55
48
56
49
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
Deleted patch
1
Add more detail to the documentation for memory_region_init_iommu()
2
and other IOMMU-related functions and data structures.
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
9
---
10
include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
11
1 file changed, 95 insertions(+), 10 deletions(-)
12
13
diff --git a/include/exec/memory.h b/include/exec/memory.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/memory.h
16
+++ b/include/exec/memory.h
17
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
18
IOMMU_ATTR_SPAPR_TCE_FD
19
};
20
21
+/**
22
+ * IOMMUMemoryRegionClass:
23
+ *
24
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
25
+ * and provide an implementation of at least the @translate method here
26
+ * to handle requests to the memory region. Other methods are optional.
27
+ *
28
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
29
+ * to report whenever mappings are changed, by calling
30
+ * memory_region_notify_iommu() (or, if necessary, by calling
31
+ * memory_region_notify_one() for each registered notifier).
32
+ */
33
typedef struct IOMMUMemoryRegionClass {
34
/* private */
35
struct DeviceClass parent_class;
36
37
/*
38
- * Return a TLB entry that contains a given address. Flag should
39
- * be the access permission of this translation operation. We can
40
- * set flag to IOMMU_NONE to mean that we don't need any
41
- * read/write permission checks, like, when for region replay.
42
+ * Return a TLB entry that contains a given address.
43
+ *
44
+ * The IOMMUAccessFlags indicated via @flag are optional and may
45
+ * be specified as IOMMU_NONE to indicate that the caller needs
46
+ * the full translation information for both reads and writes. If
47
+ * the access flags are specified then the IOMMU implementation
48
+ * may use this as an optimization, to stop doing a page table
49
+ * walk as soon as it knows that the requested permissions are not
50
+ * allowed. If IOMMU_NONE is passed then the IOMMU must do the
51
+ * full page table walk and report the permissions in the returned
52
+ * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
53
+ * return different mappings for reads and writes.)
54
+ *
55
+ * The returned information remains valid while the caller is
56
+ * holding the big QEMU lock or is inside an RCU critical section;
57
+ * if the caller wishes to cache the mapping beyond that it must
58
+ * register an IOMMU notifier so it can invalidate its cached
59
+ * information when the IOMMU mapping changes.
60
+ *
61
+ * @iommu: the IOMMUMemoryRegion
62
+ * @hwaddr: address to be translated within the memory region
63
+ * @flag: requested access permissions
64
*/
65
IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
66
IOMMUAccessFlags flag);
67
- /* Returns minimum supported page size */
68
+ /* Returns minimum supported page size in bytes.
69
+ * If this method is not provided then the minimum is assumed to
70
+ * be TARGET_PAGE_SIZE.
71
+ *
72
+ * @iommu: the IOMMUMemoryRegion
73
+ */
74
uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
75
- /* Called when IOMMU Notifier flag changed */
76
+ /* Called when IOMMU Notifier flag changes (ie when the set of
77
+ * events which IOMMU users are requesting notification for changes).
78
+ * Optional method -- need not be provided if the IOMMU does not
79
+ * need to know exactly which events must be notified.
80
+ *
81
+ * @iommu: the IOMMUMemoryRegion
82
+ * @old_flags: events which previously needed to be notified
83
+ * @new_flags: events which now need to be notified
84
+ */
85
void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
86
IOMMUNotifierFlag old_flags,
87
IOMMUNotifierFlag new_flags);
88
- /* Set this up to provide customized IOMMU replay function */
89
+ /* Called to handle memory_region_iommu_replay().
90
+ *
91
+ * The default implementation of memory_region_iommu_replay() is to
92
+ * call the IOMMU translate method for every page in the address space
93
+ * with flag == IOMMU_NONE and then call the notifier if translate
94
+ * returns a valid mapping. If this method is implemented then it
95
+ * overrides the default behaviour, and must provide the full semantics
96
+ * of memory_region_iommu_replay(), by calling @notifier for every
97
+ * translation present in the IOMMU.
98
+ *
99
+ * Optional method -- an IOMMU only needs to provide this method
100
+ * if the default is inefficient or produces undesirable side effects.
101
+ *
102
+ * Note: this is not related to record-and-replay functionality.
103
+ */
104
void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
105
106
- /* Get IOMMU misc attributes */
107
- int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
108
+ /* Get IOMMU misc attributes. This is an optional method that
109
+ * can be used to allow users of the IOMMU to get implementation-specific
110
+ * information. The IOMMU implements this method to handle calls
111
+ * by IOMMU users to memory_region_iommu_get_attr() by filling in
112
+ * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
113
+ * the IOMMU supports. If the method is unimplemented then
114
+ * memory_region_iommu_get_attr() will always return -EINVAL.
115
+ *
116
+ * @iommu: the IOMMUMemoryRegion
117
+ * @attr: attribute being queried
118
+ * @data: memory to fill in with the attribute data
119
+ *
120
+ * Returns 0 on success, or a negative errno; in particular
121
+ * returns -EINVAL for unrecognized or unimplemented attribute types.
122
+ */
123
+ int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
124
void *data);
125
} IOMMUMemoryRegionClass;
126
127
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
128
* An IOMMU region translates addresses and forwards accesses to a target
129
* memory region.
130
*
131
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
132
+ * @_iommu_mr should be a pointer to enough memory for an instance of
133
+ * that subclass, @instance_size is the size of that subclass, and
134
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
135
+ * instance of the subclass, and its methods will then be called to handle
136
+ * accesses to the memory region. See the documentation of
137
+ * #IOMMUMemoryRegionClass for further details.
138
+ *
139
* @_iommu_mr: the #IOMMUMemoryRegion to be initialized
140
* @instance_size: the IOMMUMemoryRegion subclass instance size
141
* @mrtypename: the type name of the #IOMMUMemoryRegion
142
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
143
* a notifier with the minimum page granularity returned by
144
* mr->iommu_ops->get_page_size().
145
*
146
+ * Note: this is not related to record-and-replay functionality.
147
+ *
148
* @iommu_mr: the memory region to observe
149
* @n: the notifier to which to replay iommu mappings
150
*/
151
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
152
* memory_region_iommu_replay_all: replay existing IOMMU translations
153
* to all the notifiers registered.
154
*
155
+ * Note: this is not related to record-and-replay functionality.
156
+ *
157
* @iommu_mr: the memory region to observe
158
*/
159
void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
160
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
161
* memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
162
* defined on the IOMMU.
163
*
164
- * Returns 0 if succeded, error code otherwise.
165
+ * Returns 0 on success, or a negative errno otherwise. In particular,
166
+ * -EINVAL indicates that the IOMMU does not support the requested
167
+ * attribute.
168
*
169
* @iommu_mr: the memory region
170
* @attr: the requested attribute
171
--
172
2.17.1
173
174
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_translate()
3
and address_space_translate_cached(). Callers either have an
4
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 4 +++-
12
accel/tcg/translate-all.c | 2 +-
13
exec.c | 14 +++++++++-----
14
hw/vfio/common.c | 3 ++-
15
memory_ldst.inc.c | 18 +++++++++---------
16
target/riscv/helper.c | 2 +-
17
6 files changed, 25 insertions(+), 18 deletions(-)
18
19
diff --git a/include/exec/memory.h b/include/exec/memory.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/memory.h
22
+++ b/include/exec/memory.h
23
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
24
* #MemoryRegion.
25
* @len: pointer to length
26
* @is_write: indicates the transfer direction
27
+ * @attrs: memory attributes
28
*/
29
MemoryRegion *flatview_translate(FlatView *fv,
30
hwaddr addr, hwaddr *xlat,
31
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
32
33
static inline MemoryRegion *address_space_translate(AddressSpace *as,
34
hwaddr addr, hwaddr *xlat,
35
- hwaddr *len, bool is_write)
36
+ hwaddr *len, bool is_write,
37
+ MemTxAttrs attrs)
38
{
39
return flatview_translate(address_space_to_flatview(as),
40
addr, xlat, len, is_write);
41
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/accel/tcg/translate-all.c
44
+++ b/accel/tcg/translate-all.c
45
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
46
hwaddr l = 1;
47
48
rcu_read_lock();
49
- mr = address_space_translate(as, addr, &addr, &l, false);
50
+ mr = address_space_translate(as, addr, &addr, &l, false, attrs);
51
if (!(memory_region_is_ram(mr)
52
|| memory_region_is_romd(mr))) {
53
rcu_read_unlock();
54
diff --git a/exec.c b/exec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/exec.c
57
+++ b/exec.c
58
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
59
rcu_read_lock();
60
while (len > 0) {
61
l = len;
62
- mr = address_space_translate(as, addr, &addr1, &l, true);
63
+ mr = address_space_translate(as, addr, &addr1, &l, true,
64
+ MEMTXATTRS_UNSPECIFIED);
65
66
if (!(memory_region_is_ram(mr) ||
67
memory_region_is_romd(mr))) {
68
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
69
*/
70
static inline MemoryRegion *address_space_translate_cached(
71
MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
72
- hwaddr *plen, bool is_write)
73
+ hwaddr *plen, bool is_write, MemTxAttrs attrs)
74
{
75
MemoryRegionSection section;
76
MemoryRegion *mr;
77
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
78
MemoryRegion *mr;
79
80
l = len;
81
- mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
82
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
83
+ MEMTXATTRS_UNSPECIFIED);
84
flatview_read_continue(cache->fv,
85
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
86
addr1, l, mr);
87
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
88
MemoryRegion *mr;
89
90
l = len;
91
- mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
92
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
93
+ MEMTXATTRS_UNSPECIFIED);
94
flatview_write_continue(cache->fv,
95
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
96
addr1, l, mr);
97
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
98
99
rcu_read_lock();
100
mr = address_space_translate(&address_space_memory,
101
- phys_addr, &phys_addr, &l, false);
102
+ phys_addr, &phys_addr, &l, false,
103
+ MEMTXATTRS_UNSPECIFIED);
104
105
res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
106
rcu_read_unlock();
107
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/vfio/common.c
110
+++ b/hw/vfio/common.c
111
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
112
*/
113
mr = address_space_translate(&address_space_memory,
114
iotlb->translated_addr,
115
- &xlat, &len, writable);
116
+ &xlat, &len, writable,
117
+ MEMTXATTRS_UNSPECIFIED);
118
if (!memory_region_is_ram(mr)) {
119
error_report("iommu map to non memory area %"HWADDR_PRIx"",
120
xlat);
121
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/memory_ldst.inc.c
124
+++ b/memory_ldst.inc.c
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
126
bool release_lock = false;
127
128
RCU_READ_LOCK();
129
- mr = TRANSLATE(addr, &addr1, &l, false);
130
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
131
if (l < 4 || !IS_DIRECT(mr, false)) {
132
release_lock |= prepare_mmio_access(mr);
133
134
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
135
bool release_lock = false;
136
137
RCU_READ_LOCK();
138
- mr = TRANSLATE(addr, &addr1, &l, false);
139
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
140
if (l < 8 || !IS_DIRECT(mr, false)) {
141
release_lock |= prepare_mmio_access(mr);
142
143
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
144
bool release_lock = false;
145
146
RCU_READ_LOCK();
147
- mr = TRANSLATE(addr, &addr1, &l, false);
148
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
149
if (!IS_DIRECT(mr, false)) {
150
release_lock |= prepare_mmio_access(mr);
151
152
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
153
bool release_lock = false;
154
155
RCU_READ_LOCK();
156
- mr = TRANSLATE(addr, &addr1, &l, false);
157
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
158
if (l < 2 || !IS_DIRECT(mr, false)) {
159
release_lock |= prepare_mmio_access(mr);
160
161
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
162
bool release_lock = false;
163
164
RCU_READ_LOCK();
165
- mr = TRANSLATE(addr, &addr1, &l, true);
166
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
167
if (l < 4 || !IS_DIRECT(mr, true)) {
168
release_lock |= prepare_mmio_access(mr);
169
170
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
171
bool release_lock = false;
172
173
RCU_READ_LOCK();
174
- mr = TRANSLATE(addr, &addr1, &l, true);
175
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
176
if (l < 4 || !IS_DIRECT(mr, true)) {
177
release_lock |= prepare_mmio_access(mr);
178
179
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
180
bool release_lock = false;
181
182
RCU_READ_LOCK();
183
- mr = TRANSLATE(addr, &addr1, &l, true);
184
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
185
if (!IS_DIRECT(mr, true)) {
186
release_lock |= prepare_mmio_access(mr);
187
r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
188
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
189
bool release_lock = false;
190
191
RCU_READ_LOCK();
192
- mr = TRANSLATE(addr, &addr1, &l, true);
193
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
194
if (l < 2 || !IS_DIRECT(mr, true)) {
195
release_lock |= prepare_mmio_access(mr);
196
197
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
198
bool release_lock = false;
199
200
RCU_READ_LOCK();
201
- mr = TRANSLATE(addr, &addr1, &l, true);
202
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
203
if (l < 8 || !IS_DIRECT(mr, true)) {
204
release_lock |= prepare_mmio_access(mr);
205
206
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
207
index XXXXXXX..XXXXXXX 100644
208
--- a/target/riscv/helper.c
209
+++ b/target/riscv/helper.c
210
@@ -XXX,XX +XXX,XX @@ restart:
211
MemoryRegion *mr;
212
hwaddr l = sizeof(target_ulong), addr1;
213
mr = address_space_translate(cs->as, pte_addr,
214
- &addr1, &l, false);
215
+ &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
216
if (memory_access_is_direct(mr, true)) {
217
target_ulong *pte_pa =
218
qemu_map_ram_ptr(mr->ram_block, addr1);
219
--
220
2.17.1
221
222
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_map().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 3 ++-
12
include/sysemu/dma.h | 3 ++-
13
exec.c | 6 ++++--
14
target/ppc/mmu-hash64.c | 3 ++-
15
4 files changed, 10 insertions(+), 5 deletions(-)
16
17
diff --git a/include/exec/memory.h b/include/exec/memory.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/memory.h
20
+++ b/include/exec/memory.h
21
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
22
* @addr: address within that address space
23
* @plen: pointer to length of buffer; updated on return
24
* @is_write: indicates the transfer direction
25
+ * @attrs: memory attributes
26
*/
27
void *address_space_map(AddressSpace *as, hwaddr addr,
28
- hwaddr *plen, bool is_write);
29
+ hwaddr *plen, bool is_write, MemTxAttrs attrs);
30
31
/* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
32
*
33
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/sysemu/dma.h
36
+++ b/include/sysemu/dma.h
37
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
38
hwaddr xlen = *len;
39
void *p;
40
41
- p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
42
+ p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
43
+ MEMTXATTRS_UNSPECIFIED);
44
*len = xlen;
45
return p;
46
}
47
diff --git a/exec.c b/exec.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/exec.c
50
+++ b/exec.c
51
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
52
void *address_space_map(AddressSpace *as,
53
hwaddr addr,
54
hwaddr *plen,
55
- bool is_write)
56
+ bool is_write,
57
+ MemTxAttrs attrs)
58
{
59
hwaddr len = *plen;
60
hwaddr l, xlat;
61
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
62
hwaddr *plen,
63
int is_write)
64
{
65
- return address_space_map(&address_space_memory, addr, plen, is_write);
66
+ return address_space_map(&address_space_memory, addr, plen, is_write,
67
+ MEMTXATTRS_UNSPECIFIED);
68
}
69
70
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
71
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/ppc/mmu-hash64.c
74
+++ b/target/ppc/mmu-hash64.c
75
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
76
return NULL;
77
}
78
79
- hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
80
+ hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
81
+ MEMTXATTRS_UNSPECIFIED);
82
if (plen < (n * HASH_PTE_SIZE_64)) {
83
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
84
}
85
--
86
2.17.1
87
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 4 +++-
12
include/sysemu/dma.h | 3 ++-
13
exec.c | 3 ++-
14
target/s390x/diag.c | 6 ++++--
15
target/s390x/excp_helper.c | 3 ++-
16
target/s390x/mmu_helper.c | 3 ++-
17
target/s390x/sigp.c | 3 ++-
18
7 files changed, 17 insertions(+), 8 deletions(-)
19
20
diff --git a/include/exec/memory.h b/include/exec/memory.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/memory.h
23
+++ b/include/exec/memory.h
24
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
25
* @addr: address within that address space
26
* @len: length of the area to be checked
27
* @is_write: indicates the transfer direction
28
+ * @attrs: memory attributes
29
*/
30
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
31
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
32
+ bool is_write, MemTxAttrs attrs);
33
34
/* address_space_map: map a physical memory region into a host virtual address
35
*
36
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/sysemu/dma.h
39
+++ b/include/sysemu/dma.h
40
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
41
DMADirection dir)
42
{
43
return address_space_access_valid(as, addr, len,
44
- dir == DMA_DIRECTION_FROM_DEVICE);
45
+ dir == DMA_DIRECTION_FROM_DEVICE,
46
+ MEMTXATTRS_UNSPECIFIED);
47
}
48
49
static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
50
diff --git a/exec.c b/exec.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/exec.c
53
+++ b/exec.c
54
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
55
}
56
57
bool address_space_access_valid(AddressSpace *as, hwaddr addr,
58
- int len, bool is_write)
59
+ int len, bool is_write,
60
+ MemTxAttrs attrs)
61
{
62
FlatView *fv;
63
bool result;
64
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/s390x/diag.c
67
+++ b/target/s390x/diag.c
68
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
69
return;
70
}
71
if (!address_space_access_valid(&address_space_memory, addr,
72
- sizeof(IplParameterBlock), false)) {
73
+ sizeof(IplParameterBlock), false,
74
+ MEMTXATTRS_UNSPECIFIED)) {
75
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
76
return;
77
}
78
@@ -XXX,XX +XXX,XX @@ out:
79
return;
80
}
81
if (!address_space_access_valid(&address_space_memory, addr,
82
- sizeof(IplParameterBlock), true)) {
83
+ sizeof(IplParameterBlock), true,
84
+ MEMTXATTRS_UNSPECIFIED)) {
85
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
86
return;
87
}
88
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/s390x/excp_helper.c
91
+++ b/target/s390x/excp_helper.c
92
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
93
94
/* check out of RAM access */
95
if (!address_space_access_valid(&address_space_memory, raddr,
96
- TARGET_PAGE_SIZE, rw)) {
97
+ TARGET_PAGE_SIZE, rw,
98
+ MEMTXATTRS_UNSPECIFIED)) {
99
DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
100
(uint64_t)raddr, (uint64_t)ram_size);
101
trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
102
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/s390x/mmu_helper.c
105
+++ b/target/s390x/mmu_helper.c
106
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
107
return ret;
108
}
109
if (!address_space_access_valid(&address_space_memory, pages[i],
110
- TARGET_PAGE_SIZE, is_write)) {
111
+ TARGET_PAGE_SIZE, is_write,
112
+ MEMTXATTRS_UNSPECIFIED)) {
113
trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
114
return -EFAULT;
115
}
116
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/s390x/sigp.c
119
+++ b/target/s390x/sigp.c
120
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
121
cpu_synchronize_state(cs);
122
123
if (!address_space_access_valid(&address_space_memory, addr,
124
- sizeof(struct LowCore), false)) {
125
+ sizeof(struct LowCore), false,
126
+ MEMTXATTRS_UNSPECIFIED)) {
127
set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
128
return;
129
}
130
--
131
2.17.1
132
133
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_extend_translation().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
10
---
11
exec.c | 15 ++++++++++-----
12
1 file changed, 10 insertions(+), 5 deletions(-)
13
14
diff --git a/exec.c b/exec.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
17
+++ b/exec.c
18
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
19
20
static hwaddr
21
flatview_extend_translation(FlatView *fv, hwaddr addr,
22
- hwaddr target_len,
23
- MemoryRegion *mr, hwaddr base, hwaddr len,
24
- bool is_write)
25
+ hwaddr target_len,
26
+ MemoryRegion *mr, hwaddr base, hwaddr len,
27
+ bool is_write, MemTxAttrs attrs)
28
{
29
hwaddr done = 0;
30
hwaddr xlat;
31
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
32
33
memory_region_ref(mr);
34
*plen = flatview_extend_translation(fv, addr, len, mr, xlat,
35
- l, is_write);
36
+ l, is_write, attrs);
37
ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
38
rcu_read_unlock();
39
40
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
41
mr = cache->mrs.mr;
42
memory_region_ref(mr);
43
if (memory_access_is_direct(mr, is_write)) {
44
+ /* We don't care about the memory attributes here as we're only
45
+ * doing this if we found actual RAM, which behaves the same
46
+ * regardless of attributes; so UNSPECIFIED is fine.
47
+ */
48
l = flatview_extend_translation(cache->fv, addr, len, mr,
49
- cache->xlat, l, is_write);
50
+ cache->xlat, l, is_write,
51
+ MEMTXATTRS_UNSPECIFIED);
52
cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
53
} else {
54
cache->ptr = NULL;
55
--
56
2.17.1
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to memory_region_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
The callsite in flatview_access_valid() is part of a recursive
7
loop flatview_access_valid() -> memory_region_access_valid() ->
8
subpage_accepts() -> flatview_access_valid(); we make it pass
9
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
10
have plumbed an attrs parameter through the rest of the loop
11
and we can add an attrs parameter to flatview_access_valid().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
17
---
18
include/exec/memory-internal.h | 3 ++-
19
exec.c | 4 +++-
20
hw/s390x/s390-pci-inst.c | 3 ++-
21
memory.c | 7 ++++---
22
4 files changed, 11 insertions(+), 6 deletions(-)
23
24
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/exec/memory-internal.h
27
+++ b/include/exec/memory-internal.h
28
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
29
extern const MemoryRegionOps unassigned_mem_ops;
30
31
bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
32
- unsigned size, bool is_write);
33
+ unsigned size, bool is_write,
34
+ MemTxAttrs attrs);
35
36
void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
37
AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
38
diff --git a/exec.c b/exec.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/exec.c
41
+++ b/exec.c
42
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
43
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
44
if (!memory_access_is_direct(mr, is_write)) {
45
l = memory_access_size(mr, l, addr);
46
- if (!memory_region_access_valid(mr, xlat, l, is_write)) {
47
+ /* When our callers all have attrs we'll pass them through here */
48
+ if (!memory_region_access_valid(mr, xlat, l, is_write,
49
+ MEMTXATTRS_UNSPECIFIED)) {
50
return false;
51
}
52
}
53
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/s390x/s390-pci-inst.c
56
+++ b/hw/s390x/s390-pci-inst.c
57
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
58
mr = s390_get_subregion(mr, offset, len);
59
offset -= mr->addr;
60
61
- if (!memory_region_access_valid(mr, offset, len, true)) {
62
+ if (!memory_region_access_valid(mr, offset, len, true,
63
+ MEMTXATTRS_UNSPECIFIED)) {
64
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
65
return 0;
66
}
67
diff --git a/memory.c b/memory.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/memory.c
70
+++ b/memory.c
71
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
72
bool memory_region_access_valid(MemoryRegion *mr,
73
hwaddr addr,
74
unsigned size,
75
- bool is_write)
76
+ bool is_write,
77
+ MemTxAttrs attrs)
78
{
79
int access_size_min, access_size_max;
80
int access_size, i;
81
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
82
{
83
MemTxResult r;
84
85
- if (!memory_region_access_valid(mr, addr, size, false)) {
86
+ if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
87
*pval = unassigned_mem_read(mr, addr, size);
88
return MEMTX_DECODE_ERROR;
89
}
90
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
91
unsigned size,
92
MemTxAttrs attrs)
93
{
94
- if (!memory_region_access_valid(mr, addr, size, true)) {
95
+ if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
96
unassigned_mem_write(mr, addr, data, size);
97
return MEMTX_DECODE_ERROR;
98
}
99
--
100
2.17.1
101
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_translate(); all its
3
callers now have attrs available.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
9
---
10
include/exec/memory.h | 7 ++++---
11
exec.c | 17 +++++++++--------
12
2 files changed, 13 insertions(+), 11 deletions(-)
13
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
17
+++ b/include/exec/memory.h
18
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
19
*/
20
MemoryRegion *flatview_translate(FlatView *fv,
21
hwaddr addr, hwaddr *xlat,
22
- hwaddr *len, bool is_write);
23
+ hwaddr *len, bool is_write,
24
+ MemTxAttrs attrs);
25
26
static inline MemoryRegion *address_space_translate(AddressSpace *as,
27
hwaddr addr, hwaddr *xlat,
28
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
29
MemTxAttrs attrs)
30
{
31
return flatview_translate(address_space_to_flatview(as),
32
- addr, xlat, len, is_write);
33
+ addr, xlat, len, is_write, attrs);
34
}
35
36
/* address_space_access_valid: check for validity of accessing an address
37
@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
38
rcu_read_lock();
39
fv = address_space_to_flatview(as);
40
l = len;
41
- mr = flatview_translate(fv, addr, &addr1, &l, false);
42
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
43
if (len == l && memory_access_is_direct(mr, false)) {
44
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
45
memcpy(buf, ptr, len);
46
diff --git a/exec.c b/exec.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/exec.c
49
+++ b/exec.c
50
@@ -XXX,XX +XXX,XX @@ iotlb_fail:
51
52
/* Called from RCU critical section */
53
MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
54
- hwaddr *plen, bool is_write)
55
+ hwaddr *plen, bool is_write,
56
+ MemTxAttrs attrs)
57
{
58
MemoryRegion *mr;
59
MemoryRegionSection section;
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
61
}
62
63
l = len;
64
- mr = flatview_translate(fv, addr, &addr1, &l, true);
65
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
66
}
67
68
return result;
69
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
70
MemTxResult result = MEMTX_OK;
71
72
l = len;
73
- mr = flatview_translate(fv, addr, &addr1, &l, true);
74
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
75
result = flatview_write_continue(fv, addr, attrs, buf, len,
76
addr1, l, mr);
77
78
@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
79
}
80
81
l = len;
82
- mr = flatview_translate(fv, addr, &addr1, &l, false);
83
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
84
}
85
86
return result;
87
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
88
MemoryRegion *mr;
89
90
l = len;
91
- mr = flatview_translate(fv, addr, &addr1, &l, false);
92
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
93
return flatview_read_continue(fv, addr, attrs, buf, len,
94
addr1, l, mr);
95
}
96
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
97
98
while (len > 0) {
99
l = len;
100
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
101
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
102
if (!memory_access_is_direct(mr, is_write)) {
103
l = memory_access_size(mr, l, addr);
104
if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
105
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
106
107
len = target_len;
108
this_mr = flatview_translate(fv, addr, &xlat,
109
- &len, is_write);
110
+ &len, is_write, attrs);
111
if (this_mr != mr || xlat != base + done) {
112
return done;
113
}
114
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
115
l = len;
116
rcu_read_lock();
117
fv = address_space_to_flatview(as);
118
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
119
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
120
121
if (!memory_access_is_direct(mr, is_write)) {
122
if (atomic_xchg(&bounce.in_use, true)) {
123
--
124
2.17.1
125
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_get_iotlb_entry().
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
8
---
9
include/exec/memory.h | 2 +-
10
exec.c | 2 +-
11
hw/virtio/vhost.c | 3 ++-
12
3 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
17
+++ b/include/exec/memory.h
18
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
19
* entry. Should be called from an RCU critical section.
20
*/
21
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
22
- bool is_write);
23
+ bool is_write, MemTxAttrs attrs);
24
25
/* address_space_translate: translate an address range into an address space
26
* into a MemoryRegion and an address range into that section. Should be
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
32
33
/* Called from RCU critical section */
34
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
35
- bool is_write)
36
+ bool is_write, MemTxAttrs attrs)
37
{
38
MemoryRegionSection section;
39
hwaddr xlat, page_mask;
40
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/vhost.c
43
+++ b/hw/virtio/vhost.c
44
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
45
trace_vhost_iotlb_miss(dev, 1);
46
47
iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
48
- iova, write);
49
+ iova, write,
50
+ MEMTXATTRS_UNSPECIFIED);
51
if (iotlb.target_as != NULL) {
52
ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
53
&uaddr, &len);
54
--
55
2.17.1
56
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_do_translate().
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
8
---
9
exec.c | 9 ++++++---
10
1 file changed, 6 insertions(+), 3 deletions(-)
11
12
diff --git a/exec.c b/exec.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/exec.c
15
+++ b/exec.c
16
@@ -XXX,XX +XXX,XX @@ unassigned:
17
* @is_write: whether the translation operation is for write
18
* @is_mmio: whether this can be MMIO, set true if it can
19
* @target_as: the address space targeted by the IOMMU
20
+ * @attrs: memory transaction attributes
21
*
22
* This function is called from RCU critical section
23
*/
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
25
hwaddr *page_mask_out,
26
bool is_write,
27
bool is_mmio,
28
- AddressSpace **target_as)
29
+ AddressSpace **target_as,
30
+ MemTxAttrs attrs)
31
{
32
MemoryRegionSection *section;
33
IOMMUMemoryRegion *iommu_mr;
34
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
35
* but page mask.
36
*/
37
section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
38
- NULL, &page_mask, is_write, false, &as);
39
+ NULL, &page_mask, is_write, false, &as,
40
+ attrs);
41
42
/* Illegal translation */
43
if (section.mr == &io_mem_unassigned) {
44
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
45
46
/* This can be MMIO, so setup MMIO bit. */
47
section = flatview_do_translate(fv, addr, xlat, plen, NULL,
48
- is_write, true, &as);
49
+ is_write, true, &as, attrs);
50
mr = section.mr;
51
52
if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
53
--
54
2.17.1
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_translate_iommu().
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
8
---
9
exec.c | 8 +++++---
10
1 file changed, 5 insertions(+), 3 deletions(-)
11
12
diff --git a/exec.c b/exec.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/exec.c
15
+++ b/exec.c
16
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
17
* @is_write: whether the translation operation is for write
18
* @is_mmio: whether this can be MMIO, set true if it can
19
* @target_as: the address space targeted by the IOMMU
20
+ * @attrs: transaction attributes
21
*
22
* This function is called from RCU critical section. It is the common
23
* part of flatview_do_translate and address_space_translate_cached.
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
25
hwaddr *page_mask_out,
26
bool is_write,
27
bool is_mmio,
28
- AddressSpace **target_as)
29
+ AddressSpace **target_as,
30
+ MemTxAttrs attrs)
31
{
32
MemoryRegionSection *section;
33
hwaddr page_mask = (hwaddr)-1;
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
35
return address_space_translate_iommu(iommu_mr, xlat,
36
plen_out, page_mask_out,
37
is_write, is_mmio,
38
- target_as);
39
+ target_as, attrs);
40
}
41
if (page_mask_out) {
42
/* Not behind an IOMMU, use default page size. */
43
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
44
45
section = address_space_translate_iommu(iommu_mr, xlat, plen,
46
NULL, is_write, true,
47
- &target_as);
48
+ &target_as, attrs);
49
return section.mr;
50
}
51
52
--
53
2.17.1
54
55
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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