[Qemu-devel] [PULL 00/25] target-arm queue
[Qemu-devel] [PULL 00/16] target-arm queue
1
target-arm queue. This has the "plumb txattrs through various
1
The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:
2
bits of exec.c" patches, and a collection of bug fixes from
3
various people.
4
2
5
thanks
3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)
6
-- PMM
7
8
9
10
The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
11
12
Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
13
4
14
are available in the Git repository at:
5
are available in the Git repository at:
15
6
16
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1
17
8
18
for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
9
for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:
19
10
20
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
11
linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)
21
12
22
----------------------------------------------------------------
13
----------------------------------------------------------------
23
target-arm queue:
14
target-arm queue:
24
* target/arm: Honour FPCR.FZ in FRECPX
15
* add MHU and dual-core support to Musca boards
25
* MAINTAINERS: Add entries for newer MPS2 boards and devices
16
* refactor some VFP insns to be gated by ID registers
26
* hw/intc/arm_gicv3: Fix APxR<n> register dispatching
17
* Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
27
* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
18
* Implement ARMv8.2-FHM extension
28
GIC state
19
* Advertise JSCVT via HWCAP for linux-user
29
* tcg: Fix helper function vs host abi for float16
30
* arm: fix qemu crash on startup with -bios option
31
* arm: fix malloc type mismatch
32
* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
33
* Correct CPACR reset value for v7 cores
34
* memory.h: Improve IOMMU related documentation
35
* exec: Plumb transaction attributes through various functions in
36
preparation for allowing IOMMUs to see them
37
* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
38
* ARM: ACPI: Fix use-after-free due to memory realloc
39
* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
40
20
41
----------------------------------------------------------------
21
----------------------------------------------------------------
42
Francisco Iglesias (1):
22
Peter Maydell (11):
43
xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
23
hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
24
hw/arm/armsse: Wire up the MHUs
25
target/arm/cpu: Allow init-svtor property to be set after realize
26
target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
27
hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
28
hw/arm/iotkit-sysctl: Add SSE-200 registers
29
hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
30
hw/arm/armsse: Unify init-svtor and cpuwait handling
31
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
32
target/arm: Gate "miscellaneous FP" insns by ID register field
33
Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
44
34
45
Igor Mammedov (1):
35
Richard Henderson (5):
46
arm: fix qemu crash on startup with -bios option
36
target/arm: Add helpers for FMLAL
37
target/arm: Implement FMLAL and FMLSL for aarch64
38
target/arm: Implement VFMAL and VFMSL for aarch32
39
target/arm: Enable ARMv8.2-FHM for -cpu max
40
linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
47
41
48
Jan Kiszka (1):
42
hw/misc/Makefile.objs | 1 +
49
hw/intc/arm_gicv3: Fix APxR<n> register dispatching
43
include/hw/arm/armsse.h | 3 +-
44
include/hw/misc/armsse-mhu.h | 44 ++++++
45
include/hw/misc/iotkit-sysctl.h | 25 +++-
46
target/arm/arm-powerctl.h | 16 +++
47
target/arm/cpu.h | 76 +++++++++--
48
target/arm/helper.h | 9 ++
49
hw/arm/armsse.c | 91 +++++++++----
50
hw/misc/armsse-mhu.c | 198 +++++++++++++++++++++++++++
51
hw/misc/iotkit-sysctl.c | 294 ++++++++++++++++++++++++++++++++++++++--
52
linux-user/elfload.c | 2 +
53
target/arm/arm-powerctl.c | 56 ++++++++
54
target/arm/cpu.c | 32 ++++-
55
target/arm/cpu64.c | 2 +
56
target/arm/helper.c | 27 +---
57
target/arm/kvm32.c | 23 +++-
58
target/arm/kvm64.c | 2 -
59
target/arm/machine.c | 2 +-
60
target/arm/translate-a64.c | 49 ++++++-
61
target/arm/translate.c | 180 ++++++++++++++++--------
62
target/arm/vec_helper.c | 148 ++++++++++++++++++++
63
MAINTAINERS | 2 +
64
default-configs/arm-softmmu.mak | 1 +
65
hw/misc/trace-events | 4 +
66
24 files changed, 1139 insertions(+), 148 deletions(-)
67
create mode 100644 include/hw/misc/armsse-mhu.h
68
create mode 100644 hw/misc/armsse-mhu.c
50
69
51
Paolo Bonzini (1):
52
arm: fix malloc type mismatch
53
54
Peter Maydell (17):
55
target/arm: Honour FPCR.FZ in FRECPX
56
MAINTAINERS: Add entries for newer MPS2 boards and devices
57
Correct CPACR reset value for v7 cores
58
memory.h: Improve IOMMU related documentation
59
Make tb_invalidate_phys_addr() take a MemTxAttrs argument
60
Make address_space_translate{, _cached}() take a MemTxAttrs argument
61
Make address_space_map() take a MemTxAttrs argument
62
Make address_space_access_valid() take a MemTxAttrs argument
63
Make flatview_extend_translation() take a MemTxAttrs argument
64
Make memory_region_access_valid() take a MemTxAttrs argument
65
Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
66
Make flatview_access_valid() take a MemTxAttrs argument
67
Make flatview_translate() take a MemTxAttrs argument
68
Make address_space_get_iotlb_entry() take a MemTxAttrs argument
69
Make flatview_do_translate() take a MemTxAttrs argument
70
Make address_space_translate_iommu take a MemTxAttrs argument
71
vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
72
73
Richard Henderson (1):
74
tcg: Fix helper function vs host abi for float16
75
76
Shannon Zhao (3):
77
arm_gicv3_kvm: increase clroffset accordingly
78
ARM: ACPI: Fix use-after-free due to memory realloc
79
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
80
81
include/exec/exec-all.h | 5 +-
82
include/exec/helper-head.h | 2 +-
83
include/exec/memory-internal.h | 3 +-
84
include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------
85
include/migration/vmstate.h | 3 +
86
include/sysemu/dma.h | 6 +-
87
accel/tcg/translate-all.c | 4 +-
88
exec.c | 95 ++++++++++++++++++------------
89
hw/arm/boot.c | 18 +++---
90
hw/arm/virt-acpi-build.c | 20 +++++--
91
hw/dma/xlnx-zdma.c | 10 +++-
92
hw/hppa/dino.c | 3 +-
93
hw/intc/arm_gic_kvm.c | 1 -
94
hw/intc/arm_gicv3_cpuif.c | 12 ++--
95
hw/intc/arm_gicv3_kvm.c | 2 +-
96
hw/nvram/fw_cfg.c | 12 ++--
97
hw/s390x/s390-pci-inst.c | 3 +-
98
hw/scsi/esp.c | 3 +-
99
hw/vfio/common.c | 3 +-
100
hw/virtio/vhost.c | 3 +-
101
hw/xen/xen_pt_msi.c | 3 +-
102
memory.c | 12 ++--
103
memory_ldst.inc.c | 18 +++---
104
target/arm/gdbstub.c | 3 +-
105
target/arm/helper-a64.c | 41 +++++++------
106
target/arm/helper.c | 90 ++++++++++++++++-------------
107
target/ppc/mmu-hash64.c | 3 +-
108
target/riscv/helper.c | 2 +-
109
target/s390x/diag.c | 6 +-
110
target/s390x/excp_helper.c | 3 +-
111
target/s390x/mmu_helper.c | 3 +-
112
target/s390x/sigp.c | 3 +-
113
target/xtensa/op_helper.c | 3 +-
114
MAINTAINERS | 9 ++-
115
34 files changed, 353 insertions(+), 182 deletions(-)
116
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
[Qemu-devel] [PULL 01/16] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
1
Add entries to MAINTAINERS to cover the newer MPS2 boards and
1
Implement a model of the Message Handling Unit (MHU) found in
2
the new devices they use.
2
the Arm SSE-200. This is a simple device which just contains
3
some registers which allow the two cores of the SSE-200
4
to raise interrupts on each other.
3
5
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
6
---
9
---
7
MAINTAINERS | 9 +++++++--
10
hw/misc/Makefile.objs | 1 +
8
1 file changed, 7 insertions(+), 2 deletions(-)
11
include/hw/misc/armsse-mhu.h | 44 +++++++
12
hw/misc/armsse-mhu.c | 198 ++++++++++++++++++++++++++++++++
13
MAINTAINERS | 2 +
14
default-configs/arm-softmmu.mak | 1 +
15
hw/misc/trace-events | 4 +
16
6 files changed, 250 insertions(+)
17
create mode 100644 include/hw/misc/armsse-mhu.h
18
create mode 100644 hw/misc/armsse-mhu.c
9
19
20
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/Makefile.objs
23
+++ b/hw/misc/Makefile.objs
24
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
25
obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
26
obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
27
obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o
28
+obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
29
30
obj-$(CONFIG_PVPANIC) += pvpanic.o
31
obj-$(CONFIG_AUX) += auxbus.o
32
diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/misc/armsse-mhu.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * ARM SSE-200 Message Handling Unit (MHU)
40
+ *
41
+ * Copyright (c) 2019 Linaro Limited
42
+ * Written by Peter Maydell
43
+ *
44
+ * This program is free software; you can redistribute it and/or modify
45
+ * it under the terms of the GNU General Public License version 2 or
46
+ * (at your option) any later version.
47
+ */
48
+
49
+/*
50
+ * This is a model of the Message Handling Unit (MHU) which is part of the
51
+ * Arm SSE-200 and documented in
52
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
53
+ *
54
+ * QEMU interface:
55
+ * + sysbus MMIO region 0: the system information register bank
56
+ * + sysbus IRQ 0: interrupt for CPU 0
57
+ * + sysbus IRQ 1: interrupt for CPU 1
58
+ */
59
+
60
+#ifndef HW_MISC_SSE_MHU_H
61
+#define HW_MISC_SSE_MHU_H
62
+
63
+#include "hw/sysbus.h"
64
+
65
+#define TYPE_ARMSSE_MHU "armsse-mhu"
66
+#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
67
+
68
+typedef struct ARMSSEMHU {
69
+ /*< private >*/
70
+ SysBusDevice parent_obj;
71
+
72
+ /*< public >*/
73
+ MemoryRegion iomem;
74
+ qemu_irq cpu0irq;
75
+ qemu_irq cpu1irq;
76
+
77
+ uint32_t cpu0intr;
78
+ uint32_t cpu1intr;
79
+} ARMSSEMHU;
80
+
81
+#endif
82
diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
83
new file mode 100644
84
index XXXXXXX..XXXXXXX
85
--- /dev/null
86
+++ b/hw/misc/armsse-mhu.c
87
@@ -XXX,XX +XXX,XX @@
88
+/*
89
+ * ARM SSE-200 Message Handling Unit (MHU)
90
+ *
91
+ * Copyright (c) 2019 Linaro Limited
92
+ * Written by Peter Maydell
93
+ *
94
+ * This program is free software; you can redistribute it and/or modify
95
+ * it under the terms of the GNU General Public License version 2 or
96
+ * (at your option) any later version.
97
+ */
98
+
99
+/*
100
+ * This is a model of the Message Handling Unit (MHU) which is part of the
101
+ * Arm SSE-200 and documented in
102
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
103
+ */
104
+
105
+#include "qemu/osdep.h"
106
+#include "qemu/log.h"
107
+#include "trace.h"
108
+#include "qapi/error.h"
109
+#include "sysemu/sysemu.h"
110
+#include "hw/sysbus.h"
111
+#include "hw/registerfields.h"
112
+#include "hw/misc/armsse-mhu.h"
113
+
114
+REG32(CPU0INTR_STAT, 0x0)
115
+REG32(CPU0INTR_SET, 0x4)
116
+REG32(CPU0INTR_CLR, 0x8)
117
+REG32(CPU1INTR_STAT, 0x10)
118
+REG32(CPU1INTR_SET, 0x14)
119
+REG32(CPU1INTR_CLR, 0x18)
120
+REG32(PID4, 0xfd0)
121
+REG32(PID5, 0xfd4)
122
+REG32(PID6, 0xfd8)
123
+REG32(PID7, 0xfdc)
124
+REG32(PID0, 0xfe0)
125
+REG32(PID1, 0xfe4)
126
+REG32(PID2, 0xfe8)
127
+REG32(PID3, 0xfec)
128
+REG32(CID0, 0xff0)
129
+REG32(CID1, 0xff4)
130
+REG32(CID2, 0xff8)
131
+REG32(CID3, 0xffc)
132
+
133
+/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
134
+#define INTR_MASK 0xf
135
+
136
+/* PID/CID values */
137
+static const int armsse_mhu_id[] = {
138
+ 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
139
+ 0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
140
+ 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
141
+};
142
+
143
+static void armsse_mhu_update(ARMSSEMHU *s)
144
+{
145
+ qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
146
+ qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
147
+}
148
+
149
+static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
150
+{
151
+ ARMSSEMHU *s = ARMSSE_MHU(opaque);
152
+ uint64_t r;
153
+
154
+ switch (offset) {
155
+ case A_CPU0INTR_STAT:
156
+ r = s->cpu0intr;
157
+ break;
158
+
159
+ case A_CPU1INTR_STAT:
160
+ r = s->cpu1intr;
161
+ break;
162
+
163
+ case A_PID4 ... A_CID3:
164
+ r = armsse_mhu_id[(offset - A_PID4) / 4];
165
+ break;
166
+
167
+ case A_CPU0INTR_SET:
168
+ case A_CPU0INTR_CLR:
169
+ case A_CPU1INTR_SET:
170
+ case A_CPU1INTR_CLR:
171
+ qemu_log_mask(LOG_GUEST_ERROR,
172
+ "SSE MHU: read of write-only register at offset 0x%x\n",
173
+ (int)offset);
174
+ r = 0;
175
+ break;
176
+
177
+ default:
178
+ qemu_log_mask(LOG_GUEST_ERROR,
179
+ "SSE MHU read: bad offset 0x%x\n", (int)offset);
180
+ r = 0;
181
+ break;
182
+ }
183
+ trace_armsse_mhu_read(offset, r, size);
184
+ return r;
185
+}
186
+
187
+static void armsse_mhu_write(void *opaque, hwaddr offset,
188
+ uint64_t value, unsigned size)
189
+{
190
+ ARMSSEMHU *s = ARMSSE_MHU(opaque);
191
+
192
+ trace_armsse_mhu_write(offset, value, size);
193
+
194
+ switch (offset) {
195
+ case A_CPU0INTR_SET:
196
+ s->cpu0intr |= (value & INTR_MASK);
197
+ break;
198
+ case A_CPU0INTR_CLR:
199
+ s->cpu0intr &= ~(value & INTR_MASK);
200
+ break;
201
+ case A_CPU1INTR_SET:
202
+ s->cpu1intr |= (value & INTR_MASK);
203
+ break;
204
+ case A_CPU1INTR_CLR:
205
+ s->cpu1intr &= ~(value & INTR_MASK);
206
+ break;
207
+
208
+ case A_CPU0INTR_STAT:
209
+ case A_CPU1INTR_STAT:
210
+ case A_PID4 ... A_CID3:
211
+ qemu_log_mask(LOG_GUEST_ERROR,
212
+ "SSE MHU: write to read-only register at offset 0x%x\n",
213
+ (int)offset);
214
+ break;
215
+
216
+ default:
217
+ qemu_log_mask(LOG_GUEST_ERROR,
218
+ "SSE MHU write: bad offset 0x%x\n", (int)offset);
219
+ break;
220
+ }
221
+
222
+ armsse_mhu_update(s);
223
+}
224
+
225
+static const MemoryRegionOps armsse_mhu_ops = {
226
+ .read = armsse_mhu_read,
227
+ .write = armsse_mhu_write,
228
+ .endianness = DEVICE_LITTLE_ENDIAN,
229
+ .valid.min_access_size = 4,
230
+ .valid.max_access_size = 4,
231
+};
232
+
233
+static void armsse_mhu_reset(DeviceState *dev)
234
+{
235
+ ARMSSEMHU *s = ARMSSE_MHU(dev);
236
+
237
+ s->cpu0intr = 0;
238
+ s->cpu1intr = 0;
239
+}
240
+
241
+static const VMStateDescription armsse_mhu_vmstate = {
242
+ .name = "armsse-mhu",
243
+ .version_id = 1,
244
+ .minimum_version_id = 1,
245
+ .fields = (VMStateField[]) {
246
+ VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
247
+ VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
248
+ VMSTATE_END_OF_LIST()
249
+ },
250
+};
251
+
252
+static void armsse_mhu_init(Object *obj)
253
+{
254
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
255
+ ARMSSEMHU *s = ARMSSE_MHU(obj);
256
+
257
+ memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
258
+ s, "armsse-mhu", 0x1000);
259
+ sysbus_init_mmio(sbd, &s->iomem);
260
+ sysbus_init_irq(sbd, &s->cpu0irq);
261
+ sysbus_init_irq(sbd, &s->cpu1irq);
262
+}
263
+
264
+static void armsse_mhu_class_init(ObjectClass *klass, void *data)
265
+{
266
+ DeviceClass *dc = DEVICE_CLASS(klass);
267
+
268
+ dc->reset = armsse_mhu_reset;
269
+ dc->vmsd = &armsse_mhu_vmstate;
270
+}
271
+
272
+static const TypeInfo armsse_mhu_info = {
273
+ .name = TYPE_ARMSSE_MHU,
274
+ .parent = TYPE_SYS_BUS_DEVICE,
275
+ .instance_size = sizeof(ARMSSEMHU),
276
+ .instance_init = armsse_mhu_init,
277
+ .class_init = armsse_mhu_class_init,
278
+};
279
+
280
+static void armsse_mhu_register_types(void)
281
+{
282
+ type_register_static(&armsse_mhu_info);
283
+}
284
+
285
+type_init(armsse_mhu_register_types);
10
diff --git a/MAINTAINERS b/MAINTAINERS
286
diff --git a/MAINTAINERS b/MAINTAINERS
11
index XXXXXXX..XXXXXXX 100644
287
index XXXXXXX..XXXXXXX 100644
12
--- a/MAINTAINERS
288
--- a/MAINTAINERS
13
+++ b/MAINTAINERS
289
+++ b/MAINTAINERS
14
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
290
@@ -XXX,XX +XXX,XX @@ F: hw/misc/iotkit-sysinfo.c
15
F: include/hw/timer/cmsdk-apb-timer.h
291
F: include/hw/misc/iotkit-sysinfo.h
16
F: hw/char/cmsdk-apb-uart.c
292
F: hw/misc/armsse-cpuid.c
17
F: include/hw/char/cmsdk-apb-uart.h
293
F: include/hw/misc/armsse-cpuid.h
18
+F: hw/misc/tz-ppc.c
294
+F: hw/misc/armsse-mhu.c
19
+F: include/hw/misc/tz-ppc.h
295
+F: include/hw/misc/armsse-mhu.h
20
296
21
ARM cores
297
Musca
22
M: Peter Maydell <peter.maydell@linaro.org>
298
M: Peter Maydell <peter.maydell@linaro.org>
23
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
299
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
24
L: qemu-arm@nongnu.org
300
index XXXXXXX..XXXXXXX 100644
25
S: Maintained
301
--- a/default-configs/arm-softmmu.mak
26
F: hw/arm/mps2.c
302
+++ b/default-configs/arm-softmmu.mak
27
-F: hw/misc/mps2-scc.c
303
@@ -XXX,XX +XXX,XX @@ CONFIG_IOTKIT_SECCTL=y
28
-F: include/hw/misc/mps2-scc.h
304
CONFIG_IOTKIT_SYSCTL=y
29
+F: hw/arm/mps2-tz.c
305
CONFIG_IOTKIT_SYSINFO=y
30
+F: hw/misc/mps2-*.c
306
CONFIG_ARMSSE_CPUID=y
31
+F: include/hw/misc/mps2-*.h
307
+CONFIG_ARMSSE_MHU=y
32
+F: hw/arm/iotkit.c
308
33
+F: include/hw/arm/iotkit.h
309
CONFIG_VERSATILE=y
34
310
CONFIG_VERSATILE_PCI=y
35
Musicpal
311
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
36
M: Jan Kiszka <jan.kiszka@web.de>
312
index XXXXXXX..XXXXXXX 100644
313
--- a/hw/misc/trace-events
314
+++ b/hw/misc/trace-events
315
@@ -XXX,XX +XXX,XX @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
316
# hw/misc/armsse-cpuid.c
317
armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
318
armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
319
+
320
+# hw/misc/armsse-mhu.c
321
+armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
322
+armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
37
--
323
--
38
2.17.1
324
2.20.1
39
325
40
326
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
[Qemu-devel] [PULL 02/16] hw/arm/armsse: Wire up the MHUs
1
Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
1
Create and connect the MHUs in the SSE-200.
2
and friends.
3
2
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
5
Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
7
---
6
---
8
include/migration/vmstate.h | 3 +++
7
include/hw/arm/armsse.h | 3 ++-
9
1 file changed, 3 insertions(+)
8
hw/arm/armsse.c | 40 ++++++++++++++++++++++++++++++----------
9
2 files changed, 32 insertions(+), 11 deletions(-)
10
10
11
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
11
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/include/migration/vmstate.h
13
--- a/include/hw/arm/armsse.h
14
+++ b/include/migration/vmstate.h
14
+++ b/include/hw/arm/armsse.h
15
@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
15
@@ -XXX,XX +XXX,XX @@
16
#define VMSTATE_BOOL_ARRAY(_f, _s, _n) \
16
#include "hw/misc/iotkit-sysctl.h"
17
VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
17
#include "hw/misc/iotkit-sysinfo.h"
18
18
#include "hw/misc/armsse-cpuid.h"
19
+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num) \
19
+#include "hw/misc/armsse-mhu.h"
20
+ VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
20
#include "hw/misc/unimp.h"
21
#include "hw/or-irq.h"
22
#include "hw/core/split-irq.h"
23
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
24
IoTKitSysCtl sysctl;
25
IoTKitSysCtl sysinfo;
26
27
- UnimplementedDeviceState mhu[2];
28
+ ARMSSEMHU mhu[2];
29
UnimplementedDeviceState ppu[NUM_PPUS];
30
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
31
UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
32
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/armsse.c
35
+++ b/hw/arm/armsse.c
36
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
37
sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
38
if (info->has_mhus) {
39
sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
40
- TYPE_UNIMPLEMENTED_DEVICE);
41
+ TYPE_ARMSSE_MHU);
42
sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
43
- TYPE_UNIMPLEMENTED_DEVICE);
44
+ TYPE_ARMSSE_MHU);
45
}
46
if (info->has_ppus) {
47
for (i = 0; i < info->num_cpus; i++) {
48
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
49
}
50
51
if (info->has_mhus) {
52
- for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
53
- char *name;
54
- char *port;
55
+ /*
56
+ * An SSE-200 with only one CPU should have only one MHU created,
57
+ * with the region where the second MHU usually is being RAZ/WI.
58
+ * We don't implement that SSE-200 config; if we want to support
59
+ * it then this code needs to be enhanced to handle creating the
60
+ * RAZ/WI region instead of the second MHU.
61
+ */
62
+ assert(info->num_cpus == ARRAY_SIZE(s->mhu));
21
+
63
+
22
#define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v) \
64
+ for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
23
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
65
+ char *port;
66
+ int cpunum;
67
+ SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
68
69
- name = g_strdup_printf("MHU%d", i);
70
- qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name);
71
- qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000);
72
object_property_set_bool(OBJECT(&s->mhu[i]), true,
73
"realized", &err);
74
- g_free(name);
75
if (err) {
76
error_propagate(errp, err);
77
return;
78
}
79
port = g_strdup_printf("port[%d]", i + 3);
80
- mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0);
81
+ mr = sysbus_mmio_get_region(mhu_sbd, 0);
82
object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr),
83
port, &err);
84
g_free(port);
85
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
86
error_propagate(errp, err);
87
return;
88
}
89
+
90
+ /*
91
+ * Each MHU has an irq line for each CPU:
92
+ * MHU 0 irq line 0 -> CPU 0 IRQ 6
93
+ * MHU 0 irq line 1 -> CPU 1 IRQ 6
94
+ * MHU 1 irq line 0 -> CPU 0 IRQ 7
95
+ * MHU 1 irq line 1 -> CPU 1 IRQ 7
96
+ */
97
+ for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
98
+ DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
99
+
100
+ sysbus_connect_irq(mhu_sbd, cpunum,
101
+ qdev_get_gpio_in(cpudev, 6 + i));
102
+ }
103
}
104
}
24
105
25
--
106
--
26
2.17.1
107
2.20.1
27
108
28
109
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
[Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
Make the M-profile "init-svtor" property be settable after realize.
2
add MemTxAttrs as an argument to flatview_translate(); all its
2
This matches the hardware, where this is a config signal which
3
callers now have attrs available.
3
is sampled on CPU reset and can thus be changed between one
4
reset and another. To do this we have to change the API we
5
use to add the property.
6
7
(We will need this capability for the SSE-200.)
4
8
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
11
Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
9
---
12
---
10
include/exec/memory.h | 7 ++++---
13
target/arm/cpu.c | 29 ++++++++++++++++++++++++-----
11
exec.c | 17 +++++++++--------
14
1 file changed, 24 insertions(+), 5 deletions(-)
12
2 files changed, 13 insertions(+), 11 deletions(-)
13
15
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
18
--- a/target/arm/cpu.c
17
+++ b/include/exec/memory.h
19
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
20
@@ -XXX,XX +XXX,XX @@
19
*/
21
#include "target/arm/idau.h"
20
MemoryRegion *flatview_translate(FlatView *fv,
22
#include "qemu/error-report.h"
21
hwaddr addr, hwaddr *xlat,
23
#include "qapi/error.h"
22
- hwaddr *len, bool is_write);
24
+#include "qapi/visitor.h"
23
+ hwaddr *len, bool is_write,
25
#include "cpu.h"
24
+ MemTxAttrs attrs);
26
#include "internals.h"
25
27
#include "qemu-common.h"
26
static inline MemoryRegion *address_space_translate(AddressSpace *as,
28
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
27
hwaddr addr, hwaddr *xlat,
29
pmsav7_dregion,
28
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
30
qdev_prop_uint32, uint32_t);
29
MemTxAttrs attrs)
31
32
-/* M profile: initial value of the Secure VTOR */
33
-static Property arm_cpu_initsvtor_property =
34
- DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
35
+static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
36
+ void *opaque, Error **errp)
37
+{
38
+ ARMCPU *cpu = ARM_CPU(obj);
39
+
40
+ visit_type_uint32(v, name, &cpu->init_svtor, errp);
41
+}
42
+
43
+static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
44
+ void *opaque, Error **errp)
45
+{
46
+ ARMCPU *cpu = ARM_CPU(obj);
47
+
48
+ visit_type_uint32(v, name, &cpu->init_svtor, errp);
49
+}
50
51
void arm_cpu_post_init(Object *obj)
30
{
52
{
31
return flatview_translate(address_space_to_flatview(as),
53
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
32
- addr, xlat, len, is_write);
54
qdev_prop_allow_set_link_before_realize,
33
+ addr, xlat, len, is_write, attrs);
55
OBJ_PROP_LINK_STRONG,
34
}
56
&error_abort);
35
57
- qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
36
/* address_space_access_valid: check for validity of accessing an address
58
- &error_abort);
37
@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
59
+ /*
38
rcu_read_lock();
60
+ * M profile: initial value of the Secure VTOR. We can't just use
39
fv = address_space_to_flatview(as);
61
+ * a simple DEFINE_PROP_UINT32 for this because we want to permit
40
l = len;
62
+ * the property to be set after realize.
41
- mr = flatview_translate(fv, addr, &addr1, &l, false);
63
+ */
42
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
64
+ object_property_add(obj, "init-svtor", "uint32",
43
if (len == l && memory_access_is_direct(mr, false)) {
65
+ arm_get_init_svtor, arm_set_init_svtor,
44
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
66
+ NULL, NULL, &error_abort);
45
memcpy(buf, ptr, len);
46
diff --git a/exec.c b/exec.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/exec.c
49
+++ b/exec.c
50
@@ -XXX,XX +XXX,XX @@ iotlb_fail:
51
52
/* Called from RCU critical section */
53
MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
54
- hwaddr *plen, bool is_write)
55
+ hwaddr *plen, bool is_write,
56
+ MemTxAttrs attrs)
57
{
58
MemoryRegion *mr;
59
MemoryRegionSection section;
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
61
}
62
63
l = len;
64
- mr = flatview_translate(fv, addr, &addr1, &l, true);
65
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
66
}
67
}
67
68
68
return result;
69
qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
69
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
70
MemTxResult result = MEMTX_OK;
71
72
l = len;
73
- mr = flatview_translate(fv, addr, &addr1, &l, true);
74
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
75
result = flatview_write_continue(fv, addr, attrs, buf, len,
76
addr1, l, mr);
77
78
@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
79
}
80
81
l = len;
82
- mr = flatview_translate(fv, addr, &addr1, &l, false);
83
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
84
}
85
86
return result;
87
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
88
MemoryRegion *mr;
89
90
l = len;
91
- mr = flatview_translate(fv, addr, &addr1, &l, false);
92
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
93
return flatview_read_continue(fv, addr, attrs, buf, len,
94
addr1, l, mr);
95
}
96
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
97
98
while (len > 0) {
99
l = len;
100
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
101
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
102
if (!memory_access_is_direct(mr, is_write)) {
103
l = memory_access_size(mr, l, addr);
104
if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
105
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
106
107
len = target_len;
108
this_mr = flatview_translate(fv, addr, &xlat,
109
- &len, is_write);
110
+ &len, is_write, attrs);
111
if (this_mr != mr || xlat != base + done) {
112
return done;
113
}
114
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
115
l = len;
116
rcu_read_lock();
117
fv = address_space_to_flatview(as);
118
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
119
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
120
121
if (!memory_access_is_direct(mr, is_write)) {
122
if (atomic_xchg(&bounce.in_use, true)) {
123
--
70
--
124
2.17.1
71
2.20.1
125
72
126
73
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
[Qemu-devel] [PULL 04/16] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
Currently the Arm arm-powerctl.h APIs allow:
2
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
2
* arm_set_cpu_on(), which powers on a CPU and sets its
3
callback. We'll need this for subpage_accepts().
3
initial PC and other startup state
4
* arm_reset_cpu(), which resets a CPU which is already on
5
(and fails if the CPU is powered off)
4
6
5
We could take the approach we used with the read and write
7
but there is no way to say "power on a CPU as if it had
6
callbacks and add new a new _with_attrs version, but since there
8
just come out of reset and don't do anything else to it".
7
are so few implementations of the accepts hook we just change
9
8
them all.
10
Add a new function arm_set_cpu_on_and_reset(), which does this.
9
11
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
14
Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
14
---
15
---
15
include/exec/memory.h | 3 ++-
16
target/arm/arm-powerctl.h | 16 +++++++++++
16
exec.c | 9 ++++++---
17
target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++
17
hw/hppa/dino.c | 3 ++-
18
2 files changed, 72 insertions(+)
18
hw/nvram/fw_cfg.c | 12 ++++++++----
19
hw/scsi/esp.c | 3 ++-
20
hw/xen/xen_pt_msi.c | 3 ++-
21
memory.c | 5 +++--
22
7 files changed, 25 insertions(+), 13 deletions(-)
23
19
24
diff --git a/include/exec/memory.h b/include/exec/memory.h
20
diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h
25
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
26
--- a/include/exec/memory.h
22
--- a/target/arm/arm-powerctl.h
27
+++ b/include/exec/memory.h
23
+++ b/target/arm/arm-powerctl.h
28
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
24
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_off(uint64_t cpuid);
29
* as a machine check exception).
25
*/
30
*/
26
int arm_reset_cpu(uint64_t cpuid);
31
bool (*accepts)(void *opaque, hwaddr addr,
27
32
- unsigned size, bool is_write);
28
+/*
33
+ unsigned size, bool is_write,
29
+ * arm_set_cpu_on_and_reset:
34
+ MemTxAttrs attrs);
30
+ * @cpuid: the id of the CPU we want to star
35
} valid;
31
+ *
36
/* Internal implementation constraints: */
32
+ * Start the cpu designated by @cpuid and put it through its normal
37
struct {
33
+ * CPU reset process. The CPU will start in the way it is architected
38
diff --git a/exec.c b/exec.c
34
+ * to start after a power-on reset.
35
+ *
36
+ * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success.
37
+ * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID.
38
+ * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on.
39
+ * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through
40
+ * powering on.
41
+ */
42
+int arm_set_cpu_on_and_reset(uint64_t cpuid);
43
+
44
#endif
45
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
39
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
40
--- a/exec.c
47
--- a/target/arm/arm-powerctl.c
41
+++ b/exec.c
48
+++ b/target/arm/arm-powerctl.c
42
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
49
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
50
return QEMU_ARM_POWERCTL_RET_SUCCESS;
43
}
51
}
44
52
45
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
53
+static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,
46
- unsigned size, bool is_write)
54
+ run_on_cpu_data data)
47
+ unsigned size, bool is_write,
55
+{
48
+ MemTxAttrs attrs)
56
+ ARMCPU *target_cpu = ARM_CPU(target_cpu_state);
57
+
58
+ /* Initialize the cpu we are turning on */
59
+ cpu_reset(target_cpu_state);
60
+ target_cpu_state->halted = 0;
61
+
62
+ /* Finally set the power status */
63
+ assert(qemu_mutex_iothread_locked());
64
+ target_cpu->power_state = PSCI_ON;
65
+}
66
+
67
+int arm_set_cpu_on_and_reset(uint64_t cpuid)
68
+{
69
+ CPUState *target_cpu_state;
70
+ ARMCPU *target_cpu;
71
+
72
+ assert(qemu_mutex_iothread_locked());
73
+
74
+ /* Retrieve the cpu we are powering up */
75
+ target_cpu_state = arm_get_cpu_by_id(cpuid);
76
+ if (!target_cpu_state) {
77
+ /* The cpu was not found */
78
+ return QEMU_ARM_POWERCTL_INVALID_PARAM;
79
+ }
80
+
81
+ target_cpu = ARM_CPU(target_cpu_state);
82
+ if (target_cpu->power_state == PSCI_ON) {
83
+ qemu_log_mask(LOG_GUEST_ERROR,
84
+ "[ARM]%s: CPU %" PRId64 " is already on\n",
85
+ __func__, cpuid);
86
+ return QEMU_ARM_POWERCTL_ALREADY_ON;
87
+ }
88
+
89
+ /*
90
+ * If another CPU has powered the target on we are in the state
91
+ * ON_PENDING and additional attempts to power on the CPU should
92
+ * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI
93
+ * spec)
94
+ */
95
+ if (target_cpu->power_state == PSCI_ON_PENDING) {
96
+ qemu_log_mask(LOG_GUEST_ERROR,
97
+ "[ARM]%s: CPU %" PRId64 " is already powering on\n",
98
+ __func__, cpuid);
99
+ return QEMU_ARM_POWERCTL_ON_PENDING;
100
+ }
101
+
102
+ async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work,
103
+ RUN_ON_CPU_NULL);
104
+
105
+ /* We are good to go */
106
+ return QEMU_ARM_POWERCTL_RET_SUCCESS;
107
+}
108
+
109
static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,
110
run_on_cpu_data data)
49
{
111
{
50
return is_write;
51
}
52
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
53
}
54
55
static bool subpage_accepts(void *opaque, hwaddr addr,
56
- unsigned len, bool is_write)
57
+ unsigned len, bool is_write,
58
+ MemTxAttrs attrs)
59
{
60
subpage_t *subpage = opaque;
61
#if defined(DEBUG_SUBPAGE)
62
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
63
}
64
65
static bool readonly_mem_accepts(void *opaque, hwaddr addr,
66
- unsigned size, bool is_write)
67
+ unsigned size, bool is_write,
68
+ MemTxAttrs attrs)
69
{
70
return is_write;
71
}
72
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/hw/hppa/dino.c
75
+++ b/hw/hppa/dino.c
76
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
77
}
78
79
static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
80
- unsigned size, bool is_write)
81
+ unsigned size, bool is_write,
82
+ MemTxAttrs attrs)
83
{
84
switch (addr) {
85
case DINO_IAR0:
86
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/nvram/fw_cfg.c
89
+++ b/hw/nvram/fw_cfg.c
90
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
91
}
92
93
static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
94
- unsigned size, bool is_write)
95
+ unsigned size, bool is_write,
96
+ MemTxAttrs attrs)
97
{
98
return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
99
(size == 8 && addr == 0));
100
}
101
102
static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
103
- unsigned size, bool is_write)
104
+ unsigned size, bool is_write,
105
+ MemTxAttrs attrs)
106
{
107
return addr == 0;
108
}
109
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
110
}
111
112
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
113
- unsigned size, bool is_write)
114
+ unsigned size, bool is_write,
115
+ MemTxAttrs attrs)
116
{
117
return is_write && size == 2;
118
}
119
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
120
}
121
122
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
123
- unsigned size, bool is_write)
124
+ unsigned size, bool is_write,
125
+ MemTxAttrs attrs)
126
{
127
return (size == 1) || (is_write && size == 2);
128
}
129
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
130
index XXXXXXX..XXXXXXX 100644
131
--- a/hw/scsi/esp.c
132
+++ b/hw/scsi/esp.c
133
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
134
}
135
136
static bool esp_mem_accepts(void *opaque, hwaddr addr,
137
- unsigned size, bool is_write)
138
+ unsigned size, bool is_write,
139
+ MemTxAttrs attrs)
140
{
141
return (size == 1) || (is_write && size == 4);
142
}
143
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/hw/xen/xen_pt_msi.c
146
+++ b/hw/xen/xen_pt_msi.c
147
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
148
}
149
150
static bool pci_msix_accepts(void *opaque, hwaddr addr,
151
- unsigned size, bool is_write)
152
+ unsigned size, bool is_write,
153
+ MemTxAttrs attrs)
154
{
155
return !(addr & (size - 1));
156
}
157
diff --git a/memory.c b/memory.c
158
index XXXXXXX..XXXXXXX 100644
159
--- a/memory.c
160
+++ b/memory.c
161
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
162
}
163
164
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
165
- unsigned size, bool is_write)
166
+ unsigned size, bool is_write,
167
+ MemTxAttrs attrs)
168
{
169
return false;
170
}
171
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
172
access_size = MAX(MIN(size, access_size_max), access_size_min);
173
for (i = 0; i < size; i += access_size) {
174
if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
175
- is_write)) {
176
+ is_write, attrs)) {
177
return false;
178
}
179
}
180
--
112
--
181
2.17.1
113
2.20.1
182
114
183
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
[Qemu-devel] [PULL 05/16] hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
The iotkit-sysctl device has a register it names INITSVRTOR0.
2
add MemTxAttrs as an argument to address_space_translate_iommu().
2
This is actually a typo present in the IoTKit documentation
3
and also in part of the SSE-200 documentation: it should be
4
INITSVTOR0 because it is specifying the initial value of the
5
Secure VTOR register in the CPU. Correct the typo.
3
6
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
9
Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
8
---
10
---
9
exec.c | 8 +++++---
11
include/hw/misc/iotkit-sysctl.h | 2 +-
10
1 file changed, 5 insertions(+), 3 deletions(-)
12
hw/misc/iotkit-sysctl.c | 16 ++++++++--------
13
2 files changed, 9 insertions(+), 9 deletions(-)
11
14
12
diff --git a/exec.c b/exec.c
15
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
13
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
14
--- a/exec.c
17
--- a/include/hw/misc/iotkit-sysctl.h
15
+++ b/exec.c
18
+++ b/include/hw/misc/iotkit-sysctl.h
16
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
19
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
17
* @is_write: whether the translation operation is for write
20
uint32_t reset_syndrome;
18
* @is_mmio: whether this can be MMIO, set true if it can
21
uint32_t reset_mask;
19
* @target_as: the address space targeted by the IOMMU
22
uint32_t gretreg;
20
+ * @attrs: transaction attributes
23
- uint32_t initsvrtor0;
21
*
24
+ uint32_t initsvtor0;
22
* This function is called from RCU critical section. It is the common
25
uint32_t cpuwait;
23
* part of flatview_do_translate and address_space_translate_cached.
26
uint32_t wicctrl;
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
27
} IoTKitSysCtl;
25
hwaddr *page_mask_out,
28
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
26
bool is_write,
29
index XXXXXXX..XXXXXXX 100644
27
bool is_mmio,
30
--- a/hw/misc/iotkit-sysctl.c
28
- AddressSpace **target_as)
31
+++ b/hw/misc/iotkit-sysctl.c
29
+ AddressSpace **target_as,
32
@@ -XXX,XX +XXX,XX @@ REG32(RESET_MASK, 0x104)
30
+ MemTxAttrs attrs)
33
REG32(SWRESET, 0x108)
31
{
34
FIELD(SWRESET, SWRESETREQ, 9, 1)
32
MemoryRegionSection *section;
35
REG32(GRETREG, 0x10c)
33
hwaddr page_mask = (hwaddr)-1;
36
-REG32(INITSVRTOR0, 0x110)
34
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
37
+REG32(INITSVTOR0, 0x110)
35
return address_space_translate_iommu(iommu_mr, xlat,
38
REG32(CPUWAIT, 0x118)
36
plen_out, page_mask_out,
39
REG32(BUSWAIT, 0x11c)
37
is_write, is_mmio,
40
REG32(WICCTRL, 0x120)
38
- target_as);
41
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
39
+ target_as, attrs);
42
case A_GRETREG:
40
}
43
r = s->gretreg;
41
if (page_mask_out) {
44
break;
42
/* Not behind an IOMMU, use default page size. */
45
- case A_INITSVRTOR0:
43
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
46
- r = s->initsvrtor0;
44
47
+ case A_INITSVTOR0:
45
section = address_space_translate_iommu(iommu_mr, xlat, plen,
48
+ r = s->initsvtor0;
46
NULL, is_write, true,
49
break;
47
- &target_as);
50
case A_CPUWAIT:
48
+ &target_as, attrs);
51
r = s->cpuwait;
49
return section.mr;
52
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
53
*/
54
s->gretreg = value;
55
break;
56
- case A_INITSVRTOR0:
57
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
58
- s->initsvrtor0 = value;
59
+ case A_INITSVTOR0:
60
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
61
+ s->initsvtor0 = value;
62
break;
63
case A_CPUWAIT:
64
qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
65
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
66
s->reset_syndrome = 1;
67
s->reset_mask = 0;
68
s->gretreg = 0;
69
- s->initsvrtor0 = 0x10000000;
70
+ s->initsvtor0 = 0x10000000;
71
s->cpuwait = 0;
72
s->wicctrl = 0;
50
}
73
}
51
74
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
75
VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
76
VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
77
VMSTATE_UINT32(gretreg, IoTKitSysCtl),
78
- VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
79
+ VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
80
VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
81
VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
82
VMSTATE_END_OF_LIST()
52
--
83
--
53
2.17.1
84
2.20.1
54
85
55
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
[Qemu-devel] [PULL 06/16] hw/arm/iotkit-sysctl: Add SSE-200 registers
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
The SYSCTL block in the SSE-200 has some extra registers that
2
add MemTxAttrs as an argument to flatview_access_valid().
2
are not present in the IoTKit version. Add these registers
3
Its callers now all have an attrs value to hand, so we can
3
(as reads-as-written stubs), enabled by a new QOM property.
4
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
5
4
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
7
Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
10
---
8
---
11
exec.c | 12 +++++-------
9
include/hw/misc/iotkit-sysctl.h | 20 +++
12
1 file changed, 5 insertions(+), 7 deletions(-)
10
hw/arm/armsse.c | 2 +
11
hw/misc/iotkit-sysctl.c | 245 +++++++++++++++++++++++++++++++-
12
3 files changed, 262 insertions(+), 5 deletions(-)
13
13
14
diff --git a/exec.c b/exec.c
14
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
16
--- a/include/hw/misc/iotkit-sysctl.h
17
+++ b/exec.c
17
+++ b/include/hw/misc/iotkit-sysctl.h
18
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
18
@@ -XXX,XX +XXX,XX @@
19
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
19
* "system control register" blocks.
20
const uint8_t *buf, int len);
20
*
21
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
21
* QEMU interface:
22
- bool is_write);
22
+ * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
23
+ bool is_write, MemTxAttrs attrs);
23
+ * system information block of the SSE
24
24
+ * (used to identify whether to provide SSE-200-only registers)
25
static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
25
* + sysbus MMIO region 0: the system information register bank
26
unsigned len, MemTxAttrs attrs)
26
* + sysbus MMIO region 1: the system control register bank
27
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
27
*/
28
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
29
uint32_t initsvtor0;
30
uint32_t cpuwait;
31
uint32_t wicctrl;
32
+ uint32_t scsecctrl;
33
+ uint32_t fclk_div;
34
+ uint32_t sysclk_div;
35
+ uint32_t clock_force;
36
+ uint32_t initsvtor1;
37
+ uint32_t nmi_enable;
38
+ uint32_t ewctrl;
39
+ uint32_t pdcm_pd_sys_sense;
40
+ uint32_t pdcm_pd_sram0_sense;
41
+ uint32_t pdcm_pd_sram1_sense;
42
+ uint32_t pdcm_pd_sram2_sense;
43
+ uint32_t pdcm_pd_sram3_sense;
44
+
45
+ /* Properties */
46
+ uint32_t sys_version;
47
+
48
+ bool is_sse200;
49
} IoTKitSysCtl;
50
28
#endif
51
#endif
29
52
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
30
return flatview_access_valid(subpage->fv, addr + subpage->base,
53
index XXXXXXX..XXXXXXX 100644
31
- len, is_write);
54
--- a/hw/arm/armsse.c
32
+ len, is_write, attrs);
55
+++ b/hw/arm/armsse.c
56
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
57
/* System information registers */
58
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
59
/* System control registers */
60
+ object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
61
+ "SYS_VERSION", &err);
62
object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
63
if (err) {
64
error_propagate(errp, err);
65
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/misc/iotkit-sysctl.c
68
+++ b/hw/misc/iotkit-sysctl.c
69
@@ -XXX,XX +XXX,XX @@
70
*/
71
72
#include "qemu/osdep.h"
73
+#include "qemu/bitops.h"
74
#include "qemu/log.h"
75
#include "trace.h"
76
#include "qapi/error.h"
77
@@ -XXX,XX +XXX,XX @@
78
REG32(SECDBGSTAT, 0x0)
79
REG32(SECDBGSET, 0x4)
80
REG32(SECDBGCLR, 0x8)
81
+REG32(SCSECCTRL, 0xc)
82
+REG32(FCLK_DIV, 0x10)
83
+REG32(SYSCLK_DIV, 0x14)
84
+REG32(CLOCK_FORCE, 0x18)
85
REG32(RESET_SYNDROME, 0x100)
86
REG32(RESET_MASK, 0x104)
87
REG32(SWRESET, 0x108)
88
FIELD(SWRESET, SWRESETREQ, 9, 1)
89
REG32(GRETREG, 0x10c)
90
REG32(INITSVTOR0, 0x110)
91
+REG32(INITSVTOR1, 0x114)
92
REG32(CPUWAIT, 0x118)
93
-REG32(BUSWAIT, 0x11c)
94
+REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
95
REG32(WICCTRL, 0x120)
96
+REG32(EWCTRL, 0x124)
97
+REG32(PDCM_PD_SYS_SENSE, 0x200)
98
+REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
99
+REG32(PDCM_PD_SRAM1_SENSE, 0x210)
100
+REG32(PDCM_PD_SRAM2_SENSE, 0x214)
101
+REG32(PDCM_PD_SRAM3_SENSE, 0x218)
102
REG32(PID4, 0xfd0)
103
REG32(PID5, 0xfd4)
104
REG32(PID6, 0xfd8)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
106
case A_SECDBGSTAT:
107
r = s->secure_debug;
108
break;
109
+ case A_SCSECCTRL:
110
+ if (!s->is_sse200) {
111
+ goto bad_offset;
112
+ }
113
+ r = s->scsecctrl;
114
+ break;
115
+ case A_FCLK_DIV:
116
+ if (!s->is_sse200) {
117
+ goto bad_offset;
118
+ }
119
+ r = s->fclk_div;
120
+ break;
121
+ case A_SYSCLK_DIV:
122
+ if (!s->is_sse200) {
123
+ goto bad_offset;
124
+ }
125
+ r = s->sysclk_div;
126
+ break;
127
+ case A_CLOCK_FORCE:
128
+ if (!s->is_sse200) {
129
+ goto bad_offset;
130
+ }
131
+ r = s->clock_force;
132
+ break;
133
case A_RESET_SYNDROME:
134
r = s->reset_syndrome;
135
break;
136
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
137
case A_INITSVTOR0:
138
r = s->initsvtor0;
139
break;
140
+ case A_INITSVTOR1:
141
+ if (!s->is_sse200) {
142
+ goto bad_offset;
143
+ }
144
+ r = s->initsvtor1;
145
+ break;
146
case A_CPUWAIT:
147
r = s->cpuwait;
148
break;
149
- case A_BUSWAIT:
150
- /* In IoTKit BUSWAIT is reserved, R/O, zero */
151
- r = 0;
152
+ case A_NMI_ENABLE:
153
+ /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
154
+ if (!s->is_sse200) {
155
+ r = 0;
156
+ break;
157
+ }
158
+ r = s->nmi_enable;
159
break;
160
case A_WICCTRL:
161
r = s->wicctrl;
162
break;
163
+ case A_EWCTRL:
164
+ if (!s->is_sse200) {
165
+ goto bad_offset;
166
+ }
167
+ r = s->ewctrl;
168
+ break;
169
+ case A_PDCM_PD_SYS_SENSE:
170
+ if (!s->is_sse200) {
171
+ goto bad_offset;
172
+ }
173
+ r = s->pdcm_pd_sys_sense;
174
+ break;
175
+ case A_PDCM_PD_SRAM0_SENSE:
176
+ if (!s->is_sse200) {
177
+ goto bad_offset;
178
+ }
179
+ r = s->pdcm_pd_sram0_sense;
180
+ break;
181
+ case A_PDCM_PD_SRAM1_SENSE:
182
+ if (!s->is_sse200) {
183
+ goto bad_offset;
184
+ }
185
+ r = s->pdcm_pd_sram1_sense;
186
+ break;
187
+ case A_PDCM_PD_SRAM2_SENSE:
188
+ if (!s->is_sse200) {
189
+ goto bad_offset;
190
+ }
191
+ r = s->pdcm_pd_sram2_sense;
192
+ break;
193
+ case A_PDCM_PD_SRAM3_SENSE:
194
+ if (!s->is_sse200) {
195
+ goto bad_offset;
196
+ }
197
+ r = s->pdcm_pd_sram3_sense;
198
+ break;
199
case A_PID4 ... A_CID3:
200
r = sysctl_id[(offset - A_PID4) / 4];
201
break;
202
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
203
r = 0;
204
break;
205
default:
206
+ bad_offset:
207
qemu_log_mask(LOG_GUEST_ERROR,
208
"IoTKit SysCtl read: bad offset %x\n", (int)offset);
209
r = 0;
210
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
211
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
212
}
213
break;
214
- case A_BUSWAIT: /* In IoTKit BUSWAIT is reserved, R/O, zero */
215
+ case A_SCSECCTRL:
216
+ if (!s->is_sse200) {
217
+ goto bad_offset;
218
+ }
219
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
220
+ s->scsecctrl = value;
221
+ break;
222
+ case A_FCLK_DIV:
223
+ if (!s->is_sse200) {
224
+ goto bad_offset;
225
+ }
226
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
227
+ s->fclk_div = value;
228
+ break;
229
+ case A_SYSCLK_DIV:
230
+ if (!s->is_sse200) {
231
+ goto bad_offset;
232
+ }
233
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
234
+ s->sysclk_div = value;
235
+ break;
236
+ case A_CLOCK_FORCE:
237
+ if (!s->is_sse200) {
238
+ goto bad_offset;
239
+ }
240
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
241
+ s->clock_force = value;
242
+ break;
243
+ case A_INITSVTOR1:
244
+ if (!s->is_sse200) {
245
+ goto bad_offset;
246
+ }
247
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
248
+ s->initsvtor1 = value;
249
+ break;
250
+ case A_EWCTRL:
251
+ if (!s->is_sse200) {
252
+ goto bad_offset;
253
+ }
254
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
255
+ s->ewctrl = value;
256
+ break;
257
+ case A_PDCM_PD_SYS_SENSE:
258
+ if (!s->is_sse200) {
259
+ goto bad_offset;
260
+ }
261
+ qemu_log_mask(LOG_UNIMP,
262
+ "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
263
+ s->pdcm_pd_sys_sense = value;
264
+ break;
265
+ case A_PDCM_PD_SRAM0_SENSE:
266
+ if (!s->is_sse200) {
267
+ goto bad_offset;
268
+ }
269
+ qemu_log_mask(LOG_UNIMP,
270
+ "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
271
+ s->pdcm_pd_sram0_sense = value;
272
+ break;
273
+ case A_PDCM_PD_SRAM1_SENSE:
274
+ if (!s->is_sse200) {
275
+ goto bad_offset;
276
+ }
277
+ qemu_log_mask(LOG_UNIMP,
278
+ "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
279
+ s->pdcm_pd_sram1_sense = value;
280
+ break;
281
+ case A_PDCM_PD_SRAM2_SENSE:
282
+ if (!s->is_sse200) {
283
+ goto bad_offset;
284
+ }
285
+ qemu_log_mask(LOG_UNIMP,
286
+ "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
287
+ s->pdcm_pd_sram2_sense = value;
288
+ break;
289
+ case A_PDCM_PD_SRAM3_SENSE:
290
+ if (!s->is_sse200) {
291
+ goto bad_offset;
292
+ }
293
+ qemu_log_mask(LOG_UNIMP,
294
+ "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
295
+ s->pdcm_pd_sram3_sense = value;
296
+ break;
297
+ case A_NMI_ENABLE:
298
+ /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
299
+ if (!s->is_sse200) {
300
+ goto ro_offset;
301
+ }
302
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
303
+ s->nmi_enable = value;
304
+ break;
305
case A_SECDBGSTAT:
306
case A_PID4 ... A_CID3:
307
+ ro_offset:
308
qemu_log_mask(LOG_GUEST_ERROR,
309
"IoTKit SysCtl write: write of RO offset %x\n",
310
(int)offset);
311
break;
312
default:
313
+ bad_offset:
314
qemu_log_mask(LOG_GUEST_ERROR,
315
"IoTKit SysCtl write: bad offset %x\n", (int)offset);
316
break;
317
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
318
s->reset_mask = 0;
319
s->gretreg = 0;
320
s->initsvtor0 = 0x10000000;
321
+ s->initsvtor1 = 0x10000000;
322
s->cpuwait = 0;
323
s->wicctrl = 0;
324
+ s->scsecctrl = 0;
325
+ s->fclk_div = 0;
326
+ s->sysclk_div = 0;
327
+ s->clock_force = 0;
328
+ s->nmi_enable = 0;
329
+ s->ewctrl = 0;
330
+ s->pdcm_pd_sys_sense = 0x7f;
331
+ s->pdcm_pd_sram0_sense = 0;
332
+ s->pdcm_pd_sram1_sense = 0;
333
+ s->pdcm_pd_sram2_sense = 0;
334
+ s->pdcm_pd_sram3_sense = 0;
33
}
335
}
34
336
35
static const MemoryRegionOps subpage_ops = {
337
static void iotkit_sysctl_init(Object *obj)
36
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
338
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_init(Object *obj)
339
sysbus_init_mmio(sbd, &s->iomem);
37
}
340
}
38
341
39
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
342
+static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
40
- bool is_write)
343
+{
41
+ bool is_write, MemTxAttrs attrs)
344
+ IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
345
+
346
+ /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
347
+ if (extract32(s->sys_version, 28, 4) == 2) {
348
+ s->is_sse200 = true;
349
+ }
350
+}
351
+
352
+static bool sse200_needed(void *opaque)
353
+{
354
+ IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
355
+
356
+ return s->is_sse200;
357
+}
358
+
359
+static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
360
+ .name = "iotkit-sysctl/sse-200",
361
+ .version_id = 1,
362
+ .minimum_version_id = 1,
363
+ .needed = sse200_needed,
364
+ .fields = (VMStateField[]) {
365
+ VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
366
+ VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
367
+ VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
368
+ VMSTATE_UINT32(clock_force, IoTKitSysCtl),
369
+ VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
370
+ VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
371
+ VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
372
+ VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
373
+ VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
374
+ VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
375
+ VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
376
+ VMSTATE_END_OF_LIST()
377
+ }
378
+};
379
+
380
static const VMStateDescription iotkit_sysctl_vmstate = {
381
.name = "iotkit-sysctl",
382
.version_id = 1,
383
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
384
VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
385
VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
386
VMSTATE_END_OF_LIST()
387
+ },
388
+ .subsections = (const VMStateDescription*[]) {
389
+ &iotkit_sysctl_sse200_vmstate,
390
+ NULL
391
}
392
};
393
394
+static Property iotkit_sysctl_props[] = {
395
+ DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
396
+ DEFINE_PROP_END_OF_LIST()
397
+};
398
+
399
static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
42
{
400
{
43
MemoryRegion *mr;
401
DeviceClass *dc = DEVICE_CLASS(klass);
44
hwaddr l, xlat;
402
45
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
403
dc->vmsd = &iotkit_sysctl_vmstate;
46
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
404
dc->reset = iotkit_sysctl_reset;
47
if (!memory_access_is_direct(mr, is_write)) {
405
+ dc->props = iotkit_sysctl_props;
48
l = memory_access_size(mr, l, addr);
406
+ dc->realize = iotkit_sysctl_realize;
49
- /* When our callers all have attrs we'll pass them through here */
50
- if (!memory_region_access_valid(mr, xlat, l, is_write,
51
- MEMTXATTRS_UNSPECIFIED)) {
52
+ if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
53
return false;
54
}
55
}
56
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
57
58
rcu_read_lock();
59
fv = address_space_to_flatview(as);
60
- result = flatview_access_valid(fv, addr, len, is_write);
61
+ result = flatview_access_valid(fv, addr, len, is_write, attrs);
62
rcu_read_unlock();
63
return result;
64
}
407
}
408
409
static const TypeInfo iotkit_sysctl_info = {
65
--
410
--
66
2.17.1
411
2.20.1
67
412
68
413
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
[Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
1
Add more detail to the documentation for memory_region_init_iommu()
1
The CPUWAIT register acts as a sort of power-control: if a bit
2
and other IOMMU-related functions and data structures.
2
in it is 1 then the CPU will have been forced into waiting
3
when the system was reset (which in QEMU we model as the
4
CPU starting powered off). Writing a 0 to the register will
5
allow the CPU to boot (for QEMU, we model this as powering
6
it on). Note that writing 0 to the register does not power
7
off a CPU.
8
9
For this to work correctly we need to also honour the
10
INITSVTOR* registers, which let the guest control where the
11
CPU will load its SP and PC from when it comes out of reset.
3
12
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
9
---
16
---
10
include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
17
hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++----
11
1 file changed, 95 insertions(+), 10 deletions(-)
18
1 file changed, 37 insertions(+), 4 deletions(-)
12
19
13
diff --git a/include/exec/memory.h b/include/exec/memory.h
20
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/memory.h
22
--- a/hw/misc/iotkit-sysctl.c
16
+++ b/include/exec/memory.h
23
+++ b/hw/misc/iotkit-sysctl.c
17
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
24
@@ -XXX,XX +XXX,XX @@
18
IOMMU_ATTR_SPAPR_TCE_FD
25
#include "hw/sysbus.h"
26
#include "hw/registerfields.h"
27
#include "hw/misc/iotkit-sysctl.h"
28
+#include "target/arm/arm-powerctl.h"
29
+#include "target/arm/cpu.h"
30
31
REG32(SECDBGSTAT, 0x0)
32
REG32(SECDBGSET, 0x4)
33
@@ -XXX,XX +XXX,XX @@ static const int sysctl_id[] = {
34
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
19
};
35
};
20
36
21
+/**
37
+/*
22
+ * IOMMUMemoryRegionClass:
38
+ * Set the initial secure vector table offset address for the core.
23
+ *
39
+ * This will take effect when the CPU next resets.
24
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
25
+ * and provide an implementation of at least the @translate method here
26
+ * to handle requests to the memory region. Other methods are optional.
27
+ *
28
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
29
+ * to report whenever mappings are changed, by calling
30
+ * memory_region_notify_iommu() (or, if necessary, by calling
31
+ * memory_region_notify_one() for each registered notifier).
32
+ */
40
+ */
33
typedef struct IOMMUMemoryRegionClass {
41
+static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
34
/* private */
42
+{
35
struct DeviceClass parent_class;
43
+ Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
36
44
+
37
/*
45
+ if (cpuobj) {
38
- * Return a TLB entry that contains a given address. Flag should
46
+ if (object_property_find(cpuobj, "init-svtor", NULL)) {
39
- * be the access permission of this translation operation. We can
47
+ object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
40
- * set flag to IOMMU_NONE to mean that we don't need any
48
+ }
41
- * read/write permission checks, like, when for region replay.
49
+ }
42
+ * Return a TLB entry that contains a given address.
50
+}
43
+ *
51
+
44
+ * The IOMMUAccessFlags indicated via @flag are optional and may
52
static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
45
+ * be specified as IOMMU_NONE to indicate that the caller needs
53
unsigned size)
46
+ * the full translation information for both reads and writes. If
54
{
47
+ * the access flags are specified then the IOMMU implementation
55
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
48
+ * may use this as an optimization, to stop doing a page table
56
s->gretreg = value;
49
+ * walk as soon as it knows that the requested permissions are not
57
break;
50
+ * allowed. If IOMMU_NONE is passed then the IOMMU must do the
58
case A_INITSVTOR0:
51
+ * full page table walk and report the permissions in the returned
59
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
52
+ * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
60
s->initsvtor0 = value;
53
+ * return different mappings for reads and writes.)
61
+ set_init_vtor(0, s->initsvtor0);
54
+ *
62
break;
55
+ * The returned information remains valid while the caller is
63
case A_CPUWAIT:
56
+ * holding the big QEMU lock or is inside an RCU critical section;
64
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
57
+ * if the caller wishes to cache the mapping beyond that it must
65
+ if ((s->cpuwait & 1) && !(value & 1)) {
58
+ * register an IOMMU notifier so it can invalidate its cached
66
+ /* Powering up CPU 0 */
59
+ * information when the IOMMU mapping changes.
67
+ arm_set_cpu_on_and_reset(0);
60
+ *
68
+ }
61
+ * @iommu: the IOMMUMemoryRegion
69
+ if ((s->cpuwait & 2) && !(value & 2)) {
62
+ * @hwaddr: address to be translated within the memory region
70
+ /* Powering up CPU 1 */
63
+ * @flag: requested access permissions
71
+ arm_set_cpu_on_and_reset(1);
64
*/
72
+ }
65
IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
73
s->cpuwait = value;
66
IOMMUAccessFlags flag);
74
break;
67
- /* Returns minimum supported page size */
75
case A_WICCTRL:
68
+ /* Returns minimum supported page size in bytes.
76
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
69
+ * If this method is not provided then the minimum is assumed to
77
if (!s->is_sse200) {
70
+ * be TARGET_PAGE_SIZE.
78
goto bad_offset;
71
+ *
79
}
72
+ * @iommu: the IOMMUMemoryRegion
80
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
73
+ */
81
s->initsvtor1 = value;
74
uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
82
+ set_init_vtor(1, s->initsvtor1);
75
- /* Called when IOMMU Notifier flag changed */
83
break;
76
+ /* Called when IOMMU Notifier flag changes (ie when the set of
84
case A_EWCTRL:
77
+ * events which IOMMU users are requesting notification for changes).
85
if (!s->is_sse200) {
78
+ * Optional method -- need not be provided if the IOMMU does not
86
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
79
+ * need to know exactly which events must be notified.
87
s->gretreg = 0;
80
+ *
88
s->initsvtor0 = 0x10000000;
81
+ * @iommu: the IOMMUMemoryRegion
89
s->initsvtor1 = 0x10000000;
82
+ * @old_flags: events which previously needed to be notified
90
- s->cpuwait = 0;
83
+ * @new_flags: events which now need to be notified
91
+ if (s->is_sse200) {
84
+ */
92
+ /*
85
void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
93
+ * CPU 0 starts on, CPU 1 starts off. In real hardware this is
86
IOMMUNotifierFlag old_flags,
94
+ * configurable by the SoC integrator as a verilog parameter.
87
IOMMUNotifierFlag new_flags);
95
+ */
88
- /* Set this up to provide customized IOMMU replay function */
96
+ s->cpuwait = 2;
89
+ /* Called to handle memory_region_iommu_replay().
97
+ } else {
90
+ *
98
+ /* CPU 0 starts on */
91
+ * The default implementation of memory_region_iommu_replay() is to
99
+ s->cpuwait = 0;
92
+ * call the IOMMU translate method for every page in the address space
100
+ }
93
+ * with flag == IOMMU_NONE and then call the notifier if translate
101
s->wicctrl = 0;
94
+ * returns a valid mapping. If this method is implemented then it
102
s->scsecctrl = 0;
95
+ * overrides the default behaviour, and must provide the full semantics
103
s->fclk_div = 0;
96
+ * of memory_region_iommu_replay(), by calling @notifier for every
97
+ * translation present in the IOMMU.
98
+ *
99
+ * Optional method -- an IOMMU only needs to provide this method
100
+ * if the default is inefficient or produces undesirable side effects.
101
+ *
102
+ * Note: this is not related to record-and-replay functionality.
103
+ */
104
void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
105
106
- /* Get IOMMU misc attributes */
107
- int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
108
+ /* Get IOMMU misc attributes. This is an optional method that
109
+ * can be used to allow users of the IOMMU to get implementation-specific
110
+ * information. The IOMMU implements this method to handle calls
111
+ * by IOMMU users to memory_region_iommu_get_attr() by filling in
112
+ * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
113
+ * the IOMMU supports. If the method is unimplemented then
114
+ * memory_region_iommu_get_attr() will always return -EINVAL.
115
+ *
116
+ * @iommu: the IOMMUMemoryRegion
117
+ * @attr: attribute being queried
118
+ * @data: memory to fill in with the attribute data
119
+ *
120
+ * Returns 0 on success, or a negative errno; in particular
121
+ * returns -EINVAL for unrecognized or unimplemented attribute types.
122
+ */
123
+ int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
124
void *data);
125
} IOMMUMemoryRegionClass;
126
127
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
128
* An IOMMU region translates addresses and forwards accesses to a target
129
* memory region.
130
*
131
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
132
+ * @_iommu_mr should be a pointer to enough memory for an instance of
133
+ * that subclass, @instance_size is the size of that subclass, and
134
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
135
+ * instance of the subclass, and its methods will then be called to handle
136
+ * accesses to the memory region. See the documentation of
137
+ * #IOMMUMemoryRegionClass for further details.
138
+ *
139
* @_iommu_mr: the #IOMMUMemoryRegion to be initialized
140
* @instance_size: the IOMMUMemoryRegion subclass instance size
141
* @mrtypename: the type name of the #IOMMUMemoryRegion
142
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
143
* a notifier with the minimum page granularity returned by
144
* mr->iommu_ops->get_page_size().
145
*
146
+ * Note: this is not related to record-and-replay functionality.
147
+ *
148
* @iommu_mr: the memory region to observe
149
* @n: the notifier to which to replay iommu mappings
150
*/
151
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
152
* memory_region_iommu_replay_all: replay existing IOMMU translations
153
* to all the notifiers registered.
154
*
155
+ * Note: this is not related to record-and-replay functionality.
156
+ *
157
* @iommu_mr: the memory region to observe
158
*/
159
void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
160
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
161
* memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
162
* defined on the IOMMU.
163
*
164
- * Returns 0 if succeded, error code otherwise.
165
+ * Returns 0 on success, or a negative errno otherwise. In particular,
166
+ * -EINVAL indicates that the IOMMU does not support the requested
167
+ * attribute.
168
*
169
* @iommu_mr: the memory region
170
* @attr: the requested attribute
171
--
104
--
172
2.17.1
105
2.20.1
173
106
174
107
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
[Qemu-devel] [PULL 08/16] hw/arm/armsse: Unify init-svtor and cpuwait handling
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
1
At the moment the handling of init-svtor and cpuwait initial
2
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
2
values is split between armsse.c and iotkit-sysctl.c:
3
Its callers either have an attrs value to hand, or don't care
3
the code in armsse.c sets the initial state of the CPU
4
and can use MEMTXATTRS_UNSPECIFIED.
4
object by setting the init-svtor and start-powered-off
5
properties, but the iotkit-sysctl.c code has its own
6
code setting the reset values of its registers (which are
7
then used when updating the CPU when the guest makes
8
runtime changes).
9
10
Clean this up by making the armsse.c code set properties on the
11
iotkit-sysctl object to define the initial values of the
12
registers, so they always match the initial CPU state,
13
and update the comments in armsse.c accordingly.
5
14
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
17
Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
9
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
10
---
18
---
11
include/exec/exec-all.h | 5 +++--
19
include/hw/misc/iotkit-sysctl.h | 3 ++
12
accel/tcg/translate-all.c | 2 +-
20
hw/arm/armsse.c | 49 +++++++++++++++++++++------------
13
exec.c | 2 +-
21
hw/misc/iotkit-sysctl.c | 20 ++++++--------
14
target/xtensa/op_helper.c | 3 ++-
22
3 files changed, 42 insertions(+), 30 deletions(-)
15
4 files changed, 7 insertions(+), 5 deletions(-)
16
23
17
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
24
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
18
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/exec-all.h
26
--- a/include/hw/misc/iotkit-sysctl.h
20
+++ b/include/exec/exec-all.h
27
+++ b/include/hw/misc/iotkit-sysctl.h
21
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
28
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
22
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
29
23
hwaddr paddr, int prot,
30
/* Properties */
24
int mmu_idx, target_ulong size);
31
uint32_t sys_version;
25
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
32
+ uint32_t cpuwait_rst;
26
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
33
+ uint32_t initsvtor0_rst;
27
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
34
+ uint32_t initsvtor1_rst;
28
uintptr_t retaddr);
35
29
#else
36
bool is_sse200;
30
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
37
} IoTKitSysCtl;
31
uint16_t idxmap)
38
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
32
{
33
}
34
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
35
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
36
+ MemTxAttrs attrs)
37
{
38
}
39
#endif
40
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
41
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
42
--- a/accel/tcg/translate-all.c
40
--- a/hw/arm/armsse.c
43
+++ b/accel/tcg/translate-all.c
41
+++ b/hw/arm/armsse.c
44
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
42
@@ -XXX,XX +XXX,XX @@
45
}
43
46
44
#include "qemu/osdep.h"
47
#if !defined(CONFIG_USER_ONLY)
45
#include "qemu/log.h"
48
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
46
+#include "qemu/bitops.h"
49
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
47
#include "qapi/error.h"
50
{
48
#include "trace.h"
51
ram_addr_t ram_addr;
49
#include "hw/sysbus.h"
52
MemoryRegion *mr;
50
@@ -XXX,XX +XXX,XX @@ struct ARMSSEInfo {
53
diff --git a/exec.c b/exec.c
51
int sram_banks;
52
int num_cpus;
53
uint32_t sys_version;
54
+ uint32_t cpuwait_rst;
55
SysConfigFormat sys_config_format;
56
bool has_mhus;
57
bool has_ppus;
58
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
59
.sram_banks = 1,
60
.num_cpus = 1,
61
.sys_version = 0x41743,
62
+ .cpuwait_rst = 0,
63
.sys_config_format = IoTKitFormat,
64
.has_mhus = false,
65
.has_ppus = false,
66
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
67
.sram_banks = 4,
68
.num_cpus = 2,
69
.sys_version = 0x22041743,
70
+ .cpuwait_rst = 2,
71
.sys_config_format = SSE200Format,
72
.has_mhus = true,
73
.has_ppus = true,
74
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
75
76
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
77
/*
78
- * In real hardware the initial Secure VTOR is set from the INITSVTOR0
79
- * register in the IoT Kit System Control Register block, and the
80
- * initial value of that is in turn specifiable by the FPGA that
81
- * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
82
- * and simply set the CPU's init-svtor to the IoT Kit default value.
83
- * In SSE-200 the situation is similar, except that the default value
84
- * is a reset-time signal input. Typically a board using the SSE-200
85
- * will have a system control processor whose boot firmware initializes
86
- * the INITSVTOR* registers before powering up the CPUs in any case,
87
- * so the hardware's default value doesn't matter. QEMU doesn't emulate
88
+ * In real hardware the initial Secure VTOR is set from the INITSVTOR*
89
+ * registers in the IoT Kit System Control Register block. In QEMU
90
+ * we set the initial value here, and also the reset value of the
91
+ * sysctl register, from this object's QOM init-svtor property.
92
+ * If the guest changes the INITSVTOR* registers at runtime then the
93
+ * code in iotkit-sysctl.c will update the CPU init-svtor property
94
+ * (which will then take effect on the next CPU warm-reset).
95
+ *
96
+ * Note that typically a board using the SSE-200 will have a system
97
+ * control processor whose boot firmware initializes the INITSVTOR*
98
+ * registers before powering up the CPUs. QEMU doesn't emulate
99
* the control processor, so instead we behave in the way that the
100
- * firmware does. The initial value is configurable by the board code
101
- * to match whatever its firmware does.
102
+ * firmware does: the initial value should be set by the board code
103
+ * (using the init-svtor property on the ARMSSE object) to match
104
+ * whatever its firmware does.
105
*/
106
qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
107
/*
108
- * Start all CPUs except CPU0 powered down. In real hardware it is
109
- * a configurable property of the SSE-200 which CPUs start powered up
110
- * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
111
- * the boards we care about start CPU0 and leave CPU1 powered off,
112
- * we hard-code that for now. We can add QOM properties for this
113
+ * CPUs start powered down if the corresponding bit in the CPUWAIT
114
+ * register is 1. In real hardware the CPUWAIT register reset value is
115
+ * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
116
+ * CPUWAIT1_RST parameters), but since all the boards we care about
117
+ * start CPU0 and leave CPU1 powered off, we hard-code that in
118
+ * info->cpuwait_rst for now. We can add QOM properties for this
119
* later if necessary.
120
*/
121
- if (i > 0) {
122
+ if (extract32(info->cpuwait_rst, i, 1)) {
123
object_property_set_bool(cpuobj, true, "start-powered-off", &err);
124
if (err) {
125
error_propagate(errp, err);
126
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
127
/* System control registers */
128
object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
129
"SYS_VERSION", &err);
130
+ object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
131
+ "CPUWAIT_RST", &err);
132
+ object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
133
+ "INITSVTOR0_RST", &err);
134
+ object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
135
+ "INITSVTOR1_RST", &err);
136
object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
137
if (err) {
138
error_propagate(errp, err);
139
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
54
index XXXXXXX..XXXXXXX 100644
140
index XXXXXXX..XXXXXXX 100644
55
--- a/exec.c
141
--- a/hw/misc/iotkit-sysctl.c
56
+++ b/exec.c
142
+++ b/hw/misc/iotkit-sysctl.c
57
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
143
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
58
if (phys != -1) {
144
s->reset_syndrome = 1;
59
/* Locks grabbed by tb_invalidate_phys_addr */
145
s->reset_mask = 0;
60
tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
146
s->gretreg = 0;
61
- phys | (pc & ~TARGET_PAGE_MASK));
147
- s->initsvtor0 = 0x10000000;
62
+ phys | (pc & ~TARGET_PAGE_MASK), attrs);
148
- s->initsvtor1 = 0x10000000;
63
}
149
- if (s->is_sse200) {
64
}
150
- /*
65
#endif
151
- * CPU 0 starts on, CPU 1 starts off. In real hardware this is
66
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
152
- * configurable by the SoC integrator as a verilog parameter.
67
index XXXXXXX..XXXXXXX 100644
153
- */
68
--- a/target/xtensa/op_helper.c
154
- s->cpuwait = 2;
69
+++ b/target/xtensa/op_helper.c
155
- } else {
70
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
156
- /* CPU 0 starts on */
71
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
157
- s->cpuwait = 0;
72
&paddr, &page_size, &access);
158
- }
73
if (ret == 0) {
159
+ s->initsvtor0 = s->initsvtor0_rst;
74
- tb_invalidate_phys_addr(&address_space_memory, paddr);
160
+ s->initsvtor1 = s->initsvtor1_rst;
75
+ tb_invalidate_phys_addr(&address_space_memory, paddr,
161
+ s->cpuwait = s->cpuwait_rst;
76
+ MEMTXATTRS_UNSPECIFIED);
162
s->wicctrl = 0;
77
}
163
s->scsecctrl = 0;
78
}
164
s->fclk_div = 0;
165
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
166
167
static Property iotkit_sysctl_props[] = {
168
DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
169
+ DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
170
+ DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
171
+ 0x10000000),
172
+ DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
173
+ 0x10000000),
174
DEFINE_PROP_END_OF_LIST()
175
};
79
176
80
--
177
--
81
2.17.1
178
2.20.1
82
179
83
180
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
[Qemu-devel] [PULL 09/16] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
1
In commit f0aff255700 we made cpacr_write() enforce that some CPACR
1
Instead of gating the A32/T32 FP16 conversion instructions on
2
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
2
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
3
we forgot to also update the register's reset value. The effect
3
looking at ID register bits. In this case MVFR1 fields FPHP
4
was that (a) a guest that read CPACR on reset would not see ones in
4
and SIMDHP indicate the presence of these insns.
5
the RAO bits, and (b) if you did a migration before the guest did
6
a write to the CPACR then the migration would fail because the
7
destination would enforce the RAO bits and then complain that they
8
didn't match the zero value from the source.
9
5
10
Implement reset for the CPACR using a custom reset function
6
This change doesn't alter behaviour for any of our CPUs.
11
that just calls cpacr_write(), to avoid having to duplicate
12
the logic for which bits are RAO.
13
7
14
This bug would affect migration for TCG CPUs which are ARMv7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
with VFP but without one of Neon or VFPv3.
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
11
---
12
target/arm/cpu.h | 37 ++++++++++++++++++++++++++++++++++++-
13
target/arm/cpu.c | 2 --
14
target/arm/kvm32.c | 3 ---
15
target/arm/translate.c | 26 ++++++++++++++++++--------
16
4 files changed, 54 insertions(+), 14 deletions(-)
16
17
17
Reported-by: Cédric Le Goater <clg@kaod.org>
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Tested-by: Cédric Le Goater <clg@kaod.org>
20
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
21
---
22
target/arm/helper.c | 10 +++++++++-
23
1 file changed, 9 insertions(+), 1 deletion(-)
24
25
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
27
--- a/target/arm/helper.c
20
--- a/target/arm/cpu.h
28
+++ b/target/arm/helper.c
21
+++ b/target/arm/cpu.h
29
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
22
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
30
env->cp15.cpacr_el1 = value;
23
FIELD(ID_DFR0, PERFMON, 24, 4)
24
FIELD(ID_DFR0, TRACEFILT, 28, 4)
25
26
+FIELD(MVFR0, SIMDREG, 0, 4)
27
+FIELD(MVFR0, FPSP, 4, 4)
28
+FIELD(MVFR0, FPDP, 8, 4)
29
+FIELD(MVFR0, FPTRAP, 12, 4)
30
+FIELD(MVFR0, FPDIVIDE, 16, 4)
31
+FIELD(MVFR0, FPSQRT, 20, 4)
32
+FIELD(MVFR0, FPSHVEC, 24, 4)
33
+FIELD(MVFR0, FPROUND, 28, 4)
34
+
35
+FIELD(MVFR1, FPFTZ, 0, 4)
36
+FIELD(MVFR1, FPDNAN, 4, 4)
37
+FIELD(MVFR1, SIMDLS, 8, 4)
38
+FIELD(MVFR1, SIMDINT, 12, 4)
39
+FIELD(MVFR1, SIMDSP, 16, 4)
40
+FIELD(MVFR1, SIMDHP, 20, 4)
41
+FIELD(MVFR1, FPHP, 24, 4)
42
+FIELD(MVFR1, SIMDFMAC, 28, 4)
43
+
44
+FIELD(MVFR2, SIMDMISC, 0, 4)
45
+FIELD(MVFR2, FPMISC, 4, 4)
46
+
47
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
48
49
/* If adding a feature bit which corresponds to a Linux ELF
50
@@ -XXX,XX +XXX,XX @@ enum arm_features {
51
ARM_FEATURE_THUMB2,
52
ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
53
ARM_FEATURE_VFP3,
54
- ARM_FEATURE_VFP_FP16,
55
ARM_FEATURE_NEON,
56
ARM_FEATURE_M, /* Microcontroller profile. */
57
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
58
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
59
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
31
}
60
}
32
61
33
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
62
+/*
63
+ * We always set the FP and SIMD FP16 fields to indicate identical
64
+ * levels of support (assuming SIMD is implemented at all), so
65
+ * we only need one set of accessors.
66
+ */
67
+static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
34
+{
68
+{
35
+ /* Call cpacr_write() so that we reset with the correct RAO bits set
69
+ return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
36
+ * for our CPU features.
37
+ */
38
+ cpacr_write(env, ri, 0);
39
+}
70
+}
40
+
71
+
41
static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
72
+static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
42
bool isread)
73
+{
43
{
74
+ return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
75
+}
45
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
76
+
46
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
77
/*
47
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
78
* 64-bit feature tests via id registers.
48
- .resetvalue = 0, .writefn = cpacr_write },
79
*/
49
+ .resetfn = cpacr_reset, .writefn = cpacr_write },
80
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
50
REGINFO_SENTINEL
81
index XXXXXXX..XXXXXXX 100644
51
};
82
--- a/target/arm/cpu.c
52
83
+++ b/target/arm/cpu.c
84
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
85
}
86
if (arm_feature(env, ARM_FEATURE_VFP4)) {
87
set_feature(env, ARM_FEATURE_VFP3);
88
- set_feature(env, ARM_FEATURE_VFP_FP16);
89
}
90
if (arm_feature(env, ARM_FEATURE_VFP3)) {
91
set_feature(env, ARM_FEATURE_VFP);
92
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
93
cpu->dtb_compatible = "arm,cortex-a9";
94
set_feature(&cpu->env, ARM_FEATURE_V7);
95
set_feature(&cpu->env, ARM_FEATURE_VFP3);
96
- set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
97
set_feature(&cpu->env, ARM_FEATURE_NEON);
98
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
99
set_feature(&cpu->env, ARM_FEATURE_EL3);
100
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/kvm32.c
103
+++ b/target/arm/kvm32.c
104
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
105
if (extract32(id_pfr0, 12, 4) == 1) {
106
set_feature(&features, ARM_FEATURE_THUMB2EE);
107
}
108
- if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
109
- set_feature(&features, ARM_FEATURE_VFP_FP16);
110
- }
111
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
112
set_feature(&features, ARM_FEATURE_NEON);
113
}
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
119
* UNPREDICTABLE if bit 8 is set prior to ARMv8
120
* (we choose to UNDEF)
121
*/
122
- if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
123
- !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
124
- return 1;
125
+ if (dp) {
126
+ if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
127
+ return 1;
128
+ }
129
+ } else {
130
+ if (!dc_isar_feature(aa32_fp16_spconv, s)) {
131
+ return 1;
132
+ }
133
}
134
rm_is_dp = false;
135
break;
136
case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
137
case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
138
- if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
139
- !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
140
- return 1;
141
+ if (dp) {
142
+ if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
143
+ return 1;
144
+ }
145
+ } else {
146
+ if (!dc_isar_feature(aa32_fp16_spconv, s)) {
147
+ return 1;
148
+ }
149
}
150
rd_is_dp = false;
151
break;
152
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
153
TCGv_ptr fpst;
154
TCGv_i32 ahp;
155
156
- if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
157
+ if (!dc_isar_feature(aa32_fp16_spconv, s) ||
158
q || (rm & 1)) {
159
return 1;
160
}
161
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
162
{
163
TCGv_ptr fpst;
164
TCGv_i32 ahp;
165
- if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
166
+ if (!dc_isar_feature(aa32_fp16_spconv, s) ||
167
q || (rd & 1)) {
168
return 1;
169
}
53
--
170
--
54
2.17.1
171
2.20.1
55
172
56
173
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
[Qemu-devel] [PULL 10/16] target/arm: Gate "miscellaneous FP" insns by ID register field
1
The FRECPX instructions should (like most other floating point operations)
1
There is a set of VFP instructions which we implement in
2
honour the FPCR.FZ bit which specifies whether input denormals should
2
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
3
be flushed to zero (or FZ16 for the half-precision version).
3
These were all first introduced in v8 for A-profile, but in
4
We forgot to implement this, which doesn't affect the results (since
4
M-profile they appeared in v7M. Gate them on the MVFR2
5
the calculation doesn't actually care about the mantissa bits) but did
5
FPMisc field instead, and rename the function appropriately.
6
mean we were failing to set the FPSR.IDC bit.
7
6
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
9
Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
11
---
10
---
12
target/arm/helper-a64.c | 6 ++++++
11
target/arm/cpu.h | 20 ++++++++++++++++++++
13
1 file changed, 6 insertions(+)
12
target/arm/translate.c | 25 +++++++++++++------------
13
2 files changed, 33 insertions(+), 12 deletions(-)
14
14
15
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper-a64.c
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/helper-a64.c
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
19
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
20
return nan;
20
return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
21
}
22
23
+static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
24
+{
25
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
26
+}
27
+
28
+static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
29
+{
30
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
31
+}
32
+
33
+static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
34
+{
35
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
36
+}
37
+
38
+static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
39
+{
40
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
41
+}
42
+
43
/*
44
* 64-bit feature tests via id registers.
45
*/
46
diff --git a/target/arm/translate.c b/target/arm/translate.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate.c
49
+++ b/target/arm/translate.c
50
@@ -XXX,XX +XXX,XX @@ static const uint8_t fp_decode_rm[] = {
51
FPROUNDING_NEGINF,
52
};
53
54
-static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
55
+static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
56
{
57
uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
58
59
- if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
60
- return 1;
61
- }
62
-
63
if (dp) {
64
VFP_DREG_D(rd, insn);
65
VFP_DREG_N(rn, insn);
66
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
67
rm = VFP_SREG_M(insn);
21
}
68
}
22
69
23
+ a = float16_squash_input_denormal(a, fpst);
70
- if ((insn & 0x0f800e50) == 0x0e000a00) {
24
+
71
+ if ((insn & 0x0f800e50) == 0x0e000a00 && dc_isar_feature(aa32_vsel, s)) {
25
val16 = float16_val(a);
72
return handle_vsel(insn, rd, rn, rm, dp);
26
sbit = 0x8000 & val16;
73
- } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
27
exp = extract32(val16, 10, 5);
74
+ } else if ((insn & 0x0fb00e10) == 0x0e800a00 &&
28
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
75
+ dc_isar_feature(aa32_vminmaxnm, s)) {
29
return nan;
76
return handle_vminmaxnm(insn, rd, rn, rm, dp);
77
- } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
78
+ } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
79
+ dc_isar_feature(aa32_vrint, s)) {
80
/* VRINTA, VRINTN, VRINTP, VRINTM */
81
int rounding = fp_decode_rm[extract32(insn, 16, 2)];
82
return handle_vrint(insn, rd, rm, dp, rounding);
83
- } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40) {
84
+ } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&
85
+ dc_isar_feature(aa32_vcvt_dr, s)) {
86
/* VCVTA, VCVTN, VCVTP, VCVTM */
87
int rounding = fp_decode_rm[extract32(insn, 16, 2)];
88
return handle_vcvt(insn, rd, rm, dp, rounding);
89
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
30
}
90
}
31
91
32
+ a = float32_squash_input_denormal(a, fpst);
92
if (extract32(insn, 28, 4) == 0xf) {
33
+
93
- /* Encodings with T=1 (Thumb) or unconditional (ARM):
34
val32 = float32_val(a);
94
- * only used in v8 and above.
35
sbit = 0x80000000ULL & val32;
95
+ /*
36
exp = extract32(val32, 23, 8);
96
+ * Encodings with T=1 (Thumb) or unconditional (ARM):
37
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
97
+ * only used for the "miscellaneous VFP features" added in v8A
38
return nan;
98
+ * and v7M (and gated on the MVFR2.FPMisc field).
99
*/
100
- return disas_vfp_v8_insn(s, insn);
101
+ return disas_vfp_misc_insn(s, insn);
39
}
102
}
40
103
41
+ a = float64_squash_input_denormal(a, fpst);
104
dp = ((insn & 0xf00) == 0xb00);
42
+
43
val64 = float64_val(a);
44
sbit = 0x8000000000000000ULL & val64;
45
exp = extract64(float64_val(a), 52, 11);
46
--
105
--
47
2.17.1
106
2.20.1
48
107
49
108
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
[Qemu-devel] [PULL 11/16] Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
1
From: Richard Henderson <richard.henderson@linaro.org>
1
This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
2
which introduces a regression running EDK2 guest firmware
3
under KVM:
2
4
3
Depending on the host abi, float16, aka uint16_t, values are
5
error: kvm run failed Function not implemented
4
passed and returned either zero-extended in the host register
6
PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
5
or with garbage at the top of the host register.
7
X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
8
X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
9
X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
10
X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
11
X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
12
X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
13
X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
14
X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
15
X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
16
X29=000000013e3d12a0 X30=000000013f5a2518 SP=000000013b7be0b0
17
PSTATE=404003c4 -Z-- EL1t
6
18
7
The tcg code generator has so far been assuming garbage, as that
19
with
8
matches the x86 abi, but this is incorrect for other host abis.
20
[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
9
Further, target/arm has so far been assuming zero-extended results,
21
in the host dmesg.
10
so that it may store the 16-bit value into a 32-bit slot with the
11
high 16-bits already clear.
12
22
13
Rectify both problems by mapping "f16" in the helper definition
23
Revert the change for the moment until we can investigate the
14
to uint32_t instead of (a typedef for) uint16_t. This forces
24
cause of the regression.
15
the host compiler to assume garbage in the upper 16 bits on input
16
and to zero-extend the result on output.
17
25
18
Cc: qemu-stable@nongnu.org
26
Reported-by: Eric Auger <eric.auger@redhat.com>
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
22
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
28
---
26
include/exec/helper-head.h | 2 +-
29
target/arm/cpu.h | 9 +--------
27
target/arm/helper-a64.c | 35 +++++++++--------
30
target/arm/helper.c | 27 ++-------------------------
28
target/arm/helper.c | 80 +++++++++++++++++++-------------------
31
target/arm/kvm32.c | 20 ++++++++++++++++++--
29
3 files changed, 59 insertions(+), 58 deletions(-)
32
target/arm/kvm64.c | 2 --
33
target/arm/machine.c | 2 +-
34
5 files changed, 22 insertions(+), 38 deletions(-)
30
35
31
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
36
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
33
--- a/include/exec/helper-head.h
38
--- a/target/arm/cpu.h
34
+++ b/include/exec/helper-head.h
39
+++ b/target/arm/cpu.h
35
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
36
#define dh_ctype_int int
41
/**
37
#define dh_ctype_i64 uint64_t
42
* write_cpustate_to_list:
38
#define dh_ctype_s64 int64_t
43
* @cpu: ARMCPU
39
-#define dh_ctype_f16 float16
44
- * @kvm_sync: true if this is for syncing back to KVM
40
+#define dh_ctype_f16 uint32_t
45
*
41
#define dh_ctype_f32 float32
46
* For each register listed in the ARMCPU cpreg_indexes list, write
42
#define dh_ctype_f64 float64
47
* its value from the ARMCPUState structure into the cpreg_values list.
43
#define dh_ctype_ptr void *
48
* This is used to copy info from TCG's working data structures into
44
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
49
* KVM or for outbound migration.
45
index XXXXXXX..XXXXXXX 100644
50
*
46
--- a/target/arm/helper-a64.c
51
- * @kvm_sync is true if we are doing this in order to sync the
47
+++ b/target/arm/helper-a64.c
52
- * register state back to KVM. In this case we will only update
48
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
53
- * values in the list if the previous list->cpustate sync actually
49
return flags;
54
- * successfully wrote the CPU state. Otherwise we will keep the value
50
}
55
- * that is in the list.
51
56
- *
52
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
57
* Returns: true if all register values were read correctly,
53
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
58
* false if some register was unknown or could not be read.
54
{
59
* Note that we do not stop early on failure -- we will attempt
55
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
60
* reading all registers in the list.
56
}
57
58
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
59
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
60
{
61
return float_rel_to_flags(float16_compare(x, y, fp_status));
62
}
63
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
64
#define float64_three make_float64(0x4008000000000000ULL)
65
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
66
67
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
68
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
69
{
70
float_status *fpst = fpstp;
71
72
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
73
return float64_muladd(a, b, float64_two, 0, fpst);
74
}
75
76
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
77
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
78
{
79
float_status *fpst = fpstp;
80
81
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
82
}
83
84
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
85
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
86
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
87
{
88
float_status *fpst = fpstp;
89
uint16_t val16, sbit;
90
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
91
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
92
93
#define ADVSIMD_HALFOP(name) \
94
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
95
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
96
{ \
97
float_status *fpst = fpstp; \
98
return float16_ ## name(a, b, fpst); \
99
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
100
ADVSIMD_TWOHALFOP(mulx)
101
102
/* fused multiply-accumulate */
103
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
104
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
105
+ void *fpstp)
106
{
107
float_status *fpst = fpstp;
108
return float16_muladd(a, b, c, 0, fpst);
109
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
110
111
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
112
113
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
114
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
115
{
116
float_status *fpst = fpstp;
117
int compare = float16_compare_quiet(a, b, fpst);
118
return ADVSIMD_CMPRES(compare == float_relation_equal);
119
}
120
121
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
122
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
123
{
124
float_status *fpst = fpstp;
125
int compare = float16_compare(a, b, fpst);
126
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
127
compare == float_relation_equal);
128
}
129
130
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
131
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
132
{
133
float_status *fpst = fpstp;
134
int compare = float16_compare(a, b, fpst);
135
return ADVSIMD_CMPRES(compare == float_relation_greater);
136
}
137
138
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
139
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
140
{
141
float_status *fpst = fpstp;
142
float16 f0 = float16_abs(a);
143
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
144
compare == float_relation_equal);
145
}
146
147
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
148
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
149
{
150
float_status *fpst = fpstp;
151
float16 f0 = float16_abs(a);
152
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
153
}
154
155
/* round to integral */
156
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
157
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
158
{
159
return float16_round_to_int(x, fp_status);
160
}
161
162
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
163
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
164
{
165
int old_flags = get_float_exception_flags(fp_status), new_flags;
166
float16 ret;
167
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
168
* setting the mode appropriately before calling the helper.
169
*/
61
*/
170
62
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
171
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
63
+bool write_cpustate_to_list(ARMCPU *cpu);
172
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
64
173
{
65
#define ARM_CPUID_TI915T 0x54029152
174
float_status *fpst = fpstp;
66
#define ARM_CPUID_TI925T 0x54029252
175
176
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
177
return float16_to_int16(a, fpst);
178
}
179
180
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
181
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
182
{
183
float_status *fpst = fpstp;
184
185
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
186
* Square Root and Reciprocal square root
187
*/
188
189
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
190
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
191
{
192
float_status *s = fpstp;
193
194
diff --git a/target/arm/helper.c b/target/arm/helper.c
67
diff --git a/target/arm/helper.c b/target/arm/helper.c
195
index XXXXXXX..XXXXXXX 100644
68
index XXXXXXX..XXXXXXX 100644
196
--- a/target/arm/helper.c
69
--- a/target/arm/helper.c
197
+++ b/target/arm/helper.c
70
+++ b/target/arm/helper.c
198
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
71
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
199
72
return true;
200
/* Integer to float and float to integer conversions */
201
202
-#define CONV_ITOF(name, fsz, sign) \
203
- float##fsz HELPER(name)(uint32_t x, void *fpstp) \
204
-{ \
205
- float_status *fpst = fpstp; \
206
- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
207
+#define CONV_ITOF(name, ftype, fsz, sign) \
208
+ftype HELPER(name)(uint32_t x, void *fpstp) \
209
+{ \
210
+ float_status *fpst = fpstp; \
211
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
212
}
73
}
213
74
214
-#define CONV_FTOI(name, fsz, sign, round) \
75
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
215
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
76
+bool write_cpustate_to_list(ARMCPU *cpu)
216
-{ \
77
{
217
- float_status *fpst = fpstp; \
78
/* Write the coprocessor state from cpu->env to the (index,value) list. */
218
- if (float##fsz##_is_any_nan(x)) { \
79
int i;
219
- float_raise(float_flag_invalid, fpst); \
80
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
220
- return 0; \
81
for (i = 0; i < cpu->cpreg_array_len; i++) {
221
- } \
82
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
222
- return float##fsz##_to_##sign##int32##round(x, fpst); \
83
const ARMCPRegInfo *ri;
223
+#define CONV_FTOI(name, ftype, fsz, sign, round) \
84
- uint64_t newval;
224
+uint32_t HELPER(name)(ftype x, void *fpstp) \
85
225
+{ \
86
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
226
+ float_status *fpst = fpstp; \
87
if (!ri) {
227
+ if (float##fsz##_is_any_nan(x)) { \
88
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
228
+ float_raise(float_flag_invalid, fpst); \
89
if (ri->type & ARM_CP_NO_RAW) {
229
+ return 0; \
90
continue;
230
+ } \
91
}
231
+ return float##fsz##_to_##sign##int32##round(x, fpst); \
92
-
93
- newval = read_raw_cp_reg(&cpu->env, ri);
94
- if (kvm_sync) {
95
- /*
96
- * Only sync if the previous list->cpustate sync succeeded.
97
- * Rather than tracking the success/failure state for every
98
- * item in the list, we just recheck "does the raw write we must
99
- * have made in write_list_to_cpustate() read back OK" here.
100
- */
101
- uint64_t oldval = cpu->cpreg_values[i];
102
-
103
- if (oldval == newval) {
104
- continue;
105
- }
106
-
107
- write_raw_cp_reg(&cpu->env, ri, oldval);
108
- if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
109
- continue;
110
- }
111
-
112
- write_raw_cp_reg(&cpu->env, ri, newval);
113
- }
114
- cpu->cpreg_values[i] = newval;
115
+ cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
116
}
117
return ok;
232
}
118
}
233
119
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
234
-#define FLOAT_CONVS(name, p, fsz, sign) \
120
index XXXXXXX..XXXXXXX 100644
235
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
121
--- a/target/arm/kvm32.c
236
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
122
+++ b/target/arm/kvm32.c
237
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
123
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
238
+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
124
return ret;
239
+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
240
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
241
+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
242
243
-FLOAT_CONVS(si, h, 16, )
244
-FLOAT_CONVS(si, s, 32, )
245
-FLOAT_CONVS(si, d, 64, )
246
-FLOAT_CONVS(ui, h, 16, u)
247
-FLOAT_CONVS(ui, s, 32, u)
248
-FLOAT_CONVS(ui, d, 64, u)
249
+FLOAT_CONVS(si, h, uint32_t, 16, )
250
+FLOAT_CONVS(si, s, float32, 32, )
251
+FLOAT_CONVS(si, d, float64, 64, )
252
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
253
+FLOAT_CONVS(ui, s, float32, 32, u)
254
+FLOAT_CONVS(ui, d, float64, 64, u)
255
256
#undef CONV_ITOF
257
#undef CONV_FTOI
258
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
259
return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
260
}
261
262
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
263
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
264
{
265
return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
266
}
267
268
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
269
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
270
{
271
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
272
}
273
274
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
275
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
276
{
277
return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
278
}
279
280
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
281
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
282
{
283
return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
284
}
285
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
286
}
125
}
287
}
126
288
127
- write_cpustate_to_list(cpu, true);
289
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
128
-
290
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
129
+ /* Note that we do not call write_cpustate_to_list()
291
{
130
+ * here, so we are only writing the tuple list back to
292
return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
131
+ * KVM. This is safe because nothing can change the
293
}
132
+ * CPUARMState cp15 fields (in particular gdb accesses cannot)
294
133
+ * and so there are no changes to sync. In fact syncing would
295
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
134
+ * be wrong at this point: for a constant register where TCG and
296
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
135
+ * KVM disagree about its value, the preceding write_list_to_cpustate()
297
{
136
+ * would not have had any effect on the CPUARMState value (since the
298
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
137
+ * register is read-only), and a write_cpustate_to_list() here would
299
}
138
+ * then try to write the TCG value back into KVM -- this would either
300
139
+ * fail or incorrectly change the value the guest sees.
301
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
140
+ *
302
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
141
+ * If we ever want to allow the user to modify cp15 registers via
303
{
142
+ * the gdb stub, we would need to be more clever here (for instance
304
return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
143
+ * tracking the set of registers kvm_arch_get_registers() successfully
305
}
144
+ * managed to update the CPUARMState with, and only allowing those
306
145
+ * to be written back up into the kernel).
307
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
146
+ */
308
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
147
if (!write_list_to_kvmstate(cpu, level)) {
309
{
148
return EINVAL;
310
return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
149
}
311
}
150
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
312
151
index XXXXXXX..XXXXXXX 100644
313
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
152
--- a/target/arm/kvm64.c
314
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
153
+++ b/target/arm/kvm64.c
315
{
154
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
316
return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
155
return ret;
317
}
156
}
318
157
319
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
158
- write_cpustate_to_list(cpu, true);
320
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
159
-
321
{
160
if (!write_list_to_kvmstate(cpu, level)) {
322
return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
161
return EINVAL;
323
}
162
}
324
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
163
diff --git a/target/arm/machine.c b/target/arm/machine.c
325
}
164
index XXXXXXX..XXXXXXX 100644
326
165
--- a/target/arm/machine.c
327
/* Half precision conversions. */
166
+++ b/target/arm/machine.c
328
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
167
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
329
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
168
abort();
330
{
169
}
331
/* Squash FZ16 to 0 for the duration of conversion. In this case,
170
} else {
332
* it would affect flushing input denormals.
171
- if (!write_cpustate_to_list(cpu, false)) {
333
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
172
+ if (!write_cpustate_to_list(cpu)) {
334
return r;
173
/* This should never fail. */
335
}
174
abort();
336
175
}
337
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
338
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
339
{
340
/* Squash FZ16 to 0 for the duration of conversion. In this case,
341
* it would affect flushing output denormals.
342
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
343
return r;
344
}
345
346
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
347
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
348
{
349
/* Squash FZ16 to 0 for the duration of conversion. In this case,
350
* it would affect flushing input denormals.
351
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
352
return r;
353
}
354
355
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
356
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
357
{
358
/* Squash FZ16 to 0 for the duration of conversion. In this case,
359
* it would affect flushing output denormals.
360
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
361
g_assert_not_reached();
362
}
363
364
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
365
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
366
{
367
float_status *fpst = fpstp;
368
float16 f16 = float16_squash_input_denormal(input, fpst);
369
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
370
return extract64(estimate, 0, 8) << 44;
371
}
372
373
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
374
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
375
{
376
float_status *s = fpstp;
377
float16 f16 = float16_squash_input_denormal(input, s);
378
--
176
--
379
2.17.1
177
2.20.1
380
178
381
179
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
[Qemu-devel] [PULL 12/16] target/arm: Add helpers for FMLAL
1
From: Igor Mammedov <imammedo@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
When QEMU is started with following CLI
3
Note that float16_to_float32 rightly squashes SNaN to QNaN.
4
-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
4
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
5
it crashes with abort at
5
So we have to preserve SNaN long enough for the correct NaN
6
accel/kvm/kvm-all.c:2164:
6
to be selected. Thus float16_to_float32_by_bits.
7
KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
8
7
9
Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
arm_gicv3_icc_reset() where the later is called by CPU reset
9
Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
11
reset callback.
12
13
However commit:
14
3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
15
broke CPU reset callback registration in case
16
17
arm_load_kernel()
18
...
19
if (!info->kernel_filename || info->firmware_loaded)
20
21
branch is taken, i.e. it's sufficient to provide a firmware
22
or do not provide kernel on CLI to skip cpu reset callback
23
registration, where before offending commit the callback
24
has been registered unconditionally.
25
26
Fix it by registering the callback right at the beginning of
27
arm_load_kernel() unconditionally instead of doing it at the end.
28
29
NOTE:
30
we probably should eliminate that dependency anyways as well as
31
separate arch CPU reset parts from arm_load_kernel() into CPU
32
itself, but that refactoring that I probably would have to do
33
anyways later for CPU hotplug to work.
34
35
Reported-by: Auger Eric <eric.auger@redhat.com>
36
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
37
Reviewed-by: Eric Auger <eric.auger@redhat.com>
38
Tested-by: Eric Auger <eric.auger@redhat.com>
39
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
40
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
41
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
42
---
12
---
43
hw/arm/boot.c | 18 +++++++++---------
13
target/arm/helper.h | 9 +++
44
1 file changed, 9 insertions(+), 9 deletions(-)
14
target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++
15
2 files changed, 157 insertions(+)
45
16
46
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
47
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/arm/boot.c
19
--- a/target/arm/helper.h
49
+++ b/hw/arm/boot.c
20
+++ b/target/arm/helper.h
50
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
51
static const ARMInsnFixup *primary_loader;
22
DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
52
AddressSpace *as = arm_boot_address_space(cpu, info);
23
void, ptr, ptr, ptr, ptr, i32)
53
24
54
+ /* CPU objects (unlike devices) are not automatically reset on system
25
+DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
55
+ * reset, so we must always register a handler to do so. If we're
26
+ void, ptr, ptr, ptr, ptr, i32)
56
+ * actually loading a kernel, the handler is also responsible for
27
+DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
57
+ * arranging that we start it correctly.
28
+ void, ptr, ptr, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
30
+ void, ptr, ptr, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
32
+ void, ptr, ptr, ptr, ptr, i32)
33
+
34
#ifdef TARGET_AARCH64
35
#include "helper-a64.h"
36
#include "helper-sve.h"
37
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/vec_helper.c
40
+++ b/target/arm/vec_helper.c
41
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
42
}
43
clear_tail(d, oprsz, simd_maxsz(desc));
44
}
45
+
46
+/*
47
+ * Convert float16 to float32, raising no exceptions and
48
+ * preserving exceptional values, including SNaN.
49
+ * This is effectively an unpack+repack operation.
50
+ */
51
+static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
52
+{
53
+ const int f16_bias = 15;
54
+ const int f32_bias = 127;
55
+ uint32_t sign = extract32(f16, 15, 1);
56
+ uint32_t exp = extract32(f16, 10, 5);
57
+ uint32_t frac = extract32(f16, 0, 10);
58
+
59
+ if (exp == 0x1f) {
60
+ /* Inf or NaN */
61
+ exp = 0xff;
62
+ } else if (exp == 0) {
63
+ /* Zero or denormal. */
64
+ if (frac != 0) {
65
+ if (fz16) {
66
+ frac = 0;
67
+ } else {
68
+ /*
69
+ * Denormal; these are all normal float32.
70
+ * Shift the fraction so that the msb is at bit 11,
71
+ * then remove bit 11 as the implicit bit of the
72
+ * normalized float32. Note that we still go through
73
+ * the shift for normal numbers below, to put the
74
+ * float32 fraction at the right place.
75
+ */
76
+ int shift = clz32(frac) - 21;
77
+ frac = (frac << shift) & 0x3ff;
78
+ exp = f32_bias - f16_bias - shift + 1;
79
+ }
80
+ }
81
+ } else {
82
+ /* Normal number; adjust the bias. */
83
+ exp += f32_bias - f16_bias;
84
+ }
85
+ sign <<= 31;
86
+ exp <<= 23;
87
+ frac <<= 23 - 10;
88
+
89
+ return sign | exp | frac;
90
+}
91
+
92
+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
93
+{
94
+ /*
95
+ * Branchless load of u32[0], u64[0], u32[1], or u64[1].
96
+ * Load the 2nd qword iff is_q & is_2.
97
+ * Shift to the 2nd dword iff !is_q & is_2.
98
+ * For !is_q & !is_2, the upper bits of the result are garbage.
58
+ */
99
+ */
59
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
100
+ return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
60
+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
101
+}
102
+
103
+/*
104
+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
105
+ * as there is not yet SVE versions that might use blocking.
106
+ */
107
+
108
+static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
109
+ uint32_t desc, bool fz16)
110
+{
111
+ intptr_t i, oprsz = simd_oprsz(desc);
112
+ int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
113
+ int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
114
+ int is_q = oprsz == 16;
115
+ uint64_t n_4, m_4;
116
+
117
+ /* Pre-load all of the f16 data, avoiding overlap issues. */
118
+ n_4 = load4_f16(vn, is_q, is_2);
119
+ m_4 = load4_f16(vm, is_q, is_2);
120
+
121
+ /* Negate all inputs for FMLSL at once. */
122
+ if (is_s) {
123
+ n_4 ^= 0x8000800080008000ull;
61
+ }
124
+ }
62
+
125
+
63
/* The board code is not supposed to set secure_board_setup unless
126
+ for (i = 0; i < oprsz / 4; i++) {
64
* running its code in secure mode is actually possible, and KVM
127
+ float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
65
* doesn't support secure.
128
+ float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
66
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
129
+ d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
67
ARM_CPU(cs)->env.boot_info = info;
130
+ }
68
}
131
+ clear_tail(d, oprsz, simd_maxsz(desc));
69
132
+}
70
- /* CPU objects (unlike devices) are not automatically reset on system
133
+
71
- * reset, so we must always register a handler to do so. If we're
134
+void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
72
- * actually loading a kernel, the handler is also responsible for
135
+ void *venv, uint32_t desc)
73
- * arranging that we start it correctly.
136
+{
74
- */
137
+ CPUARMState *env = venv;
75
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
138
+ do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
76
- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
139
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
77
- }
140
+}
78
-
141
+
79
if (!info->skip_dtb_autoload && have_dtb(info)) {
142
+void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
80
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
143
+ void *venv, uint32_t desc)
81
exit(1);
144
+{
145
+ CPUARMState *env = venv;
146
+ do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
147
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
148
+}
149
+
150
+static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
151
+ uint32_t desc, bool fz16)
152
+{
153
+ intptr_t i, oprsz = simd_oprsz(desc);
154
+ int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
155
+ int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
156
+ int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
157
+ int is_q = oprsz == 16;
158
+ uint64_t n_4;
159
+ float32 m_1;
160
+
161
+ /* Pre-load all of the f16 data, avoiding overlap issues. */
162
+ n_4 = load4_f16(vn, is_q, is_2);
163
+
164
+ /* Negate all inputs for FMLSL at once. */
165
+ if (is_s) {
166
+ n_4 ^= 0x8000800080008000ull;
167
+ }
168
+
169
+ m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
170
+
171
+ for (i = 0; i < oprsz / 4; i++) {
172
+ float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
173
+ d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
174
+ }
175
+ clear_tail(d, oprsz, simd_maxsz(desc));
176
+}
177
+
178
+void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
179
+ void *venv, uint32_t desc)
180
+{
181
+ CPUARMState *env = venv;
182
+ do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
183
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
184
+}
185
+
186
+void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
187
+ void *venv, uint32_t desc)
188
+{
189
+ CPUARMState *env = venv;
190
+ do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
191
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
192
+}
82
--
193
--
83
2.17.1
194
2.20.1
84
195
85
196
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
[Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
acpi_data_push uses g_array_set_size to resize the memory size. If there
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
is no enough contiguous memory, the address will be changed. So previous
4
Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
5
pointer could not be used any more. It must update the pointer and use
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
the new one.
7
8
Also, previous codes wrongly use le32 conversion of iort->node_offset
9
for subsequent computations that will result incorrect value if host is
10
not litlle endian. So use the non-converted one instead.
11
12
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
13
Reviewed-by: Eric Auger <eric.auger@redhat.com>
14
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
7
---
17
hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
8
target/arm/cpu.h | 5 ++++
18
1 file changed, 15 insertions(+), 5 deletions(-)
9
target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
10
2 files changed, 53 insertions(+), 1 deletion(-)
19
11
20
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt-acpi-build.c
14
--- a/target/arm/cpu.h
23
+++ b/hw/arm/virt-acpi-build.c
15
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
25
AcpiIortItsGroup *its;
17
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
26
AcpiIortTable *iort;
18
}
27
AcpiIortSmmu3 *smmu;
19
28
- size_t node_size, iort_length, smmu_offset = 0;
20
+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
29
+ size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
21
+{
30
AcpiIortRC *rc;
22
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
31
23
+}
32
iort = acpi_data_push(table_data, sizeof(*iort));
24
+
33
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
25
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
34
26
{
35
iort_length = sizeof(*iort);
27
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
36
iort->node_count = cpu_to_le32(nb_nodes);
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
37
- iort->node_offset = cpu_to_le32(sizeof(*iort));
29
index XXXXXXX..XXXXXXX 100644
38
+ /*
30
--- a/target/arm/translate-a64.c
39
+ * Use a copy in case table_data->data moves during acpi_data_push
31
+++ b/target/arm/translate-a64.c
40
+ * operations.
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
41
+ */
33
if (!fp_access_check(s)) {
42
+ iort_node_offset = sizeof(*iort);
34
return;
43
+ iort->node_offset = cpu_to_le32(iort_node_offset);
35
}
44
36
-
45
/* ITS group node */
37
handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
46
node_size = sizeof(*its) + sizeof(uint32_t);
38
return;
47
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
39
+
48
int irq = vms->irqmap[VIRT_SMMU];
40
+ case 0x1d: /* FMLAL */
49
41
+ case 0x3d: /* FMLSL */
50
/* SMMUv3 node */
42
+ case 0x59: /* FMLAL2 */
51
- smmu_offset = iort->node_offset + node_size;
43
+ case 0x79: /* FMLSL2 */
52
+ smmu_offset = iort_node_offset + node_size;
44
+ if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
53
node_size = sizeof(*smmu) + sizeof(*idmap);
45
+ unallocated_encoding(s);
54
iort_length += node_size;
46
+ return;
55
smmu = acpi_data_push(table_data, node_size);
47
+ }
56
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
48
+ if (fp_access_check(s)) {
57
idmap->id_count = cpu_to_le32(0xFFFF);
49
+ int is_s = extract32(insn, 23, 1);
58
idmap->output_base = 0;
50
+ int is_2 = extract32(insn, 29, 1);
59
/* output IORT node is the ITS group node (the first node) */
51
+ int data = (is_2 << 1) | is_s;
60
- idmap->output_reference = cpu_to_le32(iort->node_offset);
52
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
61
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
53
+ vec_full_reg_offset(s, rn),
54
+ vec_full_reg_offset(s, rm), cpu_env,
55
+ is_q ? 16 : 8, vec_full_reg_size(s),
56
+ data, gen_helper_gvec_fmlal_a64);
57
+ }
58
+ return;
59
+
60
default:
61
unallocated_encoding(s);
62
return;
63
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
64
}
65
is_fp = 2;
66
break;
67
+ case 0x00: /* FMLAL */
68
+ case 0x04: /* FMLSL */
69
+ case 0x18: /* FMLAL2 */
70
+ case 0x1c: /* FMLSL2 */
71
+ if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
72
+ unallocated_encoding(s);
73
+ return;
74
+ }
75
+ size = MO_16;
76
+ /* is_fp, but we pass cpu_env not fp_status. */
77
+ break;
78
default:
79
unallocated_encoding(s);
80
return;
81
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
82
tcg_temp_free_ptr(fpst);
83
}
84
return;
85
+
86
+ case 0x00: /* FMLAL */
87
+ case 0x04: /* FMLSL */
88
+ case 0x18: /* FMLAL2 */
89
+ case 0x1c: /* FMLSL2 */
90
+ {
91
+ int is_s = extract32(opcode, 2, 1);
92
+ int is_2 = u;
93
+ int data = (index << 2) | (is_2 << 1) | is_s;
94
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
95
+ vec_full_reg_offset(s, rn),
96
+ vec_full_reg_offset(s, rm), cpu_env,
97
+ is_q ? 16 : 8, vec_full_reg_size(s),
98
+ data, gen_helper_gvec_fmlal_idx_a64);
99
+ }
100
+ return;
62
}
101
}
63
102
64
/* Root Complex Node */
103
if (size == 3) {
65
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
66
idmap->output_reference = cpu_to_le32(smmu_offset);
67
} else {
68
/* output IORT node is the ITS group node (the first node) */
69
- idmap->output_reference = cpu_to_le32(iort->node_offset);
70
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
71
}
72
73
+ /*
74
+ * Update the pointer address in case table_data->data moves during above
75
+ * acpi_data_push operations.
76
+ */
77
+ iort = (AcpiIortTable *)(table_data->data + iort_start);
78
iort->length = cpu_to_le32(iort_length);
79
80
build_header(linker, table_data, (void *)(table_data->data + iort_start),
81
--
104
--
82
2.17.1
105
2.20.1
83
106
84
107
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
[Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
It forgot to increase clroffset during the loop. So it only clear the
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
first 4 bytes.
4
Message-id: 20190219222952.22183-4-richard.henderson@linaro.org
5
6
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
7
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
7
---
14
hw/intc/arm_gicv3_kvm.c | 1 +
8
target/arm/cpu.h | 5 ++
15
1 file changed, 1 insertion(+)
9
target/arm/translate.c | 129 ++++++++++++++++++++++++++++++-----------
16
10
2 files changed, 101 insertions(+), 33 deletions(-)
17
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
11
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/arm_gicv3_kvm.c
14
--- a/target/arm/cpu.h
20
+++ b/hw/intc/arm_gicv3_kvm.c
15
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
22
if (clroffset != 0) {
17
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
23
reg = 0;
18
}
24
kvm_gicd_access(s, clroffset, &reg, true);
19
25
+ clroffset += 4;
20
+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
21
+{
22
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
23
+}
24
+
25
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
26
{
27
/*
28
diff --git a/target/arm/translate.c b/target/arm/translate.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate.c
31
+++ b/target/arm/translate.c
32
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
33
gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
34
int rd, rn, rm, opr_sz;
35
int data = 0;
36
- bool q;
37
-
38
- q = extract32(insn, 6, 1);
39
- VFP_DREG_D(rd, insn);
40
- VFP_DREG_N(rn, insn);
41
- VFP_DREG_M(rm, insn);
42
- if ((rd | rn | rm) & q) {
43
- return 1;
44
- }
45
+ int off_rn, off_rm;
46
+ bool is_long = false, q = extract32(insn, 6, 1);
47
+ bool ptr_is_env = false;
48
49
if ((insn & 0xfe200f10) == 0xfc200800) {
50
/* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
51
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
52
return 1;
26
}
53
}
27
reg = *gic_bmp_ptr32(bmp, irq);
54
fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
28
kvm_gicd_access(s, offset, &reg, true);
55
+ } else if ((insn & 0xff300f10) == 0xfc200810) {
56
+ /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
57
+ int is_s = extract32(insn, 23, 1);
58
+ if (!dc_isar_feature(aa32_fhm, s)) {
59
+ return 1;
60
+ }
61
+ is_long = true;
62
+ data = is_s; /* is_2 == 0 */
63
+ fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
64
+ ptr_is_env = true;
65
} else {
66
return 1;
67
}
68
69
+ VFP_DREG_D(rd, insn);
70
+ if (rd & q) {
71
+ return 1;
72
+ }
73
+ if (q || !is_long) {
74
+ VFP_DREG_N(rn, insn);
75
+ VFP_DREG_M(rm, insn);
76
+ if ((rn | rm) & q & !is_long) {
77
+ return 1;
78
+ }
79
+ off_rn = vfp_reg_offset(1, rn);
80
+ off_rm = vfp_reg_offset(1, rm);
81
+ } else {
82
+ rn = VFP_SREG_N(insn);
83
+ rm = VFP_SREG_M(insn);
84
+ off_rn = vfp_reg_offset(0, rn);
85
+ off_rm = vfp_reg_offset(0, rm);
86
+ }
87
+
88
if (s->fp_excp_el) {
89
gen_exception_insn(s, 4, EXCP_UDEF,
90
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
91
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
92
93
opr_sz = (1 + q) * 8;
94
if (fn_gvec_ptr) {
95
- TCGv_ptr fpst = get_fpstatus_ptr(1);
96
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
97
- vfp_reg_offset(1, rn),
98
- vfp_reg_offset(1, rm), fpst,
99
+ TCGv_ptr ptr;
100
+ if (ptr_is_env) {
101
+ ptr = cpu_env;
102
+ } else {
103
+ ptr = get_fpstatus_ptr(1);
104
+ }
105
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
106
opr_sz, opr_sz, data, fn_gvec_ptr);
107
- tcg_temp_free_ptr(fpst);
108
+ if (!ptr_is_env) {
109
+ tcg_temp_free_ptr(ptr);
110
+ }
111
} else {
112
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
113
- vfp_reg_offset(1, rn),
114
- vfp_reg_offset(1, rm),
115
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
116
opr_sz, opr_sz, data, fn_gvec);
117
}
118
return 0;
119
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
120
gen_helper_gvec_3 *fn_gvec = NULL;
121
gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
122
int rd, rn, rm, opr_sz, data;
123
- bool q;
124
-
125
- q = extract32(insn, 6, 1);
126
- VFP_DREG_D(rd, insn);
127
- VFP_DREG_N(rn, insn);
128
- if ((rd | rn) & q) {
129
- return 1;
130
- }
131
+ int off_rn, off_rm;
132
+ bool is_long = false, q = extract32(insn, 6, 1);
133
+ bool ptr_is_env = false;
134
135
if ((insn & 0xff000f10) == 0xfe000800) {
136
/* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
137
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
138
} else if ((insn & 0xffb00f00) == 0xfe200d00) {
139
/* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
140
int u = extract32(insn, 4, 1);
141
+
142
if (!dc_isar_feature(aa32_dp, s)) {
143
return 1;
144
}
145
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
146
/* rm is just Vm, and index is M. */
147
data = extract32(insn, 5, 1); /* index */
148
rm = extract32(insn, 0, 4);
149
+ } else if ((insn & 0xffa00f10) == 0xfe000810) {
150
+ /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
151
+ int is_s = extract32(insn, 20, 1);
152
+ int vm20 = extract32(insn, 0, 3);
153
+ int vm3 = extract32(insn, 3, 1);
154
+ int m = extract32(insn, 5, 1);
155
+ int index;
156
+
157
+ if (!dc_isar_feature(aa32_fhm, s)) {
158
+ return 1;
159
+ }
160
+ if (q) {
161
+ rm = vm20;
162
+ index = m * 2 + vm3;
163
+ } else {
164
+ rm = vm20 * 2 + m;
165
+ index = vm3;
166
+ }
167
+ is_long = true;
168
+ data = (index << 2) | is_s; /* is_2 == 0 */
169
+ fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
170
+ ptr_is_env = true;
171
} else {
172
return 1;
173
}
174
175
+ VFP_DREG_D(rd, insn);
176
+ if (rd & q) {
177
+ return 1;
178
+ }
179
+ if (q || !is_long) {
180
+ VFP_DREG_N(rn, insn);
181
+ if (rn & q & !is_long) {
182
+ return 1;
183
+ }
184
+ off_rn = vfp_reg_offset(1, rn);
185
+ off_rm = vfp_reg_offset(1, rm);
186
+ } else {
187
+ rn = VFP_SREG_N(insn);
188
+ off_rn = vfp_reg_offset(0, rn);
189
+ off_rm = vfp_reg_offset(0, rm);
190
+ }
191
if (s->fp_excp_el) {
192
gen_exception_insn(s, 4, EXCP_UDEF,
193
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
194
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
195
196
opr_sz = (1 + q) * 8;
197
if (fn_gvec_ptr) {
198
- TCGv_ptr fpst = get_fpstatus_ptr(1);
199
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
200
- vfp_reg_offset(1, rn),
201
- vfp_reg_offset(1, rm), fpst,
202
+ TCGv_ptr ptr;
203
+ if (ptr_is_env) {
204
+ ptr = cpu_env;
205
+ } else {
206
+ ptr = get_fpstatus_ptr(1);
207
+ }
208
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
209
opr_sz, opr_sz, data, fn_gvec_ptr);
210
- tcg_temp_free_ptr(fpst);
211
+ if (!ptr_is_env) {
212
+ tcg_temp_free_ptr(ptr);
213
+ }
214
} else {
215
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
216
- vfp_reg_offset(1, rn),
217
- vfp_reg_offset(1, rm),
218
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
219
opr_sz, opr_sz, data, fn_gvec);
220
}
221
return 0;
29
--
222
--
30
2.17.1
223
2.20.1
31
224
32
225
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
[Qemu-devel] [PULL 15/16] target/arm: Enable ARMv8.2-FHM for -cpu max
1
From: Shannon Zhao <zhaoshenglong@huawei.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
initialize global capability variables. If we call kvm_init_irq_routing in
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
GIC realize function, previous allocated memory will leak.
5
Message-id: 20190219222952.22183-5-richard.henderson@linaro.org
6
7
Fix this by deleting the unnecessary call.
8
9
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
7
---
14
hw/intc/arm_gic_kvm.c | 1 -
8
target/arm/cpu.c | 1 +
15
hw/intc/arm_gicv3_kvm.c | 1 -
9
target/arm/cpu64.c | 2 ++
16
2 files changed, 2 deletions(-)
10
2 files changed, 3 insertions(+)
17
11
18
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
19
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/intc/arm_gic_kvm.c
14
--- a/target/arm/cpu.c
21
+++ b/hw/intc/arm_gic_kvm.c
15
+++ b/target/arm/cpu.c
22
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
16
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
23
17
t = cpu->isar.id_isar6;
24
if (kvm_has_gsi_routing()) {
18
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
25
/* set up irq routing */
19
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
26
- kvm_init_irq_routing(kvm_state);
20
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
27
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
21
cpu->isar.id_isar6 = t;
28
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
22
29
}
23
t = cpu->id_mmfr4;
30
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
24
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
31
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_kvm.c
26
--- a/target/arm/cpu64.c
33
+++ b/hw/intc/arm_gicv3_kvm.c
27
+++ b/target/arm/cpu64.c
34
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
28
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
35
29
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
36
if (kvm_has_gsi_routing()) {
30
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
37
/* set up irq routing */
31
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
38
- kvm_init_irq_routing(kvm_state);
32
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
39
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
33
cpu->isar.id_aa64isar0 = t;
40
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
34
41
}
35
t = cpu->isar.id_aa64isar1;
36
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
37
u = cpu->isar.id_isar6;
38
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
39
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
40
+ u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
41
cpu->isar.id_isar6 = u;
42
43
/*
42
--
44
--
43
2.17.1
45
2.20.1
44
46
45
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
[Qemu-devel] [PULL 16/16] linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
1
From: Jan Kiszka <jan.kiszka@siemens.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
There was a nasty flip in identifying which register group an access is
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
targeting. The issue caused spuriously raised priorities of the guest
4
Message-id: 20190219222952.22183-6-richard.henderson@linaro.org
5
when handing CPUs over in the Jailhouse hypervisor.
6
7
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
9
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
7
---
13
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
8
linux-user/elfload.c | 2 ++
14
1 file changed, 6 insertions(+), 6 deletions(-)
9
1 file changed, 2 insertions(+)
15
10
16
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
11
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/arm_gicv3_cpuif.c
13
--- a/linux-user/elfload.c
19
+++ b/hw/intc/arm_gicv3_cpuif.c
14
+++ b/linux-user/elfload.c
20
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
15
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
21
{
16
GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
22
GICv3CPUState *cs = icc_cs_from_env(env);
17
GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
23
int regno = ri->opc2 & 3;
18
GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
24
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
19
+ GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
25
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
20
+ GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
26
uint64_t value = cs->ich_apr[grp][regno];
21
27
22
#undef GET_FEATURE_ID
28
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
29
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
30
{
31
GICv3CPUState *cs = icc_cs_from_env(env);
32
int regno = ri->opc2 & 3;
33
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
34
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
35
36
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
37
38
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
39
uint64_t value;
40
41
int regno = ri->opc2 & 3;
42
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
43
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
44
45
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
46
return icv_ap_read(env, ri);
47
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
48
GICv3CPUState *cs = icc_cs_from_env(env);
49
50
int regno = ri->opc2 & 3;
51
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
52
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
53
54
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
55
icv_ap_write(env, ri, value);
56
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
57
{
58
GICv3CPUState *cs = icc_cs_from_env(env);
59
int regno = ri->opc2 & 3;
60
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
61
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
62
uint64_t value;
63
64
value = cs->ich_apr[grp][regno];
65
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
66
{
67
GICv3CPUState *cs = icc_cs_from_env(env);
68
int regno = ri->opc2 & 3;
69
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
70
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
71
72
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
73
23
74
--
24
--
75
2.17.1
25
2.20.1
76
26
77
27
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
Deleted patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
1
3
cpregs_keys is an uint32_t* so the allocation should use uint32_t.
4
g_new is even better because it is type-safe.
5
6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/gdbstub.c | 3 +--
12
1 file changed, 1 insertion(+), 2 deletions(-)
13
14
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/gdbstub.c
17
+++ b/target/arm/gdbstub.c
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
19
RegisterSysregXmlParam param = {cs, s};
20
21
cpu->dyn_xml.num_cpregs = 0;
22
- cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
23
- g_hash_table_size(cpu->cp_regs));
24
+ cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
25
g_string_printf(s, "<?xml version=\"1.0\"?>");
26
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
27
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
28
--
29
2.17.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
Deleted patch
1
From: Francisco Iglesias <frasse.iglesias@gmail.com>
2
1
3
Coverity found that the string return by 'object_get_canonical_path' was not
4
being freed at two locations in the model (CID 1391294 and CID 1391293) and
5
also that a memset was being called with a value greater than the max of a byte
6
on the second argument (CID 1391286). This patch corrects this by adding the
7
freeing of the strings and also changing to memset to zero instead on
8
descriptor unaligned errors.
9
10
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/dma/xlnx-zdma.c | 10 +++++++---
18
1 file changed, 7 insertions(+), 3 deletions(-)
19
20
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/dma/xlnx-zdma.c
23
+++ b/hw/dma/xlnx-zdma.c
24
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
25
qemu_log_mask(LOG_GUEST_ERROR,
26
"zdma: unaligned descriptor at %" PRIx64,
27
addr);
28
- memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
29
+ memset(buf, 0x0, sizeof(XlnxZDMADescr));
30
s->error = true;
31
return false;
32
}
33
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
34
RegisterInfo *r = &s->regs_info[addr / 4];
35
36
if (!r->data) {
37
+ gchar *path = object_get_canonical_path(OBJECT(s));
38
qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
39
- object_get_canonical_path(OBJECT(s)),
40
+ path,
41
addr);
42
+ g_free(path);
43
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
44
zdma_ch_imr_update_irq(s);
45
return 0;
46
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
47
RegisterInfo *r = &s->regs_info[addr / 4];
48
49
if (!r->data) {
50
+ gchar *path = object_get_canonical_path(OBJECT(s));
51
qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
52
- object_get_canonical_path(OBJECT(s)),
53
+ path,
54
addr, value);
55
+ g_free(path);
56
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
57
zdma_ch_imr_update_irq(s);
58
return;
59
--
60
2.17.1
61
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_translate()
3
and address_space_translate_cached(). Callers either have an
4
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 4 +++-
12
accel/tcg/translate-all.c | 2 +-
13
exec.c | 14 +++++++++-----
14
hw/vfio/common.c | 3 ++-
15
memory_ldst.inc.c | 18 +++++++++---------
16
target/riscv/helper.c | 2 +-
17
6 files changed, 25 insertions(+), 18 deletions(-)
18
19
diff --git a/include/exec/memory.h b/include/exec/memory.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/exec/memory.h
22
+++ b/include/exec/memory.h
23
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
24
* #MemoryRegion.
25
* @len: pointer to length
26
* @is_write: indicates the transfer direction
27
+ * @attrs: memory attributes
28
*/
29
MemoryRegion *flatview_translate(FlatView *fv,
30
hwaddr addr, hwaddr *xlat,
31
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
32
33
static inline MemoryRegion *address_space_translate(AddressSpace *as,
34
hwaddr addr, hwaddr *xlat,
35
- hwaddr *len, bool is_write)
36
+ hwaddr *len, bool is_write,
37
+ MemTxAttrs attrs)
38
{
39
return flatview_translate(address_space_to_flatview(as),
40
addr, xlat, len, is_write);
41
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/accel/tcg/translate-all.c
44
+++ b/accel/tcg/translate-all.c
45
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
46
hwaddr l = 1;
47
48
rcu_read_lock();
49
- mr = address_space_translate(as, addr, &addr, &l, false);
50
+ mr = address_space_translate(as, addr, &addr, &l, false, attrs);
51
if (!(memory_region_is_ram(mr)
52
|| memory_region_is_romd(mr))) {
53
rcu_read_unlock();
54
diff --git a/exec.c b/exec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/exec.c
57
+++ b/exec.c
58
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
59
rcu_read_lock();
60
while (len > 0) {
61
l = len;
62
- mr = address_space_translate(as, addr, &addr1, &l, true);
63
+ mr = address_space_translate(as, addr, &addr1, &l, true,
64
+ MEMTXATTRS_UNSPECIFIED);
65
66
if (!(memory_region_is_ram(mr) ||
67
memory_region_is_romd(mr))) {
68
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
69
*/
70
static inline MemoryRegion *address_space_translate_cached(
71
MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
72
- hwaddr *plen, bool is_write)
73
+ hwaddr *plen, bool is_write, MemTxAttrs attrs)
74
{
75
MemoryRegionSection section;
76
MemoryRegion *mr;
77
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
78
MemoryRegion *mr;
79
80
l = len;
81
- mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
82
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
83
+ MEMTXATTRS_UNSPECIFIED);
84
flatview_read_continue(cache->fv,
85
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
86
addr1, l, mr);
87
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
88
MemoryRegion *mr;
89
90
l = len;
91
- mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
92
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
93
+ MEMTXATTRS_UNSPECIFIED);
94
flatview_write_continue(cache->fv,
95
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
96
addr1, l, mr);
97
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
98
99
rcu_read_lock();
100
mr = address_space_translate(&address_space_memory,
101
- phys_addr, &phys_addr, &l, false);
102
+ phys_addr, &phys_addr, &l, false,
103
+ MEMTXATTRS_UNSPECIFIED);
104
105
res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
106
rcu_read_unlock();
107
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/vfio/common.c
110
+++ b/hw/vfio/common.c
111
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
112
*/
113
mr = address_space_translate(&address_space_memory,
114
iotlb->translated_addr,
115
- &xlat, &len, writable);
116
+ &xlat, &len, writable,
117
+ MEMTXATTRS_UNSPECIFIED);
118
if (!memory_region_is_ram(mr)) {
119
error_report("iommu map to non memory area %"HWADDR_PRIx"",
120
xlat);
121
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/memory_ldst.inc.c
124
+++ b/memory_ldst.inc.c
125
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
126
bool release_lock = false;
127
128
RCU_READ_LOCK();
129
- mr = TRANSLATE(addr, &addr1, &l, false);
130
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
131
if (l < 4 || !IS_DIRECT(mr, false)) {
132
release_lock |= prepare_mmio_access(mr);
133
134
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
135
bool release_lock = false;
136
137
RCU_READ_LOCK();
138
- mr = TRANSLATE(addr, &addr1, &l, false);
139
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
140
if (l < 8 || !IS_DIRECT(mr, false)) {
141
release_lock |= prepare_mmio_access(mr);
142
143
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
144
bool release_lock = false;
145
146
RCU_READ_LOCK();
147
- mr = TRANSLATE(addr, &addr1, &l, false);
148
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
149
if (!IS_DIRECT(mr, false)) {
150
release_lock |= prepare_mmio_access(mr);
151
152
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
153
bool release_lock = false;
154
155
RCU_READ_LOCK();
156
- mr = TRANSLATE(addr, &addr1, &l, false);
157
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
158
if (l < 2 || !IS_DIRECT(mr, false)) {
159
release_lock |= prepare_mmio_access(mr);
160
161
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
162
bool release_lock = false;
163
164
RCU_READ_LOCK();
165
- mr = TRANSLATE(addr, &addr1, &l, true);
166
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
167
if (l < 4 || !IS_DIRECT(mr, true)) {
168
release_lock |= prepare_mmio_access(mr);
169
170
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
171
bool release_lock = false;
172
173
RCU_READ_LOCK();
174
- mr = TRANSLATE(addr, &addr1, &l, true);
175
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
176
if (l < 4 || !IS_DIRECT(mr, true)) {
177
release_lock |= prepare_mmio_access(mr);
178
179
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
180
bool release_lock = false;
181
182
RCU_READ_LOCK();
183
- mr = TRANSLATE(addr, &addr1, &l, true);
184
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
185
if (!IS_DIRECT(mr, true)) {
186
release_lock |= prepare_mmio_access(mr);
187
r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
188
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
189
bool release_lock = false;
190
191
RCU_READ_LOCK();
192
- mr = TRANSLATE(addr, &addr1, &l, true);
193
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
194
if (l < 2 || !IS_DIRECT(mr, true)) {
195
release_lock |= prepare_mmio_access(mr);
196
197
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
198
bool release_lock = false;
199
200
RCU_READ_LOCK();
201
- mr = TRANSLATE(addr, &addr1, &l, true);
202
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
203
if (l < 8 || !IS_DIRECT(mr, true)) {
204
release_lock |= prepare_mmio_access(mr);
205
206
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
207
index XXXXXXX..XXXXXXX 100644
208
--- a/target/riscv/helper.c
209
+++ b/target/riscv/helper.c
210
@@ -XXX,XX +XXX,XX @@ restart:
211
MemoryRegion *mr;
212
hwaddr l = sizeof(target_ulong), addr1;
213
mr = address_space_translate(cs->as, pte_addr,
214
- &addr1, &l, false);
215
+ &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
216
if (memory_access_is_direct(mr, true)) {
217
target_ulong *pte_pa =
218
qemu_map_ram_ptr(mr->ram_block, addr1);
219
--
220
2.17.1
221
222
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_map().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 3 ++-
12
include/sysemu/dma.h | 3 ++-
13
exec.c | 6 ++++--
14
target/ppc/mmu-hash64.c | 3 ++-
15
4 files changed, 10 insertions(+), 5 deletions(-)
16
17
diff --git a/include/exec/memory.h b/include/exec/memory.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/memory.h
20
+++ b/include/exec/memory.h
21
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
22
* @addr: address within that address space
23
* @plen: pointer to length of buffer; updated on return
24
* @is_write: indicates the transfer direction
25
+ * @attrs: memory attributes
26
*/
27
void *address_space_map(AddressSpace *as, hwaddr addr,
28
- hwaddr *plen, bool is_write);
29
+ hwaddr *plen, bool is_write, MemTxAttrs attrs);
30
31
/* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
32
*
33
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/sysemu/dma.h
36
+++ b/include/sysemu/dma.h
37
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
38
hwaddr xlen = *len;
39
void *p;
40
41
- p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
42
+ p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
43
+ MEMTXATTRS_UNSPECIFIED);
44
*len = xlen;
45
return p;
46
}
47
diff --git a/exec.c b/exec.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/exec.c
50
+++ b/exec.c
51
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
52
void *address_space_map(AddressSpace *as,
53
hwaddr addr,
54
hwaddr *plen,
55
- bool is_write)
56
+ bool is_write,
57
+ MemTxAttrs attrs)
58
{
59
hwaddr len = *plen;
60
hwaddr l, xlat;
61
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
62
hwaddr *plen,
63
int is_write)
64
{
65
- return address_space_map(&address_space_memory, addr, plen, is_write);
66
+ return address_space_map(&address_space_memory, addr, plen, is_write,
67
+ MEMTXATTRS_UNSPECIFIED);
68
}
69
70
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
71
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/target/ppc/mmu-hash64.c
74
+++ b/target/ppc/mmu-hash64.c
75
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
76
return NULL;
77
}
78
79
- hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
80
+ hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
81
+ MEMTXATTRS_UNSPECIFIED);
82
if (plen < (n * HASH_PTE_SIZE_64)) {
83
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
84
}
85
--
86
2.17.1
87
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
10
---
11
include/exec/memory.h | 4 +++-
12
include/sysemu/dma.h | 3 ++-
13
exec.c | 3 ++-
14
target/s390x/diag.c | 6 ++++--
15
target/s390x/excp_helper.c | 3 ++-
16
target/s390x/mmu_helper.c | 3 ++-
17
target/s390x/sigp.c | 3 ++-
18
7 files changed, 17 insertions(+), 8 deletions(-)
19
20
diff --git a/include/exec/memory.h b/include/exec/memory.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/memory.h
23
+++ b/include/exec/memory.h
24
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
25
* @addr: address within that address space
26
* @len: length of the area to be checked
27
* @is_write: indicates the transfer direction
28
+ * @attrs: memory attributes
29
*/
30
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
31
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
32
+ bool is_write, MemTxAttrs attrs);
33
34
/* address_space_map: map a physical memory region into a host virtual address
35
*
36
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/sysemu/dma.h
39
+++ b/include/sysemu/dma.h
40
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
41
DMADirection dir)
42
{
43
return address_space_access_valid(as, addr, len,
44
- dir == DMA_DIRECTION_FROM_DEVICE);
45
+ dir == DMA_DIRECTION_FROM_DEVICE,
46
+ MEMTXATTRS_UNSPECIFIED);
47
}
48
49
static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
50
diff --git a/exec.c b/exec.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/exec.c
53
+++ b/exec.c
54
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
55
}
56
57
bool address_space_access_valid(AddressSpace *as, hwaddr addr,
58
- int len, bool is_write)
59
+ int len, bool is_write,
60
+ MemTxAttrs attrs)
61
{
62
FlatView *fv;
63
bool result;
64
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/s390x/diag.c
67
+++ b/target/s390x/diag.c
68
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
69
return;
70
}
71
if (!address_space_access_valid(&address_space_memory, addr,
72
- sizeof(IplParameterBlock), false)) {
73
+ sizeof(IplParameterBlock), false,
74
+ MEMTXATTRS_UNSPECIFIED)) {
75
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
76
return;
77
}
78
@@ -XXX,XX +XXX,XX @@ out:
79
return;
80
}
81
if (!address_space_access_valid(&address_space_memory, addr,
82
- sizeof(IplParameterBlock), true)) {
83
+ sizeof(IplParameterBlock), true,
84
+ MEMTXATTRS_UNSPECIFIED)) {
85
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
86
return;
87
}
88
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/s390x/excp_helper.c
91
+++ b/target/s390x/excp_helper.c
92
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
93
94
/* check out of RAM access */
95
if (!address_space_access_valid(&address_space_memory, raddr,
96
- TARGET_PAGE_SIZE, rw)) {
97
+ TARGET_PAGE_SIZE, rw,
98
+ MEMTXATTRS_UNSPECIFIED)) {
99
DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
100
(uint64_t)raddr, (uint64_t)ram_size);
101
trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
102
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/s390x/mmu_helper.c
105
+++ b/target/s390x/mmu_helper.c
106
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
107
return ret;
108
}
109
if (!address_space_access_valid(&address_space_memory, pages[i],
110
- TARGET_PAGE_SIZE, is_write)) {
111
+ TARGET_PAGE_SIZE, is_write,
112
+ MEMTXATTRS_UNSPECIFIED)) {
113
trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
114
return -EFAULT;
115
}
116
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/target/s390x/sigp.c
119
+++ b/target/s390x/sigp.c
120
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
121
cpu_synchronize_state(cs);
122
123
if (!address_space_access_valid(&address_space_memory, addr,
124
- sizeof(struct LowCore), false)) {
125
+ sizeof(struct LowCore), false,
126
+ MEMTXATTRS_UNSPECIFIED)) {
127
set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
128
return;
129
}
130
--
131
2.17.1
132
133
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_extend_translation().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
10
---
11
exec.c | 15 ++++++++++-----
12
1 file changed, 10 insertions(+), 5 deletions(-)
13
14
diff --git a/exec.c b/exec.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/exec.c
17
+++ b/exec.c
18
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
19
20
static hwaddr
21
flatview_extend_translation(FlatView *fv, hwaddr addr,
22
- hwaddr target_len,
23
- MemoryRegion *mr, hwaddr base, hwaddr len,
24
- bool is_write)
25
+ hwaddr target_len,
26
+ MemoryRegion *mr, hwaddr base, hwaddr len,
27
+ bool is_write, MemTxAttrs attrs)
28
{
29
hwaddr done = 0;
30
hwaddr xlat;
31
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
32
33
memory_region_ref(mr);
34
*plen = flatview_extend_translation(fv, addr, len, mr, xlat,
35
- l, is_write);
36
+ l, is_write, attrs);
37
ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
38
rcu_read_unlock();
39
40
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
41
mr = cache->mrs.mr;
42
memory_region_ref(mr);
43
if (memory_access_is_direct(mr, is_write)) {
44
+ /* We don't care about the memory attributes here as we're only
45
+ * doing this if we found actual RAM, which behaves the same
46
+ * regardless of attributes; so UNSPECIFIED is fine.
47
+ */
48
l = flatview_extend_translation(cache->fv, addr, len, mr,
49
- cache->xlat, l, is_write);
50
+ cache->xlat, l, is_write,
51
+ MEMTXATTRS_UNSPECIFIED);
52
cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
53
} else {
54
cache->ptr = NULL;
55
--
56
2.17.1
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to memory_region_access_valid().
3
Its callers either have an attrs value to hand, or don't care
4
and can use MEMTXATTRS_UNSPECIFIED.
5
1
6
The callsite in flatview_access_valid() is part of a recursive
7
loop flatview_access_valid() -> memory_region_access_valid() ->
8
subpage_accepts() -> flatview_access_valid(); we make it pass
9
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
10
have plumbed an attrs parameter through the rest of the loop
11
and we can add an attrs parameter to flatview_access_valid().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
17
---
18
include/exec/memory-internal.h | 3 ++-
19
exec.c | 4 +++-
20
hw/s390x/s390-pci-inst.c | 3 ++-
21
memory.c | 7 ++++---
22
4 files changed, 11 insertions(+), 6 deletions(-)
23
24
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/exec/memory-internal.h
27
+++ b/include/exec/memory-internal.h
28
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
29
extern const MemoryRegionOps unassigned_mem_ops;
30
31
bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
32
- unsigned size, bool is_write);
33
+ unsigned size, bool is_write,
34
+ MemTxAttrs attrs);
35
36
void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
37
AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
38
diff --git a/exec.c b/exec.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/exec.c
41
+++ b/exec.c
42
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
43
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
44
if (!memory_access_is_direct(mr, is_write)) {
45
l = memory_access_size(mr, l, addr);
46
- if (!memory_region_access_valid(mr, xlat, l, is_write)) {
47
+ /* When our callers all have attrs we'll pass them through here */
48
+ if (!memory_region_access_valid(mr, xlat, l, is_write,
49
+ MEMTXATTRS_UNSPECIFIED)) {
50
return false;
51
}
52
}
53
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/s390x/s390-pci-inst.c
56
+++ b/hw/s390x/s390-pci-inst.c
57
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
58
mr = s390_get_subregion(mr, offset, len);
59
offset -= mr->addr;
60
61
- if (!memory_region_access_valid(mr, offset, len, true)) {
62
+ if (!memory_region_access_valid(mr, offset, len, true,
63
+ MEMTXATTRS_UNSPECIFIED)) {
64
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
65
return 0;
66
}
67
diff --git a/memory.c b/memory.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/memory.c
70
+++ b/memory.c
71
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
72
bool memory_region_access_valid(MemoryRegion *mr,
73
hwaddr addr,
74
unsigned size,
75
- bool is_write)
76
+ bool is_write,
77
+ MemTxAttrs attrs)
78
{
79
int access_size_min, access_size_max;
80
int access_size, i;
81
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
82
{
83
MemTxResult r;
84
85
- if (!memory_region_access_valid(mr, addr, size, false)) {
86
+ if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
87
*pval = unassigned_mem_read(mr, addr, size);
88
return MEMTX_DECODE_ERROR;
89
}
90
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
91
unsigned size,
92
MemTxAttrs attrs)
93
{
94
- if (!memory_region_access_valid(mr, addr, size, true)) {
95
+ if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
96
unassigned_mem_write(mr, addr, data, size);
97
return MEMTX_DECODE_ERROR;
98
}
99
--
100
2.17.1
101
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to address_space_get_iotlb_entry().
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
8
---
9
include/exec/memory.h | 2 +-
10
exec.c | 2 +-
11
hw/virtio/vhost.c | 3 ++-
12
3 files changed, 4 insertions(+), 3 deletions(-)
13
14
diff --git a/include/exec/memory.h b/include/exec/memory.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/memory.h
17
+++ b/include/exec/memory.h
18
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
19
* entry. Should be called from an RCU critical section.
20
*/
21
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
22
- bool is_write);
23
+ bool is_write, MemTxAttrs attrs);
24
25
/* address_space_translate: translate an address range into an address space
26
* into a MemoryRegion and an address range into that section. Should be
27
diff --git a/exec.c b/exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/exec.c
30
+++ b/exec.c
31
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
32
33
/* Called from RCU critical section */
34
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
35
- bool is_write)
36
+ bool is_write, MemTxAttrs attrs)
37
{
38
MemoryRegionSection section;
39
hwaddr xlat, page_mask;
40
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/vhost.c
43
+++ b/hw/virtio/vhost.c
44
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
45
trace_vhost_iotlb_miss(dev, 1);
46
47
iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
48
- iova, write);
49
+ iova, write,
50
+ MEMTXATTRS_UNSPECIFIED);
51
if (iotlb.target_as != NULL) {
52
ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
53
&uaddr, &len);
54
--
55
2.17.1
56
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
Deleted patch
1
As part of plumbing MemTxAttrs down to the IOMMU translate method,
2
add MemTxAttrs as an argument to flatview_do_translate().
3
1
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
8
---
9
exec.c | 9 ++++++---
10
1 file changed, 6 insertions(+), 3 deletions(-)
11
12
diff --git a/exec.c b/exec.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/exec.c
15
+++ b/exec.c
16
@@ -XXX,XX +XXX,XX @@ unassigned:
17
* @is_write: whether the translation operation is for write
18
* @is_mmio: whether this can be MMIO, set true if it can
19
* @target_as: the address space targeted by the IOMMU
20
+ * @attrs: memory transaction attributes
21
*
22
* This function is called from RCU critical section
23
*/
24
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
25
hwaddr *page_mask_out,
26
bool is_write,
27
bool is_mmio,
28
- AddressSpace **target_as)
29
+ AddressSpace **target_as,
30
+ MemTxAttrs attrs)
31
{
32
MemoryRegionSection *section;
33
IOMMUMemoryRegion *iommu_mr;
34
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
35
* but page mask.
36
*/
37
section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
38
- NULL, &page_mask, is_write, false, &as);
39
+ NULL, &page_mask, is_write, false, &as,
40
+ attrs);
41
42
/* Illegal translation */
43
if (section.mr == &io_mem_unassigned) {
44
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
45
46
/* This can be MMIO, so setup MMIO bit. */
47
section = flatview_do_translate(fv, addr, xlat, plen, NULL,
48
- is_write, true, &as);
49
+ is_write, true, &as, attrs);
50
mr = section.mr;
51
52
if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
53
--
54
2.17.1
55
56
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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