Series comparison

-[Qemu-devel] [PULL 00/25] target-arm queue
+[Qemu-devel] [PULL 00/10] target-arm queue
-target-arm queue. This has the "plumb txattrs through various
+Some Arm bugfixes for rc2...
 bits of exec.c" patches, and a collection of bug fixes from
 various people.
 thanks
 -- PMM
+The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:
+  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)
 The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
   Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119
-for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
+for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:
-  KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
+  MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * target/arm: Honour FPCR.FZ in FRECPX
+ * various MAINTAINERS file updates
- * MAINTAINERS: Add entries for newer MPS2 boards and devices
+ * hw/block/onenand: use qemu_log_mask() for reporting
- * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+ * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
- * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
+   on the n800 and n810 machine models
-   GIC state
+ * target/arm: fix smc incorrectly trapping to EL3 when secure is off
- * tcg: Fix helper function vs host abi for float16
+ * hw/arm/stm32f205: Fix the UART and Timer region size
- * arm: fix qemu crash on startup with -bios option
+ * target/arm: read ID registers for KVM guests so they can be
- * arm: fix malloc type mismatch
+   used to gate "is feature X present" checks
  * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
  * Correct CPACR reset value for v7 cores
  * memory.h: Improve IOMMU related documentation
  * exec: Plumb transaction attributes through various functions in
    preparation for allowing IOMMUs to see them
  * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
  * ARM: ACPI: Fix use-after-free due to memory realloc
  * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
 ----------------------------------------------------------------
-Francisco Iglesias (1):
+Luc Michel (1):
-      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+      target/arm: fix smc incorrectly trapping to EL3 when secure is off
-Igor Mammedov (1):
+Peter Maydell (3):
-      arm: fix qemu crash on startup with -bios option
+      hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
       hw/block/onenand: use qemu_log_mask() for reporting
       MAINTAINERS: list myself as maintainer for various Arm boards
-Jan Kiszka (1):
+Richard Henderson (4):
-      hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+      target/arm: Install ARMISARegisters from kvm host
       target/arm: Fill in ARMISARegisters for kvm64
       target/arm: Introduce read_sys_reg32 for kvm32
       target/arm: Fill in ARMISARegisters for kvm32
-Paolo Bonzini (1):
+Seth Kintigh (1):
-      arm: fix malloc type mismatch
+      hw/arm/stm32f205: Fix the UART and Timer region size
-Peter Maydell (17):
+Thomas Huth (1):
-      target/arm: Honour FPCR.FZ in FRECPX
+      MAINTAINERS: Add entries for missing ARM boards
       MAINTAINERS: Add entries for newer MPS2 boards and devices
       Correct CPACR reset value for v7 cores
       memory.h: Improve IOMMU related documentation
       Make tb_invalidate_phys_addr() take a MemTxAttrs argument
       Make address_space_translate{, _cached}() take a MemTxAttrs argument
       Make address_space_map() take a MemTxAttrs argument
       Make address_space_access_valid() take a MemTxAttrs argument
       Make flatview_extend_translation() take a MemTxAttrs argument
       Make memory_region_access_valid() take a MemTxAttrs argument
       Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
       Make flatview_access_valid() take a MemTxAttrs argument
       Make flatview_translate() take a MemTxAttrs argument
       Make address_space_get_iotlb_entry() take a MemTxAttrs argument
       Make flatview_do_translate() take a MemTxAttrs argument
       Make address_space_translate_iommu take a MemTxAttrs argument
       vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
-Richard Henderson (1):
+ target/arm/kvm_arm.h       |   1 +
-      tcg: Fix helper function vs host abi for float16
+ hw/block/onenand.c         |  24 +++++-----
  hw/char/stm32f2xx_usart.c  |   2 +-
  hw/timer/stm32f2xx_timer.c |   2 +-
  target/arm/kvm.c           |   1 +
  target/arm/kvm32.c         |  77 ++++++++++++++++++++------------
  target/arm/kvm64.c         |  90 +++++++++++++++++++++++++++++++++++++-
  target/arm/op_helper.c     |  54 +++++++++++++++++++----
  MAINTAINERS                | 106 +++++++++++++++++++++++++++++++++++++++------
 files changed, 293 insertions(+), 64 deletions(-)
-Shannon Zhao (3):
-      arm_gicv3_kvm: increase clroffset accordingly
-      ARM: ACPI: Fix use-after-free due to memory realloc
-      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
- include/exec/exec-all.h        |   5 +-
- include/exec/helper-head.h     |   2 +-
- include/exec/memory-internal.h |   3 +-
- include/exec/memory.h          | 128 +++++++++++++++++++++++++++++++++++------
- include/migration/vmstate.h    |   3 +
- include/sysemu/dma.h           |   6 +-
- accel/tcg/translate-all.c      |   4 +-
- exec.c                         |  95 ++++++++++++++++++------------
- hw/arm/boot.c                  |  18 +++---
- hw/arm/virt-acpi-build.c       |  20 +++++--
- hw/dma/xlnx-zdma.c             |  10 +++-
- hw/hppa/dino.c                 |   3 +-
- hw/intc/arm_gic_kvm.c          |   1 -
- hw/intc/arm_gicv3_cpuif.c      |  12 ++--
- hw/intc/arm_gicv3_kvm.c        |   2 +-
- hw/nvram/fw_cfg.c              |  12 ++--
- hw/s390x/s390-pci-inst.c       |   3 +-
- hw/scsi/esp.c                  |   3 +-
- hw/vfio/common.c               |   3 +-
- hw/virtio/vhost.c              |   3 +-
- hw/xen/xen_pt_msi.c            |   3 +-
- memory.c                       |  12 ++--
- memory_ldst.inc.c              |  18 +++---
- target/arm/gdbstub.c           |   3 +-
- target/arm/helper-a64.c        |  41 +++++++------
- target/arm/helper.c            |  90 ++++++++++++++++-------------
- target/ppc/mmu-hash64.c        |   3 +-
- target/riscv/helper.c          |   2 +-
- target/s390x/diag.c            |   6 +-
- target/s390x/excp_helper.c     |   3 +-
- target/s390x/mmu_helper.c      |   3 +-
- target/s390x/sigp.c            |   3 +-
- target/xtensa/op_helper.c      |   3 +-
- MAINTAINERS                    |   9 ++-
-files changed, 353 insertions(+), 182 deletions(-)

-[Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
+Deleted patch
-The FRECPX instructions should (like most other floating point operations)
-honour the FPCR.FZ bit which specifies whether input denormals should
-be flushed to zero (or FZ16 for the half-precision version).
-We forgot to implement this, which doesn't affect the results (since
-the calculation doesn't actually care about the mantissa bits) but did
-mean we were failing to set the FPSR.IDC bit.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
----
- target/arm/helper-a64.c | 6 ++++++
-file changed, 6 insertions(+)
-diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper-a64.c
-+++ b/target/arm/helper-a64.c
-@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
-         return nan;
-     }
-+    a = float16_squash_input_denormal(a, fpst);
-+
-     val16 = float16_val(a);
-     sbit = 0x8000 & val16;
-     exp = extract32(val16, 10, 5);
-@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
-         return nan;
-     }
-+    a = float32_squash_input_denormal(a, fpst);
-+
-     val32 = float32_val(a);
-     sbit = 0x80000000ULL & val32;
-     exp = extract32(val32, 23, 8);
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
-         return nan;
-     }
-+    a = float64_squash_input_denormal(a, fpst);
-+
-     val64 = float64_val(a);
-     sbit = 0x8000000000000000ULL & val64;
-     exp = extract64(float64_val(a), 52, 11);
---
-.17.1

-[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
+[Qemu-devel] [PULL 01/10] target/arm: Install ARMISARegisters from kvm host
-From: Jan Kiszka <jan.kiszka@siemens.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-There was a nasty flip in identifying which register group an access is
+The ID registers are replacing (some of) the feature bits.
-targeting. The issue caused spuriously raised priorities of the guest
+We need (some of) these values to determine the set of data
-when handing CPUs over in the Jailhouse hypervisor.
+to be handled during migration.
-Cc: qemu-stable@nongnu.org
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Message-id: 20181113180154.17903-2-richard.henderson@linaro.org
 Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
+ target/arm/kvm_arm.h | 1 +
-file changed, 6 insertions(+), 6 deletions(-)
+ target/arm/kvm.c     | 1 +
 files changed, 2 insertions(+)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/target/arm/kvm_arm.h
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/target/arm/kvm_arm.h
-@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
- {
+  * by asking the host kernel)
-     GICv3CPUState *cs = icc_cs_from_env(env);
+  */
-     int regno = ri->opc2 & 3;
+ typedef struct ARMHostCPUFeatures {
--    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
++    ARMISARegisters isar;
-+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+     uint64_t features;
-     uint64_t value = cs->ich_apr[grp][regno];
+     uint32_t target;
+     const char *dtb_compatible;
-     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
+diff --git a/target/arm/kvm.c b/target/arm/kvm.c
-@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
+index XXXXXXX..XXXXXXX 100644
- {
+--- a/target/arm/kvm.c
-     GICv3CPUState *cs = icc_cs_from_env(env);
++++ b/target/arm/kvm.c
-     int regno = ri->opc2 & 3;
+@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
--    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
-+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
+     cpu->kvm_target = arm_host_cpu_features.target;
+     cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
-     trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
++    cpu->isar = arm_host_cpu_features.isar;
+     env->features = arm_host_cpu_features.features;
-@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ }
      uint64_t value;
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
 +    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
      if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
          return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
 +    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
      if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
          icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      uint64_t value;
      value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
  {
      GICv3CPUState *cs = icc_cs_from_env(env);
      int regno = ri->opc2 & 3;
 -    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
 +    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
      trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
+[Qemu-devel] [PULL 02/10] target/arm: Fill in ARMISARegisters for kvm64
 From: Richard Henderson <richard.henderson@linaro.org>
-Depending on the host abi, float16, aka uint16_t, values are
-passed and returned either zero-extended in the host register
-or with garbage at the top of the host register.
-The tcg code generator has so far been assuming garbage, as that
-matches the x86 abi, but this is incorrect for other host abis.
-Further, target/arm has so far been assuming zero-extended results,
-so that it may store the 16-bit value into a 32-bit slot with the
-high 16-bits already clear.
-Rectify both problems by mapping "f16" in the helper definition
-to uint32_t instead of (a typedef for) uint16_t.  This forces
-the host compiler to assume garbage in the upper 16 bits on input
-and to zero-extend the result on output.
-Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20181113180154.17903-3-richard.henderson@linaro.org
 Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/exec/helper-head.h |  2 +-
+ target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--
- target/arm/helper-a64.c    | 35 +++++++++--------
+file changed, 88 insertions(+), 2 deletions(-)
  target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 files changed, 59 insertions(+), 58 deletions(-)
-diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/exec/helper-head.h
+--- a/target/arm/kvm64.c
-+++ b/include/exec/helper-head.h
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature)
- #define dh_ctype_int int
+     *features &= ~(1ULL << feature);
  #define dh_ctype_i64 uint64_t
  #define dh_ctype_s64 int64_t
 -#define dh_ctype_f16 float16
 +#define dh_ctype_f16 uint32_t
  #define dh_ctype_f32 float32
  #define dh_ctype_f64 float64
  #define dh_ctype_ptr void *
 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper-a64.c
 +++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
      return flags;
  }
--uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
++static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
-+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
++{
 +    uint64_t ret;
 +    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
 +    int err;
 +
 +    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
 +    err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
 +    if (err < 0) {
 +        return -1;
 +    }
 +    *pret = ret;
 +    return 0;
 +}
 +
 +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
 +{
 +    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
 +
 +    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
 +    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
 +}
 +
  bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  {
-     return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
+     /* Identify the feature bits corresponding to the host CPU, and
- }
+      * fill out the ARMHostCPUClass fields accordingly. To do this
+      * we have to create a scratch VM, create a single CPU inside it,
--uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+      * and then query that CPU for the relevant ID registers.
-+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
+-     * For AArch64 we currently don't care about ID registers at
- {
+-     * all; we just want to know the CPU type.
-     return float_rel_to_flags(float16_compare(x, y, fp_status));
+      */
- }
+     int fdarray[3];
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
+     uint64_t features = 0;
- #define float64_three make_float64(0x4008000000000000ULL)
++    int err;
- #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
++
+     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
--float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+      * we know these will only support creating one kind of guest CPU,
-+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
+      * which is its preferred CPU type. Fortunately these old kernels
- {
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-     float_status *fpst = fpstp;
+     ahcf->target = init.target;
+     ahcf->dtb_compatible = "arm,arm-v8";
-@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
-     return float64_muladd(a, b, float64_two, 0, fpst);
++    err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
- }
++                         ARM64_SYS_REG(3, 0, 0, 4, 0));
++    if (unlikely(err < 0)) {
--float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
++        /*
-+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
++         * Before v4.15, the kernel only exposed a limited number of system
- {
++         * registers, not including any of the interesting AArch64 ID regs.
-     float_status *fpst = fpstp;
++         * For the most part we could leave these fields as zero with minimal
++         * effect, since this does not affect the values seen by the guest.
-@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
++         *
- }
++         * However, it could cause problems down the line for QEMU,
++         * so provide a minimal v8.0 default.
- /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
++         *
--float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
++         * ??? Could read MIDR and use knowledge from cpu64.c.
-+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
++         * ??? Could map a page of memory into our temp guest and
- {
++         *     run the tiniest of hand-crafted kernels to extract
-     float_status *fpst = fpstp;
++         *     the values seen by the guest.
-     uint16_t val16, sbit;
++         * ??? Either of these sounds like too much effort just
-@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
++         *     to work around running a modern host kernel.
- #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
++         */
++        ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
- #define ADVSIMD_HALFOP(name) \
++        err = 0;
--float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
++    } else {
-+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
++        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
- { \
++                              ARM64_SYS_REG(3, 0, 0, 4, 1));
-     float_status *fpst = fpstp; \
++        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
-     return float16_ ## name(a, b, fpst);    \
++                              ARM64_SYS_REG(3, 0, 0, 6, 0));
-@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
++        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
- ADVSIMD_TWOHALFOP(mulx)
++                              ARM64_SYS_REG(3, 0, 0, 6, 1));
++
- /* fused multiply-accumulate */
++        /*
--float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
++         * Note that if AArch32 support is not present in the host,
-+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
++         * the AArch32 sysregs are present to be read, but will
-+                                 void *fpstp)
++         * return UNKNOWN values.  This is neither better nor worse
- {
++         * than skipping the reads and leaving 0, as we must avoid
-     float_status *fpst = fpstp;
++         * considering the values in every case.
-     return float16_muladd(a, b, c, 0, fpst);
++         */
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
++                              ARM64_SYS_REG(3, 0, 0, 2, 0));
- #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
++                              ARM64_SYS_REG(3, 0, 0, 2, 1));
--uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
-+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
++                              ARM64_SYS_REG(3, 0, 0, 2, 2));
- {
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
-     float_status *fpst = fpstp;
++                              ARM64_SYS_REG(3, 0, 0, 2, 3));
-     int compare = float16_compare_quiet(a, b, fpst);
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
-     return ADVSIMD_CMPRES(compare == float_relation_equal);
++                              ARM64_SYS_REG(3, 0, 0, 2, 4));
- }
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
++                              ARM64_SYS_REG(3, 0, 0, 2, 5));
--uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
-+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
++                              ARM64_SYS_REG(3, 0, 0, 2, 7));
- {
++
-     float_status *fpst = fpstp;
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
-     int compare = float16_compare(a, b, fpst);
++                              ARM64_SYS_REG(3, 0, 0, 3, 0));
-@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
-                           compare == float_relation_equal);
++                              ARM64_SYS_REG(3, 0, 0, 3, 1));
- }
++        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
++                              ARM64_SYS_REG(3, 0, 0, 3, 2));
--uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
++    }
-+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
++
- {
+     kvm_arm_destroy_scratch_host_vcpu(fdarray);
-     float_status *fpst = fpstp;
-     int compare = float16_compare(a, b, fpst);
++    if (err < 0) {
-     return ADVSIMD_CMPRES(compare == float_relation_greater);
++        return false;
- }
++    }
++
--uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+    /* We can assume any KVM supporting CPU is at least a v8
-+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
+      * with VFPv4+Neon; this in turn implies most of the other
- {
+      * feature bits.
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                            compare == float_relation_equal);
  }
 -uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 +uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
  }
  /* round to integral */
 -float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
  {
      return float16_round_to_int(x, fp_status);
  }
 -float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
 +uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
  {
      int old_flags = get_float_exception_flags(fp_status), new_flags;
      float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
   * setting the mode appropriately before calling the helper.
   */
 -uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
 +uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
      return float16_to_int16(a, fpst);
  }
 -uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
 +uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
  {
      float_status *fpst = fpstp;
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
   * Square Root and Reciprocal square root
   */
 -float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
 +uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
  {
      float_status *s = fpstp;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
  /* Integer to float and float to integer conversions */
 -#define CONV_ITOF(name, fsz, sign) \
 -    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
 +#define CONV_ITOF(name, ftype, fsz, sign)                           \
 +ftype HELPER(name)(uint32_t x, void *fpstp)                         \
 +{                                                                   \
 +    float_status *fpst = fpstp;                                     \
 +    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
  }
 -#define CONV_FTOI(name, fsz, sign, round) \
 -uint32_t HELPER(name)(float##fsz x, void *fpstp) \
 -{ \
 -    float_status *fpst = fpstp; \
 -    if (float##fsz##_is_any_nan(x)) { \
 -        float_raise(float_flag_invalid, fpst); \
 -        return 0; \
 -    } \
 -    return float##fsz##_to_##sign##int32##round(x, fpst); \
 +#define CONV_FTOI(name, ftype, fsz, sign, round)                \
 +uint32_t HELPER(name)(ftype x, void *fpstp)                     \
 +{                                                               \
 +    float_status *fpst = fpstp;                                 \
 +    if (float##fsz##_is_any_nan(x)) {                           \
 +        float_raise(float_flag_invalid, fpst);                  \
 +        return 0;                                               \
 +    }                                                           \
 +    return float##fsz##_to_##sign##int32##round(x, fpst);       \
  }
 -#define FLOAT_CONVS(name, p, fsz, sign) \
 -CONV_ITOF(vfp_##name##to##p, fsz, sign) \
 -CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
 -CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
 +#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
 +    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
 +    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
 +    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 -FLOAT_CONVS(si, h, 16, )
 -FLOAT_CONVS(si, s, 32, )
 -FLOAT_CONVS(si, d, 64, )
 -FLOAT_CONVS(ui, h, 16, u)
 -FLOAT_CONVS(ui, s, 32, u)
 -FLOAT_CONVS(ui, d, 64, u)
 +FLOAT_CONVS(si, h, uint32_t, 16, )
 +FLOAT_CONVS(si, s, float32, 32, )
 +FLOAT_CONVS(si, d, float64, 64, )
 +FLOAT_CONVS(ui, h, uint32_t, 16, u)
 +FLOAT_CONVS(ui, s, float32, 32, u)
 +FLOAT_CONVS(ui, d, float64, 64, u)
  #undef CONV_ITOF
  #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
      return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
  }
 -float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
  }
 -float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
  {
      return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
  }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
      }
  }
 -uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
 +uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
  }
 -uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
 +uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
  {
      return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
  }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
  }
  /* Half precision conversions.  */
 -float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
 +float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
      return r;
  }
 -float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 +uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
  {
      /* Squash FZ16 to 0 for the duration of conversion.  In this case,
       * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
      g_assert_not_reached();
  }
 -float16 HELPER(recpe_f16)(float16 input, void *fpstp)
 +uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
  {
      float_status *fpst = fpstp;
      float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
      return extract64(estimate, 0, 8) << 44;
  }
 -float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
 +uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
  {
      float_status *s = fpstp;
      float16 f16 = float16_squash_input_denormal(input, s);
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
+[Qemu-devel] [PULL 03/10] target/arm: Introduce read_sys_reg32 for kvm32
-From: Francisco Iglesias <frasse.iglesias@gmail.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Coverity found that the string return by 'object_get_canonical_path' was not
+Assert that the value to be written is the correct size.
-being freed at two locations in the model (CID 1391294 and CID 1391293) and
+No change in functionality here, just mirroring the same
-also that a memset was being called with a value greater than the max of a byte
+function from kvm64.
 on the second argument (CID 1391286). This patch corrects this by adding the
 freeing of the strings and also changing to memset to zero instead on
 descriptor unaligned errors.
-Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Message-id: 20181113180154.17903-4-richard.henderson@linaro.org
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/dma/xlnx-zdma.c | 10 +++++++---
+ target/arm/kvm32.c | 41 ++++++++++++++++-------------------------
-file changed, 7 insertions(+), 3 deletions(-)
+file changed, 16 insertions(+), 25 deletions(-)
-diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
+diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/dma/xlnx-zdma.c
+--- a/target/arm/kvm32.c
-+++ b/hw/dma/xlnx-zdma.c
++++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
+@@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature)
-         qemu_log_mask(LOG_GUEST_ERROR,
+     *features |= 1ULL << feature;
-                       "zdma: unaligned descriptor at %" PRIx64,
+ }
-                       addr);
--        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
++static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
-+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
++{
-         s->error = true;
++    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
 +
 +    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
 +    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
 +}
 +
  bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  {
      /* Identify the feature bits corresponding to the host CPU, and
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
       * we have to create a scratch VM, create a single CPU inside it,
       * and then query that CPU for the relevant ID registers.
       */
 -    int i, ret, fdarray[3];
 +    int err = 0, fdarray[3];
      uint32_t midr, id_pfr0, mvfr1;
      uint64_t features = 0;
 +
      /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
       * we know these will only support creating one kind of guest CPU,
       * which is its preferred CPU type.
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          QEMU_KVM_ARM_TARGET_NONE
      };
      struct kvm_vcpu_init init;
 -    struct kvm_one_reg idregs[] = {
 -        {
 -            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
 -            | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
 -            .addr = (uintptr_t)&midr,
 -        },
 -        {
 -            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
 -            | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
 -            .addr = (uintptr_t)&id_pfr0,
 -        },
 -        {
 -            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
 -            | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
 -            .addr = (uintptr_t)&mvfr1,
 -        },
 -    };
      if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
          return false;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
       */
      ahcf->dtb_compatible = "arm,arm-v7";
 -    for (i = 0; i < ARRAY_SIZE(idregs); i++) {
 -        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
 -        if (ret) {
 -            break;
 -        }
 -    }
 +    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
 +    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
 +    err |= read_sys_reg32(fdarray[2], &mvfr1,
 +                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
 +                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
      kvm_arm_destroy_scratch_host_vcpu(fdarray);
 -    if (ret) {
 +    if (err < 0) {
          return false;
      }
-@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
      RegisterInfo *r = &s->regs_info[addr / 4];
      if (!r->data) {
 +        gchar *path = object_get_canonical_path(OBJECT(s));
          qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
 -                 object_get_canonical_path(OBJECT(s)),
 +                 path,
                   addr);
 +        g_free(path);
          ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
          zdma_ch_imr_update_irq(s);
          return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
      RegisterInfo *r = &s->regs_info[addr / 4];
      if (!r->data) {
 +        gchar *path = object_get_canonical_path(OBJECT(s));
          qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
 -                 object_get_canonical_path(OBJECT(s)),
 +                 path,
                   addr, value);
 +        g_free(path);
          ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
          zdma_ch_imr_update_irq(s);
          return;
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
+[Qemu-devel] [PULL 04/10] target/arm: Fill in ARMISARegisters for kvm32
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-It forgot to increase clroffset during the loop. So it only clear the
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-first 4 bytes.
+Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
 Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gicv3_kvm.c | 1 +
+ target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++-----
-file changed, 1 insertion(+)
+file changed, 35 insertions(+), 5 deletions(-)
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_kvm.c
+--- a/target/arm/kvm32.c
-+++ b/hw/intc/arm_gicv3_kvm.c
++++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
+@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-         if (clroffset != 0) {
+      * and then query that CPU for the relevant ID registers.
-             reg = 0;
+      */
-             kvm_gicd_access(s, clroffset, &reg, true);
+     int err = 0, fdarray[3];
-+            clroffset += 4;
+-    uint32_t midr, id_pfr0, mvfr1;
-         }
++    uint32_t midr, id_pfr0;
-         reg = *gic_bmp_ptr32(bmp, irq);
+     uint64_t features = 0;
-         kvm_gicd_access(s, offset, &reg, true);
      /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
      err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
 -    err |= read_sys_reg32(fdarray[2], &mvfr1,
 +
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
 +                          ARM_CP15_REG32(0, 0, 2, 0));
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
 +                          ARM_CP15_REG32(0, 0, 2, 1));
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
 +                          ARM_CP15_REG32(0, 0, 2, 2));
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
 +                          ARM_CP15_REG32(0, 0, 2, 3));
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
 +                          ARM_CP15_REG32(0, 0, 2, 4));
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
 +                          ARM_CP15_REG32(0, 0, 2, 5));
 +    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
 +                       ARM_CP15_REG32(0, 0, 2, 7))) {
 +        /*
 +         * Older kernels don't support reading ID_ISAR6. This register was
 +         * only introduced in ARMv8, so we can assume that it is zero on a
 +         * CPU that a kernel this old is running on.
 +         */
 +        ahcf->isar.id_isar6 = 0;
 +    }
 +
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
 +                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
 +                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
 +    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
                            KVM_REG_ARM | KVM_REG_SIZE_U32 |
                            KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 +    /*
 +     * FIXME: There is not yet a way to read MVFR2.
 +     * Fortunately there is not yet anything in there that affects migration.
 +     */
      kvm_arm_destroy_scratch_host_vcpu(fdarray);
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      if (extract32(id_pfr0, 12, 4) == 1) {
          set_feature(&features, ARM_FEATURE_THUMB2EE);
      }
 -    if (extract32(mvfr1, 20, 4) == 1) {
 +    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
          set_feature(&features, ARM_FEATURE_VFP_FP16);
      }
 -    if (extract32(mvfr1, 12, 4) == 1) {
 +    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
          set_feature(&features, ARM_FEATURE_NEON);
      }
 -    if (extract32(mvfr1, 28, 4) == 1) {
 +    if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
          /* FMAC support implies VFPv4 */
          set_feature(&features, ARM_FEATURE_VFP4);
      }
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
+[Qemu-devel] [PULL 05/10] MAINTAINERS: Add entries for missing ARM boards
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Thomas Huth <thuth@redhat.com>
-kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
+Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2",
-initialize global capability variables. If we call kvm_init_irq_routing in
+"raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt".
-GIC realize function, previous allocated memory will leak.
+While we're at it, also adjust the "i.MX31" section a little bit,
 so that the wildcards there do not match anymore for unrelated files
 (e.g. the new hw/misc/imx6ul_ccm.c file).
-Fix this by deleting the unnecessary call.
+Signed-off-by: Thomas Huth <thuth@redhat.com>
+Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com
 Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
 Reviewed-by: Eric Auger <eric.auger@redhat.com>
 Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/arm_gic_kvm.c   | 1 -
+ MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++----
- hw/intc/arm_gicv3_kvm.c | 1 -
+file changed, 65 insertions(+), 5 deletions(-)
 files changed, 2 deletions(-)
-diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gic_kvm.c
+--- a/MAINTAINERS
-+++ b/hw/intc/arm_gic_kvm.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
+ S: Odd Fixes
-     if (kvm_has_gsi_routing()) {
+ F: hw/arm/gumstix.c
-         /* set up irq routing */
--        kvm_init_irq_routing(kvm_state);
+-i.MX31
-         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
++i.MX31 (kzm)
-             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
+ M: Peter Chubb <peter.chubb@nicta.com.au>
-         }
+ L: qemu-arm@nongnu.org
-diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
+-S: Odd fixes
-index XXXXXXX..XXXXXXX 100644
+-F: hw/*/imx*
---- a/hw/intc/arm_gicv3_kvm.c
+-F: include/hw/*/imx*
-+++ b/hw/intc/arm_gicv3_kvm.c
++S: Odd Fixes
-@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
+ F: hw/arm/kzm.c
+-F: include/hw/arm/fsl-imx31.h
-     if (kvm_has_gsi_routing()) {
++F: hw/*/imx_*
-         /* set up irq routing */
++F: hw/*/*imx31*
--        kvm_init_irq_routing(kvm_state);
++F: include/hw/*/imx_*
-         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
++F: include/hw/*/*imx31*
-             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
-         }
+ Integrator CP
  M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ S: Maintained
  F: hw/arm/integratorcp.c
  F: hw/misc/arm_integrator_debug.c
 +MCIMX6UL EVK / i.MX6ul
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Jean-Christophe Dubois <jcd@tribudubois.net>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/mcimx6ul-evk.c
 +F: hw/arm/fsl-imx6ul.c
 +F: hw/misc/imx6ul_ccm.c
 +F: include/hw/arm/fsl-imx6ul.h
 +F: include/hw/misc/imx6ul_ccm.h
 +
 +MCIMX7D SABRE / i.MX7
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Andrey Smirnov <andrew.smirnov@gmail.com>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/mcimx7d-sabre.c
 +F: hw/arm/fsl-imx7.c
 +F: include/hw/arm/fsl-imx7.h
 +F: hw/pci-host/designware.c
 +F: include/hw/pci-host/designware.h
 +
  MPS2
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/arm/palm.c
 +Raspberry Pi
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Andrew Baumann <Andrew.Baumann@microsoft.com>
 +R: Philippe Mathieu-Daudé <f4bug@amsat.org>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/raspi_platform.h
 +F: hw/*/bcm283*
 +F: include/hw/arm/raspi*
 +F: include/hw/*/bcm283*
 +
  Real View
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx*
  F: hw/misc/mst_fpga.c
  F: include/hw/arm/pxa.h
 +SABRELITE / i.MX6
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Jean-Christophe Dubois <jcd@tribudubois.net>
 +L: qemu-arm@nongnu.org
 +S: Odd Fixes
 +F: hw/arm/sabrelite.c
 +F: hw/arm/fsl-imx6.c
 +F: hw/misc/imx6_src.c
 +F: hw/ssi/imx_spi.c
 +F: include/hw/arm/fsl-imx6.h
 +F: include/hw/misc/imx6_src.h
 +F: include/hw/ssi/imx_spi.h
 +
  Sharp SL-5500 (Collie) PDA
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/*/stellaris*
 +Versatile Express
 +M: Peter Maydell <peter.maydell@linaro.org>
 +L: qemu-arm@nongnu.org
 +S: Maintained
 +F: hw/arm/vexpress.c
 +
  Versatile PB
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ S: Maintained
  F: hw/*/versatile*
  F: hw/misc/arm_sysctl.c
 +Virt
 +M: Peter Maydell <peter.maydell@linaro.org>
 +L: qemu-arm@nongnu.org
 +S: Maintained
 +F: hw/arm/virt*
 +F: include/hw/arm/virt.h
 +
  Xilinx Zynq
  M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
  M: Alistair Francis <alistair@alistair23.me>
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
+[Qemu-devel] [PULL 06/10] hw/arm/stm32f205: Fix the UART and Timer region size
-From: Shannon Zhao <zhaoshenglong@huawei.com>
+From: Seth Kintigh <skintigh@gmail.com>
-acpi_data_push uses g_array_set_size to resize the memory size. If there
+The UART and timer devices for the stm32f205 were being created
-is no enough contiguous memory, the address will be changed. So previous
+with memory regions that were too large. Use the size specified
-pointer could not be used any more. It must update the pointer and use
+in the chip datasheet.
 the new one.
-Also, previous codes wrongly use le32 conversion of iort->node_offset
+The old sizes were so large that the devices would overlap with
-for subsequent computations that will result incorrect value if host is
+each other in the SoC memory map, so this fixes a bug that
-not litlle endian. So use the non-converted one instead.
+caused odd behavior and/or crashes when trying to set up multiple
 UARTs.
-Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
+Signed-off-by: Seth Kintigh <skintigh@gmail.com>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
+[PMM: rephrased commit message to follow our usual standard]
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
+ hw/char/stm32f2xx_usart.c  | 2 +-
-file changed, 15 insertions(+), 5 deletions(-)
+ hw/timer/stm32f2xx_timer.c | 2 +-
 files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
+diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt-acpi-build.c
+--- a/hw/char/stm32f2xx_usart.c
-+++ b/hw/arm/virt-acpi-build.c
++++ b/hw/char/stm32f2xx_usart.c
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj)
-     AcpiIortItsGroup *its;
+     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-     AcpiIortTable *iort;
-     AcpiIortSmmu3 *smmu;
+     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
--    size_t node_size, iort_length, smmu_offset = 0;
+-                          TYPE_STM32F2XX_USART, 0x2000);
-+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
++                          TYPE_STM32F2XX_USART, 0x400);
-     AcpiIortRC *rc;
+     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+ }
-     iort = acpi_data_push(table_data, sizeof(*iort));
-@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
+diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
+index XXXXXXX..XXXXXXX 100644
-     iort_length = sizeof(*iort);
+--- a/hw/timer/stm32f2xx_timer.c
-     iort->node_count = cpu_to_le32(nb_nodes);
++++ b/hw/timer/stm32f2xx_timer.c
--    iort->node_offset = cpu_to_le32(sizeof(*iort));
+@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj)
-+    /*
+     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
-+     * Use a copy in case table_data->data moves during acpi_data_push
-+     * operations.
+     memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
-+     */
+-                          "stm32f2xx_timer", 0x4000);
-+    iort_node_offset = sizeof(*iort);
++                          "stm32f2xx_timer", 0x400);
-+    iort->node_offset = cpu_to_le32(iort_node_offset);
+     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
-     /* ITS group node */
+     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
      node_size =  sizeof(*its) + sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          int irq =  vms->irqmap[VIRT_SMMU];
          /* SMMUv3 node */
 -        smmu_offset = iort->node_offset + node_size;
 +        smmu_offset = iort_node_offset + node_size;
          node_size = sizeof(*smmu) + sizeof(*idmap);
          iort_length += node_size;
          smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          idmap->id_count = cpu_to_le32(0xFFFF);
          idmap->output_base = 0;
          /* output IORT node is the ITS group node (the first node) */
 -        idmap->output_reference = cpu_to_le32(iort->node_offset);
 +        idmap->output_reference = cpu_to_le32(iort_node_offset);
      }
      /* Root Complex Node */
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
          idmap->output_reference = cpu_to_le32(smmu_offset);
      } else {
          /* output IORT node is the ITS group node (the first node) */
 -        idmap->output_reference = cpu_to_le32(iort->node_offset);
 +        idmap->output_reference = cpu_to_le32(iort_node_offset);
      }
 +    /*
 +     * Update the pointer address in case table_data->data moves during above
 +     * acpi_data_push operations.
 +     */
 +    iort = (AcpiIortTable *)(table_data->data + iort_start);
      iort->length = cpu_to_le32(iort_length);
      build_header(linker, table_data, (void *)(table_data->data + iort_start),
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
+[Qemu-devel] [PULL 07/10] target/arm: fix smc incorrectly trapping to EL3 when secure is off
-From: Igor Mammedov <imammedo@redhat.com>
+From: Luc Michel <luc.michel@greensocs.com>
-When QEMU is started with following CLI
+This commit fixes a case where the CPU would try to go to EL3 when
- -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
+executing an smc instruction, even though ARM_FEATURE_EL3 is false. This
-it crashes with abort at
+case is raised when the PSCI conduit is set to smc, but the smc
- accel/kvm/kvm-all.c:2164:
+instruction does not lead to a valid PSCI call.
  KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
-Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
+QEMU crashes with an assertion failure latter on because of incoherent
-arm_gicv3_icc_reset() where the later is called by CPU reset
+mmu_idx.
 reset callback.
-However commit:
+This commit refactors the pre_smc helper by enumerating all the possible
-b77f6c arm/boot: split load_dtb() from arm_load_kernel()
+way of handling an scm instruction, and covering the previously missing
-broke CPU reset callback registration in case
+case leading to the crash.
-  arm_load_kernel()
+The following minimal test would crash before this commit:
       ...
       if (!info->kernel_filename || info->firmware_loaded)
-branch is taken, i.e. it's sufficient to provide a firmware
+.global _start
-or do not provide kernel on CLI to skip cpu reset callback
+    .text
-registration, where before offending commit the callback
+_start:
-has been registered unconditionally.
+    ldr x0, =0xdeadbeef  ; invalid PSCI call
     smc #0
-Fix it by registering the callback right at the beginning of
+run with the following command line:
 arm_load_kernel() unconditionally instead of doing it at the end.
-NOTE:
+aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \
- we probably should eliminate that dependency anyways as well as
+                      -o test test.s
  separate arch CPU reset parts from arm_load_kernel() into CPU
  itself, but that refactoring that I probably would have to do
  anyways later for CPU hotplug to work.
-Reported-by: Auger Eric <eric.auger@redhat.com>
+qemu-system-aarch64 -M virt,virtualization=on,secure=off \
-Signed-off-by: Igor Mammedov <imammedo@redhat.com>
+                    -cpu cortex-a57 -kernel test
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Tested-by: Eric Auger <eric.auger@redhat.com>
+Signed-off-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
+Message-id: 20181117160213.18995-1-luc.michel@greensocs.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/boot.c | 18 +++++++++---------
+ target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++-------
-file changed, 9 insertions(+), 9 deletions(-)
+file changed, 46 insertions(+), 8 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/target/arm/op_helper.c
-+++ b/hw/arm/boot.c
++++ b/target/arm/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
-     static const ARMInsnFixup *primary_loader;
+     ARMCPU *cpu = arm_env_get_cpu(env);
-     AddressSpace *as = arm_boot_address_space(cpu, info);
+     int cur_el = arm_current_el(env);
+     bool secure = arm_is_secure(env);
-+    /* CPU objects (unlike devices) are not automatically reset on system
+-    bool smd = env->cp15.scr_el3 & SCR_SMD;
-+     * reset, so we must always register a handler to do so. If we're
++    bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
-+     * actually loading a kernel, the handler is also responsible for
++
-+     * arranging that we start it correctly.
++    /*
 +     * SMC behaviour is summarized in the following table.
 +     * This helper handles the "Trap to EL2" and "Undef insn" cases.
 +     * The "Trap to EL3" and "PSCI call" cases are handled in the exception
 +     * helper.
 +     *
 +     *  -> ARM_FEATURE_EL3 and !SMD
 +     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
 +     *
 +     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
 +     *  Conduit SMC, inval call  Trap to EL2         Trap to EL3
 +     *  Conduit not SMC          Trap to EL2         Trap to EL3
 +     *
 +     *
 +     *  -> ARM_FEATURE_EL3 and SMD
 +     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
 +     *
 +     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
 +     *  Conduit SMC, inval call  Trap to EL2         Undef insn
 +     *  Conduit not SMC          Trap to EL2         Undef insn
 +     *
 +     *
 +     *  -> !ARM_FEATURE_EL3
 +     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
 +     *
 +     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
 +     *  Conduit SMC, inval call  Trap to EL2         Undef insn
 +     *  Conduit not SMC          Undef insn          Undef insn
 +     */
-+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
++
-+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
       * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
       *  extensions, SMD only applies to NS state.
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
       * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
       * so we need not special case this here.
       */
 -    bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
 +    bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag
 +                                                     : smd_flag && !secure;
      if (!arm_feature(env, ARM_FEATURE_EL3) &&
          cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
           * to forbid its EL1 from making PSCI calls into QEMU's
           * "firmware" via HCR.TSC, so for these purposes treat
           * PSCI-via-SMC as implying an EL3.
 +         * This handles the very last line of the previous table.
           */
 -        undef = true;
 -    } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
 +        raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 +                        exception_target_el(env));
 +    }
 +
-     /* The board code is not supposed to set secure_board_setup unless
++    if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
-      * running its code in secure mode is actually possible, and KVM
+         /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
-      * doesn't support secure.
+          * We also want an EL2 guest to be able to forbid its EL1 from
-@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
+          * making PSCI calls into QEMU's "firmware" via HCR.TSC.
-         ARM_CPU(cs)->env.boot_info = info;
++         * This handles all the "Trap to EL2" cases of the previous table.
           */
          raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
      }
--    /* CPU objects (unlike devices) are not automatically reset on system
+-    /* If PSCI is enabled and this looks like a valid PSCI call then
--     * reset, so we must always register a handler to do so. If we're
+-     * suppress the UNDEF -- we'll catch the SMC exception and
--     * actually loading a kernel, the handler is also responsible for
+-     * implement the PSCI call behaviour there.
--     * arranging that we start it correctly.
++    /* Catch the two remaining "Undef insn" cases of the previous table:
--     */
++     *    - PSCI conduit is SMC but we don't have a valid PCSI call,
--    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
++     *    - We don't have EL3 or SMD is set.
--        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+      */
--    }
+-    if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) {
--
++    if (!arm_is_psci_call(cpu, EXCP_SMC) &&
-     if (!info->skip_dtb_autoload && have_dtb(info)) {
++        (smd || !arm_feature(env, ARM_FEATURE_EL3))) {
-         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
+         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
-             exit(1);
+                         exception_target_el(env));
      }
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
+[Qemu-devel] [PULL 08/10] hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
-From: Paolo Bonzini <pbonzini@redhat.com>
+An off-by-one error in a switch case in onenand_read() allowed
 a misbehaving guest to read off the end of a block of memory.
-cpregs_keys is an uint32_t* so the allocation should use uint32_t.
+NB: the onenand device is used only by the "n800" and "n810"
-g_new is even better because it is type-safe.
+machines, which are usable only with TCG, not KVM, so this is
 not a security issue.
-Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
+Reported-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20181115143535.5885-2-peter.maydell@linaro.org
 Suggested-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/gdbstub.c | 3 +--
+ hw/block/onenand.c | 2 +-
-file changed, 1 insertion(+), 2 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
+diff --git a/hw/block/onenand.c b/hw/block/onenand.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/gdbstub.c
+--- a/hw/block/onenand.c
-+++ b/target/arm/gdbstub.c
++++ b/hw/block/onenand.c
-@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
-     RegisterSysregXmlParam param = {cs, s};
+     int offset = addr >> s->shift;
-     cpu->dyn_xml.num_cpregs = 0;
+     switch (offset) {
--    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
+-    case 0x0000 ... 0xc000:
--                                        g_hash_table_size(cpu->cp_regs));
++    case 0x0000 ... 0xbffe:
-+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
+         return lduw_le_p(s->boot[0] + addr);
-     g_string_printf(s, "<?xml version=\"1.0\"?>");
-     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+     case 0xf000:    /* Manufacturer ID */
      g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
+[Qemu-devel] [PULL 09/10] hw/block/onenand: use qemu_log_mask() for reporting
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
+Update the onenand device to use qemu_log_mask() for reporting
-add MemTxAttrs as an argument to flatview_access_valid().
+guest errors and unimplemented features, rather than plain
-Its callers now all have an attrs value to hand, so we can
+fprintf() and hw_error().
-correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
 (We leave the hw_error() in onenand_reset(), as that is
 triggered by a failure to read the underlying block device
 for the bootRAM, not by guest action.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
+Reviewed-by: Thomas Huth <thuth@redhat.com>
 Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20181115143535.5885-3-peter.maydell@linaro.org
 ---
- exec.c | 12 +++++-------
+ hw/block/onenand.c | 22 +++++++++++++---------
-file changed, 5 insertions(+), 7 deletions(-)
+file changed, 13 insertions(+), 9 deletions(-)
-diff --git a/exec.c b/exec.c
+diff --git a/hw/block/onenand.c b/hw/block/onenand.c
 index XXXXXXX..XXXXXXX 100644
---- a/exec.c
+--- a/hw/block/onenand.c
-+++ b/exec.c
++++ b/hw/block/onenand.c
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
+@@ -XXX,XX +XXX,XX @@
- static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
+ #include "exec/memory.h"
-                                   const uint8_t *buf, int len);
+ #include "hw/sysbus.h"
- static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
+ #include "qemu/error-report.h"
--                                  bool is_write);
++#include "qemu/log.h"
-+                                  bool is_write, MemTxAttrs attrs);
+ /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
- static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
+ #define PAGE_SHIFT    11
-                                 unsigned len, MemTxAttrs attrs)
+@@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s)
-@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
+     default:
- #endif
+         s->status |= ONEN_ERR_CMD;
+         s->intstatus |= ONEN_INT;
-     return flatview_access_valid(subpage->fv, addr + subpage->base,
+-        fprintf(stderr, "%s: unknown OneNAND command %x\n",
--                                 len, is_write);
+-                        __func__, s->command);
-+                                 len, is_write, attrs);
++        qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
 +                      s->command);
      }
      onenand_intr_update(s);
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
      case 0xff02:    /* ECC Result of spare area data */
      case 0xff03:    /* ECC Result of main area data */
      case 0xff04:    /* ECC Result of spare area data */
 -        hw_error("%s: implement ECC\n", __func__);
 +        qemu_log_mask(LOG_UNIMP,
 +                      "onenand: ECC result registers unimplemented\n");
          return 0x0000;
      }
 -    fprintf(stderr, "%s: unknown OneNAND register %x\n",
 -                    __func__, offset);
 +    qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n",
 +                  offset);
      return 0;
  }
- static const MemoryRegionOps subpage_ops = {
+@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
-@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
+             break;
          default:
 -            fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
 -                            __func__, value);
 +            qemu_log_mask(LOG_GUEST_ERROR,
 +                          "unknown OneNAND boot command %" PRIx64 "\n",
 +                          value);
          }
          break;
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
          break;
      default:
 -        fprintf(stderr, "%s: unknown OneNAND register %x\n",
 -                        __func__, offset);
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "write to unknown OneNAND register 0x%x\n",
 +                      offset);
      }
  }
- static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
--                                  bool is_write)
-+                                  bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegion *mr;
-     hwaddr l, xlat;
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
--            /* When our callers all have attrs we'll pass them through here */
--            if (!memory_region_access_valid(mr, xlat, l, is_write,
--                                            MEMTXATTRS_UNSPECIFIED)) {
-+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
-                 return false;
-             }
-         }
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-     rcu_read_lock();
-     fv = address_space_to_flatview(as);
--    result = flatview_access_valid(fv, addr, len, is_write);
-+    result = flatview_access_valid(fv, addr, len, is_write, attrs);
-     rcu_read_unlock();
-     return result;
- }
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
+[Qemu-devel] [PULL 10/10] MAINTAINERS: list myself as maintainer for various Arm boards
-Add entries to MAINTAINERS to cover the newer MPS2 boards and
+In practice for most of the more-or-less orphan Arm board models,
-the new devices they use.
+I will review patches and put them in via the target-arm tree.
 So list myself as an "Odd Fixes" status maintainer for them.
 This commit downgrades these boards to "Odd Fixes":
  * Allwinner-A10
  * Exynos
  * Calxeda Highbank
  * Canon DIGIC
  * Musicpal
  * nSeries
  * Palm
  * PXA2xx
 These boards were already "Odd Fixes":
  * Gumstix
  * i.MX31 (kzm)
 Philippe Mathieu-Daudé has requested to be moved to R:
 status for Gumstix now that I am listed as the M: contact.
 Some boards are maintained, but their patches still go
 via the target-arm tree, so add myself as a secondary
 maintainer contact for those:
  * Xilinx Zynq
  * Xilinx ZynqMP
  * STM32F205
  * Netduino 2
  * SmartFusion2
  * Mecraft M2S-FG484
  * ASPEED BMCs
  * NRF51
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Thomas Huth <thuth@redhat.com>
 Message-id: 20181108134139.31666-1-peter.maydell@linaro.org
 ---
- MAINTAINERS | 9 +++++++--
+ MAINTAINERS | 36 +++++++++++++++++++++++++++---------
-file changed, 7 insertions(+), 2 deletions(-)
+file changed, 27 insertions(+), 9 deletions(-)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
+@@ -XXX,XX +XXX,XX @@ ARM Machines
- F: include/hw/timer/cmsdk-apb-timer.h
+ ------------
- F: hw/char/cmsdk-apb-uart.c
+ Allwinner-a10
- F: include/hw/char/cmsdk-apb-uart.h
+ M: Beniamino Galvani <b.galvani@gmail.com>
-+F: hw/misc/tz-ppc.c
++M: Peter Maydell <peter.maydell@linaro.org>
-+F: include/hw/misc/tz-ppc.h
+ L: qemu-arm@nongnu.org
+-S: Maintained
- ARM cores
++S: Odd Fixes
- M: Peter Maydell <peter.maydell@linaro.org>
+ F: hw/*/allwinner*
-@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
+ F: include/hw/*/allwinner*
- L: qemu-arm@nongnu.org
+ F: hw/arm/cubieboard.c
- S: Maintained
+@@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c
- F: hw/arm/mps2.c
--F: hw/misc/mps2-scc.c
+ Exynos
--F: include/hw/misc/mps2-scc.h
+ M: Igor Mitsyanko <i.mitsyanko@gmail.com>
-+F: hw/arm/mps2-tz.c
++M: Peter Maydell <peter.maydell@linaro.org>
-+F: hw/misc/mps2-*.c
+ L: qemu-arm@nongnu.org
-+F: include/hw/misc/mps2-*.h
+-S: Maintained
-+F: hw/arm/iotkit.c
++S: Odd Fixes
-+F: include/hw/arm/iotkit.h
+ F: hw/*/exynos*
  F: include/hw/arm/exynos4210.h
  Calxeda Highbank
  M: Rob Herring <robh@kernel.org>
 +M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
 -S: Maintained
 +S: Odd Fixes
  F: hw/arm/highbank.c
  F: hw/net/xgmac.c
  Canon DIGIC
  M: Antony Pavlov <antonynpavlov@gmail.com>
 +M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
 -S: Maintained
 +S: Odd Fixes
  F: include/hw/arm/digic.h
  F: hw/*/digic*
  Gumstix
 -M: Philippe Mathieu-Daudé <f4bug@amsat.org>
 +M: Peter Maydell <peter.maydell@linaro.org>
 +R: Philippe Mathieu-Daudé <f4bug@amsat.org>
  L: qemu-devel@nongnu.org
  L: qemu-arm@nongnu.org
  S: Odd Fixes
@@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c
  i.MX31 (kzm)
  M: Peter Chubb <peter.chubb@nicta.com.au>
 +M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
  S: Odd Fixes
  F: hw/arm/kzm.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h
  Musicpal
  M: Jan Kiszka <jan.kiszka@web.de>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+-S: Maintained
++S: Odd Fixes
+ F: hw/arm/musicpal.c
+ nSeries
+ M: Andrzej Zaborowski <balrogg@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+-S: Maintained
++S: Odd Fixes
+ F: hw/arm/nseries.c
+ Palm
+ M: Andrzej Zaborowski <balrogg@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+-S: Maintained
++S: Odd Fixes
+ F: hw/arm/palm.c
+ Raspberry Pi
+@@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h
+ PXA2XX
+ M: Andrzej Zaborowski <balrogg@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+-S: Maintained
++S: Odd Fixes
+ F: hw/arm/mainstone.c
+ F: hw/arm/spitz.c
+ F: hw/arm/tosa.c
+@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h
+ Xilinx Zynq
+ M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+ M: Alistair Francis <alistair@alistair23.me>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+ S: Maintained
+ F: hw/*/xilinx_*
+@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
+ Xilinx ZynqMP
+ M: Alistair Francis <alistair@alistair23.me>
+ M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+ S: Maintained
+ F: hw/*/xlnx*.c
+@@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c
+ STM32F205
+ M: Alistair Francis <alistair@alistair23.me>
++M: Peter Maydell <peter.maydell@linaro.org>
+ S: Maintained
+ F: hw/arm/stm32f205_soc.c
+ F: hw/misc/stm32f2xx_syscfg.c
+@@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h
+ Netduino 2
+ M: Alistair Francis <alistair@alistair23.me>
++M: Peter Maydell <peter.maydell@linaro.org>
+ S: Maintained
+ F: hw/arm/netduino2.c
+ SmartFusion2
+ M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
+ S: Maintained
+ F: hw/arm/msf2-soc.c
+ F: hw/misc/msf2-sysreg.c
+@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h
+ Emcraft M2S-FG484
+ M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
++M: Peter Maydell <peter.maydell@linaro.org>
+ S: Maintained
+ F: hw/arm/msf2-som.c
+ ASPEED BMCs
+ M: Cédric Le Goater <clg@kaod.org>
++M: Peter Maydell <peter.maydell@linaro.org>
+ R: Andrew Jeffery <andrew@aj.id.au>
+ R: Joel Stanley <joel@jms.id.au>
+ L: qemu-arm@nongnu.org
+@@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h
+ NRF51
+ M: Joel Stanley <joel@jms.id.au>
++M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+ S: Maintained
+ F: hw/arm/nrf51_soc.c
 --
-.17.1
+.19.1

-[Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
+Deleted patch
-In commit f0aff255700 we made cpacr_write() enforce that some CPACR
-bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
-we forgot to also update the register's reset value. The effect
-was that (a) a guest that read CPACR on reset would not see ones in
-the RAO bits, and (b) if you did a migration before the guest did
-a write to the CPACR then the migration would fail because the
-destination would enforce the RAO bits and then complain that they
-didn't match the zero value from the source.
-Implement reset for the CPACR using a custom reset function
-that just calls cpacr_write(), to avoid having to duplicate
-the logic for which bits are RAO.
-This bug would affect migration for TCG CPUs which are ARMv7
-with VFP but without one of Neon or VFPv3.
-Reported-by: Cédric Le Goater <clg@kaod.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Tested-by: Cédric Le Goater <clg@kaod.org>
-Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
----
- target/arm/helper.c | 10 +++++++++-
-file changed, 9 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     env->cp15.cpacr_el1 = value;
- }
-+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
-+{
-+    /* Call cpacr_write() so that we reset with the correct RAO bits set
-+     * for our CPU features.
-+     */
-+    cpacr_write(env, ri, 0);
-+}
-+
- static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
-                                    bool isread)
- {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
-     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
-       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
-       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
--      .resetvalue = 0, .writefn = cpacr_write },
-+      .resetfn = cpacr_reset, .writefn = cpacr_write },
-     REGINFO_SENTINEL
- };
---
-.17.1

-[Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
+Deleted patch
-Add more detail to the documentation for memory_region_init_iommu()
-and other IOMMU-related functions and data structures.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Eric Auger <eric.auger@redhat.com>
-Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
----
- include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
-file changed, 95 insertions(+), 10 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
-     IOMMU_ATTR_SPAPR_TCE_FD
- };
-+/**
-+ * IOMMUMemoryRegionClass:
-+ *
-+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
-+ * and provide an implementation of at least the @translate method here
-+ * to handle requests to the memory region. Other methods are optional.
-+ *
-+ * The IOMMU implementation must use the IOMMU notifier infrastructure
-+ * to report whenever mappings are changed, by calling
-+ * memory_region_notify_iommu() (or, if necessary, by calling
-+ * memory_region_notify_one() for each registered notifier).
-+ */
- typedef struct IOMMUMemoryRegionClass {
-     /* private */
-     struct DeviceClass parent_class;
-     /*
--     * Return a TLB entry that contains a given address. Flag should
--     * be the access permission of this translation operation. We can
--     * set flag to IOMMU_NONE to mean that we don't need any
--     * read/write permission checks, like, when for region replay.
-+     * Return a TLB entry that contains a given address.
-+     *
-+     * The IOMMUAccessFlags indicated via @flag are optional and may
-+     * be specified as IOMMU_NONE to indicate that the caller needs
-+     * the full translation information for both reads and writes. If
-+     * the access flags are specified then the IOMMU implementation
-+     * may use this as an optimization, to stop doing a page table
-+     * walk as soon as it knows that the requested permissions are not
-+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
-+     * full page table walk and report the permissions in the returned
-+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
-+     * return different mappings for reads and writes.)
-+     *
-+     * The returned information remains valid while the caller is
-+     * holding the big QEMU lock or is inside an RCU critical section;
-+     * if the caller wishes to cache the mapping beyond that it must
-+     * register an IOMMU notifier so it can invalidate its cached
-+     * information when the IOMMU mapping changes.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @hwaddr: address to be translated within the memory region
-+     * @flag: requested access permissions
-      */
-     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
-                                IOMMUAccessFlags flag);
--    /* Returns minimum supported page size */
-+    /* Returns minimum supported page size in bytes.
-+     * If this method is not provided then the minimum is assumed to
-+     * be TARGET_PAGE_SIZE.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     */
-     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
--    /* Called when IOMMU Notifier flag changed */
-+    /* Called when IOMMU Notifier flag changes (ie when the set of
-+     * events which IOMMU users are requesting notification for changes).
-+     * Optional method -- need not be provided if the IOMMU does not
-+     * need to know exactly which events must be notified.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @old_flags: events which previously needed to be notified
-+     * @new_flags: events which now need to be notified
-+     */
-     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
-                                 IOMMUNotifierFlag old_flags,
-                                 IOMMUNotifierFlag new_flags);
--    /* Set this up to provide customized IOMMU replay function */
-+    /* Called to handle memory_region_iommu_replay().
-+     *
-+     * The default implementation of memory_region_iommu_replay() is to
-+     * call the IOMMU translate method for every page in the address space
-+     * with flag == IOMMU_NONE and then call the notifier if translate
-+     * returns a valid mapping. If this method is implemented then it
-+     * overrides the default behaviour, and must provide the full semantics
-+     * of memory_region_iommu_replay(), by calling @notifier for every
-+     * translation present in the IOMMU.
-+     *
-+     * Optional method -- an IOMMU only needs to provide this method
-+     * if the default is inefficient or produces undesirable side effects.
-+     *
-+     * Note: this is not related to record-and-replay functionality.
-+     */
-     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
--    /* Get IOMMU misc attributes */
--    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
-+    /* Get IOMMU misc attributes. This is an optional method that
-+     * can be used to allow users of the IOMMU to get implementation-specific
-+     * information. The IOMMU implements this method to handle calls
-+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
-+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
-+     * the IOMMU supports. If the method is unimplemented then
-+     * memory_region_iommu_get_attr() will always return -EINVAL.
-+     *
-+     * @iommu: the IOMMUMemoryRegion
-+     * @attr: attribute being queried
-+     * @data: memory to fill in with the attribute data
-+     *
-+     * Returns 0 on success, or a negative errno; in particular
-+     * returns -EINVAL for unrecognized or unimplemented attribute types.
-+     */
-+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
-                     void *data);
- } IOMMUMemoryRegionClass;
-@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
-  * An IOMMU region translates addresses and forwards accesses to a target
-  * memory region.
-  *
-+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
-+ * @_iommu_mr should be a pointer to enough memory for an instance of
-+ * that subclass, @instance_size is the size of that subclass, and
-+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
-+ * instance of the subclass, and its methods will then be called to handle
-+ * accesses to the memory region. See the documentation of
-+ * #IOMMUMemoryRegionClass for further details.
-+ *
-  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
-  * @instance_size: the IOMMUMemoryRegion subclass instance size
-  * @mrtypename: the type name of the #IOMMUMemoryRegion
-@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
-  * a notifier with the minimum page granularity returned by
-  * mr->iommu_ops->get_page_size().
-  *
-+ * Note: this is not related to record-and-replay functionality.
-+ *
-  * @iommu_mr: the memory region to observe
-  * @n: the notifier to which to replay iommu mappings
-  */
-@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
-  * memory_region_iommu_replay_all: replay existing IOMMU translations
-  * to all the notifiers registered.
-  *
-+ * Note: this is not related to record-and-replay functionality.
-+ *
-  * @iommu_mr: the memory region to observe
-  */
- void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
-@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
-  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
-  * defined on the IOMMU.
-  *
-- * Returns 0 if succeded, error code otherwise.
-+ * Returns 0 on success, or a negative errno otherwise. In particular,
-+ * -EINVAL indicates that the IOMMU does not support the requested
-+ * attribute.
-  *
-  * @iommu_mr: the memory region
-  * @attr: the requested attribute
---
-.17.1

-[Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to tb_invalidate_phys_addr().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
----
- include/exec/exec-all.h   | 5 +++--
- accel/tcg/translate-all.c | 2 +-
- exec.c                    | 2 +-
- target/xtensa/op_helper.c | 3 ++-
-files changed, 7 insertions(+), 5 deletions(-)
-diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/exec-all.h
-+++ b/include/exec/exec-all.h
-@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
- void tlb_set_page(CPUState *cpu, target_ulong vaddr,
-                   hwaddr paddr, int prot,
-                   int mmu_idx, target_ulong size);
--void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
-+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
- void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
-                  uintptr_t retaddr);
- #else
-@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
-                                                        uint16_t idxmap)
- {
- }
--static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
-+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
-+                                           MemTxAttrs attrs)
- {
- }
- #endif
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
- }
- #if !defined(CONFIG_USER_ONLY)
--void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
-+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
- {
-     ram_addr_t ram_addr;
-     MemoryRegion *mr;
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
-     if (phys != -1) {
-         /* Locks grabbed by tb_invalidate_phys_addr */
-         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
--                                phys | (pc & ~TARGET_PAGE_MASK));
-+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
-     }
- }
- #endif
-diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/xtensa/op_helper.c
-+++ b/target/xtensa/op_helper.c
-@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
-     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
-             &paddr, &page_size, &access);
-     if (ret == 0) {
--        tb_invalidate_phys_addr(&address_space_memory, paddr);
-+        tb_invalidate_phys_addr(&address_space_memory, paddr,
-+                                MEMTXATTRS_UNSPECIFIED);
-     }
- }
---
-.17.1

-[Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_translate()
-and address_space_translate_cached(). Callers either have an
-attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
----
- include/exec/memory.h     |  4 +++-
- accel/tcg/translate-all.c |  2 +-
- exec.c                    | 14 +++++++++-----
- hw/vfio/common.c          |  3 ++-
- memory_ldst.inc.c         | 18 +++++++++---------
- target/riscv/helper.c     |  2 +-
-files changed, 25 insertions(+), 18 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-  * #MemoryRegion.
-  * @len: pointer to length
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
- MemoryRegion *flatview_translate(FlatView *fv,
-                                  hwaddr addr, hwaddr *xlat,
-@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
- static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     hwaddr addr, hwaddr *xlat,
--                                                    hwaddr *len, bool is_write)
-+                                                    hwaddr *len, bool is_write,
-+                                                    MemTxAttrs attrs)
- {
-     return flatview_translate(address_space_to_flatview(as),
-                               addr, xlat, len, is_write);
-diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
-index XXXXXXX..XXXXXXX 100644
---- a/accel/tcg/translate-all.c
-+++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
-     hwaddr l = 1;
-     rcu_read_lock();
--    mr = address_space_translate(as, addr, &addr, &l, false);
-+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
-     if (!(memory_region_is_ram(mr)
-           || memory_region_is_romd(mr))) {
-         rcu_read_unlock();
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
-     rcu_read_lock();
-     while (len > 0) {
-         l = len;
--        mr = address_space_translate(as, addr, &addr1, &l, true);
-+        mr = address_space_translate(as, addr, &addr1, &l, true,
-+                                     MEMTXATTRS_UNSPECIFIED);
-         if (!(memory_region_is_ram(mr) ||
-               memory_region_is_romd(mr))) {
-@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
-  */
- static inline MemoryRegion *address_space_translate_cached(
-     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
--    hwaddr *plen, bool is_write)
-+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegionSection section;
-     MemoryRegion *mr;
-@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
-+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
-+                                        MEMTXATTRS_UNSPECIFIED);
-     flatview_read_continue(cache->fv,
-                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
-                            addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
-+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
-+                                        MEMTXATTRS_UNSPECIFIED);
-     flatview_write_continue(cache->fv,
-                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
-                             addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
-     rcu_read_lock();
-     mr = address_space_translate(&address_space_memory,
--                                 phys_addr, &phys_addr, &l, false);
-+                                 phys_addr, &phys_addr, &l, false,
-+                                 MEMTXATTRS_UNSPECIFIED);
-     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
-     rcu_read_unlock();
-diff --git a/hw/vfio/common.c b/hw/vfio/common.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/vfio/common.c
-+++ b/hw/vfio/common.c
-@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
-      */
-     mr = address_space_translate(&address_space_memory,
-                                  iotlb->translated_addr,
--                                 &xlat, &len, writable);
-+                                 &xlat, &len, writable,
-+                                 MEMTXATTRS_UNSPECIFIED);
-     if (!memory_region_is_ram(mr)) {
-         error_report("iommu map to non memory area %"HWADDR_PRIx"",
-                      xlat);
-diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory_ldst.inc.c
-+++ b/memory_ldst.inc.c
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 4 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 8 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (!IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, false);
-+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
-     if (l < 2 || !IS_DIRECT(mr, false)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 4 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 4 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (!IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
-@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 2 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
-     bool release_lock = false;
-     RCU_READ_LOCK();
--    mr = TRANSLATE(addr, &addr1, &l, true);
-+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
-     if (l < 8 || !IS_DIRECT(mr, true)) {
-         release_lock |= prepare_mmio_access(mr);
-diff --git a/target/riscv/helper.c b/target/riscv/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.c
-+++ b/target/riscv/helper.c
-@@ -XXX,XX +XXX,XX @@ restart:
-                 MemoryRegion *mr;
-                 hwaddr l = sizeof(target_ulong), addr1;
-                 mr = address_space_translate(cs->as, pte_addr,
--                    &addr1, &l, false);
-+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
-                 if (memory_access_is_direct(mr, true)) {
-                     target_ulong *pte_pa =
-                         qemu_map_ram_ptr(mr->ram_block, addr1);
---
-.17.1

-[Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_map().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
----
- include/exec/memory.h   | 3 ++-
- include/sysemu/dma.h    | 3 ++-
- exec.c                  | 6 ++++--
- target/ppc/mmu-hash64.c | 3 ++-
-files changed, 10 insertions(+), 5 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
-  * @addr: address within that address space
-  * @plen: pointer to length of buffer; updated on return
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
- void *address_space_map(AddressSpace *as, hwaddr addr,
--                        hwaddr *plen, bool is_write);
-+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
- /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
-  *
-diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/dma.h
-+++ b/include/sysemu/dma.h
-@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
-     hwaddr xlen = *len;
-     void *p;
--    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
-+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
-+                          MEMTXATTRS_UNSPECIFIED);
-     *len = xlen;
-     return p;
- }
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
- void *address_space_map(AddressSpace *as,
-                         hwaddr addr,
-                         hwaddr *plen,
--                        bool is_write)
-+                        bool is_write,
-+                        MemTxAttrs attrs)
- {
-     hwaddr len = *plen;
-     hwaddr l, xlat;
-@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
-                               hwaddr *plen,
-                               int is_write)
- {
--    return address_space_map(&address_space_memory, addr, plen, is_write);
-+    return address_space_map(&address_space_memory, addr, plen, is_write,
-+                             MEMTXATTRS_UNSPECIFIED);
- }
- void cpu_physical_memory_unmap(void *buffer, hwaddr len,
-diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/ppc/mmu-hash64.c
-+++ b/target/ppc/mmu-hash64.c
-@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
-         return NULL;
-     }
--    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
-+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
-+                              MEMTXATTRS_UNSPECIFIED);
-     if (plen < (n * HASH_PTE_SIZE_64)) {
-         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
-     }
---
-.17.1

-[Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_access_valid().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
----
- include/exec/memory.h      | 4 +++-
- include/sysemu/dma.h       | 3 ++-
- exec.c                     | 3 ++-
- target/s390x/diag.c        | 6 ++++--
- target/s390x/excp_helper.c | 3 ++-
- target/s390x/mmu_helper.c  | 3 ++-
- target/s390x/sigp.c        | 3 ++-
-files changed, 17 insertions(+), 8 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
-  * @addr: address within that address space
-  * @len: length of the area to be checked
-  * @is_write: indicates the transfer direction
-+ * @attrs: memory attributes
-  */
--bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
-+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
-+                                bool is_write, MemTxAttrs attrs);
- /* address_space_map: map a physical memory region into a host virtual address
-  *
-diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/sysemu/dma.h
-+++ b/include/sysemu/dma.h
-@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
-                                     DMADirection dir)
- {
-     return address_space_access_valid(as, addr, len,
--                                      dir == DMA_DIRECTION_FROM_DEVICE);
-+                                      dir == DMA_DIRECTION_FROM_DEVICE,
-+                                      MEMTXATTRS_UNSPECIFIED);
- }
- static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
- }
- bool address_space_access_valid(AddressSpace *as, hwaddr addr,
--                                int len, bool is_write)
-+                                int len, bool is_write,
-+                                MemTxAttrs attrs)
- {
-     FlatView *fv;
-     bool result;
-diff --git a/target/s390x/diag.c b/target/s390x/diag.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/diag.c
-+++ b/target/s390x/diag.c
-@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
-             return;
-         }
-         if (!address_space_access_valid(&address_space_memory, addr,
--                                        sizeof(IplParameterBlock), false)) {
-+                                        sizeof(IplParameterBlock), false,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
-             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
-             return;
-         }
-@@ -XXX,XX +XXX,XX @@ out:
-             return;
-         }
-         if (!address_space_access_valid(&address_space_memory, addr,
--                                        sizeof(IplParameterBlock), true)) {
-+                                        sizeof(IplParameterBlock), true,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
-             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
-             return;
-         }
-diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/excp_helper.c
-+++ b/target/s390x/excp_helper.c
-@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
-     /* check out of RAM access */
-     if (!address_space_access_valid(&address_space_memory, raddr,
--                                    TARGET_PAGE_SIZE, rw)) {
-+                                    TARGET_PAGE_SIZE, rw,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
-                 (uint64_t)raddr, (uint64_t)ram_size);
-         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
-diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/mmu_helper.c
-+++ b/target/s390x/mmu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
-             return ret;
-         }
-         if (!address_space_access_valid(&address_space_memory, pages[i],
--                                        TARGET_PAGE_SIZE, is_write)) {
-+                                        TARGET_PAGE_SIZE, is_write,
-+                                        MEMTXATTRS_UNSPECIFIED)) {
-             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
-             return -EFAULT;
-         }
-diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/s390x/sigp.c
-+++ b/target/s390x/sigp.c
-@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
-     cpu_synchronize_state(cs);
-     if (!address_space_access_valid(&address_space_memory, addr,
--                                    sizeof(struct LowCore), false)) {
-+                                    sizeof(struct LowCore), false,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
-         return;
-     }
---
-.17.1

-[Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_extend_translation().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
----
- exec.c | 15 ++++++++++-----
-file changed, 10 insertions(+), 5 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
- static hwaddr
- flatview_extend_translation(FlatView *fv, hwaddr addr,
--                                 hwaddr target_len,
--                                 MemoryRegion *mr, hwaddr base, hwaddr len,
--                                 bool is_write)
-+                            hwaddr target_len,
-+                            MemoryRegion *mr, hwaddr base, hwaddr len,
-+                            bool is_write, MemTxAttrs attrs)
- {
-     hwaddr done = 0;
-     hwaddr xlat;
-@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
-     memory_region_ref(mr);
-     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
--                                             l, is_write);
-+                                        l, is_write, attrs);
-     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
-     rcu_read_unlock();
-@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
-     mr = cache->mrs.mr;
-     memory_region_ref(mr);
-     if (memory_access_is_direct(mr, is_write)) {
-+        /* We don't care about the memory attributes here as we're only
-+         * doing this if we found actual RAM, which behaves the same
-+         * regardless of attributes; so UNSPECIFIED is fine.
-+         */
-         l = flatview_extend_translation(cache->fv, addr, len, mr,
--                                        cache->xlat, l, is_write);
-+                                        cache->xlat, l, is_write,
-+                                        MEMTXATTRS_UNSPECIFIED);
-         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
-     } else {
-         cache->ptr = NULL;
---
-.17.1

-[Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to memory_region_access_valid().
-Its callers either have an attrs value to hand, or don't care
-and can use MEMTXATTRS_UNSPECIFIED.
-The callsite in flatview_access_valid() is part of a recursive
-loop flatview_access_valid() -> memory_region_access_valid() ->
- subpage_accepts() -> flatview_access_valid(); we make it pass
-MEMTXATTRS_UNSPECIFIED for now, until the next several commits
-have plumbed an attrs parameter through the rest of the loop
-and we can add an attrs parameter to flatview_access_valid().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
----
- include/exec/memory-internal.h | 3 ++-
- exec.c                         | 4 +++-
- hw/s390x/s390-pci-inst.c       | 3 ++-
- memory.c                       | 7 ++++---
-files changed, 11 insertions(+), 6 deletions(-)
-diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory-internal.h
-+++ b/include/exec/memory-internal.h
-@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
- extern const MemoryRegionOps unassigned_mem_ops;
- bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
--                                unsigned size, bool is_write);
-+                                unsigned size, bool is_write,
-+                                MemTxAttrs attrs);
- void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
- AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
--            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
-+            /* When our callers all have attrs we'll pass them through here */
-+            if (!memory_region_access_valid(mr, xlat, l, is_write,
-+                                            MEMTXATTRS_UNSPECIFIED)) {
-                 return false;
-             }
-         }
-diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/s390x/s390-pci-inst.c
-+++ b/hw/s390x/s390-pci-inst.c
-@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
-     mr = s390_get_subregion(mr, offset, len);
-     offset -= mr->addr;
--    if (!memory_region_access_valid(mr, offset, len, true)) {
-+    if (!memory_region_access_valid(mr, offset, len, true,
-+                                    MEMTXATTRS_UNSPECIFIED)) {
-         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
-         return 0;
-     }
-diff --git a/memory.c b/memory.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory.c
-+++ b/memory.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
- bool memory_region_access_valid(MemoryRegion *mr,
-                                 hwaddr addr,
-                                 unsigned size,
--                                bool is_write)
-+                                bool is_write,
-+                                MemTxAttrs attrs)
- {
-     int access_size_min, access_size_max;
-     int access_size, i;
-@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
- {
-     MemTxResult r;
--    if (!memory_region_access_valid(mr, addr, size, false)) {
-+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
-         *pval = unassigned_mem_read(mr, addr, size);
-         return MEMTX_DECODE_ERROR;
-     }
-@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
-                                          unsigned size,
-                                          MemTxAttrs attrs)
- {
--    if (!memory_region_access_valid(mr, addr, size, true)) {
-+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
-         unassigned_mem_write(mr, addr, data, size);
-         return MEMTX_DECODE_ERROR;
-     }
---
-.17.1

-[Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to the MemoryRegion valid.accepts
-callback. We'll need this for subpage_accepts().
-We could take the approach we used with the read and write
-callbacks and add new a new _with_attrs version, but since there
-are so few implementations of the accepts hook we just change
-them all.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
----
- include/exec/memory.h |  3 ++-
- exec.c                |  9 ++++++---
- hw/hppa/dino.c        |  3 ++-
- hw/nvram/fw_cfg.c     | 12 ++++++++----
- hw/scsi/esp.c         |  3 ++-
- hw/xen/xen_pt_msi.c   |  3 ++-
- memory.c              |  5 +++--
-files changed, 25 insertions(+), 13 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
-          * as a machine check exception).
-          */
-         bool (*accepts)(void *opaque, hwaddr addr,
--                        unsigned size, bool is_write);
-+                        unsigned size, bool is_write,
-+                        MemTxAttrs attrs);
-     } valid;
-     /* Internal implementation constraints: */
-     struct {
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
- }
- static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
--                                 unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return is_write;
- }
-@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
- }
- static bool subpage_accepts(void *opaque, hwaddr addr,
--                            unsigned len, bool is_write)
-+                            unsigned len, bool is_write,
-+                            MemTxAttrs attrs)
- {
-     subpage_t *subpage = opaque;
- #if defined(DEBUG_SUBPAGE)
-@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
- }
- static bool readonly_mem_accepts(void *opaque, hwaddr addr,
--                                 unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return is_write;
- }
-diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/hppa/dino.c
-+++ b/hw/hppa/dino.c
-@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
- }
- static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
--                                unsigned size, bool is_write)
-+                                unsigned size, bool is_write,
-+                                MemTxAttrs attrs)
- {
-     switch (addr) {
-     case DINO_IAR0:
-diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/nvram/fw_cfg.c
-+++ b/hw/nvram/fw_cfg.c
-@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
- }
- static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
--                                  unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
-                          (size == 8 && addr == 0));
- }
- static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
--                                  unsigned size, bool is_write)
-+                                  unsigned size, bool is_write,
-+                                  MemTxAttrs attrs)
- {
-     return addr == 0;
- }
-@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
- }
- static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
--                                 unsigned size, bool is_write)
-+                                 unsigned size, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     return is_write && size == 2;
- }
-@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
- }
- static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
--                                  unsigned size, bool is_write)
-+                              unsigned size, bool is_write,
-+                              MemTxAttrs attrs)
- {
-     return (size == 1) || (is_write && size == 2);
- }
-diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/scsi/esp.c
-+++ b/hw/scsi/esp.c
-@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
- }
- static bool esp_mem_accepts(void *opaque, hwaddr addr,
--                            unsigned size, bool is_write)
-+                            unsigned size, bool is_write,
-+                            MemTxAttrs attrs)
- {
-     return (size == 1) || (is_write && size == 4);
- }
-diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/xen/xen_pt_msi.c
-+++ b/hw/xen/xen_pt_msi.c
-@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
- }
- static bool pci_msix_accepts(void *opaque, hwaddr addr,
--                             unsigned size, bool is_write)
-+                             unsigned size, bool is_write,
-+                             MemTxAttrs attrs)
- {
-     return !(addr & (size - 1));
- }
-diff --git a/memory.c b/memory.c
-index XXXXXXX..XXXXXXX 100644
---- a/memory.c
-+++ b/memory.c
-@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
- }
- static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
--                                   unsigned size, bool is_write)
-+                                   unsigned size, bool is_write,
-+                                   MemTxAttrs attrs)
- {
-     return false;
- }
-@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
-     access_size = MAX(MIN(size, access_size_max), access_size_min);
-     for (i = 0; i < size; i += access_size) {
-         if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
--                                    is_write)) {
-+                                    is_write, attrs)) {
-             return false;
-         }
-     }
---
-.17.1

-[Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_translate(); all its
-callers now have attrs available.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
----
- include/exec/memory.h |  7 ++++---
- exec.c                | 17 +++++++++--------
-files changed, 13 insertions(+), 11 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-  */
- MemoryRegion *flatview_translate(FlatView *fv,
-                                  hwaddr addr, hwaddr *xlat,
--                                 hwaddr *len, bool is_write);
-+                                 hwaddr *len, bool is_write,
-+                                 MemTxAttrs attrs);
- static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     hwaddr addr, hwaddr *xlat,
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
-                                                     MemTxAttrs attrs)
- {
-     return flatview_translate(address_space_to_flatview(as),
--                              addr, xlat, len, is_write);
-+                              addr, xlat, len, is_write, attrs);
- }
- /* address_space_access_valid: check for validity of accessing an address
-@@ -XXX,XX +XXX,XX @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
-             rcu_read_lock();
-             fv = address_space_to_flatview(as);
-             l = len;
--            mr = flatview_translate(fv, addr, &addr1, &l, false);
-+            mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-             if (len == l && memory_access_is_direct(mr, false)) {
-                 ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
-                 memcpy(buf, ptr, len);
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ iotlb_fail:
- /* Called from RCU critical section */
- MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
--                                 hwaddr *plen, bool is_write)
-+                                 hwaddr *plen, bool is_write,
-+                                 MemTxAttrs attrs)
- {
-     MemoryRegion *mr;
-     MemoryRegionSection section;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
-         }
-         l = len;
--        mr = flatview_translate(fv, addr, &addr1, &l, true);
-+        mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
-     }
-     return result;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
-     MemTxResult result = MEMTX_OK;
-     l = len;
--    mr = flatview_translate(fv, addr, &addr1, &l, true);
-+    mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
-     result = flatview_write_continue(fv, addr, attrs, buf, len,
-                                      addr1, l, mr);
-@@ -XXX,XX +XXX,XX @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
-         }
-         l = len;
--        mr = flatview_translate(fv, addr, &addr1, &l, false);
-+        mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-     }
-     return result;
-@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
-     MemoryRegion *mr;
-     l = len;
--    mr = flatview_translate(fv, addr, &addr1, &l, false);
-+    mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
-     return flatview_read_continue(fv, addr, attrs, buf, len,
-                                   addr1, l, mr);
- }
-@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-     while (len > 0) {
-         l = len;
--        mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-+        mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
-         if (!memory_access_is_direct(mr, is_write)) {
-             l = memory_access_size(mr, l, addr);
-             if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
-@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
-         len = target_len;
-         this_mr = flatview_translate(fv, addr, &xlat,
--                                                   &len, is_write);
-+                                     &len, is_write, attrs);
-         if (this_mr != mr || xlat != base + done) {
-             return done;
-         }
-@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
-     l = len;
-     rcu_read_lock();
-     fv = address_space_to_flatview(as);
--    mr = flatview_translate(fv, addr, &xlat, &l, is_write);
-+    mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
-     if (!memory_access_is_direct(mr, is_write)) {
-         if (atomic_xchg(&bounce.in_use, true)) {
---
-.17.1

-[Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_get_iotlb_entry().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
----
- include/exec/memory.h | 2 +-
- exec.c                | 2 +-
- hw/virtio/vhost.c     | 3 ++-
-files changed, 4 insertions(+), 3 deletions(-)
-diff --git a/include/exec/memory.h b/include/exec/memory.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/exec/memory.h
-+++ b/include/exec/memory.h
-@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
-  * entry. Should be called from an RCU critical section.
-  */
- IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
--                                            bool is_write);
-+                                            bool is_write, MemTxAttrs attrs);
- /* address_space_translate: translate an address range into an address space
-  * into a MemoryRegion and an address range into that section.  Should be
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
- /* Called from RCU critical section */
- IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
--                                            bool is_write)
-+                                            bool is_write, MemTxAttrs attrs)
- {
-     MemoryRegionSection section;
-     hwaddr xlat, page_mask;
-diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/virtio/vhost.c
-+++ b/hw/virtio/vhost.c
-@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
-     trace_vhost_iotlb_miss(dev, 1);
-     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
--                                          iova, write);
-+                                          iova, write,
-+                                          MEMTXATTRS_UNSPECIFIED);
-     if (iotlb.target_as != NULL) {
-         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
-                                          &uaddr, &len);
---
-.17.1

-[Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to flatview_do_translate().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
----
- exec.c | 9 ++++++---
-file changed, 6 insertions(+), 3 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ unassigned:
-  * @is_write: whether the translation operation is for write
-  * @is_mmio: whether this can be MMIO, set true if it can
-  * @target_as: the address space targeted by the IOMMU
-+ * @attrs: memory transaction attributes
-  *
-  * This function is called from RCU critical section
-  */
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-                                                  hwaddr *page_mask_out,
-                                                  bool is_write,
-                                                  bool is_mmio,
--                                                 AddressSpace **target_as)
-+                                                 AddressSpace **target_as,
-+                                                 MemTxAttrs attrs)
- {
-     MemoryRegionSection *section;
-     IOMMUMemoryRegion *iommu_mr;
-@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-      * but page mask.
-      */
-     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
--                                    NULL, &page_mask, is_write, false, &as);
-+                                    NULL, &page_mask, is_write, false, &as,
-+                                    attrs);
-     /* Illegal translation */
-     if (section.mr == &io_mem_unassigned) {
-@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
-     /* This can be MMIO, so setup MMIO bit. */
-     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
--                                    is_write, true, &as);
-+                                    is_write, true, &as, attrs);
-     mr = section.mr;
-     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
---
-.17.1

-[Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
+Deleted patch
-As part of plumbing MemTxAttrs down to the IOMMU translate method,
-add MemTxAttrs as an argument to address_space_translate_iommu().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
----
- exec.c | 8 +++++---
-file changed, 5 insertions(+), 3 deletions(-)
-diff --git a/exec.c b/exec.c
-index XXXXXXX..XXXXXXX 100644
---- a/exec.c
-+++ b/exec.c
-@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
-  * @is_write: whether the translation operation is for write
-  * @is_mmio: whether this can be MMIO, set true if it can
-  * @target_as: the address space targeted by the IOMMU
-+ * @attrs: transaction attributes
-  *
-  * This function is called from RCU critical section.  It is the common
-  * part of flatview_do_translate and address_space_translate_cached.
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
-                                                          hwaddr *page_mask_out,
-                                                          bool is_write,
-                                                          bool is_mmio,
--                                                         AddressSpace **target_as)
-+                                                         AddressSpace **target_as,
-+                                                         MemTxAttrs attrs)
- {
-     MemoryRegionSection *section;
-     hwaddr page_mask = (hwaddr)-1;
-@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
-         return address_space_translate_iommu(iommu_mr, xlat,
-                                              plen_out, page_mask_out,
-                                              is_write, is_mmio,
--                                             target_as);
-+                                             target_as, attrs);
-     }
-     if (page_mask_out) {
-         /* Not behind an IOMMU, use default page size. */
-@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
-     section = address_space_translate_iommu(iommu_mr, xlat, plen,
-                                             NULL, is_write, true,
--                                            &target_as);
-+                                            &target_as, attrs);
-     return section.mr;
- }
---
-.17.1

-[Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
+Deleted patch
-Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
-and friends.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
----
- include/migration/vmstate.h | 3 +++
-file changed, 3 insertions(+)
-diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/migration/vmstate.h
-+++ b/include/migration/vmstate.h
-@@ -XXX,XX +XXX,XX @@ extern const VMStateInfo vmstate_info_qtailq;
- #define VMSTATE_BOOL_ARRAY(_f, _s, _n)                               \
-     VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
-+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num)                \
-+    VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
-+
- #define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v)                         \
-     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
---
-.17.1

target-arm queue. This has the "plumb txattrs through various
bits of exec.c" patches, and a collection of bug fixes from
various people.

thanks
-- PMM

The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:

Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531

for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:

KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)

----------------------------------------------------------------
target-arm queue:
 * target/arm: Honour FPCR.FZ in FRECPX
 * MAINTAINERS: Add entries for newer MPS2 boards and devices
 * hw/intc/arm_gicv3: Fix APxR<n> register dispatching
 * arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
   GIC state
 * tcg: Fix helper function vs host abi for float16
 * arm: fix qemu crash on startup with -bios option
 * arm: fix malloc type mismatch
 * xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
 * Correct CPACR reset value for v7 cores
 * memory.h: Improve IOMMU related documentation
 * exec: Plumb transaction attributes through various functions in
   preparation for allowing IOMMUs to see them
 * vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
 * ARM: ACPI: Fix use-after-free due to memory realloc
 * KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

----------------------------------------------------------------
Francisco Iglesias (1):
      xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors

Igor Mammedov (1):
      arm: fix qemu crash on startup with -bios option

Jan Kiszka (1):
      hw/intc/arm_gicv3: Fix APxR<n> register dispatching

Paolo Bonzini (1):
      arm: fix malloc type mismatch

Peter Maydell (17):
      target/arm: Honour FPCR.FZ in FRECPX
      MAINTAINERS: Add entries for newer MPS2 boards and devices
      Correct CPACR reset value for v7 cores
      memory.h: Improve IOMMU related documentation
      Make tb_invalidate_phys_addr() take a MemTxAttrs argument
      Make address_space_translate{, _cached}() take a MemTxAttrs argument
      Make address_space_map() take a MemTxAttrs argument
      Make address_space_access_valid() take a MemTxAttrs argument
      Make flatview_extend_translation() take a MemTxAttrs argument
      Make memory_region_access_valid() take a MemTxAttrs argument
      Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
      Make flatview_access_valid() take a MemTxAttrs argument
      Make flatview_translate() take a MemTxAttrs argument
      Make address_space_get_iotlb_entry() take a MemTxAttrs argument
      Make flatview_do_translate() take a MemTxAttrs argument
      Make address_space_translate_iommu take a MemTxAttrs argument
      vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY

Richard Henderson (1):
      tcg: Fix helper function vs host abi for float16

Shannon Zhao (3):
      arm_gicv3_kvm: increase clroffset accordingly
      ARM: ACPI: Fix use-after-free due to memory realloc
      KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice

The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
---
 target/arm/helper-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
         return nan;
     }
 
+    a = float16_squash_input_denormal(a, fpst);
+
     val16 = float16_val(a);
     sbit = 0x8000 & val16;
     exp = extract32(val16, 10, 5);
@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
         return nan;
     }
 
+    a = float32_squash_input_denormal(a, fpst);
+
     val32 = float32_val(a);
     sbit = 0x80000000ULL & val32;
     exp = extract32(val32, 23, 8);
@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
         return nan;
     }
 
+    a = float64_squash_input_denormal(a, fpst);
+
     val64 = float64_val(a);
     sbit = 0x8000000000000000ULL & val64;
     exp = extract64(float64_val(a), 52, 11);
-- 
2.17.1

Add entries to MAINTAINERS to cover the newer MPS2 boards and
the new devices they use.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
---
 MAINTAINERS | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/timer/cmsdk-apb-timer.c
 F: include/hw/timer/cmsdk-apb-timer.h
 F: hw/char/cmsdk-apb-uart.c
 F: include/hw/char/cmsdk-apb-uart.h
+F: hw/misc/tz-ppc.c
+F: include/hw/misc/tz-ppc.h
 
 ARM cores
 M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/mps2.c
-F: hw/misc/mps2-scc.c
-F: include/hw/misc/mps2-scc.h
+F: hw/arm/mps2-tz.c
+F: hw/misc/mps2-*.c
+F: include/hw/misc/mps2-*.h
+F: hw/arm/iotkit.c
+F: include/hw/arm/iotkit.h
 
 Musicpal
 M: Jan Kiszka <jan.kiszka@web.de>
-- 
2.17.1

From: Jan Kiszka <jan.kiszka@siemens.com>

There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.

Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value = cs->ich_apr[grp][regno];
 
     trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -XXX,XX +XXX,XX @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
@@ -XXX,XX +XXX,XX @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
     uint64_t value;
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         return icv_ap_read(env, ri);
@@ -XXX,XX +XXX,XX @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
     GICv3CPUState *cs = icc_cs_from_env(env);
 
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+    int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
 
     if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
         icv_ap_write(env, ri, value);
@@ -XXX,XX +XXX,XX @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
     uint64_t value;
 
     value = cs->ich_apr[grp][regno];
@@ -XXX,XX +XXX,XX @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
 {
     GICv3CPUState *cs = icc_cs_from_env(env);
     int regno = ri->opc2 & 3;
-    int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+    int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
 
     trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.

Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-stable@nongnu.org
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_kvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
         if (clroffset != 0) {
             reg = 0;
             kvm_gicd_access(s, clroffset, &reg, true);
+            clroffset += 4;
         }
         reg = *gic_bmp_ptr32(bmp, irq);
         kvm_gicd_access(s, offset, &reg, true);
-- 
2.17.1

From: Richard Henderson <richard.henderson@linaro.org>

Depending on the host abi, float16, aka uint16_t, values are
passed and returned either zero-extended in the host register
or with garbage at the top of the host register.

The tcg code generator has so far been assuming garbage, as that
matches the x86 abi, but this is incorrect for other host abis.
Further, target/arm has so far been assuming zero-extended results,
so that it may store the 16-bit value into a 32-bit slot with the
high 16-bits already clear.

Rectify both problems by mapping "f16" in the helper definition
to uint32_t instead of (a typedef for) uint16_t.  This forces
the host compiler to assume garbage in the upper 16 bits on input
and to zero-extend the result on output.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/exec/helper-head.h |  2 +-
 target/arm/helper-a64.c    | 35 +++++++++--------
 target/arm/helper.c        | 80 +++++++++++++++++++-------------------
 3 files changed, 59 insertions(+), 58 deletions(-)

diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -XXX,XX +XXX,XX @@
 #define dh_ctype_int int
 #define dh_ctype_i64 uint64_t
 #define dh_ctype_s64 int64_t
-#define dh_ctype_f16 float16
+#define dh_ctype_f16 uint32_t
 #define dh_ctype_f32 float32
 #define dh_ctype_f64 float64
 #define dh_ctype_ptr void *
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
     return flags;
 }
 
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
 }
 
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
 {
     return float_rel_to_flags(float16_compare(x, y, fp_status));
 }
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 #define float64_three make_float64(0x4008000000000000ULL)
 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
     return float64_muladd(a, b, float64_two, 0, fpst);
 }
 
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 }
 
 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
     uint16_t val16, sbit;
@@ -XXX,XX +XXX,XX @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
 #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
 
 #define ADVSIMD_HALFOP(name) \
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
 { \
     float_status *fpst = fpstp; \
     return float16_ ## name(a, b, fpst);    \
@@ -XXX,XX +XXX,XX @@ ADVSIMD_HALFOP(mulx)
 ADVSIMD_TWOHALFOP(mulx)
 
 /* fused multiply-accumulate */
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
+                                 void *fpstp)
 {
     float_status *fpst = fpstp;
     return float16_muladd(a, b, c, 0, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
 
 #define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
 
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare_quiet(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     int compare = float16_compare(a, b, fpst);
     return ADVSIMD_CMPRES(compare == float_relation_greater);
 }
 
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
                           compare == float_relation_equal);
 }
 
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f0 = float16_abs(a);
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
 }
 
 /* round to integral */
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
 {
     return float16_round_to_int(x, fp_status);
 }
 
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
 {
     int old_flags = get_float_exception_flags(fp_status), new_flags;
     float16 ret;
@@ -XXX,XX +XXX,XX @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
  * setting the mode appropriately before calling the helper.
  */
 
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
     return float16_to_int16(a, fpst);
 }
 
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
 {
     float_status *fpst = fpstp;
 
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
  * Square Root and Reciprocal square root
  */
 
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
 {
     float_status *s = fpstp;
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ DO_VFP_cmp(d, float64)
 
 /* Integer to float and float to integer conversions */
 
-#define CONV_ITOF(name, fsz, sign) \
-    float##fsz HELPER(name)(uint32_t x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
+#define CONV_ITOF(name, ftype, fsz, sign)                           \
+ftype HELPER(name)(uint32_t x, void *fpstp)                         \
+{                                                                   \
+    float_status *fpst = fpstp;                                     \
+    return sign##int32_to_##float##fsz((sign##int32_t)x, fpst);     \
 }
 
-#define CONV_FTOI(name, fsz, sign, round) \
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
-{ \
-    float_status *fpst = fpstp; \
-    if (float##fsz##_is_any_nan(x)) { \
-        float_raise(float_flag_invalid, fpst); \
-        return 0; \
-    } \
-    return float##fsz##_to_##sign##int32##round(x, fpst); \
+#define CONV_FTOI(name, ftype, fsz, sign, round)                \
+uint32_t HELPER(name)(ftype x, void *fpstp)                     \
+{                                                               \
+    float_status *fpst = fpstp;                                 \
+    if (float##fsz##_is_any_nan(x)) {                           \
+        float_raise(float_flag_invalid, fpst);                  \
+        return 0;                                               \
+    }                                                           \
+    return float##fsz##_to_##sign##int32##round(x, fpst);       \
 }
 
-#define FLOAT_CONVS(name, p, fsz, sign) \
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
+#define FLOAT_CONVS(name, p, ftype, fsz, sign)            \
+    CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign)        \
+    CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, )        \
+    CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
 
-FLOAT_CONVS(si, h, 16, )
-FLOAT_CONVS(si, s, 32, )
-FLOAT_CONVS(si, d, 64, )
-FLOAT_CONVS(ui, h, 16, u)
-FLOAT_CONVS(ui, s, 32, u)
-FLOAT_CONVS(ui, d, 64, u)
+FLOAT_CONVS(si, h, uint32_t, 16, )
+FLOAT_CONVS(si, s, float32, 32, )
+FLOAT_CONVS(si, d, float64, 64, )
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
+FLOAT_CONVS(ui, s, float32, 32, u)
+FLOAT_CONVS(ui, d, float64, 64, u)
 
 #undef CONV_ITOF
 #undef CONV_FTOI
@@ -XXX,XX +XXX,XX @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
     return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
 }
 
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
 }
 
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
 {
     return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
 }
@@ -XXX,XX +XXX,XX @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
     }
 }
 
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
 }
 
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
 {
     return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
 }
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
 }
 
 /* Half precision conversions.  */
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing input denormals.
@@ -XXX,XX +XXX,XX @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
     return r;
 }
 
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
 {
     /* Squash FZ16 to 0 for the duration of conversion.  In this case,
      * it would affect flushing output denormals.
@@ -XXX,XX +XXX,XX @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
     g_assert_not_reached();
 }
 
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
 {
     float_status *fpst = fpstp;
     float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -XXX,XX +XXX,XX @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
     return extract64(estimate, 0, 8) << 44;
 }
 
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
 {
     float_status *s = fpstp;
     float16 f16 = float16_squash_input_denormal(input, s);
-- 
2.17.1

From: Igor Mammedov <imammedo@redhat.com>

When QEMU is started with following CLI
 -machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
it crashes with abort at
 accel/kvm/kvm-all.c:2164:
 KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument

Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
arm_gicv3_icc_reset() where the later is called by CPU reset
reset callback.

However commit:
 3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
broke CPU reset callback registration in case

arm_load_kernel()
      ...
      if (!info->kernel_filename || info->firmware_loaded)

branch is taken, i.e. it's sufficient to provide a firmware
or do not provide kernel on CLI to skip cpu reset callback
registration, where before offending commit the callback
has been registered unconditionally.

Fix it by registering the callback right at the beginning of
arm_load_kernel() unconditionally instead of doing it at the end.

NOTE:
 we probably should eliminate that dependency anyways as well as
 separate arch CPU reset parts from arm_load_kernel() into CPU
 itself, but that refactoring that I probably would have to do
 anyways later for CPU hotplug to work.

Reported-by: Auger Eric <eric.auger@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
     static const ARMInsnFixup *primary_loader;
     AddressSpace *as = arm_boot_address_space(cpu, info);
 
+    /* CPU objects (unlike devices) are not automatically reset on system
+     * reset, so we must always register a handler to do so. If we're
+     * actually loading a kernel, the handler is also responsible for
+     * arranging that we start it correctly.
+     */
+    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+    }
+
     /* The board code is not supposed to set secure_board_setup unless
      * running its code in secure mode is actually possible, and KVM
      * doesn't support secure.
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
         ARM_CPU(cs)->env.boot_info = info;
     }
 
-    /* CPU objects (unlike devices) are not automatically reset on system
-     * reset, so we must always register a handler to do so. If we're
-     * actually loading a kernel, the handler is also responsible for
-     * arranging that we start it correctly.
-     */
-    for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
-        qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
-    }
-
     if (!info->skip_dtb_autoload && have_dtb(info)) {
         if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
             exit(1);
-- 
2.17.1

From: Paolo Bonzini <pbonzini@redhat.com>

cpregs_keys is an uint32_t* so the allocation should use uint32_t.
g_new is even better because it is type-safe.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gdbstub.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_xml(CPUState *cs)
     RegisterSysregXmlParam param = {cs, s};
 
     cpu->dyn_xml.num_cpregs = 0;
-    cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
-                                        g_hash_table_size(cpu->cp_regs));
+    cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
     g_string_printf(s, "<?xml version=\"1.0\"?>");
     g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
     g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
-- 
2.17.1

From: Francisco Iglesias <frasse.iglesias@gmail.com>

Coverity found that the string return by 'object_get_canonical_path' was not
being freed at two locations in the model (CID 1391294 and CID 1391293) and
also that a memset was being called with a value greater than the max of a byte
on the second argument (CID 1391286). This patch corrects this by adding the
freeing of the strings and also changing to memset to zero instead on
descriptor unaligned errors.

Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/dma/xlnx-zdma.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/xlnx-zdma.c
+++ b/hw/dma/xlnx-zdma.c
@@ -XXX,XX +XXX,XX @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
         qemu_log_mask(LOG_GUEST_ERROR,
                       "zdma: unaligned descriptor at %" PRIx64,
                       addr);
-        memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+        memset(buf, 0x0, sizeof(XlnxZDMADescr));
         s->error = true;
         return false;
     }
@@ -XXX,XX +XXX,XX @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return 0;
@@ -XXX,XX +XXX,XX @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
     RegisterInfo *r = &s->regs_info[addr / 4];
 
     if (!r->data) {
+        gchar *path = object_get_canonical_path(OBJECT(s));
         qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
-                 object_get_canonical_path(OBJECT(s)),
+                 path,
                  addr, value);
+        g_free(path);
         ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
         zdma_ch_imr_update_irq(s);
         return;
-- 
2.17.1

In commit f0aff255700 we made cpacr_write() enforce that some CPACR
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
we forgot to also update the register's reset value. The effect
was that (a) a guest that read CPACR on reset would not see ones in
the RAO bits, and (b) if you did a migration before the guest did
a write to the CPACR then the migration would fail because the
destination would enforce the RAO bits and then complain that they
didn't match the zero value from the source.

Implement reset for the CPACR using a custom reset function
that just calls cpacr_write(), to avoid having to duplicate
the logic for which bits are RAO.

This bug would affect migration for TCG CPUs which are ARMv7
with VFP but without one of Neon or VFPv3.

Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
     env->cp15.cpacr_el1 = value;
 }
 
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /* Call cpacr_write() so that we reset with the correct RAO bits set
+     * for our CPU features.
+     */
+    cpacr_write(env, ri, 0);
+}
+
 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
-      .resetvalue = 0, .writefn = cpacr_write },
+      .resetfn = cpacr_reset, .writefn = cpacr_write },
     REGINFO_SENTINEL
 };
 
-- 
2.17.1

Add more detail to the documentation for memory_region_init_iommu()
and other IOMMU-related functions and data structures.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
---
 include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
 1 file changed, 95 insertions(+), 10 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ enum IOMMUMemoryRegionAttr {
     IOMMU_ATTR_SPAPR_TCE_FD
 };
 
+/**
+ * IOMMUMemoryRegionClass:
+ *
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
+ * and provide an implementation of at least the @translate method here
+ * to handle requests to the memory region. Other methods are optional.
+ *
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
+ * to report whenever mappings are changed, by calling
+ * memory_region_notify_iommu() (or, if necessary, by calling
+ * memory_region_notify_one() for each registered notifier).
+ */
 typedef struct IOMMUMemoryRegionClass {
     /* private */
     struct DeviceClass parent_class;
 
     /*
-     * Return a TLB entry that contains a given address. Flag should
-     * be the access permission of this translation operation. We can
-     * set flag to IOMMU_NONE to mean that we don't need any
-     * read/write permission checks, like, when for region replay.
+     * Return a TLB entry that contains a given address.
+     *
+     * The IOMMUAccessFlags indicated via @flag are optional and may
+     * be specified as IOMMU_NONE to indicate that the caller needs
+     * the full translation information for both reads and writes. If
+     * the access flags are specified then the IOMMU implementation
+     * may use this as an optimization, to stop doing a page table
+     * walk as soon as it knows that the requested permissions are not
+     * allowed. If IOMMU_NONE is passed then the IOMMU must do the
+     * full page table walk and report the permissions in the returned
+     * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
+     * return different mappings for reads and writes.)
+     *
+     * The returned information remains valid while the caller is
+     * holding the big QEMU lock or is inside an RCU critical section;
+     * if the caller wishes to cache the mapping beyond that it must
+     * register an IOMMU notifier so it can invalidate its cached
+     * information when the IOMMU mapping changes.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @hwaddr: address to be translated within the memory region
+     * @flag: requested access permissions
      */
     IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
                                IOMMUAccessFlags flag);
-    /* Returns minimum supported page size */
+    /* Returns minimum supported page size in bytes.
+     * If this method is not provided then the minimum is assumed to
+     * be TARGET_PAGE_SIZE.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     */
     uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
-    /* Called when IOMMU Notifier flag changed */
+    /* Called when IOMMU Notifier flag changes (ie when the set of
+     * events which IOMMU users are requesting notification for changes).
+     * Optional method -- need not be provided if the IOMMU does not
+     * need to know exactly which events must be notified.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @old_flags: events which previously needed to be notified
+     * @new_flags: events which now need to be notified
+     */
     void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
                                 IOMMUNotifierFlag old_flags,
                                 IOMMUNotifierFlag new_flags);
-    /* Set this up to provide customized IOMMU replay function */
+    /* Called to handle memory_region_iommu_replay().
+     *
+     * The default implementation of memory_region_iommu_replay() is to
+     * call the IOMMU translate method for every page in the address space
+     * with flag == IOMMU_NONE and then call the notifier if translate
+     * returns a valid mapping. If this method is implemented then it
+     * overrides the default behaviour, and must provide the full semantics
+     * of memory_region_iommu_replay(), by calling @notifier for every
+     * translation present in the IOMMU.
+     *
+     * Optional method -- an IOMMU only needs to provide this method
+     * if the default is inefficient or produces undesirable side effects.
+     *
+     * Note: this is not related to record-and-replay functionality.
+     */
     void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
 
-    /* Get IOMMU misc attributes */
-    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
+    /* Get IOMMU misc attributes. This is an optional method that
+     * can be used to allow users of the IOMMU to get implementation-specific
+     * information. The IOMMU implements this method to handle calls
+     * by IOMMU users to memory_region_iommu_get_attr() by filling in
+     * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
+     * the IOMMU supports. If the method is unimplemented then
+     * memory_region_iommu_get_attr() will always return -EINVAL.
+     *
+     * @iommu: the IOMMUMemoryRegion
+     * @attr: attribute being queried
+     * @data: memory to fill in with the attribute data
+     *
+     * Returns 0 on success, or a negative errno; in particular
+     * returns -EINVAL for unrecognized or unimplemented attribute types.
+     */
+    int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
                     void *data);
 } IOMMUMemoryRegionClass;
 
@@ -XXX,XX +XXX,XX @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
  * An IOMMU region translates addresses and forwards accesses to a target
  * memory region.
  *
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
+ * @_iommu_mr should be a pointer to enough memory for an instance of
+ * that subclass, @instance_size is the size of that subclass, and
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
+ * instance of the subclass, and its methods will then be called to handle
+ * accesses to the memory region. See the documentation of
+ * #IOMMUMemoryRegionClass for further details.
+ *
  * @_iommu_mr: the #IOMMUMemoryRegion to be initialized
  * @instance_size: the IOMMUMemoryRegion subclass instance size
  * @mrtypename: the type name of the #IOMMUMemoryRegion
@@ -XXX,XX +XXX,XX @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
  * a notifier with the minimum page granularity returned by
  * mr->iommu_ops->get_page_size().
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  * @n: the notifier to which to replay iommu mappings
  */
@@ -XXX,XX +XXX,XX @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
  * memory_region_iommu_replay_all: replay existing IOMMU translations
  * to all the notifiers registered.
  *
+ * Note: this is not related to record-and-replay functionality.
+ *
  * @iommu_mr: the memory region to observe
  */
 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
@@ -XXX,XX +XXX,XX @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
  * memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
  * defined on the IOMMU.
  *
- * Returns 0 if succeded, error code otherwise.
+ * Returns 0 on success, or a negative errno otherwise. In particular,
+ * -EINVAL indicates that the IOMMU does not support the requested
+ * attribute.
  *
  * @iommu_mr: the memory region
  * @attr: the requested attribute
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
---
 include/exec/exec-all.h   | 5 +++--
 accel/tcg/translate-all.c | 2 +-
 exec.c                    | 2 +-
 target/xtensa/op_helper.c | 3 ++-
 4 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
                   hwaddr paddr, int prot,
                   int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
 void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
                  uintptr_t retaddr);
 #else
@@ -XXX,XX +XXX,XX @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                        uint16_t idxmap)
 {
 }
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
+                                           MemTxAttrs attrs)
 {
 }
 #endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
 {
     ram_addr_t ram_addr;
     MemoryRegion *mr;
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
     if (phys != -1) {
         /* Locks grabbed by tb_invalidate_phys_addr */
         tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
-                                phys | (pc & ~TARGET_PAGE_MASK));
+                                phys | (pc & ~TARGET_PAGE_MASK), attrs);
     }
 }
 #endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -XXX,XX +XXX,XX @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
     int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
             &paddr, &page_size, &access);
     if (ret == 0) {
-        tb_invalidate_phys_addr(&address_space_memory, paddr);
+        tb_invalidate_phys_addr(&address_space_memory, paddr,
+                                MEMTXATTRS_UNSPECIFIED);
     }
 }
 
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate()
and address_space_translate_cached(). Callers either have an
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
---
 include/exec/memory.h     |  4 +++-
 accel/tcg/translate-all.c |  2 +-
 exec.c                    | 14 +++++++++-----
 hw/vfio/common.c          |  3 ++-
 memory_ldst.inc.c         | 18 +++++++++---------
 target/riscv/helper.c     |  2 +-
 6 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
  * #MemoryRegion.
  * @len: pointer to length
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 MemoryRegion *flatview_translate(FlatView *fv,
                                  hwaddr addr, hwaddr *xlat,
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv,
 
 static inline MemoryRegion *address_space_translate(AddressSpace *as,
                                                     hwaddr addr, hwaddr *xlat,
-                                                    hwaddr *len, bool is_write)
+                                                    hwaddr *len, bool is_write,
+                                                    MemTxAttrs attrs)
 {
     return flatview_translate(address_space_to_flatview(as),
                               addr, xlat, len, is_write);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
     hwaddr l = 1;
 
     rcu_read_lock();
-    mr = address_space_translate(as, addr, &addr, &l, false);
+    mr = address_space_translate(as, addr, &addr, &l, false, attrs);
     if (!(memory_region_is_ram(mr)
           || memory_region_is_romd(mr))) {
         rcu_read_unlock();
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
     rcu_read_lock();
     while (len > 0) {
         l = len;
-        mr = address_space_translate(as, addr, &addr1, &l, true);
+        mr = address_space_translate(as, addr, &addr1, &l, true,
+                                     MEMTXATTRS_UNSPECIFIED);
 
         if (!(memory_region_is_ram(mr) ||
               memory_region_is_romd(mr))) {
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache)
  */
 static inline MemoryRegion *address_space_translate_cached(
     MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
-    hwaddr *plen, bool is_write)
+    hwaddr *plen, bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     MemoryRegion *mr;
@@ -XXX,XX +XXX,XX @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_read_continue(cache->fv,
                            addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                            addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
     MemoryRegion *mr;
 
     l = len;
-    mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
+    mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
+                                        MEMTXATTRS_UNSPECIFIED);
     flatview_write_continue(cache->fv,
                             addr, MEMTXATTRS_UNSPECIFIED, buf, len,
                             addr1, l, mr);
@@ -XXX,XX +XXX,XX @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
 
     rcu_read_lock();
     mr = address_space_translate(&address_space_memory,
-                                 phys_addr, &phys_addr, &l, false);
+                                 phys_addr, &phys_addr, &l, false,
+                                 MEMTXATTRS_UNSPECIFIED);
 
     res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
     rcu_read_unlock();
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -XXX,XX +XXX,XX @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
      */
     mr = address_space_translate(&address_space_memory,
                                  iotlb->translated_addr,
-                                 &xlat, &len, writable);
+                                 &xlat, &len, writable,
+                                 MEMTXATTRS_UNSPECIFIED);
     if (!memory_region_is_ram(mr)) {
         error_report("iommu map to non memory area %"HWADDR_PRIx"",
                      xlat);
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 4 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 8 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (!IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, false);
+    mr = TRANSLATE(addr, &addr1, &l, false, attrs);
     if (l < 2 || !IS_DIRECT(mr, false)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 4 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (!IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
@@ -XXX,XX +XXX,XX @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 2 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
@@ -XXX,XX +XXX,XX @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
     bool release_lock = false;
 
     RCU_READ_LOCK();
-    mr = TRANSLATE(addr, &addr1, &l, true);
+    mr = TRANSLATE(addr, &addr1, &l, true, attrs);
     if (l < 8 || !IS_DIRECT(mr, true)) {
         release_lock |= prepare_mmio_access(mr);
 
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -XXX,XX +XXX,XX @@ restart:
                 MemoryRegion *mr;
                 hwaddr l = sizeof(target_ulong), addr1;
                 mr = address_space_translate(cs->as, pte_addr,
-                    &addr1, &l, false);
+                    &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
                 if (memory_access_is_direct(mr, true)) {
                     target_ulong *pte_pa =
                         qemu_map_ram_ptr(mr->ram_block, addr1);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_map().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
---
 include/exec/memory.h   | 3 ++-
 include/sysemu/dma.h    | 3 ++-
 exec.c                  | 6 ++++--
 target/ppc/mmu-hash64.c | 3 ++-
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
  * @addr: address within that address space
  * @plen: pointer to length of buffer; updated on return
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
 void *address_space_map(AddressSpace *as, hwaddr addr,
-                        hwaddr *plen, bool is_write);
+                        hwaddr *plen, bool is_write, MemTxAttrs attrs);
 
 /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline void *dma_memory_map(AddressSpace *as,
     hwaddr xlen = *len;
     void *p;
 
-    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
+    p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
+                          MEMTXATTRS_UNSPECIFIED);
     *len = xlen;
     return p;
 }
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
 void *address_space_map(AddressSpace *as,
                         hwaddr addr,
                         hwaddr *plen,
-                        bool is_write)
+                        bool is_write,
+                        MemTxAttrs attrs)
 {
     hwaddr len = *plen;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ void *cpu_physical_memory_map(hwaddr addr,
                               hwaddr *plen,
                               int is_write)
 {
-    return address_space_map(&address_space_memory, addr, plen, is_write);
+    return address_space_map(&address_space_memory, addr, plen, is_write,
+                             MEMTXATTRS_UNSPECIFIED);
 }
 
 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -XXX,XX +XXX,XX @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
         return NULL;
     }
 
-    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
+    hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
+                              MEMTXATTRS_UNSPECIFIED);
     if (plen < (n * HASH_PTE_SIZE_64)) {
         hw_error("%s: Unable to map all requested HPTEs\n", __func__);
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
---
 include/exec/memory.h      | 4 +++-
 include/sysemu/dma.h       | 3 ++-
 exec.c                     | 3 ++-
 target/s390x/diag.c        | 6 ++++--
 target/s390x/excp_helper.c | 3 ++-
 target/s390x/mmu_helper.c  | 3 ++-
 target/s390x/sigp.c        | 3 ++-
 7 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
  * @addr: address within that address space
  * @len: length of the area to be checked
  * @is_write: indicates the transfer direction
+ * @attrs: memory attributes
  */
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
+                                bool is_write, MemTxAttrs attrs);
 
 /* address_space_map: map a physical memory region into a host virtual address
  *
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -XXX,XX +XXX,XX @@ static inline bool dma_memory_valid(AddressSpace *as,
                                     DMADirection dir)
 {
     return address_space_access_valid(as, addr, len,
-                                      dir == DMA_DIRECTION_FROM_DEVICE);
+                                      dir == DMA_DIRECTION_FROM_DEVICE,
+                                      MEMTXATTRS_UNSPECIFIED);
 }
 
 static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
 }
 
 bool address_space_access_valid(AddressSpace *as, hwaddr addr,
-                                int len, bool is_write)
+                                int len, bool is_write,
+                                MemTxAttrs attrs)
 {
     FlatView *fv;
     bool result;
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/diag.c
+++ b/target/s390x/diag.c
@@ -XXX,XX +XXX,XX @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), false)) {
+                                        sizeof(IplParameterBlock), false,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
@@ -XXX,XX +XXX,XX @@ out:
             return;
         }
         if (!address_space_access_valid(&address_space_memory, addr,
-                                        sizeof(IplParameterBlock), true)) {
+                                        sizeof(IplParameterBlock), true,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
             return;
         }
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -XXX,XX +XXX,XX @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
 
     /* check out of RAM access */
     if (!address_space_access_valid(&address_space_memory, raddr,
-                                    TARGET_PAGE_SIZE, rw)) {
+                                    TARGET_PAGE_SIZE, rw,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
                 (uint64_t)raddr, (uint64_t)ram_size);
         trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -XXX,XX +XXX,XX @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
             return ret;
         }
         if (!address_space_access_valid(&address_space_memory, pages[i],
-                                        TARGET_PAGE_SIZE, is_write)) {
+                                        TARGET_PAGE_SIZE, is_write,
+                                        MEMTXATTRS_UNSPECIFIED)) {
             trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
             return -EFAULT;
         }
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index XXXXXXX..XXXXXXX 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -XXX,XX +XXX,XX @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
     cpu_synchronize_state(cs);
 
     if (!address_space_access_valid(&address_space_memory, addr,
-                                    sizeof(struct LowCore), false)) {
+                                    sizeof(struct LowCore), false,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
         return;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_extend_translation().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
 static hwaddr
 flatview_extend_translation(FlatView *fv, hwaddr addr,
-                                 hwaddr target_len,
-                                 MemoryRegion *mr, hwaddr base, hwaddr len,
-                                 bool is_write)
+                            hwaddr target_len,
+                            MemoryRegion *mr, hwaddr base, hwaddr len,
+                            bool is_write, MemTxAttrs attrs)
 {
     hwaddr done = 0;
     hwaddr xlat;
@@ -XXX,XX +XXX,XX @@ void *address_space_map(AddressSpace *as,
 
     memory_region_ref(mr);
     *plen = flatview_extend_translation(fv, addr, len, mr, xlat,
-                                             l, is_write);
+                                        l, is_write, attrs);
     ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
     rcu_read_unlock();
 
@@ -XXX,XX +XXX,XX @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
     mr = cache->mrs.mr;
     memory_region_ref(mr);
     if (memory_access_is_direct(mr, is_write)) {
+        /* We don't care about the memory attributes here as we're only
+         * doing this if we found actual RAM, which behaves the same
+         * regardless of attributes; so UNSPECIFIED is fine.
+         */
         l = flatview_extend_translation(cache->fv, addr, len, mr,
-                                        cache->xlat, l, is_write);
+                                        cache->xlat, l, is_write,
+                                        MEMTXATTRS_UNSPECIFIED);
         cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
     } else {
         cache->ptr = NULL;
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to memory_region_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.

The callsite in flatview_access_valid() is part of a recursive
loop flatview_access_valid() -> memory_region_access_valid() ->
 subpage_accepts() -> flatview_access_valid(); we make it pass
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
have plumbed an attrs parameter through the rest of the loop
and we can add an attrs parameter to flatview_access_valid().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
---
 include/exec/memory-internal.h | 3 ++-
 exec.c                         | 4 +++-
 hw/s390x/s390-pci-inst.c       | 3 ++-
 memory.c                       | 7 ++++---
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -XXX,XX +XXX,XX @@ void flatview_unref(FlatView *view);
 extern const MemoryRegionOps unassigned_mem_ops;
 
 bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
-                                unsigned size, bool is_write);
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs);
 
 void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
 AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            if (!memory_region_access_valid(mr, xlat, l, is_write)) {
+            /* When our callers all have attrs we'll pass them through here */
+            if (!memory_region_access_valid(mr, xlat, l, is_write,
+                                            MEMTXATTRS_UNSPECIFIED)) {
                 return false;
             }
         }
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -XXX,XX +XXX,XX @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
     mr = s390_get_subregion(mr, offset, len);
     offset -= mr->addr;
 
-    if (!memory_region_access_valid(mr, offset, len, true)) {
+    if (!memory_region_access_valid(mr, offset, len, true,
+                                    MEMTXATTRS_UNSPECIFIED)) {
         s390_program_interrupt(env, PGM_OPERAND, 6, ra);
         return 0;
     }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps ram_device_mem_ops = {
 bool memory_region_access_valid(MemoryRegion *mr,
                                 hwaddr addr,
                                 unsigned size,
-                                bool is_write)
+                                bool is_write,
+                                MemTxAttrs attrs)
 {
     int access_size_min, access_size_max;
     int access_size, i;
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
 {
     MemTxResult r;
 
-    if (!memory_region_access_valid(mr, addr, size, false)) {
+    if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
         *pval = unassigned_mem_read(mr, addr, size);
         return MEMTX_DECODE_ERROR;
     }
@@ -XXX,XX +XXX,XX @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
                                          unsigned size,
                                          MemTxAttrs attrs)
 {
-    if (!memory_region_access_valid(mr, addr, size, true)) {
+    if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
         unassigned_mem_write(mr, addr, data, size);
         return MEMTX_DECODE_ERROR;
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
callback. We'll need this for subpage_accepts().

We could take the approach we used with the read and write
callbacks and add new a new _with_attrs version, but since there
are so few implementations of the accepts hook we just change
them all.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
---
 include/exec/memory.h |  3 ++-
 exec.c                |  9 ++++++---
 hw/hppa/dino.c        |  3 ++-
 hw/nvram/fw_cfg.c     | 12 ++++++++----
 hw/scsi/esp.c         |  3 ++-
 hw/xen/xen_pt_msi.c   |  3 ++-
 memory.c              |  5 +++--
 7 files changed, 25 insertions(+), 13 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionOps {
          * as a machine check exception).
          */
         bool (*accepts)(void *opaque, hwaddr addr,
-                        unsigned size, bool is_write);
+                        unsigned size, bool is_write,
+                        MemTxAttrs attrs);
     } valid;
     /* Internal implementation constraints: */
     struct {
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
 }
 
 static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
@@ -XXX,XX +XXX,XX @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
 }
 
 static bool subpage_accepts(void *opaque, hwaddr addr,
-                            unsigned len, bool is_write)
+                            unsigned len, bool is_write,
+                            MemTxAttrs attrs)
 {
     subpage_t *subpage = opaque;
 #if defined(DEBUG_SUBPAGE)
@@ -XXX,XX +XXX,XX @@ static void readonly_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool readonly_mem_accepts(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write;
 }
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/hppa/dino.c
+++ b/hw/hppa/dino.c
@@ -XXX,XX +XXX,XX @@ static void gsc_to_pci_forwarding(DinoState *s)
 }
 
 static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
-                                unsigned size, bool is_write)
+                                unsigned size, bool is_write,
+                                MemTxAttrs attrs)
 {
     switch (addr) {
     case DINO_IAR0:
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
                          (size == 8 && addr == 0));
 }
 
 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                                  unsigned size, bool is_write,
+                                  MemTxAttrs attrs)
 {
     return addr == 0;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
-                                 unsigned size, bool is_write)
+                                 unsigned size, bool is_write,
+                                 MemTxAttrs attrs)
 {
     return is_write && size == 2;
 }
@@ -XXX,XX +XXX,XX @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
 }
 
 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
-                                  unsigned size, bool is_write)
+                              unsigned size, bool is_write,
+                              MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 2);
 }
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -XXX,XX +XXX,XX @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 }
 
 static bool esp_mem_accepts(void *opaque, hwaddr addr,
-                            unsigned size, bool is_write)
+                            unsigned size, bool is_write,
+                            MemTxAttrs attrs)
 {
     return (size == 1) || (is_write && size == 4);
 }
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/xen/xen_pt_msi.c
+++ b/hw/xen/xen_pt_msi.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
 }
 
 static bool pci_msix_accepts(void *opaque, hwaddr addr,
-                             unsigned size, bool is_write)
+                             unsigned size, bool is_write,
+                             MemTxAttrs attrs)
 {
     return !(addr & (size - 1));
 }
diff --git a/memory.c b/memory.c
index XXXXXXX..XXXXXXX 100644
--- a/memory.c
+++ b/memory.c
@@ -XXX,XX +XXX,XX @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
 }
 
 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
-                                   unsigned size, bool is_write)
+                                   unsigned size, bool is_write,
+                                   MemTxAttrs attrs)
 {
     return false;
 }
@@ -XXX,XX +XXX,XX @@ bool memory_region_access_valid(MemoryRegion *mr,
     access_size = MAX(MIN(size, access_size_max), access_size_min);
     for (i = 0; i < size; i += access_size) {
         if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
-                                    is_write)) {
+                                    is_write, attrs)) {
             return false;
         }
     }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_access_valid().
Its callers now all have an attrs value to hand, so we can
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
 static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
                                   const uint8_t *buf, int len);
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write);
+                                  bool is_write, MemTxAttrs attrs);
 
 static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
                                 unsigned len, MemTxAttrs attrs)
@@ -XXX,XX +XXX,XX @@ static bool subpage_accepts(void *opaque, hwaddr addr,
 #endif
 
     return flatview_access_valid(subpage->fv, addr + subpage->base,
-                                 len, is_write);
+                                 len, is_write, attrs);
 }
 
 static const MemoryRegionOps subpage_ops = {
@@ -XXX,XX +XXX,XX @@ static void cpu_notify_map_clients(void)
 }
 
 static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
-                                  bool is_write)
+                                  bool is_write, MemTxAttrs attrs)
 {
     MemoryRegion *mr;
     hwaddr l, xlat;
@@ -XXX,XX +XXX,XX @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
         mr = flatview_translate(fv, addr, &xlat, &l, is_write);
         if (!memory_access_is_direct(mr, is_write)) {
             l = memory_access_size(mr, l, addr);
-            /* When our callers all have attrs we'll pass them through here */
-            if (!memory_region_access_valid(mr, xlat, l, is_write,
-                                            MEMTXATTRS_UNSPECIFIED)) {
+            if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
                 return false;
             }
         }
@@ -XXX,XX +XXX,XX @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
 
     rcu_read_lock();
     fv = address_space_to_flatview(as);
-    result = flatview_access_valid(fv, addr, len, is_write);
+    result = flatview_access_valid(fv, addr, len, is_write, attrs);
     rcu_read_unlock();
     return result;
 }
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_translate(); all its
callers now have attrs available.

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_get_iotlb_entry().

diff --git a/include/exec/memory.h b/include/exec/memory.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -XXX,XX +XXX,XX @@ void address_space_cache_destroy(MemoryRegionCache *cache);
  * entry. Should be called from an RCU critical section.
  */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write);
+                                            bool is_write, MemTxAttrs attrs);
 
 /* address_space_translate: translate an address range into an address space
  * into a MemoryRegion and an address range into that section.  Should be
diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
 
 /* Called from RCU critical section */
 IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
-                                            bool is_write)
+                                            bool is_write, MemTxAttrs attrs)
 {
     MemoryRegionSection section;
     hwaddr xlat, page_mask;
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -XXX,XX +XXX,XX @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
     trace_vhost_iotlb_miss(dev, 1);
 
     iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
-                                          iova, write);
+                                          iova, write,
+                                          MEMTXATTRS_UNSPECIFIED);
     if (iotlb.target_as != NULL) {
         ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
                                          &uaddr, &len);
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_do_translate().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ unassigned:
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: memory transaction attributes
  *
  * This function is called from RCU critical section
  */
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
                                                  hwaddr *page_mask_out,
                                                  bool is_write,
                                                  bool is_mmio,
-                                                 AddressSpace **target_as)
+                                                 AddressSpace **target_as,
+                                                 MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     IOMMUMemoryRegion *iommu_mr;
@@ -XXX,XX +XXX,XX @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
      * but page mask.
      */
     section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
-                                    NULL, &page_mask, is_write, false, &as);
+                                    NULL, &page_mask, is_write, false, &as,
+                                    attrs);
 
     /* Illegal translation */
     if (section.mr == &io_mem_unassigned) {
@@ -XXX,XX +XXX,XX @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
 
     /* This can be MMIO, so setup MMIO bit. */
     section = flatview_do_translate(fv, addr, xlat, plen, NULL,
-                                    is_write, true, &as);
+                                    is_write, true, &as, attrs);
     mr = section.mr;
 
     if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
-- 
2.17.1

As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate_iommu().

diff --git a/exec.c b/exec.c
index XXXXXXX..XXXXXXX 100644
--- a/exec.c
+++ b/exec.c
@@ -XXX,XX +XXX,XX @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
  * @is_write: whether the translation operation is for write
  * @is_mmio: whether this can be MMIO, set true if it can
  * @target_as: the address space targeted by the IOMMU
+ * @attrs: transaction attributes
  *
  * This function is called from RCU critical section.  It is the common
  * part of flatview_do_translate and address_space_translate_cached.
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
                                                          hwaddr *page_mask_out,
                                                          bool is_write,
                                                          bool is_mmio,
-                                                         AddressSpace **target_as)
+                                                         AddressSpace **target_as,
+                                                         MemTxAttrs attrs)
 {
     MemoryRegionSection *section;
     hwaddr page_mask = (hwaddr)-1;
@@ -XXX,XX +XXX,XX @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
         return address_space_translate_iommu(iommu_mr, xlat,
                                              plen_out, page_mask_out,
                                              is_write, is_mmio,
-                                             target_as);
+                                             target_as, attrs);
     }
     if (page_mask_out) {
         /* Not behind an IOMMU, use default page size. */
@@ -XXX,XX +XXX,XX @@ static inline MemoryRegion *address_space_translate_cached(
 
     section = address_space_translate_iommu(iommu_mr, xlat, plen,
                                             NULL, is_write, true,
-                                            &target_as);
+                                            &target_as, attrs);
     return section.mr;
 }
 
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. So previous
pointer could not be used any more. It must update the pointer and use
the new one.

Also, previous codes wrongly use le32 conversion of iort->node_offset
for subsequent computations that will result incorrect value if host is
not litlle endian. So use the non-converted one instead.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
     AcpiIortItsGroup *its;
     AcpiIortTable *iort;
     AcpiIortSmmu3 *smmu;
-    size_t node_size, iort_length, smmu_offset = 0;
+    size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
     AcpiIortRC *rc;
 
     iort = acpi_data_push(table_data, sizeof(*iort));
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
 
     iort_length = sizeof(*iort);
     iort->node_count = cpu_to_le32(nb_nodes);
-    iort->node_offset = cpu_to_le32(sizeof(*iort));
+    /*
+     * Use a copy in case table_data->data moves during acpi_data_push
+     * operations.
+     */
+    iort_node_offset = sizeof(*iort);
+    iort->node_offset = cpu_to_le32(iort_node_offset);
 
     /* ITS group node */
     node_size =  sizeof(*its) + sizeof(uint32_t);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         int irq =  vms->irqmap[VIRT_SMMU];
 
         /* SMMUv3 node */
-        smmu_offset = iort->node_offset + node_size;
+        smmu_offset = iort_node_offset + node_size;
         node_size = sizeof(*smmu) + sizeof(*idmap);
         iort_length += node_size;
         smmu = acpi_data_push(table_data, node_size);
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->id_count = cpu_to_le32(0xFFFF);
         idmap->output_base = 0;
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
     /* Root Complex Node */
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         idmap->output_reference = cpu_to_le32(smmu_offset);
     } else {
         /* output IORT node is the ITS group node (the first node) */
-        idmap->output_reference = cpu_to_le32(iort->node_offset);
+        idmap->output_reference = cpu_to_le32(iort_node_offset);
     }
 
+    /*
+     * Update the pointer address in case table_data->data moves during above
+     * acpi_data_push operations.
+     */
+    iort = (AcpiIortTable *)(table_data->data + iort_start);
     iort->length = cpu_to_le32(iort_length);
 
     build_header(linker, table_data, (void *)(table_data->data + iort_start),
-- 
2.17.1

From: Shannon Zhao <zhaoshenglong@huawei.com>

kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
initialize global capability variables. If we call kvm_init_irq_routing in
GIC realize function, previous allocated memory will leak.

Fix this by deleting the unnecessary call.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic_kvm.c   | 1 -
 hw/intc/arm_gicv3_kvm.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
 
     if (kvm_has_gsi_routing()) {
         /* set up irq routing */
-        kvm_init_irq_routing(kvm_state);
         for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
             kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
         }
-- 
2.17.1

Some Arm bugfixes for rc2...

thanks
-- PMM

The following changes since commit e6ebbd46b6e539f3613136111977721d212c2812:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-11-19 14:31:48 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181119

for you to fetch changes up to a00d7f2048c2a1a6a4487ac195c804c78adcf60e:

MAINTAINERS: list myself as maintainer for various Arm boards (2018-11-19 15:55:11 +0000)

----------------------------------------------------------------
target-arm queue:
 * various MAINTAINERS file updates
 * hw/block/onenand: use qemu_log_mask() for reporting
 * hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
   on the n800 and n810 machine models
 * target/arm: fix smc incorrectly trapping to EL3 when secure is off
 * hw/arm/stm32f205: Fix the UART and Timer region size
 * target/arm: read ID registers for KVM guests so they can be
   used to gate "is feature X present" checks

----------------------------------------------------------------
Luc Michel (1):
      target/arm: fix smc incorrectly trapping to EL3 when secure is off

Peter Maydell (3):
      hw/block/onenand: Fix off-by-one error allowing out-of-bounds read
      hw/block/onenand: use qemu_log_mask() for reporting
      MAINTAINERS: list myself as maintainer for various Arm boards

Richard Henderson (4):
      target/arm: Install ARMISARegisters from kvm host
      target/arm: Fill in ARMISARegisters for kvm64
      target/arm: Introduce read_sys_reg32 for kvm32
      target/arm: Fill in ARMISARegisters for kvm32

Seth Kintigh (1):
      hw/arm/stm32f205: Fix the UART and Timer region size

Thomas Huth (1):
      MAINTAINERS: Add entries for missing ARM boards

target/arm/kvm_arm.h       |   1 +
 hw/block/onenand.c         |  24 +++++-----
 hw/char/stm32f2xx_usart.c  |   2 +-
 hw/timer/stm32f2xx_timer.c |   2 +-
 target/arm/kvm.c           |   1 +
 target/arm/kvm32.c         |  77 ++++++++++++++++++++------------
 target/arm/kvm64.c         |  90 +++++++++++++++++++++++++++++++++++++-
 target/arm/op_helper.c     |  54 +++++++++++++++++++----
 MAINTAINERS                | 106 +++++++++++++++++++++++++++++++++++++++------
 9 files changed, 293 insertions(+), 64 deletions(-)

From: Richard Henderson <richard.henderson@linaro.org>

The ID registers are replacing (some of) the feature bits.
We need (some of) these values to determine the set of data
to be handled during migration.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm_arm.h | 1 +
 target/arm/kvm.c     | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -XXX,XX +XXX,XX @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
  * by asking the host kernel)
  */
 typedef struct ARMHostCPUFeatures {
+    ARMISARegisters isar;
     uint64_t features;
     uint32_t target;
     const char *dtb_compatible;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
 
     cpu->kvm_target = arm_host_cpu_features.target;
     cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible;
+    cpu->isar = arm_host_cpu_features.isar;
     env->features = arm_host_cpu_features.features;
 }
 
-- 
2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm64.c | 90 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 88 insertions(+), 2 deletions(-)

diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ static inline void unset_feature(uint64_t *features, int feature)
     *features &= ~(1ULL << feature);
 }
 
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
+{
+    uint64_t ret;
+    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
+    int err;
+
+    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
+    err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
+    if (err < 0) {
+        return -1;
+    }
+    *pret = ret;
+    return 0;
+}
+
+static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
+{
+    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
+
+    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
+    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
+}
+
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 {
     /* Identify the feature bits corresponding to the host CPU, and
      * fill out the ARMHostCPUClass fields accordingly. To do this
      * we have to create a scratch VM, create a single CPU inside it,
      * and then query that CPU for the relevant ID registers.
-     * For AArch64 we currently don't care about ID registers at
-     * all; we just want to know the CPU type.
      */
     int fdarray[3];
     uint64_t features = 0;
+    int err;
+
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
      * we know these will only support creating one kind of guest CPU,
      * which is its preferred CPU type. Fortunately these old kernels
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     ahcf->target = init.target;
     ahcf->dtb_compatible = "arm,arm-v8";
 
+    err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
+                         ARM64_SYS_REG(3, 0, 0, 4, 0));
+    if (unlikely(err < 0)) {
+        /*
+         * Before v4.15, the kernel only exposed a limited number of system
+         * registers, not including any of the interesting AArch64 ID regs.
+         * For the most part we could leave these fields as zero with minimal
+         * effect, since this does not affect the values seen by the guest.
+         *
+         * However, it could cause problems down the line for QEMU,
+         * so provide a minimal v8.0 default.
+         *
+         * ??? Could read MIDR and use knowledge from cpu64.c.
+         * ??? Could map a page of memory into our temp guest and
+         *     run the tiniest of hand-crafted kernels to extract
+         *     the values seen by the guest.
+         * ??? Either of these sounds like too much effort just
+         *     to work around running a modern host kernel.
+         */
+        ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
+        err = 0;
+    } else {
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
+                              ARM64_SYS_REG(3, 0, 0, 4, 1));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
+                              ARM64_SYS_REG(3, 0, 0, 6, 0));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
+                              ARM64_SYS_REG(3, 0, 0, 6, 1));
+
+        /*
+         * Note that if AArch32 support is not present in the host,
+         * the AArch32 sysregs are present to be read, but will
+         * return UNKNOWN values.  This is neither better nor worse
+         * than skipping the reads and leaving 0, as we must avoid
+         * considering the values in every case.
+         */
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
+                              ARM64_SYS_REG(3, 0, 0, 2, 0));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
+                              ARM64_SYS_REG(3, 0, 0, 2, 1));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
+                              ARM64_SYS_REG(3, 0, 0, 2, 2));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
+                              ARM64_SYS_REG(3, 0, 0, 2, 3));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
+                              ARM64_SYS_REG(3, 0, 0, 2, 4));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
+                              ARM64_SYS_REG(3, 0, 0, 2, 5));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
+                              ARM64_SYS_REG(3, 0, 0, 2, 7));
+
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
+                              ARM64_SYS_REG(3, 0, 0, 3, 0));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
+                              ARM64_SYS_REG(3, 0, 0, 3, 1));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
+                              ARM64_SYS_REG(3, 0, 0, 3, 2));
+    }
+
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
+    if (err < 0) {
+        return false;
+    }
+
    /* We can assume any KVM supporting CPU is at least a v8
      * with VFPv4+Neon; this in turn implies most of the other
      * feature bits.
-- 
2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

Assert that the value to be written is the correct size.
No change in functionality here, just mirroring the same
function from kvm64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm32.c | 41 ++++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 25 deletions(-)

diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ static inline void set_feature(uint64_t *features, int feature)
     *features |= 1ULL << feature;
 }
 
+static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
+{
+    struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
+
+    assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
+    return ioctl(fd, KVM_GET_ONE_REG, &idreg);
+}
+
 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 {
     /* Identify the feature bits corresponding to the host CPU, and
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      * we have to create a scratch VM, create a single CPU inside it,
      * and then query that CPU for the relevant ID registers.
      */
-    int i, ret, fdarray[3];
+    int err = 0, fdarray[3];
     uint32_t midr, id_pfr0, mvfr1;
     uint64_t features = 0;
+
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
      * we know these will only support creating one kind of guest CPU,
      * which is its preferred CPU type.
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
         QEMU_KVM_ARM_TARGET_NONE
     };
     struct kvm_vcpu_init init;
-    struct kvm_one_reg idregs[] = {
-        {
-            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
-            | ENCODE_CP_REG(15, 0, 0, 0, 0, 0, 0),
-            .addr = (uintptr_t)&midr,
-        },
-        {
-            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
-            | ENCODE_CP_REG(15, 0, 0, 0, 1, 0, 0),
-            .addr = (uintptr_t)&id_pfr0,
-        },
-        {
-            .id = KVM_REG_ARM | KVM_REG_SIZE_U32
-            | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1,
-            .addr = (uintptr_t)&mvfr1,
-        },
-    };
 
     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
         return false;
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      */
     ahcf->dtb_compatible = "arm,arm-v7";
 
-    for (i = 0; i < ARRAY_SIZE(idregs); i++) {
-        ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]);
-        if (ret) {
-            break;
-        }
-    }
+    err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
+    err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
+    err |= read_sys_reg32(fdarray[2], &mvfr1,
+                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
+                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
-    if (ret) {
+    if (err < 0) {
         return false;
     }
 
-- 
2.19.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/kvm32.c | 40 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 35 insertions(+), 5 deletions(-)

diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
      * and then query that CPU for the relevant ID registers.
      */
     int err = 0, fdarray[3];
-    uint32_t midr, id_pfr0, mvfr1;
+    uint32_t midr, id_pfr0;
     uint64_t features = 0;
 
     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
 
     err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
     err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
-    err |= read_sys_reg32(fdarray[2], &mvfr1,
+
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
+                          ARM_CP15_REG32(0, 0, 2, 0));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
+                          ARM_CP15_REG32(0, 0, 2, 1));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
+                          ARM_CP15_REG32(0, 0, 2, 2));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
+                          ARM_CP15_REG32(0, 0, 2, 3));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
+                          ARM_CP15_REG32(0, 0, 2, 4));
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
+                          ARM_CP15_REG32(0, 0, 2, 5));
+    if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
+                       ARM_CP15_REG32(0, 0, 2, 7))) {
+        /*
+         * Older kernels don't support reading ID_ISAR6. This register was
+         * only introduced in ARMv8, so we can assume that it is zero on a
+         * CPU that a kernel this old is running on.
+         */
+        ahcf->isar.id_isar6 = 0;
+    }
+
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
+                          KVM_REG_ARM | KVM_REG_SIZE_U32 |
+                          KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
+    err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
+    /*
+     * FIXME: There is not yet a way to read MVFR2.
+     * Fortunately there is not yet anything in there that affects migration.
+     */
 
     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     if (extract32(id_pfr0, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_THUMB2EE);
     }
-    if (extract32(mvfr1, 20, 4) == 1) {
+    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
         set_feature(&features, ARM_FEATURE_VFP_FP16);
     }
-    if (extract32(mvfr1, 12, 4) == 1) {
+    if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_NEON);
     }
-    if (extract32(mvfr1, 28, 4) == 1) {
+    if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
         /* FMAC support implies VFPv4 */
         set_feature(&features, ARM_FEATURE_VFP4);
     }
-- 
2.19.1

From: Thomas Huth <thuth@redhat.com>

Add entries for the boards "mcimx6ul-evk", "mcimx7d-sabre", "raspi2",
"raspi3", "sabrelite", "vexpress-a15", "vexpress-a9" and "virt".
While we're at it, also adjust the "i.MX31" section a little bit,
so that the wildcards there do not match anymore for unrelated files
(e.g. the new hw/misc/imx6ul_ccm.c file).

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1542184999-11145-1-git-send-email-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS | 70 +++++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 65 insertions(+), 5 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/arm/gumstix.c
 
-i.MX31
+i.MX31 (kzm)
 M: Peter Chubb <peter.chubb@nicta.com.au>
 L: qemu-arm@nongnu.org
-S: Odd fixes
-F: hw/*/imx*
-F: include/hw/*/imx*
+S: Odd Fixes
 F: hw/arm/kzm.c
-F: include/hw/arm/fsl-imx31.h
+F: hw/*/imx_*
+F: hw/*/*imx31*
+F: include/hw/*/imx_*
+F: include/hw/*/*imx31*
 
 Integrator CP
 M: Peter Maydell <peter.maydell@linaro.org>
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/arm/integratorcp.c
 F: hw/misc/arm_integrator_debug.c
 
+MCIMX6UL EVK / i.MX6ul
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/mcimx6ul-evk.c
+F: hw/arm/fsl-imx6ul.c
+F: hw/misc/imx6ul_ccm.c
+F: include/hw/arm/fsl-imx6ul.h
+F: include/hw/misc/imx6ul_ccm.h
+
+MCIMX7D SABRE / i.MX7
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Andrey Smirnov <andrew.smirnov@gmail.com>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/mcimx7d-sabre.c
+F: hw/arm/fsl-imx7.c
+F: include/hw/arm/fsl-imx7.h
+F: hw/pci-host/designware.c
+F: include/hw/pci-host/designware.h
+
 MPS2
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/palm.c
 
+Raspberry Pi
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Andrew Baumann <Andrew.Baumann@microsoft.com>
+R: Philippe Mathieu-Daudé <f4bug@amsat.org>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/raspi_platform.h
+F: hw/*/bcm283*
+F: include/hw/arm/raspi*
+F: include/hw/*/bcm283*
+
 Real View
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: hw/*/pxa2xx*
 F: hw/misc/mst_fpga.c
 F: include/hw/arm/pxa.h
 
+SABRELITE / i.MX6
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Jean-Christophe Dubois <jcd@tribudubois.net>
+L: qemu-arm@nongnu.org
+S: Odd Fixes
+F: hw/arm/sabrelite.c
+F: hw/arm/fsl-imx6.c
+F: hw/misc/imx6_src.c
+F: hw/ssi/imx_spi.c
+F: include/hw/arm/fsl-imx6.h
+F: include/hw/misc/imx6_src.h
+F: include/hw/ssi/imx_spi.h
+
 Sharp SL-5500 (Collie) PDA
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/stellaris*
 
+Versatile Express
+M: Peter Maydell <peter.maydell@linaro.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/vexpress.c
+
 Versatile PB
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/*/versatile*
 F: hw/misc/arm_sysctl.c
 
+Virt
+M: Peter Maydell <peter.maydell@linaro.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/virt*
+F: include/hw/arm/virt.h
+
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 M: Alistair Francis <alistair@alistair23.me>
-- 
2.19.1

From: Seth Kintigh <skintigh@gmail.com>

The UART and timer devices for the stm32f205 were being created
with memory regions that were too large. Use the size specified
in the chip datasheet.

The old sizes were so large that the devices would overlap with
each other in the SoC memory map, so this fixes a bug that
caused odd behavior and/or crashes when trying to set up multiple
UARTs.

Signed-off-by: Seth Kintigh <skintigh@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: rephrased commit message to follow our usual standard]
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/char/stm32f2xx_usart.c  | 2 +-
 hw/timer/stm32f2xx_timer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/stm32f2xx_usart.c
+++ b/hw/char/stm32f2xx_usart.c
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_init(Object *obj)
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 
     memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
-                          TYPE_STM32F2XX_USART, 0x2000);
+                          TYPE_STM32F2XX_USART, 0x400);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 }
 
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_timer_init(Object *obj)
     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 
     memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
-                          "stm32f2xx_timer", 0x4000);
+                          "stm32f2xx_timer", 0x400);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 
     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
-- 
2.19.1

From: Luc Michel <luc.michel@greensocs.com>

This commit fixes a case where the CPU would try to go to EL3 when
executing an smc instruction, even though ARM_FEATURE_EL3 is false. This
case is raised when the PSCI conduit is set to smc, but the smc
instruction does not lead to a valid PSCI call.

QEMU crashes with an assertion failure latter on because of incoherent
mmu_idx.

This commit refactors the pre_smc helper by enumerating all the possible
way of handling an scm instruction, and covering the previously missing
case leading to the crash.

The following minimal test would crash before this commit:

.global _start
    .text
_start:
    ldr x0, =0xdeadbeef  ; invalid PSCI call
    smc #0

run with the following command line:

aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \
                      -o test test.s

qemu-system-aarch64 -M virt,virtualization=on,secure=off \
                    -cpu cortex-a57 -kernel test

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20181117160213.18995-1-luc.michel@greensocs.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/op_helper.c | 54 +++++++++++++++++++++++++++++++++++-------
 1 file changed, 46 insertions(+), 8 deletions(-)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
     ARMCPU *cpu = arm_env_get_cpu(env);
     int cur_el = arm_current_el(env);
     bool secure = arm_is_secure(env);
-    bool smd = env->cp15.scr_el3 & SCR_SMD;
+    bool smd_flag = env->cp15.scr_el3 & SCR_SMD;
+
+    /*
+     * SMC behaviour is summarized in the following table.
+     * This helper handles the "Trap to EL2" and "Undef insn" cases.
+     * The "Trap to EL3" and "PSCI call" cases are handled in the exception
+     * helper.
+     *
+     *  -> ARM_FEATURE_EL3 and !SMD
+     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
+     *
+     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
+     *  Conduit SMC, inval call  Trap to EL2         Trap to EL3
+     *  Conduit not SMC          Trap to EL2         Trap to EL3
+     *
+     *
+     *  -> ARM_FEATURE_EL3 and SMD
+     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
+     *
+     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
+     *  Conduit SMC, inval call  Trap to EL2         Undef insn
+     *  Conduit not SMC          Trap to EL2         Undef insn
+     *
+     *
+     *  -> !ARM_FEATURE_EL3
+     *                           HCR_TSC && NS EL1   !HCR_TSC || !NS EL1
+     *
+     *  Conduit SMC, valid call  Trap to EL2         PSCI Call
+     *  Conduit SMC, inval call  Trap to EL2         Undef insn
+     *  Conduit not SMC          Undef insn          Undef insn
+     */
+
     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
      * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
      *  extensions, SMD only applies to NS state.
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
      * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
      * so we need not special case this here.
      */
-    bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
+    bool smd = arm_feature(env, ARM_FEATURE_AARCH64) ? smd_flag
+                                                     : smd_flag && !secure;
 
     if (!arm_feature(env, ARM_FEATURE_EL3) &&
         cpu->psci_conduit != QEMU_PSCI_CONDUIT_SMC) {
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
          * to forbid its EL1 from making PSCI calls into QEMU's
          * "firmware" via HCR.TSC, so for these purposes treat
          * PSCI-via-SMC as implying an EL3.
+         * This handles the very last line of the previous table.
          */
-        undef = true;
-    } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
+        raise_exception(env, EXCP_UDEF, syn_uncategorized(),
+                        exception_target_el(env));
+    }
+
+    if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
         /* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
          * We also want an EL2 guest to be able to forbid its EL1 from
          * making PSCI calls into QEMU's "firmware" via HCR.TSC.
+         * This handles all the "Trap to EL2" cases of the previous table.
          */
         raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
     }
 
-    /* If PSCI is enabled and this looks like a valid PSCI call then
-     * suppress the UNDEF -- we'll catch the SMC exception and
-     * implement the PSCI call behaviour there.
+    /* Catch the two remaining "Undef insn" cases of the previous table:
+     *    - PSCI conduit is SMC but we don't have a valid PCSI call,
+     *    - We don't have EL3 or SMD is set.
      */
-    if (undef && !arm_is_psci_call(cpu, EXCP_SMC)) {
+    if (!arm_is_psci_call(cpu, EXCP_SMC) &&
+        (smd || !arm_feature(env, ARM_FEATURE_EL3))) {
         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
                         exception_target_el(env));
     }
-- 
2.19.1

An off-by-one error in a switch case in onenand_read() allowed
a misbehaving guest to read off the end of a block of memory.

NB: the onenand device is used only by the "n800" and "n810"
machines, which are usable only with TCG, not KVM, so this is
not a security issue.

Reported-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20181115143535.5885-2-peter.maydell@linaro.org
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/onenand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/block/onenand.c b/hw/block/onenand.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/onenand.c
+++ b/hw/block/onenand.c
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
     int offset = addr >> s->shift;
 
     switch (offset) {
-    case 0x0000 ... 0xc000:
+    case 0x0000 ... 0xbffe:
         return lduw_le_p(s->boot[0] + addr);
 
     case 0xf000:	/* Manufacturer ID */
-- 
2.19.1

Update the onenand device to use qemu_log_mask() for reporting
guest errors and unimplemented features, rather than plain
fprintf() and hw_error().

(We leave the hw_error() in onenand_reset(), as that is
triggered by a failure to read the underlying block device
for the bootRAM, not by guest action.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20181115143535.5885-3-peter.maydell@linaro.org
---
 hw/block/onenand.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/hw/block/onenand.c b/hw/block/onenand.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/onenand.c
+++ b/hw/block/onenand.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "hw/sysbus.h"
 #include "qemu/error-report.h"
+#include "qemu/log.h"
 
 /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
 #define PAGE_SHIFT	11
@@ -XXX,XX +XXX,XX @@ static void onenand_command(OneNANDState *s)
     default:
         s->status |= ONEN_ERR_CMD;
         s->intstatus |= ONEN_INT;
-        fprintf(stderr, "%s: unknown OneNAND command %x\n",
-                        __func__, s->command);
+        qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n",
+                      s->command);
     }
 
     onenand_intr_update(s);
@@ -XXX,XX +XXX,XX @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
     case 0xff02:	/* ECC Result of spare area data */
     case 0xff03:	/* ECC Result of main area data */
     case 0xff04:	/* ECC Result of spare area data */
-        hw_error("%s: implement ECC\n", __func__);
+        qemu_log_mask(LOG_UNIMP,
+                      "onenand: ECC result registers unimplemented\n");
         return 0x0000;
     }
 
-    fprintf(stderr, "%s: unknown OneNAND register %x\n",
-                    __func__, offset);
+    qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n",
+                  offset);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
             break;
 
         default:
-            fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
-                            __func__, value);
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "unknown OneNAND boot command %" PRIx64 "\n",
+                          value);
         }
         break;
 
@@ -XXX,XX +XXX,XX @@ static void onenand_write(void *opaque, hwaddr addr,
         break;
 
     default:
-        fprintf(stderr, "%s: unknown OneNAND register %x\n",
-                        __func__, offset);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "write to unknown OneNAND register 0x%x\n",
+                      offset);
     }
 }
 
-- 
2.19.1

In practice for most of the more-or-less orphan Arm board models,
I will review patches and put them in via the target-arm tree.
So list myself as an "Odd Fixes" status maintainer for them.

This commit downgrades these boards to "Odd Fixes":
 * Allwinner-A10
 * Exynos
 * Calxeda Highbank
 * Canon DIGIC
 * Musicpal
 * nSeries
 * Palm
 * PXA2xx

These boards were already "Odd Fixes":
 * Gumstix
 * i.MX31 (kzm)

Philippe Mathieu-Daudé has requested to be moved to R:
status for Gumstix now that I am listed as the M: contact.

Some boards are maintained, but their patches still go
via the target-arm tree, so add myself as a secondary
maintainer contact for those:
 * Xilinx Zynq
 * Xilinx ZynqMP
 * STM32F205
 * Netduino 2
 * SmartFusion2
 * Mecraft M2S-FG484
 * ASPEED BMCs
 * NRF51

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20181108134139.31666-1-peter.maydell@linaro.org
---
 MAINTAINERS | 36 +++++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ ARM Machines
 ------------
 Allwinner-a10
 M: Beniamino Galvani <b.galvani@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/*/allwinner*
 F: include/hw/*/allwinner*
 F: hw/arm/cubieboard.c
@@ -XXX,XX +XXX,XX @@ F: tests/test-arm-mptimer.c
 
 Exynos
 M: Igor Mitsyanko <i.mitsyanko@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/*/exynos*
 F: include/hw/arm/exynos4210.h
 
 Calxeda Highbank
 M: Rob Herring <robh@kernel.org>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/highbank.c
 F: hw/net/xgmac.c
 
 Canon DIGIC
 M: Antony Pavlov <antonynpavlov@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: include/hw/arm/digic.h
 F: hw/*/digic*
 
 Gumstix
-M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+M: Peter Maydell <peter.maydell@linaro.org>
+R: Philippe Mathieu-Daudé <f4bug@amsat.org>
 L: qemu-devel@nongnu.org
 L: qemu-arm@nongnu.org
 S: Odd Fixes
@@ -XXX,XX +XXX,XX @@ F: hw/arm/gumstix.c
 
 i.MX31 (kzm)
 M: Peter Chubb <peter.chubb@nicta.com.au>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/arm/kzm.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/misc/iotkit-sysinfo.h
 
 Musicpal
 M: Jan Kiszka <jan.kiszka@web.de>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/musicpal.c
 
 nSeries
 M: Andrzej Zaborowski <balrogg@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/nseries.c
 
 Palm
 M: Andrzej Zaborowski <balrogg@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/palm.c
 
 Raspberry Pi
@@ -XXX,XX +XXX,XX @@ F: include/hw/intc/realview_gic.h
 
 PXA2XX
 M: Andrzej Zaborowski <balrogg@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
-S: Maintained
+S: Odd Fixes
 F: hw/arm/mainstone.c
 F: hw/arm/spitz.c
 F: hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/virt.h
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/xilinx_*
@@ -XXX,XX +XXX,XX @@ X: hw/ssi/xilinx_*
 Xilinx ZynqMP
 M: Alistair Francis <alistair@alistair23.me>
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/*/xlnx*.c
@@ -XXX,XX +XXX,XX @@ F: hw/arm/virt-acpi-build.c
 
 STM32F205
 M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/stm32f205_soc.c
 F: hw/misc/stm32f2xx_syscfg.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/*/stm32*.h
 
 Netduino 2
 M: Alistair Francis <alistair@alistair23.me>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/netduino2.c
 
 SmartFusion2
 M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/msf2-soc.c
 F: hw/misc/msf2-sysreg.c
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/mss-spi.h
 
 Emcraft M2S-FG484
 M: Subbaraya Sundeep <sundeep.lkml@gmail.com>
+M: Peter Maydell <peter.maydell@linaro.org>
 S: Maintained
 F: hw/arm/msf2-som.c
 
 ASPEED BMCs
 M: Cédric Le Goater <clg@kaod.org>
+M: Peter Maydell <peter.maydell@linaro.org>
 R: Andrew Jeffery <andrew@aj.id.au>
 R: Joel Stanley <joel@jms.id.au>
 L: qemu-arm@nongnu.org
@@ -XXX,XX +XXX,XX @@ F: include/hw/net/ftgmac100.h
 
 NRF51
 M: Joel Stanley <joel@jms.id.au>
+M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/nrf51_soc.c
-- 
2.19.1