[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/17] target-arm queue
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
1
Hi; here's a target-arm pullreq for rc0; these are all bugfixes
2
and similar minor stuff.
2
3
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
4
thanks
5
-- PMM
6
7
The following changes since commit 0462a32b4f63b2448b4a196381138afd50719dc4:
8
9
Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging (2025-03-14 09:31:13 +0800)
4
10
5
are available in the Git repository at:
11
are available in the Git repository at:
6
12
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250314-1
8
14
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
15
for you to fetch changes up to a019e15edfd62beae1e2f6adc0fa7415ba20b14c:
10
16
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
17
meson.build: Set RUST_BACKTRACE for all tests (2025-03-14 12:54:33 +0000)
12
18
13
----------------------------------------------------------------
19
----------------------------------------------------------------
14
target-arm queue:
20
target-arm queue:
15
* Fix coverity nit in int_to_float code
21
* Correctly handle corner cases of guest attempting an exception
16
* Don't set Invalid for float-to-int(MAXINT)
22
return to AArch32 when target EL is AArch64 only
17
* Fix fp_status_f16 tininess before rounding
23
* MAINTAINERS: Fix status for Arm boards I "maintain"
18
* Add various missing insns from the v8.2-FP16 extension
24
* tests/functional: Bump up arm_replay timeout
19
* Fix sqrt_f16 exception raising
25
* Revert "hw/char/pl011: Warn when using disabled receiver"
20
* sdcard: Correct CRC16 offset in sd_function_switch()
26
* util/cacheflush: Make first DSB unconditional on aarch64
21
* tcg: Optionally log FPU state in TCG -d cpu logging
27
* target/arm: Fix SVE/SME access check logic
28
* meson.build: Set RUST_BACKTRACE for all tests
22
29
23
----------------------------------------------------------------
30
----------------------------------------------------------------
24
Alex Bennée (5):
31
Joe Komlodi (1):
25
fpu/softfloat: int_to_float ensure r fully initialised
32
util/cacheflush: Make first DSB unconditional on aarch64
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
30
33
31
Peter Maydell (3):
34
Paolo Bonzini (1):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
35
Revert "hw/char/pl011: Warn when using disabled receiver"
33
target/arm: Fix fp_status_f16 tininess before rounding
34
tcg: Optionally log FPU state in TCG -d cpu logging
35
36
36
Philippe Mathieu-Daudé (1):
37
Peter Maydell (13):
37
sdcard: Correct CRC16 offset in sd_function_switch()
38
target/arm: Move A32_BANKED_REG_{GET,SET} macros to cpregs.h
39
target/arm: Un-inline access_secure_reg()
40
linux-user/aarch64: Remove unused get/put_user macros
41
linux-user/arm: Remove unused get_put_user macros
42
target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h
43
target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h
44
target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32
45
target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32
46
target/arm: Add cpu local variable to exception_return helper
47
target/arm: Forbid return to AArch32 when CPU is AArch64-only
48
MAINTAINERS: Fix status for Arm boards I "maintain"
49
tests/functional: Bump up arm_replay timeout
50
meson.build: Set RUST_BACKTRACE for all tests
38
51
39
Richard Henderson (7):
52
Richard Henderson (2):
40
target/arm: Implement FMOV (general) for fp16
53
target/arm: Make DisasContext.{fp, sve}_access_checked tristate
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
54
target/arm: Simplify pstate_sm check in sve_access_check
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
47
55
48
include/qemu/log.h | 1 +
56
MAINTAINERS | 14 ++--
49
target/arm/helper-a64.h | 2 +
57
meson.build | 9 ++-
50
target/arm/helper.h | 6 +
58
target/arm/cpregs.h | 28 +++++++
51
accel/tcg/cpu-exec.c | 9 +-
59
target/arm/cpu.h | 153 +-----------------------------------
52
fpu/softfloat.c | 6 +-
60
target/arm/internals.h | 135 +++++++++++++++++++++++++++++++
53
hw/sd/sd.c | 2 +-
61
target/arm/tcg/translate-a64.h | 2 +-
54
target/arm/cpu.c | 2 +
62
target/arm/tcg/translate.h | 10 ++-
55
target/arm/helper-a64.c | 10 ++
63
hw/char/pl011.c | 19 ++---
56
target/arm/helper.c | 38 +++-
64
hw/intc/arm_gicv3_cpuif.c | 1 +
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
65
linux-user/aarch64/cpu_loop.c | 48 -----------
58
util/log.c | 2 +
66
linux-user/arm/cpu_loop.c | 43 +---------
59
11 files changed, 428 insertions(+), 71 deletions(-)
67
target/arm/arch_dump.c | 1 +
60
68
target/arm/helper.c | 16 +++-
69
target/arm/tcg/helper-a64.c | 12 ++-
70
target/arm/tcg/hflags.c | 9 +++
71
target/arm/tcg/translate-a64.c | 37 ++++-----
72
util/cacheflush.c | 4 +-
73
.gitlab-ci.d/buildtest-template.yml | 1 -
74
18 files changed, 257 insertions(+), 285 deletions(-)
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
[PULL 01/17] target/arm: Move A32_BANKED_REG_{GET, SET} macros to cpregs.h
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm;
2
move their definitions to cpregs.h. There's no need to have them
3
defined in all the code that includes cpu.h.
2
4
3
These were missed out from the rest of the half-precision work.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
target/arm/cpregs.h | 28 ++++++++++++++++++++++++++++
9
target/arm/cpu.h | 27 ---------------------------
10
2 files changed, 28 insertions(+), 27 deletions(-)
4
11
5
Cc: qemu-stable@nongnu.org
12
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
16
1 file changed, 25 insertions(+), 6 deletions(-)
17
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
14
--- a/target/arm/cpregs.h
21
+++ b/target/arm/translate-a64.c
15
+++ b/target/arm/cpregs.h
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
16
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
23
unsigned int mos, type, rm, cond, rn, rd;
17
return ri->opc1 == 4 || ri->opc1 == 5;
24
TCGv_i64 t_true, t_false, t_zero;
18
}
25
DisasCompare64 c;
19
26
+ TCGMemOp sz;
20
+/* Macros for accessing a specified CP register bank */
27
21
+#define A32_BANKED_REG_GET(_env, _regname, _secure) \
28
mos = extract32(insn, 29, 3);
22
+ ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
30
+ type = extract32(insn, 22, 2);
31
rm = extract32(insn, 16, 5);
32
cond = extract32(insn, 12, 4);
33
rn = extract32(insn, 5, 5);
34
rd = extract32(insn, 0, 5);
35
36
- if (mos || type > 1) {
37
+ if (mos) {
38
+ unallocated_encoding(s);
39
+ return;
40
+ }
41
+
23
+
42
+ switch (type) {
24
+#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
43
+ case 0:
25
+ do { \
44
+ sz = MO_32;
26
+ if (_secure) { \
45
+ break;
27
+ (_env)->cp15._regname##_s = (_val); \
46
+ case 1:
28
+ } else { \
47
+ sz = MO_64;
29
+ (_env)->cp15._regname##_ns = (_val); \
48
+ break;
30
+ } \
49
+ case 3:
31
+ } while (0)
50
+ sz = MO_16;
32
+
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
33
+/*
52
+ break;
34
+ * Macros for automatically accessing a specific CP register bank depending on
53
+ }
35
+ * the current secure state of the system. These macros are not intended for
54
+ /* fallthru */
36
+ * supporting instruction translation reads/writes as these are dependent
55
+ default:
37
+ * solely on the SCR.NS bit and not the mode.
56
unallocated_encoding(s);
38
+ */
57
return;
39
+#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
58
}
40
+ A32_BANKED_REG_GET((_env), _regname, \
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
41
+ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
60
return;
42
+
61
}
43
+#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
62
44
+ A32_BANKED_REG_SET((_env), _regname, \
63
- /* Zero extend sreg inputs to 64 bits now. */
45
+ (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
46
+ (_val))
65
t_true = tcg_temp_new_i64();
47
+
66
t_false = tcg_temp_new_i64();
48
#endif /* TARGET_ARM_CPREGS_H */
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
49
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
50
index XXXXXXX..XXXXXXX 100644
69
+ read_vec_element(s, t_true, rn, 0, sz);
51
--- a/target/arm/cpu.h
70
+ read_vec_element(s, t_false, rm, 0, sz);
52
+++ b/target/arm/cpu.h
71
53
@@ -XXX,XX +XXX,XX @@ static inline bool access_secure_reg(CPUARMState *env)
72
a64_test_cc(&c, cond);
54
return ret;
73
t_zero = tcg_const_i64(0);
55
}
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
56
75
tcg_temp_free_i64(t_false);
57
-/* Macros for accessing a specified CP register bank */
76
a64_free_cc(&c);
58
-#define A32_BANKED_REG_GET(_env, _regname, _secure) \
77
59
- ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
78
- /* Note that sregs write back zeros to the high bits,
60
-
79
+ /* Note that sregs & hregs write back zeros to the high bits,
61
-#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
80
and we've already done the zero-extension. */
62
- do { \
81
write_fp_dreg(s, rd, t_true);
63
- if (_secure) { \
82
tcg_temp_free_i64(t_true);
64
- (_env)->cp15._regname##_s = (_val); \
65
- } else { \
66
- (_env)->cp15._regname##_ns = (_val); \
67
- } \
68
- } while (0)
69
-
70
-/* Macros for automatically accessing a specific CP register bank depending on
71
- * the current secure state of the system. These macros are not intended for
72
- * supporting instruction translation reads/writes as these are dependent
73
- * solely on the SCR.NS bit and not the mode.
74
- */
75
-#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
76
- A32_BANKED_REG_GET((_env), _regname, \
77
- (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
78
-
79
-#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
80
- A32_BANKED_REG_SET((_env), _regname, \
81
- (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
82
- (_val))
83
-
84
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
85
uint32_t cur_el, bool secure);
86
83
--
87
--
84
2.17.0
88
2.43.0
85
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
[PULL 02/17] target/arm: Un-inline access_secure_reg()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
We would like to move arm_el_is_aa64() to internals.h; however, it is
2
used by access_secure_reg(). Make that function not be inline, so
3
that it can stay in cpu.h.
2
4
3
We missed all of the scalar fp16 fma operations.
5
access_secure_reg() is used only in two places:
6
* in hflags.c
7
* in the user-mode arm emulators, to decide whether to store
8
the TLS value in the secure or non-secure banked field
4
9
5
Cc: qemu-stable@nongnu.org
10
The second of these is not on a super-hot path that would care about
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
the inlining (and incidentally will always use the NS banked field
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
because our user-mode CPUs never set ARM_FEATURE_EL3); put the
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
definition of access_secure_reg() in hflags.c, near its only use
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
14
inside target/arm.
15
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
---
18
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
19
target/arm/cpu.h | 12 +++---------
13
1 file changed, 48 insertions(+)
20
target/arm/tcg/hflags.c | 9 +++++++++
21
2 files changed, 12 insertions(+), 9 deletions(-)
14
22
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
25
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate-a64.c
26
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
27
@@ -XXX,XX +XXX,XX @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
20
tcg_temp_free_i64(tcg_res);
28
return aa64;
21
}
29
}
22
30
23
+/* Floating-point data-processing (3 source) - half precision */
31
-/* Function for determining whether guest cp register reads and writes should
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
32
+/*
25
+ int rd, int rn, int rm, int ra)
33
+ * Function for determining whether guest cp register reads and writes should
34
* access the secure or non-secure bank of a cp register. When EL3 is
35
* operating in AArch32 state, the NS-bit determines whether the secure
36
* instance of a cp register should be used. When EL3 is AArch64 (or if
37
* it doesn't exist at all) then there is no register banking, and all
38
* accesses are to the non-secure version.
39
*/
40
-static inline bool access_secure_reg(CPUARMState *env)
41
-{
42
- bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
43
- !arm_el_is_aa64(env, 3) &&
44
- !(env->cp15.scr_el3 & SCR_NS));
45
-
46
- return ret;
47
-}
48
+bool access_secure_reg(CPUARMState *env);
49
50
uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
51
uint32_t cur_el, bool secure);
52
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/tcg/hflags.c
55
+++ b/target/arm/tcg/hflags.c
56
@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
57
#endif
58
}
59
60
+bool access_secure_reg(CPUARMState *env)
26
+{
61
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
62
+ bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
63
+ !arm_el_is_aa64(env, 3) &&
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
64
+ !(env->cp15.scr_el3 & SCR_NS));
30
+
65
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
66
+ return ret;
32
+ tcg_op2 = read_fp_hreg(s, rm);
33
+ tcg_op3 = read_fp_hreg(s, ra);
34
+
35
+ /* These are fused multiply-add, and must be done as one
36
+ * floating point operation with no rounding between the
37
+ * multiplication and addition steps.
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
42
+ if (o1 == true) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
44
+ }
45
+
46
+ if (o0 != o1) {
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
48
+ }
49
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
51
+
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
59
+}
67
+}
60
+
68
+
61
/* Floating point data-processing (3 source)
69
static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
70
ARMMMUIdx mmu_idx,
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
71
CPUARMTBFlags flags)
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
65
}
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
67
break;
68
+ case 3:
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
+ unallocated_encoding(s);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
80
}
81
--
72
--
82
2.17.0
73
2.43.0
83
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
[PULL 03/17] linux-user/aarch64: Remove unused get/put_user macros
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
At the top of linux-user/aarch64/cpu_loop.c we define a set of
2
to diagnose problems, but sometimes you want to see the state of
2
macros for reading and writing data and code words, but we never
3
the floating point registers as well. We don't want to enable that
3
use these macros. Delete them.
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
6
4
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
10
---
7
---
11
include/qemu/log.h | 1 +
8
linux-user/aarch64/cpu_loop.c | 48 -----------------------------------
12
accel/tcg/cpu-exec.c | 9 ++++++---
9
1 file changed, 48 deletions(-)
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
10
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
11
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
13
--- a/linux-user/aarch64/cpu_loop.c
19
+++ b/include/qemu/log.h
14
+++ b/linux-user/aarch64/cpu_loop.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
15
@@ -XXX,XX +XXX,XX @@
21
#define CPU_LOG_PAGE (1 << 14)
16
#include "target/arm/syndrome.h"
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
17
#include "target/arm/cpu-features.h"
23
#define CPU_LOG_TB_OP_IND (1 << 16)
18
24
+#define CPU_LOG_TB_FPU (1 << 17)
19
-#define get_user_code_u32(x, gaddr, env) \
25
20
- ({ abi_long __r = get_user_u32((x), (gaddr)); \
26
/* Lock output for a series of related logs. Since this is not needed
21
- if (!__r && bswap_code(arm_sctlr_b(env))) { \
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
22
- (x) = bswap32(x); \
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
23
- } \
29
index XXXXXXX..XXXXXXX 100644
24
- __r; \
30
--- a/accel/tcg/cpu-exec.c
25
- })
31
+++ b/accel/tcg/cpu-exec.c
26
-
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
27
-#define get_user_code_u16(x, gaddr, env) \
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
28
- ({ abi_long __r = get_user_u16((x), (gaddr)); \
34
&& qemu_log_in_addr_range(itb->pc)) {
29
- if (!__r && bswap_code(arm_sctlr_b(env))) { \
35
qemu_log_lock();
30
- (x) = bswap16(x); \
36
+ int flags = 0;
31
- } \
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
32
- __r; \
38
+ flags |= CPU_DUMP_FPU;
33
- })
39
+ }
34
-
40
#if defined(TARGET_I386)
35
-#define get_user_data_u32(x, gaddr, env) \
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
36
- ({ abi_long __r = get_user_u32((x), (gaddr)); \
42
-#else
37
- if (!__r && arm_cpu_bswap_data(env)) { \
43
- log_cpu_state(cpu, 0);
38
- (x) = bswap32(x); \
44
+ flags |= CPU_DUMP_CCOP;
39
- } \
45
#endif
40
- __r; \
46
+ log_cpu_state(cpu, flags);
41
- })
47
qemu_log_unlock();
42
-
48
}
43
-#define get_user_data_u16(x, gaddr, env) \
49
#endif /* DEBUG_DISAS */
44
- ({ abi_long __r = get_user_u16((x), (gaddr)); \
50
diff --git a/util/log.c b/util/log.c
45
- if (!__r && arm_cpu_bswap_data(env)) { \
51
index XXXXXXX..XXXXXXX 100644
46
- (x) = bswap16(x); \
52
--- a/util/log.c
47
- } \
53
+++ b/util/log.c
48
- __r; \
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
49
- })
55
"show trace before each executed TB (lots of logs)" },
50
-
56
{ CPU_LOG_TB_CPU, "cpu",
51
-#define put_user_data_u32(x, gaddr, env) \
57
"show CPU registers before entering a TB (lots of logs)" },
52
- ({ typeof(x) __x = (x); \
58
+ { CPU_LOG_TB_FPU, "fpu",
53
- if (arm_cpu_bswap_data(env)) { \
59
+ "include FPU registers in the 'cpu' logging" },
54
- __x = bswap32(__x); \
60
{ CPU_LOG_MMU, "mmu",
55
- } \
61
"log MMU-related activities" },
56
- put_user_u32(__x, (gaddr)); \
62
{ CPU_LOG_PCALL, "pcall",
57
- })
58
-
59
-#define put_user_data_u16(x, gaddr, env) \
60
- ({ typeof(x) __x = (x); \
61
- if (arm_cpu_bswap_data(env)) { \
62
- __x = bswap16(__x); \
63
- } \
64
- put_user_u16(__x, (gaddr)); \
65
- })
66
-
67
/* AArch64 main loop */
68
void cpu_loop(CPUARMState *env)
69
{
63
--
70
--
64
2.17.0
71
2.43.0
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
[PULL 04/17] linux-user/arm: Remove unused get_put_user macros
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In linux-user/arm/cpu_loop.c we define a full set of get/put
2
macros for both code and data (since the endianness handling
3
is different between the two). However the only one we actually
4
use is get_user_code_u32(). Remove the rest.
2
5
3
No sense in emitting code after the exception.
6
We leave a comment noting how data-side accesses should be handled
7
for big-endian, because that's a subtle point and we just removed the
8
macros that were effectively documenting it.
4
9
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
---
12
---
11
target/arm/translate-a64.c | 2 +-
13
linux-user/arm/cpu_loop.c | 43 ++++-----------------------------------
12
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 4 insertions(+), 39 deletions(-)
13
15
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
18
--- a/linux-user/arm/cpu_loop.c
17
+++ b/target/arm/translate-a64.c
19
+++ b/linux-user/arm/cpu_loop.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@
19
default:
21
__r; \
20
/* all other sf/type/rmode combinations are invalid */
22
})
21
unallocated_encoding(s);
23
22
- break;
24
-#define get_user_code_u16(x, gaddr, env) \
23
+ return;
25
- ({ abi_long __r = get_user_u16((x), (gaddr)); \
24
}
26
- if (!__r && bswap_code(arm_sctlr_b(env))) { \
25
27
- (x) = bswap16(x); \
26
if (!fp_access_check(s)) {
28
- } \
29
- __r; \
30
- })
31
-
32
-#define get_user_data_u32(x, gaddr, env) \
33
- ({ abi_long __r = get_user_u32((x), (gaddr)); \
34
- if (!__r && arm_cpu_bswap_data(env)) { \
35
- (x) = bswap32(x); \
36
- } \
37
- __r; \
38
- })
39
-
40
-#define get_user_data_u16(x, gaddr, env) \
41
- ({ abi_long __r = get_user_u16((x), (gaddr)); \
42
- if (!__r && arm_cpu_bswap_data(env)) { \
43
- (x) = bswap16(x); \
44
- } \
45
- __r; \
46
- })
47
-
48
-#define put_user_data_u32(x, gaddr, env) \
49
- ({ typeof(x) __x = (x); \
50
- if (arm_cpu_bswap_data(env)) { \
51
- __x = bswap32(__x); \
52
- } \
53
- put_user_u32(__x, (gaddr)); \
54
- })
55
-
56
-#define put_user_data_u16(x, gaddr, env) \
57
- ({ typeof(x) __x = (x); \
58
- if (arm_cpu_bswap_data(env)) { \
59
- __x = bswap16(__x); \
60
- } \
61
- put_user_u16(__x, (gaddr)); \
62
- })
63
+/*
64
+ * Note that if we need to do data accesses here, they should do a
65
+ * bswap if arm_cpu_bswap_data() returns true.
66
+ */
67
68
/*
69
* Similar to code in accel/tcg/user-exec.c, but outside the execution loop.
27
--
70
--
28
2.17.0
71
2.43.0
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
[PULL 05/17] target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The arm_cpu_data_is_big_endian() and related functions are now used
2
only in target/arm; they can be moved to internals.h.
2
3
3
These where missed out from the rest of the half-precision work.
4
The motivation here is that we would like to move arm_current_el()
5
to internals.h.
4
6
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
---
9
---
15
target/arm/helper-a64.h | 2 +
10
target/arm/cpu.h | 48 ------------------------------------------
16
target/arm/helper-a64.c | 10 +++++
11
target/arm/internals.h | 48 ++++++++++++++++++++++++++++++++++++++++++
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
12
2 files changed, 48 insertions(+), 48 deletions(-)
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
13
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
16
--- a/target/arm/cpu.h
23
+++ b/target/arm/helper-a64.h
17
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static inline bool arm_sctlr_b(CPUARMState *env)
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
19
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
20
uint64_t arm_sctlr(CPUARMState *env, int el);
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
21
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
22
-static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
23
- bool sctlr_b)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
24
-{
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
25
-#ifdef CONFIG_USER_ONLY
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
26
- /*
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
27
- * In system mode, BE32 is modelled in line with the
28
- * architecture (as word-invariant big-endianness), where loads
29
- * and stores are done little endian but from addresses which
30
- * are adjusted by XORing with the appropriate constant. So the
31
- * endianness to use for the raw data access is not affected by
32
- * SCTLR.B.
33
- * In user mode, however, we model BE32 as byte-invariant
34
- * big-endianness (because user-only code cannot tell the
35
- * difference), and so we need to use a data access endianness
36
- * that depends on SCTLR.B.
37
- */
38
- if (sctlr_b) {
39
- return true;
40
- }
41
-#endif
42
- /* In 32bit endianness is determined by looking at CPSR's E bit */
43
- return env->uncached_cpsr & CPSR_E;
44
-}
45
-
46
-static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
47
-{
48
- return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
49
-}
50
-
51
-/* Return true if the processor is in big-endian mode. */
52
-static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
53
-{
54
- if (!is_a64(env)) {
55
- return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
56
- } else {
57
- int cur_el = arm_current_el(env);
58
- uint64_t sctlr = arm_sctlr(env, cur_el);
59
- return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
60
- }
61
-}
62
-
63
#include "exec/cpu-all.h"
64
65
/*
66
@@ -XXX,XX +XXX,XX @@ static inline bool bswap_code(bool sctlr_b)
67
#endif
68
}
69
70
-#ifdef CONFIG_USER_ONLY
71
-static inline bool arm_cpu_bswap_data(CPUARMState *env)
72
-{
73
- return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env);
74
-}
75
-#endif
76
-
77
void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
78
uint64_t *cs_base, uint32_t *flags);
79
80
diff --git a/target/arm/internals.h b/target/arm/internals.h
34
index XXXXXXX..XXXXXXX 100644
81
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
82
--- a/target/arm/internals.h
36
+++ b/target/arm/helper-a64.c
83
+++ b/target/arm/internals.h
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
84
@@ -XXX,XX +XXX,XX @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
38
return flags;
85
return arm_rmode_to_sf_map[rmode];
39
}
86
}
40
87
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
88
+static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
89
+ bool sctlr_b)
42
+{
90
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
91
+#ifdef CONFIG_USER_ONLY
92
+ /*
93
+ * In system mode, BE32 is modelled in line with the
94
+ * architecture (as word-invariant big-endianness), where loads
95
+ * and stores are done little endian but from addresses which
96
+ * are adjusted by XORing with the appropriate constant. So the
97
+ * endianness to use for the raw data access is not affected by
98
+ * SCTLR.B.
99
+ * In user mode, however, we model BE32 as byte-invariant
100
+ * big-endianness (because user-only code cannot tell the
101
+ * difference), and so we need to use a data access endianness
102
+ * that depends on SCTLR.B.
103
+ */
104
+ if (sctlr_b) {
105
+ return true;
106
+ }
107
+#endif
108
+ /* In 32bit endianness is determined by looking at CPSR's E bit */
109
+ return env->uncached_cpsr & CPSR_E;
44
+}
110
+}
45
+
111
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
112
+static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
47
+{
113
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
114
+ return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
49
+}
115
+}
50
+
116
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
117
+/* Return true if the processor is in big-endian mode. */
118
+static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
119
+{
120
+ if (!is_a64(env)) {
121
+ return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
122
+ } else {
123
+ int cur_el = arm_current_el(env);
124
+ uint64_t sctlr = arm_sctlr(env, cur_el);
125
+ return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
126
+ }
127
+}
128
+
129
+#ifdef CONFIG_USER_ONLY
130
+static inline bool arm_cpu_bswap_data(CPUARMState *env)
131
+{
132
+ return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env);
133
+}
134
+#endif
135
+
136
static inline void aarch64_save_sp(CPUARMState *env, int el)
52
{
137
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
138
if (env->pstate & PSTATE_SP) {
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
60
}
61
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
63
+static void handle_fp_compare(DisasContext *s, int size,
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
165
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
139
--
215
2.17.0
140
2.43.0
216
217
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
[PULL 06/17] target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The functions arm_current_el() and arm_el_is_aa64() are used only in
2
2
target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that
3
Cc: qemu-stable@nongnu.org
3
query internal state of the CPU. Move them out of cpu.h and into
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
internals.h.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
This means we need to include internals.h in arm_gicv3_cpuif.c, but
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
7
this is justifiable because that file is implementing the GICv3 CPU
8
interface, which really is part of the CPU proper; we just ended up
9
implementing it in code in hw/intc/ for historical reasons.
10
11
The motivation for this move is that we'd like to change
12
arm_el_is_aa64() to add a condition that uses cpu_isar_feature();
13
but we don't want to include cpu-features.h in cpu.h.
14
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
---
17
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
18
target/arm/cpu.h | 66 --------------------------------------
11
1 file changed, 14 insertions(+), 16 deletions(-)
19
target/arm/internals.h | 67 +++++++++++++++++++++++++++++++++++++++
12
20
hw/intc/arm_gicv3_cpuif.c | 1 +
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
target/arm/arch_dump.c | 1 +
14
index XXXXXXX..XXXXXXX 100644
22
4 files changed, 69 insertions(+), 66 deletions(-)
15
--- a/target/arm/translate-a64.c
23
16
+++ b/target/arm/translate-a64.c
24
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
25
index XXXXXXX..XXXXXXX 100644
18
return v;
26
--- a/target/arm/cpu.h
27
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
29
uint64_t arm_hcr_el2_eff(CPUARMState *env);
30
uint64_t arm_hcrx_el2_eff(CPUARMState *env);
31
32
-/* Return true if the specified exception level is running in AArch64 state. */
33
-static inline bool arm_el_is_aa64(CPUARMState *env, int el)
34
-{
35
- /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
36
- * and if we're not in EL0 then the state of EL0 isn't well defined.)
37
- */
38
- assert(el >= 1 && el <= 3);
39
- bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
40
-
41
- /* The highest exception level is always at the maximum supported
42
- * register width, and then lower levels have a register width controlled
43
- * by bits in the SCR or HCR registers.
44
- */
45
- if (el == 3) {
46
- return aa64;
47
- }
48
-
49
- if (arm_feature(env, ARM_FEATURE_EL3) &&
50
- ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
51
- aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
52
- }
53
-
54
- if (el == 2) {
55
- return aa64;
56
- }
57
-
58
- if (arm_is_el2_enabled(env)) {
59
- aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
60
- }
61
-
62
- return aa64;
63
-}
64
-
65
/*
66
* Function for determining whether guest cp register reads and writes should
67
* access the secure or non-secure bank of a cp register. When EL3 is
68
@@ -XXX,XX +XXX,XX @@ static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
69
return env->v7m.exception != 0;
19
}
70
}
20
71
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
72
-/* Return the current Exception Level (as per ARMv8; note that this differs
73
- * from the ARMv7 Privilege Level).
74
- */
75
-static inline int arm_current_el(CPUARMState *env)
76
-{
77
- if (arm_feature(env, ARM_FEATURE_M)) {
78
- return arm_v7m_is_handler_mode(env) ||
79
- !(env->v7m.control[env->v7m.secure] & 1);
80
- }
81
-
82
- if (is_a64(env)) {
83
- return extract32(env->pstate, 2, 2);
84
- }
85
-
86
- switch (env->uncached_cpsr & 0x1f) {
87
- case ARM_CPU_MODE_USR:
88
- return 0;
89
- case ARM_CPU_MODE_HYP:
90
- return 2;
91
- case ARM_CPU_MODE_MON:
92
- return 3;
93
- default:
94
- if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
95
- /* If EL3 is 32-bit then all secure privileged modes run in
96
- * EL3
97
- */
98
- return 3;
99
- }
100
-
101
- return 1;
102
- }
103
-}
104
-
105
/**
106
* write_list_to_cpustate
107
* @cpu: ARMCPU
108
diff --git a/target/arm/internals.h b/target/arm/internals.h
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/arm/internals.h
111
+++ b/target/arm/internals.h
112
@@ -XXX,XX +XXX,XX @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
113
return arm_rmode_to_sf_map[rmode];
114
}
115
116
+/* Return true if the specified exception level is running in AArch64 state. */
117
+static inline bool arm_el_is_aa64(CPUARMState *env, int el)
22
+{
118
+{
23
+ TCGv_i32 v = tcg_temp_new_i32();
119
+ /*
24
+
120
+ * This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
121
+ * and if we're not in EL0 then the state of EL0 isn't well defined.)
26
+ return v;
122
+ */
123
+ assert(el >= 1 && el <= 3);
124
+ bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
125
+
126
+ /*
127
+ * The highest exception level is always at the maximum supported
128
+ * register width, and then lower levels have a register width controlled
129
+ * by bits in the SCR or HCR registers.
130
+ */
131
+ if (el == 3) {
132
+ return aa64;
133
+ }
134
+
135
+ if (arm_feature(env, ARM_FEATURE_EL3) &&
136
+ ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
137
+ aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
138
+ }
139
+
140
+ if (el == 2) {
141
+ return aa64;
142
+ }
143
+
144
+ if (arm_is_el2_enabled(env)) {
145
+ aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
146
+ }
147
+
148
+ return aa64;
27
+}
149
+}
28
+
150
+
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
151
+/*
30
* If SVE is not enabled, then there are only 128 bits in the vector.
152
+ * Return the current Exception Level (as per ARMv8; note that this differs
31
*/
153
+ * from the ARMv7 Privilege Level).
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
154
+ */
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
155
+static inline int arm_current_el(CPUARMState *env)
156
+{
157
+ if (arm_feature(env, ARM_FEATURE_M)) {
158
+ return arm_v7m_is_handler_mode(env) ||
159
+ !(env->v7m.control[env->v7m.secure] & 1);
160
+ }
161
+
162
+ if (is_a64(env)) {
163
+ return extract32(env->pstate, 2, 2);
164
+ }
165
+
166
+ switch (env->uncached_cpsr & 0x1f) {
167
+ case ARM_CPU_MODE_USR:
168
+ return 0;
169
+ case ARM_CPU_MODE_HYP:
170
+ return 2;
171
+ case ARM_CPU_MODE_MON:
172
+ return 3;
173
+ default:
174
+ if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
175
+ /* If EL3 is 32-bit then all secure privileged modes run in EL3 */
176
+ return 3;
177
+ }
178
+
179
+ return 1;
180
+ }
181
+}
182
+
183
static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
184
bool sctlr_b)
34
{
185
{
35
TCGv_ptr fpst = NULL;
186
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
187
index XXXXXXX..XXXXXXX 100644
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
188
--- a/hw/intc/arm_gicv3_cpuif.c
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
189
+++ b/hw/intc/arm_gicv3_cpuif.c
39
190
@@ -XXX,XX +XXX,XX @@
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
191
#include "cpu.h"
41
-
192
#include "target/arm/cpregs.h"
42
switch (opcode) {
193
#include "target/arm/cpu-features.h"
43
case 0x0: /* FMOV */
194
+#include "target/arm/internals.h"
44
tcg_gen_mov_i32(tcg_res, tcg_op);
195
#include "system/tcg.h"
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
196
#include "system/qtest.h"
46
tcg_temp_free_i64(tcg_op2);
197
47
tcg_temp_free_i64(tcg_res);
198
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
48
} else {
199
index XXXXXXX..XXXXXXX 100644
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
200
--- a/target/arm/arch_dump.c
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
201
+++ b/target/arm/arch_dump.c
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
202
@@ -XXX,XX +XXX,XX @@
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
203
#include "elf.h"
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
204
#include "system/dump.h"
54
205
#include "cpu-features.h"
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
206
+#include "internals.h"
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
207
57
-
208
/* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
209
struct aarch64_user_regs {
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
79
80
if (is_scalar) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
90
--
210
--
91
2.17.0
211
2.43.0
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
[PULL 07/17] target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The definition of SCR_EL3.RW says that its effective value is 1 if:
2
- EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1
3
- the effective value of SCR_EL3.{EEL2,NS} is {1,0} (i.e. we are
4
Secure and Secure EL2 is disabled)
2
5
3
All the hard work is already done by vfp_expand_imm, we just need to
6
We implement the second of these in arm_el_is_aa64(), but forgot the
4
make sure we pick up the correct size.
7
first.
5
8
6
Cc: qemu-stable@nongnu.org
9
Provide a new function arm_scr_rw_eff() to return the effective
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
value of SCR_EL3.RW, and use it in arm_el_is_aa64() and the other
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
places that currently look directly at the bit value.
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
(scr_write() enforces that the RW bit is RAO/WI if neither EL1 nor
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
14
EL2 have AArch32 support, but if EL1 does but EL2 does not then the
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
15
bit must still be writeable.)
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
17
This will mean that if code at EL3 attempts to perform an exception
18
return to AArch32 EL2 when EL2 is AArch64-only we will correctly
19
handle this as an illegal exception return: it will be caught by the
20
"return to an EL which is configured for a different register width"
21
check in HELPER(exception_return).
22
23
We do already have some CPU types which don't implement AArch32
24
above EL0, so this is technically a bug; it doesn't seem worth
25
backporting to stable because no sensible guest code will be
26
deliberately attempting to set the RW bit to a value corresponding
27
to an unimplemented execution state and then checking that we
28
did the right thing.
29
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
---
32
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
33
target/arm/internals.h | 26 +++++++++++++++++++++++---
17
1 file changed, 17 insertions(+), 3 deletions(-)
34
target/arm/helper.c | 4 ++--
35
2 files changed, 25 insertions(+), 5 deletions(-)
18
36
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
37
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
39
--- a/target/arm/internals.h
22
+++ b/target/arm/translate-a64.c
40
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
41
@@ -XXX,XX +XXX,XX @@ static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
42
return arm_rmode_to_sf_map[rmode];
43
}
44
45
+/* Return the effective value of SCR_EL3.RW */
46
+static inline bool arm_scr_rw_eff(CPUARMState *env)
47
+{
48
+ /*
49
+ * SCR_EL3.RW has an effective value of 1 if:
50
+ * - we are NS and EL2 is implemented but doesn't support AArch32
51
+ * - we are S and EL2 is enabled (in which case it must be AArch64)
52
+ */
53
+ ARMCPU *cpu = env_archcpu(env);
54
+
55
+ if (env->cp15.scr_el3 & SCR_RW) {
56
+ return true;
57
+ }
58
+ if (env->cp15.scr_el3 & SCR_NS) {
59
+ return arm_feature(env, ARM_FEATURE_EL2) &&
60
+ !cpu_isar_feature(aa64_aa32_el2, cpu);
61
+ } else {
62
+ return env->cp15.scr_el3 & SCR_EEL2;
63
+ }
64
+}
65
+
66
/* Return true if the specified exception level is running in AArch64 state. */
67
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
24
{
68
{
25
int rd = extract32(insn, 0, 5);
69
@@ -XXX,XX +XXX,XX @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
26
int imm8 = extract32(insn, 13, 8);
70
return aa64;
27
- int is_double = extract32(insn, 22, 2);
28
+ int type = extract32(insn, 22, 2);
29
uint64_t imm;
30
TCGv_i64 tcg_res;
31
+ TCGMemOp sz;
32
33
- if (is_double > 1) {
34
+ switch (type) {
35
+ case 0:
36
+ sz = MO_32;
37
+ break;
38
+ case 1:
39
+ sz = MO_64;
40
+ break;
41
+ case 3:
42
+ sz = MO_16;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
44
+ break;
45
+ }
46
+ /* fallthru */
47
+ default:
48
unallocated_encoding(s);
49
return;
50
}
71
}
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
72
52
return;
73
- if (arm_feature(env, ARM_FEATURE_EL3) &&
74
- ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
75
- aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
76
+ if (arm_feature(env, ARM_FEATURE_EL3)) {
77
+ aa64 = aa64 && arm_scr_rw_eff(env);
53
}
78
}
54
79
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
80
if (el == 2) {
56
+ imm = vfp_expand_imm(sz, imm8);
81
diff --git a/target/arm/helper.c b/target/arm/helper.c
57
82
index XXXXXXX..XXXXXXX 100644
58
tcg_res = tcg_const_i64(imm);
83
--- a/target/arm/helper.c
59
write_fp_dreg(s, rd, tcg_res);
84
+++ b/target/arm/helper.c
85
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
86
uint64_t hcr_el2;
87
88
if (arm_feature(env, ARM_FEATURE_EL3)) {
89
- rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
90
+ rw = arm_scr_rw_eff(env);
91
} else {
92
/*
93
* Either EL2 is the highest EL (and so the EL2 register width
94
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
95
96
switch (new_el) {
97
case 3:
98
- is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
99
+ is_aa64 = arm_scr_rw_eff(env);
100
break;
101
case 2:
102
hcr = arm_hcr_el2_eff(env);
60
--
103
--
61
2.17.0
104
2.43.0
62
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
[PULL 08/17] target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32
1
From: Richard Henderson <richard.henderson@linaro.org>
1
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
2
be RAO/WI. Enforce the RAO/WI behaviour.
2
3
3
Cc: qemu-stable@nongnu.org
4
Note that we handle "reset value should honour RES1 bits" in the same
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
way that SCR_EL3 does, via a reset function.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
We do already have some CPU types which don't implement AArch32
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
above EL0, so this is technically a bug; it doesn't seem worth
9
backporting to stable because no sensible guest code will be
10
deliberately attempting to set the RW bit to a value corresponding
11
to an unimplemented execution state and then checking that we
12
did the right thing.
13
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
---
16
---
10
target/arm/helper.h | 6 +++
17
target/arm/helper.c | 12 ++++++++++++
11
target/arm/helper.c | 38 ++++++++++++++-
18
1 file changed, 12 insertions(+)
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
19
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
22
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
23
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
24
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
44
#undef VFP_CONV_FIX_A64
25
/* Clear RES0 bits. */
45
26
value &= valid_mask;
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
27
47
- * Therefore we convert to f64 (which does not round), scale,
28
+ /* RW is RAO/WI if EL1 is AArch64 only */
48
- * and then convert f64 to f16 (which may round).
29
+ if (!cpu_isar_feature(aa64_aa32_el1, cpu)) {
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
30
+ value |= HCR_RW;
50
+ * vice versa for conversion to integer.
31
+ }
51
+ *
32
+
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
33
/*
53
+ * For 64-bit integers, any integer that would cause rounding will also
34
* These bits change the MMU setup:
54
+ * overflow to f16 infinity, so there is no double rounding problem.
35
* HCR_VM enables stage 2 translation
55
*/
36
@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
56
37
do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32));
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
38
}
61
39
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
40
+static void hcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
63
+{
41
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
42
+ /* hcr_write will set the RES1 bits on an AArch64-only CPU */
43
+ hcr_write(env, ri, 0);
65
+}
44
+}
66
+
45
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
46
/*
68
+{
47
* Return the effective value of HCR_EL2, at the given security state.
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
48
* Bits that are not included here:
70
+}
49
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
71
+
50
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
51
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
73
{
52
.nv2_redirect_offset = 0x78,
74
if (unlikely(float16_is_any_nan(f))) {
53
+ .resetfn = hcr_reset,
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
54
.writefn = hcr_write, .raw_writefn = raw_write },
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
55
{ .name = "HCR", .state = ARM_CP_STATE_AA32,
77
}
56
.type = ARM_CP_ALIAS | ARM_CP_IO,
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
57
--
266
2.17.0
58
2.43.0
267
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
[PULL 09/17] target/arm: Add cpu local variable to exception_return helper
1
In float-to-integer conversion, if the floating point input
1
We already call env_archcpu() multiple times within the
2
converts exactly to the largest or smallest integer that
2
exception_return helper function, and we're about to want to
3
fits in to the result type, this is not an overflow.
3
add another use of the ARMCPU pointer. Add a local variable
4
In this situation we were producing the correct result value,
4
cpu so we can call env_archcpu() just once.
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
5
9
Fix the boundary case to take the right half of the if()
10
statements.
11
12
This fixes a regression from 2.11 introduced by the softfloat
13
refactoring.
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
20
---
8
---
21
fpu/softfloat.c | 4 ++--
9
target/arm/tcg/helper-a64.c | 7 ++++---
22
1 file changed, 2 insertions(+), 2 deletions(-)
10
1 file changed, 4 insertions(+), 3 deletions(-)
23
11
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
12
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
25
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
14
--- a/target/arm/tcg/helper-a64.c
27
+++ b/fpu/softfloat.c
15
+++ b/target/arm/tcg/helper-a64.c
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
16
@@ -XXX,XX +XXX,XX @@ static void cpsr_write_from_spsr_elx(CPUARMState *env,
29
r = UINT64_MAX;
17
30
}
18
void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
31
if (p.sign) {
19
{
32
- if (r < -(uint64_t) min) {
20
+ ARMCPU *cpu = env_archcpu(env);
33
+ if (r <= -(uint64_t) min) {
21
int cur_el = arm_current_el(env);
34
return -r;
22
unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
35
} else {
23
uint32_t spsr = env->banked_spsr[spsr_idx];
36
s->float_exception_flags = orig_flags | float_flag_invalid;
24
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
37
return min;
25
}
38
}
26
39
} else {
27
bql_lock();
40
- if (r < max) {
28
- arm_call_pre_el_change_hook(env_archcpu(env));
41
+ if (r <= max) {
29
+ arm_call_pre_el_change_hook(cpu);
42
return r;
30
bql_unlock();
43
} else {
31
44
s->float_exception_flags = orig_flags | float_flag_invalid;
32
if (!return_to_aa64) {
33
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
34
int tbii;
35
36
env->aarch64 = true;
37
- spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
38
+ spsr &= aarch64_pstate_valid_mask(&cpu->isar);
39
pstate_write(env, spsr);
40
if (!arm_singlestep_active(env)) {
41
env->pstate &= ~PSTATE_SS;
42
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
43
aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
44
45
bql_lock();
46
- arm_call_el_change_hook(env_archcpu(env));
47
+ arm_call_el_change_hook(cpu);
48
bql_unlock();
49
50
return;
45
--
51
--
46
2.17.0
52
2.43.0
47
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
[PULL 10/17] target/arm: Forbid return to AArch32 when CPU is AArch64-only
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In the Arm ARM, rule R_TYTWB states that returning to AArch32
2
is an illegal exception return if:
3
* AArch32 is not supported at any exception level
4
* the target EL is configured for AArch64 via SCR_EL3.RW
5
or HCR_EL2.RW or via CPU state at reset
2
6
3
Cc: qemu-stable@nongnu.org
7
We check the second of these, but not the first (which can only be
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
relevant for the case of a return to EL0, because if AArch32 is not
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
supported at one of the higher ELs then the RW bits will have an
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
effective value of 1 and the the "configured for AArch64" condition
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
11
will hold also).
12
13
Add the missing condition. Although this is technically a bug
14
(because we have one AArch64-only CPU: a64fx) it isn't worth
15
backporting to stable because no sensible guest code will
16
deliberately try to return to a nonexistent execution state
17
to check that it gets an illegal exception return.
18
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
---
21
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
22
target/arm/tcg/helper-a64.c | 5 +++++
11
1 file changed, 15 insertions(+), 2 deletions(-)
23
1 file changed, 5 insertions(+)
12
24
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
14
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
27
--- a/target/arm/tcg/helper-a64.c
16
+++ b/target/arm/translate-a64.c
28
+++ b/target/arm/tcg/helper-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
29
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
18
bool sf = extract32(insn, 31, 1);
30
goto illegal_return;
19
bool itof;
31
}
20
32
21
- if (sbit || (type > 1)
33
+ if (!return_to_aa64 && !cpu_isar_feature(aa64_aa32, cpu)) {
22
- || (!sf && scale < 32)) {
34
+ /* Return to AArch32 when CPU is AArch64-only */
23
+ if (sbit || (!sf && scale < 32)) {
35
+ goto illegal_return;
24
+ unallocated_encoding(s);
25
+ return;
26
+ }
36
+ }
27
+
37
+
28
+ switch (type) {
38
if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
29
+ case 0: /* float32 */
39
goto illegal_return;
30
+ case 1: /* float64 */
31
+ break;
32
+ case 3: /* float16 */
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
34
+ break;
35
+ }
36
+ /* fallthru */
37
+ default:
38
unallocated_encoding(s);
39
return;
40
}
40
}
41
--
41
--
42
2.17.0
42
2.43.0
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
[PULL 11/17] MAINTAINERS: Fix status for Arm boards I "maintain"
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
I'm down as the only listed maintainer for quite a lot of Arm SoC and
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
2
board types. In some cases this is only as the "maintainer of last
3
by setting it to float_tininess_before_rounding. This currently
3
resort" and I'm not in practice doing anything beyond patch review
4
will only cause problems for the new V8_FP16 feature, since the
4
and the odd bit of tidyup.
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
8
5
9
Add the missing initialization.
6
Move these entries in MAINTAINERS from "Maintained" to "Odd Fixes",
7
to better represent reality. Entries for other boards and SoCs where
8
I do more actively care (or where there is a listed co-maintainer)
9
remain as they are.
10
10
11
Fixes: d81ce0ef2c4f105
12
Cc: qemu-stable@nongnu.org
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Message-id: 20250307152838.3226398-1-peter.maydell@linaro.org
17
---
14
---
18
target/arm/cpu.c | 2 ++
15
MAINTAINERS | 14 +++++++-------
19
1 file changed, 2 insertions(+)
16
1 file changed, 7 insertions(+), 7 deletions(-)
20
17
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
diff --git a/MAINTAINERS b/MAINTAINERS
22
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
20
--- a/MAINTAINERS
24
+++ b/target/arm/cpu.c
21
+++ b/MAINTAINERS
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
22
@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/kzm.rst
26
&env->vfp.fp_status);
23
Integrator CP
27
set_float_detect_tininess(float_tininess_before_rounding,
24
M: Peter Maydell <peter.maydell@linaro.org>
28
&env->vfp.standard_fp_status);
25
L: qemu-arm@nongnu.org
29
+ set_float_detect_tininess(float_tininess_before_rounding,
26
-S: Maintained
30
+ &env->vfp.fp_status_f16);
27
+S: Odd Fixes
31
#ifndef CONFIG_USER_ONLY
28
F: hw/arm/integratorcp.c
32
if (kvm_enabled()) {
29
F: hw/misc/arm_integrator_debug.c
33
kvm_arm_reset_vcpu(cpu);
30
F: include/hw/misc/arm_integrator_debug.h
31
@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/mps2.rst
32
Musca
33
M: Peter Maydell <peter.maydell@linaro.org>
34
L: qemu-arm@nongnu.org
35
-S: Maintained
36
+S: Odd Fixes
37
F: hw/arm/musca.c
38
F: docs/system/arm/musca.rst
39
40
@@ -XXX,XX +XXX,XX @@ F: tests/functional/test_aarch64_raspi4.py
41
Real View
42
M: Peter Maydell <peter.maydell@linaro.org>
43
L: qemu-arm@nongnu.org
44
-S: Maintained
45
+S: Odd Fixes
46
F: hw/arm/realview*
47
F: hw/cpu/realview_mpcore.c
48
F: hw/intc/realview_gic.c
49
@@ -XXX,XX +XXX,XX @@ F: tests/functional/test_arm_collie.py
50
Stellaris
51
M: Peter Maydell <peter.maydell@linaro.org>
52
L: qemu-arm@nongnu.org
53
-S: Maintained
54
+S: Odd Fixes
55
F: hw/*/stellaris*
56
F: hw/display/ssd03*
57
F: include/hw/input/gamepad.h
58
@@ -XXX,XX +XXX,XX @@ F: docs/system/arm/stm32.rst
59
Versatile Express
60
M: Peter Maydell <peter.maydell@linaro.org>
61
L: qemu-arm@nongnu.org
62
-S: Maintained
63
+S: Odd Fixes
64
F: hw/arm/vexpress.c
65
F: hw/display/sii9022.c
66
F: docs/system/arm/vexpress.rst
67
@@ -XXX,XX +XXX,XX @@ F: tests/functional/test_arm_vexpress.py
68
Versatile PB
69
M: Peter Maydell <peter.maydell@linaro.org>
70
L: qemu-arm@nongnu.org
71
-S: Maintained
72
+S: Odd Fixes
73
F: hw/*/versatile*
74
F: hw/i2c/arm_sbcon_i2c.c
75
F: include/hw/i2c/arm_sbcon_i2c.h
76
@@ -XXX,XX +XXX,XX @@ F: include/hw/hyperv/vmbus*.h
77
OMAP
78
M: Peter Maydell <peter.maydell@linaro.org>
79
L: qemu-arm@nongnu.org
80
-S: Maintained
81
+S: Odd Fixes
82
F: hw/*/omap*
83
F: include/hw/arm/omap.h
84
F: docs/system/arm/sx1.rst
34
--
85
--
35
2.17.0
86
2.43.0
36
87
37
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
[PULL 13/17] Revert "hw/char/pl011: Warn when using disabled receiver"
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
2
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
3
The guest does not control whether characters are sent on the UART.
4
Sending them before the guest happens to boot will now result in a
5
"guest error" log entry that is only because of timing, even if the
6
guest _would_ later setup the receiver correctly.
4
7
5
The block length is predefined to 512 bits
8
This reverts the bulk of commit abf2b6a028670bd2890bb3aee7e103fe53e4b0df,
9
and instead adds a comment about why we don't check the enable bits.
6
10
7
and "4.10.2 SD Status":
11
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
8
12
Cc: Peter Maydell <peter.maydell@linaro.org>
9
The SD Status contains status bits that are related to the SD Memory Card
13
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10
proprietary features and may be used for future application-specific usage.
14
Message-id: 20250311153717.206129-1-pbonzini@redhat.com
11
The size of the SD Status is one data block of 512 bit. The content of this
15
[PMM: expanded comment]
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
18
---
21
hw/sd/sd.c | 2 +-
19
hw/char/pl011.c | 19 ++++++++++---------
22
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 10 insertions(+), 9 deletions(-)
23
21
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
22
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
25
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
24
--- a/hw/char/pl011.c
27
+++ b/hw/sd/sd.c
25
+++ b/hw/char/pl011.c
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
26
@@ -XXX,XX +XXX,XX @@ static int pl011_can_receive(void *opaque)
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
27
unsigned fifo_depth = pl011_get_fifo_depth(s);
30
}
28
unsigned fifo_available = fifo_depth - s->read_count;
31
memset(&sd->data[17], 0, 47);
29
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
30
- if (!(s->cr & CR_UARTEN)) {
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
31
- qemu_log_mask(LOG_GUEST_ERROR,
32
- "PL011 receiving data on disabled UART\n");
33
- }
34
- if (!(s->cr & CR_RXE)) {
35
- qemu_log_mask(LOG_GUEST_ERROR,
36
- "PL011 receiving data on disabled RX UART\n");
37
- }
38
- trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available);
39
+ /*
40
+ * In theory we should check the UART and RX enable bits here and
41
+ * return 0 if they are not set (so the guest can't receive data
42
+ * until you have enabled the UART). In practice we suspect there
43
+ * is at least some guest code out there which has been tested only
44
+ * on QEMU and which never bothers to enable the UART because we
45
+ * historically never enforced that. So we effectively keep the
46
+ * UART continuously enabled regardless of the enable bits.
47
+ */
48
49
+ trace_pl011_can_receive(s->lcr, s->read_count, fifo_depth, fifo_available);
50
return fifo_available;
34
}
51
}
35
52
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
37
--
53
--
38
2.17.0
54
2.43.0
39
55
40
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
[PULL 14/17] util/cacheflush: Make first DSB unconditional on aarch64
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Joe Komlodi <komlodi@google.com>
2
2
3
We are meant to explicitly pass fpst, not cpu_env.
3
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
4
an ISB to be executed during cache maintenance, which could lead to QEMU
5
executing TBs containing garbage instructions.
6
7
This seems to be because the ISB finishes executing instructions and
8
flushes the pipeline, but the ISB doesn't guarantee that writes from the
9
executed instructions are committed. If a small enough TB is created, it's
10
possible that the writes setting up the TB aren't committed by the time the
11
TB is executed.
12
13
This function is intended to be a port of the gcc implementation
14
(https://github.com/gcc-mirror/gcc/blob/85b46d0795ac76bc192cb8f88b646a647acf98c1/libgcc/config/aarch64/sync-cache.c#L67)
15
which makes the first DSB unconditional, so we can fix the synchronization
16
issue by doing that as well.
4
17
5
Cc: qemu-stable@nongnu.org
18
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
19
Fixes: 664a79735e4deb1 ("util: Specialize flush_idcache_range for aarch64")
20
Signed-off-by: Joe Komlodi <komlodi@google.com>
21
Message-id: 20250310203622.1827940-2-komlodi@google.com
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
25
---
13
target/arm/translate-a64.c | 3 ++-
26
util/cacheflush.c | 4 +++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
27
1 file changed, 3 insertions(+), 1 deletion(-)
15
28
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
diff --git a/util/cacheflush.c b/util/cacheflush.c
17
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
31
--- a/util/cacheflush.c
19
+++ b/target/arm/translate-a64.c
32
+++ b/util/cacheflush.c
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
33
@@ -XXX,XX +XXX,XX @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
34
for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) {
22
break;
35
asm volatile("dc\tcvau, %0" : : "r" (p) : "memory");
23
case 0x3: /* FSQRT */
36
}
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
37
- asm volatile("dsb\tish" : : : "memory");
25
+ fpst = get_fpstatus_ptr(true);
38
}
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
39
27
break;
40
+ /* DSB unconditionally to ensure any outstanding writes are committed. */
28
case 0x8: /* FRINTN */
41
+ asm volatile("dsb\tish" : : : "memory");
29
case 0x9: /* FRINTP */
42
+
43
/*
44
* If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point
45
* of Unification is not required for instruction to data coherence.
30
--
46
--
31
2.17.0
47
2.43.0
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
[PULL 15/17] target/arm: Make DisasContext.{fp, sve}_access_checked tristate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Adding the fp16 moves to/from general registers.
3
The check for fp_excp_el in assert_fp_access_checked is
4
incorrect. For SME, with StreamingMode enabled, the access
5
is really against the streaming mode vectors, and access
6
to the normal fp registers is allowed to be disabled.
7
C.f. sme_enabled_check.
8
9
Convert sve_access_checked to match, even though we don't
10
currently check the exception state.
4
11
5
Cc: qemu-stable@nongnu.org
12
Cc: qemu-stable@nongnu.org
13
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20250307190415.982049-2-richard.henderson@linaro.org
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
18
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
19
target/arm/tcg/translate-a64.h | 2 +-
13
1 file changed, 21 insertions(+)
20
target/arm/tcg/translate.h | 10 +++++++---
21
target/arm/tcg/translate-a64.c | 17 +++++++++--------
22
3 files changed, 17 insertions(+), 12 deletions(-)
14
23
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
16
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
26
--- a/target/arm/tcg/translate-a64.h
18
+++ b/target/arm/translate-a64.c
27
+++ b/target/arm/tcg/translate-a64.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
28
@@ -XXX,XX +XXX,XX @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
29
static inline void assert_fp_access_checked(DisasContext *s)
21
clear_vec_high(s, true, rd);
30
{
22
break;
31
#ifdef CONFIG_DEBUG_TCG
23
+ case 3:
32
- if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
24
+ /* 16 bit */
33
+ if (unlikely(s->fp_access_checked <= 0)) {
25
+ tmp = tcg_temp_new_i64();
34
fprintf(stderr, "target-arm: FP access check missing for "
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
35
"instruction 0x%08x\n", s->insn);
27
+ write_fp_dreg(s, rd, tmp);
36
abort();
28
+ tcg_temp_free_i64(tmp);
37
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
29
+ break;
38
index XXXXXXX..XXXXXXX 100644
30
+ default:
39
--- a/target/arm/tcg/translate.h
31
+ g_assert_not_reached();
40
+++ b/target/arm/tcg/translate.h
32
}
41
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
33
} else {
42
bool aarch64;
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
43
bool thumb;
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
44
bool lse2;
36
/* 64 bits from top half */
45
- /* Because unallocated encodings generate different exception syndrome
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
46
+ /*
38
break;
47
+ * Because unallocated encodings generate different exception syndrome
39
+ case 3:
48
* information from traps due to FP being disabled, we can't do a single
40
+ /* 16 bit */
49
* "is fp access disabled" check at a high level in the decode tree.
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
50
* To help in catching bugs where the access check was forgotten in some
42
+ break;
51
* code path, we set this flag when the access check is done, and assert
43
+ default:
52
* that it is set at the point where we actually touch the FP regs.
44
+ g_assert_not_reached();
53
+ * 0: not checked,
45
}
54
+ * 1: checked, access ok
55
+ * -1: checked, access denied
56
*/
57
- bool fp_access_checked;
58
- bool sve_access_checked;
59
+ int8_t fp_access_checked;
60
+ int8_t sve_access_checked;
61
/* ARMv8 single-step state (this is distinct from the QEMU gdbstub
62
* single-step support).
63
*/
64
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/tcg/translate-a64.c
67
+++ b/target/arm/tcg/translate-a64.c
68
@@ -XXX,XX +XXX,XX @@ static bool fp_access_check_only(DisasContext *s)
69
{
70
if (s->fp_excp_el) {
71
assert(!s->fp_access_checked);
72
- s->fp_access_checked = true;
73
+ s->fp_access_checked = -1;
74
75
gen_exception_insn_el(s, 0, EXCP_UDEF,
76
syn_fp_access_trap(1, 0xe, false, 0),
77
s->fp_excp_el);
78
return false;
46
}
79
}
80
- s->fp_access_checked = true;
81
+ s->fp_access_checked = 1;
82
return true;
47
}
83
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
84
49
case 0xa: /* 64 bit */
85
@@ -XXX,XX +XXX,XX @@ bool sve_access_check(DisasContext *s)
50
case 0xd: /* 64 bit to top half of quad */
86
syn_sve_access_trap(), s->sve_excp_el);
51
break;
87
goto fail_exit;
52
+ case 0x6: /* 16-bit float, 32-bit int */
88
}
53
+ case 0xe: /* 16-bit float, 64-bit int */
89
- s->sve_access_checked = true;
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
90
+ s->sve_access_checked = 1;
55
+ break;
91
return fp_access_check(s);
56
+ }
92
57
+ /* fallthru */
93
fail_exit:
58
default:
94
/* Assert that we only raise one exception per instruction. */
59
/* all other sf/type/rmode combinations are invalid */
95
assert(!s->sve_access_checked);
60
unallocated_encoding(s);
96
- s->sve_access_checked = true;
97
+ s->sve_access_checked = -1;
98
return false;
99
}
100
101
@@ -XXX,XX +XXX,XX @@ bool sme_enabled_check(DisasContext *s)
102
* sme_excp_el by itself for cpregs access checks.
103
*/
104
if (!s->fp_excp_el || s->sme_excp_el < s->fp_excp_el) {
105
- s->fp_access_checked = true;
106
- return sme_access_check(s);
107
+ bool ret = sme_access_check(s);
108
+ s->fp_access_checked = (ret ? 1 : -1);
109
+ return ret;
110
}
111
return fp_access_check_only(s);
112
}
113
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
114
s->insn = insn;
115
s->base.pc_next = pc + 4;
116
117
- s->fp_access_checked = false;
118
- s->sve_access_checked = false;
119
+ s->fp_access_checked = 0;
120
+ s->sve_access_checked = 0;
121
122
if (s->pstate_il) {
123
/*
61
--
124
--
62
2.17.0
125
2.43.0
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
[PULL 16/17] target/arm: Simplify pstate_sm check in sve_access_check
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 binary operations.
3
In StreamingMode, fp_access_checked is handled already.
4
We cannot fall through to fp_access_check lest we fall
5
foul of the double-check assertion.
4
6
5
Cc: qemu-stable@nongnu.org
7
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20250307190415.982049-3-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
[PMM: move declaration of 'ret' to top of block]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
15
target/arm/tcg/translate-a64.c | 22 +++++++++++-----------
13
1 file changed, 65 insertions(+)
16
1 file changed, 11 insertions(+), 11 deletions(-)
14
17
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
20
--- a/target/arm/tcg/translate-a64.c
18
+++ b/target/arm/translate-a64.c
21
+++ b/target/arm/tcg/translate-a64.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
22
@@ -XXX,XX +XXX,XX @@ static int fp_access_check_vector_hsd(DisasContext *s, bool is_q, MemOp esz)
20
tcg_temp_free_i64(tcg_res);
23
bool sve_access_check(DisasContext *s)
24
{
25
if (s->pstate_sm || !dc_isar_feature(aa64_sve, s)) {
26
+ bool ret;
27
+
28
assert(dc_isar_feature(aa64_sme, s));
29
- if (!sme_sm_enabled_check(s)) {
30
- goto fail_exit;
31
- }
32
- } else if (s->sve_excp_el) {
33
+ ret = sme_sm_enabled_check(s);
34
+ s->sve_access_checked = (ret ? 1 : -1);
35
+ return ret;
36
+ }
37
+ if (s->sve_excp_el) {
38
+ /* Assert that we only raise one exception per instruction. */
39
+ assert(!s->sve_access_checked);
40
gen_exception_insn_el(s, 0, EXCP_UDEF,
41
syn_sve_access_trap(), s->sve_excp_el);
42
- goto fail_exit;
43
+ s->sve_access_checked = -1;
44
+ return false;
45
}
46
s->sve_access_checked = 1;
47
return fp_access_check(s);
48
-
49
- fail_exit:
50
- /* Assert that we only raise one exception per instruction. */
51
- assert(!s->sve_access_checked);
52
- s->sve_access_checked = -1;
53
- return false;
21
}
54
}
22
55
23
+/* Floating-point data-processing (2 source) - half precision */
56
/*
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
25
+ int rd, int rn, int rm)
26
+{
27
+ TCGv_i32 tcg_op1;
28
+ TCGv_i32 tcg_op2;
29
+ TCGv_i32 tcg_res;
30
+ TCGv_ptr fpst;
31
+
32
+ tcg_res = tcg_temp_new_i32();
33
+ fpst = get_fpstatus_ptr(true);
34
+ tcg_op1 = read_fp_hreg(s, rn);
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
77
+
78
/* Floating point data-processing (2 source)
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
82
}
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
84
break;
85
+ case 3:
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
87
+ unallocated_encoding(s);
88
+ return;
89
+ }
90
+ if (!fp_access_check(s)) {
91
+ return;
92
+ }
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
94
+ break;
95
default:
96
unallocated_encoding(s);
97
}
98
--
57
--
99
2.17.0
58
2.43.0
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
[PULL 17/17] meson.build: Set RUST_BACKTRACE for all tests
1
From: Alex Bennée <alex.bennee@linaro.org>
1
We want to capture potential Rust backtraces on panics in our test
2
logs, which isn't Rust's default behaviour. Set RUST_BACKTRACE=1 in
3
the add_test_setup environments, so that all our tests get run with
4
this environment variable set.
2
5
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
6
This makes the setting of that variable in the gitlab CI template
4
later on so we might as well mirror that.
7
redundant, so we can remove it.
5
8
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20250310102950.3752908-1-peter.maydell@linaro.org
10
---
13
---
11
fpu/softfloat.c | 2 +-
14
meson.build | 9 ++++++---
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
.gitlab-ci.d/buildtest-template.yml | 1 -
16
2 files changed, 6 insertions(+), 4 deletions(-)
13
17
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
18
diff --git a/meson.build b/meson.build
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
20
--- a/meson.build
17
+++ b/fpu/softfloat.c
21
+++ b/meson.build
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
22
@@ -XXX,XX +XXX,XX @@ project('qemu', ['c'], meson_version: '>=1.5.0',
19
23
20
static FloatParts int_to_float(int64_t a, float_status *status)
24
meson.add_devenv({ 'MESON_BUILD_ROOT' : meson.project_build_root() })
21
{
25
22
- FloatParts r;
26
-add_test_setup('quick', exclude_suites: ['slow', 'thorough'], is_default: true)
23
+ FloatParts r = {};
27
-add_test_setup('slow', exclude_suites: ['thorough'], env: ['G_TEST_SLOW=1', 'SPEED=slow'])
24
if (a == 0) {
28
-add_test_setup('thorough', env: ['G_TEST_SLOW=1', 'SPEED=thorough'])
25
r.cls = float_class_zero;
29
+add_test_setup('quick', exclude_suites: ['slow', 'thorough'], is_default: true,
26
r.sign = false;
30
+ env: ['RUST_BACKTRACE=1'])
31
+add_test_setup('slow', exclude_suites: ['thorough'],
32
+ env: ['G_TEST_SLOW=1', 'SPEED=slow', 'RUST_BACKTRACE=1'])
33
+add_test_setup('thorough',
34
+ env: ['G_TEST_SLOW=1', 'SPEED=thorough', 'RUST_BACKTRACE=1'])
35
36
meson.add_postconf_script(find_program('scripts/symlink-install-tree.py'))
37
38
diff --git a/.gitlab-ci.d/buildtest-template.yml b/.gitlab-ci.d/buildtest-template.yml
39
index XXXXXXX..XXXXXXX 100644
40
--- a/.gitlab-ci.d/buildtest-template.yml
41
+++ b/.gitlab-ci.d/buildtest-template.yml
42
@@ -XXX,XX +XXX,XX @@
43
stage: test
44
image: $CI_REGISTRY_IMAGE/qemu/$IMAGE:$QEMU_CI_CONTAINER_TAG
45
script:
46
- - export RUST_BACKTRACE=1
47
- source scripts/ci/gitlab-ci-section
48
- section_start buildenv "Setting up to run tests"
49
- scripts/git-submodule.sh update roms/SLOF
27
--
50
--
28
2.17.0
51
2.43.0
29
52
30
53
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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