[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/21] target-arm queue
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The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
1
Here's another arm pullreq; nothing too exciting in here I think.
2
2
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
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thanks
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-- PMM
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6
The following changes since commit 5fee33d97a7f2e95716417bd164f2f5264acd976:
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8
Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu into staging (2024-04-29 14:34:25 -0700)
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9
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are available in the Git repository at:
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are available in the Git repository at:
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11
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240430
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13
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for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
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for you to fetch changes up to a0c325c4b05cf7815739d6a84e567b95c8c5be7e:
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15
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tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
16
tests/qtest : Add testcase for DM163 (2024-04-30 16:05:08 +0100)
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17
13
----------------------------------------------------------------
18
----------------------------------------------------------------
14
target-arm queue:
19
target-arm queue:
15
* Fix coverity nit in int_to_float code
20
* hw/core/clock: allow clock_propagate on child clocks
16
* Don't set Invalid for float-to-int(MAXINT)
21
* hvf: arm: Remove unused PL1_WRITE_MASK define
17
* Fix fp_status_f16 tininess before rounding
22
* target/arm: Restrict translation disabled alignment check to VMSA
18
* Add various missing insns from the v8.2-FP16 extension
23
* docs/system/arm/emulation.rst: Add missing implemented features
19
* Fix sqrt_f16 exception raising
24
* target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max'
20
* sdcard: Correct CRC16 offset in sd_function_switch()
25
* tests/avocado: update sunxi kernel from armbian to 6.6.16
21
* tcg: Optionally log FPU state in TCG -d cpu logging
26
* target/arm: Make new CPUs default to 1GHz generic timer
27
* hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
28
* hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
29
* hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
30
* hw/arm: Add DM163 display to B-L475E-IOT01A board
22
31
23
----------------------------------------------------------------
32
----------------------------------------------------------------
24
Alex Bennée (5):
33
Alexandra Diupina (1):
25
fpu/softfloat: int_to_float ensure r fully initialised
34
hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
30
35
31
Peter Maydell (3):
36
Inès Varhol (5):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
37
hw/display : Add device DM163
33
target/arm: Fix fp_status_f16 tininess before rounding
38
hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
34
tcg: Optionally log FPU state in TCG -d cpu logging
39
hw/arm : Create Bl475eMachineState
40
hw/arm : Connect DM163 to B-L475E-IOT01A
41
tests/qtest : Add testcase for DM163
42
43
Peter Maydell (10):
44
docs/system/arm/emulation.rst: Add missing implemented features
45
target/arm: Enable FEAT_CSV2_3 for -cpu max
46
target/arm: Enable FEAT_ETS2 for -cpu max
47
target/arm: Implement ID_AA64MMFR3_EL1
48
target/arm: Enable FEAT_Spec_FPACC for -cpu max
49
tests/avocado: update sunxi kernel from armbian to 6.6.16
50
target/arm: Refactor default generic timer frequency handling
51
hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
52
hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
53
target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
35
54
36
Philippe Mathieu-Daudé (1):
55
Philippe Mathieu-Daudé (1):
37
sdcard: Correct CRC16 offset in sd_function_switch()
56
hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
38
57
39
Richard Henderson (7):
58
Raphael Poggi (1):
40
target/arm: Implement FMOV (general) for fp16
59
hw/core/clock: allow clock_propagate on child clocks
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
47
60
48
include/qemu/log.h | 1 +
61
Richard Henderson (1):
49
target/arm/helper-a64.h | 2 +
62
target/arm: Restrict translation disabled alignment check to VMSA
50
target/arm/helper.h | 6 +
51
accel/tcg/cpu-exec.c | 9 +-
52
fpu/softfloat.c | 6 +-
53
hw/sd/sd.c | 2 +-
54
target/arm/cpu.c | 2 +
55
target/arm/helper-a64.c | 10 ++
56
target/arm/helper.c | 38 +++-
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
58
util/log.c | 2 +
59
11 files changed, 428 insertions(+), 71 deletions(-)
60
63
64
Thomas Huth (1):
65
hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
66
67
Zenghui Yu (1):
68
hvf: arm: Remove PL1_WRITE_MASK
69
70
docs/system/arm/b-l475e-iot01a.rst | 3 +-
71
docs/system/arm/emulation.rst | 42 ++++-
72
include/hw/display/dm163.h | 59 ++++++
73
include/hw/watchdog/sbsa_gwdt.h | 3 +-
74
target/arm/cpu.h | 28 +++
75
target/arm/internals.h | 15 +-
76
hw/arm/b-l475e-iot01a.c | 105 +++++++++--
77
hw/arm/npcm7xx.c | 3 +-
78
hw/arm/sbsa-ref.c | 16 ++
79
hw/arm/stm32l4x5_soc.c | 6 +-
80
hw/char/stm32l4x5_usart.c | 1 +
81
hw/core/clock.c | 1 -
82
hw/core/machine.c | 4 +-
83
hw/display/dm163.c | 349 ++++++++++++++++++++++++++++++++++++
84
hw/dma/xlnx_dpdma.c | 20 +--
85
hw/watchdog/sbsa_gwdt.c | 15 +-
86
target/arm/cpu.c | 42 +++--
87
target/arm/cpu64.c | 2 +
88
target/arm/helper.c | 22 +--
89
target/arm/hvf/hvf.c | 3 +-
90
target/arm/kvm.c | 2 +
91
target/arm/tcg/cpu32.c | 6 +-
92
target/arm/tcg/cpu64.c | 28 ++-
93
target/arm/tcg/hflags.c | 12 +-
94
tests/qtest/dm163-test.c | 194 ++++++++++++++++++++
95
tests/qtest/stm32l4x5_gpio-test.c | 13 +-
96
tests/qtest/stm32l4x5_syscfg-test.c | 17 +-
97
hw/arm/Kconfig | 1 +
98
hw/display/Kconfig | 3 +
99
hw/display/meson.build | 1 +
100
hw/display/trace-events | 14 ++
101
tests/avocado/boot_linux_console.py | 70 ++++----
102
tests/avocado/replay_kernel.py | 8 +-
103
tests/qtest/meson.build | 2 +
104
34 files changed, 987 insertions(+), 123 deletions(-)
105
create mode 100644 include/hw/display/dm163.h
106
create mode 100644 hw/display/dm163.c
107
create mode 100644 tests/qtest/dm163-test.c
108
diff view generated by jsdifflib
New patch
[PULL 01/21] hw/core/clock: allow clock_propagate on child clocks
1
From: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
1
2
3
clock_propagate() has an assert that clk->source is NULL, i.e. that
4
you are calling it on a clock which has no source clock. This made
5
sense in the original design where the only way for a clock's
6
frequency to change if it had a source clock was when that source
7
clock changed. However, we subsequently added multiplier/divider
8
support, but didn't look at what that meant for propagation.
9
10
If a clock-management device changes the multiplier or divider value
11
on a clock, it needs to propagate that change down to child clocks,
12
even if the clock has a source clock set. So the assertion is now
13
incorrect.
14
15
Remove the assertion.
16
17
Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk>
18
Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
20
[PMM: Rewrote the commit message]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/core/clock.c | 1 -
24
1 file changed, 1 deletion(-)
25
26
diff --git a/hw/core/clock.c b/hw/core/clock.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/core/clock.c
29
+++ b/hw/core/clock.c
30
@@ -XXX,XX +XXX,XX @@ static void clock_propagate_period(Clock *clk, bool call_callbacks)
31
32
void clock_propagate(Clock *clk)
33
{
34
- assert(clk->source == NULL);
35
trace_clock_propagate(CLOCK_PATH(clk));
36
clock_propagate_period(clk, true);
37
}
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 02/21] hvf: arm: Remove PL1_WRITE_MASK
1
From: Zenghui Yu <zenghui.yu@linux.dev>
1
2
3
As it had never been used since the first commit a1477da3ddeb ("hvf: Add
4
Apple Silicon support").
5
6
Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev>
7
Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/hvf/hvf.c | 1 -
12
1 file changed, 1 deletion(-)
13
14
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/hvf/hvf.c
17
+++ b/target/arm/hvf/hvf.c
18
@@ -XXX,XX +XXX,XX @@ void hvf_arm_init_debug(void)
19
20
#define HVF_SYSREG(crn, crm, op0, op1, op2) \
21
ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
22
-#define PL1_WRITE_MASK 0x4
23
24
#define SYSREG_OP0_SHIFT 20
25
#define SYSREG_OP0_MASK 0x3
26
--
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2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
[PULL 03/21] target/arm: Restrict translation disabled alignment check to VMSA
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From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 fma operations.
3
For cpus using PMSA, when the MPU is disabled, the default memory
4
type is Normal, Non-cachable. This means that it should not
5
have alignment restrictions enforced.
4
6
5
Cc: qemu-stable@nongnu.org
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Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled")
9
Reported-by: Clément Chigot <chigot@adacore.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
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Tested-by: Clément Chigot <chigot@adacore.com>
13
Message-id: 20240422170722.117409-1-richard.henderson@linaro.org
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[PMM: trivial comment, commit message tweaks]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
17
target/arm/tcg/hflags.c | 12 ++++++++++--
13
1 file changed, 48 insertions(+)
18
1 file changed, 10 insertions(+), 2 deletions(-)
14
19
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
22
--- a/target/arm/tcg/hflags.c
18
+++ b/target/arm/translate-a64.c
23
+++ b/target/arm/tcg/hflags.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
24
@@ -XXX,XX +XXX,XX @@ static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr)
20
tcg_temp_free_i64(tcg_res);
25
}
21
}
26
22
27
/*
23
+/* Floating-point data-processing (3 source) - half precision */
28
- * If translation is disabled, then the default memory type is
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
29
- * Device(-nGnRnE) instead of Normal, which requires that alignment
25
+ int rd, int rn, int rm, int ra)
30
+ * With PMSA, when the MPU is disabled, all memory types in the
26
+{
31
+ * default map are Normal, so don't need aligment enforcing.
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
30
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
32
+ tcg_op2 = read_fp_hreg(s, rm);
33
+ tcg_op3 = read_fp_hreg(s, ra);
34
+
35
+ /* These are fused multiply-add, and must be done as one
36
+ * floating point operation with no rounding between the
37
+ * multiplication and addition steps.
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
32
+ */
42
+ if (o1 == true) {
33
+ if (arm_feature(env, ARM_FEATURE_PMSA)) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
34
+ return false;
44
+ }
35
+ }
45
+
36
+
46
+ if (o0 != o1) {
37
+ /*
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
38
+ * With VMSA, if translation is disabled, then the default memory type
48
+ }
39
+ * is Device(-nGnRnE) instead of Normal, which requires that alignment
49
+
40
* be enforced. Since this affects all ram, it is most efficient
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
41
* to handle this during translation.
51
+
42
*/
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
59
+}
60
+
61
/* Floating point data-processing (3 source)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
65
}
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
67
break;
68
+ case 3:
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
+ unallocated_encoding(s);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
80
}
81
--
43
--
82
2.17.0
44
2.34.1
83
45
84
46
diff view generated by jsdifflib
New patch
[PULL 04/21] docs/system/arm/emulation.rst: Add missing implemented features
1
As of version DDI0487K.a of the Arm ARM, some architectural features
2
which previously didn't have official names have been named. Add
3
these to the list of features which QEMU's TCG emulation supports.
4
Mostly these are features which we thought of as part of baseline 8.0
5
support. For SVE and SVE2, the names have been brought into line
6
with the FEAT_* naming convention of other extensions, and some
7
sub-components split into separate FEAT_ items. In a few cases (eg
8
FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
13
---
14
docs/system/arm/emulation.rst | 38 +++++++++++++++++++++++++++++++++--
15
1 file changed, 36 insertions(+), 2 deletions(-)
16
17
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
18
index XXXXXXX..XXXXXXX 100644
19
--- a/docs/system/arm/emulation.rst
20
+++ b/docs/system/arm/emulation.rst
21
@@ -XXX,XX +XXX,XX @@ Armv8 versions of the A-profile architecture. It also has support for
22
the following architecture extensions:
23
24
- FEAT_AA32BF16 (AArch32 BFloat16 instructions)
25
+- FEAT_AA32EL0 (Support for AArch32 at EL0)
26
+- FEAT_AA32EL1 (Support for AArch32 at EL1)
27
+- FEAT_AA32EL2 (Support for AArch32 at EL2)
28
+- FEAT_AA32EL3 (Support for AArch32 at EL3)
29
- FEAT_AA32HPD (AArch32 hierarchical permission disables)
30
- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
31
+- FEAT_AA64EL0 (Support for AArch64 at EL0)
32
+- FEAT_AA64EL1 (Support for AArch64 at EL1)
33
+- FEAT_AA64EL2 (Support for AArch64 at EL2)
34
+- FEAT_AA64EL3 (Support for AArch64 at EL3)
35
+- FEAT_AdvSIMD (Advanced SIMD Extension)
36
- FEAT_AES (AESD and AESE instructions)
37
+- FEAT_Armv9_Crypto (Armv9 Cryptographic Extension)
38
+- FEAT_ASID16 (16 bit ASID)
39
- FEAT_BBM at level 2 (Translation table break-before-make levels)
40
- FEAT_BF16 (AArch64 BFloat16 instructions)
41
- FEAT_BTI (Branch Target Identification)
42
+- FEAT_CCIDX (Extended cache index)
43
- FEAT_CRC32 (CRC32 instructions)
44
+- FEAT_Crypto (Cryptographic Extension)
45
- FEAT_CSV2 (Cache speculation variant 2)
46
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
47
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
48
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
49
- FEAT_DGH (Data gathering hint)
50
- FEAT_DIT (Data Independent Timing instructions)
51
- FEAT_DPB (DC CVAP instruction)
52
+- FEAT_DPB2 (DC CVADP instruction)
53
+- FEAT_Debugv8p1 (Debug with VHE)
54
- FEAT_Debugv8p2 (Debug changes for v8.2)
55
- FEAT_Debugv8p4 (Debug changes for v8.4)
56
- FEAT_DotProd (Advanced SIMD dot product instructions)
57
- FEAT_DoubleFault (Double Fault Extension)
58
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
59
- FEAT_ECV (Enhanced Counter Virtualization)
60
+- FEAT_EL0 (Support for execution at EL0)
61
+- FEAT_EL1 (Support for execution at EL1)
62
+- FEAT_EL2 (Support for execution at EL2)
63
+- FEAT_EL3 (Support for execution at EL3)
64
- FEAT_EPAC (Enhanced pointer authentication)
65
- FEAT_ETS (Enhanced Translation Synchronization)
66
- FEAT_EVT (Enhanced Virtualization Traps)
67
+- FEAT_F32MM (Single-precision Matrix Multiplication)
68
+- FEAT_F64MM (Double-precision Matrix Multiplication)
69
- FEAT_FCMA (Floating-point complex number instructions)
70
- FEAT_FGT (Fine-Grained Traps)
71
- FEAT_FHM (Floating-point half-precision multiplication instructions)
72
+- FEAT_FP (Floating Point extensions)
73
- FEAT_FP16 (Half-precision floating-point data processing)
74
- FEAT_FPAC (Faulting on AUT* instructions)
75
- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
76
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
77
- FEAT_LSE (Large System Extensions)
78
- FEAT_LSE2 (Large System Extensions v2)
79
- FEAT_LVA (Large Virtual Address space)
80
+- FEAT_MixedEnd (Mixed-endian support)
81
+- FEAT_MixdEndEL0 (Mixed-endian support at EL0)
82
- FEAT_MOPS (Standardization of memory operations)
83
- FEAT_MTE (Memory Tagging Extension)
84
- FEAT_MTE2 (Memory Tagging Extension)
85
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
86
+- FEAT_MTE_ASYM_FAULT (Memory tagging asymmetric faults)
87
- FEAT_NMI (Non-maskable Interrupt)
88
- FEAT_NV (Nested Virtualization)
89
- FEAT_NV2 (Enhanced nested virtualization support)
90
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
91
- FEAT_PAuth (Pointer authentication)
92
- FEAT_PAuth2 (Enhancements to pointer authentication)
93
- FEAT_PMULL (PMULL, PMULL2 instructions)
94
+- FEAT_PMUv3 (PMU extension version 3)
95
- FEAT_PMUv3p1 (PMU Extensions v3.1)
96
- FEAT_PMUv3p4 (PMU Extensions v3.4)
97
- FEAT_PMUv3p5 (PMU Extensions v3.5)
98
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
99
- FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)
100
- FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)
101
- FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)
102
+- FEAT_SVE (Scalable Vector Extension)
103
+- FEAT_SVE_AES (Scalable Vector AES instructions)
104
+- FEAT_SVE_BitPerm (Scalable Vector Bit Permutes instructions)
105
+- FEAT_SVE_PMULL128 (Scalable Vector PMULL instructions)
106
+- FEAT_SVE_SHA3 (Scalable Vector SHA3 instructions)
107
+- FEAT_SVE_SM4 (Scalable Vector SM4 instructions)
108
+- FEAT_SVE2 (Scalable Vector Extension version 2)
109
- FEAT_SPECRES (Speculation restriction instructions)
110
- FEAT_SSBS (Speculative Store Bypass Safe)
111
+- FEAT_TGran16K (Support for 16KB memory translation granule size at stage 1)
112
+- FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1)
113
+- FEAT_TGran64K (Support for 64KB memory translation granule size at stage 1)
114
- FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)
115
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
116
- FEAT_TLBIRANGE (TLB invalidate range instructions)
117
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
118
- FEAT_VHE (Virtualization Host Extensions)
119
- FEAT_VMID16 (16-bit VMID)
120
- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)
121
-- SVE (The Scalable Vector Extension)
122
-- SVE2 (The Scalable Vector Extension v2)
123
124
For information on the specifics of these extensions, please refer
125
to the `Armv8-A Arm Architecture Reference Manual
126
--
127
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
[PULL 05/21] target/arm: Enable FEAT_CSV2_3 for -cpu max
1
From: Alex Bennée <alex.bennee@linaro.org>
1
FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose
2
information about whether branch targets and branch history trained
3
in one hardware described context can control speculative execution
4
in a different hardware context.
2
5
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
6
There is no branch prediction in TCG, so we don't need to do anything
4
later on so we might as well mirror that.
7
to be compliant with this. Upadte the '-cpu max' ID registers to
8
advertise the feature.
5
9
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
10
---
14
---
11
fpu/softfloat.c | 2 +-
15
docs/system/arm/emulation.rst | 1 +
12
1 file changed, 1 insertion(+), 1 deletion(-)
16
target/arm/tcg/cpu64.c | 4 ++--
17
2 files changed, 3 insertions(+), 2 deletions(-)
13
18
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
21
--- a/docs/system/arm/emulation.rst
17
+++ b/fpu/softfloat.c
22
+++ b/docs/system/arm/emulation.rst
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
19
24
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
20
static FloatParts int_to_float(int64_t a, float_status *status)
25
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
21
{
26
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
22
- FloatParts r;
27
+- FEAT_CSV2_3 (Cache speculation variant 2, version 3)
23
+ FloatParts r = {};
28
- FEAT_CSV3 (Cache speculation variant 3)
24
if (a == 0) {
29
- FEAT_DGH (Data gathering hint)
25
r.cls = float_class_zero;
30
- FEAT_DIT (Data Independent Timing instructions)
26
r.sign = false;
31
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu64.c
34
+++ b/target/arm/tcg/cpu64.c
35
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
36
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
37
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
38
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
39
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
40
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */
41
t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
42
cpu->isar.id_aa64pfr0 = t;
43
44
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
45
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
46
t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
47
t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
48
- t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
49
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
50
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
51
cpu->isar.id_aa64pfr1 = t;
52
27
--
53
--
28
2.17.0
54
2.34.1
29
55
30
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
[PULL 06/21] target/arm: Enable FEAT_ETS2 for -cpu max
1
From: Alex Bennée <alex.bennee@linaro.org>
1
FEAT_ETS2 is a tighter set of guarantees about memory ordering
2
involving translation table walks than the old FEAT_ETS; FEAT_ETS has
3
been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1
4
now gives no greater guarantees than ETS == 0.
2
5
3
All the hard work is already done by vfp_expand_imm, we just need to
6
FEAT_ETS2 requires:
4
make sure we pick up the correct size.
7
* the virtual address of a load or store that appears in program
8
order after a DSB cannot be translated until after the DSB
9
completes (section B2.10.9)
10
* TLB maintenance operations that only affect translations without
11
execute permission are guaranteed complete after a DSB
12
(R_BLDZX)
13
* if a memory access RW2 is ordered-before memory access RW2,
14
then RW1 is also ordered-before any translation table walk
15
generated by RW2 that generates a Translation, Address size
16
or Access flag fault (R_NNFPF, I_CLGHP)
5
17
6
Cc: qemu-stable@nongnu.org
18
As with FEAT_ETS, QEMU is already compliant, because we do not
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
reorder translation table walk memory accesses relative to other
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
20
memory accesses, and we always guarantee to have finished TLB
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
21
maintenance as soon as the TLB op is done.
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
22
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
23
Update the documentation to list FEAT_ETS2 instead of the
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
24
no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers.
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
25
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
29
Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
15
---
30
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
31
docs/system/arm/emulation.rst | 2 +-
17
1 file changed, 17 insertions(+), 3 deletions(-)
32
target/arm/tcg/cpu32.c | 2 +-
33
target/arm/tcg/cpu64.c | 2 +-
34
3 files changed, 3 insertions(+), 3 deletions(-)
18
35
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
36
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
20
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
38
--- a/docs/system/arm/emulation.rst
22
+++ b/target/arm/translate-a64.c
39
+++ b/docs/system/arm/emulation.rst
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
40
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
24
{
41
- FEAT_EL2 (Support for execution at EL2)
25
int rd = extract32(insn, 0, 5);
42
- FEAT_EL3 (Support for execution at EL3)
26
int imm8 = extract32(insn, 13, 8);
43
- FEAT_EPAC (Enhanced pointer authentication)
27
- int is_double = extract32(insn, 22, 2);
44
-- FEAT_ETS (Enhanced Translation Synchronization)
28
+ int type = extract32(insn, 22, 2);
45
+- FEAT_ETS2 (Enhanced Translation Synchronization)
29
uint64_t imm;
46
- FEAT_EVT (Enhanced Virtualization Traps)
30
TCGv_i64 tcg_res;
47
- FEAT_F32MM (Single-precision Matrix Multiplication)
31
+ TCGMemOp sz;
48
- FEAT_F64MM (Double-precision Matrix Multiplication)
32
49
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
33
- if (is_double > 1) {
50
index XXXXXXX..XXXXXXX 100644
34
+ switch (type) {
51
--- a/target/arm/tcg/cpu32.c
35
+ case 0:
52
+++ b/target/arm/tcg/cpu32.c
36
+ sz = MO_32;
53
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
37
+ break;
54
cpu->isar.id_mmfr4 = t;
38
+ case 1:
55
39
+ sz = MO_64;
56
t = cpu->isar.id_mmfr5;
40
+ break;
57
- t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
41
+ case 3:
58
+ t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
42
+ sz = MO_16;
59
cpu->isar.id_mmfr5 = t;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
60
44
+ break;
61
t = cpu->isar.id_pfr0;
45
+ }
62
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
46
+ /* fallthru */
63
index XXXXXXX..XXXXXXX 100644
47
+ default:
64
--- a/target/arm/tcg/cpu64.c
48
unallocated_encoding(s);
65
+++ b/target/arm/tcg/cpu64.c
49
return;
66
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
50
}
67
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
68
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
52
return;
69
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
53
}
70
- t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
54
71
+ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 2); /* FEAT_ETS2 */
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
72
t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
56
+ imm = vfp_expand_imm(sz, imm8);
73
t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
57
74
cpu->isar.id_aa64mmfr1 = t;
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
60
--
75
--
61
2.17.0
76
2.34.1
62
77
63
78
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
[PULL 07/21] target/arm: Implement ID_AA64MMFR3_EL1
1
In float-to-integer conversion, if the floating point input
1
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for
2
converts exactly to the largest or smallest integer that
2
ID_AA64MMFR3_EL1. Implement this register, so that we can set the
3
fits in to the result type, this is not an overflow.
3
fields if we need to. There's no behaviour change here since we
4
In this situation we were producing the correct result value,
4
don't currently set the register value to non-zero.
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
5
9
Fix the boundary case to take the right half of the if()
10
statements.
11
12
This fixes a regression from 2.11 introduced by the softfloat
13
refactoring.
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
20
---
10
---
21
fpu/softfloat.c | 4 ++--
11
target/arm/cpu.h | 17 +++++++++++++++++
22
1 file changed, 2 insertions(+), 2 deletions(-)
12
target/arm/helper.c | 6 ++++--
13
target/arm/hvf/hvf.c | 2 ++
14
target/arm/kvm.c | 2 ++
15
4 files changed, 25 insertions(+), 2 deletions(-)
23
16
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
19
--- a/target/arm/cpu.h
27
+++ b/fpu/softfloat.c
20
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
21
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
29
r = UINT64_MAX;
22
uint64_t id_aa64mmfr0;
30
}
23
uint64_t id_aa64mmfr1;
31
if (p.sign) {
24
uint64_t id_aa64mmfr2;
32
- if (r < -(uint64_t) min) {
25
+ uint64_t id_aa64mmfr3;
33
+ if (r <= -(uint64_t) min) {
26
uint64_t id_aa64dfr0;
34
return -r;
27
uint64_t id_aa64dfr1;
35
} else {
28
uint64_t id_aa64zfr0;
36
s->float_exception_flags = orig_flags | float_flag_invalid;
29
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
37
return min;
30
FIELD(ID_AA64MMFR2, EVT, 56, 4)
38
}
31
FIELD(ID_AA64MMFR2, E0PD, 60, 4)
39
} else {
32
40
- if (r < max) {
33
+FIELD(ID_AA64MMFR3, TCRX, 0, 4)
41
+ if (r <= max) {
34
+FIELD(ID_AA64MMFR3, SCTLRX, 4, 4)
42
return r;
35
+FIELD(ID_AA64MMFR3, S1PIE, 8, 4)
43
} else {
36
+FIELD(ID_AA64MMFR3, S2PIE, 12, 4)
44
s->float_exception_flags = orig_flags | float_flag_invalid;
37
+FIELD(ID_AA64MMFR3, S1POE, 16, 4)
38
+FIELD(ID_AA64MMFR3, S2POE, 20, 4)
39
+FIELD(ID_AA64MMFR3, AIE, 24, 4)
40
+FIELD(ID_AA64MMFR3, MEC, 28, 4)
41
+FIELD(ID_AA64MMFR3, D128, 32, 4)
42
+FIELD(ID_AA64MMFR3, D128_2, 36, 4)
43
+FIELD(ID_AA64MMFR3, SNERR, 40, 4)
44
+FIELD(ID_AA64MMFR3, ANERR, 44, 4)
45
+FIELD(ID_AA64MMFR3, SDERR, 52, 4)
46
+FIELD(ID_AA64MMFR3, ADERR, 56, 4)
47
+FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4)
48
+
49
FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
50
FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
51
FIELD(ID_AA64DFR0, PMUVER, 8, 4)
52
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/helper.c
55
+++ b/target/arm/helper.c
56
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
57
.access = PL1_R, .type = ARM_CP_CONST,
58
.accessfn = access_aa64_tid3,
59
.resetvalue = cpu->isar.id_aa64mmfr2 },
60
- { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
61
+ { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
62
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
63
.access = PL1_R, .type = ARM_CP_CONST,
64
.accessfn = access_aa64_tid3,
65
- .resetvalue = 0 },
66
+ .resetvalue = cpu->isar.id_aa64mmfr3 },
67
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
68
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
69
.access = PL1_R, .type = ARM_CP_CONST,
70
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
71
.exported_bits = R_ID_AA64MMFR1_AFP_MASK },
72
{ .name = "ID_AA64MMFR2_EL1",
73
.exported_bits = R_ID_AA64MMFR2_AT_MASK },
74
+ { .name = "ID_AA64MMFR3_EL1",
75
+ .exported_bits = 0 },
76
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
77
.is_glob = true },
78
{ .name = "ID_AA64DFR0_EL1",
79
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/target/arm/hvf/hvf.c
82
+++ b/target/arm/hvf/hvf.c
83
@@ -XXX,XX +XXX,XX @@ static struct hvf_sreg_match hvf_sreg_match[] = {
84
#endif
85
{ HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) },
86
{ HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) },
87
+ /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
88
89
{ HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) },
90
{ HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) },
91
@@ -XXX,XX +XXX,XX @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
92
{ HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
93
{ HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
94
{ HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
95
+ /* Add ID_AA64MMFR3_EL1 here when HVF supports it */
96
};
97
hv_vcpu_t fd;
98
hv_return_t r = HV_SUCCESS;
99
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
100
index XXXXXXX..XXXXXXX 100644
101
--- a/target/arm/kvm.c
102
+++ b/target/arm/kvm.c
103
@@ -XXX,XX +XXX,XX @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
104
ARM64_SYS_REG(3, 0, 0, 7, 1));
105
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
106
ARM64_SYS_REG(3, 0, 0, 7, 2));
107
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
108
+ ARM64_SYS_REG(3, 0, 0, 7, 3));
109
110
/*
111
* Note that if AArch32 support is not present in the host,
45
--
112
--
46
2.17.0
113
2.34.1
47
114
48
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
[PULL 08/21] target/arm: Enable FEAT_Spec_FPACC for -cpu max
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
FEAT_Spec_FPACC is a feature describing speculative behaviour in the
2
to diagnose problems, but sometimes you want to see the state of
2
event of a PAC authontication failure when FEAT_FPACCOMBINE is
3
the floating point registers as well. We don't want to enable that
3
implemented. FEAT_Spec_FPACC means that the speculative use of
4
by default as it adds a lot of extra data to the log; instead,
4
pointers processed by a PAC Authentication is not materially
5
allow it to be optionally enabled via -d fpu.
5
different in terms of the impact on cached microarchitectural state
6
(caches, TLBs, etc) between passing and failing of the PAC
7
Authentication.
8
9
QEMU doesn't do speculative execution, so we can advertise
10
this feature.
6
11
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
10
---
16
---
11
include/qemu/log.h | 1 +
17
docs/system/arm/emulation.rst | 1 +
12
accel/tcg/cpu-exec.c | 9 ++++++---
18
target/arm/tcg/cpu64.c | 4 ++++
13
util/log.c | 2 ++
19
2 files changed, 5 insertions(+)
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
20
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
21
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
23
--- a/docs/system/arm/emulation.rst
19
+++ b/include/qemu/log.h
24
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
25
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
#define CPU_LOG_PAGE (1 << 14)
26
- FEAT_FP16 (Half-precision floating-point data processing)
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
27
- FEAT_FPAC (Faulting on AUT* instructions)
23
#define CPU_LOG_TB_OP_IND (1 << 16)
28
- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)
24
+#define CPU_LOG_TB_FPU (1 << 17)
29
+- FEAT_FPACC_SPEC (Speculative behavior of combined pointer authentication instructions)
25
30
- FEAT_FRINTTS (Floating-point to integer instructions)
26
/* Lock output for a series of related logs. Since this is not needed
31
- FEAT_FlagM (Flag manipulation instructions v2)
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
32
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
33
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
29
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/cpu-exec.c
35
--- a/target/arm/tcg/cpu64.c
31
+++ b/accel/tcg/cpu-exec.c
36
+++ b/target/arm/tcg/cpu64.c
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
37
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
38
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
34
&& qemu_log_in_addr_range(itb->pc)) {
39
cpu->isar.id_aa64mmfr2 = t;
35
qemu_log_lock();
40
36
+ int flags = 0;
41
+ t = cpu->isar.id_aa64mmfr3;
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
42
+ t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
38
+ flags |= CPU_DUMP_FPU;
43
+ cpu->isar.id_aa64mmfr3 = t;
39
+ }
44
+
40
#if defined(TARGET_I386)
45
t = cpu->isar.id_aa64zfr0;
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
46
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
42
-#else
47
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
43
- log_cpu_state(cpu, 0);
44
+ flags |= CPU_DUMP_CCOP;
45
#endif
46
+ log_cpu_state(cpu, flags);
47
qemu_log_unlock();
48
}
49
#endif /* DEBUG_DISAS */
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
63
--
48
--
64
2.17.0
49
2.34.1
65
50
66
51
diff view generated by jsdifflib
New patch
[PULL 09/21] tests/avocado: update sunxi kernel from armbian to 6.6.16
1
The Linux kernel 5.10.16 binary for sunxi has been removed from
2
apt.armbian.com. This means that the avocado tests for these machines
3
will be skipped (status CANCEL) if the old binary isn't present in
4
the avocado cache.
1
5
6
Update to 6.6.16, in the same way we did in commit e384db41d8661
7
when we moved to 5.10.16 in 2021.
8
9
Cc: qemu-stable@nongnu.org
10
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
13
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
14
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
15
Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
16
---
17
tests/avocado/boot_linux_console.py | 70 ++++++++++++++---------------
18
tests/avocado/replay_kernel.py | 8 ++--
19
2 files changed, 39 insertions(+), 39 deletions(-)
20
21
diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py
22
index XXXXXXX..XXXXXXX 100644
23
--- a/tests/avocado/boot_linux_console.py
24
+++ b/tests/avocado/boot_linux_console.py
25
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
26
:avocado: tags=accel:tcg
27
"""
28
deb_url = ('https://apt.armbian.com/pool/main/l/'
29
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
30
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
31
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
32
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
33
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
34
kernel_path = self.extract_from_deb(deb_path,
35
- '/boot/vmlinuz-5.10.16-sunxi')
36
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
37
+ '/boot/vmlinuz-6.6.16-current-sunxi')
38
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
39
dtb_path = self.extract_from_deb(deb_path, dtb_path)
40
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
41
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
42
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_sata(self):
43
:avocado: tags=accel:tcg
44
"""
45
deb_url = ('https://apt.armbian.com/pool/main/l/'
46
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
47
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
48
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
49
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
50
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
51
kernel_path = self.extract_from_deb(deb_path,
52
- '/boot/vmlinuz-5.10.16-sunxi')
53
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
54
+ '/boot/vmlinuz-6.6.16-current-sunxi')
55
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
56
dtb_path = self.extract_from_deb(deb_path, dtb_path)
57
rootfs_url = ('https://github.com/groeck/linux-build-test/raw/'
58
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
59
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u(self):
60
:avocado: tags=machine:bpim2u
61
:avocado: tags=accel:tcg
62
"""
63
- deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
64
- 'linux-image-current-sunxi_21.02.2_armhf.deb')
65
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
66
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
67
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
68
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
69
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
70
kernel_path = self.extract_from_deb(deb_path,
71
- '/boot/vmlinuz-5.10.16-sunxi')
72
- dtb_path = ('/usr/lib/linux-image-current-sunxi/'
73
+ '/boot/vmlinuz-6.6.16-current-sunxi')
74
+ dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
75
'sun8i-r40-bananapi-m2-ultra.dtb')
76
dtb_path = self.extract_from_deb(deb_path, dtb_path)
77
78
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_initrd(self):
79
:avocado: tags=accel:tcg
80
:avocado: tags=machine:bpim2u
81
"""
82
- deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
83
- 'linux-image-current-sunxi_21.02.2_armhf.deb')
84
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
85
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
86
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
87
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
88
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
89
kernel_path = self.extract_from_deb(deb_path,
90
- '/boot/vmlinuz-5.10.16-sunxi')
91
- dtb_path = ('/usr/lib/linux-image-current-sunxi/'
92
+ '/boot/vmlinuz-6.6.16-current-sunxi')
93
+ dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
94
'sun8i-r40-bananapi-m2-ultra.dtb')
95
dtb_path = self.extract_from_deb(deb_path, dtb_path)
96
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
97
@@ -XXX,XX +XXX,XX @@ def test_arm_bpim2u_gmac(self):
98
"""
99
self.require_netdev('user')
100
101
- deb_url = ('https://apt.armbian.com/pool/main/l/linux-5.10.16-sunxi/'
102
- 'linux-image-current-sunxi_21.02.2_armhf.deb')
103
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
104
+ deb_url = ('https://apt.armbian.com/pool/main/l/'
105
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
106
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
107
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
108
kernel_path = self.extract_from_deb(deb_path,
109
- '/boot/vmlinuz-5.10.16-sunxi')
110
- dtb_path = ('/usr/lib/linux-image-current-sunxi/'
111
+ '/boot/vmlinuz-6.6.16-current-sunxi')
112
+ dtb_path = ('/usr/lib/linux-image-6.6.16-current-sunxi/'
113
'sun8i-r40-bananapi-m2-ultra.dtb')
114
dtb_path = self.extract_from_deb(deb_path, dtb_path)
115
rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
116
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi(self):
117
:avocado: tags=accel:tcg
118
"""
119
deb_url = ('https://apt.armbian.com/pool/main/l/'
120
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
121
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
122
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
123
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
124
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
125
kernel_path = self.extract_from_deb(deb_path,
126
- '/boot/vmlinuz-5.10.16-sunxi')
127
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
128
+ '/boot/vmlinuz-6.6.16-current-sunxi')
129
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
130
dtb_path = self.extract_from_deb(deb_path, dtb_path)
131
132
self.vm.set_console()
133
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_initrd(self):
134
:avocado: tags=machine:orangepi-pc
135
"""
136
deb_url = ('https://apt.armbian.com/pool/main/l/'
137
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
138
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
139
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
140
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
141
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
142
kernel_path = self.extract_from_deb(deb_path,
143
- '/boot/vmlinuz-5.10.16-sunxi')
144
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
145
+ '/boot/vmlinuz-6.6.16-current-sunxi')
146
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
147
dtb_path = self.extract_from_deb(deb_path, dtb_path)
148
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
149
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
150
@@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_sd(self):
151
self.require_netdev('user')
152
153
deb_url = ('https://apt.armbian.com/pool/main/l/'
154
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
155
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
156
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
157
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
158
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
159
kernel_path = self.extract_from_deb(deb_path,
160
- '/boot/vmlinuz-5.10.16-sunxi')
161
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun8i-h3-orangepi-pc.dtb'
162
+ '/boot/vmlinuz-6.6.16-current-sunxi')
163
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun8i-h3-orangepi-pc.dtb'
164
dtb_path = self.extract_from_deb(deb_path, dtb_path)
165
rootfs_url = ('http://storage.kernelci.org/images/rootfs/buildroot/'
166
'buildroot-baseline/20221116.0/armel/rootfs.ext2.xz')
167
diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
168
index XXXXXXX..XXXXXXX 100644
169
--- a/tests/avocado/replay_kernel.py
170
+++ b/tests/avocado/replay_kernel.py
171
@@ -XXX,XX +XXX,XX @@ def test_arm_cubieboard_initrd(self):
172
:avocado: tags=machine:cubieboard
173
"""
174
deb_url = ('https://apt.armbian.com/pool/main/l/'
175
- 'linux-5.10.16-sunxi/linux-image-current-sunxi_21.02.2_armhf.deb')
176
- deb_hash = '9fa84beda245cabf0b4fa84cf6eaa7738ead1da0'
177
+ 'linux-6.6.16/linux-image-current-sunxi_24.2.1_armhf__6.6.16-Seb3e-D6b4a-P2359-Ce96bHfe66-HK01ba-V014b-B067e-R448a.deb')
178
+ deb_hash = 'f7c3c8c5432f765445dc6e7eab02f3bbe668256b'
179
deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)
180
kernel_path = self.extract_from_deb(deb_path,
181
- '/boot/vmlinuz-5.10.16-sunxi')
182
- dtb_path = '/usr/lib/linux-image-current-sunxi/sun4i-a10-cubieboard.dtb'
183
+ '/boot/vmlinuz-6.6.16-current-sunxi')
184
+ dtb_path = '/usr/lib/linux-image-6.6.16-current-sunxi/sun4i-a10-cubieboard.dtb'
185
dtb_path = self.extract_from_deb(deb_path, dtb_path)
186
initrd_url = ('https://github.com/groeck/linux-build-test/raw/'
187
'2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
188
--
189
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
[PULL 10/21] target/arm: Refactor default generic timer frequency handling
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The generic timer frequency is settable by board code via a QOM
2
property "cntfrq", but otherwise defaults to 62.5MHz. The way this
3
is done includes some complication resulting from how this was
4
originally a fixed value with no QOM property. Clean it up:
2
5
3
Cc: qemu-stable@nongnu.org
6
* always set cpu->gt_cntfrq_hz to some sensible value, whether
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
the CPU has the generic timer or not, and whether it's system
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
or user-only emulation
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
* this means we can always use gt_cntfrq_hz, and never need
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
10
the old GTIMER_SCALE define
11
* set the default value in exactly one place, in the realize fn
12
13
The aim here is to pave the way for handling the ARMv8.6 requirement
14
that the generic timer frequency is always 1GHz. We're going to do
15
that by having old CPU types keep their legacy-in-QEMU behaviour and
16
having the default for any new CPU types be a 1GHz rather han 62.5MHz
17
cntfrq, so we want the point where the default is decided to be in
18
one place, and in code, not in a DEFINE_PROP_UINT64() initializer.
19
20
This commit should have no behavioural changes.
21
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
24
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
9
---
26
---
10
target/arm/helper.h | 6 +++
27
target/arm/internals.h | 7 ++++---
11
target/arm/helper.c | 38 ++++++++++++++-
28
target/arm/cpu.c | 31 +++++++++++++++++--------------
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
29
target/arm/helper.c | 16 ++++++++--------
13
3 files changed, 122 insertions(+), 18 deletions(-)
30
3 files changed, 29 insertions(+), 25 deletions(-)
14
31
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
32
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
34
--- a/target/arm/internals.h
18
+++ b/target/arm/helper.h
35
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
36
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
37
|| excp == EXCP_SEMIHOST;
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
38
}
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
39
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
40
-/* Scale factor for generic timers, ie number of ns per tick.
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
41
- * This gives a 62.5MHz timer.
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
42
+/*
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
43
+ * Default frequency for the generic timer, in Hz.
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
44
+ * This is 62.5MHz, which gives a 16 ns tick period.
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
45
*/
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
46
-#define GTIMER_SCALE 16
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
47
+#define GTIMER_DEFAULT_HZ 62500000
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
48
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
49
/* Bit definitions for the v7M CONTROL register */
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
50
FIELD(V7M_CONTROL, NPRIV, 0, 1)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
51
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
52
index XXXXXXX..XXXXXXX 100644
36
53
--- a/target/arm/cpu.c
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
54
+++ b/target/arm/cpu.c
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
55
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
56
}
57
}
58
59
+/*
60
+ * 0 means "unset, use the default value". That default might vary depending
61
+ * on the CPU type, and is set in the realize fn.
62
+ */
63
static Property arm_cpu_gt_cntfrq_property =
64
- DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz,
65
- NANOSECONDS_PER_SECOND / GTIMER_SCALE);
66
+ DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
67
68
static Property arm_cpu_reset_cbar_property =
69
DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
70
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
71
return;
72
}
73
74
+ if (!cpu->gt_cntfrq_hz) {
75
+ /*
76
+ * 0 means "the board didn't set a value, use the default".
77
+ * The default value of the generic timer frequency (as seen in
78
+ * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
79
+ * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
80
+ * board doesn't set it.
81
+ */
82
+ cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
83
+ }
84
+
85
#ifndef CONFIG_USER_ONLY
86
/* The NVIC and M-profile CPU are two halves of a single piece of
87
* hardware; trying to use one without the other is a command line
88
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
89
}
90
91
{
92
- uint64_t scale;
93
-
94
- if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
95
- if (!cpu->gt_cntfrq_hz) {
96
- error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz",
97
- cpu->gt_cntfrq_hz);
98
- return;
99
- }
100
- scale = gt_cntfrq_period_ns(cpu);
101
- } else {
102
- scale = GTIMER_SCALE;
103
- }
104
+ uint64_t scale = gt_cntfrq_period_ns(cpu);
105
106
cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
107
arm_gt_ptimer_cb, cpu);
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
108
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
109
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
110
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
111
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6k_cp_reginfo[] = {
44
#undef VFP_CONV_FIX_A64
113
.resetvalue = 0 },
45
114
};
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
115
47
- * Therefore we convert to f64 (which does not round), scale,
116
+static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
48
- * and then convert f64 to f16 (which may round).
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
50
+ * vice versa for conversion to integer.
51
+ *
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
53
+ * For 64-bit integers, any integer that would cause rounding will also
54
+ * overflow to f16 infinity, so there is no double rounding problem.
55
*/
56
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
61
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
117
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
118
+ ARMCPU *cpu = env_archcpu(env);
119
+
120
+ cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
65
+}
121
+}
66
+
122
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
123
#ifndef CONFIG_USER_ONLY
68
+{
124
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
125
static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
70
+}
126
@@ -XXX,XX +XXX,XX @@ void arm_gt_hvtimer_cb(void *opaque)
71
+
127
gt_recalc_timer(cpu, GTIMER_HYPVIRT);
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
128
}
78
129
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
130
-static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaque)
80
+{
131
-{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
132
- ARMCPU *cpu = env_archcpu(env);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
133
-
237
- if (!sf) {
134
- cpu->env.cp15.c14_cntfrq = cpu->gt_cntfrq_hz;
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
135
-}
239
- }
136
-
240
}
137
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
241
138
/*
242
tcg_temp_free_ptr(tcg_fpstatus);
139
* Note that CNTFRQ is purely reads-as-written for the benefit
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
140
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
244
/* actual FP conversions */
141
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
245
bool itof = extract32(opcode, 1, 1);
142
.type = ARM_CP_CONST, .access = PL0_R /* no PL1_RW in linux-user */,
246
143
.fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
144
- .resetvalue = NANOSECONDS_PER_SECOND / GTIMER_SCALE,
248
+ if (rmode != 0 && opcode > 1) {
145
+ .resetfn = arm_gt_cntfrq_reset,
249
+ unallocated_encoding(s);
146
},
250
+ return;
147
{ .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
251
+ }
148
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
149
--
266
2.17.0
150
2.34.1
267
151
268
152
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
[PULL 11/21] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently QEMU CPUs always run with a generic timer counter frequency
2
of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of
3
the TF-A firmware that sbsa-ref runs, the frequency of the generic
4
timer is hardcoded into the firmware, and so if the CPU actually has
5
a different frequency then timers in the guest will be set
6
incorrectly.
2
7
3
No sense in emitting code after the exception.
8
The default frequency used by the 'max' CPU is about to change, so
9
make the sbsa-ref board force the CPU frequency to the value which
10
the firmware expects.
4
11
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Newer versions of TF-A will read the frequency from the CPU's
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
CNTFRQ_EL0 register:
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
14
https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
so in the longer term we could make this board use the 1GHz
16
frequency. We will need to make sure we update the binaries used
17
by our avocado test
18
Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
19
before we can do that.
20
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
23
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
24
Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
10
---
25
---
11
target/arm/translate-a64.c | 2 +-
26
hw/arm/sbsa-ref.c | 15 +++++++++++++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
27
1 file changed, 15 insertions(+)
13
28
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
29
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
31
--- a/hw/arm/sbsa-ref.c
17
+++ b/target/arm/translate-a64.c
32
+++ b/hw/arm/sbsa-ref.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
33
@@ -XXX,XX +XXX,XX @@
19
default:
34
#define NUM_SMMU_IRQS 4
20
/* all other sf/type/rmode combinations are invalid */
35
#define NUM_SATA_PORTS 6
21
unallocated_encoding(s);
36
22
- break;
37
+/*
23
+ return;
38
+ * Generic timer frequency in Hz (which drives both the CPU generic timers
39
+ * and the SBSA watchdog-timer). Older versions of the TF-A firmware
40
+ * typically used with sbsa-ref (including the binaries in our Avocado test
41
+ * Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef
42
+ * assume it is this value.
43
+ *
44
+ * TODO: this value is not architecturally correct for an Armv8.6 or
45
+ * better CPU, so we should move to 1GHz once the TF-A fix above has
46
+ * made it into a release and into our Avocado test.
47
+ */
48
+#define SBSA_GTIMER_HZ 62500000
49
+
50
enum {
51
SBSA_FLASH,
52
SBSA_MEM,
53
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
54
&error_abort);
24
}
55
}
25
56
26
if (!fp_access_check(s)) {
57
+ object_property_set_int(cpuobj, "cntfrq", SBSA_GTIMER_HZ, &error_abort);
58
+
59
object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
60
&error_abort);
61
27
--
62
--
28
2.17.0
63
2.34.1
29
64
30
65
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
[PULL 12/21] hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Currently the sbsa_gdwt watchdog device hardcodes its frequency at
2
62.5MHz. In real hardware, this watchdog is supposed to be driven
3
from the system counter, which also drives the CPU generic timers.
4
Newer CPU types (in particular from Armv8.6) should have a CPU
5
generic timer frequency of 1GHz, so we can't leave the watchdog
6
on the old QEMU default of 62.5GHz.
2
7
3
These where missed out from the rest of the half-precision work.
8
Make the frequency a QOM property so it can be set by the board,
9
and have our only board that uses this device set that frequency
10
to the same value it sets the CPU frequency.
4
11
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
14
---
15
---
15
target/arm/helper-a64.h | 2 +
16
include/hw/watchdog/sbsa_gwdt.h | 3 +--
16
target/arm/helper-a64.c | 10 +++++
17
hw/arm/sbsa-ref.c | 1 +
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
18
hw/watchdog/sbsa_gwdt.c | 15 ++++++++++++++-
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
3 files changed, 16 insertions(+), 3 deletions(-)
19
20
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
21
diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwdt.h
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
23
--- a/include/hw/watchdog/sbsa_gwdt.h
23
+++ b/target/arm/helper-a64.h
24
+++ b/include/hw/watchdog/sbsa_gwdt.h
24
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
26
#define SBSA_GWDT_RMMIO_SIZE 0x1000
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
27
#define SBSA_GWDT_CMMIO_SIZE 0x1000
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
28
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
29
-#define SBSA_TIMER_FREQ 62500000 /* Hz */
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
30
-
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
31
typedef struct SBSA_GWDTState {
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
32
/* <private> */
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
33
SysBusDevice parent_obj;
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
@@ -XXX,XX +XXX,XX @@ typedef struct SBSA_GWDTState {
35
qemu_irq irq;
36
37
QEMUTimer *timer;
38
+ uint64_t freq;
39
40
uint32_t id;
41
uint32_t wcs;
42
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
34
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
44
--- a/hw/arm/sbsa-ref.c
36
+++ b/target/arm/helper-a64.c
45
+++ b/hw/arm/sbsa-ref.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
46
@@ -XXX,XX +XXX,XX @@ static void create_wdt(const SBSAMachineState *sms)
38
return flags;
47
SysBusDevice *s = SYS_BUS_DEVICE(dev);
48
int irq = sbsa_ref_irqmap[SBSA_GWDT_WS0];
49
50
+ qdev_prop_set_uint64(dev, "clock-frequency", SBSA_GTIMER_HZ);
51
sysbus_realize_and_unref(s, &error_fatal);
52
sysbus_mmio_map(s, 0, rbase);
53
sysbus_mmio_map(s, 1, cbase);
54
diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/watchdog/sbsa_gwdt.c
57
+++ b/hw/watchdog/sbsa_gwdt.c
58
@@ -XXX,XX +XXX,XX @@
59
#include "qemu/osdep.h"
60
#include "sysemu/reset.h"
61
#include "sysemu/watchdog.h"
62
+#include "hw/qdev-properties.h"
63
#include "hw/watchdog/sbsa_gwdt.h"
64
#include "qemu/timer.h"
65
#include "migration/vmstate.h"
66
@@ -XXX,XX +XXX,XX @@ static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype)
67
timeout = s->woru;
68
timeout <<= 32;
69
timeout |= s->worl;
70
- timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_FREQ);
71
+ timeout = muldiv64(timeout, NANOSECONDS_PER_SECOND, s->freq);
72
timeout += qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
73
74
if ((rtype == EXPLICIT_REFRESH) || ((rtype == TIMEOUT_REFRESH) &&
75
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp)
76
dev);
39
}
77
}
40
78
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
79
+static Property wdt_sbsa_gwdt_props[] = {
42
+{
80
+ /*
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
81
+ * Timer frequency in Hz. This must match the frequency used by
44
+}
82
+ * the CPU's generic timer. Default 62.5Hz matches QEMU's legacy
83
+ * CPU timer frequency default.
84
+ */
85
+ DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq,
86
+ 62500000),
87
+ DEFINE_PROP_END_OF_LIST(),
88
+};
45
+
89
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
90
static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
52
{
91
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
92
DeviceClass *dc = DEVICE_CLASS(klass);
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
93
@@ -XXX,XX +XXX,XX @@ static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data)
55
index XXXXXXX..XXXXXXX 100644
94
set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
56
--- a/target/arm/translate-a64.c
95
dc->vmsd = &vmstate_sbsa_gwdt;
57
+++ b/target/arm/translate-a64.c
96
dc->desc = "SBSA-compliant generic watchdog device";
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
97
+ device_class_set_props(dc, wdt_sbsa_gwdt_props);
59
}
60
}
98
}
61
99
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
100
static const TypeInfo wdt_sbsa_gwdt_info = {
63
+static void handle_fp_compare(DisasContext *s, int size,
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
165
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
101
--
215
2.17.0
102
2.34.1
216
103
217
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
[PULL 13/21] target/arm: Default to 1GHz cntfrq for 'max' and new CPUs
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
In previous versions of the Arm architecture, the frequency of the
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
2
generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
3
by setting it to float_tininess_before_rounding. This currently
3
and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
4
will only cause problems for the new V8_FP16 feature, since the
4
In Armv8.6, the architecture standardized this frequency to 1GHz.
5
float-to-float conversion code doesn't use it yet. The effect
5
6
would be that we failed to set the Underflow IEEE exception flag
6
Because there is no ID register feature field that indicates whether
7
in all the cases where we should.
7
a CPU is v8.6 or that it ought to have this counter frequency, we
8
8
implement this by changing our default CNTFRQ value for all CPUs,
9
Add the missing initialization.
9
with exceptions for backwards compatibility:
10
10
11
Fixes: d81ce0ef2c4f105
11
* CPU types which we already implement will retain the old
12
Cc: qemu-stable@nongnu.org
12
default value. None of these are v8.6 CPUs, so this is
13
architecturally OK.
14
* CPUs used in versioned machine types with a version of 9.0
15
or earlier will retain the old default value.
16
17
The upshot is that the only CPU type that changes is 'max'; but any
18
new type we add in future (whether v8.6 or not) will also get the new
19
1GHz default.
20
21
It remains the case that the machine model can override the default
22
value via the 'cntfrq' QOM property (regardless of the CPU type).
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
26
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
28
---
18
target/arm/cpu.c | 2 ++
29
target/arm/cpu.h | 11 +++++++++++
19
1 file changed, 2 insertions(+)
30
target/arm/internals.h | 12 ++++++++++--
20
31
hw/core/machine.c | 4 +++-
32
target/arm/cpu.c | 23 +++++++++++++++++------
33
target/arm/cpu64.c | 2 ++
34
target/arm/tcg/cpu32.c | 4 ++++
35
target/arm/tcg/cpu64.c | 18 ++++++++++++++++++
36
7 files changed, 65 insertions(+), 9 deletions(-)
37
38
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
39
index XXXXXXX..XXXXXXX 100644
40
--- a/target/arm/cpu.h
41
+++ b/target/arm/cpu.h
42
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
43
*/
44
bool host_cpu_probe_failed;
45
46
+ /* QOM property to indicate we should use the back-compat CNTFRQ default */
47
+ bool backcompat_cntfrq;
48
+
49
/* Specify the number of cores in this CPU cluster. Used for the L2CTLR
50
* register.
51
*/
52
@@ -XXX,XX +XXX,XX @@ enum arm_features {
53
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
54
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
55
ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
56
+ /*
57
+ * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
58
+ * if the board doesn't set a value, instead of 1GHz. It is for backwards
59
+ * compatibility and used only with CPU definitions that were already
60
+ * in QEMU before we changed the default. It should not be set on any
61
+ * CPU types added in future.
62
+ */
63
+ ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
64
};
65
66
static inline int arm_feature(CPUARMState *env, int feature)
67
diff --git a/target/arm/internals.h b/target/arm/internals.h
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/internals.h
70
+++ b/target/arm/internals.h
71
@@ -XXX,XX +XXX,XX @@ static inline bool excp_is_internal(int excp)
72
73
/*
74
* Default frequency for the generic timer, in Hz.
75
- * This is 62.5MHz, which gives a 16 ns tick period.
76
+ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
77
+ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
78
+ * which gives a 16ns tick period.
79
+ *
80
+ * We will use the back-compat value:
81
+ * - for QEMU CPU types added before we standardized on 1GHz
82
+ * - for versioned machine types with a version of 9.0 or earlier
83
+ * In any case, the machine model may override via the cntfrq property.
84
*/
85
-#define GTIMER_DEFAULT_HZ 62500000
86
+#define GTIMER_DEFAULT_HZ 1000000000
87
+#define GTIMER_BACKCOMPAT_HZ 62500000
88
89
/* Bit definitions for the v7M CONTROL register */
90
FIELD(V7M_CONTROL, NPRIV, 0, 1)
91
diff --git a/hw/core/machine.c b/hw/core/machine.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/core/machine.c
94
+++ b/hw/core/machine.c
95
@@ -XXX,XX +XXX,XX @@
96
#include "hw/virtio/virtio-iommu.h"
97
#include "audio/audio.h"
98
99
-GlobalProperty hw_compat_9_0[] = {};
100
+GlobalProperty hw_compat_9_0[] = {
101
+ {"arm-cpu", "backcompat-cntfrq", "true" },
102
+};
103
const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0);
104
105
GlobalProperty hw_compat_8_2[] = {
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
106
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
22
index XXXXXXX..XXXXXXX 100644
107
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
108
--- a/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
109
+++ b/target/arm/cpu.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
110
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
26
&env->vfp.fp_status);
111
27
set_float_detect_tininess(float_tininess_before_rounding,
112
if (!cpu->gt_cntfrq_hz) {
28
&env->vfp.standard_fp_status);
113
/*
29
+ set_float_detect_tininess(float_tininess_before_rounding,
114
- * 0 means "the board didn't set a value, use the default".
30
+ &env->vfp.fp_status_f16);
115
- * The default value of the generic timer frequency (as seen in
116
- * CNTFRQ_EL0) is 62.5MHz, which corresponds to a period of 16ns.
117
- * This is what you get (a) for a CONFIG_USER_ONLY CPU (b) if the
118
- * board doesn't set it.
119
+ * 0 means "the board didn't set a value, use the default". (We also
120
+ * get here for the CONFIG_USER_ONLY case.)
121
+ * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
122
+ * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
123
+ * which gives a 16ns tick period.
124
+ *
125
+ * We will use the back-compat value:
126
+ * - for QEMU CPU types added before we standardized on 1GHz
127
+ * - for versioned machine types with a version of 9.0 or earlier
128
*/
129
- cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
130
+ if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
131
+ cpu->backcompat_cntfrq) {
132
+ cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
133
+ } else {
134
+ cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
135
+ }
136
}
137
31
#ifndef CONFIG_USER_ONLY
138
#ifndef CONFIG_USER_ONLY
32
if (kvm_enabled()) {
139
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_properties[] = {
33
kvm_arm_reset_vcpu(cpu);
140
mp_affinity, ARM64_AFFINITY_INVALID),
141
DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
142
DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
143
+ /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
144
+ DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
145
DEFINE_PROP_END_OF_LIST()
146
};
147
148
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/cpu64.c
151
+++ b/target/arm/cpu64.c
152
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
153
set_feature(&cpu->env, ARM_FEATURE_V8);
154
set_feature(&cpu->env, ARM_FEATURE_NEON);
155
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
156
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
157
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
158
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
159
set_feature(&cpu->env, ARM_FEATURE_EL2);
160
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
161
set_feature(&cpu->env, ARM_FEATURE_V8);
162
set_feature(&cpu->env, ARM_FEATURE_NEON);
163
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
164
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
165
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
166
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
167
set_feature(&cpu->env, ARM_FEATURE_EL2);
168
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
169
index XXXXXXX..XXXXXXX 100644
170
--- a/target/arm/tcg/cpu32.c
171
+++ b/target/arm/tcg/cpu32.c
172
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
173
set_feature(&cpu->env, ARM_FEATURE_NEON);
174
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
175
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
176
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
177
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
178
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
179
set_feature(&cpu->env, ARM_FEATURE_EL2);
180
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
181
set_feature(&cpu->env, ARM_FEATURE_NEON);
182
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
183
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
184
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
185
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
186
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
187
set_feature(&cpu->env, ARM_FEATURE_EL2);
188
@@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj)
189
set_feature(&cpu->env, ARM_FEATURE_PMSA);
190
set_feature(&cpu->env, ARM_FEATURE_NEON);
191
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
192
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
193
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
194
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
195
cpu->midr = 0x411fd133; /* r1p3 */
196
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
197
set_feature(&cpu->env, ARM_FEATURE_V8);
198
set_feature(&cpu->env, ARM_FEATURE_NEON);
199
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
200
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
201
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
202
set_feature(&cpu->env, ARM_FEATURE_EL2);
203
set_feature(&cpu->env, ARM_FEATURE_EL3);
204
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
205
index XXXXXXX..XXXXXXX 100644
206
--- a/target/arm/tcg/cpu64.c
207
+++ b/target/arm/tcg/cpu64.c
208
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
209
set_feature(&cpu->env, ARM_FEATURE_V8);
210
set_feature(&cpu->env, ARM_FEATURE_NEON);
211
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
212
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
213
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
214
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
215
set_feature(&cpu->env, ARM_FEATURE_EL2);
216
@@ -XXX,XX +XXX,XX @@ static void aarch64_a55_initfn(Object *obj)
217
set_feature(&cpu->env, ARM_FEATURE_V8);
218
set_feature(&cpu->env, ARM_FEATURE_NEON);
219
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
220
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
221
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
222
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
223
set_feature(&cpu->env, ARM_FEATURE_EL2);
224
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
225
set_feature(&cpu->env, ARM_FEATURE_V8);
226
set_feature(&cpu->env, ARM_FEATURE_NEON);
227
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
228
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
229
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
230
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
231
set_feature(&cpu->env, ARM_FEATURE_EL2);
232
@@ -XXX,XX +XXX,XX @@ static void aarch64_a76_initfn(Object *obj)
233
set_feature(&cpu->env, ARM_FEATURE_V8);
234
set_feature(&cpu->env, ARM_FEATURE_NEON);
235
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
236
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
237
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
238
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
239
set_feature(&cpu->env, ARM_FEATURE_EL2);
240
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
241
set_feature(&cpu->env, ARM_FEATURE_V8);
242
set_feature(&cpu->env, ARM_FEATURE_NEON);
243
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
244
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
245
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
246
set_feature(&cpu->env, ARM_FEATURE_EL2);
247
set_feature(&cpu->env, ARM_FEATURE_EL3);
248
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n1_initfn(Object *obj)
249
set_feature(&cpu->env, ARM_FEATURE_V8);
250
set_feature(&cpu->env, ARM_FEATURE_NEON);
251
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
252
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
253
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
254
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
255
set_feature(&cpu->env, ARM_FEATURE_EL2);
256
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
257
set_feature(&cpu->env, ARM_FEATURE_V8);
258
set_feature(&cpu->env, ARM_FEATURE_NEON);
259
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
260
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
261
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
262
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
263
set_feature(&cpu->env, ARM_FEATURE_EL2);
264
@@ -XXX,XX +XXX,XX @@ static void aarch64_a710_initfn(Object *obj)
265
set_feature(&cpu->env, ARM_FEATURE_V8);
266
set_feature(&cpu->env, ARM_FEATURE_NEON);
267
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
268
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
269
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
270
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
271
set_feature(&cpu->env, ARM_FEATURE_EL2);
272
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_n2_initfn(Object *obj)
273
set_feature(&cpu->env, ARM_FEATURE_V8);
274
set_feature(&cpu->env, ARM_FEATURE_NEON);
275
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
+ set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
277
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
278
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
279
set_feature(&cpu->env, ARM_FEATURE_EL2);
280
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
281
uint64_t t;
282
uint32_t u;
283
284
+ /*
285
+ * Unset ARM_FEATURE_BACKCOMPAT_CNTFRQ, which we would otherwise default
286
+ * to because we started with aarch64_a57_initfn(). A 'max' CPU might
287
+ * be a v8.6-or-later one, in which case the cntfrq must be 1GHz; and
288
+ * because it is our "may change" CPU type we are OK with it not being
289
+ * backwards-compatible with how it worked in old QEMU.
290
+ */
291
+ unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
292
+
293
/*
294
* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
295
* one and try to apply errata workarounds or use impdef features we
34
--
296
--
35
2.17.0
297
2.34.1
36
298
37
299
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
[PULL 14/21] hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Alexandra Diupina <adiupina@astralinux.ru>
2
2
3
Adding the fp16 moves to/from general registers.
3
The DMA descriptor structures for this device have
4
a set of "address extension" fields which extend the 32
5
bit source addresses with an extra 16 bits to give a
6
48 bit address:
7
https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field
8
9
However, we misimplemented this address extension in several ways:
10
* we only extracted 12 bits of the extension fields, not 16
11
* we didn't shift the extension field up far enough
12
* we accidentally did the shift as 32-bit arithmetic, which
13
meant that we would have an overflow instead of setting
14
bits [47:32] of the resulting 64-bit address
15
16
Add a type cast and use extract64() instead of extract32()
17
to avoid integer overflow on addition. Fix bit fields
18
extraction according to documentation.
19
20
Found by Linux Verification Center (linuxtesting.org) with SVACE.
4
21
5
Cc: qemu-stable@nongnu.org
22
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
Fixes: d3c6369a96 ("introduce xlnx-dpdma")
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
24
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
25
Message-id: 20240428181131.23801-1-adiupina@astralinux.ru
26
[PMM: adjusted commit message]
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
29
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
30
hw/dma/xlnx_dpdma.c | 20 ++++++++++----------
13
1 file changed, 21 insertions(+)
31
1 file changed, 10 insertions(+), 10 deletions(-)
14
32
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
33
diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c
16
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
35
--- a/hw/dma/xlnx_dpdma.c
18
+++ b/target/arm/translate-a64.c
36
+++ b/hw/dma/xlnx_dpdma.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
37
@@ -XXX,XX +XXX,XX @@ static uint64_t xlnx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
38
21
clear_vec_high(s, true, rd);
39
switch (frag) {
22
break;
40
case 0:
23
+ case 3:
41
- addr = desc->source_address
24
+ /* 16 bit */
42
- + (extract32(desc->address_extension, 16, 12) << 20);
25
+ tmp = tcg_temp_new_i64();
43
+ addr = (uint64_t)desc->source_address
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
44
+ + (extract64(desc->address_extension, 16, 16) << 32);
27
+ write_fp_dreg(s, rd, tmp);
45
break;
28
+ tcg_temp_free_i64(tmp);
46
case 1:
29
+ break;
47
- addr = desc->source_address2
30
+ default:
48
- + (extract32(desc->address_extension_23, 0, 12) << 8);
31
+ g_assert_not_reached();
49
+ addr = (uint64_t)desc->source_address2
32
}
50
+ + (extract64(desc->address_extension_23, 0, 16) << 32);
33
} else {
51
break;
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
52
case 2:
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
53
- addr = desc->source_address3
36
/* 64 bits from top half */
54
- + (extract32(desc->address_extension_23, 16, 12) << 20);
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
55
+ addr = (uint64_t)desc->source_address3
38
break;
56
+ + (extract64(desc->address_extension_23, 16, 16) << 32);
39
+ case 3:
57
break;
40
+ /* 16 bit */
58
case 3:
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
59
- addr = desc->source_address4
42
+ break;
60
- + (extract32(desc->address_extension_45, 0, 12) << 8);
43
+ default:
61
+ addr = (uint64_t)desc->source_address4
44
+ g_assert_not_reached();
62
+ + (extract64(desc->address_extension_45, 0, 16) << 32);
45
}
63
break;
46
}
64
case 4:
47
}
65
- addr = desc->source_address5
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
66
- + (extract32(desc->address_extension_45, 16, 12) << 20);
49
case 0xa: /* 64 bit */
67
+ addr = (uint64_t)desc->source_address5
50
case 0xd: /* 64 bit to top half of quad */
68
+ + (extract64(desc->address_extension_45, 16, 16) << 32);
51
break;
69
break;
52
+ case 0x6: /* 16-bit float, 32-bit int */
70
default:
53
+ case 0xe: /* 16-bit float, 64-bit int */
71
addr = 0;
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
55
+ break;
56
+ }
57
+ /* fallthru */
58
default:
59
/* all other sf/type/rmode combinations are invalid */
60
unallocated_encoding(s);
61
--
72
--
62
2.17.0
73
2.34.1
63
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
[PULL 15/21] hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
These were missed out from the rest of the half-precision work.
3
"make check-qtest-aarch64" recently started failing on FreeBSD builds,
4
and valgrind on Linux also detected that there is something fishy with
5
the new stm32l4x5-usart: The code forgot to set the correct class_size
6
here, so the various class_init functions in this file wrote beyond
7
the allocated buffer when setting the subc->type field.
4
8
5
Cc: qemu-stable@nongnu.org
9
Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton")
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20240429075908.36302-1-thuth@redhat.com
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
14
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
15
hw/char/stm32l4x5_usart.c | 1 +
16
1 file changed, 25 insertions(+), 6 deletions(-)
16
1 file changed, 1 insertion(+)
17
17
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
20
--- a/hw/char/stm32l4x5_usart.c
21
+++ b/target/arm/translate-a64.c
21
+++ b/hw/char/stm32l4x5_usart.c
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
22
@@ -XXX,XX +XXX,XX @@ static const TypeInfo stm32l4x5_usart_types[] = {
23
unsigned int mos, type, rm, cond, rn, rd;
23
.parent = TYPE_SYS_BUS_DEVICE,
24
TCGv_i64 t_true, t_false, t_zero;
24
.instance_size = sizeof(Stm32l4x5UsartBaseState),
25
DisasCompare64 c;
25
.instance_init = stm32l4x5_usart_base_init,
26
+ TCGMemOp sz;
26
+ .class_size = sizeof(Stm32l4x5UsartBaseClass),
27
27
.class_init = stm32l4x5_usart_base_class_init,
28
mos = extract32(insn, 29, 3);
28
.abstract = true,
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
29
}, {
30
+ type = extract32(insn, 22, 2);
31
rm = extract32(insn, 16, 5);
32
cond = extract32(insn, 12, 4);
33
rn = extract32(insn, 5, 5);
34
rd = extract32(insn, 0, 5);
35
36
- if (mos || type > 1) {
37
+ if (mos) {
38
+ unallocated_encoding(s);
39
+ return;
40
+ }
41
+
42
+ switch (type) {
43
+ case 0:
44
+ sz = MO_32;
45
+ break;
46
+ case 1:
47
+ sz = MO_64;
48
+ break;
49
+ case 3:
50
+ sz = MO_16;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
52
+ break;
53
+ }
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
60
return;
61
}
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
83
--
30
--
84
2.17.0
31
2.34.1
85
32
86
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
[PULL 16/21] hw/arm/npcm7xx: Store derivative OTP fuse key in little endian
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
2
3
We are meant to explicitly pass fpst, not cpu_env.
3
Use little endian for derivative OTP fuse key.
4
4
5
Cc: qemu-stable@nongnu.org
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model")
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20240422125813.1403-1-philmd@linaro.org
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
target/arm/translate-a64.c | 3 ++-
13
hw/arm/npcm7xx.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
15
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
18
--- a/hw/arm/npcm7xx.c
19
+++ b/target/arm/translate-a64.c
19
+++ b/hw/arm/npcm7xx.c
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
20
@@ -XXX,XX +XXX,XX @@
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
21
#include "hw/qdev-clock.h"
22
break;
22
#include "hw/qdev-properties.h"
23
case 0x3: /* FSQRT */
23
#include "qapi/error.h"
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
24
+#include "qemu/bswap.h"
25
+ fpst = get_fpstatus_ptr(true);
25
#include "qemu/units.h"
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
26
#include "sysemu/sysemu.h"
27
break;
27
#include "target/arm/cpu-qom.h"
28
case 0x8: /* FRINTN */
28
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
29
case 0x9: /* FRINTP */
29
* The initial mask of disabled modules indicates the chip derivative (e.g.
30
* NPCM750 or NPCM730).
31
*/
32
- value = tswap32(nc->disabled_modules);
33
+ value = cpu_to_le32(nc->disabled_modules);
34
npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
35
sizeof(value));
36
}
30
--
37
--
31
2.17.0
38
2.34.1
32
39
33
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
[PULL 17/21] hw/display : Add device DM163
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Cc: qemu-stable@nongnu.org
3
This device implements the IM120417002 colors shield v1.1 for Arduino
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
(which relies on the DM163 8x3-channel led driving logic) and features
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
a simple display of an 8x8 RGB matrix. The columns of the matrix are
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
driven by the DM163 and the rows are driven externally.
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
7
8
Acked-by: Alistair Francis <alistair.francis@wdc.com>
9
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
10
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
12
Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr
13
[PMM: updated to new reset hold method prototype]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
15
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
16
docs/system/arm/b-l475e-iot01a.rst | 3 +-
11
1 file changed, 15 insertions(+), 2 deletions(-)
17
include/hw/display/dm163.h | 59 +++++
18
hw/display/dm163.c | 349 +++++++++++++++++++++++++++++
19
hw/display/Kconfig | 3 +
20
hw/display/meson.build | 1 +
21
hw/display/trace-events | 14 ++
22
6 files changed, 428 insertions(+), 1 deletion(-)
23
create mode 100644 include/hw/display/dm163.h
24
create mode 100644 hw/display/dm163.c
12
25
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-iot01a.rst
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
28
--- a/docs/system/arm/b-l475e-iot01a.rst
16
+++ b/target/arm/translate-a64.c
29
+++ b/docs/system/arm/b-l475e-iot01a.rst
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
30
@@ -XXX,XX +XXX,XX @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety of sensors.
18
bool sf = extract32(insn, 31, 1);
31
Supported devices
19
bool itof;
32
"""""""""""""""""
20
33
21
- if (sbit || (type > 1)
34
-Currently B-L475E-IOT01A machine's only supports the following devices:
22
- || (!sf && scale < 32)) {
35
+Currently B-L475E-IOT01A machines support the following devices:
23
+ if (sbit || (!sf && scale < 32)) {
36
24
+ unallocated_encoding(s);
37
- Cortex-M4F based STM32L4x5 SoC
25
+ return;
38
- STM32L4x5 EXTI (Extended interrupts and events controller)
26
+ }
39
@@ -XXX,XX +XXX,XX @@ Currently B-L475E-IOT01A machine's only supports the following devices:
27
+
40
- STM32L4x5 RCC (Reset and clock control)
28
+ switch (type) {
41
- STM32L4x5 GPIOs (General-purpose I/Os)
29
+ case 0: /* float32 */
42
- STM32L4x5 USARTs, UARTs and LPUART (Serial ports)
30
+ case 1: /* float64 */
43
+- optional 8x8 led display (based on DM163 driver)
31
+ break;
44
32
+ case 3: /* float16 */
45
Missing devices
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
46
"""""""""""""""
34
+ break;
47
diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h
48
new file mode 100644
49
index XXXXXXX..XXXXXXX
50
--- /dev/null
51
+++ b/include/hw/display/dm163.h
52
@@ -XXX,XX +XXX,XX @@
53
+/*
54
+ * QEMU DM163 8x3-channel constant current led driver
55
+ * driving columns of associated 8x8 RGB matrix.
56
+ *
57
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
58
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
59
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
60
+ *
61
+ * SPDX-License-Identifier: GPL-2.0-or-later
62
+ */
63
+
64
+#ifndef HW_DISPLAY_DM163_H
65
+#define HW_DISPLAY_DM163_H
66
+
67
+#include "qom/object.h"
68
+#include "hw/qdev-core.h"
69
+
70
+#define TYPE_DM163 "dm163"
71
+OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163);
72
+
73
+#define RGB_MATRIX_NUM_ROWS 8
74
+#define RGB_MATRIX_NUM_COLS 8
75
+#define DM163_NUM_LEDS (RGB_MATRIX_NUM_COLS * 3)
76
+/* The last row is filled with 0 (turned off row) */
77
+#define COLOR_BUFFER_SIZE (RGB_MATRIX_NUM_ROWS + 1)
78
+
79
+typedef struct DM163State {
80
+ DeviceState parent_obj;
81
+
82
+ /* DM163 driver */
83
+ uint64_t bank0_shift_register[3];
84
+ uint64_t bank1_shift_register[3];
85
+ uint16_t latched_outputs[DM163_NUM_LEDS];
86
+ uint16_t outputs[DM163_NUM_LEDS];
87
+ qemu_irq sout;
88
+
89
+ uint8_t sin;
90
+ uint8_t dck;
91
+ uint8_t rst_b;
92
+ uint8_t lat_b;
93
+ uint8_t selbk;
94
+ uint8_t en_b;
95
+
96
+ /* IM120417002 colors shield */
97
+ uint8_t activated_rows;
98
+
99
+ /* 8x8 RGB matrix */
100
+ QemuConsole *console;
101
+ uint8_t redraw;
102
+ /* Rows currently being displayed on the matrix. */
103
+ /* The last row is filled with 0 (turned off row) */
104
+ uint32_t buffer[COLOR_BUFFER_SIZE][RGB_MATRIX_NUM_COLS];
105
+ uint8_t last_buffer_idx;
106
+ uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS];
107
+ /* Used to simulate retinal persistence of rows */
108
+ uint8_t row_persistence_delay[RGB_MATRIX_NUM_ROWS];
109
+} DM163State;
110
+
111
+#endif /* HW_DISPLAY_DM163_H */
112
diff --git a/hw/display/dm163.c b/hw/display/dm163.c
113
new file mode 100644
114
index XXXXXXX..XXXXXXX
115
--- /dev/null
116
+++ b/hw/display/dm163.c
117
@@ -XXX,XX +XXX,XX @@
118
+/*
119
+ * QEMU DM163 8x3-channel constant current led driver
120
+ * driving columns of associated 8x8 RGB matrix.
121
+ *
122
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
123
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
124
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
125
+ *
126
+ * SPDX-License-Identifier: GPL-2.0-or-later
127
+ */
128
+
129
+/*
130
+ * The reference used for the DM163 is the following :
131
+ * http://www.siti.com.tw/product/spec/LED/DM163.pdf
132
+ */
133
+
134
+#include "qemu/osdep.h"
135
+#include "qapi/error.h"
136
+#include "migration/vmstate.h"
137
+#include "hw/irq.h"
138
+#include "hw/qdev-properties.h"
139
+#include "hw/display/dm163.h"
140
+#include "ui/console.h"
141
+#include "trace.h"
142
+
143
+#define LED_SQUARE_SIZE 100
144
+/* Number of frames a row stays visible after being turned off. */
145
+#define ROW_PERSISTENCE 3
146
+#define TURNED_OFF_ROW (COLOR_BUFFER_SIZE - 1)
147
+
148
+static const VMStateDescription vmstate_dm163 = {
149
+ .name = TYPE_DM163,
150
+ .version_id = 1,
151
+ .minimum_version_id = 1,
152
+ .fields = (const VMStateField[]) {
153
+ VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3),
154
+ VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3),
155
+ VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS),
156
+ VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS),
157
+ VMSTATE_UINT8(dck, DM163State),
158
+ VMSTATE_UINT8(en_b, DM163State),
159
+ VMSTATE_UINT8(lat_b, DM163State),
160
+ VMSTATE_UINT8(rst_b, DM163State),
161
+ VMSTATE_UINT8(selbk, DM163State),
162
+ VMSTATE_UINT8(sin, DM163State),
163
+ VMSTATE_UINT8(activated_rows, DM163State),
164
+ VMSTATE_UINT32_2DARRAY(buffer, DM163State, COLOR_BUFFER_SIZE,
165
+ RGB_MATRIX_NUM_COLS),
166
+ VMSTATE_UINT8(last_buffer_idx, DM163State),
167
+ VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_ROWS),
168
+ VMSTATE_UINT8_ARRAY(row_persistence_delay, DM163State,
169
+ RGB_MATRIX_NUM_ROWS),
170
+ VMSTATE_END_OF_LIST()
171
+ }
172
+};
173
+
174
+static void dm163_reset_hold(Object *obj, ResetType type)
175
+{
176
+ DM163State *s = DM163(obj);
177
+
178
+ s->sin = 0;
179
+ s->dck = 0;
180
+ s->rst_b = 0;
181
+ /* Ensuring the first falling edge of lat_b isn't missed */
182
+ s->lat_b = 1;
183
+ s->selbk = 0;
184
+ s->en_b = 0;
185
+ /* Reset stops the PWM, not the shift and latched registers. */
186
+ memset(s->outputs, 0, sizeof(s->outputs));
187
+
188
+ s->activated_rows = 0;
189
+ s->redraw = 0;
190
+ trace_dm163_redraw(s->redraw);
191
+ for (unsigned i = 0; i < COLOR_BUFFER_SIZE; i++) {
192
+ memset(s->buffer[i], 0, sizeof(s->buffer[0]));
193
+ }
194
+ s->last_buffer_idx = 0;
195
+ memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_row));
196
+ memset(s->row_persistence_delay, 0, sizeof(s->row_persistence_delay));
197
+}
198
+
199
+static void dm163_dck_gpio_handler(void *opaque, int line, int new_state)
200
+{
201
+ DM163State *s = opaque;
202
+
203
+ if (new_state && !s->dck) {
204
+ /*
205
+ * On raising dck, sample selbk to get the bank to use, and
206
+ * sample sin for the bit to enter into the bank shift buffer.
207
+ */
208
+ uint64_t *sb =
209
+ s->selbk ? s->bank1_shift_register : s->bank0_shift_register;
210
+ /* Output the outgoing bit on sout */
211
+ const bool sout = (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) :
212
+ sb[2] & MAKE_64BIT_MASK(15, 1)) != 0;
213
+ qemu_set_irq(s->sout, sout);
214
+ /* Enter sin into the shift buffer */
215
+ sb[2] = (sb[2] << 1) | ((sb[1] >> 63) & 1);
216
+ sb[1] = (sb[1] << 1) | ((sb[0] >> 63) & 1);
217
+ sb[0] = (sb[0] << 1) | s->sin;
218
+ }
219
+
220
+ s->dck = new_state;
221
+ trace_dm163_dck(new_state);
222
+}
223
+
224
+static void dm163_propagate_outputs(DM163State *s)
225
+{
226
+ s->last_buffer_idx = (s->last_buffer_idx + 1) % RGB_MATRIX_NUM_ROWS;
227
+ /* Values are output when reset is high and enable is low. */
228
+ if (s->rst_b && !s->en_b) {
229
+ memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs));
230
+ } else {
231
+ memset(s->outputs, 0, sizeof(s->outputs));
232
+ }
233
+ for (unsigned x = 0; x < RGB_MATRIX_NUM_COLS; x++) {
234
+ /* Grouping the 3 RGB channels in a pixel value */
235
+ const uint16_t b = extract16(s->outputs[3 * x + 0], 6, 8);
236
+ const uint16_t g = extract16(s->outputs[3 * x + 1], 6, 8);
237
+ const uint16_t r = extract16(s->outputs[3 * x + 2], 6, 8);
238
+ uint32_t rgba = 0;
239
+
240
+ trace_dm163_channels(3 * x + 2, r);
241
+ trace_dm163_channels(3 * x + 1, g);
242
+ trace_dm163_channels(3 * x + 0, b);
243
+
244
+ rgba = deposit32(rgba, 0, 8, r);
245
+ rgba = deposit32(rgba, 8, 8, g);
246
+ rgba = deposit32(rgba, 16, 8, b);
247
+
248
+ /* Led values are sent from the last one to the first one */
249
+ s->buffer[s->last_buffer_idx][RGB_MATRIX_NUM_COLS - x - 1] = rgba;
250
+ }
251
+ for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
252
+ if (s->activated_rows & (1 << row)) {
253
+ s->buffer_idx_of_row[row] = s->last_buffer_idx;
254
+ s->redraw |= (1 << row);
255
+ trace_dm163_redraw(s->redraw);
35
+ }
256
+ }
36
+ /* fallthru */
257
+ }
37
+ default:
258
+}
38
unallocated_encoding(s);
259
+
39
return;
260
+static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state)
40
}
261
+{
262
+ DM163State *s = opaque;
263
+
264
+ s->en_b = new_state;
265
+ dm163_propagate_outputs(s);
266
+ trace_dm163_en_b(new_state);
267
+}
268
+
269
+static uint8_t dm163_bank0(const DM163State *s, uint8_t led)
270
+{
271
+ /*
272
+ * Bank 0 uses 6 bits per led, so a value may be stored accross
273
+ * two uint64_t entries.
274
+ */
275
+ const uint8_t low_bit = 6 * led;
276
+ const uint8_t low_word = low_bit / 64;
277
+ const uint8_t high_word = (low_bit + 5) / 64;
278
+ const uint8_t low_shift = low_bit % 64;
279
+
280
+ if (low_word == high_word) {
281
+ /* Simple case: the value belongs to one entry. */
282
+ return extract64(s->bank0_shift_register[low_word], low_shift, 6);
283
+ }
284
+
285
+ const uint8_t nb_bits_in_low_word = 64 - low_shift;
286
+ const uint8_t nb_bits_in_high_word = 6 - nb_bits_in_low_word;
287
+
288
+ const uint64_t bits_in_low_word = \
289
+ extract64(s->bank0_shift_register[low_word], low_shift,
290
+ nb_bits_in_low_word);
291
+ const uint64_t bits_in_high_word = \
292
+ extract64(s->bank0_shift_register[high_word], 0,
293
+ nb_bits_in_high_word);
294
+ uint8_t val = 0;
295
+
296
+ val = deposit32(val, 0, nb_bits_in_low_word, bits_in_low_word);
297
+ val = deposit32(val, nb_bits_in_low_word, nb_bits_in_high_word,
298
+ bits_in_high_word);
299
+
300
+ return val;
301
+}
302
+
303
+static uint8_t dm163_bank1(const DM163State *s, uint8_t led)
304
+{
305
+ const uint64_t entry = s->bank1_shift_register[led / RGB_MATRIX_NUM_COLS];
306
+ return extract64(entry, 8 * (led % RGB_MATRIX_NUM_COLS), 8);
307
+}
308
+
309
+static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state)
310
+{
311
+ DM163State *s = opaque;
312
+
313
+ if (s->lat_b && !new_state) {
314
+ for (int led = 0; led < DM163_NUM_LEDS; led++) {
315
+ s->latched_outputs[led] = dm163_bank0(s, led) * dm163_bank1(s, led);
316
+ }
317
+ dm163_propagate_outputs(s);
318
+ }
319
+
320
+ s->lat_b = new_state;
321
+ trace_dm163_lat_b(new_state);
322
+}
323
+
324
+static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state)
325
+{
326
+ DM163State *s = opaque;
327
+
328
+ s->rst_b = new_state;
329
+ dm163_propagate_outputs(s);
330
+ trace_dm163_rst_b(new_state);
331
+}
332
+
333
+static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state)
334
+{
335
+ DM163State *s = opaque;
336
+
337
+ s->selbk = new_state;
338
+ trace_dm163_selbk(new_state);
339
+}
340
+
341
+static void dm163_sin_gpio_handler(void *opaque, int line, int new_state)
342
+{
343
+ DM163State *s = opaque;
344
+
345
+ s->sin = new_state;
346
+ trace_dm163_sin(new_state);
347
+}
348
+
349
+static void dm163_rows_gpio_handler(void *opaque, int line, int new_state)
350
+{
351
+ DM163State *s = opaque;
352
+
353
+ if (new_state) {
354
+ s->activated_rows |= (1 << line);
355
+ s->buffer_idx_of_row[line] = s->last_buffer_idx;
356
+ s->redraw |= (1 << line);
357
+ trace_dm163_redraw(s->redraw);
358
+ } else {
359
+ s->activated_rows &= ~(1 << line);
360
+ s->row_persistence_delay[line] = ROW_PERSISTENCE;
361
+ }
362
+ trace_dm163_activated_rows(s->activated_rows);
363
+}
364
+
365
+static void dm163_invalidate_display(void *opaque)
366
+{
367
+ DM163State *s = (DM163State *)opaque;
368
+ s->redraw = 0xFF;
369
+ trace_dm163_redraw(s->redraw);
370
+}
371
+
372
+static void update_row_persistence_delay(DM163State *s, unsigned row)
373
+{
374
+ if (s->row_persistence_delay[row]) {
375
+ s->row_persistence_delay[row]--;
376
+ } else {
377
+ /*
378
+ * If the ROW_PERSISTENCE delay is up,
379
+ * the row is turned off.
380
+ */
381
+ s->buffer_idx_of_row[row] = TURNED_OFF_ROW;
382
+ s->redraw |= (1 << row);
383
+ trace_dm163_redraw(s->redraw);
384
+ }
385
+}
386
+
387
+static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest,
388
+ unsigned row)
389
+{
390
+ for (unsigned _ = 0; _ < LED_SQUARE_SIZE; _++) {
391
+ for (int x = 0; x < RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE; x++) {
392
+ /* UI layer guarantees that there's 32 bits per pixel (Mar 2024) */
393
+ *dest++ = s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUARE_SIZE];
394
+ }
395
+ }
396
+
397
+ dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row,
398
+ RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE);
399
+ s->redraw &= ~(1 << row);
400
+ trace_dm163_redraw(s->redraw);
401
+
402
+ return dest;
403
+}
404
+
405
+static void dm163_update_display(void *opaque)
406
+{
407
+ DM163State *s = (DM163State *)opaque;
408
+ DisplaySurface *surface = qemu_console_surface(s->console);
409
+ uint32_t *dest;
410
+
411
+ dest = surface_data(surface);
412
+ for (unsigned row = 0; row < RGB_MATRIX_NUM_ROWS; row++) {
413
+ update_row_persistence_delay(s, row);
414
+ if (!extract8(s->redraw, row, 1)) {
415
+ dest += LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_COLS;
416
+ continue;
417
+ }
418
+ dest = update_display_of_row(s, dest, row);
419
+ }
420
+}
421
+
422
+static const GraphicHwOps dm163_ops = {
423
+ .invalidate = dm163_invalidate_display,
424
+ .gfx_update = dm163_update_display,
425
+};
426
+
427
+static void dm163_realize(DeviceState *dev, Error **errp)
428
+{
429
+ DM163State *s = DM163(dev);
430
+
431
+ qdev_init_gpio_in(dev, dm163_rows_gpio_handler, RGB_MATRIX_NUM_ROWS);
432
+ qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1);
433
+ qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1);
434
+ qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1);
435
+ qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1);
436
+ qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1);
437
+ qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1);
438
+ qdev_init_gpio_out_named(dev, &s->sout, "sout", 1);
439
+
440
+ s->console = graphic_console_init(dev, 0, &dm163_ops, s);
441
+ qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE,
442
+ RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE);
443
+}
444
+
445
+static void dm163_class_init(ObjectClass *klass, void *data)
446
+{
447
+ DeviceClass *dc = DEVICE_CLASS(klass);
448
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
449
+
450
+ dc->desc = "DM163";
451
+ dc->vmsd = &vmstate_dm163;
452
+ dc->realize = dm163_realize;
453
+ rc->phases.hold = dm163_reset_hold;
454
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
455
+}
456
+
457
+static const TypeInfo dm163_types[] = {
458
+ {
459
+ .name = TYPE_DM163,
460
+ .parent = TYPE_DEVICE,
461
+ .instance_size = sizeof(DM163State),
462
+ .class_init = dm163_class_init
463
+ }
464
+};
465
+
466
+DEFINE_TYPES(dm163_types)
467
diff --git a/hw/display/Kconfig b/hw/display/Kconfig
468
index XXXXXXX..XXXXXXX 100644
469
--- a/hw/display/Kconfig
470
+++ b/hw/display/Kconfig
471
@@ -XXX,XX +XXX,XX @@ config XLNX_DISPLAYPORT
472
bool
473
# defaults to "N", enabled by specific boards
474
depends on PIXMAN
475
+
476
+config DM163
477
+ bool
478
diff --git a/hw/display/meson.build b/hw/display/meson.build
479
index XXXXXXX..XXXXXXX 100644
480
--- a/hw/display/meson.build
481
+++ b/hw/display/meson.build
482
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-fb.c'))
483
484
system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
485
system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c'))
486
+system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c'))
487
488
if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
489
config_all_devices.has_key('CONFIG_VGA_PCI') or
490
diff --git a/hw/display/trace-events b/hw/display/trace-events
491
index XXXXXXX..XXXXXXX 100644
492
--- a/hw/display/trace-events
493
+++ b/hw/display/trace-events
494
@@ -XXX,XX +XXX,XX @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%"PRI
495
macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
496
macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
497
macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting mode to width %"PRId32 " height %"PRId32 " size %d"
498
+
499
+# dm163.c
500
+dm163_redraw(uint8_t redraw) "0x%02x"
501
+dm163_dck(unsigned new_state) "dck : %u"
502
+dm163_en_b(unsigned new_state) "en_b : %u"
503
+dm163_rst_b(unsigned new_state) "rst_b : %u"
504
+dm163_lat_b(unsigned new_state) "lat_b : %u"
505
+dm163_sin(unsigned new_state) "sin : %u"
506
+dm163_selbk(unsigned new_state) "selbk : %u"
507
+dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 ""
508
+dm163_bits_ppi(unsigned dest_width) "dest_width : %u"
509
+dm163_leds(int led, uint32_t value) "led %d: 0x%x"
510
+dm163_channels(int channel, uint8_t value) "channel %d: 0x%x"
511
+dm163_refresh_rate(uint32_t rr) "refresh rate %d"
41
--
512
--
42
2.17.0
513
2.34.1
43
514
44
515
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
[PULL 18/21] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
3
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC
4
to the optional DM163 display from the board code (GPIOs outputs need
5
to be connected to both SYSCFG inputs and DM163 inputs).
4
6
5
The block length is predefined to 512 bits
7
STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly.
6
8
7
and "4.10.2 SD Status":
9
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
8
10
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
9
The SD Status contains status bits that are related to the SD Memory Card
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
proprietary features and may be used for future application-specific usage.
12
Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
14
---
21
hw/sd/sd.c | 2 +-
15
hw/arm/stm32l4x5_soc.c | 6 ++++--
22
1 file changed, 1 insertion(+), 1 deletion(-)
16
tests/qtest/stm32l4x5_gpio-test.c | 13 ++++++++-----
17
tests/qtest/stm32l4x5_syscfg-test.c | 17 ++++++++++-------
18
3 files changed, 22 insertions(+), 14 deletions(-)
23
19
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
20
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
25
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
22
--- a/hw/arm/stm32l4x5_soc.c
27
+++ b/hw/sd/sd.c
23
+++ b/hw/arm/stm32l4x5_soc.c
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
24
@@ -XXX,XX +XXX,XX @@
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
25
/*
26
* STM32L4x5 SoC family
27
*
28
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
29
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
30
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
31
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
32
*
33
* SPDX-License-Identifier: GPL-2.0-or-later
34
*
35
@@ -XXX,XX +XXX,XX @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
36
}
30
}
37
}
31
memset(&sd->data[17], 0, 47);
38
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
39
+ qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL);
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
40
+
41
/* EXTI device */
42
busdev = SYS_BUS_DEVICE(&s->exti);
43
if (!sysbus_realize(busdev, errp)) {
44
diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/tests/qtest/stm32l4x5_gpio-test.c
47
+++ b/tests/qtest/stm32l4x5_gpio-test.c
48
@@ -XXX,XX +XXX,XX @@
49
#define OTYPER_PUSH_PULL 0
50
#define OTYPER_OPEN_DRAIN 1
51
52
+/* SoC forwards GPIOs to SysCfg */
53
+#define SYSCFG "/machine/soc"
54
+
55
const uint32_t moder_reset[NUM_GPIOS] = {
56
0xABFFFFFF,
57
0xFFFFFEBF,
58
@@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data)
59
uint32_t gpio = test_gpio_addr(data);
60
unsigned int gpio_id = get_gpio_id(gpio);
61
62
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
63
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
64
65
/* Set a bit in ODR and check nothing happens */
66
gpio_set_bit(gpio, ODR, pin, 1);
67
@@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data)
68
uint32_t gpio = test_gpio_addr(data);
69
unsigned int gpio_id = get_gpio_id(gpio);
70
71
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
72
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
73
74
/* Configure a line as input, raise it, and check that the pin is high */
75
gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
76
@@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data)
77
uint32_t gpio = test_gpio_addr(data);
78
unsigned int gpio_id = get_gpio_id(gpio);
79
80
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
81
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
82
83
/* Configure a line as input with pull-up, check the line is set high */
84
gpio_set_2bits(gpio, MODER, pin, MODER_INPUT);
85
@@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data)
86
uint32_t gpio = test_gpio_addr(data);
87
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
88
89
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
90
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
91
92
/* Setting a line high externally, configuring it in push-pull output */
93
/* And checking the pin was disconnected */
94
@@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data)
95
uint32_t gpio = test_gpio_addr(data);
96
uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio);
97
98
- qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg");
99
+ qtest_irq_intercept_in(global_qtest, SYSCFG);
100
101
/* Setting a line high externally, configuring it in open-drain output */
102
/* And checking the pin was disconnected */
103
diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_syscfg-test.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/tests/qtest/stm32l4x5_syscfg-test.c
106
+++ b/tests/qtest/stm32l4x5_syscfg-test.c
107
@@ -XXX,XX +XXX,XX @@
108
/*
109
* QTest testcase for STM32L4x5_SYSCFG
110
*
111
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
112
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
113
+ * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
114
+ * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
115
*
116
* This work is licensed under the terms of the GNU GPL, version 2 or later.
117
* See the COPYING file in the top-level directory.
118
@@ -XXX,XX +XXX,XX @@
119
#define SYSCFG_SWPR2 0x28
120
#define INVALID_ADDR 0x2C
121
122
+/* SoC forwards GPIOs to SysCfg */
123
+#define SYSCFG "/machine/soc"
124
+#define EXTI "/machine/soc/exti"
125
+
126
static void syscfg_writel(unsigned int offset, uint32_t value)
127
{
128
writel(SYSCFG_BASE_ADDR + offset, value);
129
@@ -XXX,XX +XXX,XX @@ static uint32_t syscfg_readl(unsigned int offset)
130
131
static void syscfg_set_irq(int num, int level)
132
{
133
- qtest_set_irq_in(global_qtest, "/machine/soc/syscfg",
134
- NULL, num, level);
135
+ qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level);
34
}
136
}
35
137
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
138
static void system_reset(void)
139
@@ -XXX,XX +XXX,XX @@ static void test_interrupt(void)
140
* Test that GPIO rising lines result in an irq
141
* with the right configuration
142
*/
143
- qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
144
+ qtest_irq_intercept_in(global_qtest, EXTI);
145
146
/* GPIOA is the default source for EXTI lines 0 to 15 */
147
148
@@ -XXX,XX +XXX,XX @@ static void test_irq_pin_multiplexer(void)
149
* Test that syscfg irq sets the right exti irq
150
*/
151
152
- qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
153
+ qtest_irq_intercept_in(global_qtest, EXTI);
154
155
syscfg_set_irq(0, 1);
156
157
@@ -XXX,XX +XXX,XX @@ static void test_irq_gpio_multiplexer(void)
158
* Test that an irq is generated only by the right GPIO
159
*/
160
161
- qtest_irq_intercept_in(global_qtest, "/machine/soc/exti");
162
+ qtest_irq_intercept_in(global_qtest, EXTI);
163
164
/* GPIOA is the default source for EXTI lines 0 to 15 */
165
37
--
166
--
38
2.17.0
167
2.34.1
39
168
40
169
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
[PULL 19/21] hw/arm : Create Bl475eMachineState
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
We missed all of the scalar fp16 binary operations.
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
Cc: qemu-stable@nongnu.org
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
8
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
9
hw/arm/b-l475e-iot01a.c | 46 ++++++++++++++++++++++++++++-------------
13
1 file changed, 65 insertions(+)
10
1 file changed, 32 insertions(+), 14 deletions(-)
14
11
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
14
--- a/hw/arm/b-l475e-iot01a.c
18
+++ b/target/arm/translate-a64.c
15
+++ b/hw/arm/b-l475e-iot01a.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
16
@@ -XXX,XX +XXX,XX @@
20
tcg_temp_free_i64(tcg_res);
17
* B-L475E-IOT01A Discovery Kit machine
18
* (B-L475E-IOT01A IoT Node)
19
*
20
- * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
21
- * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
22
+ * Copyright (c) 2023-2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
23
+ * Copyright (c) 2023-2024 Inès Varhol <ines.varhol@telecom-paris.fr>
24
*
25
* SPDX-License-Identifier: GPL-2.0-or-later
26
*
27
@@ -XXX,XX +XXX,XX @@
28
29
/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
30
31
-static void b_l475e_iot01a_init(MachineState *machine)
32
+#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
33
+OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
34
+
35
+typedef struct Bl475eMachineState {
36
+ MachineState parent_obj;
37
+
38
+ Stm32l4x5SocState soc;
39
+} Bl475eMachineState;
40
+
41
+static void bl475e_init(MachineState *machine)
42
{
43
+ Bl475eMachineState *s = B_L475E_IOT01A(machine);
44
const Stm32l4x5SocClass *sc;
45
- DeviceState *dev;
46
47
- dev = qdev_new(TYPE_STM32L4X5XG_SOC);
48
- object_property_add_child(OBJECT(machine), "soc", OBJECT(dev));
49
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
50
+ object_initialize_child(OBJECT(machine), "soc", &s->soc,
51
+ TYPE_STM32L4X5XG_SOC);
52
+ sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal);
53
54
- sc = STM32L4X5_SOC_GET_CLASS(dev);
55
- armv7m_load_kernel(ARM_CPU(first_cpu),
56
- machine->kernel_filename,
57
- 0, sc->flash_size);
58
+ sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
59
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
60
+ sc->flash_size);
21
}
61
}
22
62
23
+/* Floating-point data-processing (2 source) - half precision */
63
-static void b_l475e_iot01a_machine_init(MachineClass *mc)
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
64
+static void bl475e_machine_init(ObjectClass *oc, void *data)
25
+ int rd, int rn, int rm)
65
{
26
+{
66
+ MachineClass *mc = MACHINE_CLASS(oc);
27
+ TCGv_i32 tcg_op1;
67
static const char *machine_valid_cpu_types[] = {
28
+ TCGv_i32 tcg_op2;
68
ARM_CPU_TYPE_NAME("cortex-m4"),
29
+ TCGv_i32 tcg_res;
69
NULL
30
+ TCGv_ptr fpst;
70
};
71
mc->desc = "B-L475E-IOT01A Discovery Kit (Cortex-M4)";
72
- mc->init = b_l475e_iot01a_init;
73
+ mc->init = bl475e_init;
74
mc->valid_cpu_types = machine_valid_cpu_types;
75
76
/* SRAM pre-allocated as part of the SoC instantiation */
77
mc->default_ram_size = 0;
78
}
79
80
-DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init)
81
+static const TypeInfo bl475e_machine_type[] = {
82
+ {
83
+ .name = TYPE_B_L475E_IOT01A,
84
+ .parent = TYPE_MACHINE,
85
+ .instance_size = sizeof(Bl475eMachineState),
86
+ .class_init = bl475e_machine_init,
87
+ }
88
+};
31
+
89
+
32
+ tcg_res = tcg_temp_new_i32();
90
+DEFINE_TYPES(bl475e_machine_type)
33
+ fpst = get_fpstatus_ptr(true);
34
+ tcg_op1 = read_fp_hreg(s, rn);
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
77
+
78
/* Floating point data-processing (2 source)
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
82
}
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
84
break;
85
+ case 3:
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
87
+ unallocated_encoding(s);
88
+ return;
89
+ }
90
+ if (!fp_access_check(s)) {
91
+ return;
92
+ }
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
94
+ break;
95
default:
96
unallocated_encoding(s);
97
}
98
--
91
--
99
2.17.0
92
2.34.1
100
93
101
94
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
[PULL 20/21] hw/arm : Connect DM163 to B-L475E-IOT01A
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
2
3
Cc: qemu-stable@nongnu.org
3
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
8
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
9
hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++--
11
1 file changed, 14 insertions(+), 16 deletions(-)
10
hw/arm/Kconfig | 1 +
11
2 files changed, 58 insertions(+), 2 deletions(-)
12
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
15
--- a/hw/arm/b-l475e-iot01a.c
16
+++ b/target/arm/translate-a64.c
16
+++ b/hw/arm/b-l475e-iot01a.c
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
17
@@ -XXX,XX +XXX,XX @@
18
return v;
18
#include "hw/boards.h"
19
#include "hw/qdev-properties.h"
20
#include "qemu/error-report.h"
21
-#include "hw/arm/stm32l4x5_soc.h"
22
#include "hw/arm/boot.h"
23
+#include "hw/core/split-irq.h"
24
+#include "hw/arm/stm32l4x5_soc.h"
25
+#include "hw/gpio/stm32l4x5_gpio.h"
26
+#include "hw/display/dm163.h"
27
28
-/* B-L475E-IOT01A implementation is derived from netduinoplus2 */
29
+/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduino */
30
+
31
+/*
32
+ * There are actually 14 input pins in the DM163 device.
33
+ * Here the DM163 input pin EN isn't connected to the STM32L4x5
34
+ * GPIOs as the IM120417002 colors shield doesn't actually use
35
+ * this pin to drive the RGB matrix.
36
+ */
37
+#define NUM_DM163_INPUTS 13
38
+
39
+static const unsigned dm163_input[NUM_DM163_INPUTS] = {
40
+ 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */
41
+ 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */
42
+ 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */
43
+ 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */
44
+ 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */
45
+ 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */
46
+ 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */
47
+ 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */
48
+ 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */
49
+ 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */
50
+ 2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */
51
+ 2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */
52
+ 2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */
53
+};
54
55
#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a")
56
OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A)
57
@@ -XXX,XX +XXX,XX @@ typedef struct Bl475eMachineState {
58
MachineState parent_obj;
59
60
Stm32l4x5SocState soc;
61
+ SplitIRQ gpio_splitters[NUM_DM163_INPUTS];
62
+ DM163State dm163;
63
} Bl475eMachineState;
64
65
static void bl475e_init(MachineState *machine)
66
{
67
Bl475eMachineState *s = B_L475E_IOT01A(machine);
68
const Stm32l4x5SocClass *sc;
69
+ DeviceState *dev, *gpio_out_splitter;
70
+ unsigned gpio, pin;
71
72
object_initialize_child(OBJECT(machine), "soc", &s->soc,
73
TYPE_STM32L4X5XG_SOC);
74
@@ -XXX,XX +XXX,XX @@ static void bl475e_init(MachineState *machine)
75
sc = STM32L4X5_SOC_GET_CLASS(&s->soc);
76
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0,
77
sc->flash_size);
78
+
79
+ if (object_class_by_name(TYPE_DM163)) {
80
+ object_initialize_child(OBJECT(machine), "dm163",
81
+ &s->dm163, TYPE_DM163);
82
+ dev = DEVICE(&s->dm163);
83
+ qdev_realize(dev, NULL, &error_abort);
84
+
85
+ for (unsigned i = 0; i < NUM_DM163_INPUTS; i++) {
86
+ object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]",
87
+ &s->gpio_splitters[i], TYPE_SPLIT_IRQ);
88
+ gpio_out_splitter = DEVICE(&s->gpio_splitters[i]);
89
+ qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2);
90
+ qdev_realize(gpio_out_splitter, NULL, &error_fatal);
91
+
92
+ qdev_connect_gpio_out(gpio_out_splitter, 0,
93
+ qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i]));
94
+ qdev_connect_gpio_out(gpio_out_splitter, 1,
95
+ qdev_get_gpio_in(dev, i));
96
+ gpio = dm163_input[i] / GPIO_NUM_PINS;
97
+ pin = dm163_input[i] % GPIO_NUM_PINS;
98
+ qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin,
99
+ qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0));
100
+ }
101
+ }
19
}
102
}
20
103
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
104
static void bl475e_machine_init(ObjectClass *oc, void *data)
22
+{
105
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
23
+ TCGv_i32 v = tcg_temp_new_i32();
106
index XXXXXXX..XXXXXXX 100644
24
+
107
--- a/hw/arm/Kconfig
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
108
+++ b/hw/arm/Kconfig
26
+ return v;
109
@@ -XXX,XX +XXX,XX @@ config B_L475E_IOT01A
27
+}
110
default y
28
+
111
depends on TCG && ARM
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
112
select STM32L4X5_SOC
30
* If SVE is not enabled, then there are only 128 bits in the vector.
113
+ imply DM163
31
*/
114
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
115
config STM32L4X5_SOC
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
116
bool
34
{
35
TCGv_ptr fpst = NULL;
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
39
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
41
-
42
switch (opcode) {
43
case 0x0: /* FMOV */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
48
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
79
80
if (is_scalar) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
90
--
117
--
91
2.17.0
118
2.34.1
92
119
93
120
diff view generated by jsdifflib
New patch
[PULL 21/21] tests/qtest : Add testcase for DM163
1
1
From: Inès Varhol <ines.varhol@telecom-paris.fr>
2
3
`test_dm163_bank()`
4
Checks that the pin "sout" of the DM163 led driver outputs the values
5
received on pin "sin" with the expected latency (depending on the bank).
6
7
`test_dm163_gpio_connection()`
8
Check that changes to relevant STM32L4x5 GPIO pins are propagated to the
9
DM163 device.
10
11
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
12
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
13
Acked-by: Thomas Huth <thuth@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
15
Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
tests/qtest/dm163-test.c | 194 +++++++++++++++++++++++++++++++++++++++
19
tests/qtest/meson.build | 2 +
20
2 files changed, 196 insertions(+)
21
create mode 100644 tests/qtest/dm163-test.c
22
23
diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c
24
new file mode 100644
25
index XXXXXXX..XXXXXXX
26
--- /dev/null
27
+++ b/tests/qtest/dm163-test.c
28
@@ -XXX,XX +XXX,XX @@
29
+/*
30
+ * QTest testcase for DM163
31
+ *
32
+ * Copyright (C) 2024 Samuel Tardieu <sam@rfc1149.net>
33
+ * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
34
+ * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
35
+ *
36
+ * SPDX-License-Identifier: GPL-2.0-or-later
37
+ */
38
+
39
+#include "qemu/osdep.h"
40
+#include "libqtest.h"
41
+
42
+enum DM163_INPUTS {
43
+ SIN = 8,
44
+ DCK = 9,
45
+ RST_B = 10,
46
+ LAT_B = 11,
47
+ SELBK = 12,
48
+ EN_B = 13
49
+};
50
+
51
+#define DEVICE_NAME "/machine/dm163"
52
+#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, name, \
53
+ value)
54
+#define GPIO_PULSE(name) \
55
+ do { \
56
+ GPIO_OUT(name, 1); \
57
+ GPIO_OUT(name, 0); \
58
+ } while (0)
59
+
60
+
61
+static void rise_gpio_pin_dck(QTestState *qts)
62
+{
63
+ /* Configure output mode for pin PB1 */
64
+ qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
65
+ /* Write 1 in ODR for PB1 */
66
+ qtest_writel(qts, 0x48000414, 0x00000002);
67
+}
68
+
69
+static void lower_gpio_pin_dck(QTestState *qts)
70
+{
71
+ /* Configure output mode for pin PB1 */
72
+ qtest_writel(qts, 0x48000400, 0xFFFFFEB7);
73
+ /* Write 0 in ODR for PB1 */
74
+ qtest_writel(qts, 0x48000414, 0x00000000);
75
+}
76
+
77
+static void rise_gpio_pin_selbk(QTestState *qts)
78
+{
79
+ /* Configure output mode for pin PC5 */
80
+ qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
81
+ /* Write 1 in ODR for PC5 */
82
+ qtest_writel(qts, 0x48000814, 0x00000020);
83
+}
84
+
85
+static void lower_gpio_pin_selbk(QTestState *qts)
86
+{
87
+ /* Configure output mode for pin PC5 */
88
+ qtest_writel(qts, 0x48000800, 0xFFFFF7FF);
89
+ /* Write 0 in ODR for PC5 */
90
+ qtest_writel(qts, 0x48000814, 0x00000000);
91
+}
92
+
93
+static void rise_gpio_pin_lat_b(QTestState *qts)
94
+{
95
+ /* Configure output mode for pin PC4 */
96
+ qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
97
+ /* Write 1 in ODR for PC4 */
98
+ qtest_writel(qts, 0x48000814, 0x00000010);
99
+}
100
+
101
+static void lower_gpio_pin_lat_b(QTestState *qts)
102
+{
103
+ /* Configure output mode for pin PC4 */
104
+ qtest_writel(qts, 0x48000800, 0xFFFFFDFF);
105
+ /* Write 0 in ODR for PC4 */
106
+ qtest_writel(qts, 0x48000814, 0x00000000);
107
+}
108
+
109
+static void rise_gpio_pin_rst_b(QTestState *qts)
110
+{
111
+ /* Configure output mode for pin PC3 */
112
+ qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
113
+ /* Write 1 in ODR for PC3 */
114
+ qtest_writel(qts, 0x48000814, 0x00000008);
115
+}
116
+
117
+static void lower_gpio_pin_rst_b(QTestState *qts)
118
+{
119
+ /* Configure output mode for pin PC3 */
120
+ qtest_writel(qts, 0x48000800, 0xFFFFFF7F);
121
+ /* Write 0 in ODR for PC3 */
122
+ qtest_writel(qts, 0x48000814, 0x00000000);
123
+}
124
+
125
+static void rise_gpio_pin_sin(QTestState *qts)
126
+{
127
+ /* Configure output mode for pin PA4 */
128
+ qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
129
+ /* Write 1 in ODR for PA4 */
130
+ qtest_writel(qts, 0x48000014, 0x00000010);
131
+}
132
+
133
+static void lower_gpio_pin_sin(QTestState *qts)
134
+{
135
+ /* Configure output mode for pin PA4 */
136
+ qtest_writel(qts, 0x48000000, 0xFFFFFDFF);
137
+ /* Write 0 in ODR for PA4 */
138
+ qtest_writel(qts, 0x48000014, 0x00000000);
139
+}
140
+
141
+static void test_dm163_bank(const void *opaque)
142
+{
143
+ const unsigned bank = (uintptr_t) opaque;
144
+ const int width = bank ? 192 : 144;
145
+
146
+ QTestState *qts = qtest_initf("-M b-l475e-iot01a");
147
+ qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout");
148
+ GPIO_OUT(RST_B, 1);
149
+ GPIO_OUT(EN_B, 0);
150
+ GPIO_OUT(DCK, 0);
151
+ GPIO_OUT(SELBK, bank);
152
+ GPIO_OUT(LAT_B, 1);
153
+
154
+ /* Fill bank with zeroes */
155
+ GPIO_OUT(SIN, 0);
156
+ for (int i = 0; i < width; i++) {
157
+ GPIO_PULSE(DCK);
158
+ }
159
+ /* Fill bank with ones, check that we get the previous zeroes */
160
+ GPIO_OUT(SIN, 1);
161
+ for (int i = 0; i < width; i++) {
162
+ GPIO_PULSE(DCK);
163
+ g_assert(!qtest_get_irq(qts, 0));
164
+ }
165
+
166
+ /* Pulse one more bit in the bank, check that we get a one */
167
+ GPIO_PULSE(DCK);
168
+ g_assert(qtest_get_irq(qts, 0));
169
+
170
+ qtest_quit(qts);
171
+}
172
+
173
+static void test_dm163_gpio_connection(void)
174
+{
175
+ QTestState *qts = qtest_init("-M b-l475e-iot01a");
176
+ qtest_irq_intercept_in(qts, DEVICE_NAME);
177
+
178
+ g_assert_false(qtest_get_irq(qts, SIN));
179
+ g_assert_false(qtest_get_irq(qts, DCK));
180
+ g_assert_false(qtest_get_irq(qts, RST_B));
181
+ g_assert_false(qtest_get_irq(qts, LAT_B));
182
+ g_assert_false(qtest_get_irq(qts, SELBK));
183
+
184
+ rise_gpio_pin_dck(qts);
185
+ g_assert_true(qtest_get_irq(qts, DCK));
186
+ lower_gpio_pin_dck(qts);
187
+ g_assert_false(qtest_get_irq(qts, DCK));
188
+
189
+ rise_gpio_pin_lat_b(qts);
190
+ g_assert_true(qtest_get_irq(qts, LAT_B));
191
+ lower_gpio_pin_lat_b(qts);
192
+ g_assert_false(qtest_get_irq(qts, LAT_B));
193
+
194
+ rise_gpio_pin_selbk(qts);
195
+ g_assert_true(qtest_get_irq(qts, SELBK));
196
+ lower_gpio_pin_selbk(qts);
197
+ g_assert_false(qtest_get_irq(qts, SELBK));
198
+
199
+ rise_gpio_pin_rst_b(qts);
200
+ g_assert_true(qtest_get_irq(qts, RST_B));
201
+ lower_gpio_pin_rst_b(qts);
202
+ g_assert_false(qtest_get_irq(qts, RST_B));
203
+
204
+ rise_gpio_pin_sin(qts);
205
+ g_assert_true(qtest_get_irq(qts, SIN));
206
+ lower_gpio_pin_sin(qts);
207
+ g_assert_false(qtest_get_irq(qts, SIN));
208
+
209
+ g_assert_false(qtest_get_irq(qts, DCK));
210
+ g_assert_false(qtest_get_irq(qts, LAT_B));
211
+ g_assert_false(qtest_get_irq(qts, SELBK));
212
+ g_assert_false(qtest_get_irq(qts, RST_B));
213
+}
214
+
215
+int main(int argc, char **argv)
216
+{
217
+ g_test_init(&argc, &argv, NULL);
218
+ qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank);
219
+ qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank);
220
+ qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection);
221
+ return g_test_run();
222
+}
223
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
224
index XXXXXXX..XXXXXXX 100644
225
--- a/tests/qtest/meson.build
226
+++ b/tests/qtest/meson.build
227
@@ -XXX,XX +XXX,XX @@ qtests_arm = \
228
(config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : []) + \
229
(config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 : []) + \
230
(config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-test'] : []) + \
231
+ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and
232
+ config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \
233
['arm-cpu-features',
234
'boot-serial-test']
235
236
--
237
2.34.1
238
239
diff view generated by jsdifflib

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