[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/21] target-arm queue
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The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
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The following changes since commit f003dd8d81f7d88f4b1f8802309eaa76f6eb223a:
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Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
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Merge tag 'pull-tcg-20230305' of https://gitlab.com/rth7680/qemu into staging (2023-03-06 10:20:04 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230306
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9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
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for you to fetch changes up to 2ddc45954f97cd1d7ee5cbca0def05e980d1da9f:
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tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
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hw: arm: allwinner-h3: Fix and complete H3 i2c devices (2023-03-06 15:31:24 +0000)
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12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
target-arm queue:
14
target-arm queue:
15
* Fix coverity nit in int_to_float code
15
* allwinner-h3: Fix I2C controller model for Sun6i SoCs
16
* Don't set Invalid for float-to-int(MAXINT)
16
* allwinner-h3: Add missing i2c controllers
17
* Fix fp_status_f16 tininess before rounding
17
* Expose M-profile system registers to gdbstub
18
* Add various missing insns from the v8.2-FP16 extension
18
* Expose pauth information to gdbstub
19
* Fix sqrt_f16 exception raising
19
* Support direct boot for Linux/arm64 EFI zboot images
20
* sdcard: Correct CRC16 offset in sd_function_switch()
20
* Fix incorrect stage 2 MMU setup validation
21
* tcg: Optionally log FPU state in TCG -d cpu logging
22
21
23
----------------------------------------------------------------
22
----------------------------------------------------------------
24
Alex Bennée (5):
23
Ard Biesheuvel (1):
25
fpu/softfloat: int_to_float ensure r fully initialised
24
hw: arm: Support direct boot for Linux/arm64 EFI zboot images
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
30
25
31
Peter Maydell (3):
26
David Reiss (2):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
27
target/arm: Export arm_v7m_mrs_control
33
target/arm: Fix fp_status_f16 tininess before rounding
28
target/arm: Export arm_v7m_get_sp_ptr
34
tcg: Optionally log FPU state in TCG -d cpu logging
35
29
36
Philippe Mathieu-Daudé (1):
30
Richard Henderson (16):
37
sdcard: Correct CRC16 offset in sd_function_switch()
31
target/arm: Normalize aarch64 gdbstub get/set function names
32
target/arm: Unexport arm_gen_dynamic_sysreg_xml
33
target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
34
target/arm: Split out output_vector_union_type
35
target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
36
target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
37
target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
38
target/arm: Add name argument to output_vector_union_type
39
target/arm: Simplify iteration over bit widths
40
target/arm: Create pauth_ptr_mask
41
target/arm: Implement gdbstub pauth extension
42
target/arm: Implement gdbstub m-profile systemreg and secext
43
target/arm: Handle m-profile in arm_is_secure
44
target/arm: Stub arm_hcr_el2_eff for m-profile
45
target/arm: Diagnose incorrect usage of arm_is_secure subroutines
46
target/arm: Rewrite check_s2_mmu_setup
38
47
39
Richard Henderson (7):
48
qianfan Zhao (2):
40
target/arm: Implement FMOV (general) for fp16
49
hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
50
hw: arm: allwinner-h3: Fix and complete H3 i2c devices
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
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51
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include/qemu/log.h | 1 +
52
configs/targets/aarch64-linux-user.mak | 2 +-
49
target/arm/helper-a64.h | 2 +
53
configs/targets/aarch64-softmmu.mak | 2 +-
50
target/arm/helper.h | 6 +
54
configs/targets/aarch64_be-linux-user.mak | 2 +-
51
accel/tcg/cpu-exec.c | 9 +-
55
include/hw/arm/allwinner-h3.h | 6 +
52
fpu/softfloat.c | 6 +-
56
include/hw/i2c/allwinner-i2c.h | 6 +
53
hw/sd/sd.c | 2 +-
57
include/hw/loader.h | 19 ++
54
target/arm/cpu.c | 2 +
58
target/arm/cpu.h | 17 +-
55
target/arm/helper-a64.c | 10 ++
59
target/arm/internals.h | 34 +++-
56
target/arm/helper.c | 38 +++-
60
hw/arm/allwinner-h3.c | 29 +++-
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
61
hw/arm/boot.c | 6 +
58
util/log.c | 2 +
62
hw/core/loader.c | 91 ++++++++++
59
11 files changed, 428 insertions(+), 71 deletions(-)
63
hw/i2c/allwinner-i2c.c | 26 ++-
60
64
target/arm/gdbstub.c | 278 ++++++++++++++++++------------
65
target/arm/gdbstub64.c | 175 ++++++++++++++++++-
66
target/arm/helper.c | 3 +
67
target/arm/ptw.c | 173 +++++++++++--------
68
target/arm/tcg/m_helper.c | 90 +++++-----
69
target/arm/tcg/pauth_helper.c | 26 ++-
70
gdb-xml/aarch64-pauth.xml | 15 ++
71
19 files changed, 742 insertions(+), 258 deletions(-)
72
create mode 100644 gdb-xml/aarch64-pauth.xml
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
[PULL 01/21] target/arm: Normalize aarch64 gdbstub get/set function names
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
These where missed out from the rest of the half-precision work.
3
Make the form of the function names between fp and sve the same:
4
- arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
5
- aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
4
6
5
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
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Message-id: 20230227213329.793795-2-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
target/arm/helper-a64.h | 2 +
13
target/arm/internals.h | 8 ++++----
16
target/arm/helper-a64.c | 10 +++++
14
target/arm/gdbstub.c | 9 +++++----
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
15
target/arm/gdbstub64.c | 8 ++++----
18
3 files changed, 83 insertions(+), 17 deletions(-)
16
3 files changed, 13 insertions(+), 12 deletions(-)
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17
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
21
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
20
--- a/target/arm/internals.h
23
+++ b/target/arm/helper-a64.h
21
+++ b/target/arm/internals.h
24
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
23
}
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
24
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
25
#ifdef TARGET_AARCH64
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
26
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg);
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
27
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg);
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
28
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg);
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
29
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
30
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
31
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
32
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
33
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
34
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
35
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
36
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
37
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
34
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
39
--- a/target/arm/gdbstub.c
36
+++ b/target/arm/helper-a64.c
40
+++ b/target/arm/gdbstub.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
41
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
38
return flags;
42
*/
43
#ifdef TARGET_AARCH64
44
if (isar_feature_aa64_sve(&cpu->isar)) {
45
- gdb_register_coprocessor(cs, arm_gdb_get_svereg, arm_gdb_set_svereg,
46
- arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs),
47
+ int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);
48
+ gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,
49
+ aarch64_gdb_set_sve_reg, nreg,
50
"sve-registers.xml", 0);
51
} else {
52
- gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
53
- aarch64_fpu_gdb_set_reg,
54
+ gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,
55
+ aarch64_gdb_set_fpu_reg,
56
34, "aarch64-fpu.xml", 0);
57
}
58
#endif
59
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/gdbstub64.c
62
+++ b/target/arm/gdbstub64.c
63
@@ -XXX,XX +XXX,XX @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
64
return 0;
39
}
65
}
40
66
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
67
-int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
42
+{
68
+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
44
+}
45
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
52
{
69
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
70
switch (reg) {
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
71
case 0 ... 31:
55
index XXXXXXX..XXXXXXX 100644
72
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
73
}
60
}
74
}
61
75
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
76
-int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
63
+static void handle_fp_compare(DisasContext *s, int size,
77
+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
78
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
79
switch (reg) {
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
80
case 0 ... 31:
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
81
@@ -XXX,XX +XXX,XX @@ int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
82
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
83
}
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
84
85
-int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
86
+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)
122
{
87
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
88
ARMCPU *cpu = env_archcpu(env);
124
+ int size;
89
125
90
@@ -XXX,XX +XXX,XX @@ int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg)
126
mos = extract32(insn, 29, 3);
91
return 0;
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
92
}
165
93
166
/* Floating point conditional compare
94
-int arm_gdb_set_svereg(CPUARMState *env, uint8_t *buf, int reg)
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
95
+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
96
{
169
TCGv_i64 tcg_flags;
97
ARMCPU *cpu = env_archcpu(env);
170
TCGLabel *label_continue = NULL;
98
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
99
--
215
2.17.0
100
2.34.1
216
101
217
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
[PULL 02/21] target/arm: Unexport arm_gen_dynamic_sysreg_xml
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Adding the fp16 moves to/from general registers.
3
This function is not used outside gdbstub.c.
4
4
5
Cc: qemu-stable@nongnu.org
5
Reviewed-by: Fabiano Rosas <farosas@suse.de>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230227213329.793795-3-richard.henderson@linaro.org
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
11
target/arm/cpu.h | 1 -
13
1 file changed, 21 insertions(+)
12
target/arm/gdbstub.c | 2 +-
13
2 files changed, 1 insertion(+), 2 deletions(-)
14
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
19
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
20
* Helpers to dynamically generates XML descriptions of the sysregs
21
clear_vec_high(s, true, rd);
21
* and SVE registers. Returns the number of registers in each set.
22
break;
22
*/
23
+ case 3:
23
-int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
24
+ /* 16 bit */
24
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
25
+ tmp = tcg_temp_new_i64();
25
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
26
/* Returns the dynamically generated XML for the gdb stub.
27
+ write_fp_dreg(s, rd, tmp);
27
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
28
+ tcg_temp_free_i64(tmp);
28
index XXXXXXX..XXXXXXX 100644
29
+ break;
29
--- a/target/arm/gdbstub.c
30
+ default:
30
+++ b/target/arm/gdbstub.c
31
+ g_assert_not_reached();
31
@@ -XXX,XX +XXX,XX @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
32
}
33
} else {
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
36
/* 64 bits from top half */
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
46
}
32
}
47
}
33
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
34
49
case 0xa: /* 64 bit */
35
-int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
50
case 0xd: /* 64 bit to top half of quad */
36
+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
51
break;
37
{
52
+ case 0x6: /* 16-bit float, 32-bit int */
38
ARMCPU *cpu = ARM_CPU(cs);
53
+ case 0xe: /* 16-bit float, 64-bit int */
39
GString *s = g_string_new(NULL);
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
55
+ break;
56
+ }
57
+ /* fallthru */
58
default:
59
/* all other sf/type/rmode combinations are invalid */
60
unallocated_encoding(s);
61
--
40
--
62
2.17.0
41
2.34.1
63
42
64
43
diff view generated by jsdifflib
New patch
[PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
1
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
The function is only used for aarch64, so move it to the
4
file that has the other aarch64 gdbstub stuff. Move the
5
declaration to internals.h.
6
7
Reviewed-by: Fabiano Rosas <farosas@suse.de>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230227213329.793795-4-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.h | 6 ---
14
target/arm/internals.h | 1 +
15
target/arm/gdbstub.c | 120 -----------------------------------------
16
target/arm/gdbstub64.c | 118 ++++++++++++++++++++++++++++++++++++++++
17
4 files changed, 119 insertions(+), 126 deletions(-)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
24
int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
25
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
26
27
-/*
28
- * Helpers to dynamically generates XML descriptions of the sysregs
29
- * and SVE registers. Returns the number of registers in each set.
30
- */
31
-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
32
-
33
/* Returns the dynamically generated XML for the gdb stub.
34
* Returns a pointer to the XML contents for the specified XML file or NULL
35
* if the XML name doesn't match the predefined one.
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/internals.h
39
+++ b/target/arm/internals.h
40
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
41
}
42
43
#ifdef TARGET_AARCH64
44
+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
45
int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
46
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
47
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
48
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/gdbstub.c
51
+++ b/target/arm/gdbstub.c
52
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
53
return cpu->dyn_sysreg_xml.num;
54
}
55
56
-struct TypeSize {
57
- const char *gdb_type;
58
- int size;
59
- const char sz, suffix;
60
-};
61
-
62
-static const struct TypeSize vec_lanes[] = {
63
- /* quads */
64
- { "uint128", 128, 'q', 'u' },
65
- { "int128", 128, 'q', 's' },
66
- /* 64 bit */
67
- { "ieee_double", 64, 'd', 'f' },
68
- { "uint64", 64, 'd', 'u' },
69
- { "int64", 64, 'd', 's' },
70
- /* 32 bit */
71
- { "ieee_single", 32, 's', 'f' },
72
- { "uint32", 32, 's', 'u' },
73
- { "int32", 32, 's', 's' },
74
- /* 16 bit */
75
- { "ieee_half", 16, 'h', 'f' },
76
- { "uint16", 16, 'h', 'u' },
77
- { "int16", 16, 'h', 's' },
78
- /* bytes */
79
- { "uint8", 8, 'b', 'u' },
80
- { "int8", 8, 'b', 's' },
81
-};
82
-
83
-
84
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
85
-{
86
- ARMCPU *cpu = ARM_CPU(cs);
87
- GString *s = g_string_new(NULL);
88
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
89
- g_autoptr(GString) ts = g_string_new("");
90
- int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
91
- info->num = 0;
92
- g_string_printf(s, "<?xml version=\"1.0\"?>");
93
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
94
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
95
-
96
- /* First define types and totals in a whole VL */
97
- for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
98
- int count = reg_width / vec_lanes[i].size;
99
- g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
100
- g_string_append_printf(s,
101
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
102
- ts->str, vec_lanes[i].gdb_type, count);
103
- }
104
- /*
105
- * Now define a union for each size group containing unsigned and
106
- * signed and potentially float versions of each size from 128 to
107
- * 8 bits.
108
- */
109
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
110
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
111
- g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
112
- for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
113
- if (vec_lanes[j].size == bits) {
114
- g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
115
- vec_lanes[j].suffix,
116
- vec_lanes[j].sz, vec_lanes[j].suffix);
117
- }
118
- }
119
- g_string_append(s, "</union>");
120
- }
121
- /* And now the final union of unions */
122
- g_string_append(s, "<union id=\"svev\">");
123
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
124
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
125
- g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
126
- suf[i], suf[i]);
127
- }
128
- g_string_append(s, "</union>");
129
-
130
- /* Finally the sve prefix type */
131
- g_string_append_printf(s,
132
- "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
133
- reg_width / 8);
134
-
135
- /* Then define each register in parts for each vq */
136
- for (i = 0; i < 32; i++) {
137
- g_string_append_printf(s,
138
- "<reg name=\"z%d\" bitsize=\"%d\""
139
- " regnum=\"%d\" type=\"svev\"/>",
140
- i, reg_width, base_reg++);
141
- info->num++;
142
- }
143
- /* fpscr & status registers */
144
- g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
145
- " regnum=\"%d\" group=\"float\""
146
- " type=\"int\"/>", base_reg++);
147
- g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
148
- " regnum=\"%d\" group=\"float\""
149
- " type=\"int\"/>", base_reg++);
150
- info->num += 2;
151
-
152
- for (i = 0; i < 16; i++) {
153
- g_string_append_printf(s,
154
- "<reg name=\"p%d\" bitsize=\"%d\""
155
- " regnum=\"%d\" type=\"svep\"/>",
156
- i, cpu->sve_max_vq * 16, base_reg++);
157
- info->num++;
158
- }
159
- g_string_append_printf(s,
160
- "<reg name=\"ffr\" bitsize=\"%d\""
161
- " regnum=\"%d\" group=\"vector\""
162
- " type=\"svep\"/>",
163
- cpu->sve_max_vq * 16, base_reg++);
164
- g_string_append_printf(s,
165
- "<reg name=\"vg\" bitsize=\"64\""
166
- " regnum=\"%d\" type=\"int\"/>",
167
- base_reg++);
168
- info->num += 2;
169
- g_string_append_printf(s, "</feature>");
170
- cpu->dyn_svereg_xml.desc = g_string_free(s, false);
171
-
172
- return cpu->dyn_svereg_xml.num;
173
-}
174
-
175
-
176
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
177
{
178
ARMCPU *cpu = ARM_CPU(cs);
179
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
180
index XXXXXXX..XXXXXXX 100644
181
--- a/target/arm/gdbstub64.c
182
+++ b/target/arm/gdbstub64.c
183
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
184
185
return 0;
186
}
187
+
188
+struct TypeSize {
189
+ const char *gdb_type;
190
+ short size;
191
+ char sz, suffix;
192
+};
193
+
194
+static const struct TypeSize vec_lanes[] = {
195
+ /* quads */
196
+ { "uint128", 128, 'q', 'u' },
197
+ { "int128", 128, 'q', 's' },
198
+ /* 64 bit */
199
+ { "ieee_double", 64, 'd', 'f' },
200
+ { "uint64", 64, 'd', 'u' },
201
+ { "int64", 64, 'd', 's' },
202
+ /* 32 bit */
203
+ { "ieee_single", 32, 's', 'f' },
204
+ { "uint32", 32, 's', 'u' },
205
+ { "int32", 32, 's', 's' },
206
+ /* 16 bit */
207
+ { "ieee_half", 16, 'h', 'f' },
208
+ { "uint16", 16, 'h', 'u' },
209
+ { "int16", 16, 'h', 's' },
210
+ /* bytes */
211
+ { "uint8", 8, 'b', 'u' },
212
+ { "int8", 8, 'b', 's' },
213
+};
214
+
215
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
216
+{
217
+ ARMCPU *cpu = ARM_CPU(cs);
218
+ GString *s = g_string_new(NULL);
219
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
220
+ g_autoptr(GString) ts = g_string_new("");
221
+ int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
222
+ info->num = 0;
223
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
224
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
225
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
226
+
227
+ /* First define types and totals in a whole VL */
228
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
229
+ int count = reg_width / vec_lanes[i].size;
230
+ g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
231
+ g_string_append_printf(s,
232
+ "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
233
+ ts->str, vec_lanes[i].gdb_type, count);
234
+ }
235
+ /*
236
+ * Now define a union for each size group containing unsigned and
237
+ * signed and potentially float versions of each size from 128 to
238
+ * 8 bits.
239
+ */
240
+ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
241
+ const char suf[] = { 'q', 'd', 's', 'h', 'b' };
242
+ g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
243
+ for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
244
+ if (vec_lanes[j].size == bits) {
245
+ g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
246
+ vec_lanes[j].suffix,
247
+ vec_lanes[j].sz, vec_lanes[j].suffix);
248
+ }
249
+ }
250
+ g_string_append(s, "</union>");
251
+ }
252
+ /* And now the final union of unions */
253
+ g_string_append(s, "<union id=\"svev\">");
254
+ for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
255
+ const char suf[] = { 'q', 'd', 's', 'h', 'b' };
256
+ g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
257
+ suf[i], suf[i]);
258
+ }
259
+ g_string_append(s, "</union>");
260
+
261
+ /* Finally the sve prefix type */
262
+ g_string_append_printf(s,
263
+ "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
264
+ reg_width / 8);
265
+
266
+ /* Then define each register in parts for each vq */
267
+ for (i = 0; i < 32; i++) {
268
+ g_string_append_printf(s,
269
+ "<reg name=\"z%d\" bitsize=\"%d\""
270
+ " regnum=\"%d\" type=\"svev\"/>",
271
+ i, reg_width, base_reg++);
272
+ info->num++;
273
+ }
274
+ /* fpscr & status registers */
275
+ g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
276
+ " regnum=\"%d\" group=\"float\""
277
+ " type=\"int\"/>", base_reg++);
278
+ g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
279
+ " regnum=\"%d\" group=\"float\""
280
+ " type=\"int\"/>", base_reg++);
281
+ info->num += 2;
282
+
283
+ for (i = 0; i < 16; i++) {
284
+ g_string_append_printf(s,
285
+ "<reg name=\"p%d\" bitsize=\"%d\""
286
+ " regnum=\"%d\" type=\"svep\"/>",
287
+ i, cpu->sve_max_vq * 16, base_reg++);
288
+ info->num++;
289
+ }
290
+ g_string_append_printf(s,
291
+ "<reg name=\"ffr\" bitsize=\"%d\""
292
+ " regnum=\"%d\" group=\"vector\""
293
+ " type=\"svep\"/>",
294
+ cpu->sve_max_vq * 16, base_reg++);
295
+ g_string_append_printf(s,
296
+ "<reg name=\"vg\" bitsize=\"64\""
297
+ " regnum=\"%d\" type=\"int\"/>",
298
+ base_reg++);
299
+ info->num += 2;
300
+ g_string_append_printf(s, "</feature>");
301
+ info->desc = g_string_free(s, false);
302
+
303
+ return info->num;
304
+}
305
--
306
2.34.1
307
308
diff view generated by jsdifflib
New patch
[PULL 04/21] target/arm: Split out output_vector_union_type
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Create a subroutine for creating the union of unions
4
of the various type sizes that a vector may contain.
5
6
Reviewed-by: Fabiano Rosas <farosas@suse.de>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20230227213329.793795-5-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/gdbstub64.c | 83 +++++++++++++++++++++++-------------------
13
1 file changed, 45 insertions(+), 38 deletions(-)
14
15
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/gdbstub64.c
18
+++ b/target/arm/gdbstub64.c
19
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
20
return 0;
21
}
22
23
-struct TypeSize {
24
- const char *gdb_type;
25
- short size;
26
- char sz, suffix;
27
-};
28
-
29
-static const struct TypeSize vec_lanes[] = {
30
- /* quads */
31
- { "uint128", 128, 'q', 'u' },
32
- { "int128", 128, 'q', 's' },
33
- /* 64 bit */
34
- { "ieee_double", 64, 'd', 'f' },
35
- { "uint64", 64, 'd', 'u' },
36
- { "int64", 64, 'd', 's' },
37
- /* 32 bit */
38
- { "ieee_single", 32, 's', 'f' },
39
- { "uint32", 32, 's', 'u' },
40
- { "int32", 32, 's', 's' },
41
- /* 16 bit */
42
- { "ieee_half", 16, 'h', 'f' },
43
- { "uint16", 16, 'h', 'u' },
44
- { "int16", 16, 'h', 's' },
45
- /* bytes */
46
- { "uint8", 8, 'b', 'u' },
47
- { "int8", 8, 'b', 's' },
48
-};
49
-
50
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
51
+static void output_vector_union_type(GString *s, int reg_width)
52
{
53
- ARMCPU *cpu = ARM_CPU(cs);
54
- GString *s = g_string_new(NULL);
55
- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
56
+ struct TypeSize {
57
+ const char *gdb_type;
58
+ short size;
59
+ char sz, suffix;
60
+ };
61
+
62
+ static const struct TypeSize vec_lanes[] = {
63
+ /* quads */
64
+ { "uint128", 128, 'q', 'u' },
65
+ { "int128", 128, 'q', 's' },
66
+ /* 64 bit */
67
+ { "ieee_double", 64, 'd', 'f' },
68
+ { "uint64", 64, 'd', 'u' },
69
+ { "int64", 64, 'd', 's' },
70
+ /* 32 bit */
71
+ { "ieee_single", 32, 's', 'f' },
72
+ { "uint32", 32, 's', 'u' },
73
+ { "int32", 32, 's', 's' },
74
+ /* 16 bit */
75
+ { "ieee_half", 16, 'h', 'f' },
76
+ { "uint16", 16, 'h', 'u' },
77
+ { "int16", 16, 'h', 's' },
78
+ /* bytes */
79
+ { "uint8", 8, 'b', 'u' },
80
+ { "int8", 8, 'b', 's' },
81
+ };
82
+
83
+ static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
84
+
85
g_autoptr(GString) ts = g_string_new("");
86
- int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
87
- info->num = 0;
88
- g_string_printf(s, "<?xml version=\"1.0\"?>");
89
- g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
90
- g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
91
+ int i, j, bits;
92
93
/* First define types and totals in a whole VL */
94
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
95
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
96
* 8 bits.
97
*/
98
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
99
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
100
g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
101
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
102
if (vec_lanes[j].size == bits) {
103
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
104
/* And now the final union of unions */
105
g_string_append(s, "<union id=\"svev\">");
106
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
107
- const char suf[] = { 'q', 'd', 's', 'h', 'b' };
108
g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
109
suf[i], suf[i]);
110
}
111
g_string_append(s, "</union>");
112
+}
113
+
114
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
115
+{
116
+ ARMCPU *cpu = ARM_CPU(cs);
117
+ GString *s = g_string_new(NULL);
118
+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
119
+ int i, reg_width = (cpu->sve_max_vq * 128);
120
+ info->num = 0;
121
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
122
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
123
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
124
+
125
+ output_vector_union_type(s, reg_width);
126
127
/* Finally the sve prefix type */
128
g_string_append_printf(s,
129
--
130
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
[PULL 05/21] target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to diagnose problems, but sometimes you want to see the state of
3
the floating point registers as well. We don't want to enable that
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
6
2
3
Rather than increment base_reg and num, compute num from the change
4
to base_reg at the end. Clean up some nearby comments.
5
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
10
---
10
---
11
include/qemu/log.h | 1 +
11
target/arm/gdbstub64.c | 27 ++++++++++++++++-----------
12
accel/tcg/cpu-exec.c | 9 ++++++---
12
1 file changed, 16 insertions(+), 11 deletions(-)
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
13
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
16
--- a/target/arm/gdbstub64.c
19
+++ b/include/qemu/log.h
17
+++ b/target/arm/gdbstub64.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
18
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
21
#define CPU_LOG_PAGE (1 << 14)
19
g_string_append(s, "</union>");
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
20
}
23
#define CPU_LOG_TB_OP_IND (1 << 16)
21
24
+#define CPU_LOG_TB_FPU (1 << 17)
22
-int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
25
23
+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
26
/* Lock output for a series of related logs. Since this is not needed
24
{
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
25
ARMCPU *cpu = ARM_CPU(cs);
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
26
GString *s = g_string_new(NULL);
29
index XXXXXXX..XXXXXXX 100644
27
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
30
--- a/accel/tcg/cpu-exec.c
28
- int i, reg_width = (cpu->sve_max_vq * 128);
31
+++ b/accel/tcg/cpu-exec.c
29
- info->num = 0;
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
30
+ int reg_width = cpu->sve_max_vq * 128;
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
31
+ int base_reg = orig_base_reg;
34
&& qemu_log_in_addr_range(itb->pc)) {
32
+ int i;
35
qemu_log_lock();
33
+
36
+ int flags = 0;
34
g_string_printf(s, "<?xml version=\"1.0\"?>");
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
35
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
38
+ flags |= CPU_DUMP_FPU;
36
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
39
+ }
37
40
#if defined(TARGET_I386)
38
+ /* Create the vector union type. */
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
39
output_vector_union_type(s, reg_width);
42
-#else
40
43
- log_cpu_state(cpu, 0);
41
- /* Finally the sve prefix type */
44
+ flags |= CPU_DUMP_CCOP;
42
+ /* Create the predicate vector type. */
45
#endif
43
g_string_append_printf(s,
46
+ log_cpu_state(cpu, flags);
44
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
47
qemu_log_unlock();
45
reg_width / 8);
46
47
- /* Then define each register in parts for each vq */
48
+ /* Define the vector registers. */
49
for (i = 0; i < 32; i++) {
50
g_string_append_printf(s,
51
"<reg name=\"z%d\" bitsize=\"%d\""
52
" regnum=\"%d\" type=\"svev\"/>",
53
i, reg_width, base_reg++);
54
- info->num++;
48
}
55
}
49
#endif /* DEBUG_DISAS */
56
+
50
diff --git a/util/log.c b/util/log.c
57
/* fpscr & status registers */
51
index XXXXXXX..XXXXXXX 100644
58
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
52
--- a/util/log.c
59
" regnum=\"%d\" group=\"float\""
53
+++ b/util/log.c
60
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
61
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
55
"show trace before each executed TB (lots of logs)" },
62
" regnum=\"%d\" group=\"float\""
56
{ CPU_LOG_TB_CPU, "cpu",
63
" type=\"int\"/>", base_reg++);
57
"show CPU registers before entering a TB (lots of logs)" },
64
- info->num += 2;
58
+ { CPU_LOG_TB_FPU, "fpu",
65
59
+ "include FPU registers in the 'cpu' logging" },
66
+ /* Define the predicate registers. */
60
{ CPU_LOG_MMU, "mmu",
67
for (i = 0; i < 16; i++) {
61
"log MMU-related activities" },
68
g_string_append_printf(s,
62
{ CPU_LOG_PCALL, "pcall",
69
"<reg name=\"p%d\" bitsize=\"%d\""
70
" regnum=\"%d\" type=\"svep\"/>",
71
i, cpu->sve_max_vq * 16, base_reg++);
72
- info->num++;
73
}
74
g_string_append_printf(s,
75
"<reg name=\"ffr\" bitsize=\"%d\""
76
" regnum=\"%d\" group=\"vector\""
77
" type=\"svep\"/>",
78
cpu->sve_max_vq * 16, base_reg++);
79
+
80
+ /* Define the vector length pseudo-register. */
81
g_string_append_printf(s,
82
"<reg name=\"vg\" bitsize=\"64\""
83
" regnum=\"%d\" type=\"int\"/>",
84
base_reg++);
85
- info->num += 2;
86
- g_string_append_printf(s, "</feature>");
87
- info->desc = g_string_free(s, false);
88
89
+ g_string_append_printf(s, "</feature>");
90
+
91
+ info->desc = g_string_free(s, false);
92
+ info->num = base_reg - orig_base_reg;
93
return info->num;
94
}
63
--
95
--
64
2.17.0
96
2.34.1
65
97
66
98
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
[PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We are meant to explicitly pass fpst, not cpu_env.
3
Reviewed-by: Fabiano Rosas <farosas@suse.de>
4
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20230227213329.793795-7-richard.henderson@linaro.org
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
8
---
13
target/arm/translate-a64.c | 3 ++-
9
target/arm/gdbstub64.c | 5 +++--
14
1 file changed, 2 insertions(+), 1 deletion(-)
10
1 file changed, 3 insertions(+), 2 deletions(-)
15
11
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
14
--- a/target/arm/gdbstub64.c
19
+++ b/target/arm/translate-a64.c
15
+++ b/target/arm/gdbstub64.c
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
16
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
17
GString *s = g_string_new(NULL);
22
break;
18
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
23
case 0x3: /* FSQRT */
19
int reg_width = cpu->sve_max_vq * 128;
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
20
+ int pred_width = cpu->sve_max_vq * 16;
25
+ fpst = get_fpstatus_ptr(true);
21
int base_reg = orig_base_reg;
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
22
int i;
27
break;
23
28
case 0x8: /* FRINTN */
24
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
29
case 0x9: /* FRINTP */
25
g_string_append_printf(s,
26
"<reg name=\"p%d\" bitsize=\"%d\""
27
" regnum=\"%d\" type=\"svep\"/>",
28
- i, cpu->sve_max_vq * 16, base_reg++);
29
+ i, pred_width, base_reg++);
30
}
31
g_string_append_printf(s,
32
"<reg name=\"ffr\" bitsize=\"%d\""
33
" regnum=\"%d\" group=\"vector\""
34
" type=\"svep\"/>",
35
- cpu->sve_max_vq * 16, base_reg++);
36
+ pred_width, base_reg++);
37
38
/* Define the vector length pseudo-register. */
39
g_string_append_printf(s,
30
--
40
--
31
2.17.0
41
2.34.1
32
42
33
43
diff view generated by jsdifflib
New patch
[PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Define svep based on the size of the predicates,
4
not the primary vector registers.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20230227213329.793795-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/gdbstub64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/gdbstub64.c
17
+++ b/target/arm/gdbstub64.c
18
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
19
/* Create the predicate vector type. */
20
g_string_append_printf(s,
21
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
22
- reg_width / 8);
23
+ pred_width / 8);
24
25
/* Define the vector registers. */
26
for (i = 0; i < 32; i++) {
27
--
28
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
[PULL 08/21] target/arm: Add name argument to output_vector_union_type
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
From: Richard Henderson <richard.henderson@linaro.org>
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
8
2
9
Add the missing initialization.
3
This will make the function usable between SVE and SME.
10
4
11
Fixes: d81ce0ef2c4f105
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230227213329.793795-9-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
10
---
18
target/arm/cpu.c | 2 ++
11
target/arm/gdbstub64.c | 28 ++++++++++++++--------------
19
1 file changed, 2 insertions(+)
12
1 file changed, 14 insertions(+), 14 deletions(-)
20
13
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
16
--- a/target/arm/gdbstub64.c
24
+++ b/target/arm/cpu.c
17
+++ b/target/arm/gdbstub64.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
18
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
26
&env->vfp.fp_status);
19
return 0;
27
set_float_detect_tininess(float_tininess_before_rounding,
20
}
28
&env->vfp.standard_fp_status);
21
29
+ set_float_detect_tininess(float_tininess_before_rounding,
22
-static void output_vector_union_type(GString *s, int reg_width)
30
+ &env->vfp.fp_status_f16);
23
+static void output_vector_union_type(GString *s, int reg_width,
31
#ifndef CONFIG_USER_ONLY
24
+ const char *name)
32
if (kvm_enabled()) {
25
{
33
kvm_arm_reset_vcpu(cpu);
26
struct TypeSize {
27
const char *gdb_type;
28
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width)
29
};
30
31
static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
32
-
33
- g_autoptr(GString) ts = g_string_new("");
34
int i, j, bits;
35
36
/* First define types and totals in a whole VL */
37
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
38
- int count = reg_width / vec_lanes[i].size;
39
- g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
40
g_string_append_printf(s,
41
- "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
42
- ts->str, vec_lanes[i].gdb_type, count);
43
+ "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
44
+ name, vec_lanes[i].sz, vec_lanes[i].suffix,
45
+ vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
46
}
47
+
48
/*
49
* Now define a union for each size group containing unsigned and
50
* signed and potentially float versions of each size from 128 to
51
* 8 bits.
52
*/
53
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
54
- g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
55
+ g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
56
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
57
if (vec_lanes[j].size == bits) {
58
- g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
59
- vec_lanes[j].suffix,
60
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",
61
+ vec_lanes[j].suffix, name,
62
vec_lanes[j].sz, vec_lanes[j].suffix);
63
}
64
}
65
g_string_append(s, "</union>");
66
}
67
+
68
/* And now the final union of unions */
69
- g_string_append(s, "<union id=\"svev\">");
70
+ g_string_append_printf(s, "<union id=\"%s\">", name);
71
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
72
- g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
73
- suf[i], suf[i]);
74
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
75
+ suf[i], name, suf[i]);
76
}
77
g_string_append(s, "</union>");
78
}
79
@@ -XXX,XX +XXX,XX @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)
80
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
81
82
/* Create the vector union type. */
83
- output_vector_union_type(s, reg_width);
84
+ output_vector_union_type(s, reg_width, "svev");
85
86
/* Create the predicate vector type. */
87
g_string_append_printf(s,
34
--
88
--
35
2.17.0
89
2.34.1
36
90
37
91
diff view generated by jsdifflib
New patch
[PULL 09/21] target/arm: Simplify iteration over bit widths
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Order suf[] by the log8 of the width.
4
Use ARRAY_SIZE instead of hard-coding 128.
5
6
This changes the order of the union definitions,
7
but retains the order of the union-of-union members.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227213329.793795-10-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/gdbstub64.c | 10 ++++++----
15
1 file changed, 6 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/gdbstub64.c
20
+++ b/target/arm/gdbstub64.c
21
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
22
{ "int8", 8, 'b', 's' },
23
};
24
25
- static const char suf[] = { 'q', 'd', 's', 'h', 'b' };
26
- int i, j, bits;
27
+ static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
28
+ int i, j;
29
30
/* First define types and totals in a whole VL */
31
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
32
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
33
* signed and potentially float versions of each size from 128 to
34
* 8 bits.
35
*/
36
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
37
+ for (i = 0; i < ARRAY_SIZE(suf); i++) {
38
+ int bits = 8 << i;
39
+
40
g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);
41
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
42
if (vec_lanes[j].size == bits) {
43
@@ -XXX,XX +XXX,XX @@ static void output_vector_union_type(GString *s, int reg_width,
44
45
/* And now the final union of unions */
46
g_string_append_printf(s, "<union id=\"%s\">", name);
47
- for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
48
+ for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
49
g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",
50
suf[i], name, suf[i]);
51
}
52
--
53
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
[PULL 10/21] target/arm: Create pauth_ptr_mask
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 binary operations.
3
Keep the logic for pauth within pauth_helper.c, and expose
4
a helper function for use with the gdbstub pac extension.
4
5
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20230227213329.793795-11-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
11
target/arm/internals.h | 10 ++++++++++
13
1 file changed, 65 insertions(+)
12
target/arm/tcg/pauth_helper.c | 26 ++++++++++++++++++++++----
13
2 files changed, 32 insertions(+), 4 deletions(-)
14
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
17
--- a/target/arm/internals.h
18
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
19
@@ -XXX,XX +XXX,XX @@ int exception_target_el(CPUARMState *env);
20
tcg_temp_free_i64(tcg_res);
20
bool arm_singlestep_active(CPUARMState *env);
21
bool arm_generate_debug_exceptions(CPUARMState *env);
22
23
+/**
24
+ * pauth_ptr_mask:
25
+ * @env: cpu context
26
+ * @ptr: selects between TTBR0 and TTBR1
27
+ * @data: selects between TBI and TBID
28
+ *
29
+ * Return a mask of the bits of @ptr that contain the authentication code.
30
+ */
31
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);
32
+
33
/* Add the cpreg definitions for debug related system registers */
34
void define_debug_regs(ARMCPU *cpu);
35
36
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/tcg/pauth_helper.c
39
+++ b/target/arm/tcg/pauth_helper.c
40
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
41
return pac | ext | ptr;
21
}
42
}
22
43
23
+/* Floating-point data-processing (2 source) - half precision */
44
-static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
45
+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)
25
+ int rd, int rn, int rm)
46
{
26
+{
47
- /* Note that bit 55 is used whether or not the regime has 2 ranges. */
27
+ TCGv_i32 tcg_op1;
48
- uint64_t extfield = sextract64(ptr, 55, 1);
28
+ TCGv_i32 tcg_op2;
49
int bot_pac_bit = 64 - param.tsz;
29
+ TCGv_i32 tcg_res;
50
int top_pac_bit = 64 - 8 * param.tbi;
30
+ TCGv_ptr fpst;
51
31
+
52
- return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
32
+ tcg_res = tcg_temp_new_i32();
53
+ return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);
33
+ fpst = get_fpstatus_ptr(true);
34
+ tcg_op1 = read_fp_hreg(s, rn);
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
54
+}
77
+
55
+
78
/* Floating point data-processing (2 source)
56
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
57
+{
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
58
+ uint64_t mask = pauth_ptr_mask_internal(param);
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
59
+
82
}
60
+ /* Note that bit 55 is used whether or not the regime has 2 ranges. */
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
61
+ if (extract64(ptr, 55, 1)) {
84
break;
62
+ return ptr | mask;
85
+ case 3:
63
+ } else {
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
64
+ return ptr & ~mask;
87
+ unallocated_encoding(s);
65
+ }
88
+ return;
66
+}
89
+ }
67
+
90
+ if (!fp_access_check(s)) {
68
+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)
91
+ return;
69
+{
92
+ }
70
+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
71
+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
94
+ break;
72
+
95
default:
73
+ return pauth_ptr_mask_internal(param);
96
unallocated_encoding(s);
74
}
97
}
75
76
static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
98
--
77
--
99
2.17.0
78
2.34.1
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
[PULL 11/21] target/arm: Implement gdbstub pauth extension
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
4
ptrace register set.
5
6
The original gdb feature consists of two masks, data and code, which are
7
used to mask out the authentication code within a pointer. Following
8
discussion with Luis Machado, add two more masks in order to support
9
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
10
11
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
16
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
17
configs/targets/aarch64-linux-user.mak | 2 +-
11
1 file changed, 14 insertions(+), 16 deletions(-)
18
configs/targets/aarch64-softmmu.mak | 2 +-
19
configs/targets/aarch64_be-linux-user.mak | 2 +-
20
target/arm/internals.h | 2 ++
21
target/arm/gdbstub.c | 5 ++++
22
target/arm/gdbstub64.c | 34 +++++++++++++++++++++++
23
gdb-xml/aarch64-pauth.xml | 15 ++++++++++
24
7 files changed, 59 insertions(+), 3 deletions(-)
25
create mode 100644 gdb-xml/aarch64-pauth.xml
12
26
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
27
diff --git a/configs/targets/aarch64-linux-user.mak b/configs/targets/aarch64-linux-user.mak
14
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
29
--- a/configs/targets/aarch64-linux-user.mak
16
+++ b/target/arm/translate-a64.c
30
+++ b/configs/targets/aarch64-linux-user.mak
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
31
@@ -XXX,XX +XXX,XX @@
18
return v;
32
TARGET_ARCH=aarch64
33
TARGET_BASE_ARCH=arm
34
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
35
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
36
TARGET_HAS_BFLT=y
37
CONFIG_SEMIHOSTING=y
38
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
39
diff --git a/configs/targets/aarch64-softmmu.mak b/configs/targets/aarch64-softmmu.mak
40
index XXXXXXX..XXXXXXX 100644
41
--- a/configs/targets/aarch64-softmmu.mak
42
+++ b/configs/targets/aarch64-softmmu.mak
43
@@ -XXX,XX +XXX,XX @@
44
TARGET_ARCH=aarch64
45
TARGET_BASE_ARCH=arm
46
TARGET_SUPPORTS_MTTCG=y
47
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml
48
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
49
TARGET_NEED_FDT=y
50
diff --git a/configs/targets/aarch64_be-linux-user.mak b/configs/targets/aarch64_be-linux-user.mak
51
index XXXXXXX..XXXXXXX 100644
52
--- a/configs/targets/aarch64_be-linux-user.mak
53
+++ b/configs/targets/aarch64_be-linux-user.mak
54
@@ -XXX,XX +XXX,XX @@
55
TARGET_ARCH=aarch64
56
TARGET_BASE_ARCH=arm
57
TARGET_BIG_ENDIAN=y
58
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
59
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml
60
TARGET_HAS_BFLT=y
61
CONFIG_SEMIHOSTING=y
62
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
63
diff --git a/target/arm/internals.h b/target/arm/internals.h
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/internals.h
66
+++ b/target/arm/internals.h
67
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
68
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
69
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
70
int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
71
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
72
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
73
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
74
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
75
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
76
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/gdbstub.c
79
+++ b/target/arm/gdbstub.c
80
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
81
aarch64_gdb_set_fpu_reg,
82
34, "aarch64-fpu.xml", 0);
83
}
84
+ if (isar_feature_aa64_pauth(&cpu->isar)) {
85
+ gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
86
+ aarch64_gdb_set_pauth_reg,
87
+ 4, "aarch64-pauth.xml", 0);
88
+ }
89
#endif
90
} else {
91
if (arm_feature(env, ARM_FEATURE_NEON)) {
92
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/gdbstub64.c
95
+++ b/target/arm/gdbstub64.c
96
@@ -XXX,XX +XXX,XX @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
97
return 0;
19
}
98
}
20
99
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
100
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
22
+{
101
+{
23
+ TCGv_i32 v = tcg_temp_new_i32();
102
+ switch (reg) {
24
+
103
+ case 0: /* pauth_dmask */
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
104
+ case 1: /* pauth_cmask */
26
+ return v;
105
+ case 2: /* pauth_dmask_high */
106
+ case 3: /* pauth_cmask_high */
107
+ /*
108
+ * Note that older versions of this feature only contained
109
+ * pauth_{d,c}mask, for use with Linux user processes, and
110
+ * thus exclusively in the low half of the address space.
111
+ *
112
+ * To support system mode, and to debug kernels, two new regs
113
+ * were added to cover the high half of the address space.
114
+ * For the purpose of pauth_ptr_mask, we can use any well-formed
115
+ * address within the address space half -- here, 0 and -1.
116
+ */
117
+ {
118
+ bool is_data = !(reg & 1);
119
+ bool is_high = reg & 2;
120
+ uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
121
+ return gdb_get_reg64(buf, mask);
122
+ }
123
+ default:
124
+ return 0;
125
+ }
27
+}
126
+}
28
+
127
+
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
128
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
30
* If SVE is not enabled, then there are only 128 bits in the vector.
129
+{
31
*/
130
+ /* All pseudo registers are read-only. */
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
131
+ return 0;
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
132
+}
133
+
134
static void output_vector_union_type(GString *s, int reg_width,
135
const char *name)
34
{
136
{
35
TCGv_ptr fpst = NULL;
137
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
138
new file mode 100644
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
139
index XXXXXXX..XXXXXXX
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
140
--- /dev/null
39
141
+++ b/gdb-xml/aarch64-pauth.xml
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
142
@@ -XXX,XX +XXX,XX @@
41
-
143
+<?xml version="1.0"?>
42
switch (opcode) {
144
+<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
43
case 0x0: /* FMOV */
145
+
44
tcg_gen_mov_i32(tcg_res, tcg_op);
146
+ Copying and distribution of this file, with or without modification,
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
147
+ are permitted in any medium without royalty provided the copyright
46
tcg_temp_free_i64(tcg_op2);
148
+ notice and this notice are preserved. -->
47
tcg_temp_free_i64(tcg_res);
149
+
48
} else {
150
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
151
+<feature name="org.gnu.gdb.aarch64.pauth">
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
152
+ <reg name="pauth_dmask" bitsize="64"/>
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
153
+ <reg name="pauth_cmask" bitsize="64"/>
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
154
+ <reg name="pauth_dmask_high" bitsize="64"/>
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
155
+ <reg name="pauth_cmask_high" bitsize="64"/>
54
156
+</feature>
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
157
+
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
79
80
if (is_scalar) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
90
--
158
--
91
2.17.0
159
2.34.1
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
[PULL 12/21] target/arm: Export arm_v7m_mrs_control
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: David Reiss <dreiss@meta.com>
2
2
3
All the hard work is already done by vfp_expand_imm, we just need to
3
Allow the function to be used outside of m_helper.c.
4
make sure we pick up the correct size.
4
Rename with an "arm_" prefix.
5
5
6
Cc: qemu-stable@nongnu.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: David Reiss <dreiss@meta.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
10
Message-id: 20230227213329.793795-13-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
11
[rth: Split out of a larger patch]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
14
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
15
target/arm/internals.h | 3 +++
17
1 file changed, 17 insertions(+), 3 deletions(-)
16
target/arm/tcg/m_helper.c | 6 +++---
17
2 files changed, 6 insertions(+), 3 deletions(-)
18
18
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
21
--- a/target/arm/internals.h
22
+++ b/target/arm/translate-a64.c
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
23
@@ -XXX,XX +XXX,XX @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
24
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
25
#endif
26
27
+/* Read the CONTROL register as the MRS instruction would. */
28
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
29
+
30
#ifdef CONFIG_USER_ONLY
31
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
32
#else
33
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/tcg/m_helper.c
36
+++ b/target/arm/tcg/m_helper.c
37
@@ -XXX,XX +XXX,XX @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
38
return xpsr_read(env) & mask;
39
}
40
41
-static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
42
+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)
24
{
43
{
25
int rd = extract32(insn, 0, 5);
44
uint32_t value = env->v7m.control[secure];
26
int imm8 = extract32(insn, 13, 8);
45
27
- int is_double = extract32(insn, 22, 2);
46
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
28
+ int type = extract32(insn, 22, 2);
47
case 0 ... 7: /* xPSR sub-fields */
29
uint64_t imm;
48
return v7m_mrs_xpsr(env, reg, 0);
30
TCGv_i64 tcg_res;
49
case 20: /* CONTROL */
31
+ TCGMemOp sz;
50
- return v7m_mrs_control(env, 0);
32
51
+ return arm_v7m_mrs_control(env, 0);
33
- if (is_double > 1) {
52
default:
34
+ switch (type) {
53
/* Unprivileged reads others as zero. */
35
+ case 0:
54
return 0;
36
+ sz = MO_32;
55
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
37
+ break;
56
case 0 ... 7: /* xPSR sub-fields */
38
+ case 1:
57
return v7m_mrs_xpsr(env, reg, el);
39
+ sz = MO_64;
58
case 20: /* CONTROL */
40
+ break;
59
- return v7m_mrs_control(env, env->v7m.secure);
41
+ case 3:
60
+ return arm_v7m_mrs_control(env, env->v7m.secure);
42
+ sz = MO_16;
61
case 0x94: /* CONTROL_NS */
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
62
/*
44
+ break;
63
* We have to handle this here because unprivileged Secure code
45
+ }
46
+ /* fallthru */
47
+ default:
48
unallocated_encoding(s);
49
return;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
52
return;
53
}
54
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
56
+ imm = vfp_expand_imm(sz, imm8);
57
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
60
--
64
--
61
2.17.0
65
2.34.1
62
66
63
67
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
[PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: David Reiss <dreiss@meta.com>
2
2
3
These were missed out from the rest of the half-precision work.
3
Allow the function to be used outside of m_helper.c.
4
Move to be outside of ifndef CONFIG_USER_ONLY block.
5
Rename from get_v7m_sp_ptr.
4
6
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: David Reiss <dreiss@meta.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
Message-id: 20230227213329.793795-14-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
[rth: Split out of a larger patch]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
16
target/arm/internals.h | 10 +++++
16
1 file changed, 25 insertions(+), 6 deletions(-)
17
target/arm/tcg/m_helper.c | 84 +++++++++++++++++++--------------------
18
2 files changed, 51 insertions(+), 43 deletions(-)
17
19
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
22
--- a/target/arm/internals.h
21
+++ b/target/arm/translate-a64.c
23
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
24
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
23
unsigned int mos, type, rm, cond, rn, rd;
25
/* Read the CONTROL register as the MRS instruction would. */
24
TCGv_i64 t_true, t_false, t_zero;
26
uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);
25
DisasCompare64 c;
27
26
+ TCGMemOp sz;
28
+/*
27
29
+ * Return a pointer to the location where we currently store the
28
mos = extract32(insn, 29, 3);
30
+ * stack pointer for the requested security state and thread mode.
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
31
+ * This pointer will become invalid if the CPU state is updated
30
+ type = extract32(insn, 22, 2);
32
+ * such that the stack pointers are switched around (eg changing
31
rm = extract32(insn, 16, 5);
33
+ * the SPSEL control bit).
32
cond = extract32(insn, 12, 4);
34
+ */
33
rn = extract32(insn, 5, 5);
35
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,
34
rd = extract32(insn, 0, 5);
36
+ bool threadmode, bool spsel);
35
37
+
36
- if (mos || type > 1) {
38
#ifdef CONFIG_USER_ONLY
37
+ if (mos) {
39
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
38
+ unallocated_encoding(s);
40
#else
39
+ return;
41
diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/tcg/m_helper.c
44
+++ b/target/arm/tcg/m_helper.c
45
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
46
arm_rebuild_hflags(env);
47
}
48
49
-static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
50
- bool spsel)
51
-{
52
- /*
53
- * Return a pointer to the location where we currently store the
54
- * stack pointer for the requested security state and thread mode.
55
- * This pointer will become invalid if the CPU state is updated
56
- * such that the stack pointers are switched around (eg changing
57
- * the SPSEL control bit).
58
- * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
59
- * Unlike that pseudocode, we require the caller to pass us in the
60
- * SPSEL control bit value; this is because we also use this
61
- * function in handling of pushing of the callee-saves registers
62
- * part of the v8M stack frame (pseudocode PushCalleeStack()),
63
- * and in the tailchain codepath the SPSEL bit comes from the exception
64
- * return magic LR value from the previous exception. The pseudocode
65
- * opencodes the stack-selection in PushCalleeStack(), but we prefer
66
- * to make this utility function generic enough to do the job.
67
- */
68
- bool want_psp = threadmode && spsel;
69
-
70
- if (secure == env->v7m.secure) {
71
- if (want_psp == v7m_using_psp(env)) {
72
- return &env->regs[13];
73
- } else {
74
- return &env->v7m.other_sp;
75
- }
76
- } else {
77
- if (want_psp) {
78
- return &env->v7m.other_ss_psp;
79
- } else {
80
- return &env->v7m.other_ss_msp;
81
- }
82
- }
83
-}
84
-
85
static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
86
uint32_t *pvec)
87
{
88
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
89
!mode;
90
91
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, priv);
92
- frame_sp_p = get_v7m_sp_ptr(env, M_REG_S, mode,
93
- lr & R_V7M_EXCRET_SPSEL_MASK);
94
+ frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,
95
+ lr & R_V7M_EXCRET_SPSEL_MASK);
96
want_psp = mode && (lr & R_V7M_EXCRET_SPSEL_MASK);
97
if (want_psp) {
98
limit = env->v7m.psplim[M_REG_S];
99
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
100
* use 'frame_sp_p' after we do something that makes it invalid.
101
*/
102
bool spsel = env->v7m.control[return_to_secure] & R_V7M_CONTROL_SPSEL_MASK;
103
- uint32_t *frame_sp_p = get_v7m_sp_ptr(env,
104
- return_to_secure,
105
- !return_to_handler,
106
- spsel);
107
+ uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,
108
+ !return_to_handler, spsel);
109
uint32_t frameptr = *frame_sp_p;
110
bool pop_ok = true;
111
ARMMMUIdx mmu_idx;
112
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
113
threadmode = !arm_v7m_is_handler_mode(env);
114
spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
115
116
- frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
117
+ frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);
118
frameptr = *frame_sp_p;
119
120
/*
121
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
122
}
123
124
#endif /* !CONFIG_USER_ONLY */
125
+
126
+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
127
+ bool spsel)
128
+{
129
+ /*
130
+ * Return a pointer to the location where we currently store the
131
+ * stack pointer for the requested security state and thread mode.
132
+ * This pointer will become invalid if the CPU state is updated
133
+ * such that the stack pointers are switched around (eg changing
134
+ * the SPSEL control bit).
135
+ * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
136
+ * Unlike that pseudocode, we require the caller to pass us in the
137
+ * SPSEL control bit value; this is because we also use this
138
+ * function in handling of pushing of the callee-saves registers
139
+ * part of the v8M stack frame (pseudocode PushCalleeStack()),
140
+ * and in the tailchain codepath the SPSEL bit comes from the exception
141
+ * return magic LR value from the previous exception. The pseudocode
142
+ * opencodes the stack-selection in PushCalleeStack(), but we prefer
143
+ * to make this utility function generic enough to do the job.
144
+ */
145
+ bool want_psp = threadmode && spsel;
146
+
147
+ if (secure == env->v7m.secure) {
148
+ if (want_psp == v7m_using_psp(env)) {
149
+ return &env->regs[13];
150
+ } else {
151
+ return &env->v7m.other_sp;
152
+ }
153
+ } else {
154
+ if (want_psp) {
155
+ return &env->v7m.other_ss_psp;
156
+ } else {
157
+ return &env->v7m.other_ss_msp;
158
+ }
40
+ }
159
+ }
41
+
160
+}
42
+ switch (type) {
43
+ case 0:
44
+ sz = MO_32;
45
+ break;
46
+ case 1:
47
+ sz = MO_64;
48
+ break;
49
+ case 3:
50
+ sz = MO_16;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
52
+ break;
53
+ }
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
60
return;
61
}
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
83
--
161
--
84
2.17.0
162
2.34.1
85
163
86
164
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
[PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
No sense in emitting code after the exception.
3
The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
4
4
go ahead and implement the other system registers as well.
5
6
Since there is significant overlap between the two, implement
7
them with common code. The only exception is the systemreg
8
view of CONTROL, which merges the banked bits as per MRS.
9
10
Signed-off-by: David Reiss <dreiss@meta.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20230227213329.793795-15-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
13
[rth: Substatial rewrite using enumerator and shared code.]
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
17
---
11
target/arm/translate-a64.c | 2 +-
18
target/arm/cpu.h | 2 +
12
1 file changed, 1 insertion(+), 1 deletion(-)
19
target/arm/gdbstub.c | 178 +++++++++++++++++++++++++++++++++++++++++++
13
20
2 files changed, 180 insertions(+)
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
24
--- a/target/arm/cpu.h
17
+++ b/target/arm/translate-a64.c
25
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
26
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
19
default:
27
20
/* all other sf/type/rmode combinations are invalid */
28
DynamicGDBXMLInfo dyn_sysreg_xml;
21
unallocated_encoding(s);
29
DynamicGDBXMLInfo dyn_svereg_xml;
22
- break;
30
+ DynamicGDBXMLInfo dyn_m_systemreg_xml;
23
+ return;
31
+ DynamicGDBXMLInfo dyn_m_secextreg_xml;
24
}
32
25
33
/* Timers used by the generic (architected) timer */
26
if (!fp_access_check(s)) {
34
QEMUTimer *gt_timer[NUM_GTIMERS];
35
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/gdbstub.c
38
+++ b/target/arm/gdbstub.c
39
@@ -XXX,XX +XXX,XX @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
40
return cpu->dyn_sysreg_xml.num;
41
}
42
43
+typedef enum {
44
+ M_SYSREG_MSP,
45
+ M_SYSREG_PSP,
46
+ M_SYSREG_PRIMASK,
47
+ M_SYSREG_CONTROL,
48
+ M_SYSREG_BASEPRI,
49
+ M_SYSREG_FAULTMASK,
50
+ M_SYSREG_MSPLIM,
51
+ M_SYSREG_PSPLIM,
52
+} MProfileSysreg;
53
+
54
+static const struct {
55
+ const char *name;
56
+ int feature;
57
+} m_sysreg_def[] = {
58
+ [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },
59
+ [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },
60
+ [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },
61
+ [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },
62
+ [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },
63
+ [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },
64
+ [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },
65
+ [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },
66
+};
67
+
68
+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)
69
+{
70
+ uint32_t *ptr;
71
+
72
+ switch (reg) {
73
+ case M_SYSREG_MSP:
74
+ ptr = arm_v7m_get_sp_ptr(env, sec, false, true);
75
+ break;
76
+ case M_SYSREG_PSP:
77
+ ptr = arm_v7m_get_sp_ptr(env, sec, true, true);
78
+ break;
79
+ case M_SYSREG_MSPLIM:
80
+ ptr = &env->v7m.msplim[sec];
81
+ break;
82
+ case M_SYSREG_PSPLIM:
83
+ ptr = &env->v7m.psplim[sec];
84
+ break;
85
+ case M_SYSREG_PRIMASK:
86
+ ptr = &env->v7m.primask[sec];
87
+ break;
88
+ case M_SYSREG_BASEPRI:
89
+ ptr = &env->v7m.basepri[sec];
90
+ break;
91
+ case M_SYSREG_FAULTMASK:
92
+ ptr = &env->v7m.faultmask[sec];
93
+ break;
94
+ case M_SYSREG_CONTROL:
95
+ ptr = &env->v7m.control[sec];
96
+ break;
97
+ default:
98
+ return NULL;
99
+ }
100
+ return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;
101
+}
102
+
103
+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,
104
+ MProfileSysreg reg, bool secure)
105
+{
106
+ uint32_t *ptr = m_sysreg_ptr(env, reg, secure);
107
+
108
+ if (ptr == NULL) {
109
+ return 0;
110
+ }
111
+ return gdb_get_reg32(buf, *ptr);
112
+}
113
+
114
+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)
115
+{
116
+ /*
117
+ * Here, we emulate MRS instruction, where CONTROL has a mix of
118
+ * banked and non-banked bits.
119
+ */
120
+ if (reg == M_SYSREG_CONTROL) {
121
+ return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));
122
+ }
123
+ return m_sysreg_get(env, buf, reg, env->v7m.secure);
124
+}
125
+
126
+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)
127
+{
128
+ return 0; /* TODO */
129
+}
130
+
131
+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)
132
+{
133
+ ARMCPU *cpu = ARM_CPU(cs);
134
+ CPUARMState *env = &cpu->env;
135
+ GString *s = g_string_new(NULL);
136
+ int base_reg = orig_base_reg;
137
+ int i;
138
+
139
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
140
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
141
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");
142
+
143
+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
144
+ if (arm_feature(env, m_sysreg_def[i].feature)) {
145
+ g_string_append_printf(s,
146
+ "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",
147
+ m_sysreg_def[i].name, base_reg++);
148
+ }
149
+ }
150
+
151
+ g_string_append_printf(s, "</feature>");
152
+ cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);
153
+ cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;
154
+
155
+ return cpu->dyn_m_systemreg_xml.num;
156
+}
157
+
158
+#ifndef CONFIG_USER_ONLY
159
+/*
160
+ * For user-only, we see the non-secure registers via m_systemreg above.
161
+ * For secext, encode the non-secure view as even and secure view as odd.
162
+ */
163
+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)
164
+{
165
+ return m_sysreg_get(env, buf, reg >> 1, reg & 1);
166
+}
167
+
168
+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)
169
+{
170
+ return 0; /* TODO */
171
+}
172
+
173
+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)
174
+{
175
+ ARMCPU *cpu = ARM_CPU(cs);
176
+ GString *s = g_string_new(NULL);
177
+ int base_reg = orig_base_reg;
178
+ int i;
179
+
180
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
181
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
182
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");
183
+
184
+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {
185
+ g_string_append_printf(s,
186
+ "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",
187
+ m_sysreg_def[i].name, base_reg++);
188
+ g_string_append_printf(s,
189
+ "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",
190
+ m_sysreg_def[i].name, base_reg++);
191
+ }
192
+
193
+ g_string_append_printf(s, "</feature>");
194
+ cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);
195
+ cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;
196
+
197
+ return cpu->dyn_m_secextreg_xml.num;
198
+}
199
+#endif
200
+
201
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
202
{
203
ARMCPU *cpu = ARM_CPU(cs);
204
@@ -XXX,XX +XXX,XX @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
205
return cpu->dyn_sysreg_xml.desc;
206
} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
207
return cpu->dyn_svereg_xml.desc;
208
+ } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {
209
+ return cpu->dyn_m_systemreg_xml.desc;
210
+#ifndef CONFIG_USER_ONLY
211
+ } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {
212
+ return cpu->dyn_m_secextreg_xml.desc;
213
+#endif
214
}
215
return NULL;
216
}
217
@@ -XXX,XX +XXX,XX @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
218
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
219
"system-registers.xml", 0);
220
221
+ if (arm_feature(env, ARM_FEATURE_M)) {
222
+ gdb_register_coprocessor(cs,
223
+ arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,
224
+ arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),
225
+ "arm-m-system.xml", 0);
226
+#ifndef CONFIG_USER_ONLY
227
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
228
+ gdb_register_coprocessor(cs,
229
+ arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,
230
+ arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),
231
+ "arm-m-secext.xml", 0);
232
+ }
233
+#endif
234
+ }
235
}
27
--
236
--
28
2.17.0
237
2.34.1
29
30
diff view generated by jsdifflib
New patch
[PULL 15/21] target/arm: Handle m-profile in arm_is_secure
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20230227225832.816605-2-richard.henderson@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
target/arm/cpu.h | 3 +++
10
1 file changed, 3 insertions(+)
11
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.h
15
+++ b/target/arm/cpu.h
16
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el3_or_mon(CPUARMState *env)
17
/* Return true if the processor is in secure state */
18
static inline bool arm_is_secure(CPUARMState *env)
19
{
20
+ if (arm_feature(env, ARM_FEATURE_M)) {
21
+ return env->v7m.secure;
22
+ }
23
if (arm_is_el3_or_mon(env)) {
24
return true;
25
}
26
--
27
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
[PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
M-profile doesn't have HCR_EL2. While we could test features
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
before each call, zero is a generally safe return value to
5
disable the code in the caller. This test is required to
6
avoid an assert in arm_is_secure_below_el3.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20230227225832.816605-3-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/helper.h | 6 +++
13
target/arm/helper.c | 3 +++
11
target/arm/helper.c | 38 ++++++++++++++-
14
1 file changed, 3 insertions(+)
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
15
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
18
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
19
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
20
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
44
#undef VFP_CONV_FIX_A64
21
45
22
uint64_t arm_hcr_el2_eff(CPUARMState *env)
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
23
{
47
- * Therefore we convert to f64 (which does not round), scale,
24
+ if (arm_feature(env, ARM_FEATURE_M)) {
48
- * and then convert f64 to f16 (which may round).
25
+ return 0;
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
26
+ }
50
+ * vice versa for conversion to integer.
27
return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
51
+ *
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
53
+ * For 64-bit integers, any integer that would cause rounding will also
54
+ * overflow to f16 infinity, so there is no double rounding problem.
55
*/
56
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
28
}
61
29
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
65
+}
66
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
68
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
70
+}
71
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
30
--
266
2.17.0
31
2.34.1
267
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
[PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines
1
In float-to-integer conversion, if the floating point input
1
From: Richard Henderson <richard.henderson@linaro.org>
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
2
9
Fix the boundary case to take the right half of the if()
3
In several places we use arm_is_secure_below_el3 and
10
statements.
4
arm_is_el3_or_mon separately from arm_is_secure.
5
These functions make no sense for m-profile, and
6
would indicate prior incorrect feature testing.
11
7
12
This fixes a regression from 2.11 introduced by the softfloat
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
refactoring.
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20230227225832.816605-4-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 5 ++++-
15
1 file changed, 4 insertions(+), 1 deletion(-)
14
16
15
Cc: qemu-stable@nongnu.org
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
20
---
21
fpu/softfloat.c | 4 ++--
22
1 file changed, 2 insertions(+), 2 deletions(-)
23
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
25
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
19
--- a/target/arm/cpu.h
27
+++ b/fpu/softfloat.c
20
+++ b/target/arm/cpu.h
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
21
@@ -XXX,XX +XXX,XX @@ static inline int arm_feature(CPUARMState *env, int feature)
29
r = UINT64_MAX;
22
void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
30
}
23
31
if (p.sign) {
24
#if !defined(CONFIG_USER_ONLY)
32
- if (r < -(uint64_t) min) {
25
-/* Return true if exception levels below EL3 are in secure state,
33
+ if (r <= -(uint64_t) min) {
26
+/*
34
return -r;
27
+ * Return true if exception levels below EL3 are in secure state,
35
} else {
28
* or would be following an exception return to that level.
36
s->float_exception_flags = orig_flags | float_flag_invalid;
29
* Unlike arm_is_secure() (which is always a question about the
37
return min;
30
* _current_ state of the CPU) this doesn't care about the current
38
}
31
@@ -XXX,XX +XXX,XX @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
39
} else {
32
*/
40
- if (r < max) {
33
static inline bool arm_is_secure_below_el3(CPUARMState *env)
41
+ if (r <= max) {
34
{
42
return r;
35
+ assert(!arm_feature(env, ARM_FEATURE_M));
43
} else {
36
if (arm_feature(env, ARM_FEATURE_EL3)) {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
37
return !(env->cp15.scr_el3 & SCR_NS);
38
} else {
39
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure_below_el3(CPUARMState *env)
40
/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
41
static inline bool arm_is_el3_or_mon(CPUARMState *env)
42
{
43
+ assert(!arm_feature(env, ARM_FEATURE_M));
44
if (arm_feature(env, ARM_FEATURE_EL3)) {
45
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
46
/* CPU currently in AArch64 state and EL3 */
45
--
47
--
46
2.17.0
48
2.34.1
47
49
48
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
[PULL 18/21] target/arm: Rewrite check_s2_mmu_setup
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
Integrate neighboring code from get_phys_addr_lpae which computed
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
starting level, as it is easier to validate when doing both at the
5
same time. Mirror the checks at the start of AArch{64,32}.S2Walk,
6
especially S2InvalidSL and S2InconsistentSL.
7
8
This reverts 49ba115bb74, which was incorrect -- there is nothing
9
in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the
10
pseudocode is consistent in referencing PAMax.
11
12
Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup")
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20230227225832.816605-5-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
17
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
18
target/arm/ptw.c | 173 ++++++++++++++++++++++++++---------------------
11
1 file changed, 15 insertions(+), 2 deletions(-)
19
1 file changed, 97 insertions(+), 76 deletions(-)
12
20
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
14
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
23
--- a/target/arm/ptw.c
16
+++ b/target/arm/translate-a64.c
24
+++ b/target/arm/ptw.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
25
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
18
bool sf = extract32(insn, 31, 1);
26
* check_s2_mmu_setup
19
bool itof;
27
* @cpu: ARMCPU
20
28
* @is_aa64: True if the translation regime is in AArch64 state
21
- if (sbit || (type > 1)
29
- * @startlevel: Suggested starting level
22
- || (!sf && scale < 32)) {
30
- * @inputsize: Bitsize of IPAs
23
+ if (sbit || (!sf && scale < 32)) {
31
+ * @tcr: VTCR_EL2 or VSTCR_EL2
24
+ unallocated_encoding(s);
32
+ * @ds: Effective value of TCR.DS.
25
+ return;
33
+ * @iasize: Bitsize of IPAs
34
* @stride: Page-table stride (See the ARM ARM)
35
*
36
- * Returns true if the suggested S2 translation parameters are OK and
37
- * false otherwise.
38
+ * Decode the starting level of the S2 lookup, returning INT_MIN if
39
+ * the configuration is invalid.
40
*/
41
-static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
42
- int inputsize, int stride, int outputsize)
43
+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,
44
+ bool ds, int iasize, int stride)
45
{
46
- const int grainsize = stride + 3;
47
- int startsizecheck;
48
-
49
- /*
50
- * Negative levels are usually not allowed...
51
- * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
52
- * begins with level -1. Note that previous feature tests will have
53
- * eliminated this combination if it is not enabled.
54
- */
55
- if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
56
- return false;
57
- }
58
-
59
- startsizecheck = inputsize - ((3 - level) * stride + grainsize);
60
- if (startsizecheck < 1 || startsizecheck > stride + 4) {
61
- return false;
62
- }
63
+ int sl0, sl2, startlevel, granulebits, levels;
64
+ int s1_min_iasize, s1_max_iasize;
65
66
+ sl0 = extract32(tcr, 6, 2);
67
if (is_aa64) {
68
+ /*
69
+ * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of
70
+ * get_phys_addr_lpae, that used aa64_va_parameters which apply
71
+ * to aarch64. If Stage1 is aarch32, the min_txsz is larger.
72
+ * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to
73
+ * inputsize is 64 - 24 = 40.
74
+ */
75
+ if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {
76
+ goto fail;
77
+ }
78
+
79
+ /*
80
+ * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,
81
+ * so interleave AArch64.S2StartLevel.
82
+ */
83
switch (stride) {
84
- case 13: /* 64KB Pages. */
85
- if (level == 0 || (level == 1 && outputsize <= 42)) {
86
- return false;
87
+ case 9: /* 4KB */
88
+ /* SL2 is RES0 unless DS=1 & 4KB granule. */
89
+ sl2 = extract64(tcr, 33, 1);
90
+ if (ds && sl2) {
91
+ if (sl0 != 0) {
92
+ goto fail;
93
+ }
94
+ startlevel = -1;
95
+ } else {
96
+ startlevel = 2 - sl0;
97
+ switch (sl0) {
98
+ case 2:
99
+ if (arm_pamax(cpu) < 44) {
100
+ goto fail;
101
+ }
102
+ break;
103
+ case 3:
104
+ if (!cpu_isar_feature(aa64_st, cpu)) {
105
+ goto fail;
106
+ }
107
+ startlevel = 3;
108
+ break;
109
+ }
110
}
111
break;
112
- case 11: /* 16KB Pages. */
113
- if (level == 0 || (level == 1 && outputsize <= 40)) {
114
- return false;
115
+ case 11: /* 16KB */
116
+ switch (sl0) {
117
+ case 2:
118
+ if (arm_pamax(cpu) < 42) {
119
+ goto fail;
120
+ }
121
+ break;
122
+ case 3:
123
+ if (!ds) {
124
+ goto fail;
125
+ }
126
+ break;
127
}
128
+ startlevel = 3 - sl0;
129
break;
130
- case 9: /* 4KB Pages. */
131
- if (level == 0 && outputsize <= 42) {
132
- return false;
133
+ case 13: /* 64KB */
134
+ switch (sl0) {
135
+ case 2:
136
+ if (arm_pamax(cpu) < 44) {
137
+ goto fail;
138
+ }
139
+ break;
140
+ case 3:
141
+ goto fail;
142
}
143
+ startlevel = 3 - sl0;
144
break;
145
default:
146
g_assert_not_reached();
147
}
148
-
149
- /* Inputsize checks. */
150
- if (inputsize > outputsize &&
151
- (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
152
- /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
153
- return false;
154
- }
155
} else {
156
- /* AArch32 only supports 4KB pages. Assert on that. */
157
+ /*
158
+ * Things are simpler for AArch32 EL2, with only 4k pages.
159
+ * There is no separate S2InvalidSL function, but AArch32.S2Walk
160
+ * begins with walkparms.sl0 in {'1x'}.
161
+ */
162
assert(stride == 9);
163
-
164
- if (level == 0) {
165
- return false;
166
+ if (sl0 >= 2) {
167
+ goto fail;
168
}
169
+ startlevel = 2 - sl0;
170
}
171
- return true;
172
+
173
+ /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */
174
+ levels = 3 - startlevel;
175
+ granulebits = stride + 3;
176
+
177
+ s1_min_iasize = levels * stride + granulebits + 1;
178
+ s1_max_iasize = s1_min_iasize + (stride - 1) + 4;
179
+
180
+ if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {
181
+ return startlevel;
26
+ }
182
+ }
27
+
183
+
28
+ switch (type) {
184
+ fail:
29
+ case 0: /* float32 */
185
+ return INT_MIN;
30
+ case 1: /* float64 */
186
}
31
+ break;
187
32
+ case 3: /* float16 */
188
/**
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
189
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
34
+ break;
190
*/
35
+ }
191
level = 4 - (inputsize - 4) / stride;
36
+ /* fallthru */
192
} else {
37
+ default:
193
- /*
38
unallocated_encoding(s);
194
- * For stage 2 translations the starting level is specified by the
39
return;
195
- * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
40
}
196
- */
197
- uint32_t sl0 = extract32(tcr, 6, 2);
198
- uint32_t sl2 = extract64(tcr, 33, 1);
199
- int32_t startlevel;
200
- bool ok;
201
-
202
- /* SL2 is RES0 unless DS=1 & 4kb granule. */
203
- if (param.ds && stride == 9 && sl2) {
204
- if (sl0 != 0) {
205
- level = 0;
206
- goto do_translation_fault;
207
- }
208
- startlevel = -1;
209
- } else if (!aarch64 || stride == 9) {
210
- /* AArch32 or 4KB pages */
211
- startlevel = 2 - sl0;
212
-
213
- if (cpu_isar_feature(aa64_st, cpu)) {
214
- startlevel &= 3;
215
- }
216
- } else {
217
- /* 16KB or 64KB pages */
218
- startlevel = 3 - sl0;
219
- }
220
-
221
- /* Check that the starting level is valid. */
222
- ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
223
- inputsize, stride, outputsize);
224
- if (!ok) {
225
+ int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,
226
+ inputsize, stride);
227
+ if (startlevel == INT_MIN) {
228
+ level = 0;
229
goto do_translation_fault;
230
}
231
level = startlevel;
41
--
232
--
42
2.17.0
233
2.34.1
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
[PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Ard Biesheuvel <ardb@kernel.org>
2
2
3
We missed all of the scalar fp16 fma operations.
3
Fedora 39 will ship its arm64 kernels in the new generic EFI zboot
4
format, using gzip compression for the payload.
4
5
5
Cc: qemu-stable@nongnu.org
6
For doing EFI boot in QEMU, this is completely transparent, as the
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
firmware or bootloader will take care of this. However, for direct
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
kernel boot without firmware, we will lose the ability to boot such
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
distro kernels unless we deal with the new format directly.
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
10
11
EFI zboot images contain metadata in the header regarding the placement
12
of the compressed payload inside the image, and the type of compression
13
used. This means we can wire up the existing gzip support without too
14
much hassle, by parsing the header and grabbing the payload from inside
15
the loaded zboot image.
16
17
Cc: Peter Maydell <peter.maydell@linaro.org>
18
Cc: Alex Bennée <alex.bennee@linaro.org>
19
Cc: Richard Henderson <richard.henderson@linaro.org>
20
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
22
Message-id: 20230303160109.3626966-1-ardb@kernel.org
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
[PMM: tweaked comment formatting, fixed checkpatch nits]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
26
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
27
include/hw/loader.h | 19 ++++++++++
13
1 file changed, 48 insertions(+)
28
hw/arm/boot.c | 6 +++
29
hw/core/loader.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
30
3 files changed, 116 insertions(+)
14
31
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
diff --git a/include/hw/loader.h b/include/hw/loader.h
16
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
34
--- a/include/hw/loader.h
18
+++ b/target/arm/translate-a64.c
35
+++ b/include/hw/loader.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
36
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped_buffer(const char *filename, uint64_t max_sz,
20
tcg_temp_free_i64(tcg_res);
37
uint8_t **buffer);
38
ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz);
39
40
+/**
41
+ * unpack_efi_zboot_image:
42
+ * @buffer: pointer to a variable holding the address of a buffer containing the
43
+ * image
44
+ * @size: pointer to a variable holding the size of the buffer
45
+ *
46
+ * Check whether the buffer contains a EFI zboot image, and if it does, extract
47
+ * the compressed payload and decompress it into a new buffer. If successful,
48
+ * the old buffer is freed, and the *buffer and size variables pointed to by the
49
+ * function arguments are updated to refer to the newly populated buffer.
50
+ *
51
+ * Returns 0 if the image could not be identified as a EFI zboot image.
52
+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but
53
+ * unpacking failed for any reason.
54
+ * Returns the size of the decompressed payload if decompression was performed
55
+ * successfully.
56
+ */
57
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);
58
+
59
#define ELF_LOAD_FAILED -1
60
#define ELF_LOAD_NOT_ELF -2
61
#define ELF_LOAD_WRONG_ARCH -3
62
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/hw/arm/boot.c
65
+++ b/hw/arm/boot.c
66
@@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
67
return -1;
68
}
69
size = len;
70
+
71
+ /* Unpack the image if it is a EFI zboot image */
72
+ if (unpack_efi_zboot_image(&buffer, &size) < 0) {
73
+ g_free(buffer);
74
+ return -1;
75
+ }
76
}
77
78
/* check the arm64 magic header value -- very old kernels may not have it */
79
diff --git a/hw/core/loader.c b/hw/core/loader.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/core/loader.c
82
+++ b/hw/core/loader.c
83
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz)
84
return bytes;
21
}
85
}
22
86
23
+/* Floating-point data-processing (3 source) - half precision */
87
+/* The PE/COFF MS-DOS stub magic number */
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
88
+#define EFI_PE_MSDOS_MAGIC "MZ"
25
+ int rd, int rn, int rm, int ra)
89
+
90
+/*
91
+ * The Linux header magic number for a EFI PE/COFF
92
+ * image targetting an unspecified architecture.
93
+ */
94
+#define EFI_PE_LINUX_MAGIC "\xcd\x23\x82\x81"
95
+
96
+/*
97
+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are
98
+ * self-decompressing executables when loaded via EFI. The compressed payload
99
+ * can also be extracted from the image and decompressed by a non-EFI loader.
100
+ *
101
+ * The de facto specification for this format is at the following URL:
102
+ *
103
+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S
104
+ *
105
+ * This definition is based on Linux upstream commit 29636a5ce87beba.
106
+ */
107
+struct linux_efi_zboot_header {
108
+ uint8_t msdos_magic[2]; /* PE/COFF 'MZ' magic number */
109
+ uint8_t reserved0[2];
110
+ uint8_t zimg[4]; /* "zimg" for Linux EFI zboot images */
111
+ uint32_t payload_offset; /* LE offset to compressed payload */
112
+ uint32_t payload_size; /* LE size of the compressed payload */
113
+ uint8_t reserved1[8];
114
+ char compression_type[32]; /* Compression type, NUL terminated */
115
+ uint8_t linux_magic[4]; /* Linux header magic */
116
+ uint32_t pe_header_offset; /* LE offset to the PE header */
117
+};
118
+
119
+/*
120
+ * Check whether *buffer points to a Linux EFI zboot image in memory.
121
+ *
122
+ * If it does, attempt to decompress it to a new buffer, and free the old one.
123
+ * If any of this fails, return an error to the caller.
124
+ *
125
+ * If the image is not a Linux EFI zboot image, do nothing and return success.
126
+ */
127
+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)
26
+{
128
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
129
+ const struct linux_efi_zboot_header *header;
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
130
+ uint8_t *data = NULL;
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
131
+ int ploff, plsize;
132
+ ssize_t bytes;
30
+
133
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
134
+ /* ignore if this is too small to be a EFI zboot image */
32
+ tcg_op2 = read_fp_hreg(s, rm);
135
+ if (*size < sizeof(*header)) {
33
+ tcg_op3 = read_fp_hreg(s, ra);
136
+ return 0;
34
+
35
+ /* These are fused multiply-add, and must be done as one
36
+ * floating point operation with no rounding between the
37
+ * multiplication and addition steps.
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
42
+ if (o1 == true) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
44
+ }
137
+ }
45
+
138
+
46
+ if (o0 != o1) {
139
+ header = (struct linux_efi_zboot_header *)*buffer;
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
140
+
141
+ /* ignore if this is not a Linux EFI zboot image */
142
+ if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||
143
+ memcmp(&header->zimg, "zimg", 4) != 0 ||
144
+ memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {
145
+ return 0;
48
+ }
146
+ }
49
+
147
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
148
+ if (strcmp(header->compression_type, "gzip") != 0) {
149
+ fprintf(stderr,
150
+ "unable to handle EFI zboot image with \"%.*s\" compression\n",
151
+ (int)sizeof(header->compression_type) - 1,
152
+ header->compression_type);
153
+ return -1;
154
+ }
51
+
155
+
52
+ write_fp_sreg(s, rd, tcg_res);
156
+ ploff = ldl_le_p(&header->payload_offset);
157
+ plsize = ldl_le_p(&header->payload_size);
53
+
158
+
54
+ tcg_temp_free_ptr(fpst);
159
+ if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {
55
+ tcg_temp_free_i32(tcg_op1);
160
+ fprintf(stderr, "unable to handle corrupt EFI zboot image\n");
56
+ tcg_temp_free_i32(tcg_op2);
161
+ return -1;
57
+ tcg_temp_free_i32(tcg_op3);
162
+ }
58
+ tcg_temp_free_i32(tcg_res);
163
+
164
+ data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);
165
+ bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);
166
+ if (bytes < 0) {
167
+ fprintf(stderr, "failed to decompress EFI zboot image\n");
168
+ g_free(data);
169
+ return -1;
170
+ }
171
+
172
+ g_free(*buffer);
173
+ *buffer = g_realloc(data, bytes);
174
+ *size = bytes;
175
+ return bytes;
59
+}
176
+}
60
+
177
+
61
/* Floating point data-processing (3 source)
178
/*
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
179
* Functions for reboot-persistent memory regions.
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
180
* - used for vga bios and option roms.
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
65
}
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
67
break;
68
+ case 3:
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
+ unallocated_encoding(s);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
80
}
81
--
181
--
82
2.17.0
182
2.34.1
83
183
84
184
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
[PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: qianfan Zhao <qianfanguijin@163.com>
2
2
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
3
TWI_CNTR_INT_FLAG is W1C(write 1 to clear and write 0 has non-effect)
4
later on so we might as well mirror that.
4
register on SUN6i based SoCs, we should lower interrupt when the guest
5
set this bit.
5
6
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
The linux kernel will hang in irq handler(mv64xxx_i2c_intr) if no
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
device connected on the i2c bus, next is the trace log:
9
10
allwinner_i2c_write write CNTR(0x0c): 0xc4 A_ACK BUS_EN INT_EN
11
allwinner_i2c_write write CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
12
allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN
13
allwinner_i2c_read read STAT(0x10): 0x20 STAT_M_ADDR_WR_NACK
14
allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
15
allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
16
allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
17
allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE
18
allwinner_i2c_write write CNTR(0x0c): 0x54 A_ACK M_STP BUS_EN
19
allwinner_i2c_write write CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
20
allwinner_i2c_read read CNTR(0x0c): 0x4c A_ACK INT_FLAG BUS_EN
21
allwinner_i2c_read read STAT(0x10): 0xf8 STAT_IDLE
22
...
23
24
Fix it.
25
26
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
27
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
28
Tested-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
31
---
11
fpu/softfloat.c | 2 +-
32
include/hw/i2c/allwinner-i2c.h | 6 ++++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
33
hw/i2c/allwinner-i2c.c | 26 ++++++++++++++++++++++++--
34
2 files changed, 30 insertions(+), 2 deletions(-)
13
35
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
36
diff --git a/include/hw/i2c/allwinner-i2c.h b/include/hw/i2c/allwinner-i2c.h
15
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
38
--- a/include/hw/i2c/allwinner-i2c.h
17
+++ b/fpu/softfloat.c
39
+++ b/include/hw/i2c/allwinner-i2c.h
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
40
@@ -XXX,XX +XXX,XX @@
19
41
#include "qom/object.h"
20
static FloatParts int_to_float(int64_t a, float_status *status)
42
43
#define TYPE_AW_I2C "allwinner.i2c"
44
+
45
+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
46
+#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i"
47
+
48
OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
49
50
#define AW_I2C_MEM_SIZE 0x24
51
@@ -XXX,XX +XXX,XX @@ struct AWI2CState {
52
uint8_t srst;
53
uint8_t efr;
54
uint8_t lcr;
55
+
56
+ bool irq_clear_inverted;
57
};
58
59
#endif /* ALLWINNER_I2C_H */
60
diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/i2c/allwinner-i2c.c
63
+++ b/hw/i2c/allwinner-i2c.c
64
@@ -XXX,XX +XXX,XX @@ static void allwinner_i2c_write(void *opaque, hwaddr offset,
65
s->stat = STAT_FROM_STA(STAT_IDLE);
66
s->cntr &= ~TWI_CNTR_M_STP;
67
}
68
- if ((s->cntr & TWI_CNTR_INT_FLAG) == 0) {
69
- /* Interrupt flag cleared */
70
+
71
+ if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {
72
+ /* Write 0 to clear this flag */
73
+ qemu_irq_lower(s->irq);
74
+ } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {
75
+ /* Write 1 to clear this flag */
76
+ s->cntr &= ~TWI_CNTR_INT_FLAG;
77
qemu_irq_lower(s->irq);
78
}
79
+
80
if ((s->cntr & TWI_CNTR_A_ACK) == 0) {
81
if (STAT_TO_STA(s->stat) == STAT_M_DATA_RX_ACK) {
82
s->stat = STAT_FROM_STA(STAT_M_DATA_RX_NACK);
83
@@ -XXX,XX +XXX,XX @@ static const TypeInfo allwinner_i2c_type_info = {
84
.class_init = allwinner_i2c_class_init,
85
};
86
87
+static void allwinner_i2c_sun6i_init(Object *obj)
88
+{
89
+ AWI2CState *s = AW_I2C(obj);
90
+
91
+ s->irq_clear_inverted = true;
92
+}
93
+
94
+static const TypeInfo allwinner_i2c_sun6i_type_info = {
95
+ .name = TYPE_AW_I2C_SUN6I,
96
+ .parent = TYPE_SYS_BUS_DEVICE,
97
+ .instance_size = sizeof(AWI2CState),
98
+ .instance_init = allwinner_i2c_sun6i_init,
99
+ .class_init = allwinner_i2c_class_init,
100
+};
101
+
102
static void allwinner_i2c_register_types(void)
21
{
103
{
22
- FloatParts r;
104
type_register_static(&allwinner_i2c_type_info);
23
+ FloatParts r = {};
105
+ type_register_static(&allwinner_i2c_sun6i_type_info);
24
if (a == 0) {
106
}
25
r.cls = float_class_zero;
107
26
r.sign = false;
108
type_init(allwinner_i2c_register_types)
27
--
109
--
28
2.17.0
110
2.34.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
[PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: qianfan Zhao <qianfanguijin@163.com>
2
2
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
3
Allwinner h3 has 4 twi(i2c) devices named twi0, twi1, twi2 and r_twi.
4
The registers are compatible with TYPE_AW_I2C_SUN6I, write 1 to clear
5
control register's INT_FLAG bit.
4
6
5
The block length is predefined to 512 bits
7
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
6
8
Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
7
and "4.10.2 SD Status":
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
11
---
21
hw/sd/sd.c | 2 +-
12
include/hw/arm/allwinner-h3.h | 6 ++++++
22
1 file changed, 1 insertion(+), 1 deletion(-)
13
hw/arm/allwinner-h3.c | 29 +++++++++++++++++++++++++----
14
2 files changed, 31 insertions(+), 4 deletions(-)
23
15
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
16
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
25
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
18
--- a/include/hw/arm/allwinner-h3.h
27
+++ b/hw/sd/sd.c
19
+++ b/include/hw/arm/allwinner-h3.h
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
20
@@ -XXX,XX +XXX,XX @@ enum {
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
21
AW_H3_DEV_UART3,
30
}
22
AW_H3_DEV_EMAC,
31
memset(&sd->data[17], 0, 47);
23
AW_H3_DEV_TWI0,
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
24
+ AW_H3_DEV_TWI1,
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
25
+ AW_H3_DEV_TWI2,
26
AW_H3_DEV_DRAMCOM,
27
AW_H3_DEV_DRAMCTL,
28
AW_H3_DEV_DRAMPHY,
29
@@ -XXX,XX +XXX,XX @@ enum {
30
AW_H3_DEV_GIC_VCPU,
31
AW_H3_DEV_RTC,
32
AW_H3_DEV_CPUCFG,
33
+ AW_H3_DEV_R_TWI,
34
AW_H3_DEV_SDRAM
35
};
36
37
@@ -XXX,XX +XXX,XX @@ struct AwH3State {
38
AwSidState sid;
39
AwSdHostState mmc0;
40
AWI2CState i2c0;
41
+ AWI2CState i2c1;
42
+ AWI2CState i2c2;
43
+ AWI2CState r_twi;
44
AwSun8iEmacState emac;
45
AwRtcState rtc;
46
GICState gic;
47
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/allwinner-h3.c
50
+++ b/hw/arm/allwinner-h3.c
51
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
52
[AW_H3_DEV_UART2] = 0x01c28800,
53
[AW_H3_DEV_UART3] = 0x01c28c00,
54
[AW_H3_DEV_TWI0] = 0x01c2ac00,
55
+ [AW_H3_DEV_TWI1] = 0x01c2b000,
56
+ [AW_H3_DEV_TWI2] = 0x01c2b400,
57
[AW_H3_DEV_EMAC] = 0x01c30000,
58
[AW_H3_DEV_DRAMCOM] = 0x01c62000,
59
[AW_H3_DEV_DRAMCTL] = 0x01c63000,
60
@@ -XXX,XX +XXX,XX @@ const hwaddr allwinner_h3_memmap[] = {
61
[AW_H3_DEV_GIC_VCPU] = 0x01c86000,
62
[AW_H3_DEV_RTC] = 0x01f00000,
63
[AW_H3_DEV_CPUCFG] = 0x01f01c00,
64
+ [AW_H3_DEV_R_TWI] = 0x01f02400,
65
[AW_H3_DEV_SDRAM] = 0x40000000
66
};
67
68
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
69
{ "uart1", 0x01c28400, 1 * KiB },
70
{ "uart2", 0x01c28800, 1 * KiB },
71
{ "uart3", 0x01c28c00, 1 * KiB },
72
- { "twi1", 0x01c2b000, 1 * KiB },
73
- { "twi2", 0x01c2b400, 1 * KiB },
74
{ "scr", 0x01c2c400, 1 * KiB },
75
{ "gpu", 0x01c40000, 64 * KiB },
76
{ "hstmr", 0x01c60000, 4 * KiB },
77
@@ -XXX,XX +XXX,XX @@ struct AwH3Unimplemented {
78
{ "r_prcm", 0x01f01400, 1 * KiB },
79
{ "r_twd", 0x01f01800, 1 * KiB },
80
{ "r_cir-rx", 0x01f02000, 1 * KiB },
81
- { "r_twi", 0x01f02400, 1 * KiB },
82
{ "r_uart", 0x01f02800, 1 * KiB },
83
{ "r_pio", 0x01f02c00, 1 * KiB },
84
{ "r_pwm", 0x01f03800, 1 * KiB },
85
@@ -XXX,XX +XXX,XX @@ enum {
86
AW_H3_GIC_SPI_UART2 = 2,
87
AW_H3_GIC_SPI_UART3 = 3,
88
AW_H3_GIC_SPI_TWI0 = 6,
89
+ AW_H3_GIC_SPI_TWI1 = 7,
90
+ AW_H3_GIC_SPI_TWI2 = 8,
91
AW_H3_GIC_SPI_TIMER0 = 18,
92
AW_H3_GIC_SPI_TIMER1 = 19,
93
+ AW_H3_GIC_SPI_R_TWI = 44,
94
AW_H3_GIC_SPI_MMC0 = 60,
95
AW_H3_GIC_SPI_EHCI0 = 72,
96
AW_H3_GIC_SPI_OHCI0 = 73,
97
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_init(Object *obj)
98
99
object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
100
101
- object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C);
102
+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
103
+ object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I);
104
+ object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I);
105
+ object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);
34
}
106
}
35
107
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
108
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
109
@@ -XXX,XX +XXX,XX @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
110
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c0), 0,
111
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI0));
112
113
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);
114
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);
115
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,
116
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));
117
+
118
+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);
119
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);
120
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,
121
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));
122
+
123
+ sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);
124
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);
125
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,
126
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));
127
+
128
/* Unimplemented devices */
129
for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
130
create_unimplemented_device(unimplemented[i].device_name,
37
--
131
--
38
2.17.0
132
2.34.1
39
40
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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