[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/29] target-arm queue
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
1
First arm pullreq of the 8.0 series...
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2
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
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The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:
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5
Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)
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6
5
are available in the Git repository at:
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are available in the Git repository at:
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8
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215
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10
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
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for you to fetch changes up to 4f3ebdc33618e7c163f769047859d6f34373e3af:
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12
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tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
13
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 11:18:20 +0000)
12
14
13
----------------------------------------------------------------
15
----------------------------------------------------------------
14
target-arm queue:
16
target-arm queue:
15
* Fix coverity nit in int_to_float code
17
* hw/arm/virt: Add properties to allow more granular
16
* Don't set Invalid for float-to-int(MAXINT)
18
configuration of use of highmem space
17
* Fix fp_status_f16 tininess before rounding
19
* target/arm: Add Cortex-A55 CPU
18
* Add various missing insns from the v8.2-FP16 extension
20
* hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
19
* Fix sqrt_f16 exception raising
21
* Implement FEAT_EVT
20
* sdcard: Correct CRC16 offset in sd_function_switch()
22
* Some 3-phase-reset conversions for Arm GIC, SMMU
21
* tcg: Optionally log FPU state in TCG -d cpu logging
23
* hw/arm/boot: set initrd with #address-cells type in fdt
24
* align user-mode exposed ID registers with Linux
25
* hw/misc: Move some arm-related files from specific_ss into softmmu_ss
26
* Restrict arm_cpu_exec_interrupt() to TCG accelerator
22
27
23
----------------------------------------------------------------
28
----------------------------------------------------------------
24
Alex Bennée (5):
29
Gavin Shan (7):
25
fpu/softfloat: int_to_float ensure r fully initialised
30
hw/arm/virt: Introduce virt_set_high_memmap() helper
26
target/arm: Implement FCMP for fp16
31
hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
27
target/arm: Implement FCSEL for fp16
32
hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
28
target/arm: Implement FMOV (immediate) for fp16
33
hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
29
target/arm: Fix sqrt_f16 exception raising
34
hw/arm/virt: Improve high memory region address assignment
35
hw/arm/virt: Add 'compact-highmem' property
36
hw/arm/virt: Add properties to disable high memory regions
30
37
31
Peter Maydell (3):
38
Luke Starrett (1):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
39
hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
33
target/arm: Fix fp_status_f16 tininess before rounding
40
34
tcg: Optionally log FPU state in TCG -d cpu logging
41
Mihai Carabas (1):
42
hw/arm/virt: build SMBIOS 19 table
43
44
Peter Maydell (15):
45
target/arm: Allow relevant HCR bits to be written for FEAT_EVT
46
target/arm: Implement HCR_EL2.TTLBIS traps
47
target/arm: Implement HCR_EL2.TTLBOS traps
48
target/arm: Implement HCR_EL2.TICAB,TOCU traps
49
target/arm: Implement HCR_EL2.TID4 traps
50
target/arm: Report FEAT_EVT for TCG '-cpu max'
51
hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
52
hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
53
hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
54
hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
55
hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
56
hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
57
hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
58
hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
59
hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
35
60
36
Philippe Mathieu-Daudé (1):
61
Philippe Mathieu-Daudé (1):
37
sdcard: Correct CRC16 offset in sd_function_switch()
62
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
38
63
39
Richard Henderson (7):
64
Schspa Shi (1):
40
target/arm: Implement FMOV (general) for fp16
65
hw/arm/boot: set initrd with #address-cells type in fdt
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
47
66
48
include/qemu/log.h | 1 +
67
Thomas Huth (1):
49
target/arm/helper-a64.h | 2 +
68
hw/misc: Move some arm-related files from specific_ss into softmmu_ss
50
target/arm/helper.h | 6 +
51
accel/tcg/cpu-exec.c | 9 +-
52
fpu/softfloat.c | 6 +-
53
hw/sd/sd.c | 2 +-
54
target/arm/cpu.c | 2 +
55
target/arm/helper-a64.c | 10 ++
56
target/arm/helper.c | 38 +++-
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
58
util/log.c | 2 +
59
11 files changed, 428 insertions(+), 71 deletions(-)
60
69
70
Timofey Kutergin (1):
71
target/arm: Add Cortex-A55 CPU
72
73
Zhuojia Shen (1):
74
target/arm: align exposed ID registers with Linux
75
76
docs/system/arm/emulation.rst | 1 +
77
docs/system/arm/virt.rst | 18 +++
78
include/hw/arm/smmuv3.h | 2 +-
79
include/hw/arm/virt.h | 2 +
80
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +-
81
target/arm/cpu.h | 30 +++++
82
target/arm/kvm-consts.h | 8 +-
83
hw/arm/boot.c | 10 +-
84
hw/arm/smmu-common.c | 7 +-
85
hw/arm/smmuv3.c | 12 +-
86
hw/arm/virt.c | 202 +++++++++++++++++++++++-----
87
hw/intc/arm_gic_common.c | 7 +-
88
hw/intc/arm_gic_kvm.c | 14 +-
89
hw/intc/arm_gicv3_common.c | 7 +-
90
hw/intc/arm_gicv3_dist.c | 4 +-
91
hw/intc/arm_gicv3_its.c | 14 +-
92
hw/intc/arm_gicv3_its_common.c | 7 +-
93
hw/intc/arm_gicv3_its_kvm.c | 14 +-
94
hw/intc/arm_gicv3_kvm.c | 14 +-
95
hw/misc/imx6_src.c | 2 +-
96
hw/misc/iotkit-sysctl.c | 1 -
97
target/arm/cpu.c | 5 +-
98
target/arm/cpu64.c | 70 ++++++++++
99
target/arm/cpu_tcg.c | 1 +
100
target/arm/helper.c | 231 ++++++++++++++++++++++++---------
101
hw/misc/meson.build | 11 +-
102
26 files changed, 538 insertions(+), 158 deletions(-)
103
diff view generated by jsdifflib
New patch
[PULL 01/29] hw/arm/virt: Introduce virt_set_high_memmap() helper
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
This introduces virt_set_high_memmap() helper. The logic of high
4
memory region address assignment is moved to the helper. The intention
5
is to make the subsequent optimization for high memory region address
6
assignment easier.
7
8
No functional change intended.
9
10
Signed-off-by: Gavin Shan <gshan@redhat.com>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
12
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
13
Reviewed-by: Marc Zyngier <maz@kernel.org>
14
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
15
Message-id: 20221029224307.138822-2-gshan@redhat.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/arm/virt.c | 74 ++++++++++++++++++++++++++++-----------------------
19
1 file changed, 41 insertions(+), 33 deletions(-)
20
21
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/arm/virt.c
24
+++ b/hw/arm/virt.c
25
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
26
return arm_cpu_mp_affinity(idx, clustersz);
27
}
28
29
+static void virt_set_high_memmap(VirtMachineState *vms,
30
+ hwaddr base, int pa_bits)
31
+{
32
+ int i;
33
+
34
+ for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
35
+ hwaddr size = extended_memmap[i].size;
36
+ bool fits;
37
+
38
+ base = ROUND_UP(base, size);
39
+ vms->memmap[i].base = base;
40
+ vms->memmap[i].size = size;
41
+
42
+ /*
43
+ * Check each device to see if they fit in the PA space,
44
+ * moving highest_gpa as we go.
45
+ *
46
+ * For each device that doesn't fit, disable it.
47
+ */
48
+ fits = (base + size) <= BIT_ULL(pa_bits);
49
+ if (fits) {
50
+ vms->highest_gpa = base + size - 1;
51
+ }
52
+
53
+ switch (i) {
54
+ case VIRT_HIGH_GIC_REDIST2:
55
+ vms->highmem_redists &= fits;
56
+ break;
57
+ case VIRT_HIGH_PCIE_ECAM:
58
+ vms->highmem_ecam &= fits;
59
+ break;
60
+ case VIRT_HIGH_PCIE_MMIO:
61
+ vms->highmem_mmio &= fits;
62
+ break;
63
+ }
64
+
65
+ base += size;
66
+ }
67
+}
68
+
69
static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
70
{
71
MachineState *ms = MACHINE(vms);
72
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
73
/* We know for sure that at least the memory fits in the PA space */
74
vms->highest_gpa = memtop - 1;
75
76
- for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
77
- hwaddr size = extended_memmap[i].size;
78
- bool fits;
79
-
80
- base = ROUND_UP(base, size);
81
- vms->memmap[i].base = base;
82
- vms->memmap[i].size = size;
83
-
84
- /*
85
- * Check each device to see if they fit in the PA space,
86
- * moving highest_gpa as we go.
87
- *
88
- * For each device that doesn't fit, disable it.
89
- */
90
- fits = (base + size) <= BIT_ULL(pa_bits);
91
- if (fits) {
92
- vms->highest_gpa = base + size - 1;
93
- }
94
-
95
- switch (i) {
96
- case VIRT_HIGH_GIC_REDIST2:
97
- vms->highmem_redists &= fits;
98
- break;
99
- case VIRT_HIGH_PCIE_ECAM:
100
- vms->highmem_ecam &= fits;
101
- break;
102
- case VIRT_HIGH_PCIE_MMIO:
103
- vms->highmem_mmio &= fits;
104
- break;
105
- }
106
-
107
- base += size;
108
- }
109
+ virt_set_high_memmap(vms, base, pa_bits);
110
111
if (device_memory_size > 0) {
112
ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
113
--
114
2.25.1
diff view generated by jsdifflib
New patch
[PULL 02/29] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
This renames variable 'size' to 'region_size' in virt_set_high_memmap().
4
Its counterpart ('region_base') will be introduced in next patch.
5
6
No functional change intended.
7
8
Signed-off-by: Gavin Shan <gshan@redhat.com>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
11
Reviewed-by: Marc Zyngier <maz@kernel.org>
12
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
13
Message-id: 20221029224307.138822-3-gshan@redhat.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/virt.c | 15 ++++++++-------
17
1 file changed, 8 insertions(+), 7 deletions(-)
18
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/virt.c
22
+++ b/hw/arm/virt.c
23
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
24
static void virt_set_high_memmap(VirtMachineState *vms,
25
hwaddr base, int pa_bits)
26
{
27
+ hwaddr region_size;
28
+ bool fits;
29
int i;
30
31
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
32
- hwaddr size = extended_memmap[i].size;
33
- bool fits;
34
+ region_size = extended_memmap[i].size;
35
36
- base = ROUND_UP(base, size);
37
+ base = ROUND_UP(base, region_size);
38
vms->memmap[i].base = base;
39
- vms->memmap[i].size = size;
40
+ vms->memmap[i].size = region_size;
41
42
/*
43
* Check each device to see if they fit in the PA space,
44
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
45
*
46
* For each device that doesn't fit, disable it.
47
*/
48
- fits = (base + size) <= BIT_ULL(pa_bits);
49
+ fits = (base + region_size) <= BIT_ULL(pa_bits);
50
if (fits) {
51
- vms->highest_gpa = base + size - 1;
52
+ vms->highest_gpa = base + region_size - 1;
53
}
54
55
switch (i) {
56
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
57
break;
58
}
59
60
- base += size;
61
+ base += region_size;
62
}
63
}
64
65
--
66
2.25.1
diff view generated by jsdifflib
New patch
[PULL 03/29] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
This introduces variable 'region_base' for the base address of the
4
specific high memory region. It's the preparatory work to optimize
5
high memory region address assignment.
6
7
No functional change intended.
8
9
Signed-off-by: Gavin Shan <gshan@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
12
Reviewed-by: Marc Zyngier <maz@kernel.org>
13
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
14
Message-id: 20221029224307.138822-4-gshan@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/virt.c | 12 ++++++------
18
1 file changed, 6 insertions(+), 6 deletions(-)
19
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt.c
23
+++ b/hw/arm/virt.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
25
static void virt_set_high_memmap(VirtMachineState *vms,
26
hwaddr base, int pa_bits)
27
{
28
- hwaddr region_size;
29
+ hwaddr region_base, region_size;
30
bool fits;
31
int i;
32
33
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
34
+ region_base = ROUND_UP(base, extended_memmap[i].size);
35
region_size = extended_memmap[i].size;
36
37
- base = ROUND_UP(base, region_size);
38
- vms->memmap[i].base = base;
39
+ vms->memmap[i].base = region_base;
40
vms->memmap[i].size = region_size;
41
42
/*
43
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
44
*
45
* For each device that doesn't fit, disable it.
46
*/
47
- fits = (base + region_size) <= BIT_ULL(pa_bits);
48
+ fits = (region_base + region_size) <= BIT_ULL(pa_bits);
49
if (fits) {
50
- vms->highest_gpa = base + region_size - 1;
51
+ vms->highest_gpa = region_base + region_size - 1;
52
}
53
54
switch (i) {
55
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
56
break;
57
}
58
59
- base += region_size;
60
+ base = region_base + region_size;
61
}
62
}
63
64
--
65
2.25.1
diff view generated by jsdifflib
New patch
[PULL 04/29] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
This introduces virt_get_high_memmap_enabled() helper, which returns
4
the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
5
be used in the subsequent patches.
6
7
No functional change intended.
8
9
Signed-off-by: Gavin Shan <gshan@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
12
Reviewed-by: Marc Zyngier <maz@kernel.org>
13
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
14
Message-id: 20221029224307.138822-5-gshan@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/virt.c | 32 +++++++++++++++++++-------------
18
1 file changed, 19 insertions(+), 13 deletions(-)
19
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt.c
23
+++ b/hw/arm/virt.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
25
return arm_cpu_mp_affinity(idx, clustersz);
26
}
27
28
+static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
29
+ int index)
30
+{
31
+ bool *enabled_array[] = {
32
+ &vms->highmem_redists,
33
+ &vms->highmem_ecam,
34
+ &vms->highmem_mmio,
35
+ };
36
+
37
+ assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
38
+ ARRAY_SIZE(enabled_array));
39
+ assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
40
+
41
+ return enabled_array[index - VIRT_LOWMEMMAP_LAST];
42
+}
43
+
44
static void virt_set_high_memmap(VirtMachineState *vms,
45
hwaddr base, int pa_bits)
46
{
47
hwaddr region_base, region_size;
48
- bool fits;
49
+ bool *region_enabled, fits;
50
int i;
51
52
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
53
+ region_enabled = virt_get_high_memmap_enabled(vms, i);
54
region_base = ROUND_UP(base, extended_memmap[i].size);
55
region_size = extended_memmap[i].size;
56
57
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
58
vms->highest_gpa = region_base + region_size - 1;
59
}
60
61
- switch (i) {
62
- case VIRT_HIGH_GIC_REDIST2:
63
- vms->highmem_redists &= fits;
64
- break;
65
- case VIRT_HIGH_PCIE_ECAM:
66
- vms->highmem_ecam &= fits;
67
- break;
68
- case VIRT_HIGH_PCIE_MMIO:
69
- vms->highmem_mmio &= fits;
70
- break;
71
- }
72
-
73
+ *region_enabled &= fits;
74
base = region_base + region_size;
75
}
76
}
77
--
78
2.25.1
diff view generated by jsdifflib
New patch
[PULL 05/29] hw/arm/virt: Improve high memory region address assignment
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
There are three high memory regions, which are VIRT_HIGH_REDIST2,
4
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
5
are floating on highest RAM address. However, they can be disabled
6
in several cases.
7
8
(1) One specific high memory region is likely to be disabled by
9
code by toggling vms->highmem_{redists, ecam, mmio}.
10
11
(2) VIRT_HIGH_PCIE_ECAM region is disabled on machine, which is
12
'virt-2.12' or ealier than it.
13
14
(3) VIRT_HIGH_PCIE_ECAM region is disabled when firmware is loaded
15
on 32-bits system.
16
17
(4) One specific high memory region is disabled when it breaks the
18
PA space limit.
19
20
The current implementation of virt_set_{memmap, high_memmap}() isn't
21
optimized because the high memory region's PA space is always reserved,
22
regardless of whatever the actual state in the corresponding
23
vms->highmem_{redists, ecam, mmio} flag. In the code, 'base' and
24
'vms->highest_gpa' are always increased for case (1), (2) and (3).
25
It's unnecessary since the assigned PA space for the disabled high
26
memory region won't be used afterwards.
27
28
Improve the address assignment for those three high memory region by
29
skipping the address assignment for one specific high memory region if
30
it has been disabled in case (1), (2) and (3). The memory layout may
31
be changed after the improvement is applied, which leads to potential
32
migration breakage. So 'vms->highmem_compact' is added to control if
33
the improvement should be applied. For now, 'vms->highmem_compact' is
34
set to false, meaning that we don't have memory layout change until it
35
becomes configurable through property 'compact-highmem' in next patch.
36
37
Signed-off-by: Gavin Shan <gshan@redhat.com>
38
Reviewed-by: Eric Auger <eric.auger@redhat.com>
39
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
40
Reviewed-by: Marc Zyngier <maz@kernel.org>
41
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
42
Message-id: 20221029224307.138822-6-gshan@redhat.com
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
44
---
45
include/hw/arm/virt.h | 1 +
46
hw/arm/virt.c | 15 ++++++++++-----
47
2 files changed, 11 insertions(+), 5 deletions(-)
48
49
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
50
index XXXXXXX..XXXXXXX 100644
51
--- a/include/hw/arm/virt.h
52
+++ b/include/hw/arm/virt.h
53
@@ -XXX,XX +XXX,XX @@ struct VirtMachineState {
54
PFlashCFI01 *flash[2];
55
bool secure;
56
bool highmem;
57
+ bool highmem_compact;
58
bool highmem_ecam;
59
bool highmem_mmio;
60
bool highmem_redists;
61
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/virt.c
64
+++ b/hw/arm/virt.c
65
@@ -XXX,XX +XXX,XX @@ static void virt_set_high_memmap(VirtMachineState *vms,
66
vms->memmap[i].size = region_size;
67
68
/*
69
- * Check each device to see if they fit in the PA space,
70
- * moving highest_gpa as we go.
71
+ * Check each device to see if it fits in the PA space,
72
+ * moving highest_gpa as we go. For compatibility, move
73
+ * highest_gpa for disabled fitting devices as well, if
74
+ * the compact layout has been disabled.
75
*
76
* For each device that doesn't fit, disable it.
77
*/
78
fits = (region_base + region_size) <= BIT_ULL(pa_bits);
79
- if (fits) {
80
- vms->highest_gpa = region_base + region_size - 1;
81
+ *region_enabled &= fits;
82
+ if (vms->highmem_compact && !*region_enabled) {
83
+ continue;
84
}
85
86
- *region_enabled &= fits;
87
base = region_base + region_size;
88
+ if (fits) {
89
+ vms->highest_gpa = base - 1;
90
+ }
91
}
92
}
93
94
--
95
2.25.1
diff view generated by jsdifflib
New patch
[PULL 06/29] hw/arm/virt: Add 'compact-highmem' property
1
From: Gavin Shan <gshan@redhat.com>
1
2
3
After the improvement to high memory region address assignment is
4
applied, the memory layout can be changed, introducing possible
5
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
6
is disabled or enabled when the optimization is applied or not, with
7
the following configuration. The configuration is only achievable by
8
modifying the source code until more properties are added to allow
9
users selectively disable those high memory regions.
10
11
pa_bits = 40;
12
vms->highmem_redists = false;
13
vms->highmem_ecam = false;
14
vms->highmem_mmio = true;
15
16
# qemu-system-aarch64 -accel kvm -cpu host \
17
-machine virt-7.2,compact-highmem={on, off} \
18
-m 4G,maxmem=511G -monitor stdio
19
20
Region compact-highmem=off compact-highmem=on
21
----------------------------------------------------------------
22
MEM [1GB 512GB] [1GB 512GB]
23
HIGH_GIC_REDISTS2 [512GB 512GB+64MB] [disabled]
24
HIGH_PCIE_ECAM [512GB+256MB 512GB+512MB] [disabled]
25
HIGH_PCIE_MMIO [disabled] [512GB 1TB]
26
27
In order to keep backwords compatibility, we need to disable the
28
optimization on machine, which is virt-7.1 or ealier than it. It
29
means the optimization is enabled by default from virt-7.2. Besides,
30
'compact-highmem' property is added so that the optimization can be
31
explicitly enabled or disabled on all machine types by users.
32
33
Signed-off-by: Gavin Shan <gshan@redhat.com>
34
Reviewed-by: Eric Auger <eric.auger@redhat.com>
35
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
36
Reviewed-by: Marc Zyngier <maz@kernel.org>
37
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
38
Message-id: 20221029224307.138822-7-gshan@redhat.com
39
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
40
---
41
docs/system/arm/virt.rst | 4 ++++
42
include/hw/arm/virt.h | 1 +
43
hw/arm/virt.c | 32 ++++++++++++++++++++++++++++++++
44
3 files changed, 37 insertions(+)
45
46
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
47
index XXXXXXX..XXXXXXX 100644
48
--- a/docs/system/arm/virt.rst
49
+++ b/docs/system/arm/virt.rst
50
@@ -XXX,XX +XXX,XX @@ highmem
51
address space above 32 bits. The default is ``on`` for machine types
52
later than ``virt-2.12``.
53
54
+compact-highmem
55
+ Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
56
+ The default is ``on`` for machine types later than ``virt-7.2``.
57
+
58
gic-version
59
Specify the version of the Generic Interrupt Controller (GIC) to provide.
60
Valid values are:
61
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
62
index XXXXXXX..XXXXXXX 100644
63
--- a/include/hw/arm/virt.h
64
+++ b/include/hw/arm/virt.h
65
@@ -XXX,XX +XXX,XX @@ struct VirtMachineClass {
66
bool no_pmu;
67
bool claim_edge_triggered_timers;
68
bool smbios_old_sys_ver;
69
+ bool no_highmem_compact;
70
bool no_highmem_ecam;
71
bool no_ged; /* Machines < 4.2 have no support for ACPI GED device */
72
bool kvm_no_adjvtime;
73
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/arm/virt.c
76
+++ b/hw/arm/virt.c
77
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
78
* Note the extended_memmap is sized so that it eventually also includes the
79
* base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
80
* index of base_memmap).
81
+ *
82
+ * The memory map for these Highmem IO Regions can be in legacy or compact
83
+ * layout, depending on 'compact-highmem' property. With legacy layout, the
84
+ * PA space for one specific region is always reserved, even if the region
85
+ * has been disabled or doesn't fit into the PA space. However, the PA space
86
+ * for the region won't be reserved in these circumstances with compact layout.
87
*/
88
static MemMapEntry extended_memmap[] = {
89
/* Additional 64 MB redist region (can contain up to 512 redistributors) */
90
@@ -XXX,XX +XXX,XX @@ static void virt_set_highmem(Object *obj, bool value, Error **errp)
91
vms->highmem = value;
92
}
93
94
+static bool virt_get_compact_highmem(Object *obj, Error **errp)
95
+{
96
+ VirtMachineState *vms = VIRT_MACHINE(obj);
97
+
98
+ return vms->highmem_compact;
99
+}
100
+
101
+static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
102
+{
103
+ VirtMachineState *vms = VIRT_MACHINE(obj);
104
+
105
+ vms->highmem_compact = value;
106
+}
107
+
108
static bool virt_get_its(Object *obj, Error **errp)
109
{
110
VirtMachineState *vms = VIRT_MACHINE(obj);
111
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
112
"Set on/off to enable/disable using "
113
"physical address space above 32 bits");
114
115
+ object_class_property_add_bool(oc, "compact-highmem",
116
+ virt_get_compact_highmem,
117
+ virt_set_compact_highmem);
118
+ object_class_property_set_description(oc, "compact-highmem",
119
+ "Set on/off to enable/disable compact "
120
+ "layout for high memory regions");
121
+
122
object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
123
virt_set_gic_version);
124
object_class_property_set_description(oc, "gic-version",
125
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
126
127
/* High memory is enabled by default */
128
vms->highmem = true;
129
+ vms->highmem_compact = !vmc->no_highmem_compact;
130
vms->gic_version = VIRT_GIC_VERSION_NOSEL;
131
132
vms->highmem_ecam = !vmc->no_highmem_ecam;
133
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(7, 2)
134
135
static void virt_machine_7_1_options(MachineClass *mc)
136
{
137
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
138
+
139
virt_machine_7_2_options(mc);
140
compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
141
+ /* Compact layout for high memory regions was introduced with 7.2 */
142
+ vmc->no_highmem_compact = true;
143
}
144
DEFINE_VIRT_MACHINE(7, 1)
145
146
--
147
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
[PULL 07/29] hw/arm/virt: Add properties to disable high memory regions
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Gavin Shan <gshan@redhat.com>
2
2
3
Cc: qemu-stable@nongnu.org
3
The 3 high memory regions are usually enabled by default, but they may
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2.
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
This leads to waste in the PA space.
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
7
Add properties ("highmem-redists", "highmem-ecam", "highmem-mmio") to
8
allow users selectively disable them if needed. After that, the high
9
memory region for GICv3 or GICv4 redistributor can be disabled by user,
10
the number of maximal supported CPUs needs to be calculated based on
11
'vms->highmem_redists'. The follow-up error message is also improved
12
to indicate if the high memory region for GICv3 and GICv4 has been
13
enabled or not.
14
15
Suggested-by: Marc Zyngier <maz@kernel.org>
16
Signed-off-by: Gavin Shan <gshan@redhat.com>
17
Reviewed-by: Marc Zyngier <maz@kernel.org>
18
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
19
Reviewed-by: Eric Auger <eric.auger@redhat.com>
20
Message-id: 20221029224307.138822-8-gshan@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
22
---
10
target/arm/helper.h | 6 +++
23
docs/system/arm/virt.rst | 13 +++++++
11
target/arm/helper.c | 38 ++++++++++++++-
24
hw/arm/virt.c | 75 ++++++++++++++++++++++++++++++++++++++--
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
25
2 files changed, 86 insertions(+), 2 deletions(-)
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
26
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
27
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
16
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
29
--- a/docs/system/arm/virt.rst
18
+++ b/target/arm/helper.h
30
+++ b/docs/system/arm/virt.rst
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
31
@@ -XXX,XX +XXX,XX @@ compact-highmem
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
32
Set ``on``/``off`` to enable/disable the compact layout for high memory regions.
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
33
The default is ``on`` for machine types later than ``virt-7.2``.
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
34
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
35
+highmem-redists
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
36
+ Set ``on``/``off`` to enable/disable the high memory region for GICv3 or
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
37
+ GICv4 redistributor. The default is ``on``. Setting this to ``off`` will
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
38
+ limit the maximum number of CPUs when GICv3 or GICv4 is used.
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
39
+
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
40
+highmem-ecam
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
41
+ Set ``on``/``off`` to enable/disable the high memory region for PCI ECAM.
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
42
+ The default is ``on`` for machine types later than ``virt-3.0``.
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
43
+
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
44
+highmem-mmio
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
45
+ Set ``on``/``off`` to enable/disable the high memory region for PCI MMIO.
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
46
+ The default is ``on``.
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
47
+
36
48
gic-version
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
49
Specify the version of the Generic Interrupt Controller (GIC) to provide.
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
50
Valid values are:
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
51
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
40
index XXXXXXX..XXXXXXX 100644
52
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
53
--- a/hw/arm/virt.c
42
+++ b/target/arm/helper.c
54
+++ b/hw/arm/virt.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
55
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
44
#undef VFP_CONV_FIX_A64
56
if (vms->gic_version == VIRT_GIC_VERSION_2) {
45
57
virt_max_cpus = GIC_NCPU;
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
58
} else {
47
- * Therefore we convert to f64 (which does not round), scale,
59
- virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) +
48
- * and then convert f64 to f16 (which may round).
60
- virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
61
+ virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
50
+ * vice versa for conversion to integer.
62
+ if (vms->highmem_redists) {
51
+ *
63
+ virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
64
+ }
53
+ * For 64-bit integers, any integer that would cause rounding will also
65
}
54
+ * overflow to f16 infinity, so there is no double rounding problem.
66
55
*/
67
if (max_cpus > virt_max_cpus) {
56
68
error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
69
"supported by machine 'mach-virt' (%d)",
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
70
max_cpus, virt_max_cpus);
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
71
+ if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
72
+ error_printf("Try 'highmem-redists=on' for more CPUs\n");
73
+ }
74
+
75
exit(1);
76
}
77
78
@@ -XXX,XX +XXX,XX @@ static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
79
vms->highmem_compact = value;
60
}
80
}
61
81
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
82
+static bool virt_get_highmem_redists(Object *obj, Error **errp)
63
+{
83
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
84
+ VirtMachineState *vms = VIRT_MACHINE(obj);
85
+
86
+ return vms->highmem_redists;
65
+}
87
+}
66
+
88
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
89
+static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
68
+{
90
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
91
+ VirtMachineState *vms = VIRT_MACHINE(obj);
92
+
93
+ vms->highmem_redists = value;
70
+}
94
+}
71
+
95
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
96
+static bool virt_get_highmem_ecam(Object *obj, Error **errp)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
97
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
98
+ VirtMachineState *vms = VIRT_MACHINE(obj);
99
+
100
+ return vms->highmem_ecam;
82
+}
101
+}
83
+
102
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
103
+static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
85
+{
104
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
105
+ VirtMachineState *vms = VIRT_MACHINE(obj);
106
+
107
+ vms->highmem_ecam = value;
87
+}
108
+}
88
+
109
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
110
+static bool virt_get_highmem_mmio(Object *obj, Error **errp)
90
+{
111
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
112
+ VirtMachineState *vms = VIRT_MACHINE(obj);
113
+
114
+ return vms->highmem_mmio;
92
+}
115
+}
93
+
116
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
117
+static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
95
+{
118
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
119
+ VirtMachineState *vms = VIRT_MACHINE(obj);
120
+
121
+ vms->highmem_mmio = value;
97
+}
122
+}
98
+
123
+
99
/* Set the current fp rounding mode and return the old one.
124
+
100
* The argument is a softfloat float_round_ value.
125
static bool virt_get_its(Object *obj, Error **errp)
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
126
{
109
bool is_signed = !(opcode & 1);
127
VirtMachineState *vms = VIRT_MACHINE(obj);
110
- bool is_double = type;
128
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
111
TCGv_ptr tcg_fpstatus;
129
"Set on/off to enable/disable compact "
112
- TCGv_i32 tcg_shift;
130
"layout for high memory regions");
113
+ TCGv_i32 tcg_shift, tcg_single;
131
114
+ TCGv_i64 tcg_double;
132
+ object_class_property_add_bool(oc, "highmem-redists",
115
133
+ virt_get_highmem_redists,
116
- tcg_fpstatus = get_fpstatus_ptr(false);
134
+ virt_set_highmem_redists);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
135
+ object_class_property_set_description(oc, "highmem-redists",
118
136
+ "Set on/off to enable/disable high "
119
tcg_shift = tcg_const_i32(64 - scale);
137
+ "memory region for GICv3 or GICv4 "
120
138
+ "redistributor");
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
139
+
141
+ case 0: /* float32 */
140
+ object_class_property_add_bool(oc, "highmem-ecam",
142
+ tcg_single = tcg_temp_new_i32();
141
+ virt_get_highmem_ecam,
143
if (is_signed) {
142
+ virt_set_highmem_ecam);
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
143
+ object_class_property_set_description(oc, "highmem-ecam",
145
tcg_shift, tcg_fpstatus);
144
+ "Set on/off to enable/disable high "
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
145
+ "memory region for PCI ECAM");
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
146
+
152
+ case 3: /* float16 */
147
+ object_class_property_add_bool(oc, "highmem-mmio",
153
+ tcg_single = tcg_temp_new_i32();
148
+ virt_get_highmem_mmio,
154
+ if (is_signed) {
149
+ virt_set_highmem_mmio);
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
150
+ object_class_property_set_description(oc, "highmem-mmio",
156
+ tcg_shift, tcg_fpstatus);
151
+ "Set on/off to enable/disable high "
157
+ } else {
152
+ "memory region for PCI MMIO");
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
153
+
165
+ default:
154
object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
166
+ g_assert_not_reached();
155
virt_set_gic_version);
167
}
156
object_class_property_set_description(oc, "gic-version",
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
157
--
266
2.17.0
158
2.25.1
267
268
diff view generated by jsdifflib
New patch
[PULL 08/29] hw/arm/virt: build SMBIOS 19 table
1
From: Mihai Carabas <mihai.carabas@oracle.com>
1
2
3
Use the base_memmap to build the SMBIOS 19 table which provides the address
4
mapping for a Physical Memory Array (from spec [1] chapter 7.20).
5
6
This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5
7
("SMBIOS: Build aggregate smbios tables and entry point").
8
9
[1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.5.0.pdf
10
11
The absence of this table is a breach of the specs and is
12
detected by the FirmwareTestSuite (FWTS), but it doesn't
13
cause any known problems for guest OSes.
14
15
Signed-off-by: Mihai Carabas <mihai.carabas@oracle.com>
16
Message-id: 1668789029-5432-1-git-send-email-mihai.carabas@oracle.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/virt.c | 8 +++++++-
21
1 file changed, 7 insertions(+), 1 deletion(-)
22
23
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/virt.c
26
+++ b/hw/arm/virt.c
27
@@ -XXX,XX +XXX,XX @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
28
static void virt_build_smbios(VirtMachineState *vms)
29
{
30
MachineClass *mc = MACHINE_GET_CLASS(vms);
31
+ MachineState *ms = MACHINE(vms);
32
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
33
uint8_t *smbios_tables, *smbios_anchor;
34
size_t smbios_tables_len, smbios_anchor_len;
35
+ struct smbios_phys_mem_area mem_array;
36
const char *product = "QEMU Virtual Machine";
37
38
if (kvm_enabled()) {
39
@@ -XXX,XX +XXX,XX @@ static void virt_build_smbios(VirtMachineState *vms)
40
vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
41
true, SMBIOS_ENTRY_POINT_TYPE_64);
42
43
- smbios_get_tables(MACHINE(vms), NULL, 0,
44
+ /* build the array of physical mem area from base_memmap */
45
+ mem_array.address = vms->memmap[VIRT_MEM].base;
46
+ mem_array.length = ms->ram_size;
47
+
48
+ smbios_get_tables(ms, &mem_array, 1,
49
&smbios_tables, &smbios_tables_len,
50
&smbios_anchor, &smbios_anchor_len,
51
&error_fatal);
52
--
53
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
[PULL 09/29] target/arm: Add Cortex-A55 CPU
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Timofey Kutergin <tkutergin@gmail.com>
2
2
3
We missed all of the scalar fp16 fma operations.
3
The Cortex-A55 is one of the newer armv8.2+ CPUs; in particular
4
it supports the Privileged Access Never (PAN) feature. Add
5
a model of this CPU, so you can use a CPU type on the virt
6
board that models a specific real hardware CPU, rather than
7
having to use the QEMU-specific "max" CPU type.
4
8
5
Cc: qemu-stable@nongnu.org
9
Signed-off-by: Timofey Kutergin <tkutergin@gmail.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20221121150819.2782817-1-tkutergin@gmail.com
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
[PMM: tweaked commit message]
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
15
docs/system/arm/virt.rst | 1 +
13
1 file changed, 48 insertions(+)
16
hw/arm/virt.c | 1 +
17
target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++
18
3 files changed, 71 insertions(+)
14
19
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
22
--- a/docs/system/arm/virt.rst
18
+++ b/target/arm/translate-a64.c
23
+++ b/docs/system/arm/virt.rst
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
24
@@ -XXX,XX +XXX,XX @@ Supported guest CPU types:
20
tcg_temp_free_i64(tcg_res);
25
- ``cortex-a15`` (32-bit; the default)
26
- ``cortex-a35`` (64-bit)
27
- ``cortex-a53`` (64-bit)
28
+- ``cortex-a55`` (64-bit)
29
- ``cortex-a57`` (64-bit)
30
- ``cortex-a72`` (64-bit)
31
- ``cortex-a76`` (64-bit)
32
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/virt.c
35
+++ b/hw/arm/virt.c
36
@@ -XXX,XX +XXX,XX @@ static const char *valid_cpus[] = {
37
ARM_CPU_TYPE_NAME("cortex-a15"),
38
ARM_CPU_TYPE_NAME("cortex-a35"),
39
ARM_CPU_TYPE_NAME("cortex-a53"),
40
+ ARM_CPU_TYPE_NAME("cortex-a55"),
41
ARM_CPU_TYPE_NAME("cortex-a57"),
42
ARM_CPU_TYPE_NAME("cortex-a72"),
43
ARM_CPU_TYPE_NAME("cortex-a76"),
44
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu64.c
47
+++ b/target/arm/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
49
define_cortex_a72_a57_a53_cp_reginfo(cpu);
21
}
50
}
22
51
23
+/* Floating-point data-processing (3 source) - half precision */
52
+static void aarch64_a55_initfn(Object *obj)
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
25
+ int rd, int rn, int rm, int ra)
26
+{
53
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
54
+ ARMCPU *cpu = ARM_CPU(obj);
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
30
+
55
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
56
+ cpu->dtb_compatible = "arm,cortex-a55";
32
+ tcg_op2 = read_fp_hreg(s, rm);
57
+ set_feature(&cpu->env, ARM_FEATURE_V8);
33
+ tcg_op3 = read_fp_hreg(s, ra);
58
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
59
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
60
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
61
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
62
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
63
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
64
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
34
+
65
+
35
+ /* These are fused multiply-add, and must be done as one
66
+ /* Ordered by B2.4 AArch64 registers by functional group */
36
+ * floating point operation with no rounding between the
67
+ cpu->clidr = 0x82000023;
37
+ * multiplication and addition steps.
68
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
38
+ * NB that doing the negations here as separate steps is
69
+ cpu->dcz_blocksize = 4; /* 64 bytes */
39
+ * correct : an input NaN should come out with its sign bit
70
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
40
+ * flipped if it is a negated-input.
71
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
41
+ */
72
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
42
+ if (o1 == true) {
73
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
74
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
44
+ }
75
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
76
+ cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
77
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
78
+ cpu->id_afr0 = 0x00000000;
79
+ cpu->isar.id_dfr0 = 0x04010088;
80
+ cpu->isar.id_isar0 = 0x02101110;
81
+ cpu->isar.id_isar1 = 0x13112111;
82
+ cpu->isar.id_isar2 = 0x21232042;
83
+ cpu->isar.id_isar3 = 0x01112131;
84
+ cpu->isar.id_isar4 = 0x00011142;
85
+ cpu->isar.id_isar5 = 0x01011121;
86
+ cpu->isar.id_isar6 = 0x00000010;
87
+ cpu->isar.id_mmfr0 = 0x10201105;
88
+ cpu->isar.id_mmfr1 = 0x40000000;
89
+ cpu->isar.id_mmfr2 = 0x01260000;
90
+ cpu->isar.id_mmfr3 = 0x02122211;
91
+ cpu->isar.id_mmfr4 = 0x00021110;
92
+ cpu->isar.id_pfr0 = 0x10010131;
93
+ cpu->isar.id_pfr1 = 0x00011011;
94
+ cpu->isar.id_pfr2 = 0x00000011;
95
+ cpu->midr = 0x412FD050; /* r2p0 */
96
+ cpu->revidr = 0;
45
+
97
+
46
+ if (o0 != o1) {
98
+ /* From B2.23 CCSIDR_EL1 */
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
99
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
48
+ }
100
+ cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
101
+ cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
49
+
102
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
103
+ /* From B2.96 SCTLR_EL3 */
104
+ cpu->reset_sctlr = 0x30c50838;
51
+
105
+
52
+ write_fp_sreg(s, rd, tcg_res);
106
+ /* From B4.45 ICH_VTR_EL2 */
107
+ cpu->gic_num_lrs = 4;
108
+ cpu->gic_vpribits = 5;
109
+ cpu->gic_vprebits = 5;
110
+ cpu->gic_pribits = 5;
53
+
111
+
54
+ tcg_temp_free_ptr(fpst);
112
+ cpu->isar.mvfr0 = 0x10110222;
55
+ tcg_temp_free_i32(tcg_op1);
113
+ cpu->isar.mvfr1 = 0x13211111;
56
+ tcg_temp_free_i32(tcg_op2);
114
+ cpu->isar.mvfr2 = 0x00000043;
57
+ tcg_temp_free_i32(tcg_op3);
115
+
58
+ tcg_temp_free_i32(tcg_res);
116
+ /* From D5.4 AArch64 PMU register summary */
117
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
59
+}
118
+}
60
+
119
+
61
/* Floating point data-processing (3 source)
120
static void aarch64_a72_initfn(Object *obj)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
121
{
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
122
ARMCPU *cpu = ARM_CPU(obj);
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
123
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo aarch64_cpus[] = {
65
}
124
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
125
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
67
break;
126
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
68
+ case 3:
127
+ { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
128
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
70
+ unallocated_encoding(s);
129
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
71
+ return;
130
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
80
}
81
--
131
--
82
2.17.0
132
2.25.1
83
84
diff view generated by jsdifflib
New patch
[PULL 10/29] hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
1
From: Luke Starrett <lukes@xsightlabs.com>
1
2
3
The ARM GICv3 TRM describes that the ITLinesNumber field of GICD_TYPER
4
register:
5
6
"indicates the maximum SPI INTID that the GIC implementation supports"
7
8
As SPI #0 is absolute IRQ #32, the max SPI INTID should have accounted
9
for the internal 16x SGI's and 16x PPI's. However, the original GICv3
10
model subtracted off the SGI/PPI. Cosmetically this can be seen at OS
11
boot (Linux) showing 32 shy of what should be there, i.e.:
12
13
[ 0.000000] GICv3: 224 SPIs implemented
14
15
Though in hw/arm/virt.c, the machine is configured for 256 SPI's. ARM
16
virt machine likely doesn't have a problem with this because the upper
17
32 IRQ's don't actually have anything meaningful wired. But, this does
18
become a functional issue on a custom use case which wants to make use
19
of these IRQ's. Additionally, boot code (i.e. TF-A) will only init up
20
to the number (blocks of 32) that it believes to actually be there.
21
22
Signed-off-by: Luke Starrett <lukes@xsightlabs.com>
23
Message-id: AM9P193MB168473D99B761E204E032095D40D9@AM9P193MB1684.EURP193.PROD.OUTLOOK.COM
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
hw/intc/arm_gicv3_dist.c | 4 ++--
28
1 file changed, 2 insertions(+), 2 deletions(-)
29
30
diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_dist.c
33
+++ b/hw/intc/arm_gicv3_dist.c
34
@@ -XXX,XX +XXX,XX @@ static bool gicd_readl(GICv3State *s, hwaddr offset,
35
* MBIS == 0 (message-based SPIs not supported)
36
* SecurityExtn == 1 if security extns supported
37
* CPUNumber == 0 since for us ARE is always 1
38
- * ITLinesNumber == (num external irqs / 32) - 1
39
+ * ITLinesNumber == (((max SPI IntID + 1) / 32) - 1)
40
*/
41
- int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
42
+ int itlinesnumber = (s->num_irq / 32) - 1;
43
/*
44
* SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
45
* "security extensions not supported" always implies DS == 1,
46
--
47
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
[PULL 11/29] target/arm: Allow relevant HCR bits to be written for FEAT_EVT
1
From: Richard Henderson <richard.henderson@linaro.org>
1
FEAT_EVT adds five new bits to the HCR_EL2 register: TTLBIS, TTLBOS,
2
TICAB, TOCU and TID4. These allow the guest to enable trapping of
3
various EL1 instructions to EL2. In this commit, add the necessary
4
code to allow the guest to set these bits if the feature is present;
5
because the bit is always zero when the feature isn't present we
6
won't need to use explicit feature checks in the "trap on condition"
7
tests in the following commits.
2
8
3
Cc: qemu-stable@nongnu.org
9
Note that although full implementation of the feature (mandatory from
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Armv8.5 onward) requires all five trap bits, the ID registers permit
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
a value indicating that only TICAB, TOCU and TID4 are implemented,
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
which might be the case for CPUs between Armv8.2 and Armv8.5.
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
13
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
---
16
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
17
target/arm/cpu.h | 30 ++++++++++++++++++++++++++++++
11
1 file changed, 14 insertions(+), 16 deletions(-)
18
target/arm/helper.c | 6 ++++++
19
2 files changed, 36 insertions(+)
12
20
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
23
--- a/target/arm/cpu.h
16
+++ b/target/arm/translate-a64.c
24
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
25
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
18
return v;
26
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
19
}
27
}
20
28
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
29
+static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
22
+{
30
+{
23
+ TCGv_i32 v = tcg_temp_new_i32();
31
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
24
+
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
26
+ return v;
27
+}
32
+}
28
+
33
+
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
34
+static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
30
* If SVE is not enabled, then there are only 128 bits in the vector.
35
+{
36
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
37
+}
38
+
39
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
40
{
41
return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
42
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
43
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
44
}
45
46
+static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
47
+{
48
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
49
+}
50
+
51
+static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
52
+{
53
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
54
+}
55
+
56
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
57
{
58
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
59
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ras(const ARMISARegisters *id)
60
return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
61
}
62
63
+static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
64
+{
65
+ return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
66
+}
67
+
68
+static inline bool isar_feature_any_evt(const ARMISARegisters *id)
69
+{
70
+ return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
71
+}
72
+
73
/*
74
* Forward to the above feature tests given an ARMCPU pointer.
31
*/
75
*/
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
76
diff --git a/target/arm/helper.c b/target/arm/helper.c
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
77
index XXXXXXX..XXXXXXX 100644
34
{
78
--- a/target/arm/helper.c
35
TCGv_ptr fpst = NULL;
79
+++ b/target/arm/helper.c
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
80
@@ -XXX,XX +XXX,XX @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask)
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
81
}
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
39
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
41
-
42
switch (opcode) {
43
case 0x0: /* FMOV */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
48
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
82
}
79
83
80
if (is_scalar) {
84
+ if (cpu_isar_feature(any_evt, cpu)) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
85
+ valid_mask |= HCR_TTLBIS | HCR_TTLBOS | HCR_TICAB | HCR_TOCU | HCR_TID4;
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
86
+ } else if (cpu_isar_feature(any_half_evt, cpu)) {
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
87
+ valid_mask |= HCR_TICAB | HCR_TOCU | HCR_TID4;
84
88
+ }
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
89
+
86
-
90
/* Clear RES0 bits. */
87
switch (fpop) {
91
value &= valid_mask;
88
case 0x1a: /* FCVTNS */
92
89
case 0x1b: /* FCVTMS */
90
--
93
--
91
2.17.0
94
2.25.1
92
93
diff view generated by jsdifflib
New patch
[PULL 12/29] target/arm: Implement HCR_EL2.TTLBIS traps
1
For FEAT_EVT, the HCR_EL2.TTLBIS bit allows trapping on EL1 use of
2
TLB maintenance instructions that operate on the inner shareable
3
domain:
1
4
5
AArch64:
6
TLBI VMALLE1IS, TLBI VAE1IS, TLBI ASIDE1IS, TLBI VAAE1IS,
7
TLBI VALE1IS, TLBI VAALE1IS, TLBI RVAE1IS, TLBI RVAAE1IS,
8
TLBI RVALE1IS, and TLBI RVAALE1IS.
9
10
AArch32:
11
TLBIALLIS, TLBIMVAIS, TLBIASIDIS, TLBIMVAAIS, TLBIMVALIS,
12
and TLBIMVAALIS.
13
14
Add the trapping support.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
---
19
target/arm/helper.c | 43 +++++++++++++++++++++++++++----------------
20
1 file changed, 27 insertions(+), 16 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
27
return CP_ACCESS_OK;
28
}
29
30
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
31
+static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
32
+ bool isread)
33
+{
34
+ if (arm_current_el(env) == 1 &&
35
+ (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
36
+ return CP_ACCESS_TRAP_EL2;
37
+ }
38
+ return CP_ACCESS_OK;
39
+}
40
+
41
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
42
{
43
ARMCPU *cpu = env_archcpu(env);
44
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
45
static const ARMCPRegInfo v7mp_cp_reginfo[] = {
46
/* 32 bit TLB invalidates, Inner Shareable */
47
{ .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
48
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
49
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
50
.writefn = tlbiall_is_write },
51
{ .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
52
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
53
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
54
.writefn = tlbimva_is_write },
55
{ .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
56
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
57
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
58
.writefn = tlbiasid_is_write },
59
{ .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
60
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
61
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
62
.writefn = tlbimvaa_is_write },
63
};
64
65
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
66
/* TLBI operations */
67
{ .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
68
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
69
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
70
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
71
.writefn = tlbi_aa64_vmalle1is_write },
72
{ .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
73
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
74
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
75
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
76
.writefn = tlbi_aa64_vae1is_write },
77
{ .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
78
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
79
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
80
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
81
.writefn = tlbi_aa64_vmalle1is_write },
82
{ .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
83
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
84
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
85
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
86
.writefn = tlbi_aa64_vae1is_write },
87
{ .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
88
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
89
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
90
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
91
.writefn = tlbi_aa64_vae1is_write },
92
{ .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
93
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
94
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
95
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
96
.writefn = tlbi_aa64_vae1is_write },
97
{ .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
98
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
100
#endif
101
/* TLB invalidate last level of translation table walk */
102
{ .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
103
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
104
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
105
.writefn = tlbimva_is_write },
106
{ .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
107
- .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
108
+ .type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlbis,
109
.writefn = tlbimvaa_is_write },
110
{ .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
111
.type = ARM_CP_NO_RAW, .access = PL1_W, .accessfn = access_ttlb,
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
113
static const ARMCPRegInfo tlbirange_reginfo[] = {
114
{ .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64,
115
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1,
116
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
117
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
118
.writefn = tlbi_aa64_rvae1is_write },
119
{ .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64,
120
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3,
121
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
122
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
123
.writefn = tlbi_aa64_rvae1is_write },
124
{ .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64,
125
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5,
126
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
127
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
128
.writefn = tlbi_aa64_rvae1is_write },
129
{ .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64,
130
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7,
131
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
132
+ .access = PL1_W, .accessfn = access_ttlbis, .type = ARM_CP_NO_RAW,
133
.writefn = tlbi_aa64_rvae1is_write },
134
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
135
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
136
--
137
2.25.1
diff view generated by jsdifflib
New patch
[PULL 13/29] target/arm: Implement HCR_EL2.TTLBOS traps
1
For FEAT_EVT, the HCR_EL2.TTLBOS bit allows trapping on EL1
2
use of TLB maintenance instructions that operate on the
3
outer shareable domain:
1
4
5
TLBI VMALLE1OS, TLBI VAE1OS, TLBI ASIDE1OS,TLBI VAAE1OS,
6
TLBI VALE1OS, TLBI VAALE1OS, TLBI RVAE1OS, TLBI RVAAE1OS,
7
TLBI RVALE1OS, and TLBI RVAALE1OS.
8
9
(There are no AArch32 outer-shareable TLB maintenance ops.)
10
11
Implement the trapping.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
target/arm/helper.c | 33 +++++++++++++++++++++++----------
17
1 file changed, 23 insertions(+), 10 deletions(-)
18
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
22
+++ b/target/arm/helper.c
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
24
return CP_ACCESS_OK;
25
}
26
27
+#ifdef TARGET_AARCH64
28
+/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
29
+static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
30
+ bool isread)
31
+{
32
+ if (arm_current_el(env) == 1 &&
33
+ (arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
34
+ return CP_ACCESS_TRAP_EL2;
35
+ }
36
+ return CP_ACCESS_OK;
37
+}
38
+#endif
39
+
40
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
41
{
42
ARMCPU *cpu = env_archcpu(env);
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
44
.writefn = tlbi_aa64_rvae1is_write },
45
{ .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64,
46
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
47
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
48
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
49
.writefn = tlbi_aa64_rvae1is_write },
50
{ .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64,
51
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3,
52
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
53
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
54
.writefn = tlbi_aa64_rvae1is_write },
55
{ .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64,
56
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5,
57
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
58
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
59
.writefn = tlbi_aa64_rvae1is_write },
60
{ .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64,
61
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7,
62
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
63
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
64
.writefn = tlbi_aa64_rvae1is_write },
65
{ .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64,
66
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo tlbirange_reginfo[] = {
68
static const ARMCPRegInfo tlbios_reginfo[] = {
69
{ .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64,
70
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0,
71
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
72
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
73
.writefn = tlbi_aa64_vmalle1is_write },
74
{ .name = "TLBI_VAE1OS", .state = ARM_CP_STATE_AA64,
75
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 1,
76
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
77
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
78
.writefn = tlbi_aa64_vae1is_write },
79
{ .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64,
80
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2,
81
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
82
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
83
.writefn = tlbi_aa64_vmalle1is_write },
84
{ .name = "TLBI_VAAE1OS", .state = ARM_CP_STATE_AA64,
85
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 3,
86
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
87
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
88
.writefn = tlbi_aa64_vae1is_write },
89
{ .name = "TLBI_VALE1OS", .state = ARM_CP_STATE_AA64,
90
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 5,
91
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
92
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
93
.writefn = tlbi_aa64_vae1is_write },
94
{ .name = "TLBI_VAALE1OS", .state = ARM_CP_STATE_AA64,
95
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 7,
96
- .access = PL1_W, .accessfn = access_ttlb, .type = ARM_CP_NO_RAW,
97
+ .access = PL1_W, .accessfn = access_ttlbos, .type = ARM_CP_NO_RAW,
98
.writefn = tlbi_aa64_vae1is_write },
99
{ .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64,
100
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0,
101
--
102
2.25.1
diff view generated by jsdifflib
New patch
[PULL 14/29] target/arm: Implement HCR_EL2.TICAB,TOCU traps
1
For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
2
and IC IALLUIS cache maintenance instructions.
1
3
4
The HCR_EL2.TOCU bit traps all the other cache maintenance
5
instructions that operate to the point of unification:
6
AArch64 IC IVAU, IC IALLU, DC CVAU
7
AArch32 ICIMVAU, ICIALLU, DCCMVAU
8
9
The two trap bits between them cover all of the cache maintenance
10
instructions which must also check the HCR_TPU flag. Turn the old
11
aa64_cacheop_pou_access() function into a helper function which takes
12
the set of HCR_EL2 flags to check as an argument, and call it from
13
new access_ticab() and access_tocu() functions as appropriate for
14
each cache op.
15
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
---
19
target/arm/helper.c | 36 +++++++++++++++++++++++-------------
20
1 file changed, 23 insertions(+), 13 deletions(-)
21
22
diff --git a/target/arm/helper.c b/target/arm/helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/helper.c
25
+++ b/target/arm/helper.c
26
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
27
return CP_ACCESS_OK;
28
}
29
30
-static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
31
- const ARMCPRegInfo *ri,
32
- bool isread)
33
+static CPAccessResult do_cacheop_pou_access(CPUARMState *env, uint64_t hcrflags)
34
{
35
/* Cache invalidate/clean to Point of Unification... */
36
switch (arm_current_el(env)) {
37
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
38
}
39
/* fall through */
40
case 1:
41
- /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
42
- if (arm_hcr_el2_eff(env) & HCR_TPU) {
43
+ /* ... EL1 must trap to EL2 if relevant HCR_EL2 flags are set. */
44
+ if (arm_hcr_el2_eff(env) & hcrflags) {
45
return CP_ACCESS_TRAP_EL2;
46
}
47
break;
48
@@ -XXX,XX +XXX,XX @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
49
return CP_ACCESS_OK;
50
}
51
52
+static CPAccessResult access_ticab(CPUARMState *env, const ARMCPRegInfo *ri,
53
+ bool isread)
54
+{
55
+ return do_cacheop_pou_access(env, HCR_TICAB | HCR_TPU);
56
+}
57
+
58
+static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
59
+ bool isread)
60
+{
61
+ return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
62
+}
63
+
64
/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
65
* Page D4-1736 (DDI0487A.b)
66
*/
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
68
{ .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
69
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
70
.access = PL1_W, .type = ARM_CP_NOP,
71
- .accessfn = aa64_cacheop_pou_access },
72
+ .accessfn = access_ticab },
73
{ .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
74
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
75
.access = PL1_W, .type = ARM_CP_NOP,
76
- .accessfn = aa64_cacheop_pou_access },
77
+ .accessfn = access_tocu },
78
{ .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
79
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
80
.access = PL0_W, .type = ARM_CP_NOP,
81
- .accessfn = aa64_cacheop_pou_access },
82
+ .accessfn = access_tocu },
83
{ .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
84
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
85
.access = PL1_W, .accessfn = aa64_cacheop_poc_access,
86
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
87
{ .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
88
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
89
.access = PL0_W, .type = ARM_CP_NOP,
90
- .accessfn = aa64_cacheop_pou_access },
91
+ .accessfn = access_tocu },
92
{ .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
93
.opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
94
.access = PL0_W, .type = ARM_CP_NOP,
95
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
96
.writefn = tlbiipas2is_hyp_write },
97
/* 32 bit cache operations */
98
{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
99
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
100
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_ticab },
101
{ .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
102
.type = ARM_CP_NOP, .access = PL1_W },
103
{ .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
104
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
105
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
106
{ .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
107
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
108
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
109
{ .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
110
.type = ARM_CP_NOP, .access = PL1_W },
111
{ .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
112
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
113
{ .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
114
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tsw },
115
{ .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
116
- .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
117
+ .type = ARM_CP_NOP, .access = PL1_W, .accessfn = access_tocu },
118
{ .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
119
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_poc_access },
120
{ .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
121
--
122
2.25.1
diff view generated by jsdifflib
New patch
[PULL 15/29] target/arm: Implement HCR_EL2.TID4 traps
1
For FEAT_EVT, the HCR_EL2.TID4 trap allows trapping of the cache ID
2
registers CCSIDR_EL1, CCSIDR2_EL1, CLIDR_EL1 and CSSELR_EL1 (and
3
their AArch32 equivalents). This is a subset of the registers
4
trapped by HCR_EL2.TID2, which includes all of these and also the
5
CTR_EL0 register.
1
6
7
Our implementation already uses a separate access function for
8
CTR_EL0 (ctr_el0_access()), so all of the registers currently using
9
access_aa64_tid2() should also be checking TID4. Make that function
10
check both TID2 and TID4, and rename it appropriately.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
---
15
target/arm/helper.c | 17 +++++++++--------
16
1 file changed, 9 insertions(+), 8 deletions(-)
17
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.c
21
+++ b/target/arm/helper.c
22
@@ -XXX,XX +XXX,XX @@ static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
23
scr_write(env, ri, 0);
24
}
25
26
-static CPAccessResult access_aa64_tid2(CPUARMState *env,
27
- const ARMCPRegInfo *ri,
28
- bool isread)
29
+static CPAccessResult access_tid4(CPUARMState *env,
30
+ const ARMCPRegInfo *ri,
31
+ bool isread)
32
{
33
- if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TID2)) {
34
+ if (arm_current_el(env) == 1 &&
35
+ (arm_hcr_el2_eff(env) & (HCR_TID2 | HCR_TID4))) {
36
return CP_ACCESS_TRAP_EL2;
37
}
38
39
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
40
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
41
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
42
.access = PL1_R,
43
- .accessfn = access_aa64_tid2,
44
+ .accessfn = access_tid4,
45
.readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
46
{ .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
47
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
48
.access = PL1_RW,
49
- .accessfn = access_aa64_tid2,
50
+ .accessfn = access_tid4,
51
.writefn = csselr_write, .resetvalue = 0,
52
.bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
53
offsetof(CPUARMState, cp15.csselr_ns) } },
54
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo ccsidr2_reginfo[] = {
55
{ .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
56
.opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
57
.access = PL1_R,
58
- .accessfn = access_aa64_tid2,
59
+ .accessfn = access_tid4,
60
.readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
61
};
62
63
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
64
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
65
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
66
.access = PL1_R, .type = ARM_CP_CONST,
67
- .accessfn = access_aa64_tid2,
68
+ .accessfn = access_tid4,
69
.resetvalue = cpu->clidr
70
};
71
define_one_arm_cp_reg(cpu, &clidr);
72
--
73
2.25.1
diff view generated by jsdifflib
New patch
[PULL 16/29] target/arm: Report FEAT_EVT for TCG '-cpu max'
1
Update the ID registers for TCG's '-cpu max' to report the
2
FEAT_EVT Enhanced Virtualization Traps support.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
---
7
docs/system/arm/emulation.rst | 1 +
8
target/arm/cpu64.c | 1 +
9
target/arm/cpu_tcg.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
13
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/emulation.rst
15
+++ b/docs/system/arm/emulation.rst
16
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
17
- FEAT_DoubleFault (Double Fault Extension)
18
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
19
- FEAT_ETS (Enhanced Translation Synchronization)
20
+- FEAT_EVT (Enhanced Virtualization Traps)
21
- FEAT_FCMA (Floating-point complex number instructions)
22
- FEAT_FHM (Floating-point half-precision multiplication instructions)
23
- FEAT_FP16 (Half-precision floating-point data processing)
24
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/cpu64.c
27
+++ b/target/arm/cpu64.c
28
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
29
t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
30
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
31
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
32
+ t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
33
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
34
cpu->isar.id_aa64mmfr2 = t;
35
36
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu_tcg.c
39
+++ b/target/arm/cpu_tcg.c
40
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
41
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
42
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
43
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
44
+ t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
45
cpu->isar.id_mmfr4 = t;
46
47
t = cpu->isar.id_mmfr5;
48
--
49
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
[PULL 17/29] hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Convert the TYPE_ARM_SMMU device to 3-phase reset. The legacy method
2
doesn't do anything that's invalid in the hold phase, so the
3
conversion is simple and not a behaviour change.
2
4
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
5
Note that we must convert this base class before we can convert the
6
TYPE_ARM_SMMUV3 subclass -- transitional support in Resettable
7
handles "chain to parent class reset" when the base class is 3-phase
8
and the subclass is still using legacy reset, but not the other way
9
around.
4
10
5
The block length is predefined to 512 bits
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
15
Message-id: 20221109161444.3397405-2-peter.maydell@linaro.org
16
---
17
hw/arm/smmu-common.c | 7 ++++---
18
1 file changed, 4 insertions(+), 3 deletions(-)
6
19
7
and "4.10.2 SD Status":
20
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/sd/sd.c | 2 +-
22
1 file changed, 1 insertion(+), 1 deletion(-)
23
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
25
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
22
--- a/hw/arm/smmu-common.c
27
+++ b/hw/sd/sd.c
23
+++ b/hw/arm/smmu-common.c
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
24
@@ -XXX,XX +XXX,XX @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
30
}
25
}
31
memset(&sd->data[17], 0, 47);
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
34
}
26
}
35
27
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
28
-static void smmu_base_reset(DeviceState *dev)
29
+static void smmu_base_reset_hold(Object *obj)
30
{
31
- SMMUState *s = ARM_SMMU(dev);
32
+ SMMUState *s = ARM_SMMU(obj);
33
34
g_hash_table_remove_all(s->configs);
35
g_hash_table_remove_all(s->iotlb);
36
@@ -XXX,XX +XXX,XX @@ static Property smmu_dev_properties[] = {
37
static void smmu_base_class_init(ObjectClass *klass, void *data)
38
{
39
DeviceClass *dc = DEVICE_CLASS(klass);
40
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
41
SMMUBaseClass *sbc = ARM_SMMU_CLASS(klass);
42
43
device_class_set_props(dc, smmu_dev_properties);
44
device_class_set_parent_realize(dc, smmu_base_realize,
45
&sbc->parent_realize);
46
- dc->reset = smmu_base_reset;
47
+ rc->phases.hold = smmu_base_reset_hold;
48
}
49
50
static const TypeInfo smmu_base_info = {
37
--
51
--
38
2.17.0
52
2.25.1
39
53
40
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
[PULL 18/29] hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Convert the TYPE_ARM_SMMUV3 device to 3-phase reset. The legacy
2
reset method doesn't do anything that's invalid in the hold phase, so
3
the conversion only requires changing it to a hold phase method, and
4
using the 3-phase versions of the "save the parent reset method and
5
chain to it" code.
2
6
3
We are meant to explicitly pass fpst, not cpu_env.
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20221109161444.3397405-3-peter.maydell@linaro.org
12
---
13
include/hw/arm/smmuv3.h | 2 +-
14
hw/arm/smmuv3.c | 12 ++++++++----
15
2 files changed, 9 insertions(+), 5 deletions(-)
4
16
5
Cc: qemu-stable@nongnu.org
17
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-a64.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
19
--- a/include/hw/arm/smmuv3.h
19
+++ b/target/arm/translate-a64.c
20
+++ b/include/hw/arm/smmuv3.h
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
21
@@ -XXX,XX +XXX,XX @@ struct SMMUv3Class {
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
22
/*< public >*/
22
break;
23
23
case 0x3: /* FSQRT */
24
DeviceRealize parent_realize;
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
25
- DeviceReset parent_reset;
25
+ fpst = get_fpstatus_ptr(true);
26
+ ResettablePhases parent_phases;
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
27
};
27
break;
28
28
case 0x8: /* FRINTN */
29
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
29
case 0x9: /* FRINTP */
30
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/arm/smmuv3.c
33
+++ b/hw/arm/smmuv3.c
34
@@ -XXX,XX +XXX,XX @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
35
}
36
}
37
38
-static void smmu_reset(DeviceState *dev)
39
+static void smmu_reset_hold(Object *obj)
40
{
41
- SMMUv3State *s = ARM_SMMUV3(dev);
42
+ SMMUv3State *s = ARM_SMMUV3(obj);
43
SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
44
45
- c->parent_reset(dev);
46
+ if (c->parent_phases.hold) {
47
+ c->parent_phases.hold(obj);
48
+ }
49
50
smmuv3_init_regs(s);
51
}
52
@@ -XXX,XX +XXX,XX @@ static void smmuv3_instance_init(Object *obj)
53
static void smmuv3_class_init(ObjectClass *klass, void *data)
54
{
55
DeviceClass *dc = DEVICE_CLASS(klass);
56
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
57
SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
58
59
dc->vmsd = &vmstate_smmuv3;
60
- device_class_set_parent_reset(dc, smmu_reset, &c->parent_reset);
61
+ resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL,
62
+ &c->parent_phases);
63
c->parent_realize = dc->realize;
64
dc->realize = smmu_realize;
65
}
30
--
66
--
31
2.17.0
67
2.25.1
32
68
33
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
[PULL 19/29] hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Convert the TYPE_ARM_GIC_COMMON device to 3-phase reset. This is a
2
simple no-behaviour-change conversion.
2
3
3
All the hard work is already done by vfp_expand_imm, we just need to
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
make sure we pick up the correct size.
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20221109161444.3397405-4-peter.maydell@linaro.org
8
---
9
hw/intc/arm_gic_common.c | 7 ++++---
10
1 file changed, 4 insertions(+), 3 deletions(-)
5
11
6
Cc: qemu-stable@nongnu.org
12
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
17
1 file changed, 17 insertions(+), 3 deletions(-)
18
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
14
--- a/hw/intc/arm_gic_common.c
22
+++ b/target/arm/translate-a64.c
15
+++ b/hw/intc/arm_gic_common.c
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
16
@@ -XXX,XX +XXX,XX @@ static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
17
}
18
}
19
20
-static void arm_gic_common_reset(DeviceState *dev)
21
+static void arm_gic_common_reset_hold(Object *obj)
24
{
22
{
25
int rd = extract32(insn, 0, 5);
23
- GICState *s = ARM_GIC_COMMON(dev);
26
int imm8 = extract32(insn, 13, 8);
24
+ GICState *s = ARM_GIC_COMMON(obj);
27
- int is_double = extract32(insn, 22, 2);
25
int i, j;
28
+ int type = extract32(insn, 22, 2);
26
int resetprio;
29
uint64_t imm;
27
30
TCGv_i64 tcg_res;
28
@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {
31
+ TCGMemOp sz;
29
static void arm_gic_common_class_init(ObjectClass *klass, void *data)
32
30
{
33
- if (is_double > 1) {
31
DeviceClass *dc = DEVICE_CLASS(klass);
34
+ switch (type) {
32
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
35
+ case 0:
33
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
36
+ sz = MO_32;
34
37
+ break;
35
- dc->reset = arm_gic_common_reset;
38
+ case 1:
36
+ rc->phases.hold = arm_gic_common_reset_hold;
39
+ sz = MO_64;
37
dc->realize = arm_gic_common_realize;
40
+ break;
38
device_class_set_props(dc, arm_gic_common_properties);
41
+ case 3:
39
dc->vmsd = &vmstate_gic;
42
+ sz = MO_16;
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
44
+ break;
45
+ }
46
+ /* fallthru */
47
+ default:
48
unallocated_encoding(s);
49
return;
50
}
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
52
return;
53
}
54
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
56
+ imm = vfp_expand_imm(sz, imm8);
57
58
tcg_res = tcg_const_i64(imm);
59
write_fp_dreg(s, rd, tcg_res);
60
--
40
--
61
2.17.0
41
2.25.1
62
42
63
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
[PULL 20/29] hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Now we have converted TYPE_ARM_GIC_COMMON, we can convert the
2
TYPE_ARM_GIC_KVM subclass to 3-phase reset.
2
3
3
Adding the fp16 moves to/from general registers.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20221109161444.3397405-5-peter.maydell@linaro.org
8
---
9
hw/intc/arm_gic_kvm.c | 14 +++++++++-----
10
1 file changed, 9 insertions(+), 5 deletions(-)
4
11
5
Cc: qemu-stable@nongnu.org
12
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
13
1 file changed, 21 insertions(+)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
14
--- a/hw/intc/arm_gic_kvm.c
18
+++ b/target/arm/translate-a64.c
15
+++ b/hw/intc/arm_gic_kvm.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
16
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
17
struct KVMARMGICClass {
21
clear_vec_high(s, true, rd);
18
ARMGICCommonClass parent_class;
22
break;
19
DeviceRealize parent_realize;
23
+ case 3:
20
- void (*parent_reset)(DeviceState *dev);
24
+ /* 16 bit */
21
+ ResettablePhases parent_phases;
25
+ tmp = tcg_temp_new_i64();
22
};
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
23
27
+ write_fp_dreg(s, rd, tmp);
24
void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
28
+ tcg_temp_free_i64(tmp);
25
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_get(GICState *s)
29
+ break;
30
+ default:
31
+ g_assert_not_reached();
32
}
33
} else {
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
36
/* 64 bits from top half */
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
46
}
26
}
47
}
27
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
28
49
case 0xa: /* 64 bit */
29
-static void kvm_arm_gic_reset(DeviceState *dev)
50
case 0xd: /* 64 bit to top half of quad */
30
+static void kvm_arm_gic_reset_hold(Object *obj)
51
break;
31
{
52
+ case 0x6: /* 16-bit float, 32-bit int */
32
- GICState *s = ARM_GIC_COMMON(dev);
53
+ case 0xe: /* 16-bit float, 64-bit int */
33
+ GICState *s = ARM_GIC_COMMON(obj);
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
34
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
55
+ break;
35
56
+ }
36
- kgc->parent_reset(dev);
57
+ /* fallthru */
37
+ if (kgc->parent_phases.hold) {
58
default:
38
+ kgc->parent_phases.hold(obj);
59
/* all other sf/type/rmode combinations are invalid */
39
+ }
60
unallocated_encoding(s);
40
41
if (kvm_arm_gic_can_save_restore(s)) {
42
kvm_arm_gic_put(s);
43
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
44
static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
48
ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
49
KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
50
51
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
52
agcc->post_load = kvm_arm_gic_put;
53
device_class_set_parent_realize(dc, kvm_arm_gic_realize,
54
&kgc->parent_realize);
55
- device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
56
+ resettable_class_set_parent_phases(rc, NULL, kvm_arm_gic_reset_hold, NULL,
57
+ &kgc->parent_phases);
58
}
59
60
static const TypeInfo kvm_arm_gic_info = {
61
--
61
--
62
2.17.0
62
2.25.1
63
63
64
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
[PULL 21/29] hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
Convert the TYPE_ARM_GICV3_COMMON parent class to 3-phase reset.
2
to diagnose problems, but sometimes you want to see the state of
3
the floating point registers as well. We don't want to enable that
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
6
2
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20221109161444.3397405-6-peter.maydell@linaro.org
10
---
7
---
11
include/qemu/log.h | 1 +
8
hw/intc/arm_gicv3_common.c | 7 ++++---
12
accel/tcg/cpu-exec.c | 9 ++++++---
9
1 file changed, 4 insertions(+), 3 deletions(-)
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
10
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
11
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
13
--- a/hw/intc/arm_gicv3_common.c
19
+++ b/include/qemu/log.h
14
+++ b/hw/intc/arm_gicv3_common.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
15
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_finalize(Object *obj)
21
#define CPU_LOG_PAGE (1 << 14)
16
g_free(s->redist_region_count);
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
17
}
23
#define CPU_LOG_TB_OP_IND (1 << 16)
18
24
+#define CPU_LOG_TB_FPU (1 << 17)
19
-static void arm_gicv3_common_reset(DeviceState *dev)
25
20
+static void arm_gicv3_common_reset_hold(Object *obj)
26
/* Lock output for a series of related logs. Since this is not needed
21
{
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
22
- GICv3State *s = ARM_GICV3_COMMON(dev);
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
23
+ GICv3State *s = ARM_GICV3_COMMON(obj);
29
index XXXXXXX..XXXXXXX 100644
24
int i;
30
--- a/accel/tcg/cpu-exec.c
25
31
+++ b/accel/tcg/cpu-exec.c
26
for (i = 0; i < s->num_cpu; i++) {
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
27
@@ -XXX,XX +XXX,XX @@ static Property arm_gicv3_common_properties[] = {
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
28
static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
34
&& qemu_log_in_addr_range(itb->pc)) {
29
{
35
qemu_log_lock();
30
DeviceClass *dc = DEVICE_CLASS(klass);
36
+ int flags = 0;
31
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
32
ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
38
+ flags |= CPU_DUMP_FPU;
33
39
+ }
34
- dc->reset = arm_gicv3_common_reset;
40
#if defined(TARGET_I386)
35
+ rc->phases.hold = arm_gicv3_common_reset_hold;
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
36
dc->realize = arm_gicv3_common_realize;
42
-#else
37
device_class_set_props(dc, arm_gicv3_common_properties);
43
- log_cpu_state(cpu, 0);
38
dc->vmsd = &vmstate_gicv3;
44
+ flags |= CPU_DUMP_CCOP;
45
#endif
46
+ log_cpu_state(cpu, flags);
47
qemu_log_unlock();
48
}
49
#endif /* DEBUG_DISAS */
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
63
--
39
--
64
2.17.0
40
2.25.1
65
41
66
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
[PULL 22/29] hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Convert the TYPE_KVM_ARM_GICV3 device to 3-phase reset.
2
2
3
These were missed out from the rest of the half-precision work.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20221109161444.3397405-7-peter.maydell@linaro.org
7
---
8
hw/intc/arm_gicv3_kvm.c | 14 +++++++++-----
9
1 file changed, 9 insertions(+), 5 deletions(-)
4
10
5
Cc: qemu-stable@nongnu.org
11
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
16
1 file changed, 25 insertions(+), 6 deletions(-)
17
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
13
--- a/hw/intc/arm_gicv3_kvm.c
21
+++ b/target/arm/translate-a64.c
14
+++ b/hw/intc/arm_gicv3_kvm.c
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
15
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3State, KVMARMGICv3Class,
23
unsigned int mos, type, rm, cond, rn, rd;
16
struct KVMARMGICv3Class {
24
TCGv_i64 t_true, t_false, t_zero;
17
ARMGICv3CommonClass parent_class;
25
DisasCompare64 c;
18
DeviceRealize parent_realize;
26
+ TCGMemOp sz;
19
- void (*parent_reset)(DeviceState *dev);
27
20
+ ResettablePhases parent_phases;
28
mos = extract32(insn, 29, 3);
21
};
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
22
30
+ type = extract32(insn, 22, 2);
23
static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
31
rm = extract32(insn, 16, 5);
24
@@ -XXX,XX +XXX,XX @@ static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
32
cond = extract32(insn, 12, 4);
25
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
33
rn = extract32(insn, 5, 5);
26
}
34
rd = extract32(insn, 0, 5);
27
35
28
-static void kvm_arm_gicv3_reset(DeviceState *dev)
36
- if (mos || type > 1) {
29
+static void kvm_arm_gicv3_reset_hold(Object *obj)
37
+ if (mos) {
30
{
38
+ unallocated_encoding(s);
31
- GICv3State *s = ARM_GICV3_COMMON(dev);
39
+ return;
32
+ GICv3State *s = ARM_GICV3_COMMON(obj);
33
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_GET_CLASS(s);
34
35
DPRINTF("Reset\n");
36
37
- kgc->parent_reset(dev);
38
+ if (kgc->parent_phases.hold) {
39
+ kgc->parent_phases.hold(obj);
40
+ }
40
+ }
41
+
41
42
+ switch (type) {
42
if (s->migration_blocker) {
43
+ case 0:
43
DPRINTF("Cannot put kernel gic state, no kernel interface\n");
44
+ sz = MO_32;
44
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
45
+ break;
45
static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
46
+ case 1:
46
{
47
+ sz = MO_64;
47
DeviceClass *dc = DEVICE_CLASS(klass);
48
+ break;
48
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
49
+ case 3:
49
ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
50
+ sz = MO_16;
50
KVMARMGICv3Class *kgc = KVM_ARM_GICV3_CLASS(klass);
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
51
52
+ break;
52
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
53
+ }
53
agcc->post_load = kvm_arm_gicv3_put;
54
+ /* fallthru */
54
device_class_set_parent_realize(dc, kvm_arm_gicv3_realize,
55
+ default:
55
&kgc->parent_realize);
56
unallocated_encoding(s);
56
- device_class_set_parent_reset(dc, kvm_arm_gicv3_reset, &kgc->parent_reset);
57
return;
57
+ resettable_class_set_parent_phases(rc, NULL, kvm_arm_gicv3_reset_hold, NULL,
58
}
58
+ &kgc->parent_phases);
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
59
}
60
return;
60
61
}
61
static const TypeInfo kvm_arm_gicv3_info = {
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
83
--
62
--
84
2.17.0
63
2.25.1
85
64
86
65
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
[PULL 23/29] hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Convert the TYPE_ARM_GICV3_ITS_COMMON parent class to 3-phase reset.
2
2
3
We missed all of the scalar fp16 binary operations.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20221109161444.3397405-8-peter.maydell@linaro.org
7
---
8
hw/intc/arm_gicv3_its_common.c | 7 ++++---
9
1 file changed, 4 insertions(+), 3 deletions(-)
4
10
5
Cc: qemu-stable@nongnu.org
11
diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
13
1 file changed, 65 insertions(+)
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
13
--- a/hw/intc/arm_gicv3_its_common.c
18
+++ b/target/arm/translate-a64.c
14
+++ b/hw/intc/arm_gicv3_its_common.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
15
@@ -XXX,XX +XXX,XX @@ void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
20
tcg_temp_free_i64(tcg_res);
16
msi_nonbroken = true;
21
}
17
}
22
18
23
+/* Floating-point data-processing (2 source) - half precision */
19
-static void gicv3_its_common_reset(DeviceState *dev)
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
20
+static void gicv3_its_common_reset_hold(Object *obj)
25
+ int rd, int rn, int rm)
21
{
26
+{
22
- GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
27
+ TCGv_i32 tcg_op1;
23
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
28
+ TCGv_i32 tcg_op2;
24
29
+ TCGv_i32 tcg_res;
25
s->ctlr = 0;
30
+ TCGv_ptr fpst;
26
s->cbaser = 0;
31
+
27
@@ -XXX,XX +XXX,XX @@ static void gicv3_its_common_reset(DeviceState *dev)
32
+ tcg_res = tcg_temp_new_i32();
28
static void gicv3_its_common_class_init(ObjectClass *klass, void *data)
33
+ fpst = get_fpstatus_ptr(true);
29
{
34
+ tcg_op1 = read_fp_hreg(s, rn);
30
DeviceClass *dc = DEVICE_CLASS(klass);
35
+ tcg_op2 = read_fp_hreg(s, rm);
31
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
36
+
32
37
+ switch (opcode) {
33
- dc->reset = gicv3_its_common_reset;
38
+ case 0x0: /* FMUL */
34
+ rc->phases.hold = gicv3_its_common_reset_hold;
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
35
dc->vmsd = &vmstate_its;
40
+ break;
36
}
41
+ case 0x1: /* FDIV */
37
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
77
+
78
/* Floating point data-processing (2 source)
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
82
}
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
84
break;
85
+ case 3:
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
87
+ unallocated_encoding(s);
88
+ return;
89
+ }
90
+ if (!fp_access_check(s)) {
91
+ return;
92
+ }
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
94
+ break;
95
default:
96
unallocated_encoding(s);
97
}
98
--
38
--
99
2.17.0
39
2.25.1
100
40
101
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
[PULL 24/29] hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
1
From: Alex Bennée <alex.bennee@linaro.org>
1
Convert the TYPE_ARM_GICV3_ITS device to 3-phase reset.
2
2
3
These where missed out from the rest of the half-precision work.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20221109161444.3397405-9-peter.maydell@linaro.org
7
---
8
hw/intc/arm_gicv3_its.c | 14 +++++++++-----
9
1 file changed, 9 insertions(+), 5 deletions(-)
4
10
5
Cc: qemu-stable@nongnu.org
11
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/helper-a64.h | 2 +
16
target/arm/helper-a64.c | 10 +++++
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
21
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
13
--- a/hw/intc/arm_gicv3_its.c
23
+++ b/target/arm/helper-a64.h
14
+++ b/hw/intc/arm_gicv3_its.c
24
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
16
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
17
struct GICv3ITSClass {
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
18
GICv3ITSCommonClass parent_class;
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
19
- void (*parent_reset)(DeviceState *dev);
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
20
+ ResettablePhases parent_phases;
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
21
};
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
22
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
23
/*
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
24
@@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
36
+++ b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
38
return flags;
39
}
40
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
42
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
44
+}
45
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
52
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
25
}
60
}
26
}
61
27
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
28
-static void gicv3_its_reset(DeviceState *dev)
63
+static void handle_fp_compare(DisasContext *s, int size,
29
+static void gicv3_its_reset_hold(Object *obj)
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
30
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
31
- GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
32
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
33
GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
70
34
71
- if (is_double) {
35
- c->parent_reset(dev);
72
+ if (size == MO_64) {
36
+ if (c->parent_phases.hold) {
73
TCGv_i64 tcg_vn, tcg_vm;
37
+ c->parent_phases.hold(obj);
74
38
+ }
75
tcg_vn = read_fp_dreg(s, rn);
39
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
40
/* Quiescent bit reset to 1 */
77
tcg_temp_free_i64(tcg_vn);
41
s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
78
tcg_temp_free_i64(tcg_vm);
42
@@ -XXX,XX +XXX,XX @@ static Property gicv3_its_props[] = {
79
} else {
43
static void gicv3_its_class_init(ObjectClass *klass, void *data)
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
44
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
45
DeviceClass *dc = DEVICE_CLASS(klass);
124
+ int size;
46
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
125
47
GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
126
mos = extract32(insn, 29, 3);
48
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
49
128
+ type = extract32(insn, 22, 2);
50
dc->realize = gicv3_arm_its_realize;
129
rm = extract32(insn, 16, 5);
51
device_class_set_props(dc, gicv3_its_props);
130
op = extract32(insn, 14, 2);
52
- device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
131
rn = extract32(insn, 5, 5);
53
+ resettable_class_set_parent_phases(rc, NULL, gicv3_its_reset_hold, NULL,
132
opc = extract32(insn, 3, 2);
54
+ &ic->parent_phases);
133
op2r = extract32(insn, 0, 3);
55
icc->post_load = gicv3_its_post_load;
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
56
}
165
57
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
58
--
215
2.17.0
59
2.25.1
216
60
217
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
[PULL 25/29] hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
1
In float-to-integer conversion, if the floating point input
1
Convert the TYPE_KVM_ARM_ITS device to 3-phase reset.
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
2
9
Fix the boundary case to take the right half of the if()
10
statements.
11
12
This fixes a regression from 2.11 introduced by the softfloat
13
refactoring.
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
5
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
6
Message-id: 20221109161444.3397405-10-peter.maydell@linaro.org
20
---
7
---
21
fpu/softfloat.c | 4 ++--
8
hw/intc/arm_gicv3_its_kvm.c | 14 +++++++++-----
22
1 file changed, 2 insertions(+), 2 deletions(-)
9
1 file changed, 9 insertions(+), 5 deletions(-)
23
10
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
11
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
25
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
13
--- a/hw/intc/arm_gicv3_its_kvm.c
27
+++ b/fpu/softfloat.c
14
+++ b/hw/intc/arm_gicv3_its_kvm.c
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
15
@@ -XXX,XX +XXX,XX @@ DECLARE_OBJ_CHECKERS(GICv3ITSState, KVMARMITSClass,
29
r = UINT64_MAX;
16
30
}
17
struct KVMARMITSClass {
31
if (p.sign) {
18
GICv3ITSCommonClass parent_class;
32
- if (r < -(uint64_t) min) {
19
- void (*parent_reset)(DeviceState *dev);
33
+ if (r <= -(uint64_t) min) {
20
+ ResettablePhases parent_phases;
34
return -r;
21
};
35
} else {
22
36
s->float_exception_flags = orig_flags | float_flag_invalid;
23
37
return min;
24
@@ -XXX,XX +XXX,XX @@ static void kvm_arm_its_post_load(GICv3ITSState *s)
38
}
25
GITS_CTLR, &s->ctlr, true, &error_abort);
39
} else {
26
}
40
- if (r < max) {
27
41
+ if (r <= max) {
28
-static void kvm_arm_its_reset(DeviceState *dev)
42
return r;
29
+static void kvm_arm_its_reset_hold(Object *obj)
43
} else {
30
{
44
s->float_exception_flags = orig_flags | float_flag_invalid;
31
- GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
32
+ GICv3ITSState *s = ARM_GICV3_ITS_COMMON(obj);
33
KVMARMITSClass *c = KVM_ARM_ITS_GET_CLASS(s);
34
int i;
35
36
- c->parent_reset(dev);
37
+ if (c->parent_phases.hold) {
38
+ c->parent_phases.hold(obj);
39
+ }
40
41
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
42
KVM_DEV_ARM_ITS_CTRL_RESET)) {
43
@@ -XXX,XX +XXX,XX @@ static Property kvm_arm_its_props[] = {
44
static void kvm_arm_its_class_init(ObjectClass *klass, void *data)
45
{
46
DeviceClass *dc = DEVICE_CLASS(klass);
47
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
48
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
49
KVMARMITSClass *ic = KVM_ARM_ITS_CLASS(klass);
50
51
dc->realize = kvm_arm_its_realize;
52
device_class_set_props(dc, kvm_arm_its_props);
53
- device_class_set_parent_reset(dc, kvm_arm_its_reset, &ic->parent_reset);
54
+ resettable_class_set_parent_phases(rc, NULL, kvm_arm_its_reset_hold, NULL,
55
+ &ic->parent_phases);
56
icc->send_msi = kvm_its_send_msi;
57
icc->pre_save = kvm_arm_its_pre_save;
58
icc->post_load = kvm_arm_its_post_load;
45
--
59
--
46
2.17.0
60
2.25.1
47
61
48
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
[PULL 26/29] hw/arm/boot: set initrd with #address-cells type in fdt
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Schspa Shi <schspa@gmail.com>
2
2
3
No sense in emitting code after the exception.
3
We use 32bit value for linux,initrd-[start/end], when we have
4
loader_start > 4GB, there will be a wrong initrd_start passed
5
to the kernel, and the kernel will report the following warning.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
[ 0.000000] ------------[ cut here ]------------
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
[ 0.000000] initrd not fully accessible via the linear mapping -- please check your bootloader ...
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
9
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/arm64/mm/init.c:355 arm64_memblock_init+0x158/0x244
10
[ 0.000000] Modules linked in:
11
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Tainted: G W 6.1.0-rc3-13250-g30a0b95b1335-dirty #28
12
[ 0.000000] Hardware name: Horizon Sigi Virtual development board (DT)
13
[ 0.000000] pstate: 600000c5 (nZCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
14
[ 0.000000] pc : arm64_memblock_init+0x158/0x244
15
[ 0.000000] lr : arm64_memblock_init+0x158/0x244
16
[ 0.000000] sp : ffff800009273df0
17
[ 0.000000] x29: ffff800009273df0 x28: 0000001000cc0010 x27: 0000800000000000
18
[ 0.000000] x26: 000000000050a3e2 x25: ffff800008b46000 x24: ffff800008b46000
19
[ 0.000000] x23: ffff800008a53000 x22: ffff800009420000 x21: ffff800008a53000
20
[ 0.000000] x20: 0000000004000000 x19: 0000000004000000 x18: 00000000ffff1020
21
[ 0.000000] x17: 6568632065736165 x16: 6c70202d2d20676e x15: 697070616d207261
22
[ 0.000000] x14: 656e696c20656874 x13: 0a2e2e2e20726564 x12: 0000000000000000
23
[ 0.000000] x11: 0000000000000000 x10: 00000000ffffffff x9 : 0000000000000000
24
[ 0.000000] x8 : 0000000000000000 x7 : 796c6c756620746f x6 : 6e20647274696e69
25
[ 0.000000] x5 : ffff8000093c7c47 x4 : ffff800008a2102f x3 : ffff800009273a88
26
[ 0.000000] x2 : 80000000fffff038 x1 : 00000000000000c0 x0 : 0000000000000056
27
[ 0.000000] Call trace:
28
[ 0.000000] arm64_memblock_init+0x158/0x244
29
[ 0.000000] setup_arch+0x164/0x1cc
30
[ 0.000000] start_kernel+0x94/0x4ac
31
[ 0.000000] __primary_switched+0xb4/0xbc
32
[ 0.000000] ---[ end trace 0000000000000000 ]---
33
[ 0.000000] Zone ranges:
34
[ 0.000000] DMA [mem 0x0000001000000000-0x0000001007ffffff]
35
36
This doesn't affect any machine types we currently support, because
37
for all of our machine types the RAM starts well below the 4GB
38
mark, but it does demonstrate that we're not currently writing
39
the device-tree properties quite as intended.
40
41
To fix it, we can change it to write these values to the dtb using a
42
type width matching #address-cells. This is the intended size for
43
these dtb properties, and is how u-boot, for instance, writes them,
44
although in practice the Linux kernel will cope with them being any
45
width as long as they're big enough to fit the value.
46
47
Signed-off-by: Schspa Shi <schspa@gmail.com>
48
Message-id: 20221129160724.75667-1-schspa@gmail.com
49
[PMM: tweaked commit message]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
50
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
51
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
52
---
11
target/arm/translate-a64.c | 2 +-
53
hw/arm/boot.c | 10 ++++++----
12
1 file changed, 1 insertion(+), 1 deletion(-)
54
1 file changed, 6 insertions(+), 4 deletions(-)
13
55
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
56
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
15
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
58
--- a/hw/arm/boot.c
17
+++ b/target/arm/translate-a64.c
59
+++ b/hw/arm/boot.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
60
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
19
default:
61
}
20
/* all other sf/type/rmode combinations are invalid */
62
21
unallocated_encoding(s);
63
if (binfo->initrd_size) {
22
- break;
64
- rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
23
+ return;
65
- binfo->initrd_start);
66
+ rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
67
+ acells, binfo->initrd_start);
68
if (rc < 0) {
69
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
70
goto fail;
24
}
71
}
25
72
26
if (!fp_access_check(s)) {
73
- rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
74
- binfo->initrd_start + binfo->initrd_size);
75
+ rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
76
+ acells,
77
+ binfo->initrd_start +
78
+ binfo->initrd_size);
79
if (rc < 0) {
80
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
81
goto fail;
27
--
82
--
28
2.17.0
83
2.25.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
[PULL 27/29] target/arm: align exposed ID registers with Linux
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Zhuojia Shen <chaosdefinition@hotmail.com>
2
2
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
3
In CPUID registers exposed to userspace, some registers were missing
4
later on so we might as well mirror that.
4
and some fields were not exposed. This patch aligns exposed ID
5
registers and their fields with what the upstream kernel currently
6
exposes.
5
7
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Specifically, the following new ID registers/fields are exposed to
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
userspace:
10
11
ID_AA64PFR1_EL1.BT: bits 3-0
12
ID_AA64PFR1_EL1.MTE: bits 11-8
13
ID_AA64PFR1_EL1.SME: bits 27-24
14
15
ID_AA64ZFR0_EL1.SVEver: bits 3-0
16
ID_AA64ZFR0_EL1.AES: bits 7-4
17
ID_AA64ZFR0_EL1.BitPerm: bits 19-16
18
ID_AA64ZFR0_EL1.BF16: bits 23-20
19
ID_AA64ZFR0_EL1.SHA3: bits 35-32
20
ID_AA64ZFR0_EL1.SM4: bits 43-40
21
ID_AA64ZFR0_EL1.I8MM: bits 47-44
22
ID_AA64ZFR0_EL1.F32MM: bits 55-52
23
ID_AA64ZFR0_EL1.F64MM: bits 59-56
24
25
ID_AA64SMFR0_EL1.F32F32: bit 32
26
ID_AA64SMFR0_EL1.B16F32: bit 34
27
ID_AA64SMFR0_EL1.F16F32: bit 35
28
ID_AA64SMFR0_EL1.I8I32: bits 39-36
29
ID_AA64SMFR0_EL1.F64F64: bit 48
30
ID_AA64SMFR0_EL1.I16I64: bits 55-52
31
ID_AA64SMFR0_EL1.FA64: bit 63
32
33
ID_AA64MMFR0_EL1.ECV: bits 63-60
34
35
ID_AA64MMFR1_EL1.AFP: bits 47-44
36
37
ID_AA64MMFR2_EL1.AT: bits 35-32
38
39
ID_AA64ISAR0_EL1.RNDR: bits 63-60
40
41
ID_AA64ISAR1_EL1.FRINTTS: bits 35-32
42
ID_AA64ISAR1_EL1.BF16: bits 47-44
43
ID_AA64ISAR1_EL1.DGH: bits 51-48
44
ID_AA64ISAR1_EL1.I8MM: bits 55-52
45
46
ID_AA64ISAR2_EL1.WFxT: bits 3-0
47
ID_AA64ISAR2_EL1.RPRES: bits 7-4
48
ID_AA64ISAR2_EL1.GPA3: bits 11-8
49
ID_AA64ISAR2_EL1.APA3: bits 15-12
50
51
The code is also refactored to use symbolic names for ID register fields
52
for better readability and maintainability.
53
54
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
55
Message-id: DS7PR12MB6309BC9133877BCC6FC419FEAC0D9@DS7PR12MB6309.namprd12.prod.outlook.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
56
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
57
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
58
---
11
fpu/softfloat.c | 2 +-
59
target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++--------
12
1 file changed, 1 insertion(+), 1 deletion(-)
60
1 file changed, 79 insertions(+), 17 deletions(-)
13
61
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
62
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
64
--- a/target/arm/helper.c
17
+++ b/fpu/softfloat.c
65
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
19
67
#ifdef CONFIG_USER_ONLY
20
static FloatParts int_to_float(int64_t a, float_status *status)
68
static const ARMCPRegUserSpaceInfo v8_user_idregs[] = {
21
{
69
{ .name = "ID_AA64PFR0_EL1",
22
- FloatParts r;
70
- .exported_bits = 0x000f000f00ff0000,
23
+ FloatParts r = {};
71
- .fixed_bits = 0x0000000000000011 },
24
if (a == 0) {
72
+ .exported_bits = R_ID_AA64PFR0_FP_MASK |
25
r.cls = float_class_zero;
73
+ R_ID_AA64PFR0_ADVSIMD_MASK |
26
r.sign = false;
74
+ R_ID_AA64PFR0_SVE_MASK |
75
+ R_ID_AA64PFR0_DIT_MASK,
76
+ .fixed_bits = (0x1 << R_ID_AA64PFR0_EL0_SHIFT) |
77
+ (0x1 << R_ID_AA64PFR0_EL1_SHIFT) },
78
{ .name = "ID_AA64PFR1_EL1",
79
- .exported_bits = 0x00000000000000f0 },
80
+ .exported_bits = R_ID_AA64PFR1_BT_MASK |
81
+ R_ID_AA64PFR1_SSBS_MASK |
82
+ R_ID_AA64PFR1_MTE_MASK |
83
+ R_ID_AA64PFR1_SME_MASK },
84
{ .name = "ID_AA64PFR*_EL1_RESERVED",
85
- .is_glob = true },
86
- { .name = "ID_AA64ZFR0_EL1" },
87
+ .is_glob = true },
88
+ { .name = "ID_AA64ZFR0_EL1",
89
+ .exported_bits = R_ID_AA64ZFR0_SVEVER_MASK |
90
+ R_ID_AA64ZFR0_AES_MASK |
91
+ R_ID_AA64ZFR0_BITPERM_MASK |
92
+ R_ID_AA64ZFR0_BFLOAT16_MASK |
93
+ R_ID_AA64ZFR0_SHA3_MASK |
94
+ R_ID_AA64ZFR0_SM4_MASK |
95
+ R_ID_AA64ZFR0_I8MM_MASK |
96
+ R_ID_AA64ZFR0_F32MM_MASK |
97
+ R_ID_AA64ZFR0_F64MM_MASK },
98
+ { .name = "ID_AA64SMFR0_EL1",
99
+ .exported_bits = R_ID_AA64SMFR0_F32F32_MASK |
100
+ R_ID_AA64SMFR0_B16F32_MASK |
101
+ R_ID_AA64SMFR0_F16F32_MASK |
102
+ R_ID_AA64SMFR0_I8I32_MASK |
103
+ R_ID_AA64SMFR0_F64F64_MASK |
104
+ R_ID_AA64SMFR0_I16I64_MASK |
105
+ R_ID_AA64SMFR0_FA64_MASK },
106
{ .name = "ID_AA64MMFR0_EL1",
107
- .fixed_bits = 0x00000000ff000000 },
108
- { .name = "ID_AA64MMFR1_EL1" },
109
+ .exported_bits = R_ID_AA64MMFR0_ECV_MASK,
110
+ .fixed_bits = (0xf << R_ID_AA64MMFR0_TGRAN64_SHIFT) |
111
+ (0xf << R_ID_AA64MMFR0_TGRAN4_SHIFT) },
112
+ { .name = "ID_AA64MMFR1_EL1",
113
+ .exported_bits = R_ID_AA64MMFR1_AFP_MASK },
114
+ { .name = "ID_AA64MMFR2_EL1",
115
+ .exported_bits = R_ID_AA64MMFR2_AT_MASK },
116
{ .name = "ID_AA64MMFR*_EL1_RESERVED",
117
- .is_glob = true },
118
+ .is_glob = true },
119
{ .name = "ID_AA64DFR0_EL1",
120
- .fixed_bits = 0x0000000000000006 },
121
- { .name = "ID_AA64DFR1_EL1" },
122
+ .fixed_bits = (0x6 << R_ID_AA64DFR0_DEBUGVER_SHIFT) },
123
+ { .name = "ID_AA64DFR1_EL1" },
124
{ .name = "ID_AA64DFR*_EL1_RESERVED",
125
- .is_glob = true },
126
+ .is_glob = true },
127
{ .name = "ID_AA64AFR*",
128
- .is_glob = true },
129
+ .is_glob = true },
130
{ .name = "ID_AA64ISAR0_EL1",
131
- .exported_bits = 0x00fffffff0fffff0 },
132
+ .exported_bits = R_ID_AA64ISAR0_AES_MASK |
133
+ R_ID_AA64ISAR0_SHA1_MASK |
134
+ R_ID_AA64ISAR0_SHA2_MASK |
135
+ R_ID_AA64ISAR0_CRC32_MASK |
136
+ R_ID_AA64ISAR0_ATOMIC_MASK |
137
+ R_ID_AA64ISAR0_RDM_MASK |
138
+ R_ID_AA64ISAR0_SHA3_MASK |
139
+ R_ID_AA64ISAR0_SM3_MASK |
140
+ R_ID_AA64ISAR0_SM4_MASK |
141
+ R_ID_AA64ISAR0_DP_MASK |
142
+ R_ID_AA64ISAR0_FHM_MASK |
143
+ R_ID_AA64ISAR0_TS_MASK |
144
+ R_ID_AA64ISAR0_RNDR_MASK },
145
{ .name = "ID_AA64ISAR1_EL1",
146
- .exported_bits = 0x000000f0ffffffff },
147
+ .exported_bits = R_ID_AA64ISAR1_DPB_MASK |
148
+ R_ID_AA64ISAR1_APA_MASK |
149
+ R_ID_AA64ISAR1_API_MASK |
150
+ R_ID_AA64ISAR1_JSCVT_MASK |
151
+ R_ID_AA64ISAR1_FCMA_MASK |
152
+ R_ID_AA64ISAR1_LRCPC_MASK |
153
+ R_ID_AA64ISAR1_GPA_MASK |
154
+ R_ID_AA64ISAR1_GPI_MASK |
155
+ R_ID_AA64ISAR1_FRINTTS_MASK |
156
+ R_ID_AA64ISAR1_SB_MASK |
157
+ R_ID_AA64ISAR1_BF16_MASK |
158
+ R_ID_AA64ISAR1_DGH_MASK |
159
+ R_ID_AA64ISAR1_I8MM_MASK },
160
+ { .name = "ID_AA64ISAR2_EL1",
161
+ .exported_bits = R_ID_AA64ISAR2_WFXT_MASK |
162
+ R_ID_AA64ISAR2_RPRES_MASK |
163
+ R_ID_AA64ISAR2_GPA3_MASK |
164
+ R_ID_AA64ISAR2_APA3_MASK },
165
{ .name = "ID_AA64ISAR*_EL1_RESERVED",
166
- .is_glob = true },
167
+ .is_glob = true },
168
};
169
modify_arm_cp_regs(v8_idregs, v8_user_idregs);
170
#endif
171
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
172
#ifdef CONFIG_USER_ONLY
173
static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = {
174
{ .name = "MIDR_EL1",
175
- .exported_bits = 0x00000000ffffffff },
176
- { .name = "REVIDR_EL1" },
177
+ .exported_bits = R_MIDR_EL1_REVISION_MASK |
178
+ R_MIDR_EL1_PARTNUM_MASK |
179
+ R_MIDR_EL1_ARCHITECTURE_MASK |
180
+ R_MIDR_EL1_VARIANT_MASK |
181
+ R_MIDR_EL1_IMPLEMENTER_MASK },
182
+ { .name = "REVIDR_EL1" },
183
};
184
modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo);
185
#endif
27
--
186
--
28
2.17.0
187
2.25.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
[PULL 28/29] hw/misc: Move some arm-related files from specific_ss into softmmu_ss
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Thomas Huth <thuth@redhat.com>
2
2
3
Cc: qemu-stable@nongnu.org
3
The header target/arm/kvm-consts.h checks CONFIG_KVM which is marked as
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
poisoned in common code, so the files that include this header have to
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
be added to specific_ss and recompiled for each, qemu-system-arm and
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
qemu-system-aarch64. However, since the kvm headers are only optionally
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
7
used in kvm-constants.h for some sanity checks, we can additionally
8
check the NEED_CPU_H macro first to avoid the poisoned CONFIG_KVM macro,
9
so kvm-constants.h can also be used from "common" files (without the
10
sanity checks - which should be OK since they are still done from other
11
target-specific files instead). This way, and by adjusting some other
12
include statements in the related files here and there, we can move some
13
files from specific_ss into softmmu_ss, so that they only need to be
14
compiled once during the build process.
15
16
Signed-off-by: Thomas Huth <thuth@redhat.com>
17
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
18
Message-id: 20221202154023.293614-1-thuth@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
20
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
21
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +-
11
1 file changed, 15 insertions(+), 2 deletions(-)
22
target/arm/kvm-consts.h | 8 ++++----
23
hw/misc/imx6_src.c | 2 +-
24
hw/misc/iotkit-sysctl.c | 1 -
25
hw/misc/meson.build | 11 +++++------
26
5 files changed, 11 insertions(+), 13 deletions(-)
12
27
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
28
diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
14
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
30
--- a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
16
+++ b/target/arm/translate-a64.c
31
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
32
@@ -XXX,XX +XXX,XX @@
18
bool sf = extract32(insn, 31, 1);
33
19
bool itof;
34
#include "hw/sysbus.h"
20
35
#include "hw/register.h"
21
- if (sbit || (type > 1)
36
-#include "target/arm/cpu.h"
22
- || (!sf && scale < 32)) {
37
+#include "target/arm/cpu-qom.h"
23
+ if (sbit || (!sf && scale < 32)) {
38
24
+ unallocated_encoding(s);
39
#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
25
+ return;
40
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
26
+ }
41
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
27
+
42
index XXXXXXX..XXXXXXX 100644
28
+ switch (type) {
43
--- a/target/arm/kvm-consts.h
29
+ case 0: /* float32 */
44
+++ b/target/arm/kvm-consts.h
30
+ case 1: /* float64 */
45
@@ -XXX,XX +XXX,XX @@
31
+ break;
46
#ifndef ARM_KVM_CONSTS_H
32
+ case 3: /* float16 */
47
#define ARM_KVM_CONSTS_H
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
48
34
+ break;
49
+#ifdef NEED_CPU_H
35
+ }
50
#ifdef CONFIG_KVM
36
+ /* fallthru */
51
#include <linux/kvm.h>
37
+ default:
52
#include <linux/psci.h>
38
unallocated_encoding(s);
53
-
39
return;
54
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(X != Y)
40
}
55
+#endif
56
+#endif
57
58
-#else
59
-
60
+#ifndef MISMATCH_CHECK
61
#define MISMATCH_CHECK(X, Y) QEMU_BUILD_BUG_ON(0)
62
-
63
#endif
64
65
#define CP_REG_SIZE_SHIFT 52
66
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/hw/misc/imx6_src.c
69
+++ b/hw/misc/imx6_src.c
70
@@ -XXX,XX +XXX,XX @@
71
#include "qemu/log.h"
72
#include "qemu/main-loop.h"
73
#include "qemu/module.h"
74
-#include "arm-powerctl.h"
75
+#include "target/arm/arm-powerctl.h"
76
#include "hw/core/cpu.h"
77
78
#ifndef DEBUG_IMX6_SRC
79
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
80
index XXXXXXX..XXXXXXX 100644
81
--- a/hw/misc/iotkit-sysctl.c
82
+++ b/hw/misc/iotkit-sysctl.c
83
@@ -XXX,XX +XXX,XX @@
84
#include "hw/qdev-properties.h"
85
#include "hw/arm/armsse-version.h"
86
#include "target/arm/arm-powerctl.h"
87
-#include "target/arm/cpu.h"
88
89
REG32(SECDBGSTAT, 0x0)
90
REG32(SECDBGSET, 0x4)
91
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
92
index XXXXXXX..XXXXXXX 100644
93
--- a/hw/misc/meson.build
94
+++ b/hw/misc/meson.build
95
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_IMX', if_true: files(
96
'imx25_ccm.c',
97
'imx31_ccm.c',
98
'imx6_ccm.c',
99
+ 'imx6_src.c',
100
'imx6ul_ccm.c',
101
'imx7_ccm.c',
102
'imx7_gpr.c',
103
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
104
))
105
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
106
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
107
-specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
108
-specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
109
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
110
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
111
specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
112
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
113
'xlnx-versal-xramc.c',
114
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_TZ_MPC', if_true: files('tz-mpc.c'))
115
softmmu_ss.add(when: 'CONFIG_TZ_MSC', if_true: files('tz-msc.c'))
116
softmmu_ss.add(when: 'CONFIG_TZ_PPC', if_true: files('tz-ppc.c'))
117
softmmu_ss.add(when: 'CONFIG_IOTKIT_SECCTL', if_true: files('iotkit-secctl.c'))
118
+softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
119
softmmu_ss.add(when: 'CONFIG_IOTKIT_SYSINFO', if_true: files('iotkit-sysinfo.c'))
120
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPU_PWRCTRL', if_true: files('armsse-cpu-pwrctrl.c'))
121
softmmu_ss.add(when: 'CONFIG_ARMSSE_CPUID', if_true: files('armsse-cpuid.c'))
122
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))
123
124
specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))
125
126
-specific_ss.add(when: 'CONFIG_IMX', if_true: files('imx6_src.c'))
127
-specific_ss.add(when: 'CONFIG_IOTKIT_SYSCTL', if_true: files('iotkit-sysctl.c'))
128
-
129
specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
130
131
specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_cmgcr.c', 'mips_cpc.c'))
132
specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c'))
133
134
-specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
135
+softmmu_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c'))
136
137
# HPPA devices
138
softmmu_ss.add(when: 'CONFIG_LASI', if_true: files('lasi.c'))
41
--
139
--
42
2.17.0
140
2.25.1
43
141
44
142
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
[PULL 29/29] target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
From: Philippe Mathieu-Daudé <philmd@linaro.org>
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
8
2
9
Add the missing initialization.
3
When building with --disable-tcg on Darwin we get:
10
4
11
Fixes: d81ce0ef2c4f105
5
target/arm/cpu.c:725:16: error: incomplete definition of type 'struct TCGCPUOps'
12
Cc: qemu-stable@nongnu.org
6
cc->tcg_ops->do_interrupt(cs);
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
~~~~~~~~~~~^
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
9
Commit 083afd18a9 ("target/arm: Restrict cpu_exec_interrupt()
10
handler to sysemu") limited this block to system emulation,
11
but neglected to also limit it to TCG.
12
13
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
Reviewed-by: Fabiano Rosas <farosas@suse.de>
15
Message-id: 20221209110823.59495-1-philmd@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
17
---
18
target/arm/cpu.c | 2 ++
18
target/arm/cpu.c | 5 +++--
19
1 file changed, 2 insertions(+)
19
1 file changed, 3 insertions(+), 2 deletions(-)
20
20
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
22
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
23
--- a/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
26
&env->vfp.fp_status);
26
arm_rebuild_hflags(env);
27
set_float_detect_tininess(float_tininess_before_rounding,
27
}
28
&env->vfp.standard_fp_status);
28
29
+ set_float_detect_tininess(float_tininess_before_rounding,
29
-#ifndef CONFIG_USER_ONLY
30
+ &env->vfp.fp_status_f16);
30
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
31
#ifndef CONFIG_USER_ONLY
31
32
if (kvm_enabled()) {
32
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
33
kvm_arm_reset_vcpu(cpu);
33
unsigned int target_el,
34
@@ -XXX,XX +XXX,XX @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
35
cc->tcg_ops->do_interrupt(cs);
36
return true;
37
}
38
-#endif /* !CONFIG_USER_ONLY */
39
+
40
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
41
42
void arm_cpu_update_virq(ARMCPU *cpu)
43
{
34
--
44
--
35
2.17.0
45
2.25.1
36
46
37
47
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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