The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

* Fix coverity nit in int_to_float code

* Don't set Invalid for float-to-int(MAXINT)

* Fix fp_status_f16 tininess before rounding

* Add various missing insns from the v8.2-FP16 extension

* Fix sqrt_f16 exception raising

* sdcard: Correct CRC16 offset in sd_function_switch()

* tcg: Optionally log FPU state in TCG -d cpu logging

Alex Bennée (5):

fpu/softfloat: int_to_float ensure r fully initialised

target/arm: Implement FCMP for fp16

target/arm: Implement FCSEL for fp16

target/arm: Implement FMOV (immediate) for fp16

target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):

fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

target/arm: Fix fp_status_f16 tininess before rounding

tcg: Optionally log FPU state in TCG -d cpu logging

Philippe Mathieu-Daudé (1):

sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):

target/arm: Implement FMOV (general) for fp16

target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

target/arm: Implement FCVT (scalar, integer) for fp16

target/arm: Implement FCVT (scalar, fixed-point) for fp16

target/arm: Introduce and use read_fp_hreg

target/arm: Implement FP data-processing (2 source) for fp16

target/arm: Implement FP data-processing (3 source) for fp16

include/qemu/log.h | 1 +

target/arm/helper-a64.h | 2 +

target/arm/helper.h | 6 +

accel/tcg/cpu-exec.c | 9 +-

fpu/softfloat.c | 6 +-

hw/sd/sd.c | 2 +-

target/arm/cpu.c | 2 +

target/arm/helper-a64.c | 10 ++

target/arm/helper.c | 38 +++-

target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------

util/log.c | 2 +

11 files changed, 428 insertions(+), 71 deletions(-)

Adding the fp16 moves to/from general registers.

Cc: qemu-stable@nongnu.org

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-2-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/translate-a64.c | 21 +++++++++++++++++++++

1 file changed, 21 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)

tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));

clear_vec_high(s, true, rd);

break;

+ case 3:

+ /* 16 bit */

+ tmp = tcg_temp_new_i64();

+ tcg_gen_ext16u_i64(tmp, tcg_rn);

+ write_fp_dreg(s, rd, tmp);

+ tcg_temp_free_i64(tmp);

+ break;

+ default:

+ g_assert_not_reached();

}

} else {

TCGv_i64 tcg_rd = cpu_reg(s, rd);

@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)

/* 64 bits from top half */

tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));

break;

+ case 3:

+ /* 16 bit */

+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));

+ break;

+ default:

+ g_assert_not_reached();

}

}

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)

case 0xa: /* 64 bit */

case 0xd: /* 64 bit to top half of quad */

break;

+ case 0x6: /* 16-bit float, 32-bit int */

+ case 0xe: /* 16-bit float, 64-bit int */

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ }

+ /* fallthru */

default:

/* all other sf/type/rmode combinations are invalid */

unallocated_encoding(s);

2.17.0

Usually the logging of the CPU state produced by -d cpu is sufficient

to diagnose problems, but sometimes you want to see the state of

the floating point registers as well. We don't want to enable that

by default as it adds a lot of extra data to the log; instead,

allow it to be optionally enabled via -d fpu.

include/qemu/log.h | 1 +

accel/tcg/cpu-exec.c | 9 ++++++---

util/log.c | 2 ++

3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/qemu/log.h b/include/qemu/log.h

--- a/include/qemu/log.h

+++ b/include/qemu/log.h

@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)

#define CPU_LOG_PAGE (1 << 14)

/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */

#define CPU_LOG_TB_OP_IND (1 << 16)

+#define CPU_LOG_TB_FPU (1 << 17)

/* Lock output for a series of related logs. Since this is not needed

* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)

if (qemu_loglevel_mask(CPU_LOG_TB_CPU)

&& qemu_log_in_addr_range(itb->pc)) {

qemu_log_lock();

+ int flags = 0;

+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {

+ flags |= CPU_DUMP_FPU;

+ }

#if defined(TARGET_I386)

- log_cpu_state(cpu, CPU_DUMP_CCOP);

-#else

- log_cpu_state(cpu, 0);

+ flags |= CPU_DUMP_CCOP;

#endif

+ log_cpu_state(cpu, flags);

qemu_log_unlock();

#endif /* DEBUG_DISAS */

diff --git a/util/log.c b/util/log.c

index XXXXXXX..XXXXXXX 100644

--- a/util/log.c

+++ b/util/log.c

@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {

"show trace before each executed TB (lots of logs)" },

{ CPU_LOG_TB_CPU, "cpu",

"show CPU registers before entering a TB (lots of logs)" },

+ { CPU_LOG_TB_FPU, "fpu",

+ "include FPU registers in the 'cpu' logging" },

{ CPU_LOG_MMU, "mmu",

"log MMU-related activities" },