| 1 | The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae: | 1 | This pullreq is (1) my GICv4 patches (2) most of the first third of RTH's |
|---|---|---|---|
| 2 | cleanup patchset (3) one patch fixing an smmuv3 bug... | ||
| 2 | 3 | ||
| 3 | Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100) | 4 | v2 changes: fix build failure on aarch64 hosts by moving the |
| 5 | gicv3_add_its() and gicv3_foreach_its() functions to | ||
| 6 | arm_gicv3_its_common.h. | ||
| 7 | |||
| 8 | thanks | ||
| 9 | -- PMM | ||
| 10 | |||
| 11 | |||
| 12 | The following changes since commit a74782936dc6e979ce371dabda4b1c05624ea87f: | ||
| 13 | |||
| 14 | Merge tag 'pull-migration-20220421a' of https://gitlab.com/dagrh/qemu into staging (2022-04-21 18:48:18 -0700) | ||
| 4 | 15 | ||
| 5 | are available in the Git repository at: | 16 | are available in the Git repository at: |
| 6 | 17 | ||
| 7 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515 | 18 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220422-1 |
| 8 | 19 | ||
| 9 | for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e: | 20 | for you to fetch changes up to c3ca7d56c4790c2223122f7e84b71161cd36dbce: |
| 10 | 21 | ||
| 11 | tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100) | 22 | hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() (2022-04-22 14:44:55 +0100) |
| 12 | 23 | ||
| 13 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 14 | target-arm queue: | 25 | target-arm queue: |
| 15 | * Fix coverity nit in int_to_float code | 26 | * Implement GICv4 emulation |
| 16 | * Don't set Invalid for float-to-int(MAXINT) | 27 | * Some cleanup patches in target/arm |
| 17 | * Fix fp_status_f16 tininess before rounding | 28 | * hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() |
| 18 | * Add various missing insns from the v8.2-FP16 extension | ||
| 19 | * Fix sqrt_f16 exception raising | ||
| 20 | * sdcard: Correct CRC16 offset in sd_function_switch() | ||
| 21 | * tcg: Optionally log FPU state in TCG -d cpu logging | ||
| 22 | 29 | ||
| 23 | ---------------------------------------------------------------- | 30 | ---------------------------------------------------------------- |
| 24 | Alex Bennée (5): | 31 | Peter Maydell (41): |
| 25 | fpu/softfloat: int_to_float ensure r fully initialised | 32 | hw/intc/arm_gicv3_its: Add missing blank line |
| 26 | target/arm: Implement FCMP for fp16 | 33 | hw/intc/arm_gicv3: Sanity-check num-cpu property |
| 27 | target/arm: Implement FCSEL for fp16 | 34 | hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count |
| 28 | target/arm: Implement FMOV (immediate) for fp16 | 35 | hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers |
| 29 | target/arm: Fix sqrt_f16 exception raising | 36 | target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 |
| 37 | hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?" | ||
| 38 | hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4 | ||
| 39 | hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI | ||
| 40 | hw/intc/arm_gicv3_its: Implement VMAPP | ||
| 41 | hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE | ||
| 42 | hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" | ||
| 43 | hw/intc/arm_gicv3_its: Factor out CTE lookup sequence | ||
| 44 | hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code | ||
| 45 | hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() | ||
| 46 | hw/intc/arm_gicv3: Keep pointers to every connected ITS | ||
| 47 | hw/intc/arm_gicv3_its: Implement VMOVP | ||
| 48 | hw/intc/arm_gicv3_its: Implement VSYNC | ||
| 49 | hw/intc/arm_gicv3_its: Implement INV command properly | ||
| 50 | hw/intc/arm_gicv3_its: Implement INV for virtual interrupts | ||
| 51 | hw/intc/arm_gicv3_its: Implement VMOVI | ||
| 52 | hw/intc/arm_gicv3_its: Implement VINVALL | ||
| 53 | hw/intc/arm_gicv3: Implement GICv4's new redistributor frame | ||
| 54 | hw/intc/arm_gicv3: Implement new GICv4 redistributor registers | ||
| 55 | hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() | ||
| 56 | hw/intc/arm_gicv3_cpuif: Support vLPIs | ||
| 57 | hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily | ||
| 58 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic | ||
| 59 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic | ||
| 60 | hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes | ||
| 61 | hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code | ||
| 62 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() | ||
| 63 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() | ||
| 64 | hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling | ||
| 65 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() | ||
| 66 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() | ||
| 67 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() | ||
| 68 | hw/intc/arm_gicv3: Update ID and feature registers for GICv4 | ||
| 69 | hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 | ||
| 70 | hw/arm/virt: Use VIRT_GIC_VERSION_* enum values in create_gic() | ||
| 71 | hw/arm/virt: Abstract out calculation of redistributor region capacity | ||
| 72 | hw/arm/virt: Support TCG GICv4 | ||
| 30 | 73 | ||
| 31 | Peter Maydell (3): | 74 | Richard Henderson (19): |
| 32 | fpu/softfloat: Don't set Invalid for float-to-int(MAXINT) | 75 | target/arm: Update ISAR fields for ARMv8.8 |
| 33 | target/arm: Fix fp_status_f16 tininess before rounding | 76 | target/arm: Update SCR_EL3 bits to ARMv8.8 |
| 34 | tcg: Optionally log FPU state in TCG -d cpu logging | 77 | target/arm: Update SCTLR bits to ARMv9.2 |
| 78 | target/arm: Change DisasContext.aarch64 to bool | ||
| 79 | target/arm: Change CPUArchState.aarch64 to bool | ||
| 80 | target/arm: Extend store_cpu_offset to take field size | ||
| 81 | target/arm: Change DisasContext.thumb to bool | ||
| 82 | target/arm: Change CPUArchState.thumb to bool | ||
| 83 | target/arm: Remove fpexc32_access | ||
| 84 | target/arm: Split out set_btype_raw | ||
| 85 | target/arm: Split out gen_rebuild_hflags | ||
| 86 | target/arm: Simplify GEN_SHIFT in translate.c | ||
| 87 | target/arm: Simplify gen_sar | ||
| 88 | target/arm: Simplify aa32 DISAS_WFI | ||
| 89 | target/arm: Use tcg_constant in translate-m-nocp.c | ||
| 90 | target/arm: Use tcg_constant in translate-neon.c | ||
| 91 | target/arm: Use smin/smax for do_sat_addsub_32 | ||
| 92 | target/arm: Use tcg_constant in translate-vfp.c | ||
| 93 | target/arm: Use tcg_constant_i32 in translate.h | ||
| 35 | 94 | ||
| 36 | Philippe Mathieu-Daudé (1): | 95 | Xiang Chen (1): |
| 37 | sdcard: Correct CRC16 offset in sd_function_switch() | 96 | hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate() |
| 38 | 97 | ||
| 39 | Richard Henderson (7): | 98 | docs/system/arm/virt.rst | 5 +- |
| 40 | target/arm: Implement FMOV (general) for fp16 | 99 | hw/intc/gicv3_internal.h | 213 +++++++- |
| 41 | target/arm: Early exit after unallocated_encoding in disas_fp_int_conv | 100 | include/hw/arm/virt.h | 19 +- |
| 42 | target/arm: Implement FCVT (scalar, integer) for fp16 | 101 | include/hw/intc/arm_gicv3_common.h | 13 + |
| 43 | target/arm: Implement FCVT (scalar, fixed-point) for fp16 | 102 | include/hw/intc/arm_gicv3_its_common.h | 19 + |
| 44 | target/arm: Introduce and use read_fp_hreg | 103 | target/arm/cpu.h | 59 ++- |
| 45 | target/arm: Implement FP data-processing (2 source) for fp16 | 104 | target/arm/translate-a32.h | 13 +- |
| 46 | target/arm: Implement FP data-processing (3 source) for fp16 | 105 | target/arm/translate.h | 17 +- |
| 47 | 106 | hw/arm/smmuv3.c | 2 +- | |
| 48 | include/qemu/log.h | 1 + | 107 | hw/arm/virt.c | 102 +++- |
| 49 | target/arm/helper-a64.h | 2 + | 108 | hw/intc/arm_gicv3_common.c | 54 +- |
| 50 | target/arm/helper.h | 6 + | 109 | hw/intc/arm_gicv3_cpuif.c | 195 ++++++-- |
| 51 | accel/tcg/cpu-exec.c | 9 +- | 110 | hw/intc/arm_gicv3_dist.c | 7 +- |
| 52 | fpu/softfloat.c | 6 +- | 111 | hw/intc/arm_gicv3_its.c | 876 +++++++++++++++++++++++++++------ |
| 53 | hw/sd/sd.c | 2 +- | 112 | hw/intc/arm_gicv3_its_kvm.c | 2 + |
| 54 | target/arm/cpu.c | 2 + | 113 | hw/intc/arm_gicv3_kvm.c | 5 + |
| 55 | target/arm/helper-a64.c | 10 ++ | 114 | hw/intc/arm_gicv3_redist.c | 480 +++++++++++++++--- |
| 56 | target/arm/helper.c | 38 +++- | 115 | linux-user/arm/cpu_loop.c | 2 +- |
| 57 | target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++------- | 116 | target/arm/cpu.c | 16 +- |
| 58 | util/log.c | 2 + | 117 | target/arm/helper-a64.c | 4 +- |
| 59 | 11 files changed, 428 insertions(+), 71 deletions(-) | 118 | target/arm/helper.c | 19 +- |
| 60 | 119 | target/arm/hvf/hvf.c | 2 +- | |
| 120 | target/arm/m_helper.c | 6 +- | ||
| 121 | target/arm/op_helper.c | 13 - | ||
| 122 | target/arm/translate-a64.c | 50 +- | ||
| 123 | target/arm/translate-m-nocp.c | 12 +- | ||
| 124 | target/arm/translate-neon.c | 21 +- | ||
| 125 | target/arm/translate-sve.c | 9 +- | ||
| 126 | target/arm/translate-vfp.c | 76 +-- | ||
| 127 | target/arm/translate.c | 101 ++-- | ||
| 128 | hw/intc/trace-events | 18 +- | ||
| 129 | 31 files changed, 1890 insertions(+), 540 deletions(-) | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
| 2 | 1 | ||
| 3 | Reported by Coverity (CID1390635). We ensure this for uint_to_float | ||
| 4 | later on so we might as well mirror that. | ||
| 5 | |||
| 6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | fpu/softfloat.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/fpu/softfloat.c | ||
| 17 | +++ b/fpu/softfloat.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64) | ||
| 19 | |||
| 20 | static FloatParts int_to_float(int64_t a, float_status *status) | ||
| 21 | { | ||
| 22 | - FloatParts r; | ||
| 23 | + FloatParts r = {}; | ||
| 24 | if (a == 0) { | ||
| 25 | r.cls = float_class_zero; | ||
| 26 | r.sign = false; | ||
| 27 | -- | ||
| 28 | 2.17.0 | ||
| 29 | |||
| 30 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In float-to-integer conversion, if the floating point input | ||
| 2 | converts exactly to the largest or smallest integer that | ||
| 3 | fits in to the result type, this is not an overflow. | ||
| 4 | In this situation we were producing the correct result value, | ||
| 5 | but were incorrectly setting the Invalid flag. | ||
| 6 | For example for Arm A64, "FCVTAS w0, d0" on an input of | ||
| 7 | 0x41dfffffffc00000 should produce 0x7fffffff and set no flags. | ||
| 8 | 1 | ||
| 9 | Fix the boundary case to take the right half of the if() | ||
| 10 | statements. | ||
| 11 | |||
| 12 | This fixes a regression from 2.11 introduced by the softfloat | ||
| 13 | refactoring. | ||
| 14 | |||
| 15 | Cc: qemu-stable@nongnu.org | ||
| 16 | Fixes: ab52f973a50 | ||
| 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 19 | Message-id: 20180510140141.12120-1-peter.maydell@linaro.org | ||
| 20 | --- | ||
| 21 | fpu/softfloat.c | 4 ++-- | ||
| 22 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 23 | |||
| 24 | diff --git a/fpu/softfloat.c b/fpu/softfloat.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/fpu/softfloat.c | ||
| 27 | +++ b/fpu/softfloat.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, | ||
| 29 | r = UINT64_MAX; | ||
| 30 | } | ||
| 31 | if (p.sign) { | ||
| 32 | - if (r < -(uint64_t) min) { | ||
| 33 | + if (r <= -(uint64_t) min) { | ||
| 34 | return -r; | ||
| 35 | } else { | ||
| 36 | s->float_exception_flags = orig_flags | float_flag_invalid; | ||
| 37 | return min; | ||
| 38 | } | ||
| 39 | } else { | ||
| 40 | - if (r < max) { | ||
| 41 | + if (r <= max) { | ||
| 42 | return r; | ||
| 43 | } else { | ||
| 44 | s->float_exception_flags = orig_flags | float_flag_invalid; | ||
| 45 | -- | ||
| 46 | 2.17.0 | ||
| 47 | |||
| 48 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In commit d81ce0ef2c4f105 we added an extra float_status field | ||
| 2 | fp_status_fp16 for Arm, but forgot to initialize it correctly | ||
| 3 | by setting it to float_tininess_before_rounding. This currently | ||
| 4 | will only cause problems for the new V8_FP16 feature, since the | ||
| 5 | float-to-float conversion code doesn't use it yet. The effect | ||
| 6 | would be that we failed to set the Underflow IEEE exception flag | ||
| 7 | in all the cases where we should. | ||
| 8 | 1 | ||
| 9 | Add the missing initialization. | ||
| 10 | |||
| 11 | Fixes: d81ce0ef2c4f105 | ||
| 12 | Cc: qemu-stable@nongnu.org | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Message-id: 20180512004311.9299-16-richard.henderson@linaro.org | ||
| 17 | --- | ||
| 18 | target/arm/cpu.c | 2 ++ | ||
| 19 | 1 file changed, 2 insertions(+) | ||
| 20 | |||
| 21 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/target/arm/cpu.c | ||
| 24 | +++ b/target/arm/cpu.c | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
| 26 | &env->vfp.fp_status); | ||
| 27 | set_float_detect_tininess(float_tininess_before_rounding, | ||
| 28 | &env->vfp.standard_fp_status); | ||
| 29 | + set_float_detect_tininess(float_tininess_before_rounding, | ||
| 30 | + &env->vfp.fp_status_f16); | ||
| 31 | #ifndef CONFIG_USER_ONLY | ||
| 32 | if (kvm_enabled()) { | ||
| 33 | kvm_arm_reset_vcpu(cpu); | ||
| 34 | -- | ||
| 35 | 2.17.0 | ||
| 36 | |||
| 37 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Adding the fp16 moves to/from general registers. | ||
| 4 | |||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 8 | Message-id: 20180512003217.9105-2-richard.henderson@linaro.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/translate-a64.c | 21 +++++++++++++++++++++ | ||
| 13 | 1 file changed, 21 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/translate-a64.c | ||
| 18 | +++ b/target/arm/translate-a64.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) | ||
| 20 | tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); | ||
| 21 | clear_vec_high(s, true, rd); | ||
| 22 | break; | ||
| 23 | + case 3: | ||
| 24 | + /* 16 bit */ | ||
| 25 | + tmp = tcg_temp_new_i64(); | ||
| 26 | + tcg_gen_ext16u_i64(tmp, tcg_rn); | ||
| 27 | + write_fp_dreg(s, rd, tmp); | ||
| 28 | + tcg_temp_free_i64(tmp); | ||
| 29 | + break; | ||
| 30 | + default: | ||
| 31 | + g_assert_not_reached(); | ||
| 32 | } | ||
| 33 | } else { | ||
| 34 | TCGv_i64 tcg_rd = cpu_reg(s, rd); | ||
| 35 | @@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) | ||
| 36 | /* 64 bits from top half */ | ||
| 37 | tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); | ||
| 38 | break; | ||
| 39 | + case 3: | ||
| 40 | + /* 16 bit */ | ||
| 41 | + tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)); | ||
| 42 | + break; | ||
| 43 | + default: | ||
| 44 | + g_assert_not_reached(); | ||
| 45 | } | ||
| 46 | } | ||
| 47 | } | ||
| 48 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | ||
| 49 | case 0xa: /* 64 bit */ | ||
| 50 | case 0xd: /* 64 bit to top half of quad */ | ||
| 51 | break; | ||
| 52 | + case 0x6: /* 16-bit float, 32-bit int */ | ||
| 53 | + case 0xe: /* 16-bit float, 64-bit int */ | ||
| 54 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 55 | + break; | ||
| 56 | + } | ||
| 57 | + /* fallthru */ | ||
| 58 | default: | ||
| 59 | /* all other sf/type/rmode combinations are invalid */ | ||
| 60 | unallocated_encoding(s); | ||
| 61 | -- | ||
| 62 | 2.17.0 | ||
| 63 | |||
| 64 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | No sense in emitting code after the exception. | ||
| 4 | |||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Message-id: 20180512003217.9105-3-richard.henderson@linaro.org | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/translate-a64.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/translate-a64.c | ||
| 17 | +++ b/target/arm/translate-a64.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | ||
| 19 | default: | ||
| 20 | /* all other sf/type/rmode combinations are invalid */ | ||
| 21 | unallocated_encoding(s); | ||
| 22 | - break; | ||
| 23 | + return; | ||
| 24 | } | ||
| 25 | |||
| 26 | if (!fp_access_check(s)) { | ||
| 27 | -- | ||
| 28 | 2.17.0 | ||
| 29 | |||
| 30 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Cc: qemu-stable@nongnu.org | ||
| 4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Message-id: 20180512003217.9105-4-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/helper.h | 6 +++ | ||
| 11 | target/arm/helper.c | 38 ++++++++++++++- | ||
| 12 | target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++------- | ||
| 13 | 3 files changed, 122 insertions(+), 18 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/helper.h | ||
| 18 | +++ b/target/arm/helper.h | ||
| 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) | ||
| 20 | DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) | ||
| 21 | DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) | ||
| 22 | DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) | ||
| 23 | +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) | ||
| 24 | +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) | ||
| 25 | +DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) | ||
| 26 | +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) | ||
| 27 | DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) | ||
| 28 | DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) | ||
| 29 | DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) | ||
| 30 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) | ||
| 31 | DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) | ||
| 32 | DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) | ||
| 33 | DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) | ||
| 34 | +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) | ||
| 35 | +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) | ||
| 36 | |||
| 37 | DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) | ||
| 38 | DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) | ||
| 39 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 40 | index XXXXXXX..XXXXXXX 100644 | ||
| 41 | --- a/target/arm/helper.c | ||
| 42 | +++ b/target/arm/helper.c | ||
| 43 | @@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) | ||
| 44 | #undef VFP_CONV_FIX_A64 | ||
| 45 | |||
| 46 | /* Conversion to/from f16 can overflow to infinity before/after scaling. | ||
| 47 | - * Therefore we convert to f64 (which does not round), scale, | ||
| 48 | - * and then convert f64 to f16 (which may round). | ||
| 49 | + * Therefore we convert to f64, scale, and then convert f64 to f16; or | ||
| 50 | + * vice versa for conversion to integer. | ||
| 51 | + * | ||
| 52 | + * For 16- and 32-bit integers, the conversion to f64 never rounds. | ||
| 53 | + * For 64-bit integers, any integer that would cause rounding will also | ||
| 54 | + * overflow to f16 infinity, so there is no double rounding problem. | ||
| 55 | */ | ||
| 56 | |||
| 57 | static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst) | ||
| 58 | @@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst) | ||
| 59 | return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst); | ||
| 60 | } | ||
| 61 | |||
| 62 | +float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst) | ||
| 63 | +{ | ||
| 64 | + return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst); | ||
| 65 | +} | ||
| 66 | + | ||
| 67 | +float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst) | ||
| 68 | +{ | ||
| 69 | + return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst); | ||
| 70 | +} | ||
| 71 | + | ||
| 72 | static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst) | ||
| 73 | { | ||
| 74 | if (unlikely(float16_is_any_nan(f))) { | ||
| 75 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst) | ||
| 76 | return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst); | ||
| 77 | } | ||
| 78 | |||
| 79 | +uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst) | ||
| 80 | +{ | ||
| 81 | + return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst); | ||
| 82 | +} | ||
| 83 | + | ||
| 84 | +uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst) | ||
| 85 | +{ | ||
| 86 | + return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst); | ||
| 87 | +} | ||
| 88 | + | ||
| 89 | +uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst) | ||
| 90 | +{ | ||
| 91 | + return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst); | ||
| 92 | +} | ||
| 93 | + | ||
| 94 | +uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst) | ||
| 95 | +{ | ||
| 96 | + return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst); | ||
| 97 | +} | ||
| 98 | + | ||
| 99 | /* Set the current fp rounding mode and return the old one. | ||
| 100 | * The argument is a softfloat float_round_ value. | ||
| 101 | */ | ||
| 102 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 103 | index XXXXXXX..XXXXXXX 100644 | ||
| 104 | --- a/target/arm/translate-a64.c | ||
| 105 | +++ b/target/arm/translate-a64.c | ||
| 106 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 107 | bool itof, int rmode, int scale, int sf, int type) | ||
| 108 | { | ||
| 109 | bool is_signed = !(opcode & 1); | ||
| 110 | - bool is_double = type; | ||
| 111 | TCGv_ptr tcg_fpstatus; | ||
| 112 | - TCGv_i32 tcg_shift; | ||
| 113 | + TCGv_i32 tcg_shift, tcg_single; | ||
| 114 | + TCGv_i64 tcg_double; | ||
| 115 | |||
| 116 | - tcg_fpstatus = get_fpstatus_ptr(false); | ||
| 117 | + tcg_fpstatus = get_fpstatus_ptr(type == 3); | ||
| 118 | |||
| 119 | tcg_shift = tcg_const_i32(64 - scale); | ||
| 120 | |||
| 121 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 122 | tcg_int = tcg_extend; | ||
| 123 | } | ||
| 124 | |||
| 125 | - if (is_double) { | ||
| 126 | - TCGv_i64 tcg_double = tcg_temp_new_i64(); | ||
| 127 | + switch (type) { | ||
| 128 | + case 1: /* float64 */ | ||
| 129 | + tcg_double = tcg_temp_new_i64(); | ||
| 130 | if (is_signed) { | ||
| 131 | gen_helper_vfp_sqtod(tcg_double, tcg_int, | ||
| 132 | tcg_shift, tcg_fpstatus); | ||
| 133 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 134 | } | ||
| 135 | write_fp_dreg(s, rd, tcg_double); | ||
| 136 | tcg_temp_free_i64(tcg_double); | ||
| 137 | - } else { | ||
| 138 | - TCGv_i32 tcg_single = tcg_temp_new_i32(); | ||
| 139 | + break; | ||
| 140 | + | ||
| 141 | + case 0: /* float32 */ | ||
| 142 | + tcg_single = tcg_temp_new_i32(); | ||
| 143 | if (is_signed) { | ||
| 144 | gen_helper_vfp_sqtos(tcg_single, tcg_int, | ||
| 145 | tcg_shift, tcg_fpstatus); | ||
| 146 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 147 | } | ||
| 148 | write_fp_sreg(s, rd, tcg_single); | ||
| 149 | tcg_temp_free_i32(tcg_single); | ||
| 150 | + break; | ||
| 151 | + | ||
| 152 | + case 3: /* float16 */ | ||
| 153 | + tcg_single = tcg_temp_new_i32(); | ||
| 154 | + if (is_signed) { | ||
| 155 | + gen_helper_vfp_sqtoh(tcg_single, tcg_int, | ||
| 156 | + tcg_shift, tcg_fpstatus); | ||
| 157 | + } else { | ||
| 158 | + gen_helper_vfp_uqtoh(tcg_single, tcg_int, | ||
| 159 | + tcg_shift, tcg_fpstatus); | ||
| 160 | + } | ||
| 161 | + write_fp_sreg(s, rd, tcg_single); | ||
| 162 | + tcg_temp_free_i32(tcg_single); | ||
| 163 | + break; | ||
| 164 | + | ||
| 165 | + default: | ||
| 166 | + g_assert_not_reached(); | ||
| 167 | } | ||
| 168 | } else { | ||
| 169 | TCGv_i64 tcg_int = cpu_reg(s, rd); | ||
| 170 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 171 | |||
| 172 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | ||
| 173 | |||
| 174 | - if (is_double) { | ||
| 175 | - TCGv_i64 tcg_double = read_fp_dreg(s, rn); | ||
| 176 | + switch (type) { | ||
| 177 | + case 1: /* float64 */ | ||
| 178 | + tcg_double = read_fp_dreg(s, rn); | ||
| 179 | if (is_signed) { | ||
| 180 | if (!sf) { | ||
| 181 | gen_helper_vfp_tosld(tcg_int, tcg_double, | ||
| 182 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 183 | tcg_shift, tcg_fpstatus); | ||
| 184 | } | ||
| 185 | } | ||
| 186 | + if (!sf) { | ||
| 187 | + tcg_gen_ext32u_i64(tcg_int, tcg_int); | ||
| 188 | + } | ||
| 189 | tcg_temp_free_i64(tcg_double); | ||
| 190 | - } else { | ||
| 191 | - TCGv_i32 tcg_single = read_fp_sreg(s, rn); | ||
| 192 | + break; | ||
| 193 | + | ||
| 194 | + case 0: /* float32 */ | ||
| 195 | + tcg_single = read_fp_sreg(s, rn); | ||
| 196 | if (sf) { | ||
| 197 | if (is_signed) { | ||
| 198 | gen_helper_vfp_tosqs(tcg_int, tcg_single, | ||
| 199 | @@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, | ||
| 200 | tcg_temp_free_i32(tcg_dest); | ||
| 201 | } | ||
| 202 | tcg_temp_free_i32(tcg_single); | ||
| 203 | + break; | ||
| 204 | + | ||
| 205 | + case 3: /* float16 */ | ||
| 206 | + tcg_single = read_fp_sreg(s, rn); | ||
| 207 | + if (sf) { | ||
| 208 | + if (is_signed) { | ||
| 209 | + gen_helper_vfp_tosqh(tcg_int, tcg_single, | ||
| 210 | + tcg_shift, tcg_fpstatus); | ||
| 211 | + } else { | ||
| 212 | + gen_helper_vfp_touqh(tcg_int, tcg_single, | ||
| 213 | + tcg_shift, tcg_fpstatus); | ||
| 214 | + } | ||
| 215 | + } else { | ||
| 216 | + TCGv_i32 tcg_dest = tcg_temp_new_i32(); | ||
| 217 | + if (is_signed) { | ||
| 218 | + gen_helper_vfp_toslh(tcg_dest, tcg_single, | ||
| 219 | + tcg_shift, tcg_fpstatus); | ||
| 220 | + } else { | ||
| 221 | + gen_helper_vfp_toulh(tcg_dest, tcg_single, | ||
| 222 | + tcg_shift, tcg_fpstatus); | ||
| 223 | + } | ||
| 224 | + tcg_gen_extu_i32_i64(tcg_int, tcg_dest); | ||
| 225 | + tcg_temp_free_i32(tcg_dest); | ||
| 226 | + } | ||
| 227 | + tcg_temp_free_i32(tcg_single); | ||
| 228 | + break; | ||
| 229 | + | ||
| 230 | + default: | ||
| 231 | + g_assert_not_reached(); | ||
| 232 | } | ||
| 233 | |||
| 234 | gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); | ||
| 235 | tcg_temp_free_i32(tcg_rmode); | ||
| 236 | - | ||
| 237 | - if (!sf) { | ||
| 238 | - tcg_gen_ext32u_i64(tcg_int, tcg_int); | ||
| 239 | - } | ||
| 240 | } | ||
| 241 | |||
| 242 | tcg_temp_free_ptr(tcg_fpstatus); | ||
| 243 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) | ||
| 244 | /* actual FP conversions */ | ||
| 245 | bool itof = extract32(opcode, 1, 1); | ||
| 246 | |||
| 247 | - if (type > 1 || (rmode != 0 && opcode > 1)) { | ||
| 248 | + if (rmode != 0 && opcode > 1) { | ||
| 249 | + unallocated_encoding(s); | ||
| 250 | + return; | ||
| 251 | + } | ||
| 252 | + switch (type) { | ||
| 253 | + case 0: /* float32 */ | ||
| 254 | + case 1: /* float64 */ | ||
| 255 | + break; | ||
| 256 | + case 3: /* float16 */ | ||
| 257 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 258 | + break; | ||
| 259 | + } | ||
| 260 | + /* fallthru */ | ||
| 261 | + default: | ||
| 262 | unallocated_encoding(s); | ||
| 263 | return; | ||
| 264 | } | ||
| 265 | -- | ||
| 266 | 2.17.0 | ||
| 267 | |||
| 268 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Cc: qemu-stable@nongnu.org | ||
| 4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Message-id: 20180512003217.9105-5-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/translate-a64.c | 17 +++++++++++++++-- | ||
| 11 | 1 file changed, 15 insertions(+), 2 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/translate-a64.c | ||
| 16 | +++ b/target/arm/translate-a64.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn) | ||
| 18 | bool sf = extract32(insn, 31, 1); | ||
| 19 | bool itof; | ||
| 20 | |||
| 21 | - if (sbit || (type > 1) | ||
| 22 | - || (!sf && scale < 32)) { | ||
| 23 | + if (sbit || (!sf && scale < 32)) { | ||
| 24 | + unallocated_encoding(s); | ||
| 25 | + return; | ||
| 26 | + } | ||
| 27 | + | ||
| 28 | + switch (type) { | ||
| 29 | + case 0: /* float32 */ | ||
| 30 | + case 1: /* float64 */ | ||
| 31 | + break; | ||
| 32 | + case 3: /* float16 */ | ||
| 33 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 34 | + break; | ||
| 35 | + } | ||
| 36 | + /* fallthru */ | ||
| 37 | + default: | ||
| 38 | unallocated_encoding(s); | ||
| 39 | return; | ||
| 40 | } | ||
| 41 | -- | ||
| 42 | 2.17.0 | ||
| 43 | |||
| 44 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | Cc: qemu-stable@nongnu.org | ||
| 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Message-id: 20180512003217.9105-6-richard.henderson@linaro.org | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | --- | ||
| 10 | target/arm/translate-a64.c | 30 ++++++++++++++---------------- | ||
| 11 | 1 file changed, 14 insertions(+), 16 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/translate-a64.c | ||
| 16 | +++ b/target/arm/translate-a64.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) | ||
| 18 | return v; | ||
| 19 | } | ||
| 20 | |||
| 21 | +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) | ||
| 22 | +{ | ||
| 23 | + TCGv_i32 v = tcg_temp_new_i32(); | ||
| 24 | + | ||
| 25 | + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); | ||
| 26 | + return v; | ||
| 27 | +} | ||
| 28 | + | ||
| 29 | /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64). | ||
| 30 | * If SVE is not enabled, then there are only 128 bits in the vector. | ||
| 31 | */ | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) | ||
| 33 | static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | ||
| 34 | { | ||
| 35 | TCGv_ptr fpst = NULL; | ||
| 36 | - TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
| 37 | + TCGv_i32 tcg_op = read_fp_hreg(s, rn); | ||
| 38 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
| 39 | |||
| 40 | - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); | ||
| 41 | - | ||
| 42 | switch (opcode) { | ||
| 43 | case 0x0: /* FMOV */ | ||
| 44 | tcg_gen_mov_i32(tcg_res, tcg_op); | ||
| 45 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn) | ||
| 46 | tcg_temp_free_i64(tcg_op2); | ||
| 47 | tcg_temp_free_i64(tcg_res); | ||
| 48 | } else { | ||
| 49 | - TCGv_i32 tcg_op1 = tcg_temp_new_i32(); | ||
| 50 | - TCGv_i32 tcg_op2 = tcg_temp_new_i32(); | ||
| 51 | + TCGv_i32 tcg_op1 = read_fp_hreg(s, rn); | ||
| 52 | + TCGv_i32 tcg_op2 = read_fp_hreg(s, rm); | ||
| 53 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | ||
| 54 | |||
| 55 | - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); | ||
| 56 | - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); | ||
| 57 | - | ||
| 58 | gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); | ||
| 59 | gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res); | ||
| 60 | |||
| 61 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, | ||
| 62 | |||
| 63 | fpst = get_fpstatus_ptr(true); | ||
| 64 | |||
| 65 | - tcg_op1 = tcg_temp_new_i32(); | ||
| 66 | - tcg_op2 = tcg_temp_new_i32(); | ||
| 67 | + tcg_op1 = read_fp_hreg(s, rn); | ||
| 68 | + tcg_op2 = read_fp_hreg(s, rm); | ||
| 69 | tcg_res = tcg_temp_new_i32(); | ||
| 70 | |||
| 71 | - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); | ||
| 72 | - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); | ||
| 73 | - | ||
| 74 | switch (fpopcode) { | ||
| 75 | case 0x03: /* FMULX */ | ||
| 76 | gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 77 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | ||
| 78 | } | ||
| 79 | |||
| 80 | if (is_scalar) { | ||
| 81 | - TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
| 82 | + TCGv_i32 tcg_op = read_fp_hreg(s, rn); | ||
| 83 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
| 84 | |||
| 85 | - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); | ||
| 86 | - | ||
| 87 | switch (fpop) { | ||
| 88 | case 0x1a: /* FCVTNS */ | ||
| 89 | case 0x1b: /* FCVTMS */ | ||
| 90 | -- | ||
| 91 | 2.17.0 | ||
| 92 | |||
| 93 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | We missed all of the scalar fp16 binary operations. | ||
| 4 | |||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 9 | Message-id: 20180512003217.9105-7-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++ | ||
| 13 | 1 file changed, 65 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/translate-a64.c | ||
| 18 | +++ b/target/arm/translate-a64.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode, | ||
| 20 | tcg_temp_free_i64(tcg_res); | ||
| 21 | } | ||
| 22 | |||
| 23 | +/* Floating-point data-processing (2 source) - half precision */ | ||
| 24 | +static void handle_fp_2src_half(DisasContext *s, int opcode, | ||
| 25 | + int rd, int rn, int rm) | ||
| 26 | +{ | ||
| 27 | + TCGv_i32 tcg_op1; | ||
| 28 | + TCGv_i32 tcg_op2; | ||
| 29 | + TCGv_i32 tcg_res; | ||
| 30 | + TCGv_ptr fpst; | ||
| 31 | + | ||
| 32 | + tcg_res = tcg_temp_new_i32(); | ||
| 33 | + fpst = get_fpstatus_ptr(true); | ||
| 34 | + tcg_op1 = read_fp_hreg(s, rn); | ||
| 35 | + tcg_op2 = read_fp_hreg(s, rm); | ||
| 36 | + | ||
| 37 | + switch (opcode) { | ||
| 38 | + case 0x0: /* FMUL */ | ||
| 39 | + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 40 | + break; | ||
| 41 | + case 0x1: /* FDIV */ | ||
| 42 | + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 43 | + break; | ||
| 44 | + case 0x2: /* FADD */ | ||
| 45 | + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 46 | + break; | ||
| 47 | + case 0x3: /* FSUB */ | ||
| 48 | + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 49 | + break; | ||
| 50 | + case 0x4: /* FMAX */ | ||
| 51 | + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 52 | + break; | ||
| 53 | + case 0x5: /* FMIN */ | ||
| 54 | + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 55 | + break; | ||
| 56 | + case 0x6: /* FMAXNM */ | ||
| 57 | + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 58 | + break; | ||
| 59 | + case 0x7: /* FMINNM */ | ||
| 60 | + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 61 | + break; | ||
| 62 | + case 0x8: /* FNMUL */ | ||
| 63 | + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 64 | + tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000); | ||
| 65 | + break; | ||
| 66 | + default: | ||
| 67 | + g_assert_not_reached(); | ||
| 68 | + } | ||
| 69 | + | ||
| 70 | + write_fp_sreg(s, rd, tcg_res); | ||
| 71 | + | ||
| 72 | + tcg_temp_free_ptr(fpst); | ||
| 73 | + tcg_temp_free_i32(tcg_op1); | ||
| 74 | + tcg_temp_free_i32(tcg_op2); | ||
| 75 | + tcg_temp_free_i32(tcg_res); | ||
| 76 | +} | ||
| 77 | + | ||
| 78 | /* Floating point data-processing (2 source) | ||
| 79 | * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 | ||
| 80 | * +---+---+---+-----------+------+---+------+--------+-----+------+------+ | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn) | ||
| 82 | } | ||
| 83 | handle_fp_2src_double(s, opcode, rd, rn, rm); | ||
| 84 | break; | ||
| 85 | + case 3: | ||
| 86 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 87 | + unallocated_encoding(s); | ||
| 88 | + return; | ||
| 89 | + } | ||
| 90 | + if (!fp_access_check(s)) { | ||
| 91 | + return; | ||
| 92 | + } | ||
| 93 | + handle_fp_2src_half(s, opcode, rd, rn, rm); | ||
| 94 | + break; | ||
| 95 | default: | ||
| 96 | unallocated_encoding(s); | ||
| 97 | } | ||
| 98 | -- | ||
| 99 | 2.17.0 | ||
| 100 | |||
| 101 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | We missed all of the scalar fp16 fma operations. | ||
| 4 | |||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 9 | Message-id: 20180512003217.9105-8-richard.henderson@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++ | ||
| 13 | 1 file changed, 48 insertions(+) | ||
| 14 | |||
| 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/translate-a64.c | ||
| 18 | +++ b/target/arm/translate-a64.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, | ||
| 20 | tcg_temp_free_i64(tcg_res); | ||
| 21 | } | ||
| 22 | |||
| 23 | +/* Floating-point data-processing (3 source) - half precision */ | ||
| 24 | +static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1, | ||
| 25 | + int rd, int rn, int rm, int ra) | ||
| 26 | +{ | ||
| 27 | + TCGv_i32 tcg_op1, tcg_op2, tcg_op3; | ||
| 28 | + TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
| 29 | + TCGv_ptr fpst = get_fpstatus_ptr(true); | ||
| 30 | + | ||
| 31 | + tcg_op1 = read_fp_hreg(s, rn); | ||
| 32 | + tcg_op2 = read_fp_hreg(s, rm); | ||
| 33 | + tcg_op3 = read_fp_hreg(s, ra); | ||
| 34 | + | ||
| 35 | + /* These are fused multiply-add, and must be done as one | ||
| 36 | + * floating point operation with no rounding between the | ||
| 37 | + * multiplication and addition steps. | ||
| 38 | + * NB that doing the negations here as separate steps is | ||
| 39 | + * correct : an input NaN should come out with its sign bit | ||
| 40 | + * flipped if it is a negated-input. | ||
| 41 | + */ | ||
| 42 | + if (o1 == true) { | ||
| 43 | + tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000); | ||
| 44 | + } | ||
| 45 | + | ||
| 46 | + if (o0 != o1) { | ||
| 47 | + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); | ||
| 48 | + } | ||
| 49 | + | ||
| 50 | + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst); | ||
| 51 | + | ||
| 52 | + write_fp_sreg(s, rd, tcg_res); | ||
| 53 | + | ||
| 54 | + tcg_temp_free_ptr(fpst); | ||
| 55 | + tcg_temp_free_i32(tcg_op1); | ||
| 56 | + tcg_temp_free_i32(tcg_op2); | ||
| 57 | + tcg_temp_free_i32(tcg_op3); | ||
| 58 | + tcg_temp_free_i32(tcg_res); | ||
| 59 | +} | ||
| 60 | + | ||
| 61 | /* Floating point data-processing (3 source) | ||
| 62 | * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0 | ||
| 63 | * +---+---+---+-----------+------+----+------+----+------+------+------+ | ||
| 64 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) | ||
| 65 | } | ||
| 66 | handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra); | ||
| 67 | break; | ||
| 68 | + case 3: | ||
| 69 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 70 | + unallocated_encoding(s); | ||
| 71 | + return; | ||
| 72 | + } | ||
| 73 | + if (!fp_access_check(s)) { | ||
| 74 | + return; | ||
| 75 | + } | ||
| 76 | + handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra); | ||
| 77 | + break; | ||
| 78 | default: | ||
| 79 | unallocated_encoding(s); | ||
| 80 | } | ||
| 81 | -- | ||
| 82 | 2.17.0 | ||
| 83 | |||
| 84 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
| 2 | 1 | ||
| 3 | These where missed out from the rest of the half-precision work. | ||
| 4 | |||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 8 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20180512003217.9105-9-richard.henderson@linaro.org | ||
| 11 | [rth: Diagnose lack of FP16 before fp_access_check] | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | target/arm/helper-a64.h | 2 + | ||
| 16 | target/arm/helper-a64.c | 10 +++++ | ||
| 17 | target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++-------- | ||
| 18 | 3 files changed, 83 insertions(+), 17 deletions(-) | ||
| 19 | |||
| 20 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
| 21 | index XXXXXXX..XXXXXXX 100644 | ||
| 22 | --- a/target/arm/helper-a64.h | ||
| 23 | +++ b/target/arm/helper-a64.h | ||
| 24 | @@ -XXX,XX +XXX,XX @@ | ||
| 25 | DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) | ||
| 26 | DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) | ||
| 27 | DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) | ||
| 28 | +DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) | ||
| 29 | +DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) | ||
| 30 | DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) | ||
| 31 | DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr) | ||
| 32 | DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr) | ||
| 33 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/target/arm/helper-a64.c | ||
| 36 | +++ b/target/arm/helper-a64.c | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res) | ||
| 38 | return flags; | ||
| 39 | } | ||
| 40 | |||
| 41 | +uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status) | ||
| 42 | +{ | ||
| 43 | + return float_rel_to_flags(float16_compare_quiet(x, y, fp_status)); | ||
| 44 | +} | ||
| 45 | + | ||
| 46 | +uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status) | ||
| 47 | +{ | ||
| 48 | + return float_rel_to_flags(float16_compare(x, y, fp_status)); | ||
| 49 | +} | ||
| 50 | + | ||
| 51 | uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status) | ||
| 52 | { | ||
| 53 | return float_rel_to_flags(float32_compare_quiet(x, y, fp_status)); | ||
| 54 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 55 | index XXXXXXX..XXXXXXX 100644 | ||
| 56 | --- a/target/arm/translate-a64.c | ||
| 57 | +++ b/target/arm/translate-a64.c | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | ||
| 59 | } | ||
| 60 | } | ||
| 61 | |||
| 62 | -static void handle_fp_compare(DisasContext *s, bool is_double, | ||
| 63 | +static void handle_fp_compare(DisasContext *s, int size, | ||
| 64 | unsigned int rn, unsigned int rm, | ||
| 65 | bool cmp_with_zero, bool signal_all_nans) | ||
| 66 | { | ||
| 67 | TCGv_i64 tcg_flags = tcg_temp_new_i64(); | ||
| 68 | - TCGv_ptr fpst = get_fpstatus_ptr(false); | ||
| 69 | + TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); | ||
| 70 | |||
| 71 | - if (is_double) { | ||
| 72 | + if (size == MO_64) { | ||
| 73 | TCGv_i64 tcg_vn, tcg_vm; | ||
| 74 | |||
| 75 | tcg_vn = read_fp_dreg(s, rn); | ||
| 76 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double, | ||
| 77 | tcg_temp_free_i64(tcg_vn); | ||
| 78 | tcg_temp_free_i64(tcg_vm); | ||
| 79 | } else { | ||
| 80 | - TCGv_i32 tcg_vn, tcg_vm; | ||
| 81 | + TCGv_i32 tcg_vn = tcg_temp_new_i32(); | ||
| 82 | + TCGv_i32 tcg_vm = tcg_temp_new_i32(); | ||
| 83 | |||
| 84 | - tcg_vn = read_fp_sreg(s, rn); | ||
| 85 | + read_vec_element_i32(s, tcg_vn, rn, 0, size); | ||
| 86 | if (cmp_with_zero) { | ||
| 87 | - tcg_vm = tcg_const_i32(0); | ||
| 88 | + tcg_gen_movi_i32(tcg_vm, 0); | ||
| 89 | } else { | ||
| 90 | - tcg_vm = read_fp_sreg(s, rm); | ||
| 91 | + read_vec_element_i32(s, tcg_vm, rm, 0, size); | ||
| 92 | } | ||
| 93 | - if (signal_all_nans) { | ||
| 94 | - gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | ||
| 95 | - } else { | ||
| 96 | - gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | ||
| 97 | + | ||
| 98 | + switch (size) { | ||
| 99 | + case MO_32: | ||
| 100 | + if (signal_all_nans) { | ||
| 101 | + gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | ||
| 102 | + } else { | ||
| 103 | + gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | ||
| 104 | + } | ||
| 105 | + break; | ||
| 106 | + case MO_16: | ||
| 107 | + if (signal_all_nans) { | ||
| 108 | + gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | ||
| 109 | + } else { | ||
| 110 | + gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst); | ||
| 111 | + } | ||
| 112 | + break; | ||
| 113 | + default: | ||
| 114 | + g_assert_not_reached(); | ||
| 115 | } | ||
| 116 | + | ||
| 117 | tcg_temp_free_i32(tcg_vn); | ||
| 118 | tcg_temp_free_i32(tcg_vm); | ||
| 119 | } | ||
| 120 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double, | ||
| 121 | static void disas_fp_compare(DisasContext *s, uint32_t insn) | ||
| 122 | { | ||
| 123 | unsigned int mos, type, rm, op, rn, opc, op2r; | ||
| 124 | + int size; | ||
| 125 | |||
| 126 | mos = extract32(insn, 29, 3); | ||
| 127 | - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | ||
| 128 | + type = extract32(insn, 22, 2); | ||
| 129 | rm = extract32(insn, 16, 5); | ||
| 130 | op = extract32(insn, 14, 2); | ||
| 131 | rn = extract32(insn, 5, 5); | ||
| 132 | opc = extract32(insn, 3, 2); | ||
| 133 | op2r = extract32(insn, 0, 3); | ||
| 134 | |||
| 135 | - if (mos || op || op2r || type > 1) { | ||
| 136 | + if (mos || op || op2r) { | ||
| 137 | + unallocated_encoding(s); | ||
| 138 | + return; | ||
| 139 | + } | ||
| 140 | + | ||
| 141 | + switch (type) { | ||
| 142 | + case 0: | ||
| 143 | + size = MO_32; | ||
| 144 | + break; | ||
| 145 | + case 1: | ||
| 146 | + size = MO_64; | ||
| 147 | + break; | ||
| 148 | + case 3: | ||
| 149 | + size = MO_16; | ||
| 150 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 151 | + break; | ||
| 152 | + } | ||
| 153 | + /* fallthru */ | ||
| 154 | + default: | ||
| 155 | unallocated_encoding(s); | ||
| 156 | return; | ||
| 157 | } | ||
| 158 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn) | ||
| 159 | return; | ||
| 160 | } | ||
| 161 | |||
| 162 | - handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2); | ||
| 163 | + handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2); | ||
| 164 | } | ||
| 165 | |||
| 166 | /* Floating point conditional compare | ||
| 167 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | ||
| 168 | unsigned int mos, type, rm, cond, rn, op, nzcv; | ||
| 169 | TCGv_i64 tcg_flags; | ||
| 170 | TCGLabel *label_continue = NULL; | ||
| 171 | + int size; | ||
| 172 | |||
| 173 | mos = extract32(insn, 29, 3); | ||
| 174 | - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | ||
| 175 | + type = extract32(insn, 22, 2); | ||
| 176 | rm = extract32(insn, 16, 5); | ||
| 177 | cond = extract32(insn, 12, 4); | ||
| 178 | rn = extract32(insn, 5, 5); | ||
| 179 | op = extract32(insn, 4, 1); | ||
| 180 | nzcv = extract32(insn, 0, 4); | ||
| 181 | |||
| 182 | - if (mos || type > 1) { | ||
| 183 | + if (mos) { | ||
| 184 | + unallocated_encoding(s); | ||
| 185 | + return; | ||
| 186 | + } | ||
| 187 | + | ||
| 188 | + switch (type) { | ||
| 189 | + case 0: | ||
| 190 | + size = MO_32; | ||
| 191 | + break; | ||
| 192 | + case 1: | ||
| 193 | + size = MO_64; | ||
| 194 | + break; | ||
| 195 | + case 3: | ||
| 196 | + size = MO_16; | ||
| 197 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 198 | + break; | ||
| 199 | + } | ||
| 200 | + /* fallthru */ | ||
| 201 | + default: | ||
| 202 | unallocated_encoding(s); | ||
| 203 | return; | ||
| 204 | } | ||
| 205 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn) | ||
| 206 | gen_set_label(label_match); | ||
| 207 | } | ||
| 208 | |||
| 209 | - handle_fp_compare(s, type, rn, rm, false, op); | ||
| 210 | + handle_fp_compare(s, size, rn, rm, false, op); | ||
| 211 | |||
| 212 | if (cond < 0x0e) { | ||
| 213 | gen_set_label(label_continue); | ||
| 214 | -- | ||
| 215 | 2.17.0 | ||
| 216 | |||
| 217 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
| 2 | 1 | ||
| 3 | These were missed out from the rest of the half-precision work. | ||
| 4 | |||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 7 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 8 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20180512003217.9105-10-richard.henderson@linaro.org | ||
| 11 | [rth: Fix erroneous check vs type] | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | --- | ||
| 15 | target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ | ||
| 16 | 1 file changed, 25 insertions(+), 6 deletions(-) | ||
| 17 | |||
| 18 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 19 | index XXXXXXX..XXXXXXX 100644 | ||
| 20 | --- a/target/arm/translate-a64.c | ||
| 21 | +++ b/target/arm/translate-a64.c | ||
| 22 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) | ||
| 23 | unsigned int mos, type, rm, cond, rn, rd; | ||
| 24 | TCGv_i64 t_true, t_false, t_zero; | ||
| 25 | DisasCompare64 c; | ||
| 26 | + TCGMemOp sz; | ||
| 27 | |||
| 28 | mos = extract32(insn, 29, 3); | ||
| 29 | - type = extract32(insn, 22, 2); /* 0 = single, 1 = double */ | ||
| 30 | + type = extract32(insn, 22, 2); | ||
| 31 | rm = extract32(insn, 16, 5); | ||
| 32 | cond = extract32(insn, 12, 4); | ||
| 33 | rn = extract32(insn, 5, 5); | ||
| 34 | rd = extract32(insn, 0, 5); | ||
| 35 | |||
| 36 | - if (mos || type > 1) { | ||
| 37 | + if (mos) { | ||
| 38 | + unallocated_encoding(s); | ||
| 39 | + return; | ||
| 40 | + } | ||
| 41 | + | ||
| 42 | + switch (type) { | ||
| 43 | + case 0: | ||
| 44 | + sz = MO_32; | ||
| 45 | + break; | ||
| 46 | + case 1: | ||
| 47 | + sz = MO_64; | ||
| 48 | + break; | ||
| 49 | + case 3: | ||
| 50 | + sz = MO_16; | ||
| 51 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 52 | + break; | ||
| 53 | + } | ||
| 54 | + /* fallthru */ | ||
| 55 | + default: | ||
| 56 | unallocated_encoding(s); | ||
| 57 | return; | ||
| 58 | } | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) | ||
| 60 | return; | ||
| 61 | } | ||
| 62 | |||
| 63 | - /* Zero extend sreg inputs to 64 bits now. */ | ||
| 64 | + /* Zero extend sreg & hreg inputs to 64 bits now. */ | ||
| 65 | t_true = tcg_temp_new_i64(); | ||
| 66 | t_false = tcg_temp_new_i64(); | ||
| 67 | - read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32); | ||
| 68 | - read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32); | ||
| 69 | + read_vec_element(s, t_true, rn, 0, sz); | ||
| 70 | + read_vec_element(s, t_false, rm, 0, sz); | ||
| 71 | |||
| 72 | a64_test_cc(&c, cond); | ||
| 73 | t_zero = tcg_const_i64(0); | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) | ||
| 75 | tcg_temp_free_i64(t_false); | ||
| 76 | a64_free_cc(&c); | ||
| 77 | |||
| 78 | - /* Note that sregs write back zeros to the high bits, | ||
| 79 | + /* Note that sregs & hregs write back zeros to the high bits, | ||
| 80 | and we've already done the zero-extension. */ | ||
| 81 | write_fp_dreg(s, rd, t_true); | ||
| 82 | tcg_temp_free_i64(t_true); | ||
| 83 | -- | ||
| 84 | 2.17.0 | ||
| 85 | |||
| 86 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
| 2 | 1 | ||
| 3 | All the hard work is already done by vfp_expand_imm, we just need to | ||
| 4 | make sure we pick up the correct size. | ||
| 5 | |||
| 6 | Cc: qemu-stable@nongnu.org | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 9 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 11 | Message-id: 20180512003217.9105-11-richard.henderson@linaro.org | ||
| 12 | [rth: Merge unallocated_encoding check with TCGMemOp conversion.] | ||
| 13 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 15 | --- | ||
| 16 | target/arm/translate-a64.c | 20 +++++++++++++++++--- | ||
| 17 | 1 file changed, 17 insertions(+), 3 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/target/arm/translate-a64.c | ||
| 22 | +++ b/target/arm/translate-a64.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) | ||
| 24 | { | ||
| 25 | int rd = extract32(insn, 0, 5); | ||
| 26 | int imm8 = extract32(insn, 13, 8); | ||
| 27 | - int is_double = extract32(insn, 22, 2); | ||
| 28 | + int type = extract32(insn, 22, 2); | ||
| 29 | uint64_t imm; | ||
| 30 | TCGv_i64 tcg_res; | ||
| 31 | + TCGMemOp sz; | ||
| 32 | |||
| 33 | - if (is_double > 1) { | ||
| 34 | + switch (type) { | ||
| 35 | + case 0: | ||
| 36 | + sz = MO_32; | ||
| 37 | + break; | ||
| 38 | + case 1: | ||
| 39 | + sz = MO_64; | ||
| 40 | + break; | ||
| 41 | + case 3: | ||
| 42 | + sz = MO_16; | ||
| 43 | + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { | ||
| 44 | + break; | ||
| 45 | + } | ||
| 46 | + /* fallthru */ | ||
| 47 | + default: | ||
| 48 | unallocated_encoding(s); | ||
| 49 | return; | ||
| 50 | } | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) | ||
| 52 | return; | ||
| 53 | } | ||
| 54 | |||
| 55 | - imm = vfp_expand_imm(MO_32 + is_double, imm8); | ||
| 56 | + imm = vfp_expand_imm(sz, imm8); | ||
| 57 | |||
| 58 | tcg_res = tcg_const_i64(imm); | ||
| 59 | write_fp_dreg(s, rd, tcg_res); | ||
| 60 | -- | ||
| 61 | 2.17.0 | ||
| 62 | |||
| 63 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Alex Bennée <alex.bennee@linaro.org> | ||
| 2 | 1 | ||
| 3 | We are meant to explicitly pass fpst, not cpu_env. | ||
| 4 | |||
| 5 | Cc: qemu-stable@nongnu.org | ||
| 6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 10 | Message-id: 20180512003217.9105-12-richard.henderson@linaro.org | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | target/arm/translate-a64.c | 3 ++- | ||
| 14 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/translate-a64.c | ||
| 19 | +++ b/target/arm/translate-a64.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | ||
| 21 | tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); | ||
| 22 | break; | ||
| 23 | case 0x3: /* FSQRT */ | ||
| 24 | - gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env); | ||
| 25 | + fpst = get_fpstatus_ptr(true); | ||
| 26 | + gen_helper_sqrt_f16(tcg_res, tcg_op, fpst); | ||
| 27 | break; | ||
| 28 | case 0x8: /* FRINTN */ | ||
| 29 | case 0x9: /* FRINTP */ | ||
| 30 | -- | ||
| 31 | 2.17.0 | ||
| 32 | |||
| 33 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 2 | 1 | ||
| 3 | Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status": | ||
| 4 | |||
| 5 | The block length is predefined to 512 bits | ||
| 6 | |||
| 7 | and "4.10.2 SD Status": | ||
| 8 | |||
| 9 | The SD Status contains status bits that are related to the SD Memory Card | ||
| 10 | proprietary features and may be used for future application-specific usage. | ||
| 11 | The size of the SD Status is one data block of 512 bit. The content of this | ||
| 12 | register is transmitted to the Host over the DAT bus along with a 16-bit CRC. | ||
| 13 | |||
| 14 | Thus the 16-bit CRC goes at offset 64. | ||
| 15 | |||
| 16 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 17 | Message-id: 20180509060104.4458-3-f4bug@amsat.org | ||
| 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 20 | --- | ||
| 21 | hw/sd/sd.c | 2 +- | ||
| 22 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 23 | |||
| 24 | diff --git a/hw/sd/sd.c b/hw/sd/sd.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/hw/sd/sd.c | ||
| 27 | +++ b/hw/sd/sd.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg) | ||
| 29 | sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4); | ||
| 30 | } | ||
| 31 | memset(&sd->data[17], 0, 47); | ||
| 32 | - stw_be_p(sd->data + 65, sd_crc16(sd->data, 64)); | ||
| 33 | + stw_be_p(sd->data + 64, sd_crc16(sd->data, 64)); | ||
| 34 | } | ||
| 35 | |||
| 36 | static inline bool sd_wp_addr(SDState *sd, uint64_t addr) | ||
| 37 | -- | ||
| 38 | 2.17.0 | ||
| 39 | |||
| 40 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Usually the logging of the CPU state produced by -d cpu is sufficient | ||
| 2 | to diagnose problems, but sometimes you want to see the state of | ||
| 3 | the floating point registers as well. We don't want to enable that | ||
| 4 | by default as it adds a lot of extra data to the log; instead, | ||
| 5 | allow it to be optionally enabled via -d fpu. | ||
| 6 | 1 | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20180510130024.31678-1-peter.maydell@linaro.org | ||
| 10 | --- | ||
| 11 | include/qemu/log.h | 1 + | ||
| 12 | accel/tcg/cpu-exec.c | 9 ++++++--- | ||
| 13 | util/log.c | 2 ++ | ||
| 14 | 3 files changed, 9 insertions(+), 3 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/include/qemu/log.h b/include/qemu/log.h | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/include/qemu/log.h | ||
| 19 | +++ b/include/qemu/log.h | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void) | ||
| 21 | #define CPU_LOG_PAGE (1 << 14) | ||
| 22 | /* LOG_TRACE (1 << 15) is defined in log-for-trace.h */ | ||
| 23 | #define CPU_LOG_TB_OP_IND (1 << 16) | ||
| 24 | +#define CPU_LOG_TB_FPU (1 << 17) | ||
| 25 | |||
| 26 | /* Lock output for a series of related logs. Since this is not needed | ||
| 27 | * for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we | ||
| 28 | diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c | ||
| 29 | index XXXXXXX..XXXXXXX 100644 | ||
| 30 | --- a/accel/tcg/cpu-exec.c | ||
| 31 | +++ b/accel/tcg/cpu-exec.c | ||
| 32 | @@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb) | ||
| 33 | if (qemu_loglevel_mask(CPU_LOG_TB_CPU) | ||
| 34 | && qemu_log_in_addr_range(itb->pc)) { | ||
| 35 | qemu_log_lock(); | ||
| 36 | + int flags = 0; | ||
| 37 | + if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) { | ||
| 38 | + flags |= CPU_DUMP_FPU; | ||
| 39 | + } | ||
| 40 | #if defined(TARGET_I386) | ||
| 41 | - log_cpu_state(cpu, CPU_DUMP_CCOP); | ||
| 42 | -#else | ||
| 43 | - log_cpu_state(cpu, 0); | ||
| 44 | + flags |= CPU_DUMP_CCOP; | ||
| 45 | #endif | ||
| 46 | + log_cpu_state(cpu, flags); | ||
| 47 | qemu_log_unlock(); | ||
| 48 | } | ||
| 49 | #endif /* DEBUG_DISAS */ | ||
| 50 | diff --git a/util/log.c b/util/log.c | ||
| 51 | index XXXXXXX..XXXXXXX 100644 | ||
| 52 | --- a/util/log.c | ||
| 53 | +++ b/util/log.c | ||
| 54 | @@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = { | ||
| 55 | "show trace before each executed TB (lots of logs)" }, | ||
| 56 | { CPU_LOG_TB_CPU, "cpu", | ||
| 57 | "show CPU registers before entering a TB (lots of logs)" }, | ||
| 58 | + { CPU_LOG_TB_FPU, "fpu", | ||
| 59 | + "include FPU registers in the 'cpu' logging" }, | ||
| 60 | { CPU_LOG_MMU, "mmu", | ||
| 61 | "log MMU-related activities" }, | ||
| 62 | { CPU_LOG_PCALL, "pcall", | ||
| 63 | -- | ||
| 64 | 2.17.0 | ||
| 65 | |||
| 66 | diff view generated by jsdifflib |