[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/26] target-arm queue
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The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
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The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
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Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
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Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302
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9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
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for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2:
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11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
11
ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000)
12
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13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
target-arm queue:
14
target-arm queue:
15
* Fix coverity nit in int_to_float code
15
* mps3-an547: Add missing user ahb interfaces
16
* Don't set Invalid for float-to-int(MAXINT)
16
* hw/arm/mps2-tz.c: Update AN547 documentation URL
17
* Fix fp_status_f16 tininess before rounding
17
* hw/input/tsc210x: Don't abort on bad SPI word widths
18
* Add various missing insns from the v8.2-FP16 extension
18
* hw/i2c: flatten pca954x mux device
19
* Fix sqrt_f16 exception raising
19
* target/arm: Support PSCI 1.1 and SMCCC 1.0
20
* sdcard: Correct CRC16 offset in sd_function_switch()
20
* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
21
* tcg: Optionally log FPU state in TCG -d cpu logging
21
* tests/qtest: add qtests for npcm7xx sdhci
22
* Implement FEAT_LVA
23
* Implement FEAT_LPA
24
* Implement FEAT_LPA2 (but do not enable it yet)
25
* Report KVM's actual PSCI version to guest in dtb
26
* ui/cocoa.m: Fix updateUIInfo threading issues
27
* ui/cocoa.m: Remove unnecessary NSAutoreleasePools
22
28
23
----------------------------------------------------------------
29
----------------------------------------------------------------
24
Alex Bennée (5):
30
Akihiko Odaki (1):
25
fpu/softfloat: int_to_float ensure r fully initialised
31
target/arm: Support PSCI 1.1 and SMCCC 1.0
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
30
32
31
Peter Maydell (3):
33
Jimmy Brisson (1):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
34
mps3-an547: Add missing user ahb interfaces
33
target/arm: Fix fp_status_f16 tininess before rounding
34
tcg: Optionally log FPU state in TCG -d cpu logging
35
35
36
Philippe Mathieu-Daudé (1):
36
Patrick Venture (1):
37
sdcard: Correct CRC16 offset in sd_function_switch()
37
hw/i2c: flatten pca954x mux device
38
38
39
Richard Henderson (7):
39
Peter Maydell (5):
40
target/arm: Implement FMOV (general) for fp16
40
hw/arm/mps2-tz.c: Update AN547 documentation URL
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
41
hw/input/tsc210x: Don't abort on bad SPI word widths
42
target/arm: Implement FCVT (scalar, integer) for fp16
42
target/arm: Report KVM's actual PSCI version to guest in dtb
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
43
ui/cocoa.m: Fix updateUIInfo threading issues
44
target/arm: Introduce and use read_fp_hreg
44
ui/cocoa.m: Remove unnecessary NSAutoreleasePools
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
47
45
48
include/qemu/log.h | 1 +
46
Richard Henderson (16):
49
target/arm/helper-a64.h | 2 +
47
hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
50
target/arm/helper.h | 6 +
48
target/arm: Set TCR_EL1.TSZ for user-only
51
accel/tcg/cpu-exec.c | 9 +-
49
target/arm: Fault on invalid TCR_ELx.TxSZ
52
fpu/softfloat.c | 6 +-
50
target/arm: Move arm_pamax out of line
53
hw/sd/sd.c | 2 +-
51
target/arm: Pass outputsize down to check_s2_mmu_setup
54
target/arm/cpu.c | 2 +
52
target/arm: Use MAKE_64BIT_MASK to compute indexmask
55
target/arm/helper-a64.c | 10 ++
53
target/arm: Honor TCR_ELx.{I}PS
56
target/arm/helper.c | 38 +++-
54
target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
55
target/arm: Implement FEAT_LVA
58
util/log.c | 2 +
56
target/arm: Implement FEAT_LPA
59
11 files changed, 428 insertions(+), 71 deletions(-)
57
target/arm: Extend arm_fi_to_lfsc to level -1
58
target/arm: Introduce tlbi_aa64_get_range
59
target/arm: Fix TLBIRange.base for 16k and 64k pages
60
target/arm: Validate tlbi TG matches translation granule in use
61
target/arm: Advertise all page sizes for -cpu max
62
target/arm: Implement FEAT_LPA2
60
63
64
Shengtan Mao (1):
65
tests/qtest: add qtests for npcm7xx sdhci
66
67
Wentao_Liang (1):
68
target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
69
70
docs/system/arm/emulation.rst | 3 +
71
include/hw/registerfields.h | 48 +++++-
72
target/arm/cpu-param.h | 4 +-
73
target/arm/cpu.h | 27 ++++
74
target/arm/internals.h | 58 ++++---
75
target/arm/kvm-consts.h | 14 +-
76
hw/arm/boot.c | 11 +-
77
hw/arm/mps2-tz.c | 6 +-
78
hw/i2c/i2c_mux_pca954x.c | 77 ++-------
79
hw/input/tsc210x.c | 8 +-
80
target/arm/cpu.c | 8 +-
81
target/arm/cpu64.c | 7 +-
82
target/arm/helper.c | 332 ++++++++++++++++++++++++++++++---------
83
target/arm/hvf/hvf.c | 27 +++-
84
target/arm/kvm64.c | 14 +-
85
target/arm/psci.c | 35 ++++-
86
target/arm/translate-a64.c | 2 +-
87
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++
88
tests/qtest/meson.build | 1 +
89
ui/cocoa.m | 31 ++--
90
20 files changed, 736 insertions(+), 192 deletions(-)
91
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
diff view generated by jsdifflib
New patch
[PULL 01/26] mps3-an547: Add missing user ahb interfaces
1
From: Jimmy Brisson <jimmy.brisson@linaro.org>
1
2
3
With these interfaces missing, TFM would delegate peripherals 0, 1,
4
2, 3 and 8, and qemu would ignore the delegation of interface 8, as
5
it thought interface 4 was eth & USB.
6
7
This patch corrects this behavior and allows TFM to delegate the
8
eth & USB peripheral to NS mode.
9
10
(The old QEMU behaviour was based on revision B of the AN547
11
appnote; revision C corrects this error in the documentation,
12
and this commit brings QEMU in to line with how the FPGA
13
image really behaves.)
14
15
Signed-off-by: Jimmy Brisson <jimmy.brisson@linaro.org>
16
Message-id: 20220210210227.3203883-1-jimmy.brisson@linaro.org
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
[PMM: added commit message note clarifying that the old behaviour
19
was a docs issue, not because there were two different versions
20
of the FPGA image]
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
23
hw/arm/mps2-tz.c | 4 ++++
24
1 file changed, 4 insertions(+)
25
26
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/arm/mps2-tz.c
29
+++ b/hw/arm/mps2-tz.c
30
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
31
{ "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 },
32
{ "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 },
33
{ "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 },
34
+ { /* port 4 USER AHB interface 0 */ },
35
+ { /* port 5 USER AHB interface 1 */ },
36
+ { /* port 6 USER AHB interface 2 */ },
37
+ { /* port 7 USER AHB interface 3 */ },
38
{ "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 49 } },
39
},
40
},
41
--
42
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
[PULL 02/26] hw/arm/mps2-tz.c: Update AN547 documentation URL
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
The AN547 application note URL has changed: update our comment
2
to diagnose problems, but sometimes you want to see the state of
2
accordingly. (Rev B is still downloadable from the old URL,
3
the floating point registers as well. We don't want to enable that
3
but there is a new Rev C of the document now.)
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
6
4
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
7
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20220221094144.426191-1-peter.maydell@linaro.org
10
---
9
---
11
include/qemu/log.h | 1 +
10
hw/arm/mps2-tz.c | 2 +-
12
accel/tcg/cpu-exec.c | 9 ++++++---
11
1 file changed, 1 insertion(+), 1 deletion(-)
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
12
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
13
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
15
--- a/hw/arm/mps2-tz.c
19
+++ b/include/qemu/log.h
16
+++ b/hw/arm/mps2-tz.c
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
17
@@ -XXX,XX +XXX,XX @@
21
#define CPU_LOG_PAGE (1 << 14)
18
* Application Note AN524:
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
19
* https://developer.arm.com/documentation/dai0524/latest/
23
#define CPU_LOG_TB_OP_IND (1 << 16)
20
* Application Note AN547:
24
+#define CPU_LOG_TB_FPU (1 << 17)
21
- * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf
25
22
+ * https://developer.arm.com/documentation/dai0547/latest/
26
/* Lock output for a series of related logs. Since this is not needed
23
*
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
24
* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
25
* (ARM ECM0601256) for the details of some of the device layout:
29
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/cpu-exec.c
31
+++ b/accel/tcg/cpu-exec.c
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
34
&& qemu_log_in_addr_range(itb->pc)) {
35
qemu_log_lock();
36
+ int flags = 0;
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
38
+ flags |= CPU_DUMP_FPU;
39
+ }
40
#if defined(TARGET_I386)
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
42
-#else
43
- log_cpu_state(cpu, 0);
44
+ flags |= CPU_DUMP_CCOP;
45
#endif
46
+ log_cpu_state(cpu, flags);
47
qemu_log_unlock();
48
}
49
#endif /* DEBUG_DISAS */
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
63
--
26
--
64
2.17.0
27
2.25.1
65
28
66
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
[PULL 03/26] hw/input/tsc210x: Don't abort on bad SPI word widths
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The tsc210x doesn't support anything other than 16-bit reads on the
2
SPI bus, but the guest can program the SPI controller to attempt
3
them anyway. If this happens, don't abort QEMU, just log this as
4
a guest error.
2
5
3
We are meant to explicitly pass fpst, not cpu_env.
6
This fixes our machine_arm_n8x0.py:N8x0Machine.test_n800
7
acceptance test, which hits this assertion.
4
8
5
Cc: qemu-stable@nongnu.org
9
The reason we hit the assertion is because the guest kernel thinks
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
there is a TSC2005 on this SPI bus address, not a TSC210x. (The n810
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
*does* have a TSC2005 at this address.) The TSC2005 supports the
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
24-bit accesses which the guest driver makes, and the TSC210x does
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
not (that is, our TSC210x emulation is not missing support for a word
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
14
width the hardware can handle). It's not clear whether the problem
15
here is that the guest kernel incorrectly thinks the n800 has the
16
same device at this SPI bus address as the n810, or that QEMU's n810
17
board model doesn't get the SPI devices right. At this late date
18
there no longer appears to be any reliable information on the web
19
about the hardware behaviour, but I am inclined to think this is a
20
guest kernel bug. In any case, we prefer not to abort QEMU for
21
guest-triggerable conditions, so logging the error is the right thing
22
to do.
23
24
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/736
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
27
Message-id: 20220221140750.514557-1-peter.maydell@linaro.org
12
---
28
---
13
target/arm/translate-a64.c | 3 ++-
29
hw/input/tsc210x.c | 8 ++++++--
14
1 file changed, 2 insertions(+), 1 deletion(-)
30
1 file changed, 6 insertions(+), 2 deletions(-)
15
31
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c
17
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
34
--- a/hw/input/tsc210x.c
19
+++ b/target/arm/translate-a64.c
35
+++ b/hw/input/tsc210x.c
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
36
@@ -XXX,XX +XXX,XX @@
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
37
#include "hw/hw.h"
22
break;
38
#include "audio/audio.h"
23
case 0x3: /* FSQRT */
39
#include "qemu/timer.h"
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
40
+#include "qemu/log.h"
25
+ fpst = get_fpstatus_ptr(true);
41
#include "sysemu/reset.h"
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
42
#include "ui/console.h"
27
break;
43
#include "hw/arm/omap.h" /* For I2SCodec */
28
case 0x8: /* FRINTN */
44
@@ -XXX,XX +XXX,XX @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)
29
case 0x9: /* FRINTP */
45
TSC210xState *s = opaque;
46
uint32_t ret = 0;
47
48
- if (len != 16)
49
- hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);
50
+ if (len != 16) {
51
+ qemu_log_mask(LOG_GUEST_ERROR,
52
+ "%s: bad SPI word width %i\n", __func__, len);
53
+ return 0;
54
+ }
55
56
/* TODO: sequential reads etc - how do we make sure the host doesn't
57
* unintentionally read out a conversion result from a register while
30
--
58
--
31
2.17.0
59
2.25.1
32
60
33
61
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
[PULL 04/26] hw/i2c: flatten pca954x mux device
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Patrick Venture <venture@google.com>
2
2
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
3
Previously this device created N subdevices which each owned an i2c bus.
4
later on so we might as well mirror that.
4
Now this device simply owns the N i2c busses directly.
5
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Tested: Verified devices behind mux are still accessible via qmp and i2c
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
from within an arm32 SoC.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
9
Reviewed-by: Hao Wu <wuhaotsh@google.com>
10
Signed-off-by: Patrick Venture <venture@google.com>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20220202164533.1283668-1-venture@google.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
15
---
11
fpu/softfloat.c | 2 +-
16
hw/i2c/i2c_mux_pca954x.c | 77 +++++++---------------------------------
12
1 file changed, 1 insertion(+), 1 deletion(-)
17
1 file changed, 13 insertions(+), 64 deletions(-)
13
18
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
19
diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
21
--- a/hw/i2c/i2c_mux_pca954x.c
17
+++ b/fpu/softfloat.c
22
+++ b/hw/i2c/i2c_mux_pca954x.c
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
23
@@ -XXX,XX +XXX,XX @@
19
24
#define PCA9548_CHANNEL_COUNT 8
20
static FloatParts int_to_float(int64_t a, float_status *status)
25
#define PCA9546_CHANNEL_COUNT 4
26
27
-/*
28
- * struct Pca954xChannel - The i2c mux device will have N of these states
29
- * that own the i2c channel bus.
30
- * @bus: The owned channel bus.
31
- * @enabled: Is this channel active?
32
- */
33
-typedef struct Pca954xChannel {
34
- SysBusDevice parent;
35
-
36
- I2CBus *bus;
37
-
38
- bool enabled;
39
-} Pca954xChannel;
40
-
41
-#define TYPE_PCA954X_CHANNEL "pca954x-channel"
42
-#define PCA954X_CHANNEL(obj) \
43
- OBJECT_CHECK(Pca954xChannel, (obj), TYPE_PCA954X_CHANNEL)
44
-
45
/*
46
* struct Pca954xState - The pca954x state object.
47
* @control: The value written to the mux control.
48
@@ -XXX,XX +XXX,XX @@ typedef struct Pca954xState {
49
50
uint8_t control;
51
52
- /* The channel i2c buses. */
53
- Pca954xChannel channel[PCA9548_CHANNEL_COUNT];
54
+ bool enabled[PCA9548_CHANNEL_COUNT];
55
+ I2CBus *bus[PCA9548_CHANNEL_COUNT];
56
} Pca954xState;
57
58
/*
59
@@ -XXX,XX +XXX,XX @@ static bool pca954x_match(I2CSlave *candidate, uint8_t address,
60
}
61
62
for (i = 0; i < mc->nchans; i++) {
63
- if (!mux->channel[i].enabled) {
64
+ if (!mux->enabled[i]) {
65
continue;
66
}
67
68
- if (i2c_scan_bus(mux->channel[i].bus, address, broadcast,
69
+ if (i2c_scan_bus(mux->bus[i], address, broadcast,
70
current_devs)) {
71
if (!broadcast) {
72
return true;
73
@@ -XXX,XX +XXX,XX @@ static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask)
74
*/
75
for (i = 0; i < mc->nchans; i++) {
76
if (enable_mask & (1 << i)) {
77
- s->channel[i].enabled = true;
78
+ s->enabled[i] = true;
79
} else {
80
- s->channel[i].enabled = false;
81
+ s->enabled[i] = false;
82
}
83
}
84
}
85
@@ -XXX,XX +XXX,XX @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel)
86
Pca954xState *pca954x = PCA954X(mux);
87
88
g_assert(channel < pc->nchans);
89
- return I2C_BUS(qdev_get_child_bus(DEVICE(&pca954x->channel[channel]),
90
- "i2c-bus"));
91
-}
92
-
93
-static void pca954x_channel_init(Object *obj)
94
-{
95
- Pca954xChannel *s = PCA954X_CHANNEL(obj);
96
- s->bus = i2c_init_bus(DEVICE(s), "i2c-bus");
97
-
98
- /* Start all channels as disabled. */
99
- s->enabled = false;
100
-}
101
-
102
-static void pca954x_channel_class_init(ObjectClass *klass, void *data)
103
-{
104
- DeviceClass *dc = DEVICE_CLASS(klass);
105
- dc->desc = "Pca954x Channel";
106
+ return pca954x->bus[channel];
107
}
108
109
static void pca9546_class_init(ObjectClass *klass, void *data)
110
@@ -XXX,XX +XXX,XX @@ static void pca9548_class_init(ObjectClass *klass, void *data)
111
s->nchans = PCA9548_CHANNEL_COUNT;
112
}
113
114
-static void pca954x_realize(DeviceState *dev, Error **errp)
115
-{
116
- Pca954xState *s = PCA954X(dev);
117
- Pca954xClass *c = PCA954X_GET_CLASS(s);
118
- int i;
119
-
120
- /* SMBus modules. Cannot fail. */
121
- for (i = 0; i < c->nchans; i++) {
122
- sysbus_realize(SYS_BUS_DEVICE(&s->channel[i]), &error_abort);
123
- }
124
-}
125
-
126
static void pca954x_init(Object *obj)
21
{
127
{
22
- FloatParts r;
128
Pca954xState *s = PCA954X(obj);
23
+ FloatParts r = {};
129
Pca954xClass *c = PCA954X_GET_CLASS(obj);
24
if (a == 0) {
130
int i;
25
r.cls = float_class_zero;
131
26
r.sign = false;
132
- /* Only initialize the children we expect. */
133
+ /* SMBus modules. Cannot fail. */
134
for (i = 0; i < c->nchans; i++) {
135
- object_initialize_child(obj, "channel[*]", &s->channel[i],
136
- TYPE_PCA954X_CHANNEL);
137
+ g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i);
138
+
139
+ /* start all channels as disabled. */
140
+ s->enabled[i] = false;
141
+ s->bus[i] = i2c_init_bus(DEVICE(s), bus_name);
142
}
143
}
144
145
@@ -XXX,XX +XXX,XX @@ static void pca954x_class_init(ObjectClass *klass, void *data)
146
rc->phases.enter = pca954x_enter_reset;
147
148
dc->desc = "Pca954x i2c-mux";
149
- dc->realize = pca954x_realize;
150
151
k->write_data = pca954x_write_data;
152
k->receive_byte = pca954x_read_byte;
153
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pca954x_info[] = {
154
.parent = TYPE_PCA954X,
155
.class_init = pca9548_class_init,
156
},
157
- {
158
- .name = TYPE_PCA954X_CHANNEL,
159
- .parent = TYPE_SYS_BUS_DEVICE,
160
- .class_init = pca954x_channel_class_init,
161
- .instance_size = sizeof(Pca954xChannel),
162
- .instance_init = pca954x_channel_init,
163
- }
164
};
165
166
DEFINE_TYPES(pca954x_info)
27
--
167
--
28
2.17.0
168
2.25.1
29
169
30
170
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
[PULL 05/26] target/arm: Support PSCI 1.1 and SMCCC 1.0
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Akihiko Odaki <akihiko.odaki@gmail.com>
2
2
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
3
Support the latest PSCI on TCG and HVF. A 64-bit function called from
4
AArch32 now returns NOT_SUPPORTED, which is necessary to adhere to SMC
5
Calling Convention 1.0. It is still not compliant with SMCCC 1.3 since
6
they do not implement mandatory functions.
4
7
5
The block length is predefined to 512 bits
8
Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com>
6
9
Message-id: 20220213035753.34577-1-akihiko.odaki@gmail.com
7
and "4.10.2 SD Status":
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: update MISMATCH_CHECK checks on PSCI_VERSION macros to match]
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
13
---
21
hw/sd/sd.c | 2 +-
14
target/arm/kvm-consts.h | 13 +++++++++----
22
1 file changed, 1 insertion(+), 1 deletion(-)
15
hw/arm/boot.c | 12 +++++++++---
16
target/arm/cpu.c | 5 +++--
17
target/arm/hvf/hvf.c | 27 ++++++++++++++++++++++++++-
18
target/arm/kvm64.c | 2 +-
19
target/arm/psci.c | 35 ++++++++++++++++++++++++++++++++---
20
6 files changed, 80 insertions(+), 14 deletions(-)
23
21
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
22
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
25
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
24
--- a/target/arm/kvm-consts.h
27
+++ b/hw/sd/sd.c
25
+++ b/target/arm/kvm-consts.h
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
26
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
27
#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)
30
}
28
#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)
31
memset(&sd->data[17], 0, 47);
29
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
30
+#define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10)
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
31
+
32
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);
33
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);
34
MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);
35
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);
36
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);
37
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);
38
MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);
39
+MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);
40
41
/* PSCI v0.2 return values used by TCG emulation of PSCI */
42
43
/* No Trusted OS migration to worry about when offlining CPUs */
44
#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2
45
46
-/* We implement version 0.2 only */
47
-#define QEMU_PSCI_0_2_RET_VERSION_0_2 2
48
+#define QEMU_PSCI_VERSION_0_1 0x00001
49
+#define QEMU_PSCI_VERSION_0_2 0x00002
50
+#define QEMU_PSCI_VERSION_1_1 0x10001
51
52
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
53
-MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,
54
- (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2)));
55
+/* We don't bother to check every possible version value */
56
+MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2));
57
+MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1));
58
59
/* PSCI return values (inclusive of all PSCI versions) */
60
#define QEMU_PSCI_RET_SUCCESS 0
61
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/hw/arm/boot.c
64
+++ b/hw/arm/boot.c
65
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
66
}
67
68
qemu_fdt_add_subnode(fdt, "/psci");
69
- if (armcpu->psci_version == 2) {
70
- const char comp[] = "arm,psci-0.2\0arm,psci";
71
- qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
72
+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||
73
+ armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {
74
+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {
75
+ const char comp[] = "arm,psci-0.2\0arm,psci";
76
+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
77
+ } else {
78
+ const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci";
79
+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
80
+ }
81
82
cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
83
if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
84
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/target/arm/cpu.c
87
+++ b/target/arm/cpu.c
88
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)
89
* picky DTB consumer will also provide a helpful error message.
90
*/
91
cpu->dtb_compatible = "qemu,unknown";
92
- cpu->psci_version = 1; /* By default assume PSCI v0.1 */
93
+ cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
94
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
95
96
if (tcg_enabled() || hvf_enabled()) {
97
- cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */
98
+ /* TCG and HVF implement PSCI 1.1 */
99
+ cpu->psci_version = QEMU_PSCI_VERSION_1_1;
100
}
34
}
101
}
35
102
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
103
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
104
index XXXXXXX..XXXXXXX 100644
105
--- a/target/arm/hvf/hvf.c
106
+++ b/target/arm/hvf/hvf.c
107
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
108
109
switch (param[0]) {
110
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
111
- ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
112
+ ret = QEMU_PSCI_VERSION_1_1;
113
break;
114
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
115
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
116
@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)
117
case QEMU_PSCI_0_2_FN_MIGRATE:
118
ret = QEMU_PSCI_RET_NOT_SUPPORTED;
119
break;
120
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
121
+ switch (param[1]) {
122
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
123
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
124
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
125
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
126
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
127
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
128
+ case QEMU_PSCI_0_1_FN_CPU_ON:
129
+ case QEMU_PSCI_0_2_FN_CPU_ON:
130
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
131
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
132
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
133
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
134
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
135
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
136
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
137
+ ret = 0;
138
+ break;
139
+ case QEMU_PSCI_0_1_FN_MIGRATE:
140
+ case QEMU_PSCI_0_2_FN_MIGRATE:
141
+ default:
142
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
143
+ }
144
+ break;
145
default:
146
return false;
147
}
148
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/kvm64.c
151
+++ b/target/arm/kvm64.c
152
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
153
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
154
}
155
if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
156
- cpu->psci_version = 2;
157
+ cpu->psci_version = QEMU_PSCI_VERSION_0_2;
158
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
159
}
160
if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
161
diff --git a/target/arm/psci.c b/target/arm/psci.c
162
index XXXXXXX..XXXXXXX 100644
163
--- a/target/arm/psci.c
164
+++ b/target/arm/psci.c
165
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
166
{
167
/*
168
* This function partially implements the logic for dispatching Power State
169
- * Coordination Interface (PSCI) calls (as described in ARM DEN 0022B.b),
170
+ * Coordination Interface (PSCI) calls (as described in ARM DEN 0022D.b),
171
* to the extent required for bringing up and taking down secondary cores,
172
* and for handling reset and poweroff requests.
173
* Additional information about the calling convention used is available in
174
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
175
}
176
177
if ((param[0] & QEMU_PSCI_0_2_64BIT) && !is_a64(env)) {
178
- ret = QEMU_PSCI_RET_INVALID_PARAMS;
179
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
180
goto err;
181
}
182
183
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
184
ARMCPU *target_cpu;
185
186
case QEMU_PSCI_0_2_FN_PSCI_VERSION:
187
- ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
188
+ ret = QEMU_PSCI_VERSION_1_1;
189
break;
190
case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
191
ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
192
@@ -XXX,XX +XXX,XX @@ void arm_handle_psci_call(ARMCPU *cpu)
193
}
194
helper_wfi(env, 4);
195
break;
196
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
197
+ switch (param[1]) {
198
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
199
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
200
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
201
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
202
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
203
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
204
+ case QEMU_PSCI_0_1_FN_CPU_ON:
205
+ case QEMU_PSCI_0_2_FN_CPU_ON:
206
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
207
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
208
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
209
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
210
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
211
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
212
+ case QEMU_PSCI_1_0_FN_PSCI_FEATURES:
213
+ if (!(param[1] & QEMU_PSCI_0_2_64BIT) || is_a64(env)) {
214
+ ret = 0;
215
+ break;
216
+ }
217
+ /* fallthrough */
218
+ case QEMU_PSCI_0_1_FN_MIGRATE:
219
+ case QEMU_PSCI_0_2_FN_MIGRATE:
220
+ default:
221
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
222
+ break;
223
+ }
224
+ break;
225
case QEMU_PSCI_0_1_FN_MIGRATE:
226
case QEMU_PSCI_0_2_FN_MIGRATE:
227
default:
37
--
228
--
38
2.17.0
229
2.25.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
[PULL 06/26] target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Wentao_Liang <Wentao_Liang_g@163.com>
2
2
3
No sense in emitting code after the exception.
3
handle_simd_shift_fpint_conv() was accidentally freeing the TCG
4
temporary tcg_fpstatus too early, before the last use of it. Move
5
the free down to where it belongs.
4
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Wentao_Liang <Wentao_Liang_g@163.com>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
9
[PMM: cleaned up commit message]
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
target/arm/translate-a64.c | 2 +-
12
target/arm/translate-a64.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
19
default:
20
/* all other sf/type/rmode combinations are invalid */
21
unallocated_encoding(s);
22
- break;
23
+ return;
24
}
20
}
25
21
}
26
if (!fp_access_check(s)) {
22
23
- tcg_temp_free_ptr(tcg_fpstatus);
24
tcg_temp_free_i32(tcg_shift);
25
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
26
+ tcg_temp_free_ptr(tcg_fpstatus);
27
tcg_temp_free_i32(tcg_rmode);
28
}
29
27
--
30
--
28
2.17.0
31
2.25.1
29
30
diff view generated by jsdifflib
New patch
[PULL 07/26] tests/qtest: add qtests for npcm7xx sdhci
1
From: Shengtan Mao <stmao@google.com>
1
2
3
Reviewed-by: Hao Wu <wuhaotsh@google.com>
4
Reviewed-by: Chris Rauer <crauer@google.com>
5
Signed-off-by: Shengtan Mao <stmao@google.com>
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Message-id: 20220225174451.192304-1-wuhaotsh@google.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
tests/qtest/npcm7xx_sdhci-test.c | 215 +++++++++++++++++++++++++++++++
11
tests/qtest/meson.build | 1 +
12
2 files changed, 216 insertions(+)
13
create mode 100644 tests/qtest/npcm7xx_sdhci-test.c
14
15
diff --git a/tests/qtest/npcm7xx_sdhci-test.c b/tests/qtest/npcm7xx_sdhci-test.c
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/tests/qtest/npcm7xx_sdhci-test.c
20
@@ -XXX,XX +XXX,XX @@
21
+/*
22
+ * QTests for NPCM7xx SD-3.0 / MMC-4.51 Host Controller
23
+ *
24
+ * Copyright (c) 2022 Google LLC
25
+ *
26
+ * This program is free software; you can redistribute it and/or modify it
27
+ * under the terms of the GNU General Public License as published by the
28
+ * Free Software Foundation; either version 2 of the License, or
29
+ * (at your option) any later version.
30
+ *
31
+ * This program is distributed in the hope that it will be useful, but WITHOUT
32
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
33
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
34
+ * for more details.
35
+ */
36
+
37
+#include "qemu/osdep.h"
38
+#include "hw/sd/npcm7xx_sdhci.h"
39
+
40
+#include "libqos/libqtest.h"
41
+#include "libqtest-single.h"
42
+#include "libqos/sdhci-cmd.h"
43
+
44
+#define NPCM7XX_REG_SIZE 0x100
45
+#define NPCM7XX_MMC_BA 0xF0842000
46
+#define NPCM7XX_BLK_SIZE 512
47
+#define NPCM7XX_TEST_IMAGE_SIZE (1 << 30)
48
+
49
+char *sd_path;
50
+
51
+static QTestState *setup_sd_card(void)
52
+{
53
+ QTestState *qts = qtest_initf(
54
+ "-machine kudo-bmc "
55
+ "-device sd-card,drive=drive0 "
56
+ "-drive id=drive0,if=none,file=%s,format=raw,auto-read-only=off",
57
+ sd_path);
58
+
59
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL);
60
+ qtest_writew(qts, NPCM7XX_MMC_BA + SDHC_CLKCON,
61
+ SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE |
62
+ SDHC_CLOCK_INT_EN);
63
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD);
64
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x41200000, 0, (41 << 8));
65
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID);
66
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0, 0, SDHC_SEND_RELATIVE_ADDR);
67
+ sdhci_cmd_regs(qts, NPCM7XX_MMC_BA, 0, 0, 0x45670000, 0,
68
+ SDHC_SELECT_DESELECT_CARD);
69
+
70
+ return qts;
71
+}
72
+
73
+static void write_sdread(QTestState *qts, const char *msg)
74
+{
75
+ int fd, ret;
76
+ size_t len = strlen(msg);
77
+ char *rmsg = g_malloc(len);
78
+
79
+ /* write message to sd */
80
+ fd = open(sd_path, O_WRONLY);
81
+ g_assert(fd >= 0);
82
+ ret = write(fd, msg, len);
83
+ close(fd);
84
+ g_assert(ret == len);
85
+
86
+ /* read message using sdhci */
87
+ ret = sdhci_read_cmd(qts, NPCM7XX_MMC_BA, rmsg, len);
88
+ g_assert(ret == len);
89
+ g_assert(!memcmp(rmsg, msg, len));
90
+
91
+ g_free(rmsg);
92
+}
93
+
94
+/* Check MMC can read values from sd */
95
+static void test_read_sd(void)
96
+{
97
+ QTestState *qts = setup_sd_card();
98
+
99
+ write_sdread(qts, "hello world");
100
+ write_sdread(qts, "goodbye");
101
+
102
+ qtest_quit(qts);
103
+}
104
+
105
+static void sdwrite_read(QTestState *qts, const char *msg)
106
+{
107
+ int fd, ret;
108
+ size_t len = strlen(msg);
109
+ char *rmsg = g_malloc(len);
110
+
111
+ /* write message using sdhci */
112
+ sdhci_write_cmd(qts, NPCM7XX_MMC_BA, msg, len, NPCM7XX_BLK_SIZE);
113
+
114
+ /* read message from sd */
115
+ fd = open(sd_path, O_RDONLY);
116
+ g_assert(fd >= 0);
117
+ ret = read(fd, rmsg, len);
118
+ close(fd);
119
+ g_assert(ret == len);
120
+
121
+ g_assert(!memcmp(rmsg, msg, len));
122
+
123
+ g_free(rmsg);
124
+}
125
+
126
+/* Check MMC can write values to sd */
127
+static void test_write_sd(void)
128
+{
129
+ QTestState *qts = setup_sd_card();
130
+
131
+ sdwrite_read(qts, "hello world");
132
+ sdwrite_read(qts, "goodbye");
133
+
134
+ qtest_quit(qts);
135
+}
136
+
137
+/* Check SDHCI has correct default values. */
138
+static void test_reset(void)
139
+{
140
+ QTestState *qts = qtest_init("-machine kudo-bmc");
141
+ uint64_t addr = NPCM7XX_MMC_BA;
142
+ uint64_t end_addr = addr + NPCM7XX_REG_SIZE;
143
+ uint16_t prstvals_resets[] = {NPCM7XX_PRSTVALS_0_RESET,
144
+ NPCM7XX_PRSTVALS_1_RESET,
145
+ 0,
146
+ NPCM7XX_PRSTVALS_3_RESET,
147
+ 0,
148
+ 0};
149
+ int i;
150
+ uint32_t mask;
151
+
152
+ while (addr < end_addr) {
153
+ switch (addr - NPCM7XX_MMC_BA) {
154
+ case SDHC_PRNSTS:
155
+ /*
156
+ * ignores bits 20 to 24: they are changed when reading registers
157
+ */
158
+ mask = 0x1f00000;
159
+ g_assert_cmphex(qtest_readl(qts, addr) | mask, ==,
160
+ NPCM7XX_PRSNTS_RESET | mask);
161
+ addr += 4;
162
+ break;
163
+ case SDHC_BLKGAP:
164
+ g_assert_cmphex(qtest_readb(qts, addr), ==, NPCM7XX_BLKGAP_RESET);
165
+ addr += 1;
166
+ break;
167
+ case SDHC_CAPAB:
168
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_CAPAB_RESET);
169
+ addr += 8;
170
+ break;
171
+ case SDHC_MAXCURR:
172
+ g_assert_cmphex(qtest_readq(qts, addr), ==, NPCM7XX_MAXCURR_RESET);
173
+ addr += 8;
174
+ break;
175
+ case SDHC_HCVER:
176
+ g_assert_cmphex(qtest_readw(qts, addr), ==, NPCM7XX_HCVER_RESET);
177
+ addr += 2;
178
+ break;
179
+ case NPCM7XX_PRSTVALS:
180
+ for (i = 0; i < NPCM7XX_PRSTVALS_SIZE; ++i) {
181
+ g_assert_cmphex(qtest_readw(qts, addr + 2 * i), ==,
182
+ prstvals_resets[i]);
183
+ }
184
+ addr += NPCM7XX_PRSTVALS_SIZE * 2;
185
+ break;
186
+ default:
187
+ g_assert_cmphex(qtest_readb(qts, addr), ==, 0);
188
+ addr += 1;
189
+ }
190
+ }
191
+
192
+ qtest_quit(qts);
193
+}
194
+
195
+static void drive_destroy(void)
196
+{
197
+ unlink(sd_path);
198
+ g_free(sd_path);
199
+}
200
+
201
+static void drive_create(void)
202
+{
203
+ int fd, ret;
204
+ GError *error = NULL;
205
+
206
+ /* Create a temporary raw image */
207
+ fd = g_file_open_tmp("sdhci_XXXXXX", &sd_path, &error);
208
+ if (fd == -1) {
209
+ fprintf(stderr, "unable to create sdhci file: %s\n", error->message);
210
+ g_error_free(error);
211
+ }
212
+ g_assert(sd_path != NULL);
213
+
214
+ ret = ftruncate(fd, NPCM7XX_TEST_IMAGE_SIZE);
215
+ g_assert_cmpint(ret, ==, 0);
216
+ g_message("%s", sd_path);
217
+ close(fd);
218
+}
219
+
220
+int main(int argc, char **argv)
221
+{
222
+ int ret;
223
+
224
+ drive_create();
225
+
226
+ g_test_init(&argc, &argv, NULL);
227
+
228
+ qtest_add_func("npcm7xx_sdhci/reset", test_reset);
229
+ qtest_add_func("npcm7xx_sdhci/write_sd", test_write_sd);
230
+ qtest_add_func("npcm7xx_sdhci/read_sd", test_read_sd);
231
+
232
+ ret = g_test_run();
233
+ drive_destroy();
234
+ return ret;
235
+}
236
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
237
index XXXXXXX..XXXXXXX 100644
238
--- a/tests/qtest/meson.build
239
+++ b/tests/qtest/meson.build
240
@@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \
241
'npcm7xx_gpio-test',
242
'npcm7xx_pwm-test',
243
'npcm7xx_rng-test',
244
+ 'npcm7xx_sdhci-test',
245
'npcm7xx_smbus-test',
246
'npcm7xx_timer-test',
247
'npcm7xx_watchdog_timer-test'] + \
248
--
249
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
[PULL 08/26] hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
All the hard work is already done by vfp_expand_imm, we just need to
3
Add new macros to manipulate signed fields within the register.
4
make sure we pick up the correct size.
5
4
6
Cc: qemu-stable@nongnu.org
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
7
Message-id: 20220301215958.157011-2-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
11
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
12
include/hw/registerfields.h | 48 ++++++++++++++++++++++++++++++++++++-
17
1 file changed, 17 insertions(+), 3 deletions(-)
13
1 file changed, 47 insertions(+), 1 deletion(-)
18
14
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
17
--- a/include/hw/registerfields.h
22
+++ b/target/arm/translate-a64.c
18
+++ b/include/hw/registerfields.h
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@
24
{
20
extract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
25
int rd = extract32(insn, 0, 5);
21
R_ ## reg ## _ ## field ## _LENGTH)
26
int imm8 = extract32(insn, 13, 8);
22
27
- int is_double = extract32(insn, 22, 2);
23
+#define FIELD_SEX8(storage, reg, field) \
28
+ int type = extract32(insn, 22, 2);
24
+ sextract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \
29
uint64_t imm;
25
+ R_ ## reg ## _ ## field ## _LENGTH)
30
TCGv_i64 tcg_res;
26
+#define FIELD_SEX16(storage, reg, field) \
31
+ TCGMemOp sz;
27
+ sextract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \
32
28
+ R_ ## reg ## _ ## field ## _LENGTH)
33
- if (is_double > 1) {
29
+#define FIELD_SEX32(storage, reg, field) \
34
+ switch (type) {
30
+ sextract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
35
+ case 0:
31
+ R_ ## reg ## _ ## field ## _LENGTH)
36
+ sz = MO_32;
32
+#define FIELD_SEX64(storage, reg, field) \
37
+ break;
33
+ sextract64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
38
+ case 1:
34
+ R_ ## reg ## _ ## field ## _LENGTH)
39
+ sz = MO_64;
35
+
40
+ break;
36
/* Extract a field from an array of registers */
41
+ case 3:
37
#define ARRAY_FIELD_EX32(regs, reg, field) \
42
+ sz = MO_16;
38
FIELD_EX32((regs)[R_ ## reg], reg, field)
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
39
@@ -XXX,XX +XXX,XX @@
44
+ break;
40
_d; })
45
+ }
41
#define FIELD_DP64(storage, reg, field, val) ({ \
46
+ /* fallthru */
42
struct { \
47
+ default:
43
- uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
48
unallocated_encoding(s);
44
+ uint64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
49
return;
45
+ } _v = { .v = val }; \
50
}
46
+ uint64_t _d; \
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
47
+ _d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
52
return;
48
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
53
}
49
+ _d; })
54
50
+
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
51
+#define FIELD_SDP8(storage, reg, field, val) ({ \
56
+ imm = vfp_expand_imm(sz, imm8);
52
+ struct { \
57
53
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
58
tcg_res = tcg_const_i64(imm);
54
+ } _v = { .v = val }; \
59
write_fp_dreg(s, rd, tcg_res);
55
+ uint8_t _d; \
56
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
57
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
58
+ _d; })
59
+#define FIELD_SDP16(storage, reg, field, val) ({ \
60
+ struct { \
61
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
62
+ } _v = { .v = val }; \
63
+ uint16_t _d; \
64
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
65
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
66
+ _d; })
67
+#define FIELD_SDP32(storage, reg, field, val) ({ \
68
+ struct { \
69
+ signed int v:R_ ## reg ## _ ## field ## _LENGTH; \
70
+ } _v = { .v = val }; \
71
+ uint32_t _d; \
72
+ _d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
73
+ R_ ## reg ## _ ## field ## _LENGTH, _v.v); \
74
+ _d; })
75
+#define FIELD_SDP64(storage, reg, field, val) ({ \
76
+ struct { \
77
+ int64_t v:R_ ## reg ## _ ## field ## _LENGTH; \
78
} _v = { .v = val }; \
79
uint64_t _d; \
80
_d = deposit64((storage), R_ ## reg ## _ ## field ## _SHIFT, \
60
--
81
--
61
2.17.0
82
2.25.1
62
83
63
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
[PULL 09/26] target/arm: Set TCR_EL1.TSZ for user-only
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
From: Richard Henderson <richard.henderson@linaro.org>
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
8
2
9
Add the missing initialization.
3
Set this as the kernel would, to 48 bits, to keep the computation
4
of the address space correct for PAuth.
10
5
11
Fixes: d81ce0ef2c4f105
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Cc: qemu-stable@nongnu.org
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220301215958.157011-3-richard.henderson@linaro.org
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
10
---
18
target/arm/cpu.c | 2 ++
11
target/arm/cpu.c | 3 ++-
19
1 file changed, 2 insertions(+)
12
1 file changed, 2 insertions(+), 1 deletion(-)
20
13
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
16
--- a/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
26
&env->vfp.fp_status);
19
aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1);
27
set_float_detect_tininess(float_tininess_before_rounding,
20
}
28
&env->vfp.standard_fp_status);
21
/*
29
+ set_float_detect_tininess(float_tininess_before_rounding,
22
+ * Enable 48-bit address space (TODO: take reserved_va into account).
30
+ &env->vfp.fp_status_f16);
23
* Enable TBI0 but not TBI1.
31
#ifndef CONFIG_USER_ONLY
24
* Note that this must match useronly_clean_ptr.
32
if (kvm_enabled()) {
25
*/
33
kvm_arm_reset_vcpu(cpu);
26
- env->cp15.tcr_el[1].raw_tcr = (1ULL << 37);
27
+ env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37);
28
29
/* Enable MTE */
30
if (cpu_isar_feature(aa64_mte, cpu)) {
34
--
31
--
35
2.17.0
32
2.25.1
36
37
diff view generated by jsdifflib
New patch
[PULL 10/26] target/arm: Fault on invalid TCR_ELx.TxSZ
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Without FEAT_LVA, the behaviour of programming an invalid value
4
is IMPLEMENTATION DEFINED. With FEAT_LVA, programming an invalid
5
minimum value requires a Translation fault.
6
7
It is most self-consistent to choose to generate the fault always.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220301215958.157011-4-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/internals.h | 1 +
15
target/arm/helper.c | 32 ++++++++++++++++++++++++++++----
16
2 files changed, 29 insertions(+), 4 deletions(-)
17
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
21
+++ b/target/arm/internals.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
23
bool hpd : 1;
24
bool using16k : 1;
25
bool using64k : 1;
26
+ bool tsz_oob : 1; /* tsz has been clamped to legal range */
27
} ARMVAParameters;
28
29
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
30
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/helper.c
33
+++ b/target/arm/helper.c
34
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
35
ARMMMUIdx mmu_idx, bool data)
36
{
37
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
38
- bool epd, hpd, using16k, using64k;
39
- int select, tsz, tbi, max_tsz;
40
+ bool epd, hpd, using16k, using64k, tsz_oob;
41
+ int select, tsz, tbi, max_tsz, min_tsz;
42
43
if (!regime_has_2_ranges(mmu_idx)) {
44
select = 0;
45
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
46
} else {
47
max_tsz = 39;
48
}
49
+ min_tsz = 16; /* TODO: ARMv8.2-LVA */
50
51
- tsz = MIN(tsz, max_tsz);
52
- tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
53
+ if (tsz > max_tsz) {
54
+ tsz = max_tsz;
55
+ tsz_oob = true;
56
+ } else if (tsz < min_tsz) {
57
+ tsz = min_tsz;
58
+ tsz_oob = true;
59
+ } else {
60
+ tsz_oob = false;
61
+ }
62
63
/* Present TBI as a composite with TBID. */
64
tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
65
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
66
.hpd = hpd,
67
.using16k = using16k,
68
.using64k = using64k,
69
+ .tsz_oob = tsz_oob,
70
};
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
74
param = aa64_va_parameters(env, address, mmu_idx,
75
access_type != MMU_INST_FETCH);
76
level = 0;
77
+
78
+ /*
79
+ * If TxSZ is programmed to a value larger than the maximum,
80
+ * or smaller than the effective minimum, it is IMPLEMENTATION
81
+ * DEFINED whether we behave as if the field were programmed
82
+ * within bounds, or if a level 0 Translation fault is generated.
83
+ *
84
+ * With FEAT_LVA, fault on less than minimum becomes required,
85
+ * so our choice is to always raise the fault.
86
+ */
87
+ if (param.tsz_oob) {
88
+ fault_type = ARMFault_Translation;
89
+ goto do_fault;
90
+ }
91
+
92
addrsize = 64 - 8 * param.tbi;
93
inputsize = 64 - param.tsz;
94
} else {
95
--
96
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
[PULL 11/26] target/arm: Move arm_pamax out of line
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 fma operations.
3
We will shortly share parts of this function with other portions
4
of address translation.
4
5
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20220301215958.157011-5-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
13
target/arm/internals.h | 19 +------------------
13
1 file changed, 48 insertions(+)
14
target/arm/helper.c | 22 ++++++++++++++++++++++
15
2 files changed, 23 insertions(+), 18 deletions(-)
14
16
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
19
--- a/target/arm/internals.h
18
+++ b/target/arm/translate-a64.c
20
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
21
@@ -XXX,XX +XXX,XX @@ static inline void update_spsel(CPUARMState *env, uint32_t imm)
20
tcg_temp_free_i64(tcg_res);
22
* Returns the implementation defined bit-width of physical addresses.
23
* The ARMv8 reference manuals refer to this as PAMax().
24
*/
25
-static inline unsigned int arm_pamax(ARMCPU *cpu)
26
-{
27
- static const unsigned int pamax_map[] = {
28
- [0] = 32,
29
- [1] = 36,
30
- [2] = 40,
31
- [3] = 42,
32
- [4] = 44,
33
- [5] = 48,
34
- };
35
- unsigned int parange =
36
- FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
37
-
38
- /* id_aa64mmfr0 is a read-only register so values outside of the
39
- * supported mappings can be considered an implementation error. */
40
- assert(parange < ARRAY_SIZE(pamax_map));
41
- return pamax_map[parange];
42
-}
43
+unsigned int arm_pamax(ARMCPU *cpu);
44
45
/* Return true if extended addresses are enabled.
46
* This is always the case if our translation regime is 64 bit,
47
diff --git a/target/arm/helper.c b/target/arm/helper.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/helper.c
50
+++ b/target/arm/helper.c
51
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
21
}
52
}
22
53
#endif /* !CONFIG_USER_ONLY */
23
+/* Floating-point data-processing (3 source) - half precision */
54
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
55
+/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
25
+ int rd, int rn, int rm, int ra)
56
+unsigned int arm_pamax(ARMCPU *cpu)
26
+{
57
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
58
+ static const unsigned int pamax_map[] = {
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
59
+ [0] = 32,
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
60
+ [1] = 36,
61
+ [2] = 40,
62
+ [3] = 42,
63
+ [4] = 44,
64
+ [5] = 48,
65
+ };
66
+ unsigned int parange =
67
+ FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
30
+
68
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
69
+ /*
32
+ tcg_op2 = read_fp_hreg(s, rm);
70
+ * id_aa64mmfr0 is a read-only register so values outside of the
33
+ tcg_op3 = read_fp_hreg(s, ra);
71
+ * supported mappings can be considered an implementation error.
34
+
35
+ /* These are fused multiply-add, and must be done as one
36
+ * floating point operation with no rounding between the
37
+ * multiplication and addition steps.
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
72
+ */
42
+ if (o1 == true) {
73
+ assert(parange < ARRAY_SIZE(pamax_map));
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
74
+ return pamax_map[parange];
44
+ }
45
+
46
+ if (o0 != o1) {
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
48
+ }
49
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
51
+
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
59
+}
75
+}
60
+
76
+
61
/* Floating point data-processing (3 source)
77
static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
78
{
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
79
if (regime_has_2_ranges(mmu_idx)) {
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
65
}
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
67
break;
68
+ case 3:
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
+ unallocated_encoding(s);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
77
+ break;
78
default:
79
unallocated_encoding(s);
80
}
81
--
80
--
82
2.17.0
81
2.25.1
83
82
84
83
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
[PULL 12/26] target/arm: Pass outputsize down to check_s2_mmu_setup
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
Pass down the width of the output address from translation.
4
For now this is still just PAMax, but a subsequent patch will
5
compute the correct value from TCR_ELx.{I}PS.
6
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20220301215958.157011-6-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
12
target/arm/helper.c | 21 ++++++++++-----------
11
1 file changed, 14 insertions(+), 16 deletions(-)
13
1 file changed, 10 insertions(+), 11 deletions(-)
12
14
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
17
--- a/target/arm/helper.c
16
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
19
@@ -XXX,XX +XXX,XX @@ do_fault:
18
return v;
20
* false otherwise.
19
}
20
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
22
+{
23
+ TCGv_i32 v = tcg_temp_new_i32();
24
+
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
26
+ return v;
27
+}
28
+
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
30
* If SVE is not enabled, then there are only 128 bits in the vector.
31
*/
21
*/
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
22
static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
23
- int inputsize, int stride)
24
+ int inputsize, int stride, int outputsize)
34
{
25
{
35
TCGv_ptr fpst = NULL;
26
const int grainsize = stride + 3;
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
27
int startsizecheck;
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
28
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
29
}
39
30
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
31
if (is_aa64) {
32
- CPUARMState *env = &cpu->env;
33
- unsigned int pamax = arm_pamax(cpu);
41
-
34
-
42
switch (opcode) {
35
switch (stride) {
43
case 0x0: /* FMOV */
36
case 13: /* 64KB Pages. */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
37
- if (level == 0 || (level == 1 && pamax <= 42)) {
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
38
+ if (level == 0 || (level == 1 && outputsize <= 42)) {
46
tcg_temp_free_i64(tcg_op2);
39
return false;
47
tcg_temp_free_i64(tcg_res);
40
}
41
break;
42
case 11: /* 16KB Pages. */
43
- if (level == 0 || (level == 1 && pamax <= 40)) {
44
+ if (level == 0 || (level == 1 && outputsize <= 40)) {
45
return false;
46
}
47
break;
48
case 9: /* 4KB Pages. */
49
- if (level == 0 && pamax <= 42) {
50
+ if (level == 0 && outputsize <= 42) {
51
return false;
52
}
53
break;
54
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
55
}
56
57
/* Inputsize checks. */
58
- if (inputsize > pamax &&
59
- (arm_el_is_aa64(env, 1) || inputsize > 40)) {
60
+ if (inputsize > outputsize &&
61
+ (arm_el_is_aa64(&cpu->env, 1) || inputsize > 40)) {
62
/* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
63
return false;
64
}
65
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
66
target_ulong page_size;
67
uint32_t attrs;
68
int32_t stride;
69
- int addrsize, inputsize;
70
+ int addrsize, inputsize, outputsize;
71
TCR *tcr = regime_tcr(env, mmu_idx);
72
int ap, ns, xn, pxn;
73
uint32_t el = regime_el(env, mmu_idx);
74
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
75
76
addrsize = 64 - 8 * param.tbi;
77
inputsize = 64 - param.tsz;
78
+ outputsize = arm_pamax(cpu);
48
} else {
79
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
80
param = aa32_va_parameters(env, address, mmu_idx);
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
81
level = 1;
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
82
addrsize = (mmu_idx == ARMMMUIdx_Stage2 ? 40 : 32);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
83
inputsize = addrsize - param.tsz;
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
84
+ outputsize = 40;
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
85
}
79
86
80
if (is_scalar) {
87
/*
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
88
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
89
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
90
/* Check that the starting level is valid. */
84
91
ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
92
- inputsize, stride);
86
-
93
+ inputsize, stride, outputsize);
87
switch (fpop) {
94
if (!ok) {
88
case 0x1a: /* FCVTNS */
95
fault_type = ARMFault_Translation;
89
case 0x1b: /* FCVTMS */
96
goto do_fault;
90
--
97
--
91
2.17.0
98
2.25.1
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
[PULL 13/26] target/arm: Use MAKE_64BIT_MASK to compute indexmask
1
In float-to-integer conversion, if the floating point input
1
From: Richard Henderson <richard.henderson@linaro.org>
2
converts exactly to the largest or smallest integer that
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
2
9
Fix the boundary case to take the right half of the if()
3
The macro is a bit more readable than the inlined computation.
10
statements.
11
4
12
This fixes a regression from 2.11 introduced by the softfloat
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
refactoring.
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
7
Message-id: 20220301215958.157011-7-richard.henderson@linaro.org
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
20
---
9
---
21
fpu/softfloat.c | 4 ++--
10
target/arm/helper.c | 4 ++--
22
1 file changed, 2 insertions(+), 2 deletions(-)
11
1 file changed, 2 insertions(+), 2 deletions(-)
23
12
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
25
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
15
--- a/target/arm/helper.c
27
+++ b/fpu/softfloat.c
16
+++ b/target/arm/helper.c
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
17
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
29
r = UINT64_MAX;
18
level = startlevel;
30
}
19
}
31
if (p.sign) {
20
32
- if (r < -(uint64_t) min) {
21
- indexmask_grainsize = (1ULL << (stride + 3)) - 1;
33
+ if (r <= -(uint64_t) min) {
22
- indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
34
return -r;
23
+ indexmask_grainsize = MAKE_64BIT_MASK(0, stride + 3);
35
} else {
24
+ indexmask = MAKE_64BIT_MASK(0, inputsize - (stride * (4 - level)));
36
s->float_exception_flags = orig_flags | float_flag_invalid;
25
37
return min;
26
/* Now we can extract the actual base address from the TTBR */
38
}
27
descaddr = extract64(ttbr, 0, 48);
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
45
--
28
--
46
2.17.0
29
2.25.1
47
30
48
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
[PULL 14/26] target/arm: Honor TCR_ELx.{I}PS
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
This field controls the output (intermediate) physical address size
4
of the translation process. V8 requires to raise an AddressSize
5
fault if the page tables are programmed incorrectly, such that any
6
intermediate descriptor address, or the final translated address,
7
is out of range.
8
9
Add a PS field to ARMVAParameters, and properly compute outputsize
10
in get_phys_addr_lpae. Test the descaddr as extracted from TTBR
11
and from page table entries.
12
13
Restrict descaddrmask so that we won't raise the fault for v7.
14
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
16
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
18
Message-id: 20220301215958.157011-8-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
20
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
21
target/arm/internals.h | 1 +
11
1 file changed, 15 insertions(+), 2 deletions(-)
22
target/arm/helper.c | 72 ++++++++++++++++++++++++++++++++----------
23
2 files changed, 57 insertions(+), 16 deletions(-)
12
24
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
27
--- a/target/arm/internals.h
16
+++ b/target/arm/translate-a64.c
28
+++ b/target/arm/internals.h
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
29
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
18
bool sf = extract32(insn, 31, 1);
30
*/
19
bool itof;
31
typedef struct ARMVAParameters {
20
32
unsigned tsz : 8;
21
- if (sbit || (type > 1)
33
+ unsigned ps : 3;
22
- || (!sf && scale < 32)) {
34
unsigned select : 1;
23
+ if (sbit || (!sf && scale < 32)) {
35
bool tbi : 1;
24
+ unallocated_encoding(s);
36
bool epd : 1;
25
+ return;
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
40
+++ b/target/arm/helper.c
41
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
42
}
43
#endif /* !CONFIG_USER_ONLY */
44
45
+/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
46
+static const uint8_t pamax_map[] = {
47
+ [0] = 32,
48
+ [1] = 36,
49
+ [2] = 40,
50
+ [3] = 42,
51
+ [4] = 44,
52
+ [5] = 48,
53
+};
54
+
55
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
56
unsigned int arm_pamax(ARMCPU *cpu)
57
{
58
- static const unsigned int pamax_map[] = {
59
- [0] = 32,
60
- [1] = 36,
61
- [2] = 40,
62
- [3] = 42,
63
- [4] = 44,
64
- [5] = 48,
65
- };
66
unsigned int parange =
67
FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
68
69
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
70
{
71
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
72
bool epd, hpd, using16k, using64k, tsz_oob;
73
- int select, tsz, tbi, max_tsz, min_tsz;
74
+ int select, tsz, tbi, max_tsz, min_tsz, ps;
75
76
if (!regime_has_2_ranges(mmu_idx)) {
77
select = 0;
78
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
79
hpd = extract32(tcr, 24, 1);
80
}
81
epd = false;
82
+ ps = extract32(tcr, 16, 3);
83
} else {
84
/*
85
* Bit 55 is always between the two regions, and is canonical for
86
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
87
epd = extract32(tcr, 23, 1);
88
hpd = extract64(tcr, 42, 1);
89
}
90
+ ps = extract64(tcr, 32, 3);
91
}
92
93
if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
94
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
95
96
return (ARMVAParameters) {
97
.tsz = tsz,
98
+ .ps = ps,
99
.select = select,
100
.tbi = tbi,
101
.epd = epd,
102
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
103
104
/* TODO: This code does not support shareability levels. */
105
if (aarch64) {
106
+ int ps;
107
+
108
param = aa64_va_parameters(env, address, mmu_idx,
109
access_type != MMU_INST_FETCH);
110
level = 0;
111
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
112
113
addrsize = 64 - 8 * param.tbi;
114
inputsize = 64 - param.tsz;
115
- outputsize = arm_pamax(cpu);
116
+
117
+ /*
118
+ * Bound PS by PARANGE to find the effective output address size.
119
+ * ID_AA64MMFR0 is a read-only register so values outside of the
120
+ * supported mappings can be considered an implementation error.
121
+ */
122
+ ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
123
+ ps = MIN(ps, param.ps);
124
+ assert(ps < ARRAY_SIZE(pamax_map));
125
+ outputsize = pamax_map[ps];
126
} else {
127
param = aa32_va_parameters(env, address, mmu_idx);
128
level = 1;
129
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
130
131
/* Now we can extract the actual base address from the TTBR */
132
descaddr = extract64(ttbr, 0, 48);
133
+
134
+ /*
135
+ * If the base address is out of range, raise AddressSizeFault.
136
+ * In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
137
+ * but we've just cleared the bits above 47, so simplify the test.
138
+ */
139
+ if (descaddr >> outputsize) {
140
+ level = 0;
141
+ fault_type = ARMFault_AddressSize;
142
+ goto do_fault;
26
+ }
143
+ }
27
+
144
+
28
+ switch (type) {
145
/*
29
+ case 0: /* float32 */
146
* We rely on this masking to clear the RES0 bits at the bottom of the TTBR
30
+ case 1: /* float64 */
147
* and also to mask out CnP (bit 0) which could validly be non-zero.
31
+ break;
148
*/
32
+ case 3: /* float16 */
149
descaddr &= ~indexmask;
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
150
34
+ break;
151
- /* The address field in the descriptor goes up to bit 39 for ARMv7
152
- * but up to bit 47 for ARMv8, but we use the descaddrmask
153
- * up to bit 39 for AArch32, because we don't need other bits in that case
154
- * to construct next descriptor address (anyway they should be all zeroes).
155
+ /*
156
+ * For AArch32, the address field in the descriptor goes up to bit 39
157
+ * for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
158
+ * or an AddressSize fault is raised. So for v8 we extract those SBZ
159
+ * bits as part of the address, which will be checked via outputsize.
160
+ * For AArch64, the address field always goes up to bit 47 (with extra
161
+ * bits for FEAT_LPA placed elsewhere). AArch64 implies v8.
162
*/
163
- descaddrmask = ((1ull << (aarch64 ? 48 : 40)) - 1) &
164
- ~indexmask_grainsize;
165
+ if (arm_feature(env, ARM_FEATURE_V8)) {
166
+ descaddrmask = MAKE_64BIT_MASK(0, 48);
167
+ } else {
168
+ descaddrmask = MAKE_64BIT_MASK(0, 40);
169
+ }
170
+ descaddrmask &= ~indexmask_grainsize;
171
172
/* Secure accesses start with the page table in secure memory and
173
* can be downgraded to non-secure at any step. Non-secure accesses
174
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
175
/* Invalid, or the Reserved level 3 encoding */
176
goto do_fault;
177
}
178
+
179
descaddr = descriptor & descaddrmask;
180
+ if (descaddr >> outputsize) {
181
+ fault_type = ARMFault_AddressSize;
182
+ goto do_fault;
35
+ }
183
+ }
36
+ /* fallthru */
184
37
+ default:
185
if ((descriptor & 2) && (level < 3)) {
38
unallocated_encoding(s);
186
/* Table entry. The top five bits are attributes which may
39
return;
40
}
41
--
187
--
42
2.17.0
188
2.25.1
43
189
44
190
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
[PULL 15/26] target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
The original A.a revision of the AArch64 ARM required that we
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
force-extend the addresses in these registers from 49 bits.
5
This language has been loosened via a combination of IMPLEMENTATION
6
DEFINED and CONSTRAINTED UNPREDICTABLE to allow consideration of
7
the entire aligned address.
8
9
This means that we do not have to consider whether or not FEAT_LVA
10
is enabled, and decide from which bit an address might need to be
11
extended.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
15
Message-id: 20220301215958.157011-9-richard.henderson@linaro.org
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
17
---
10
target/arm/helper.h | 6 +++
18
target/arm/helper.c | 32 ++++++++++++++++++++++++--------
11
target/arm/helper.c | 38 ++++++++++++++-
19
1 file changed, 24 insertions(+), 8 deletions(-)
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
13
3 files changed, 122 insertions(+), 18 deletions(-)
14
20
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
18
+++ b/target/arm/helper.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
23
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
24
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
25
@@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
44
#undef VFP_CONV_FIX_A64
26
ARMCPU *cpu = env_archcpu(env);
45
27
int i = ri->crm;
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
28
47
- * Therefore we convert to f64 (which does not round), scale,
29
- /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
48
- * and then convert f64 to f16 (which may round).
30
- * register reads and behaves as if values written are sign extended.
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
31
+ /*
50
+ * vice versa for conversion to integer.
32
* Bits [1:0] are RES0.
51
+ *
33
+ *
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
34
+ * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA)
53
+ * For 64-bit integers, any integer that would cause rounding will also
35
+ * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if
54
+ * overflow to f16 infinity, so there is no double rounding problem.
36
+ * they contain the value written. It is CONSTRAINED UNPREDICTABLE
55
*/
37
+ * whether the RESS bits are ignored when comparing an address.
56
38
+ *
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
39
+ * Therefore we are allowed to compare the entire register, which lets
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
40
+ * us avoid considering whether or not FEAT_LVA is actually enabled.
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
41
*/
60
}
42
- value = sextract64(value, 0, 49) & ~3ULL;
61
43
+ value &= ~3ULL;
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
44
63
+{
45
raw_write(env, ri, value);
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
46
hw_watchpoint_update(cpu, i);
65
+}
47
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
66
+
48
case 0: /* unlinked address match */
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
49
case 1: /* linked address match */
68
+{
50
{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
51
- /* Bits [63:49] are hardwired to the value of bit [48]; that is,
70
+}
52
- * we behave as if the register was sign extended. Bits [1:0] are
71
+
53
- * RES0. The BAS field is used to allow setting breakpoints on 16
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
54
- * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
73
{
55
+ /*
74
if (unlikely(float16_is_any_nan(f))) {
56
+ * Bits [1:0] are RES0.
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
57
+ *
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
58
+ * It is IMPLEMENTATION DEFINED whether bits [63:49]
77
}
59
+ * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit
78
60
+ * of the VA field ([48] or [52] for FEAT_LVA), or whether the
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
61
+ * value is read as written. It is CONSTRAINED UNPREDICTABLE
80
+{
62
+ * whether the RESS bits are ignored when comparing an address.
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
63
+ * Therefore we are allowed to compare the entire register, which
82
+}
64
+ * lets us avoid considering whether FEAT_LVA is actually enabled.
83
+
65
+ *
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
66
+ * The BAS field is used to allow setting breakpoints on 16-bit
85
+{
67
+ * wide instructions; it is CONSTRAINED UNPREDICTABLE whether
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
68
* a bp will fire if the addresses covered by the bp and the addresses
87
+}
69
* covered by the insn overlap but the insn doesn't start at the
88
+
70
* start of the bp address range. We choose to require the insn and
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
71
@@ -XXX,XX +XXX,XX @@ void hw_breakpoint_update(ARMCPU *cpu, int n)
90
+{
72
* See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
73
*/
92
+}
74
int bas = extract64(bcr, 5, 4);
93
+
75
- addr = sextract64(bvr, 0, 49) & ~3ULL;
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
76
+ addr = bvr & ~3ULL;
95
+{
77
if (bas == 0) {
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
78
return;
264
}
79
}
265
--
80
--
266
2.17.0
81
2.25.1
267
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
[PULL 16/26] target/arm: Implement FEAT_LVA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 binary operations.
3
This feature is relatively small, as it applies only to
4
64k pages and thus requires no additional changes to the
5
table descriptor walking algorithm, only a change to the
6
minimum TSZ (which is the inverse of the maximum virtual
7
address space size).
4
8
5
Cc: qemu-stable@nongnu.org
9
Note that this feature widens VBAR_ELx, but we already
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
treat the register as being 64 bits wide.
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
14
Message-id: 20220301215958.157011-10-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
16
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
17
docs/system/arm/emulation.rst | 1 +
13
1 file changed, 65 insertions(+)
18
target/arm/cpu-param.h | 2 +-
19
target/arm/cpu.h | 5 +++++
20
target/arm/cpu64.c | 1 +
21
target/arm/helper.c | 9 ++++++++-
22
5 files changed, 16 insertions(+), 2 deletions(-)
14
23
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
24
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
26
--- a/docs/system/arm/emulation.rst
18
+++ b/target/arm/translate-a64.c
27
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
28
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
tcg_temp_free_i64(tcg_res);
29
- FEAT_LRCPC (Load-acquire RCpc instructions)
30
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
31
- FEAT_LSE (Large System Extensions)
32
+- FEAT_LVA (Large Virtual Address space)
33
- FEAT_MTE (Memory Tagging Extension)
34
- FEAT_MTE2 (Memory Tagging Extension)
35
- FEAT_MTE3 (MTE Asymmetric Fault Handling)
36
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu-param.h
39
+++ b/target/arm/cpu-param.h
40
@@ -XXX,XX +XXX,XX @@
41
#ifdef TARGET_AARCH64
42
# define TARGET_LONG_BITS 64
43
# define TARGET_PHYS_ADDR_SPACE_BITS 48
44
-# define TARGET_VIRT_ADDR_SPACE_BITS 48
45
+# define TARGET_VIRT_ADDR_SPACE_BITS 52
46
#else
47
# define TARGET_LONG_BITS 32
48
# define TARGET_PHYS_ADDR_SPACE_BITS 40
49
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/cpu.h
52
+++ b/target/arm/cpu.h
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
54
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
21
}
55
}
22
56
23
+/* Floating-point data-processing (2 source) - half precision */
57
+static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
25
+ int rd, int rn, int rm)
26
+{
58
+{
27
+ TCGv_i32 tcg_op1;
59
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
28
+ TCGv_i32 tcg_op2;
29
+ TCGv_i32 tcg_res;
30
+ TCGv_ptr fpst;
31
+
32
+ tcg_res = tcg_temp_new_i32();
33
+ fpst = get_fpstatus_ptr(true);
34
+ tcg_op1 = read_fp_hreg(s, rn);
35
+ tcg_op2 = read_fp_hreg(s, rm);
36
+
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
40
+ break;
41
+ case 0x1: /* FDIV */
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
43
+ break;
44
+ case 0x2: /* FADD */
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
65
+ break;
66
+ default:
67
+ g_assert_not_reached();
68
+ }
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
76
+}
60
+}
77
+
61
+
78
/* Floating point data-processing (2 source)
62
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
63
{
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
64
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
65
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
82
}
66
index XXXXXXX..XXXXXXX 100644
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
67
--- a/target/arm/cpu64.c
84
break;
68
+++ b/target/arm/cpu64.c
85
+ case 3:
69
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
70
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
87
+ unallocated_encoding(s);
71
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
88
+ return;
72
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
73
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
74
cpu->isar.id_aa64mmfr2 = t;
75
76
t = cpu->isar.id_aa64zfr0;
77
diff --git a/target/arm/helper.c b/target/arm/helper.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/target/arm/helper.c
80
+++ b/target/arm/helper.c
81
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
82
} else {
83
max_tsz = 39;
84
}
85
- min_tsz = 16; /* TODO: ARMv8.2-LVA */
86
+
87
+ min_tsz = 16;
88
+ if (using64k) {
89
+ if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
90
+ min_tsz = 12;
89
+ }
91
+ }
90
+ if (!fp_access_check(s)) {
92
+ }
91
+ return;
93
+ /* TODO: FEAT_LPA2 */
92
+ }
94
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
95
if (tsz > max_tsz) {
94
+ break;
96
tsz = max_tsz;
95
default:
96
unallocated_encoding(s);
97
}
98
--
97
--
99
2.17.0
98
2.25.1
100
101
diff view generated by jsdifflib
New patch
[PULL 17/26] target/arm: Implement FEAT_LPA
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This feature widens physical addresses (and intermediate physical
4
addresses for 2-stage translation) from 48 to 52 bits, when using
5
64k pages. The only thing left at this point is to handle the
6
extra bits in the TTBR and in the table descriptors.
7
8
Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't
9
mask out the high bits when writing to those registers, so no changes
10
are required there.
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20220301215958.157011-11-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
docs/system/arm/emulation.rst | 1 +
18
target/arm/cpu-param.h | 2 +-
19
target/arm/cpu64.c | 2 +-
20
target/arm/helper.c | 19 ++++++++++++++++---
21
4 files changed, 19 insertions(+), 5 deletions(-)
22
23
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
24
index XXXXXXX..XXXXXXX 100644
25
--- a/docs/system/arm/emulation.rst
26
+++ b/docs/system/arm/emulation.rst
27
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
28
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
29
- FEAT_JSCVT (JavaScript conversion instructions)
30
- FEAT_LOR (Limited ordering regions)
31
+- FEAT_LPA (Large Physical Address space)
32
- FEAT_LRCPC (Load-acquire RCpc instructions)
33
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
34
- FEAT_LSE (Large System Extensions)
35
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/cpu-param.h
38
+++ b/target/arm/cpu-param.h
39
@@ -XXX,XX +XXX,XX @@
40
41
#ifdef TARGET_AARCH64
42
# define TARGET_LONG_BITS 64
43
-# define TARGET_PHYS_ADDR_SPACE_BITS 48
44
+# define TARGET_PHYS_ADDR_SPACE_BITS 52
45
# define TARGET_VIRT_ADDR_SPACE_BITS 52
46
#else
47
# define TARGET_LONG_BITS 32
48
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu64.c
51
+++ b/target/arm/cpu64.c
52
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
53
cpu->isar.id_aa64pfr1 = t;
54
55
t = cpu->isar.id_aa64mmfr0;
56
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
57
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
58
cpu->isar.id_aa64mmfr0 = t;
59
60
t = cpu->isar.id_aa64mmfr1;
61
diff --git a/target/arm/helper.c b/target/arm/helper.c
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/helper.c
64
+++ b/target/arm/helper.c
65
@@ -XXX,XX +XXX,XX @@ static const uint8_t pamax_map[] = {
66
[3] = 42,
67
[4] = 44,
68
[5] = 48,
69
+ [6] = 52,
70
};
71
72
/* The cpu-specific constant value of PAMax; also used by hw/arm/virt. */
73
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
74
descaddr = extract64(ttbr, 0, 48);
75
76
/*
77
- * If the base address is out of range, raise AddressSizeFault.
78
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [5:2] of TTBR.
79
+ *
80
+ * Otherwise, if the base address is out of range, raise AddressSizeFault.
81
* In the pseudocode, this is !IsZero(baseregister<47:outputsize>),
82
* but we've just cleared the bits above 47, so simplify the test.
83
*/
84
- if (descaddr >> outputsize) {
85
+ if (outputsize > 48) {
86
+ descaddr |= extract64(ttbr, 2, 4) << 48;
87
+ } else if (descaddr >> outputsize) {
88
level = 0;
89
fault_type = ARMFault_AddressSize;
90
goto do_fault;
91
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
92
}
93
94
descaddr = descriptor & descaddrmask;
95
- if (descaddr >> outputsize) {
96
+
97
+ /*
98
+ * For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
99
+ * of descriptor. Otherwise, if descaddr is out of range, raise
100
+ * AddressSizeFault.
101
+ */
102
+ if (outputsize > 48) {
103
+ descaddr |= extract64(descriptor, 12, 4) << 48;
104
+ } else if (descaddr >> outputsize) {
105
fault_type = ARMFault_AddressSize;
106
goto do_fault;
107
}
108
--
109
2.25.1
diff view generated by jsdifflib
New patch
[PULL 18/26] target/arm: Extend arm_fi_to_lfsc to level -1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
With FEAT_LPA2, rather than introducing translation level 4,
4
we introduce level -1, below the current level 0. Extend
5
arm_fi_to_lfsc to handle these faults.
6
7
Assert that this new translation level does not leak into
8
fault types for which it is not defined, which allows some
9
masking of fi->level to be removed.
10
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220301215958.157011-12-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/internals.h | 35 +++++++++++++++++++++++++++++------
17
1 file changed, 29 insertions(+), 6 deletions(-)
18
19
diff --git a/target/arm/internals.h b/target/arm/internals.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/internals.h
22
+++ b/target/arm/internals.h
23
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
24
case ARMFault_None:
25
return 0;
26
case ARMFault_AddressSize:
27
- fsc = fi->level & 3;
28
+ assert(fi->level >= -1 && fi->level <= 3);
29
+ if (fi->level < 0) {
30
+ fsc = 0b101001;
31
+ } else {
32
+ fsc = fi->level;
33
+ }
34
break;
35
case ARMFault_AccessFlag:
36
- fsc = (fi->level & 3) | (0x2 << 2);
37
+ assert(fi->level >= 0 && fi->level <= 3);
38
+ fsc = 0b001000 | fi->level;
39
break;
40
case ARMFault_Permission:
41
- fsc = (fi->level & 3) | (0x3 << 2);
42
+ assert(fi->level >= 0 && fi->level <= 3);
43
+ fsc = 0b001100 | fi->level;
44
break;
45
case ARMFault_Translation:
46
- fsc = (fi->level & 3) | (0x1 << 2);
47
+ assert(fi->level >= -1 && fi->level <= 3);
48
+ if (fi->level < 0) {
49
+ fsc = 0b101011;
50
+ } else {
51
+ fsc = 0b000100 | fi->level;
52
+ }
53
break;
54
case ARMFault_SyncExternal:
55
fsc = 0x10 | (fi->ea << 12);
56
break;
57
case ARMFault_SyncExternalOnWalk:
58
- fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12);
59
+ assert(fi->level >= -1 && fi->level <= 3);
60
+ if (fi->level < 0) {
61
+ fsc = 0b010011;
62
+ } else {
63
+ fsc = 0b010100 | fi->level;
64
+ }
65
+ fsc |= fi->ea << 12;
66
break;
67
case ARMFault_SyncParity:
68
fsc = 0x18;
69
break;
70
case ARMFault_SyncParityOnWalk:
71
- fsc = (fi->level & 3) | (0x7 << 2);
72
+ assert(fi->level >= -1 && fi->level <= 3);
73
+ if (fi->level < 0) {
74
+ fsc = 0b011011;
75
+ } else {
76
+ fsc = 0b011100 | fi->level;
77
+ }
78
break;
79
case ARMFault_AsyncParity:
80
fsc = 0x19;
81
--
82
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
[PULL 19/26] target/arm: Introduce tlbi_aa64_get_range
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Adding the fp16 moves to/from general registers.
3
Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base,
4
returning a structure containing both results. Pass in the
5
ARMMMUIdx, rather than the digested two_ranges boolean.
4
6
5
Cc: qemu-stable@nongnu.org
7
This is in preparation for FEAT_LPA2, where the interpretation
8
of 'value' depends on the effective value of DS for the regime.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20220301215958.157011-13-richard.henderson@linaro.org
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
15
target/arm/helper.c | 58 +++++++++++++++++++--------------------------
13
1 file changed, 21 insertions(+)
16
1 file changed, 24 insertions(+), 34 deletions(-)
14
17
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
20
--- a/target/arm/helper.c
18
+++ b/target/arm/translate-a64.c
21
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
22
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
23
}
21
clear_vec_high(s, true, rd);
24
22
break;
25
#ifdef TARGET_AARCH64
23
+ case 3:
26
-static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
24
+ /* 16 bit */
27
- uint64_t value)
25
+ tmp = tcg_temp_new_i64();
28
-{
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
29
- unsigned int page_shift;
27
+ write_fp_dreg(s, rd, tmp);
30
- unsigned int page_size_granule;
28
+ tcg_temp_free_i64(tmp);
31
- uint64_t num;
29
+ break;
32
- uint64_t scale;
30
+ default:
33
- uint64_t exponent;
31
+ g_assert_not_reached();
34
+typedef struct {
32
}
35
+ uint64_t base;
36
uint64_t length;
37
+} TLBIRange;
38
+
39
+static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
40
+ uint64_t value)
41
+{
42
+ unsigned int page_size_granule, page_shift, num, scale, exponent;
43
+ TLBIRange ret = { };
44
45
- num = extract64(value, 39, 5);
46
- scale = extract64(value, 44, 2);
47
page_size_granule = extract64(value, 46, 2);
48
49
if (page_size_granule == 0) {
50
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
51
page_size_granule);
52
- return 0;
53
+ return ret;
54
}
55
56
page_shift = (page_size_granule - 1) * 2 + 12;
57
-
58
+ num = extract64(value, 39, 5);
59
+ scale = extract64(value, 44, 2);
60
exponent = (5 * scale) + 1;
61
- length = (num + 1) << (exponent + page_shift);
62
63
- return length;
64
-}
65
+ ret.length = (num + 1) << (exponent + page_shift);
66
67
-static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value,
68
- bool two_ranges)
69
-{
70
- /* TODO: ARMv8.7 FEAT_LPA2 */
71
- uint64_t pageaddr;
72
-
73
- if (two_ranges) {
74
- pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
75
+ if (regime_has_2_ranges(mmuidx)) {
76
+ ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
33
} else {
77
} else {
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
78
- pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS;
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
79
+ ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
36
/* 64 bits from top half */
80
}
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
81
38
break;
82
- return pageaddr;
39
+ case 3:
83
+ return ret;
40
+ /* 16 bit */
84
}
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
85
42
+ break;
86
static void do_rvae_write(CPUARMState *env, uint64_t value,
43
+ default:
87
int idxmap, bool synced)
44
+ g_assert_not_reached();
88
{
45
}
89
ARMMMUIdx one_idx = ARM_MMU_IDX_A | ctz32(idxmap);
90
- bool two_ranges = regime_has_2_ranges(one_idx);
91
- uint64_t baseaddr, length;
92
+ TLBIRange range;
93
int bits;
94
95
- baseaddr = tlbi_aa64_range_get_base(env, value, two_ranges);
96
- length = tlbi_aa64_range_get_length(env, value);
97
- bits = tlbbits_for_regime(env, one_idx, baseaddr);
98
+ range = tlbi_aa64_get_range(env, one_idx, value);
99
+ bits = tlbbits_for_regime(env, one_idx, range.base);
100
101
if (synced) {
102
tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env),
103
- baseaddr,
104
- length,
105
+ range.base,
106
+ range.length,
107
idxmap,
108
bits);
109
} else {
110
- tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr,
111
- length, idxmap, bits);
112
+ tlb_flush_range_by_mmuidx(env_cpu(env), range.base,
113
+ range.length, idxmap, bits);
46
}
114
}
47
}
115
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
116
49
case 0xa: /* 64 bit */
50
case 0xd: /* 64 bit to top half of quad */
51
break;
52
+ case 0x6: /* 16-bit float, 32-bit int */
53
+ case 0xe: /* 16-bit float, 64-bit int */
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
55
+ break;
56
+ }
57
+ /* fallthru */
58
default:
59
/* all other sf/type/rmode combinations are invalid */
60
unallocated_encoding(s);
61
--
117
--
62
2.17.0
118
2.25.1
63
64
diff view generated by jsdifflib
New patch
[PULL 20/26] target/arm: Fix TLBIRange.base for 16k and 64k pages
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The shift of the BaseADDR field depends on the translation
4
granule in use.
5
6
Fixes: 84940ed8255 ("target/arm: Add support for FEAT_TLBIRANGE")
7
Reported-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-14-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 5 +++--
14
1 file changed, 3 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
21
ret.length = (num + 1) << (exponent + page_shift);
22
23
if (regime_has_2_ranges(mmuidx)) {
24
- ret.base = sextract64(value, 0, 37) << TARGET_PAGE_BITS;
25
+ ret.base = sextract64(value, 0, 37);
26
} else {
27
- ret.base = extract64(value, 0, 37) << TARGET_PAGE_BITS;
28
+ ret.base = extract64(value, 0, 37);
29
}
30
+ ret.base <<= page_shift;
31
32
return ret;
33
}
34
--
35
2.25.1
diff view generated by jsdifflib
New patch
[PULL 21/26] target/arm: Validate tlbi TG matches translation granule in use
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
For FEAT_LPA2, we will need other ARMVAParameters, which themselves
4
depend on the translation granule in use. We might as well validate
5
that the given TG matches; the architecture "does not require that
6
the instruction invalidates any entries" if this is not true.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220301215958.157011-15-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 10 +++++++---
14
1 file changed, 7 insertions(+), 3 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
21
uint64_t value)
22
{
23
unsigned int page_size_granule, page_shift, num, scale, exponent;
24
+ /* Extract one bit to represent the va selector in use. */
25
+ uint64_t select = sextract64(value, 36, 1);
26
+ ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
27
TLBIRange ret = { };
28
29
page_size_granule = extract64(value, 46, 2);
30
31
- if (page_size_granule == 0) {
32
- qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
33
+ /* The granule encoded in value must match the granule in use. */
34
+ if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
35
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
36
page_size_granule);
37
return ret;
38
}
39
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
40
41
ret.length = (num + 1) << (exponent + page_shift);
42
43
- if (regime_has_2_ranges(mmuidx)) {
44
+ if (param.select) {
45
ret.base = sextract64(value, 0, 37);
46
} else {
47
ret.base = extract64(value, 0, 37);
48
--
49
2.25.1
diff view generated by jsdifflib
New patch
[PULL 22/26] target/arm: Advertise all page sizes for -cpu max
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
We support 16k pages, but do not advertize that in ID_AA64MMFR0.
4
5
The value 0 in the TGRAN*_2 fields indicates that stage2 lookups defer
6
to the same support as stage1 lookups. This setting is deprecated, so
7
indicate support for all stage2 page sizes directly.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20220301215958.157011-16-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu64.c | 4 ++++
15
1 file changed, 4 insertions(+)
16
17
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu64.c
20
+++ b/target/arm/cpu64.c
21
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
22
23
t = cpu->isar.id_aa64mmfr0;
24
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
25
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
26
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
27
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
28
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
29
cpu->isar.id_aa64mmfr0 = t;
30
31
t = cpu->isar.id_aa64mmfr1;
32
--
33
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
[PULL 23/26] target/arm: Implement FEAT_LPA2
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
These where missed out from the rest of the half-precision work.
3
This feature widens physical addresses (and intermediate physical
4
4
addresses for 2-stage translation) from 48 to 52 bits, when using
5
Cc: qemu-stable@nongnu.org
5
4k or 16k pages.
6
7
This introduces the DS bit to TCR_ELx, which is RES0 unless the
8
page size is enabled and supports LPA2, resulting in the effective
9
value of DS for a given table walk. The DS bit changes the format
10
of the page table descriptor slightly, moving the PS field out to
11
TCR so that all pages have the same sharability and repurposing
12
those bits of the page table descriptor for the highest bits of
13
the output address.
14
15
Do not yet enable FEAT_LPA2; we need extra plumbing to avoid
16
tickling an old kernel bug.
17
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
20
Message-id: 20220301215958.157011-17-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
22
---
15
target/arm/helper-a64.h | 2 +
23
docs/system/arm/emulation.rst | 1 +
16
target/arm/helper-a64.c | 10 +++++
24
target/arm/cpu.h | 22 ++++++++
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
25
target/arm/internals.h | 2 +
18
3 files changed, 83 insertions(+), 17 deletions(-)
26
target/arm/helper.c | 102 +++++++++++++++++++++++++++++-----
19
27
4 files changed, 112 insertions(+), 15 deletions(-)
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
28
29
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
21
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
31
--- a/docs/system/arm/emulation.rst
23
+++ b/target/arm/helper-a64.h
32
+++ b/docs/system/arm/emulation.rst
24
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
34
- FEAT_JSCVT (JavaScript conversion instructions)
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
35
- FEAT_LOR (Limited ordering regions)
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
36
- FEAT_LPA (Large Physical Address space)
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
37
+- FEAT_LPA2 (Large Physical and virtual Address space v2)
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
38
- FEAT_LRCPC (Load-acquire RCpc instructions)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
39
- FEAT_LRCPC2 (Load-acquire RCpc instructions v2)
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
40
- FEAT_LSE (Large System Extensions)
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
41
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
43
--- a/target/arm/cpu.h
36
+++ b/target/arm/helper-a64.c
44
+++ b/target/arm/cpu.h
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
45
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
38
return flags;
46
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
39
}
47
}
40
48
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
49
+static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
42
+{
50
+{
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
51
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
44
+}
52
+}
45
+
53
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
54
+static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
47
+{
55
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
56
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
57
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
49
+}
58
+}
50
+
59
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
60
+static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
61
+{
62
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
63
+}
64
+
65
+static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
66
+{
67
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
68
+ return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
69
+}
70
+
71
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
52
{
72
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
73
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
74
diff --git a/target/arm/internals.h b/target/arm/internals.h
55
index XXXXXXX..XXXXXXX 100644
75
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
76
--- a/target/arm/internals.h
57
+++ b/target/arm/translate-a64.c
77
+++ b/target/arm/internals.h
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
78
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
59
}
79
typedef struct ARMVAParameters {
60
}
80
unsigned tsz : 8;
61
81
unsigned ps : 3;
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
82
+ unsigned sh : 2;
63
+static void handle_fp_compare(DisasContext *s, int size,
83
unsigned select : 1;
64
unsigned int rn, unsigned int rm,
84
bool tbi : 1;
65
bool cmp_with_zero, bool signal_all_nans)
85
bool epd : 1;
86
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
87
bool using16k : 1;
88
bool using64k : 1;
89
bool tsz_oob : 1; /* tsz has been clamped to legal range */
90
+ bool ds : 1;
91
} ARMVAParameters;
92
93
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
94
diff --git a/target/arm/helper.c b/target/arm/helper.c
95
index XXXXXXX..XXXXXXX 100644
96
--- a/target/arm/helper.c
97
+++ b/target/arm/helper.c
98
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
99
} else {
100
ret.base = extract64(value, 0, 37);
101
}
102
+ if (param.ds) {
103
+ /*
104
+ * With DS=1, BaseADDR is always shifted 16 so that it is able
105
+ * to address all 52 va bits. The input address is perforce
106
+ * aligned on a 64k boundary regardless of translation granule.
107
+ */
108
+ page_shift = 16;
109
+ }
110
ret.base <<= page_shift;
111
112
return ret;
113
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
114
const int grainsize = stride + 3;
115
int startsizecheck;
116
117
- /* Negative levels are never allowed. */
118
- if (level < 0) {
119
+ /*
120
+ * Negative levels are usually not allowed...
121
+ * Except for FEAT_LPA2, 4k page table, 52-bit address space, which
122
+ * begins with level -1. Note that previous feature tests will have
123
+ * eliminated this combination if it is not enabled.
124
+ */
125
+ if (level < (inputsize == 52 && stride == 9 ? -1 : 0)) {
126
return false;
127
}
128
129
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
130
ARMMMUIdx mmu_idx, bool data)
66
{
131
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
132
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
133
- bool epd, hpd, using16k, using64k, tsz_oob;
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
134
- int select, tsz, tbi, max_tsz, min_tsz, ps;
70
135
+ bool epd, hpd, using16k, using64k, tsz_oob, ds;
71
- if (is_double) {
136
+ int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
72
+ if (size == MO_64) {
137
+ ARMCPU *cpu = env_archcpu(env);
73
TCGv_i64 tcg_vn, tcg_vm;
138
74
139
if (!regime_has_2_ranges(mmu_idx)) {
75
tcg_vn = read_fp_dreg(s, rn);
140
select = 0;
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
141
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
77
tcg_temp_free_i64(tcg_vn);
142
hpd = extract32(tcr, 24, 1);
78
tcg_temp_free_i64(tcg_vm);
143
}
144
epd = false;
145
+ sh = extract32(tcr, 12, 2);
146
ps = extract32(tcr, 16, 3);
147
+ ds = extract64(tcr, 32, 1);
79
} else {
148
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
149
/*
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
150
* Bit 55 is always between the two regions, and is canonical for
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
151
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
83
152
if (!select) {
84
- tcg_vn = read_fp_sreg(s, rn);
153
tsz = extract32(tcr, 0, 6);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
154
epd = extract32(tcr, 7, 1);
86
if (cmp_with_zero) {
155
+ sh = extract32(tcr, 12, 2);
87
- tcg_vm = tcg_const_i32(0);
156
using64k = extract32(tcr, 14, 1);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
157
using16k = extract32(tcr, 15, 1);
89
} else {
158
hpd = extract64(tcr, 41, 1);
90
- tcg_vm = read_fp_sreg(s, rm);
159
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
160
using64k = tg == 3;
161
tsz = extract32(tcr, 16, 6);
162
epd = extract32(tcr, 23, 1);
163
+ sh = extract32(tcr, 28, 2);
164
hpd = extract64(tcr, 42, 1);
92
}
165
}
93
- if (signal_all_nans) {
166
ps = extract64(tcr, 32, 3);
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
167
+ ds = extract64(tcr, 59, 1);
95
- } else {
168
}
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
169
97
+
170
- if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
98
+ switch (size) {
171
+ if (cpu_isar_feature(aa64_st, cpu)) {
99
+ case MO_32:
172
max_tsz = 48 - using64k;
100
+ if (signal_all_nans) {
173
} else {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
174
max_tsz = 39;
175
}
176
177
+ /*
178
+ * DS is RES0 unless FEAT_LPA2 is supported for the given page size;
179
+ * adjust the effective value of DS, as documented.
180
+ */
181
min_tsz = 16;
182
if (using64k) {
183
- if (cpu_isar_feature(aa64_lva, env_archcpu(env))) {
184
+ if (cpu_isar_feature(aa64_lva, cpu)) {
185
+ min_tsz = 12;
186
+ }
187
+ ds = false;
188
+ } else if (ds) {
189
+ switch (mmu_idx) {
190
+ case ARMMMUIdx_Stage2:
191
+ case ARMMMUIdx_Stage2_S:
192
+ if (using16k) {
193
+ ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
102
+ } else {
194
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
195
+ ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
196
+ }
112
+ break;
197
+ break;
113
+ default:
198
+ default:
114
+ g_assert_not_reached();
199
+ if (using16k) {
115
}
200
+ ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
116
+
201
+ } else {
117
tcg_temp_free_i32(tcg_vn);
202
+ ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu);
118
tcg_temp_free_i32(tcg_vm);
203
+ }
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
204
+ break;
152
+ }
205
+ }
153
+ /* fallthru */
206
+ if (ds) {
154
+ default:
207
min_tsz = 12;
155
unallocated_encoding(s);
208
}
156
return;
209
}
157
}
210
- /* TODO: FEAT_LPA2 */
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
211
159
return;
212
if (tsz > max_tsz) {
160
}
213
tsz = max_tsz;
161
214
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
215
return (ARMVAParameters) {
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
216
.tsz = tsz,
217
.ps = ps,
218
+ .sh = sh,
219
.select = select,
220
.tbi = tbi,
221
.epd = epd,
222
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
223
.using16k = using16k,
224
.using64k = using64k,
225
.tsz_oob = tsz_oob,
226
+ .ds = ds,
227
};
164
}
228
}
165
229
166
/* Floating point conditional compare
230
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
231
* VTCR_EL2.SL0 field (whose interpretation depends on the page size)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
232
*/
169
TCGv_i64 tcg_flags;
233
uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
170
TCGLabel *label_continue = NULL;
234
+ uint32_t sl2 = extract64(tcr->raw_tcr, 33, 1);
171
+ int size;
235
uint32_t startlevel;
172
236
bool ok;
173
mos = extract32(insn, 29, 3);
237
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
238
- if (!aarch64 || stride == 9) {
175
+ type = extract32(insn, 22, 2);
239
+ /* SL2 is RES0 unless DS=1 & 4kb granule. */
176
rm = extract32(insn, 16, 5);
240
+ if (param.ds && stride == 9 && sl2) {
177
cond = extract32(insn, 12, 4);
241
+ if (sl0 != 0) {
178
rn = extract32(insn, 5, 5);
242
+ level = 0;
179
op = extract32(insn, 4, 1);
243
+ fault_type = ARMFault_Translation;
180
nzcv = extract32(insn, 0, 4);
244
+ goto do_fault;
181
245
+ }
182
- if (mos || type > 1) {
246
+ startlevel = -1;
183
+ if (mos) {
247
+ } else if (!aarch64 || stride == 9) {
184
+ unallocated_encoding(s);
248
/* AArch32 or 4KB pages */
185
+ return;
249
startlevel = 2 - sl0;
250
251
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
252
* for both v7 and v8. However, for v8 the SBZ bits [47:40] must be 0
253
* or an AddressSize fault is raised. So for v8 we extract those SBZ
254
* bits as part of the address, which will be checked via outputsize.
255
- * For AArch64, the address field always goes up to bit 47 (with extra
256
- * bits for FEAT_LPA placed elsewhere). AArch64 implies v8.
257
+ * For AArch64, the address field goes up to bit 47, or 49 with FEAT_LPA2;
258
+ * the highest bits of a 52-bit output are placed elsewhere.
259
*/
260
- if (arm_feature(env, ARM_FEATURE_V8)) {
261
+ if (param.ds) {
262
+ descaddrmask = MAKE_64BIT_MASK(0, 50);
263
+ } else if (arm_feature(env, ARM_FEATURE_V8)) {
264
descaddrmask = MAKE_64BIT_MASK(0, 48);
265
} else {
266
descaddrmask = MAKE_64BIT_MASK(0, 40);
267
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
268
269
/*
270
* For FEAT_LPA and PS=6, bits [51:48] of descaddr are in [15:12]
271
- * of descriptor. Otherwise, if descaddr is out of range, raise
272
- * AddressSizeFault.
273
+ * of descriptor. For FEAT_LPA2 and effective DS, bits [51:50] of
274
+ * descaddr are in [9:8]. Otherwise, if descaddr is out of range,
275
+ * raise AddressSizeFault.
276
*/
277
if (outputsize > 48) {
278
- descaddr |= extract64(descriptor, 12, 4) << 48;
279
+ if (param.ds) {
280
+ descaddr |= extract64(descriptor, 8, 2) << 50;
281
+ } else {
282
+ descaddr |= extract64(descriptor, 12, 4) << 48;
283
+ }
284
} else if (descaddr >> outputsize) {
285
fault_type = ARMFault_AddressSize;
286
goto do_fault;
287
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
288
assert(attrindx <= 7);
289
cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
290
}
291
- cacheattrs->shareability = extract32(attrs, 6, 2);
292
+
293
+ /*
294
+ * For FEAT_LPA2 and effective DS, the SH field in the attributes
295
+ * was re-purposed for output address bits. The SH attribute in
296
+ * that case comes from TCR_ELx, which we extracted earlier.
297
+ */
298
+ if (param.ds) {
299
+ cacheattrs->shareability = param.sh;
300
+ } else {
301
+ cacheattrs->shareability = extract32(attrs, 6, 2);
186
+ }
302
+ }
187
+
303
188
+ switch (type) {
304
*phys_ptr = descaddr;
189
+ case 0:
305
*page_size_ptr = page_size;
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
306
--
215
2.17.0
307
2.25.1
216
217
diff view generated by jsdifflib
New patch
[PULL 24/26] target/arm: Report KVM's actual PSCI version to guest in dtb
1
When we're using KVM, the PSCI implementation is provided by the
2
kernel, but QEMU has to tell the guest about it via the device tree.
3
Currently we look at the KVM_CAP_ARM_PSCI_0_2 capability to determine
4
if the kernel is providing at least PSCI 0.2, but if the kernel
5
provides a newer version than that we will still only tell the guest
6
it has PSCI 0.2. (This is fairly harmless; it just means the guest
7
won't use newer parts of the PSCI API.)
1
8
9
The kernel exposes the specific PSCI version it is implementing via
10
the ONE_REG API; use this to report in the dtb that the PSCI
11
implementation is 1.0-compatible if appropriate. (The device tree
12
binding currently only distinguishes "pre-0.2", "0.2-compatible" and
13
"1.0-compatible".)
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Marc Zyngier <maz@kernel.org>
17
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Andrew Jones <drjones@redhat.com>
20
Message-id: 20220224134655.1207865-1-peter.maydell@linaro.org
21
---
22
target/arm/kvm-consts.h | 1 +
23
hw/arm/boot.c | 5 ++---
24
target/arm/kvm64.c | 12 ++++++++++++
25
3 files changed, 15 insertions(+), 3 deletions(-)
26
27
diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/kvm-consts.h
30
+++ b/target/arm/kvm-consts.h
31
@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);
32
33
#define QEMU_PSCI_VERSION_0_1 0x00001
34
#define QEMU_PSCI_VERSION_0_2 0x00002
35
+#define QEMU_PSCI_VERSION_1_0 0x10000
36
#define QEMU_PSCI_VERSION_1_1 0x10001
37
38
MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);
39
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/arm/boot.c
42
+++ b/hw/arm/boot.c
43
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
44
}
45
46
qemu_fdt_add_subnode(fdt, "/psci");
47
- if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||
48
- armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {
49
- if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {
50
+ if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) {
51
+ if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) {
52
const char comp[] = "arm,psci-0.2\0arm,psci";
53
qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
54
} else {
55
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/target/arm/kvm64.c
58
+++ b/target/arm/kvm64.c
59
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
60
uint64_t mpidr;
61
ARMCPU *cpu = ARM_CPU(cs);
62
CPUARMState *env = &cpu->env;
63
+ uint64_t psciver;
64
65
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
66
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
67
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
68
}
69
}
70
71
+ /*
72
+ * KVM reports the exact PSCI version it is implementing via a
73
+ * special sysreg. If it is present, use its contents to determine
74
+ * what to report to the guest in the dtb (it is the PSCI version,
75
+ * in the same 15-bits major 16-bits minor format that PSCI_VERSION
76
+ * returns).
77
+ */
78
+ if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) {
79
+ cpu->psci_version = psciver;
80
+ }
81
+
82
/*
83
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
84
* Currently KVM has its own idea about MPIDR assignment, so we
85
--
86
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
[PULL 25/26] ui/cocoa.m: Fix updateUIInfo threading issues
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The updateUIInfo method makes Cocoa API calls. It also calls back
2
into QEMU functions like dpy_set_ui_info(). To do this safely, we
3
need to follow two rules:
4
* Cocoa API calls are made on the Cocoa UI thread
5
* When calling back into QEMU we must hold the iothread lock
2
6
3
These were missed out from the rest of the half-precision work.
7
Fix the places where we got this wrong, by taking the iothread lock
8
while executing updateUIInfo, and moving the call in cocoa_switch()
9
inside the dispatch_async block.
4
10
5
Cc: qemu-stable@nongnu.org
11
Some of the Cocoa UI methods which call updateUIInfo are invoked as
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
part of the initial application startup, while we're still doing the
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
13
little cross-thread dance described in the comment just above
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
14
call_qemu_main(). This meant they were calling back into the QEMU UI
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
layer before we'd actually finished initializing our display and
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
16
registered the DisplayChangeListener, which isn't really valid. Once
11
[rth: Fix erroneous check vs type]
17
updateUIInfo takes the iothread lock, we no longer get away with
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
18
this, because during this startup phase the iothread lock is held by
19
the QEMU main-loop thread which is waiting for us to finish our
20
display initialization. So we must suppress updateUIInfo until
21
applicationDidFinishLaunching allows the QEMU main-loop thread to
22
continue.
23
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
26
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
27
Message-id: 20220224101330.967429-2-peter.maydell@linaro.org
14
---
28
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
29
ui/cocoa.m | 25 ++++++++++++++++++++++---
16
1 file changed, 25 insertions(+), 6 deletions(-)
30
1 file changed, 22 insertions(+), 3 deletions(-)
17
31
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
diff --git a/ui/cocoa.m b/ui/cocoa.m
19
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
34
--- a/ui/cocoa.m
21
+++ b/target/arm/translate-a64.c
35
+++ b/ui/cocoa.m
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
36
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
23
unsigned int mos, type, rm, cond, rn, rd;
37
}
24
TCGv_i64 t_true, t_false, t_zero;
38
}
25
DisasCompare64 c;
39
26
+ TCGMemOp sz;
40
-- (void) updateUIInfo
27
41
+- (void) updateUIInfoLocked
28
mos = extract32(insn, 29, 3);
42
{
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
43
+ /* Must be called with the iothread lock, i.e. via updateUIInfo */
30
+ type = extract32(insn, 22, 2);
44
NSSize frameSize;
31
rm = extract32(insn, 16, 5);
45
QemuUIInfo info;
32
cond = extract32(insn, 12, 4);
46
33
rn = extract32(insn, 5, 5);
47
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
34
rd = extract32(insn, 0, 5);
48
dpy_set_ui_info(dcl.con, &info, TRUE);
35
49
}
36
- if (mos || type > 1) {
50
37
+ if (mos) {
51
+- (void) updateUIInfo
38
+ unallocated_encoding(s);
52
+{
53
+ if (!allow_events) {
54
+ /*
55
+ * Don't try to tell QEMU about UI information in the application
56
+ * startup phase -- we haven't yet registered dcl with the QEMU UI
57
+ * layer, and also trying to take the iothread lock would deadlock.
58
+ * When cocoa_display_init() does register the dcl, the UI layer
59
+ * will call cocoa_switch(), which will call updateUIInfo, so
60
+ * we don't lose any information here.
61
+ */
39
+ return;
62
+ return;
40
+ }
63
+ }
41
+
64
+
42
+ switch (type) {
65
+ with_iothread_lock(^{
43
+ case 0:
66
+ [self updateUIInfoLocked];
44
+ sz = MO_32;
67
+ });
45
+ break;
68
+}
46
+ case 1:
69
+
47
+ sz = MO_64;
70
- (void)viewDidMoveToWindow
48
+ break;
71
{
49
+ case 3:
72
[self updateUIInfo];
50
+ sz = MO_16;
73
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
74
52
+ break;
75
COCOA_DEBUG("qemu_cocoa: cocoa_switch\n");
53
+ }
76
54
+ /* fallthru */
77
- [cocoaView updateUIInfo];
55
+ default:
78
-
56
unallocated_encoding(s);
79
// The DisplaySurface will be freed as soon as this callback returns.
57
return;
80
// We take a reference to the underlying pixman image here so it does
58
}
81
// not disappear from under our feet; the switchSurface method will
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
82
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
60
return;
83
pixman_image_ref(image);
61
}
84
62
85
dispatch_async(dispatch_get_main_queue(), ^{
63
- /* Zero extend sreg inputs to 64 bits now. */
86
+ [cocoaView updateUIInfo];
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
87
[cocoaView switchSurface:image];
65
t_true = tcg_temp_new_i64();
88
});
66
t_false = tcg_temp_new_i64();
89
[pool release];
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
83
--
90
--
84
2.17.0
91
2.25.1
85
86
diff view generated by jsdifflib
New patch
[PULL 26/26] ui/cocoa.m: Remove unnecessary NSAutoreleasePools
1
In commit 6e657e64cdc478 in 2013 we added some autorelease pools to
2
deal with complaints from macOS when we made calls into Cocoa from
3
threads that didn't have automatically created autorelease pools.
4
Later on, macOS got stricter about forbidding cross-thread Cocoa
5
calls, and in commit 5588840ff77800e839d8 we restructured the code to
6
avoid them. This left the autorelease pool creation in several
7
functions without any purpose; delete it.
1
8
9
We still need the pool in cocoa_refresh() for the clipboard related
10
code which is called directly there.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com>
14
Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com>
15
Message-id: 20220224101330.967429-3-peter.maydell@linaro.org
16
---
17
ui/cocoa.m | 6 ------
18
1 file changed, 6 deletions(-)
19
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
21
index XXXXXXX..XXXXXXX 100644
22
--- a/ui/cocoa.m
23
+++ b/ui/cocoa.m
24
@@ -XXX,XX +XXX,XX @@ int main (int argc, char **argv) {
25
static void cocoa_update(DisplayChangeListener *dcl,
26
int x, int y, int w, int h)
27
{
28
- NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];
29
-
30
COCOA_DEBUG("qemu_cocoa: cocoa_update\n");
31
32
dispatch_async(dispatch_get_main_queue(), ^{
33
@@ -XXX,XX +XXX,XX @@ static void cocoa_update(DisplayChangeListener *dcl,
34
}
35
[cocoaView setNeedsDisplayInRect:rect];
36
});
37
-
38
- [pool release];
39
}
40
41
static void cocoa_switch(DisplayChangeListener *dcl,
42
DisplaySurface *surface)
43
{
44
- NSAutoreleasePool * pool = [[NSAutoreleasePool alloc] init];
45
pixman_image_t *image = surface->image;
46
47
COCOA_DEBUG("qemu_cocoa: cocoa_switch\n");
48
@@ -XXX,XX +XXX,XX @@ static void cocoa_switch(DisplayChangeListener *dcl,
49
[cocoaView updateUIInfo];
50
[cocoaView switchSurface:image];
51
});
52
- [pool release];
53
}
54
55
static void cocoa_refresh(DisplayChangeListener *dcl)
56
--
57
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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