The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

* Fix coverity nit in int_to_float code

* Don't set Invalid for float-to-int(MAXINT)

* Fix fp_status_f16 tininess before rounding

* Add various missing insns from the v8.2-FP16 extension

* Fix sqrt_f16 exception raising

* sdcard: Correct CRC16 offset in sd_function_switch()

* tcg: Optionally log FPU state in TCG -d cpu logging

Alex Bennée (5):

fpu/softfloat: int_to_float ensure r fully initialised

target/arm: Implement FCMP for fp16

target/arm: Implement FCSEL for fp16

target/arm: Implement FMOV (immediate) for fp16

target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):

fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

target/arm: Fix fp_status_f16 tininess before rounding

tcg: Optionally log FPU state in TCG -d cpu logging

sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):

target/arm: Implement FMOV (general) for fp16

target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

target/arm: Implement FCVT (scalar, integer) for fp16

target/arm: Implement FCVT (scalar, fixed-point) for fp16

target/arm: Introduce and use read_fp_hreg

target/arm: Implement FP data-processing (2 source) for fp16

target/arm: Implement FP data-processing (3 source) for fp16

include/qemu/log.h | 1 +

target/arm/helper-a64.h | 2 +

target/arm/helper.h | 6 +

accel/tcg/cpu-exec.c | 9 +-

fpu/softfloat.c | 6 +-

hw/sd/sd.c | 2 +-

target/arm/cpu.c | 2 +

target/arm/helper-a64.c | 10 ++

target/arm/helper.c | 38 +++-

target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------

util/log.c | 2 +

11 files changed, 428 insertions(+), 71 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

Reported by Coverity (CID1390635). We ensure this for uint_to_float

later on so we might as well mirror that.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

fpu/softfloat.c | 2 +-

diff --git a/fpu/softfloat.c b/fpu/softfloat.c

--- a/fpu/softfloat.c

+++ b/fpu/softfloat.c

@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)

static FloatParts int_to_float(int64_t a, float_status *status)

{

- FloatParts r;

+ FloatParts r = {};

if (a == 0) {

r.cls = float_class_zero;

r.sign = false;

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

We are meant to explicitly pass fpst, not cpu_env.

target/arm/translate-a64.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)

tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);

break;

case 0x3: /* FSQRT */

- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);

+ fpst = get_fpstatus_ptr(true);

+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);

break;

case 0x8: /* FRINTN */

case 0x9: /* FRINTP */

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

All the hard work is already done by vfp_expand_imm, we just need to

make sure we pick up the correct size.

Cc: qemu-stable@nongnu.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180512003217.9105-11-richard.henderson@linaro.org

[rth: Merge unallocated_encoding check with TCGMemOp conversion.]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/arm/translate-a64.c | 20 +++++++++++++++++---

1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)

{

int rd = extract32(insn, 0, 5);

int imm8 = extract32(insn, 13, 8);

- int is_double = extract32(insn, 22, 2);

+ int type = extract32(insn, 22, 2);

uint64_t imm;

TCGv_i64 tcg_res;

+ TCGMemOp sz;

- if (is_double > 1) {

+ switch (type) {

+ case 0:

+ sz = MO_32;

+ break;

+ case 1:

+ sz = MO_64;

+ break;

+ case 3:

+ sz = MO_16;

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)

return;

- imm = vfp_expand_imm(MO_32 + is_double, imm8);

+ imm = vfp_expand_imm(sz, imm8);

tcg_res = tcg_const_i64(imm);

write_fp_dreg(s, rd, tcg_res);

2.17.0

In commit d81ce0ef2c4f105 we added an extra float_status field

fp_status_fp16 for Arm, but forgot to initialize it correctly

by setting it to float_tininess_before_rounding. This currently

will only cause problems for the new V8_FP16 feature, since the

float-to-float conversion code doesn't use it yet. The effect

would be that we failed to set the Underflow IEEE exception flag

in all the cases where we should.

Add the missing initialization.

Fixes: d81ce0ef2c4f105

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20180512004311.9299-16-richard.henderson@linaro.org

target/arm/cpu.c | 2 ++

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

&env->vfp.fp_status);

set_float_detect_tininess(float_tininess_before_rounding,

&env->vfp.standard_fp_status);

+ set_float_detect_tininess(float_tininess_before_rounding,

+ &env->vfp.fp_status_f16);

#ifndef CONFIG_USER_ONLY

if (kvm_enabled()) {

kvm_arm_reset_vcpu(cpu);

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These were missed out from the rest of the half-precision work.

target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------

1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)

unsigned int mos, type, rm, cond, rn, rd;

TCGv_i64 t_true, t_false, t_zero;

DisasCompare64 c;

+ TCGMemOp sz;

mos = extract32(insn, 29, 3);

- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */

+ type = extract32(insn, 22, 2);

rm = extract32(insn, 16, 5);

cond = extract32(insn, 12, 4);

rn = extract32(insn, 5, 5);

rd = extract32(insn, 0, 5);

- if (mos || type > 1) {

+ if (mos) {

+ unallocated_encoding(s);

+ return;

+ }

+

+ switch (type) {

+ case 0:

+ sz = MO_32;

+ break;

+ case 1:

+ sz = MO_64;

+ break;

+ case 3:

+ sz = MO_16;

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ }

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)

return;

}

- /* Zero extend sreg inputs to 64 bits now. */

+ /* Zero extend sreg & hreg inputs to 64 bits now. */

t_true = tcg_temp_new_i64();

t_false = tcg_temp_new_i64();

- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);

- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);

+ read_vec_element(s, t_true, rn, 0, sz);

+ read_vec_element(s, t_false, rm, 0, sz);

a64_test_cc(&c, cond);

t_zero = tcg_const_i64(0);

@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)

tcg_temp_free_i64(t_false);

a64_free_cc(&c);

- /* Note that sregs write back zeros to the high bits,

+ /* Note that sregs & hregs write back zeros to the high bits,

and we've already done the zero-extension. */

write_fp_dreg(s, rd, t_true);

tcg_temp_free_i64(t_true);

2.17.0

Usually the logging of the CPU state produced by -d cpu is sufficient

to diagnose problems, but sometimes you want to see the state of

the floating point registers as well. We don't want to enable that

by default as it adds a lot of extra data to the log; instead,

allow it to be optionally enabled via -d fpu.

Message-id: 20180510130024.31678-1-peter.maydell@linaro.org

include/qemu/log.h | 1 +

accel/tcg/cpu-exec.c | 9 ++++++---

util/log.c | 2 ++

3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/qemu/log.h b/include/qemu/log.h

--- a/include/qemu/log.h

+++ b/include/qemu/log.h

@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)

#define CPU_LOG_PAGE (1 << 14)

/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */

#define CPU_LOG_TB_OP_IND (1 << 16)

+#define CPU_LOG_TB_FPU (1 << 17)

/* Lock output for a series of related logs. Since this is not needed

* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)

if (qemu_loglevel_mask(CPU_LOG_TB_CPU)

&& qemu_log_in_addr_range(itb->pc)) {

qemu_log_lock();

+ int flags = 0;

+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {

+ flags |= CPU_DUMP_FPU;

+ }

#if defined(TARGET_I386)

- log_cpu_state(cpu, CPU_DUMP_CCOP);

-#else

- log_cpu_state(cpu, 0);

+ flags |= CPU_DUMP_CCOP;

#endif

+ log_cpu_state(cpu, flags);

qemu_log_unlock();

#endif /* DEBUG_DISAS */

diff --git a/util/log.c b/util/log.c

index XXXXXXX..XXXXXXX 100644

--- a/util/log.c

+++ b/util/log.c

@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {

"show trace before each executed TB (lots of logs)" },

{ CPU_LOG_TB_CPU, "cpu",

"show CPU registers before entering a TB (lots of logs)" },

+ { CPU_LOG_TB_FPU, "fpu",

+ "include FPU registers in the 'cpu' logging" },

{ CPU_LOG_MMU, "mmu",

"log MMU-related activities" },

{ CPU_LOG_PCALL, "pcall",

2.17.0

In float-to-integer conversion, if the floating point input

converts exactly to the largest or smallest integer that

fits in to the result type, this is not an overflow.

In this situation we were producing the correct result value,

but were incorrectly setting the Invalid flag.

For example for Arm A64, "FCVTAS w0, d0" on an input of

0x41dfffffffc00000 should produce 0x7fffffff and set no flags.

Message-id: 20180510140141.12120-1-peter.maydell@linaro.org

fpu/softfloat.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c

--- a/fpu/softfloat.c

+++ b/fpu/softfloat.c

@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,

r = UINT64_MAX;

}

if (p.sign) {

- if (r < -(uint64_t) min) {

+ if (r <= -(uint64_t) min) {

return -r;

} else {

s->float_exception_flags = orig_flags | float_flag_invalid;

return min;

}

} else {

- if (r < max) {

+ if (r <= max) {

return r;

} else {

s->float_exception_flags = orig_flags | float_flag_invalid;

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

These where missed out from the rest of the half-precision work.

Cc: qemu-stable@nongnu.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20180512003217.9105-9-richard.henderson@linaro.org

[rth: Diagnose lack of FP16 before fp_access_check]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper-a64.h | 2 +

target/arm/helper-a64.c | 10 +++++

target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------

3 files changed, 83 insertions(+), 17 deletions(-)

diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h

--- a/target/arm/helper-a64.h

+++ b/target/arm/helper-a64.h

@@ -XXX,XX +XXX,XX @@

DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)

DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)

DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)

+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)

+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)

DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)

DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper-a64.c

+++ b/target/arm/helper-a64.c

@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)

return flags;

+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)

+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));

+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)

+{

+ return float_rel_to_flags(float16_compare(x, y, fp_status));

+}

+

uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)

return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)

}

}

-static void handle_fp_compare(DisasContext *s, bool is_double,

+static void handle_fp_compare(DisasContext *s, int size,

unsigned int rn, unsigned int rm,

bool cmp_with_zero, bool signal_all_nans)

{

TCGv_i64 tcg_flags = tcg_temp_new_i64();

- TCGv_ptr fpst = get_fpstatus_ptr(false);

+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);

- if (is_double) {

+ if (size == MO_64) {

TCGv_i64 tcg_vn, tcg_vm;

tcg_vn = read_fp_dreg(s, rn);

@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,

tcg_temp_free_i64(tcg_vn);

tcg_temp_free_i64(tcg_vm);

} else {

- TCGv_i32 tcg_vn, tcg_vm;

+ TCGv_i32 tcg_vn = tcg_temp_new_i32();

+ TCGv_i32 tcg_vm = tcg_temp_new_i32();

- tcg_vn = read_fp_sreg(s, rn);

+ read_vec_element_i32(s, tcg_vn, rn, 0, size);

if (cmp_with_zero) {

- tcg_vm = tcg_const_i32(0);

+ tcg_gen_movi_i32(tcg_vm, 0);

} else {

- tcg_vm = read_fp_sreg(s, rm);

+ read_vec_element_i32(s, tcg_vm, rm, 0, size);

}

- if (signal_all_nans) {

- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

- } else {

- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+

+ switch (size) {

+ case MO_32:

+ if (signal_all_nans) {

+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ } else {

+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ break;

+ case MO_16:

+ if (signal_all_nans) {

+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ } else {

+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);

+ }

+ break;

+ default:

+ g_assert_not_reached();

}

+

tcg_temp_free_i32(tcg_vn);

tcg_temp_free_i32(tcg_vm);

}

@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,

static void disas_fp_compare(DisasContext *s, uint32_t insn)

{

unsigned int mos, type, rm, op, rn, opc, op2r;

+ int size;

mos = extract32(insn, 29, 3);

- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */

+ type = extract32(insn, 22, 2);

rm = extract32(insn, 16, 5);

op = extract32(insn, 14, 2);

rn = extract32(insn, 5, 5);

opc = extract32(insn, 3, 2);

op2r = extract32(insn, 0, 3);

- if (mos || op || op2r || type > 1) {

+ if (mos || op || op2r) {

+ unallocated_encoding(s);

+ return;

+ }

+

+ switch (type) {

+ case 0:

+ size = MO_32;

+ break;

+ case 1:

+ size = MO_64;

+ break;

+ case 3:

+ size = MO_16;

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)

return;

}

- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);

+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);

}

/* Floating point conditional compare

@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)

unsigned int mos, type, rm, cond, rn, op, nzcv;

TCGv_i64 tcg_flags;

TCGLabel *label_continue = NULL;

+ int size;

mos = extract32(insn, 29, 3);

- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */

+ type = extract32(insn, 22, 2);

rm = extract32(insn, 16, 5);

cond = extract32(insn, 12, 4);

rn = extract32(insn, 5, 5);

op = extract32(insn, 4, 1);

nzcv = extract32(insn, 0, 4);

- if (mos || type > 1) {

+ if (mos) {

+ unallocated_encoding(s);

+ return;

+ }

+

+ switch (type) {

+ case 0:

+ size = MO_32;

+ break;

+ case 1:

+ size = MO_64;

+ break;

+ case 3:

+ size = MO_16;

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ }

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)

gen_set_label(label_match);

}

- handle_fp_compare(s, type, rn, rm, false, op);

+ handle_fp_compare(s, size, rn, rm, false, op);

if (cond < 0x0e) {

gen_set_label(label_continue);

2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

We missed all of the scalar fp16 binary operations.

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-7-richard.henderson@linaro.org

target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++

1 file changed, 65 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,

tcg_temp_free_i64(tcg_res);

}

+/* Floating-point data-processing (2 source) - half precision */

+static void handle_fp_2src_half(DisasContext *s, int opcode,

+ int rd, int rn, int rm)

+{

+ TCGv_i32 tcg_op1;

+ TCGv_i32 tcg_op2;

+ TCGv_i32 tcg_res;

+ TCGv_ptr fpst;

+

+ tcg_res = tcg_temp_new_i32();

+ fpst = get_fpstatus_ptr(true);

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

+

+ switch (opcode) {

+ case 0x0: /* FMUL */

+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x1: /* FDIV */

+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x2: /* FADD */

+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x3: /* FSUB */

+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x4: /* FMAX */

+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x5: /* FMIN */

+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x6: /* FMAXNM */

+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x7: /* FMINNM */

+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x8: /* FNMUL */

+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);

+ break;

+ default:

+ g_assert_not_reached();

+ }

+

+ write_fp_sreg(s, rd, tcg_res);

+

+ tcg_temp_free_ptr(fpst);

+ tcg_temp_free_i32(tcg_op1);

+ tcg_temp_free_i32(tcg_op2);

+ tcg_temp_free_i32(tcg_res);

+}

+

/* Floating point data-processing (2 source)

* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0

* +---+---+---+-----------+------+---+------+--------+-----+------+------+

@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)

}

handle_fp_2src_double(s, opcode, rd, rn, rm);

break;

+ case 3:

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ unallocated_encoding(s);

+ return;

+ }

+ if (!fp_access_check(s)) {

+ return;

+ }

+ handle_fp_2src_half(s, opcode, rd, rn, rm);

+ break;

default:

unallocated_encoding(s);

}

2.17.0

No sense in emitting code after the exception.

target/arm/translate-a64.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)

default:

/* all other sf/type/rmode combinations are invalid */

unallocated_encoding(s);

- break;

+ return;

}

if (!fp_access_check(s)) {

2.17.0

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-4-richard.henderson@linaro.org

target/arm/helper.h | 6 +++

target/arm/helper.c | 38 ++++++++++++++-

target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------

3 files changed, 122 insertions(+), 18 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)

DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)

DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)

+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)

+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)

+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)

+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)

DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)

DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)

DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)

DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)

DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)

+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)

+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)

DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)

DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)

@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)

#undef VFP_CONV_FIX_A64

/* Conversion to/from f16 can overflow to infinity before/after scaling.

- * Therefore we convert to f64 (which does not round), scale,

- * and then convert f64 to f16 (which may round).

+ * Therefore we convert to f64, scale, and then convert f64 to f16; or

+ * vice versa for conversion to integer.

+ *

+ * For 16- and 32-bit integers, the conversion to f64 never rounds.

+ * For 64-bit integers, any integer that would cause rounding will also

+ * overflow to f16 infinity, so there is no double rounding problem.

*/

static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)

@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)

return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);

+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)

+{

+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);

+}

+

+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)

+{

+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);

+}

+

static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)

if (unlikely(float16_is_any_nan(f))) {

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)

return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);

+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)

+{

+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);

+}

+

/* Set the current fp rounding mode and return the old one.

* The argument is a softfloat float_round_ value.

*/

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

bool itof, int rmode, int scale, int sf, int type)

{

bool is_signed = !(opcode & 1);

- bool is_double = type;

TCGv_ptr tcg_fpstatus;

- TCGv_i32 tcg_shift;

+ TCGv_i32 tcg_shift, tcg_single;

+ TCGv_i64 tcg_double;

- tcg_fpstatus = get_fpstatus_ptr(false);

+ tcg_fpstatus = get_fpstatus_ptr(type == 3);

tcg_shift = tcg_const_i32(64 - scale);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

tcg_int = tcg_extend;

}

- if (is_double) {

- TCGv_i64 tcg_double = tcg_temp_new_i64();

+ switch (type) {

+ case 1: /* float64 */

+ tcg_double = tcg_temp_new_i64();

if (is_signed) {

gen_helper_vfp_sqtod(tcg_double, tcg_int,

tcg_shift, tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

}

write_fp_dreg(s, rd, tcg_double);

tcg_temp_free_i64(tcg_double);

- } else {

- TCGv_i32 tcg_single = tcg_temp_new_i32();

+ break;

+

+ case 0: /* float32 */

+ tcg_single = tcg_temp_new_i32();

if (is_signed) {

gen_helper_vfp_sqtos(tcg_single, tcg_int,

tcg_shift, tcg_fpstatus);

@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,

}

write_fp_sreg(s, rd, tcg_single);

tcg_temp_free_i32(tcg_single);

+ break;

+

+ case 3: /* float16 */

+ tcg_single = tcg_temp_new_i32();

+ if (is_signed) {

+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,

+ tcg_shift, tcg_fpstatus);

+ } else {

+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,

+ tcg_shift, tcg_fpstatus);

+ }

+ write_fp_sreg(s, rd, tcg_single);

+ tcg_temp_free_i32(tcg_single);

+ break;

+

+ default:

+ g_assert_not_reached();

}

} else {

TCGv_i64 tcg_int = cpu_reg(s, rd);