The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:

Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515

for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:

tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)

* Fix coverity nit in int_to_float code

* Don't set Invalid for float-to-int(MAXINT)

* Fix fp_status_f16 tininess before rounding

* Add various missing insns from the v8.2-FP16 extension

* Fix sqrt_f16 exception raising

* sdcard: Correct CRC16 offset in sd_function_switch()

* tcg: Optionally log FPU state in TCG -d cpu logging

Alex Bennée (5):

fpu/softfloat: int_to_float ensure r fully initialised

target/arm: Implement FCMP for fp16

target/arm: Implement FCSEL for fp16

target/arm: Implement FMOV (immediate) for fp16

target/arm: Fix sqrt_f16 exception raising

Peter Maydell (3):

fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)

target/arm: Fix fp_status_f16 tininess before rounding

tcg: Optionally log FPU state in TCG -d cpu logging

Philippe Mathieu-Daudé (1):

sdcard: Correct CRC16 offset in sd_function_switch()

Richard Henderson (7):

target/arm: Implement FMOV (general) for fp16

target/arm: Early exit after unallocated_encoding in disas_fp_int_conv

target/arm: Implement FCVT (scalar, integer) for fp16

target/arm: Implement FCVT (scalar, fixed-point) for fp16

target/arm: Introduce and use read_fp_hreg

target/arm: Implement FP data-processing (2 source) for fp16

target/arm: Implement FP data-processing (3 source) for fp16

In commit d81ce0ef2c4f105 we added an extra float_status field

fp_status_fp16 for Arm, but forgot to initialize it correctly

by setting it to float_tininess_before_rounding. This currently

will only cause problems for the new V8_FP16 feature, since the

float-to-float conversion code doesn't use it yet. The effect

would be that we failed to set the Underflow IEEE exception flag

in all the cases where we should.

Add the missing initialization.

Fixes: d81ce0ef2c4f105

Cc: qemu-stable@nongnu.org

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20180512004311.9299-16-richard.henderson@linaro.org

---

target/arm/cpu.c | 2 ++

1 file changed, 2 insertions(+)

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)

&env->vfp.fp_status);

set_float_detect_tininess(float_tininess_before_rounding,

&env->vfp.standard_fp_status);

+ set_float_detect_tininess(float_tininess_before_rounding,

+ &env->vfp.fp_status_f16);

#ifndef CONFIG_USER_ONLY

if (kvm_enabled()) {

kvm_arm_reset_vcpu(cpu);

2.17.0

In float-to-integer conversion, if the floating point input

converts exactly to the largest or smallest integer that

fits in to the result type, this is not an overflow.

In this situation we were producing the correct result value,

but were incorrectly setting the Invalid flag.

For example for Arm A64, "FCVTAS w0, d0" on an input of

0x41dfffffffc00000 should produce 0x7fffffff and set no flags.

Fix the boundary case to take the right half of the if()

statements.

This fixes a regression from 2.11 introduced by the softfloat

refactoring.

Message-id: 20180510140141.12120-1-peter.maydell@linaro.org

fpu/softfloat.c | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c

--- a/fpu/softfloat.c

+++ b/fpu/softfloat.c

@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,

r = UINT64_MAX;

}

if (p.sign) {

- if (r < -(uint64_t) min) {

+ if (r <= -(uint64_t) min) {

return -r;

} else {

s->float_exception_flags = orig_flags | float_flag_invalid;

return min;

}

} else {

- if (r < max) {

+ if (r <= max) {

return r;

} else {

s->float_exception_flags = orig_flags | float_flag_invalid;

2.17.0

Usually the logging of the CPU state produced by -d cpu is sufficient

to diagnose problems, but sometimes you want to see the state of

the floating point registers as well. We don't want to enable that

by default as it adds a lot of extra data to the log; instead,

allow it to be optionally enabled via -d fpu.

Message-id: 20180510130024.31678-1-peter.maydell@linaro.org

include/qemu/log.h | 1 +

accel/tcg/cpu-exec.c | 9 ++++++---

util/log.c | 2 ++

3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/include/qemu/log.h b/include/qemu/log.h

--- a/include/qemu/log.h

+++ b/include/qemu/log.h

@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)

#define CPU_LOG_PAGE (1 << 14)

/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */

#define CPU_LOG_TB_OP_IND (1 << 16)

+#define CPU_LOG_TB_FPU (1 << 17)

/* Lock output for a series of related logs. Since this is not needed

* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c

index XXXXXXX..XXXXXXX 100644

--- a/accel/tcg/cpu-exec.c

+++ b/accel/tcg/cpu-exec.c

@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)

if (qemu_loglevel_mask(CPU_LOG_TB_CPU)

&& qemu_log_in_addr_range(itb->pc)) {

qemu_log_lock();

+ int flags = 0;

+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {

+ flags |= CPU_DUMP_FPU;

+ }

#if defined(TARGET_I386)

- log_cpu_state(cpu, CPU_DUMP_CCOP);

-#else

- log_cpu_state(cpu, 0);

+ flags |= CPU_DUMP_CCOP;

#endif

+ log_cpu_state(cpu, flags);

qemu_log_unlock();

}

#endif /* DEBUG_DISAS */

diff --git a/util/log.c b/util/log.c

index XXXXXXX..XXXXXXX 100644

--- a/util/log.c

+++ b/util/log.c

@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {

"show trace before each executed TB (lots of logs)" },

{ CPU_LOG_TB_CPU, "cpu",

"show CPU registers before entering a TB (lots of logs)" },

+ { CPU_LOG_TB_FPU, "fpu",

+ "include FPU registers in the 'cpu' logging" },

{ CPU_LOG_MMU, "mmu",

"log MMU-related activities" },

{ CPU_LOG_PCALL, "pcall",

2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

We missed all of the scalar fp16 fma operations.

target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++

1 file changed, 48 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,

tcg_temp_free_i64(tcg_res);

+/* Floating-point data-processing (3 source) - half precision */

+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,

+ int rd, int rn, int rm, int ra)

+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;

+ TCGv_i32 tcg_res = tcg_temp_new_i32();

+ TCGv_ptr fpst = get_fpstatus_ptr(true);

+

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

+ tcg_op3 = read_fp_hreg(s, ra);

+

+ /* These are fused multiply-add, and must be done as one

+ * floating point operation with no rounding between the

+ * multiplication and addition steps.

+ * NB that doing the negations here as separate steps is

+ * correct : an input NaN should come out with its sign bit

+ * flipped if it is a negated-input.

+ */

+ if (o1 == true) {

+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);

+ }

+

+ if (o0 != o1) {

+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);

+ }

+

+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);

+

+ write_fp_sreg(s, rd, tcg_res);

+

+ tcg_temp_free_ptr(fpst);

+ tcg_temp_free_i32(tcg_op1);

+ tcg_temp_free_i32(tcg_op2);

+ tcg_temp_free_i32(tcg_op3);

+ tcg_temp_free_i32(tcg_res);

/* Floating point data-processing (3 source)

* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0

* +---+---+---+-----------+------+----+------+----+------+------+------+

@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)

}

handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);

break;

+ case 3:

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ unallocated_encoding(s);

+ return;

+ }

+ if (!fp_access_check(s)) {

+ return;

+ }

+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);

+ break;

default:

unallocated_encoding(s);

}

2.17.0

No sense in emitting code after the exception.

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-3-richard.henderson@linaro.org

target/arm/translate-a64.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)

default:

/* all other sf/type/rmode combinations are invalid */

unallocated_encoding(s);

- break;

+ return;

if (!fp_access_check(s)) {

2.17.0

Adding the fp16 moves to/from general registers.

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-2-richard.henderson@linaro.org

target/arm/translate-a64.c | 21 +++++++++++++++++++++

1 file changed, 21 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)

tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));

clear_vec_high(s, true, rd);

break;

+ case 3:

+ /* 16 bit */

+ tmp = tcg_temp_new_i64();

+ tcg_gen_ext16u_i64(tmp, tcg_rn);

+ write_fp_dreg(s, rd, tmp);

+ tcg_temp_free_i64(tmp);

+ break;

+ default:

+ g_assert_not_reached();

}

} else {

TCGv_i64 tcg_rd = cpu_reg(s, rd);

@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)

/* 64 bits from top half */

tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));

break;

+ case 3:

+ /* 16 bit */

+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));

+ break;

+ default:

+ g_assert_not_reached();

}

2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

Cc: qemu-stable@nongnu.org

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-5-richard.henderson@linaro.org

target/arm/translate-a64.c | 17 +++++++++++++++--

1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)

bool sf = extract32(insn, 31, 1);

bool itof;

- if (sbit || (type > 1)

- || (!sf && scale < 32)) {

+ if (sbit || (!sf && scale < 32)) {

+ unallocated_encoding(s);

+ return;

+ }

+

+ switch (type) {

+ case 0: /* float32 */

+ case 1: /* float64 */

+ break;

+ case 3: /* float16 */

+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {

+ break;

+ }

+ /* fallthru */

+ default:

unallocated_encoding(s);

return;

}

2.17.0

Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":

The block length is predefined to 512 bits

and "4.10.2 SD Status":

The SD Status contains status bits that are related to the SD Memory Card

proprietary features and may be used for future application-specific usage.

The size of the SD Status is one data block of 512 bit. The content of this

register is transmitted to the Host over the DAT bus along with a 16-bit CRC.

Thus the 16-bit CRC goes at offset 64.

Message-id: 20180509060104.4458-3-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/sd/sd.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/sd/sd.c b/hw/sd/sd.c

--- a/hw/sd/sd.c

+++ b/hw/sd/sd.c

@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)

sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);

}

memset(&sd->data[17], 0, 47);

- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));

+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));

2.17.0

From: Alex Bennée <alex.bennee@linaro.org>

Reported by Coverity (CID1390635). We ensure this for uint_to_float

later on so we might as well mirror that.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

fpu/softfloat.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c

--- a/fpu/softfloat.c

+++ b/fpu/softfloat.c

@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)

static FloatParts int_to_float(int64_t a, float_status *status)

{

- FloatParts r;

+ FloatParts r = {};

if (a == 0) {

r.cls = float_class_zero;

r.sign = false;

2.17.0

From: Richard Henderson <richard.henderson@linaro.org>

We missed all of the scalar fp16 binary operations.

Cc: qemu-stable@nongnu.org

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Tested-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20180512003217.9105-7-richard.henderson@linaro.org

target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++

1 file changed, 65 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,

tcg_temp_free_i64(tcg_res);

+/* Floating-point data-processing (2 source) - half precision */

+static void handle_fp_2src_half(DisasContext *s, int opcode,

+ int rd, int rn, int rm)

+{

+ TCGv_i32 tcg_op1;

+ TCGv_i32 tcg_op2;

+ TCGv_i32 tcg_res;

+ TCGv_ptr fpst;

+

+ tcg_res = tcg_temp_new_i32();

+ fpst = get_fpstatus_ptr(true);

+ tcg_op1 = read_fp_hreg(s, rn);

+ tcg_op2 = read_fp_hreg(s, rm);

+

+ switch (opcode) {

+ case 0x0: /* FMUL */

+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x1: /* FDIV */

+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x2: /* FADD */

+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x3: /* FSUB */

+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x4: /* FMAX */

+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;

+ case 0x5: /* FMIN */

+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);

+ break;